2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
4 * Copyright (C) 2002 - 2011 Paul Mundt
5 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
7 * based off of the old drivers/char/sh-sci.c by:
9 * Copyright (C) 1999, 2000 Niibe Yutaka
10 * Copyright (C) 2000 Sugioka Toshinobu
11 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
12 * Modified to support SecureEdge. David McCullough (2002)
13 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
14 * Removed SH7300 support (Jul 2007).
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
20 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
26 #include <linux/clk.h>
27 #include <linux/console.h>
28 #include <linux/ctype.h>
29 #include <linux/cpufreq.h>
30 #include <linux/delay.h>
31 #include <linux/dmaengine.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/err.h>
34 #include <linux/errno.h>
35 #include <linux/init.h>
36 #include <linux/interrupt.h>
37 #include <linux/ioport.h>
38 #include <linux/major.h>
39 #include <linux/module.h>
41 #include <linux/notifier.h>
42 #include <linux/platform_device.h>
43 #include <linux/pm_runtime.h>
44 #include <linux/scatterlist.h>
45 #include <linux/serial.h>
46 #include <linux/serial_sci.h>
47 #include <linux/sh_dma.h>
48 #include <linux/slab.h>
49 #include <linux/string.h>
50 #include <linux/sysrq.h>
51 #include <linux/timer.h>
52 #include <linux/tty.h>
53 #include <linux/tty_flip.h>
56 #include <asm/sh_bios.h>
62 struct uart_port port;
64 /* Platform configuration */
65 struct plat_sci_port *cfg;
67 unsigned int error_mask;
68 unsigned int sampling_rate;
72 struct timer_list break_timer;
80 int irqs[SCIx_NR_IRQS];
81 char *irqstr[SCIx_NR_IRQS];
83 struct dma_chan *chan_tx;
84 struct dma_chan *chan_rx;
86 #ifdef CONFIG_SERIAL_SH_SCI_DMA
87 struct dma_async_tx_descriptor *desc_tx;
88 struct dma_async_tx_descriptor *desc_rx[2];
89 dma_cookie_t cookie_tx;
90 dma_cookie_t cookie_rx[2];
91 dma_cookie_t active_rx;
92 struct scatterlist sg_tx;
93 unsigned int sg_len_tx;
94 struct scatterlist sg_rx[2];
96 struct sh_dmae_slave param_tx;
97 struct sh_dmae_slave param_rx;
98 struct work_struct work_tx;
99 struct work_struct work_rx;
100 struct timer_list rx_timer;
101 unsigned int rx_timeout;
104 struct notifier_block freq_transition;
107 /* Function prototypes */
108 static void sci_start_tx(struct uart_port *port);
109 static void sci_stop_tx(struct uart_port *port);
110 static void sci_start_rx(struct uart_port *port);
112 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
114 static struct sci_port sci_ports[SCI_NPORTS];
115 static struct uart_driver sci_uart_driver;
117 static inline struct sci_port *
118 to_sci_port(struct uart_port *uart)
120 return container_of(uart, struct sci_port, port);
123 struct plat_sci_reg {
127 /* Helper for invalidating specific entries of an inherited map. */
128 #define sci_reg_invalid { .offset = 0, .size = 0 }
130 static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
131 [SCIx_PROBE_REGTYPE] = {
132 [0 ... SCIx_NR_REGS - 1] = sci_reg_invalid,
136 * Common SCI definitions, dependent on the port's regshift
139 [SCIx_SCI_REGTYPE] = {
140 [SCSMR] = { 0x00, 8 },
141 [SCBRR] = { 0x01, 8 },
142 [SCSCR] = { 0x02, 8 },
143 [SCxTDR] = { 0x03, 8 },
144 [SCxSR] = { 0x04, 8 },
145 [SCxRDR] = { 0x05, 8 },
146 [SCFCR] = sci_reg_invalid,
147 [SCFDR] = sci_reg_invalid,
148 [SCTFDR] = sci_reg_invalid,
149 [SCRFDR] = sci_reg_invalid,
150 [SCSPTR] = sci_reg_invalid,
151 [SCLSR] = sci_reg_invalid,
152 [HSSRR] = sci_reg_invalid,
156 * Common definitions for legacy IrDA ports, dependent on
159 [SCIx_IRDA_REGTYPE] = {
160 [SCSMR] = { 0x00, 8 },
161 [SCBRR] = { 0x01, 8 },
162 [SCSCR] = { 0x02, 8 },
163 [SCxTDR] = { 0x03, 8 },
164 [SCxSR] = { 0x04, 8 },
165 [SCxRDR] = { 0x05, 8 },
166 [SCFCR] = { 0x06, 8 },
167 [SCFDR] = { 0x07, 16 },
168 [SCTFDR] = sci_reg_invalid,
169 [SCRFDR] = sci_reg_invalid,
170 [SCSPTR] = sci_reg_invalid,
171 [SCLSR] = sci_reg_invalid,
172 [HSSRR] = sci_reg_invalid,
176 * Common SCIFA definitions.
178 [SCIx_SCIFA_REGTYPE] = {
179 [SCSMR] = { 0x00, 16 },
180 [SCBRR] = { 0x04, 8 },
181 [SCSCR] = { 0x08, 16 },
182 [SCxTDR] = { 0x20, 8 },
183 [SCxSR] = { 0x14, 16 },
184 [SCxRDR] = { 0x24, 8 },
185 [SCFCR] = { 0x18, 16 },
186 [SCFDR] = { 0x1c, 16 },
187 [SCTFDR] = sci_reg_invalid,
188 [SCRFDR] = sci_reg_invalid,
189 [SCSPTR] = sci_reg_invalid,
190 [SCLSR] = sci_reg_invalid,
191 [HSSRR] = sci_reg_invalid,
195 * Common SCIFB definitions.
197 [SCIx_SCIFB_REGTYPE] = {
198 [SCSMR] = { 0x00, 16 },
199 [SCBRR] = { 0x04, 8 },
200 [SCSCR] = { 0x08, 16 },
201 [SCxTDR] = { 0x40, 8 },
202 [SCxSR] = { 0x14, 16 },
203 [SCxRDR] = { 0x60, 8 },
204 [SCFCR] = { 0x18, 16 },
205 [SCFDR] = sci_reg_invalid,
206 [SCTFDR] = { 0x38, 16 },
207 [SCRFDR] = { 0x3c, 16 },
208 [SCSPTR] = sci_reg_invalid,
209 [SCLSR] = sci_reg_invalid,
210 [HSSRR] = sci_reg_invalid,
214 * Common SH-2(A) SCIF definitions for ports with FIFO data
217 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
218 [SCSMR] = { 0x00, 16 },
219 [SCBRR] = { 0x04, 8 },
220 [SCSCR] = { 0x08, 16 },
221 [SCxTDR] = { 0x0c, 8 },
222 [SCxSR] = { 0x10, 16 },
223 [SCxRDR] = { 0x14, 8 },
224 [SCFCR] = { 0x18, 16 },
225 [SCFDR] = { 0x1c, 16 },
226 [SCTFDR] = sci_reg_invalid,
227 [SCRFDR] = sci_reg_invalid,
228 [SCSPTR] = { 0x20, 16 },
229 [SCLSR] = { 0x24, 16 },
230 [HSSRR] = sci_reg_invalid,
234 * Common SH-3 SCIF definitions.
236 [SCIx_SH3_SCIF_REGTYPE] = {
237 [SCSMR] = { 0x00, 8 },
238 [SCBRR] = { 0x02, 8 },
239 [SCSCR] = { 0x04, 8 },
240 [SCxTDR] = { 0x06, 8 },
241 [SCxSR] = { 0x08, 16 },
242 [SCxRDR] = { 0x0a, 8 },
243 [SCFCR] = { 0x0c, 8 },
244 [SCFDR] = { 0x0e, 16 },
245 [SCTFDR] = sci_reg_invalid,
246 [SCRFDR] = sci_reg_invalid,
247 [SCSPTR] = sci_reg_invalid,
248 [SCLSR] = sci_reg_invalid,
249 [HSSRR] = sci_reg_invalid,
253 * Common SH-4(A) SCIF(B) definitions.
255 [SCIx_SH4_SCIF_REGTYPE] = {
256 [SCSMR] = { 0x00, 16 },
257 [SCBRR] = { 0x04, 8 },
258 [SCSCR] = { 0x08, 16 },
259 [SCxTDR] = { 0x0c, 8 },
260 [SCxSR] = { 0x10, 16 },
261 [SCxRDR] = { 0x14, 8 },
262 [SCFCR] = { 0x18, 16 },
263 [SCFDR] = { 0x1c, 16 },
264 [SCTFDR] = sci_reg_invalid,
265 [SCRFDR] = sci_reg_invalid,
266 [SCSPTR] = { 0x20, 16 },
267 [SCLSR] = { 0x24, 16 },
268 [HSSRR] = sci_reg_invalid,
272 * Common HSCIF definitions.
274 [SCIx_HSCIF_REGTYPE] = {
275 [SCSMR] = { 0x00, 16 },
276 [SCBRR] = { 0x04, 8 },
277 [SCSCR] = { 0x08, 16 },
278 [SCxTDR] = { 0x0c, 8 },
279 [SCxSR] = { 0x10, 16 },
280 [SCxRDR] = { 0x14, 8 },
281 [SCFCR] = { 0x18, 16 },
282 [SCFDR] = { 0x1c, 16 },
283 [SCTFDR] = sci_reg_invalid,
284 [SCRFDR] = sci_reg_invalid,
285 [SCSPTR] = { 0x20, 16 },
286 [SCLSR] = { 0x24, 16 },
287 [HSSRR] = { 0x40, 16 },
291 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
294 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
295 [SCSMR] = { 0x00, 16 },
296 [SCBRR] = { 0x04, 8 },
297 [SCSCR] = { 0x08, 16 },
298 [SCxTDR] = { 0x0c, 8 },
299 [SCxSR] = { 0x10, 16 },
300 [SCxRDR] = { 0x14, 8 },
301 [SCFCR] = { 0x18, 16 },
302 [SCFDR] = { 0x1c, 16 },
303 [SCTFDR] = sci_reg_invalid,
304 [SCRFDR] = sci_reg_invalid,
305 [SCSPTR] = sci_reg_invalid,
306 [SCLSR] = { 0x24, 16 },
307 [HSSRR] = sci_reg_invalid,
311 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
314 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
315 [SCSMR] = { 0x00, 16 },
316 [SCBRR] = { 0x04, 8 },
317 [SCSCR] = { 0x08, 16 },
318 [SCxTDR] = { 0x0c, 8 },
319 [SCxSR] = { 0x10, 16 },
320 [SCxRDR] = { 0x14, 8 },
321 [SCFCR] = { 0x18, 16 },
322 [SCFDR] = { 0x1c, 16 },
323 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
324 [SCRFDR] = { 0x20, 16 },
325 [SCSPTR] = { 0x24, 16 },
326 [SCLSR] = { 0x28, 16 },
327 [HSSRR] = sci_reg_invalid,
331 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
334 [SCIx_SH7705_SCIF_REGTYPE] = {
335 [SCSMR] = { 0x00, 16 },
336 [SCBRR] = { 0x04, 8 },
337 [SCSCR] = { 0x08, 16 },
338 [SCxTDR] = { 0x20, 8 },
339 [SCxSR] = { 0x14, 16 },
340 [SCxRDR] = { 0x24, 8 },
341 [SCFCR] = { 0x18, 16 },
342 [SCFDR] = { 0x1c, 16 },
343 [SCTFDR] = sci_reg_invalid,
344 [SCRFDR] = sci_reg_invalid,
345 [SCSPTR] = sci_reg_invalid,
346 [SCLSR] = sci_reg_invalid,
347 [HSSRR] = sci_reg_invalid,
351 #define sci_getreg(up, offset) (sci_regmap[to_sci_port(up)->cfg->regtype] + offset)
354 * The "offset" here is rather misleading, in that it refers to an enum
355 * value relative to the port mapping rather than the fixed offset
356 * itself, which needs to be manually retrieved from the platform's
357 * register map for the given port.
359 static unsigned int sci_serial_in(struct uart_port *p, int offset)
361 struct plat_sci_reg *reg = sci_getreg(p, offset);
364 return ioread8(p->membase + (reg->offset << p->regshift));
365 else if (reg->size == 16)
366 return ioread16(p->membase + (reg->offset << p->regshift));
368 WARN(1, "Invalid register access\n");
373 static void sci_serial_out(struct uart_port *p, int offset, int value)
375 struct plat_sci_reg *reg = sci_getreg(p, offset);
378 iowrite8(value, p->membase + (reg->offset << p->regshift));
379 else if (reg->size == 16)
380 iowrite16(value, p->membase + (reg->offset << p->regshift));
382 WARN(1, "Invalid register access\n");
385 static int sci_probe_regmap(struct plat_sci_port *cfg)
389 cfg->regtype = SCIx_SCI_REGTYPE;
392 cfg->regtype = SCIx_IRDA_REGTYPE;
395 cfg->regtype = SCIx_SCIFA_REGTYPE;
398 cfg->regtype = SCIx_SCIFB_REGTYPE;
402 * The SH-4 is a bit of a misnomer here, although that's
403 * where this particular port layout originated. This
404 * configuration (or some slight variation thereof)
405 * remains the dominant model for all SCIFs.
407 cfg->regtype = SCIx_SH4_SCIF_REGTYPE;
410 cfg->regtype = SCIx_HSCIF_REGTYPE;
413 printk(KERN_ERR "Can't probe register map for given port\n");
420 static void sci_port_enable(struct sci_port *sci_port)
422 if (!sci_port->port.dev)
425 pm_runtime_get_sync(sci_port->port.dev);
427 clk_prepare_enable(sci_port->iclk);
428 sci_port->port.uartclk = clk_get_rate(sci_port->iclk);
429 clk_prepare_enable(sci_port->fclk);
432 static void sci_port_disable(struct sci_port *sci_port)
434 if (!sci_port->port.dev)
437 /* Cancel the break timer to ensure that the timer handler will not try
438 * to access the hardware with clocks and power disabled. Reset the
439 * break flag to make the break debouncing state machine ready for the
442 del_timer_sync(&sci_port->break_timer);
443 sci_port->break_flag = 0;
445 clk_disable_unprepare(sci_port->fclk);
446 clk_disable_unprepare(sci_port->iclk);
448 pm_runtime_put_sync(sci_port->port.dev);
451 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
453 #ifdef CONFIG_CONSOLE_POLL
454 static int sci_poll_get_char(struct uart_port *port)
456 unsigned short status;
460 status = serial_port_in(port, SCxSR);
461 if (status & SCxSR_ERRORS(port)) {
462 serial_port_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
468 if (!(status & SCxSR_RDxF(port)))
471 c = serial_port_in(port, SCxRDR);
474 serial_port_in(port, SCxSR);
475 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
481 static void sci_poll_put_char(struct uart_port *port, unsigned char c)
483 unsigned short status;
486 status = serial_port_in(port, SCxSR);
487 } while (!(status & SCxSR_TDxE(port)));
489 serial_port_out(port, SCxTDR, c);
490 serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
492 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
494 static void sci_init_pins(struct uart_port *port, unsigned int cflag)
496 struct sci_port *s = to_sci_port(port);
497 struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
500 * Use port-specific handler if provided.
502 if (s->cfg->ops && s->cfg->ops->init_pins) {
503 s->cfg->ops->init_pins(port, cflag);
508 * For the generic path SCSPTR is necessary. Bail out if that's
514 if ((s->cfg->capabilities & SCIx_HAVE_RTSCTS) &&
515 ((!(cflag & CRTSCTS)))) {
516 unsigned short status;
518 status = serial_port_in(port, SCSPTR);
519 status &= ~SCSPTR_CTSIO;
520 status |= SCSPTR_RTSIO;
521 serial_port_out(port, SCSPTR, status); /* Set RTS = 1 */
525 static int sci_txfill(struct uart_port *port)
527 struct plat_sci_reg *reg;
529 reg = sci_getreg(port, SCTFDR);
531 return serial_port_in(port, SCTFDR) & ((port->fifosize << 1) - 1);
533 reg = sci_getreg(port, SCFDR);
535 return serial_port_in(port, SCFDR) >> 8;
537 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
540 static int sci_txroom(struct uart_port *port)
542 return port->fifosize - sci_txfill(port);
545 static int sci_rxfill(struct uart_port *port)
547 struct plat_sci_reg *reg;
549 reg = sci_getreg(port, SCRFDR);
551 return serial_port_in(port, SCRFDR) & ((port->fifosize << 1) - 1);
553 reg = sci_getreg(port, SCFDR);
555 return serial_port_in(port, SCFDR) & ((port->fifosize << 1) - 1);
557 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
561 * SCI helper for checking the state of the muxed port/RXD pins.
563 static inline int sci_rxd_in(struct uart_port *port)
565 struct sci_port *s = to_sci_port(port);
567 if (s->cfg->port_reg <= 0)
570 /* Cast for ARM damage */
571 return !!__raw_readb((void __iomem *)(uintptr_t)s->cfg->port_reg);
574 /* ********************************************************************** *
575 * the interrupt related routines *
576 * ********************************************************************** */
578 static void sci_transmit_chars(struct uart_port *port)
580 struct circ_buf *xmit = &port->state->xmit;
581 unsigned int stopped = uart_tx_stopped(port);
582 unsigned short status;
586 status = serial_port_in(port, SCxSR);
587 if (!(status & SCxSR_TDxE(port))) {
588 ctrl = serial_port_in(port, SCSCR);
589 if (uart_circ_empty(xmit))
593 serial_port_out(port, SCSCR, ctrl);
597 count = sci_txroom(port);
605 } else if (!uart_circ_empty(xmit) && !stopped) {
606 c = xmit->buf[xmit->tail];
607 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
612 serial_port_out(port, SCxTDR, c);
615 } while (--count > 0);
617 serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
619 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
620 uart_write_wakeup(port);
621 if (uart_circ_empty(xmit)) {
624 ctrl = serial_port_in(port, SCSCR);
626 if (port->type != PORT_SCI) {
627 serial_port_in(port, SCxSR); /* Dummy read */
628 serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
632 serial_port_out(port, SCSCR, ctrl);
636 /* On SH3, SCIF may read end-of-break as a space->mark char */
637 #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
639 static void sci_receive_chars(struct uart_port *port)
641 struct sci_port *sci_port = to_sci_port(port);
642 struct tty_port *tport = &port->state->port;
643 int i, count, copied = 0;
644 unsigned short status;
647 status = serial_port_in(port, SCxSR);
648 if (!(status & SCxSR_RDxF(port)))
652 /* Don't copy more bytes than there is room for in the buffer */
653 count = tty_buffer_request_room(tport, sci_rxfill(port));
655 /* If for any reason we can't copy more data, we're done! */
659 if (port->type == PORT_SCI) {
660 char c = serial_port_in(port, SCxRDR);
661 if (uart_handle_sysrq_char(port, c) ||
662 sci_port->break_flag)
665 tty_insert_flip_char(tport, c, TTY_NORMAL);
667 for (i = 0; i < count; i++) {
668 char c = serial_port_in(port, SCxRDR);
670 status = serial_port_in(port, SCxSR);
671 #if defined(CONFIG_CPU_SH3)
672 /* Skip "chars" during break */
673 if (sci_port->break_flag) {
675 (status & SCxSR_FER(port))) {
680 /* Nonzero => end-of-break */
681 dev_dbg(port->dev, "debounce<%02x>\n", c);
682 sci_port->break_flag = 0;
689 #endif /* CONFIG_CPU_SH3 */
690 if (uart_handle_sysrq_char(port, c)) {
695 /* Store data and status */
696 if (status & SCxSR_FER(port)) {
698 port->icount.frame++;
699 dev_notice(port->dev, "frame error\n");
700 } else if (status & SCxSR_PER(port)) {
702 port->icount.parity++;
703 dev_notice(port->dev, "parity error\n");
707 tty_insert_flip_char(tport, c, flag);
711 serial_port_in(port, SCxSR); /* dummy read */
712 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
715 port->icount.rx += count;
719 /* Tell the rest of the system the news. New characters! */
720 tty_flip_buffer_push(tport);
722 serial_port_in(port, SCxSR); /* dummy read */
723 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
727 #define SCI_BREAK_JIFFIES (HZ/20)
730 * The sci generates interrupts during the break,
731 * 1 per millisecond or so during the break period, for 9600 baud.
732 * So dont bother disabling interrupts.
733 * But dont want more than 1 break event.
734 * Use a kernel timer to periodically poll the rx line until
735 * the break is finished.
737 static inline void sci_schedule_break_timer(struct sci_port *port)
739 mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES);
742 /* Ensure that two consecutive samples find the break over. */
743 static void sci_break_timer(unsigned long data)
745 struct sci_port *port = (struct sci_port *)data;
747 if (sci_rxd_in(&port->port) == 0) {
748 port->break_flag = 1;
749 sci_schedule_break_timer(port);
750 } else if (port->break_flag == 1) {
752 port->break_flag = 2;
753 sci_schedule_break_timer(port);
755 port->break_flag = 0;
758 static int sci_handle_errors(struct uart_port *port)
761 unsigned short status = serial_port_in(port, SCxSR);
762 struct tty_port *tport = &port->state->port;
763 struct sci_port *s = to_sci_port(port);
765 /* Handle overruns */
766 if (status & (1 << s->overrun_bit)) {
767 port->icount.overrun++;
770 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
773 dev_notice(port->dev, "overrun error");
776 if (status & SCxSR_FER(port)) {
777 if (sci_rxd_in(port) == 0) {
778 /* Notify of BREAK */
779 struct sci_port *sci_port = to_sci_port(port);
781 if (!sci_port->break_flag) {
784 sci_port->break_flag = 1;
785 sci_schedule_break_timer(sci_port);
787 /* Do sysrq handling. */
788 if (uart_handle_break(port))
791 dev_dbg(port->dev, "BREAK detected\n");
793 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
799 port->icount.frame++;
801 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
804 dev_notice(port->dev, "frame error\n");
808 if (status & SCxSR_PER(port)) {
810 port->icount.parity++;
812 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
815 dev_notice(port->dev, "parity error");
819 tty_flip_buffer_push(tport);
824 static int sci_handle_fifo_overrun(struct uart_port *port)
826 struct tty_port *tport = &port->state->port;
827 struct sci_port *s = to_sci_port(port);
828 struct plat_sci_reg *reg;
831 reg = sci_getreg(port, SCLSR);
835 if ((serial_port_in(port, SCLSR) & (1 << s->overrun_bit))) {
836 serial_port_out(port, SCLSR, 0);
838 port->icount.overrun++;
840 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
841 tty_flip_buffer_push(tport);
843 dev_notice(port->dev, "overrun error\n");
850 static int sci_handle_breaks(struct uart_port *port)
853 unsigned short status = serial_port_in(port, SCxSR);
854 struct tty_port *tport = &port->state->port;
855 struct sci_port *s = to_sci_port(port);
857 if (uart_handle_break(port))
860 if (!s->break_flag && status & SCxSR_BRK(port)) {
861 #if defined(CONFIG_CPU_SH3)
868 /* Notify of BREAK */
869 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
872 dev_dbg(port->dev, "BREAK detected\n");
876 tty_flip_buffer_push(tport);
878 copied += sci_handle_fifo_overrun(port);
883 static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
885 #ifdef CONFIG_SERIAL_SH_SCI_DMA
886 struct uart_port *port = ptr;
887 struct sci_port *s = to_sci_port(port);
890 u16 scr = serial_port_in(port, SCSCR);
891 u16 ssr = serial_port_in(port, SCxSR);
893 /* Disable future Rx interrupts */
894 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
895 disable_irq_nosync(irq);
900 serial_port_out(port, SCSCR, scr);
901 /* Clear current interrupt */
902 serial_port_out(port, SCxSR, ssr & ~(1 | SCxSR_RDxF(port)));
903 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
904 jiffies, s->rx_timeout);
905 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
911 /* I think sci_receive_chars has to be called irrespective
912 * of whether the I_IXOFF is set, otherwise, how is the interrupt
915 sci_receive_chars(ptr);
920 static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
922 struct uart_port *port = ptr;
925 spin_lock_irqsave(&port->lock, flags);
926 sci_transmit_chars(port);
927 spin_unlock_irqrestore(&port->lock, flags);
932 static irqreturn_t sci_er_interrupt(int irq, void *ptr)
934 struct uart_port *port = ptr;
937 if (port->type == PORT_SCI) {
938 if (sci_handle_errors(port)) {
939 /* discard character in rx buffer */
940 serial_port_in(port, SCxSR);
941 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
944 sci_handle_fifo_overrun(port);
945 sci_rx_interrupt(irq, ptr);
948 serial_port_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
950 /* Kick the transmission */
951 sci_tx_interrupt(irq, ptr);
956 static irqreturn_t sci_br_interrupt(int irq, void *ptr)
958 struct uart_port *port = ptr;
961 sci_handle_breaks(port);
962 serial_port_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
967 static inline unsigned long port_rx_irq_mask(struct uart_port *port)
970 * Not all ports (such as SCIFA) will support REIE. Rather than
971 * special-casing the port type, we check the port initialization
972 * IRQ enable mask to see whether the IRQ is desired at all. If
973 * it's unset, it's logically inferred that there's no point in
976 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
979 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
981 unsigned short ssr_status, scr_status, err_enabled;
982 struct uart_port *port = ptr;
983 struct sci_port *s = to_sci_port(port);
984 irqreturn_t ret = IRQ_NONE;
986 ssr_status = serial_port_in(port, SCxSR);
987 scr_status = serial_port_in(port, SCSCR);
988 err_enabled = scr_status & port_rx_irq_mask(port);
991 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
993 ret = sci_tx_interrupt(irq, ptr);
996 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
999 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
1000 (scr_status & SCSCR_RIE))
1001 ret = sci_rx_interrupt(irq, ptr);
1003 /* Error Interrupt */
1004 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
1005 ret = sci_er_interrupt(irq, ptr);
1007 /* Break Interrupt */
1008 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
1009 ret = sci_br_interrupt(irq, ptr);
1015 * Here we define a transition notifier so that we can update all of our
1016 * ports' baud rate when the peripheral clock changes.
1018 static int sci_notifier(struct notifier_block *self,
1019 unsigned long phase, void *p)
1021 struct sci_port *sci_port;
1022 unsigned long flags;
1024 sci_port = container_of(self, struct sci_port, freq_transition);
1026 if ((phase == CPUFREQ_POSTCHANGE) ||
1027 (phase == CPUFREQ_RESUMECHANGE)) {
1028 struct uart_port *port = &sci_port->port;
1030 spin_lock_irqsave(&port->lock, flags);
1031 port->uartclk = clk_get_rate(sci_port->iclk);
1032 spin_unlock_irqrestore(&port->lock, flags);
1038 static struct sci_irq_desc {
1040 irq_handler_t handler;
1041 } sci_irq_desc[] = {
1043 * Split out handlers, the default case.
1047 .handler = sci_er_interrupt,
1052 .handler = sci_rx_interrupt,
1057 .handler = sci_tx_interrupt,
1062 .handler = sci_br_interrupt,
1066 * Special muxed handler.
1070 .handler = sci_mpxed_interrupt,
1074 static int sci_request_irq(struct sci_port *port)
1076 struct uart_port *up = &port->port;
1079 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1080 struct sci_irq_desc *desc;
1083 if (SCIx_IRQ_IS_MUXED(port)) {
1087 irq = port->irqs[i];
1090 * Certain port types won't support all of the
1091 * available interrupt sources.
1093 if (unlikely(irq < 0))
1097 desc = sci_irq_desc + i;
1098 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1099 dev_name(up->dev), desc->desc);
1100 if (!port->irqstr[j]) {
1101 dev_err(up->dev, "Failed to allocate %s IRQ string\n",
1106 ret = request_irq(irq, desc->handler, up->irqflags,
1107 port->irqstr[j], port);
1108 if (unlikely(ret)) {
1109 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1118 free_irq(port->irqs[i], port);
1122 kfree(port->irqstr[j]);
1127 static void sci_free_irq(struct sci_port *port)
1132 * Intentionally in reverse order so we iterate over the muxed
1135 for (i = 0; i < SCIx_NR_IRQS; i++) {
1136 int irq = port->irqs[i];
1139 * Certain port types won't support all of the available
1140 * interrupt sources.
1142 if (unlikely(irq < 0))
1145 free_irq(port->irqs[i], port);
1146 kfree(port->irqstr[i]);
1148 if (SCIx_IRQ_IS_MUXED(port)) {
1149 /* If there's only one IRQ, we're done. */
1155 static unsigned int sci_tx_empty(struct uart_port *port)
1157 unsigned short status = serial_port_in(port, SCxSR);
1158 unsigned short in_tx_fifo = sci_txfill(port);
1160 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1164 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
1165 * CTS/RTS is supported in hardware by at least one port and controlled
1166 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
1167 * handled via the ->init_pins() op, which is a bit of a one-way street,
1168 * lacking any ability to defer pin control -- this will later be
1169 * converted over to the GPIO framework).
1171 * Other modes (such as loopback) are supported generically on certain
1172 * port types, but not others. For these it's sufficient to test for the
1173 * existence of the support register and simply ignore the port type.
1175 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1177 if (mctrl & TIOCM_LOOP) {
1178 struct plat_sci_reg *reg;
1181 * Standard loopback mode for SCFCR ports.
1183 reg = sci_getreg(port, SCFCR);
1185 serial_port_out(port, SCFCR, serial_port_in(port, SCFCR) | 1);
1189 static unsigned int sci_get_mctrl(struct uart_port *port)
1192 * CTS/RTS is handled in hardware when supported, while nothing
1193 * else is wired up. Keep it simple and simply assert DSR/CAR.
1195 return TIOCM_DSR | TIOCM_CAR;
1198 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1199 static void sci_dma_tx_complete(void *arg)
1201 struct sci_port *s = arg;
1202 struct uart_port *port = &s->port;
1203 struct circ_buf *xmit = &port->state->xmit;
1204 unsigned long flags;
1206 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1208 spin_lock_irqsave(&port->lock, flags);
1210 xmit->tail += sg_dma_len(&s->sg_tx);
1211 xmit->tail &= UART_XMIT_SIZE - 1;
1213 port->icount.tx += sg_dma_len(&s->sg_tx);
1215 async_tx_ack(s->desc_tx);
1218 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1219 uart_write_wakeup(port);
1221 if (!uart_circ_empty(xmit)) {
1223 schedule_work(&s->work_tx);
1225 s->cookie_tx = -EINVAL;
1226 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1227 u16 ctrl = serial_port_in(port, SCSCR);
1228 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1232 spin_unlock_irqrestore(&port->lock, flags);
1235 /* Locking: called with port lock held */
1236 static int sci_dma_rx_push(struct sci_port *s, size_t count)
1238 struct uart_port *port = &s->port;
1239 struct tty_port *tport = &port->state->port;
1240 int i, active, room;
1242 room = tty_buffer_request_room(tport, count);
1244 if (s->active_rx == s->cookie_rx[0]) {
1246 } else if (s->active_rx == s->cookie_rx[1]) {
1249 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
1254 dev_warn(port->dev, "Rx overrun: dropping %zu bytes\n",
1259 for (i = 0; i < room; i++)
1260 tty_insert_flip_char(tport, ((u8 *)sg_virt(&s->sg_rx[active]))[i],
1263 port->icount.rx += room;
1268 static void sci_dma_rx_complete(void *arg)
1270 struct sci_port *s = arg;
1271 struct uart_port *port = &s->port;
1272 unsigned long flags;
1275 dev_dbg(port->dev, "%s(%d) active #%d\n", __func__, port->line, s->active_rx);
1277 spin_lock_irqsave(&port->lock, flags);
1279 count = sci_dma_rx_push(s, s->buf_len_rx);
1281 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
1283 spin_unlock_irqrestore(&port->lock, flags);
1286 tty_flip_buffer_push(&port->state->port);
1288 schedule_work(&s->work_rx);
1291 static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
1293 struct dma_chan *chan = s->chan_rx;
1294 struct uart_port *port = &s->port;
1297 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1298 dma_release_channel(chan);
1299 if (sg_dma_address(&s->sg_rx[0]))
1300 dma_free_coherent(port->dev, s->buf_len_rx * 2,
1301 sg_virt(&s->sg_rx[0]), sg_dma_address(&s->sg_rx[0]));
1306 static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1308 struct dma_chan *chan = s->chan_tx;
1309 struct uart_port *port = &s->port;
1312 s->cookie_tx = -EINVAL;
1313 dma_release_channel(chan);
1318 static void sci_submit_rx(struct sci_port *s)
1320 struct dma_chan *chan = s->chan_rx;
1323 for (i = 0; i < 2; i++) {
1324 struct scatterlist *sg = &s->sg_rx[i];
1325 struct dma_async_tx_descriptor *desc;
1327 desc = dmaengine_prep_slave_sg(chan,
1328 sg, 1, DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
1331 s->desc_rx[i] = desc;
1332 desc->callback = sci_dma_rx_complete;
1333 desc->callback_param = s;
1334 s->cookie_rx[i] = desc->tx_submit(desc);
1337 if (!desc || s->cookie_rx[i] < 0) {
1339 async_tx_ack(s->desc_rx[0]);
1340 s->cookie_rx[0] = -EINVAL;
1344 s->cookie_rx[i] = -EINVAL;
1346 dev_warn(s->port.dev,
1347 "failed to re-start DMA, using PIO\n");
1348 sci_rx_dma_release(s, true);
1351 dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n", __func__,
1352 s->cookie_rx[i], i);
1355 s->active_rx = s->cookie_rx[0];
1357 dma_async_issue_pending(chan);
1360 static void work_fn_rx(struct work_struct *work)
1362 struct sci_port *s = container_of(work, struct sci_port, work_rx);
1363 struct uart_port *port = &s->port;
1364 struct dma_async_tx_descriptor *desc;
1367 if (s->active_rx == s->cookie_rx[0]) {
1369 } else if (s->active_rx == s->cookie_rx[1]) {
1372 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
1375 desc = s->desc_rx[new];
1377 if (dma_async_is_tx_complete(s->chan_rx, s->active_rx, NULL, NULL) !=
1379 /* Handle incomplete DMA receive */
1380 struct dma_chan *chan = s->chan_rx;
1381 struct shdma_desc *sh_desc = container_of(desc,
1382 struct shdma_desc, async_tx);
1383 unsigned long flags;
1386 chan->device->device_control(chan, DMA_TERMINATE_ALL, 0);
1387 dev_dbg(port->dev, "Read %zu bytes with cookie %d\n",
1388 sh_desc->partial, sh_desc->cookie);
1390 spin_lock_irqsave(&port->lock, flags);
1391 count = sci_dma_rx_push(s, sh_desc->partial);
1392 spin_unlock_irqrestore(&port->lock, flags);
1395 tty_flip_buffer_push(&port->state->port);
1402 s->cookie_rx[new] = desc->tx_submit(desc);
1403 if (s->cookie_rx[new] < 0) {
1404 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1405 sci_rx_dma_release(s, true);
1409 s->active_rx = s->cookie_rx[!new];
1411 dev_dbg(port->dev, "%s: cookie %d #%d, new active #%d\n", __func__,
1412 s->cookie_rx[new], new, s->active_rx);
1415 static void work_fn_tx(struct work_struct *work)
1417 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1418 struct dma_async_tx_descriptor *desc;
1419 struct dma_chan *chan = s->chan_tx;
1420 struct uart_port *port = &s->port;
1421 struct circ_buf *xmit = &port->state->xmit;
1422 struct scatterlist *sg = &s->sg_tx;
1426 * Port xmit buffer is already mapped, and it is one page... Just adjust
1427 * offsets and lengths. Since it is a circular buffer, we have to
1428 * transmit till the end, and then the rest. Take the port lock to get a
1429 * consistent xmit buffer state.
1431 spin_lock_irq(&port->lock);
1432 sg->offset = xmit->tail & (UART_XMIT_SIZE - 1);
1433 sg_dma_address(sg) = (sg_dma_address(sg) & ~(UART_XMIT_SIZE - 1)) +
1435 sg_dma_len(sg) = min((int)CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
1436 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
1437 spin_unlock_irq(&port->lock);
1439 BUG_ON(!sg_dma_len(sg));
1441 desc = dmaengine_prep_slave_sg(chan,
1442 sg, s->sg_len_tx, DMA_MEM_TO_DEV,
1443 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1446 sci_tx_dma_release(s, true);
1450 dma_sync_sg_for_device(port->dev, sg, 1, DMA_TO_DEVICE);
1452 spin_lock_irq(&port->lock);
1454 desc->callback = sci_dma_tx_complete;
1455 desc->callback_param = s;
1456 spin_unlock_irq(&port->lock);
1457 s->cookie_tx = desc->tx_submit(desc);
1458 if (s->cookie_tx < 0) {
1459 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1461 sci_tx_dma_release(s, true);
1465 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n", __func__,
1466 xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
1468 dma_async_issue_pending(chan);
1472 static void sci_start_tx(struct uart_port *port)
1474 struct sci_port *s = to_sci_port(port);
1475 unsigned short ctrl;
1477 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1478 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1479 u16 new, scr = serial_port_in(port, SCSCR);
1483 new = scr & ~0x8000;
1485 serial_port_out(port, SCSCR, new);
1488 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
1491 schedule_work(&s->work_tx);
1495 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1496 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
1497 ctrl = serial_port_in(port, SCSCR);
1498 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
1502 static void sci_stop_tx(struct uart_port *port)
1504 unsigned short ctrl;
1506 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
1507 ctrl = serial_port_in(port, SCSCR);
1509 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1514 serial_port_out(port, SCSCR, ctrl);
1517 static void sci_start_rx(struct uart_port *port)
1519 unsigned short ctrl;
1521 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
1523 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1526 serial_port_out(port, SCSCR, ctrl);
1529 static void sci_stop_rx(struct uart_port *port)
1531 unsigned short ctrl;
1533 ctrl = serial_port_in(port, SCSCR);
1535 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1538 ctrl &= ~port_rx_irq_mask(port);
1540 serial_port_out(port, SCSCR, ctrl);
1543 static void sci_enable_ms(struct uart_port *port)
1546 * Not supported by hardware, always a nop.
1550 static void sci_break_ctl(struct uart_port *port, int break_state)
1552 struct sci_port *s = to_sci_port(port);
1553 struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
1554 unsigned short scscr, scsptr;
1556 /* check wheter the port has SCSPTR */
1559 * Not supported by hardware. Most parts couple break and rx
1560 * interrupts together, with break detection always enabled.
1565 scsptr = serial_port_in(port, SCSPTR);
1566 scscr = serial_port_in(port, SCSCR);
1568 if (break_state == -1) {
1569 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
1572 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
1576 serial_port_out(port, SCSPTR, scsptr);
1577 serial_port_out(port, SCSCR, scscr);
1580 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1581 static bool filter(struct dma_chan *chan, void *slave)
1583 struct sh_dmae_slave *param = slave;
1585 dev_dbg(chan->device->dev, "%s: slave ID %d\n", __func__,
1586 param->shdma_slave.slave_id);
1588 chan->private = ¶m->shdma_slave;
1592 static void rx_timer_fn(unsigned long arg)
1594 struct sci_port *s = (struct sci_port *)arg;
1595 struct uart_port *port = &s->port;
1596 u16 scr = serial_port_in(port, SCSCR);
1598 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1600 enable_irq(s->irqs[SCIx_RXI_IRQ]);
1602 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
1603 dev_dbg(port->dev, "DMA Rx timed out\n");
1604 schedule_work(&s->work_rx);
1607 static void sci_request_dma(struct uart_port *port)
1609 struct sci_port *s = to_sci_port(port);
1610 struct sh_dmae_slave *param;
1611 struct dma_chan *chan;
1612 dma_cap_mask_t mask;
1615 dev_dbg(port->dev, "%s: port %d\n", __func__,
1618 if (s->cfg->dma_slave_tx <= 0 || s->cfg->dma_slave_rx <= 0)
1622 dma_cap_set(DMA_SLAVE, mask);
1624 param = &s->param_tx;
1626 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_TX */
1627 param->shdma_slave.slave_id = s->cfg->dma_slave_tx;
1629 s->cookie_tx = -EINVAL;
1630 chan = dma_request_channel(mask, filter, param);
1631 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1634 sg_init_table(&s->sg_tx, 1);
1635 /* UART circular tx buffer is an aligned page. */
1636 BUG_ON((uintptr_t)port->state->xmit.buf & ~PAGE_MASK);
1637 sg_set_page(&s->sg_tx, virt_to_page(port->state->xmit.buf),
1639 (uintptr_t)port->state->xmit.buf & ~PAGE_MASK);
1640 nent = dma_map_sg(port->dev, &s->sg_tx, 1, DMA_TO_DEVICE);
1642 sci_tx_dma_release(s, false);
1644 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
1645 sg_dma_len(&s->sg_tx), port->state->xmit.buf,
1646 &sg_dma_address(&s->sg_tx));
1648 s->sg_len_tx = nent;
1650 INIT_WORK(&s->work_tx, work_fn_tx);
1653 param = &s->param_rx;
1655 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_RX */
1656 param->shdma_slave.slave_id = s->cfg->dma_slave_rx;
1658 chan = dma_request_channel(mask, filter, param);
1659 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1667 s->buf_len_rx = 2 * max(16, (int)port->fifosize);
1668 buf[0] = dma_alloc_coherent(port->dev, s->buf_len_rx * 2,
1669 &dma[0], GFP_KERNEL);
1673 "failed to allocate dma buffer, using PIO\n");
1674 sci_rx_dma_release(s, true);
1678 buf[1] = buf[0] + s->buf_len_rx;
1679 dma[1] = dma[0] + s->buf_len_rx;
1681 for (i = 0; i < 2; i++) {
1682 struct scatterlist *sg = &s->sg_rx[i];
1684 sg_init_table(sg, 1);
1685 sg_set_page(sg, virt_to_page(buf[i]), s->buf_len_rx,
1686 (uintptr_t)buf[i] & ~PAGE_MASK);
1687 sg_dma_address(sg) = dma[i];
1690 INIT_WORK(&s->work_rx, work_fn_rx);
1691 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1697 static void sci_free_dma(struct uart_port *port)
1699 struct sci_port *s = to_sci_port(port);
1702 sci_tx_dma_release(s, false);
1704 sci_rx_dma_release(s, false);
1707 static inline void sci_request_dma(struct uart_port *port)
1711 static inline void sci_free_dma(struct uart_port *port)
1716 static int sci_startup(struct uart_port *port)
1718 struct sci_port *s = to_sci_port(port);
1719 unsigned long flags;
1722 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1724 ret = sci_request_irq(s);
1725 if (unlikely(ret < 0))
1728 sci_request_dma(port);
1730 spin_lock_irqsave(&port->lock, flags);
1733 spin_unlock_irqrestore(&port->lock, flags);
1738 static void sci_shutdown(struct uart_port *port)
1740 struct sci_port *s = to_sci_port(port);
1741 unsigned long flags;
1743 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1745 spin_lock_irqsave(&port->lock, flags);
1748 spin_unlock_irqrestore(&port->lock, flags);
1754 static unsigned int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
1757 if (s->sampling_rate)
1758 return DIV_ROUND_CLOSEST(freq, s->sampling_rate * bps) - 1;
1760 switch (s->cfg->scbrr_algo_id) {
1762 return freq / (16 * bps);
1764 return DIV_ROUND_CLOSEST(freq, 32 * bps) - 1;
1766 return freq / (8 * bps);
1768 return DIV_ROUND_CLOSEST(freq, 16 * bps) - 1;
1771 /* Warn, but use a safe default */
1774 return ((freq + 16 * bps) / (32 * bps) - 1);
1777 /* calculate sample rate, BRR, and clock select for HSCIF */
1778 static void sci_baud_calc_hscif(unsigned int bps, unsigned long freq,
1779 int *brr, unsigned int *srr,
1783 int min_err = 1000; /* 100% */
1785 /* Find the combination of sample rate and clock select with the
1786 smallest deviation from the desired baud rate. */
1787 for (sr = 8; sr <= 32; sr++) {
1788 for (c = 0; c <= 3; c++) {
1789 /* integerized formulas from HSCIF documentation */
1790 br = freq / (sr * (1 << (2 * c + 1)) * bps) - 1;
1791 if (br < 0 || br > 255)
1793 err = freq / ((br + 1) * bps * sr *
1794 (1 << (2 * c + 1)) / 1000) - 1000;
1795 if (min_err > err) {
1804 if (min_err == 1000) {
1813 static void sci_reset(struct uart_port *port)
1815 struct plat_sci_reg *reg;
1816 unsigned int status;
1819 status = serial_port_in(port, SCxSR);
1820 } while (!(status & SCxSR_TEND(port)));
1822 serial_port_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1824 reg = sci_getreg(port, SCFCR);
1826 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
1829 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1830 struct ktermios *old)
1832 struct sci_port *s = to_sci_port(port);
1833 struct plat_sci_reg *reg;
1834 unsigned int baud, smr_val, max_baud, cks = 0;
1836 unsigned int srr = 15;
1839 * earlyprintk comes here early on with port->uartclk set to zero.
1840 * the clock framework is not up and running at this point so here
1841 * we assume that 115200 is the maximum baud rate. please note that
1842 * the baud rate is not programmed during earlyprintk - it is assumed
1843 * that the previous boot loader has enabled required clocks and
1844 * setup the baud rate generator hardware for us already.
1846 max_baud = port->uartclk ? port->uartclk / 16 : 115200;
1848 baud = uart_get_baud_rate(port, termios, old, 0, max_baud);
1849 if (likely(baud && port->uartclk)) {
1850 if (s->cfg->type == PORT_HSCIF) {
1851 sci_baud_calc_hscif(baud, port->uartclk, &t, &srr,
1854 t = sci_scbrr_calc(s, baud, port->uartclk);
1855 for (cks = 0; t >= 256 && cks <= 3; cks++)
1864 smr_val = serial_port_in(port, SCSMR) & 3;
1866 if ((termios->c_cflag & CSIZE) == CS7)
1868 if (termios->c_cflag & PARENB)
1870 if (termios->c_cflag & PARODD)
1872 if (termios->c_cflag & CSTOPB)
1875 uart_update_timeout(port, termios->c_cflag, baud);
1877 dev_dbg(port->dev, "%s: SMR %x, cks %x, t %x, SCSCR %x\n",
1878 __func__, smr_val, cks, t, s->cfg->scscr);
1881 serial_port_out(port, SCSMR, (smr_val & ~3) | cks);
1882 serial_port_out(port, SCBRR, t);
1883 reg = sci_getreg(port, HSSRR);
1885 serial_port_out(port, HSSRR, srr | HSCIF_SRE);
1886 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
1888 serial_port_out(port, SCSMR, smr_val);
1890 sci_init_pins(port, termios->c_cflag);
1892 reg = sci_getreg(port, SCFCR);
1894 unsigned short ctrl = serial_port_in(port, SCFCR);
1896 if (s->cfg->capabilities & SCIx_HAVE_RTSCTS) {
1897 if (termios->c_cflag & CRTSCTS)
1904 * As we've done a sci_reset() above, ensure we don't
1905 * interfere with the FIFOs while toggling MCE. As the
1906 * reset values could still be set, simply mask them out.
1908 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
1910 serial_port_out(port, SCFCR, ctrl);
1913 serial_port_out(port, SCSCR, s->cfg->scscr);
1915 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1917 * Calculate delay for 1.5 DMA buffers: see
1918 * drivers/serial/serial_core.c::uart_update_timeout(). With 10 bits
1919 * (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above function
1920 * calculates 1 jiffie for the data plus 5 jiffies for the "slop(e)."
1921 * Then below we calculate 3 jiffies (12ms) for 1.5 DMA buffers (3 FIFO
1922 * sizes), but it has been found out experimentally, that this is not
1923 * enough: the driver too often needlessly runs on a DMA timeout. 20ms
1924 * as a minimum seem to work perfectly.
1927 s->rx_timeout = (port->timeout - HZ / 50) * s->buf_len_rx * 3 /
1930 "DMA Rx t-out %ums, tty t-out %u jiffies\n",
1931 s->rx_timeout * 1000 / HZ, port->timeout);
1932 if (s->rx_timeout < msecs_to_jiffies(20))
1933 s->rx_timeout = msecs_to_jiffies(20);
1937 if ((termios->c_cflag & CREAD) != 0)
1940 sci_port_disable(s);
1943 static void sci_pm(struct uart_port *port, unsigned int state,
1944 unsigned int oldstate)
1946 struct sci_port *sci_port = to_sci_port(port);
1950 sci_port_disable(sci_port);
1953 sci_port_enable(sci_port);
1958 static const char *sci_type(struct uart_port *port)
1960 switch (port->type) {
1978 static inline unsigned long sci_port_size(struct uart_port *port)
1981 * Pick an arbitrary size that encapsulates all of the base
1982 * registers by default. This can be optimized later, or derived
1983 * from platform resource data at such a time that ports begin to
1984 * behave more erratically.
1986 if (port->type == PORT_HSCIF)
1992 static int sci_remap_port(struct uart_port *port)
1994 unsigned long size = sci_port_size(port);
1997 * Nothing to do if there's already an established membase.
2002 if (port->flags & UPF_IOREMAP) {
2003 port->membase = ioremap_nocache(port->mapbase, size);
2004 if (unlikely(!port->membase)) {
2005 dev_err(port->dev, "can't remap port#%d\n", port->line);
2010 * For the simple (and majority of) cases where we don't
2011 * need to do any remapping, just cast the cookie
2014 port->membase = (void __iomem *)port->mapbase;
2020 static void sci_release_port(struct uart_port *port)
2022 if (port->flags & UPF_IOREMAP) {
2023 iounmap(port->membase);
2024 port->membase = NULL;
2027 release_mem_region(port->mapbase, sci_port_size(port));
2030 static int sci_request_port(struct uart_port *port)
2032 unsigned long size = sci_port_size(port);
2033 struct resource *res;
2036 res = request_mem_region(port->mapbase, size, dev_name(port->dev));
2037 if (unlikely(res == NULL))
2040 ret = sci_remap_port(port);
2041 if (unlikely(ret != 0)) {
2042 release_resource(res);
2049 static void sci_config_port(struct uart_port *port, int flags)
2051 if (flags & UART_CONFIG_TYPE) {
2052 struct sci_port *sport = to_sci_port(port);
2054 port->type = sport->cfg->type;
2055 sci_request_port(port);
2059 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2061 if (ser->baud_base < 2400)
2062 /* No paper tape reader for Mitch.. */
2068 static struct uart_ops sci_uart_ops = {
2069 .tx_empty = sci_tx_empty,
2070 .set_mctrl = sci_set_mctrl,
2071 .get_mctrl = sci_get_mctrl,
2072 .start_tx = sci_start_tx,
2073 .stop_tx = sci_stop_tx,
2074 .stop_rx = sci_stop_rx,
2075 .enable_ms = sci_enable_ms,
2076 .break_ctl = sci_break_ctl,
2077 .startup = sci_startup,
2078 .shutdown = sci_shutdown,
2079 .set_termios = sci_set_termios,
2082 .release_port = sci_release_port,
2083 .request_port = sci_request_port,
2084 .config_port = sci_config_port,
2085 .verify_port = sci_verify_port,
2086 #ifdef CONFIG_CONSOLE_POLL
2087 .poll_get_char = sci_poll_get_char,
2088 .poll_put_char = sci_poll_put_char,
2092 static int sci_init_single(struct platform_device *dev,
2093 struct sci_port *sci_port, unsigned int index,
2094 struct plat_sci_port *p, bool early)
2096 struct uart_port *port = &sci_port->port;
2097 const struct resource *res;
2098 unsigned int sampling_rate;
2104 port->ops = &sci_uart_ops;
2105 port->iotype = UPIO_MEM;
2108 if (dev->num_resources) {
2109 /* Device has resources, use them. */
2110 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2114 port->mapbase = res->start;
2116 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i)
2117 sci_port->irqs[i] = platform_get_irq(dev, i);
2119 /* The SCI generates several interrupts. They can be muxed
2120 * together or connected to different interrupt lines. In the
2121 * muxed case only one interrupt resource is specified. In the
2122 * non-muxed case three or four interrupt resources are
2123 * specified, as the BRI interrupt is optional.
2125 if (sci_port->irqs[0] < 0)
2128 if (sci_port->irqs[1] < 0) {
2129 sci_port->irqs[1] = sci_port->irqs[0];
2130 sci_port->irqs[2] = sci_port->irqs[0];
2131 sci_port->irqs[3] = sci_port->irqs[0];
2134 /* No resources, use old-style platform data. */
2135 port->mapbase = p->mapbase;
2136 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i)
2137 sci_port->irqs[i] = p->irqs[i] ? p->irqs[i] : -ENXIO;
2140 if (p->regtype == SCIx_PROBE_REGTYPE) {
2141 ret = sci_probe_regmap(p);
2148 port->fifosize = 256;
2149 sci_port->overrun_bit = 9;
2153 port->fifosize = 128;
2155 sci_port->overrun_bit = 0;
2158 port->fifosize = 64;
2159 sci_port->overrun_bit = 9;
2163 port->fifosize = 16;
2164 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) {
2165 sci_port->overrun_bit = 9;
2168 sci_port->overrun_bit = 0;
2174 sci_port->overrun_bit = 5;
2179 /* Set the sampling rate if the baud rate calculation algorithm isn't
2182 if (p->scbrr_algo_id == SCBRR_ALGO_NONE) {
2183 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that
2184 * doesn't match the SoC datasheet, this should be investigated.
2185 * Let platform data override the sampling rate for now.
2187 sci_port->sampling_rate = p->sampling_rate ? p->sampling_rate
2192 sci_port->iclk = clk_get(&dev->dev, "sci_ick");
2193 if (IS_ERR(sci_port->iclk)) {
2194 sci_port->iclk = clk_get(&dev->dev, "peripheral_clk");
2195 if (IS_ERR(sci_port->iclk)) {
2196 dev_err(&dev->dev, "can't get iclk\n");
2197 return PTR_ERR(sci_port->iclk);
2202 * The function clock is optional, ignore it if we can't
2205 sci_port->fclk = clk_get(&dev->dev, "sci_fck");
2206 if (IS_ERR(sci_port->fclk))
2207 sci_port->fclk = NULL;
2209 port->dev = &dev->dev;
2211 pm_runtime_enable(&dev->dev);
2214 sci_port->break_timer.data = (unsigned long)sci_port;
2215 sci_port->break_timer.function = sci_break_timer;
2216 init_timer(&sci_port->break_timer);
2219 * Establish some sensible defaults for the error detection.
2221 sci_port->error_mask = (p->type == PORT_SCI) ?
2222 SCI_DEFAULT_ERROR_MASK : SCIF_DEFAULT_ERROR_MASK;
2225 * Establish sensible defaults for the overrun detection, unless
2226 * the part has explicitly disabled support for it.
2230 * Make the error mask inclusive of overrun detection, if
2233 sci_port->error_mask |= 1 << sci_port->overrun_bit;
2235 port->type = p->type;
2236 port->flags = UPF_FIXED_PORT | p->flags;
2237 port->regshift = p->regshift;
2240 * The UART port needs an IRQ value, so we peg this to the RX IRQ
2241 * for the multi-IRQ ports, which is where we are primarily
2242 * concerned with the shutdown path synchronization.
2244 * For the muxed case there's nothing more to do.
2246 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
2249 port->serial_in = sci_serial_in;
2250 port->serial_out = sci_serial_out;
2252 if (p->dma_slave_tx > 0 && p->dma_slave_rx > 0)
2253 dev_dbg(port->dev, "DMA tx %d, rx %d\n",
2254 p->dma_slave_tx, p->dma_slave_rx);
2259 static void sci_cleanup_single(struct sci_port *port)
2261 clk_put(port->iclk);
2262 clk_put(port->fclk);
2264 pm_runtime_disable(port->port.dev);
2267 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2268 static void serial_console_putchar(struct uart_port *port, int ch)
2270 sci_poll_put_char(port, ch);
2274 * Print a string to the serial port trying not to disturb
2275 * any possible real use of the port...
2277 static void serial_console_write(struct console *co, const char *s,
2280 struct sci_port *sci_port = &sci_ports[co->index];
2281 struct uart_port *port = &sci_port->port;
2282 unsigned short bits, ctrl;
2283 unsigned long flags;
2286 local_irq_save(flags);
2289 else if (oops_in_progress)
2290 locked = spin_trylock(&port->lock);
2292 spin_lock(&port->lock);
2294 /* first save the SCSCR then disable the interrupts */
2295 ctrl = serial_port_in(port, SCSCR);
2296 serial_port_out(port, SCSCR, sci_port->cfg->scscr);
2298 uart_console_write(port, s, count, serial_console_putchar);
2300 /* wait until fifo is empty and last bit has been transmitted */
2301 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
2302 while ((serial_port_in(port, SCxSR) & bits) != bits)
2305 /* restore the SCSCR */
2306 serial_port_out(port, SCSCR, ctrl);
2309 spin_unlock(&port->lock);
2310 local_irq_restore(flags);
2313 static int serial_console_setup(struct console *co, char *options)
2315 struct sci_port *sci_port;
2316 struct uart_port *port;
2324 * Refuse to handle any bogus ports.
2326 if (co->index < 0 || co->index >= SCI_NPORTS)
2329 sci_port = &sci_ports[co->index];
2330 port = &sci_port->port;
2333 * Refuse to handle uninitialized ports.
2338 ret = sci_remap_port(port);
2339 if (unlikely(ret != 0))
2343 uart_parse_options(options, &baud, &parity, &bits, &flow);
2345 return uart_set_options(port, co, baud, parity, bits, flow);
2348 static struct console serial_console = {
2350 .device = uart_console_device,
2351 .write = serial_console_write,
2352 .setup = serial_console_setup,
2353 .flags = CON_PRINTBUFFER,
2355 .data = &sci_uart_driver,
2358 static struct console early_serial_console = {
2359 .name = "early_ttySC",
2360 .write = serial_console_write,
2361 .flags = CON_PRINTBUFFER,
2365 static char early_serial_buf[32];
2367 static int sci_probe_earlyprintk(struct platform_device *pdev)
2369 struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
2371 if (early_serial_console.data)
2374 early_serial_console.index = pdev->id;
2376 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
2378 serial_console_setup(&early_serial_console, early_serial_buf);
2380 if (!strstr(early_serial_buf, "keep"))
2381 early_serial_console.flags |= CON_BOOT;
2383 register_console(&early_serial_console);
2387 #define SCI_CONSOLE (&serial_console)
2390 static inline int sci_probe_earlyprintk(struct platform_device *pdev)
2395 #define SCI_CONSOLE NULL
2397 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
2399 static char banner[] __initdata =
2400 KERN_INFO "SuperH (H)SCI(F) driver initialized\n";
2402 static struct uart_driver sci_uart_driver = {
2403 .owner = THIS_MODULE,
2404 .driver_name = "sci",
2405 .dev_name = "ttySC",
2407 .minor = SCI_MINOR_START,
2409 .cons = SCI_CONSOLE,
2412 static int sci_remove(struct platform_device *dev)
2414 struct sci_port *port = platform_get_drvdata(dev);
2416 cpufreq_unregister_notifier(&port->freq_transition,
2417 CPUFREQ_TRANSITION_NOTIFIER);
2419 uart_remove_one_port(&sci_uart_driver, &port->port);
2421 sci_cleanup_single(port);
2426 static int sci_probe_single(struct platform_device *dev,
2428 struct plat_sci_port *p,
2429 struct sci_port *sciport)
2434 if (unlikely(index >= SCI_NPORTS)) {
2435 dev_notice(&dev->dev, "Attempting to register port "
2436 "%d when only %d are available.\n",
2437 index+1, SCI_NPORTS);
2438 dev_notice(&dev->dev, "Consider bumping "
2439 "CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
2443 ret = sci_init_single(dev, sciport, index, p, false);
2447 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
2449 sci_cleanup_single(sciport);
2456 static int sci_probe(struct platform_device *dev)
2458 struct plat_sci_port *p = dev_get_platdata(&dev->dev);
2459 struct sci_port *sp = &sci_ports[dev->id];
2463 * If we've come here via earlyprintk initialization, head off to
2464 * the special early probe. We don't have sufficient device state
2465 * to make it beyond this yet.
2467 if (is_early_platform_device(dev))
2468 return sci_probe_earlyprintk(dev);
2470 platform_set_drvdata(dev, sp);
2472 ret = sci_probe_single(dev, dev->id, p, sp);
2476 sp->freq_transition.notifier_call = sci_notifier;
2478 ret = cpufreq_register_notifier(&sp->freq_transition,
2479 CPUFREQ_TRANSITION_NOTIFIER);
2480 if (unlikely(ret < 0)) {
2481 sci_cleanup_single(sp);
2485 #ifdef CONFIG_SH_STANDARD_BIOS
2486 sh_bios_gdb_detach();
2492 static int sci_suspend(struct device *dev)
2494 struct sci_port *sport = dev_get_drvdata(dev);
2497 uart_suspend_port(&sci_uart_driver, &sport->port);
2502 static int sci_resume(struct device *dev)
2504 struct sci_port *sport = dev_get_drvdata(dev);
2507 uart_resume_port(&sci_uart_driver, &sport->port);
2512 static const struct dev_pm_ops sci_dev_pm_ops = {
2513 .suspend = sci_suspend,
2514 .resume = sci_resume,
2517 static struct platform_driver sci_driver = {
2519 .remove = sci_remove,
2522 .owner = THIS_MODULE,
2523 .pm = &sci_dev_pm_ops,
2527 static int __init sci_init(void)
2533 ret = uart_register_driver(&sci_uart_driver);
2534 if (likely(ret == 0)) {
2535 ret = platform_driver_register(&sci_driver);
2537 uart_unregister_driver(&sci_uart_driver);
2543 static void __exit sci_exit(void)
2545 platform_driver_unregister(&sci_driver);
2546 uart_unregister_driver(&sci_uart_driver);
2549 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2550 early_platform_init_buffer("earlyprintk", &sci_driver,
2551 early_serial_buf, ARRAY_SIZE(early_serial_buf));
2553 module_init(sci_init);
2554 module_exit(sci_exit);
2556 MODULE_LICENSE("GPL");
2557 MODULE_ALIAS("platform:sh-sci");
2558 MODULE_AUTHOR("Paul Mundt");
2559 MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");