2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
4 * Copyright (C) 2002 - 2011 Paul Mundt
5 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
7 * based off of the old drivers/char/sh-sci.c by:
9 * Copyright (C) 1999, 2000 Niibe Yutaka
10 * Copyright (C) 2000 Sugioka Toshinobu
11 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
12 * Modified to support SecureEdge. David McCullough (2002)
13 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
14 * Removed SH7300 support (Jul 2007).
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
20 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
26 #include <linux/module.h>
27 #include <linux/errno.h>
28 #include <linux/sh_dma.h>
29 #include <linux/timer.h>
30 #include <linux/interrupt.h>
31 #include <linux/tty.h>
32 #include <linux/tty_flip.h>
33 #include <linux/serial.h>
34 #include <linux/major.h>
35 #include <linux/string.h>
36 #include <linux/sysrq.h>
37 #include <linux/ioport.h>
39 #include <linux/init.h>
40 #include <linux/delay.h>
41 #include <linux/console.h>
42 #include <linux/platform_device.h>
43 #include <linux/serial_sci.h>
44 #include <linux/notifier.h>
45 #include <linux/pm_runtime.h>
46 #include <linux/cpufreq.h>
47 #include <linux/clk.h>
48 #include <linux/ctype.h>
49 #include <linux/err.h>
50 #include <linux/dmaengine.h>
51 #include <linux/dma-mapping.h>
52 #include <linux/scatterlist.h>
53 #include <linux/slab.h>
54 #include <linux/gpio.h>
57 #include <asm/sh_bios.h>
63 struct uart_port port;
65 /* Platform configuration */
66 struct plat_sci_port *cfg;
69 struct timer_list break_timer;
77 char *irqstr[SCIx_NR_IRQS];
78 char *gpiostr[SCIx_NR_FNS];
80 struct dma_chan *chan_tx;
81 struct dma_chan *chan_rx;
83 #ifdef CONFIG_SERIAL_SH_SCI_DMA
84 struct dma_async_tx_descriptor *desc_tx;
85 struct dma_async_tx_descriptor *desc_rx[2];
86 dma_cookie_t cookie_tx;
87 dma_cookie_t cookie_rx[2];
88 dma_cookie_t active_rx;
89 struct scatterlist sg_tx;
90 unsigned int sg_len_tx;
91 struct scatterlist sg_rx[2];
93 struct sh_dmae_slave param_tx;
94 struct sh_dmae_slave param_rx;
95 struct work_struct work_tx;
96 struct work_struct work_rx;
97 struct timer_list rx_timer;
98 unsigned int rx_timeout;
101 struct notifier_block freq_transition;
104 /* Function prototypes */
105 static void sci_start_tx(struct uart_port *port);
106 static void sci_stop_tx(struct uart_port *port);
107 static void sci_start_rx(struct uart_port *port);
109 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
111 static struct sci_port sci_ports[SCI_NPORTS];
112 static struct uart_driver sci_uart_driver;
114 static inline struct sci_port *
115 to_sci_port(struct uart_port *uart)
117 return container_of(uart, struct sci_port, port);
120 struct plat_sci_reg {
124 /* Helper for invalidating specific entries of an inherited map. */
125 #define sci_reg_invalid { .offset = 0, .size = 0 }
127 static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
128 [SCIx_PROBE_REGTYPE] = {
129 [0 ... SCIx_NR_REGS - 1] = sci_reg_invalid,
133 * Common SCI definitions, dependent on the port's regshift
136 [SCIx_SCI_REGTYPE] = {
137 [SCSMR] = { 0x00, 8 },
138 [SCBRR] = { 0x01, 8 },
139 [SCSCR] = { 0x02, 8 },
140 [SCxTDR] = { 0x03, 8 },
141 [SCxSR] = { 0x04, 8 },
142 [SCxRDR] = { 0x05, 8 },
143 [SCFCR] = sci_reg_invalid,
144 [SCFDR] = sci_reg_invalid,
145 [SCTFDR] = sci_reg_invalid,
146 [SCRFDR] = sci_reg_invalid,
147 [SCSPTR] = sci_reg_invalid,
148 [SCLSR] = sci_reg_invalid,
149 [HSSRR] = sci_reg_invalid,
153 * Common definitions for legacy IrDA ports, dependent on
156 [SCIx_IRDA_REGTYPE] = {
157 [SCSMR] = { 0x00, 8 },
158 [SCBRR] = { 0x01, 8 },
159 [SCSCR] = { 0x02, 8 },
160 [SCxTDR] = { 0x03, 8 },
161 [SCxSR] = { 0x04, 8 },
162 [SCxRDR] = { 0x05, 8 },
163 [SCFCR] = { 0x06, 8 },
164 [SCFDR] = { 0x07, 16 },
165 [SCTFDR] = sci_reg_invalid,
166 [SCRFDR] = sci_reg_invalid,
167 [SCSPTR] = sci_reg_invalid,
168 [SCLSR] = sci_reg_invalid,
169 [HSSRR] = sci_reg_invalid,
173 * Common SCIFA definitions.
175 [SCIx_SCIFA_REGTYPE] = {
176 [SCSMR] = { 0x00, 16 },
177 [SCBRR] = { 0x04, 8 },
178 [SCSCR] = { 0x08, 16 },
179 [SCxTDR] = { 0x20, 8 },
180 [SCxSR] = { 0x14, 16 },
181 [SCxRDR] = { 0x24, 8 },
182 [SCFCR] = { 0x18, 16 },
183 [SCFDR] = { 0x1c, 16 },
184 [SCTFDR] = sci_reg_invalid,
185 [SCRFDR] = sci_reg_invalid,
186 [SCSPTR] = sci_reg_invalid,
187 [SCLSR] = sci_reg_invalid,
188 [HSSRR] = sci_reg_invalid,
192 * Common SCIFB definitions.
194 [SCIx_SCIFB_REGTYPE] = {
195 [SCSMR] = { 0x00, 16 },
196 [SCBRR] = { 0x04, 8 },
197 [SCSCR] = { 0x08, 16 },
198 [SCxTDR] = { 0x40, 8 },
199 [SCxSR] = { 0x14, 16 },
200 [SCxRDR] = { 0x60, 8 },
201 [SCFCR] = { 0x18, 16 },
202 [SCFDR] = sci_reg_invalid,
203 [SCTFDR] = { 0x38, 16 },
204 [SCRFDR] = { 0x3c, 16 },
205 [SCSPTR] = sci_reg_invalid,
206 [SCLSR] = sci_reg_invalid,
207 [HSSRR] = sci_reg_invalid,
211 * Common SH-2(A) SCIF definitions for ports with FIFO data
214 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
215 [SCSMR] = { 0x00, 16 },
216 [SCBRR] = { 0x04, 8 },
217 [SCSCR] = { 0x08, 16 },
218 [SCxTDR] = { 0x0c, 8 },
219 [SCxSR] = { 0x10, 16 },
220 [SCxRDR] = { 0x14, 8 },
221 [SCFCR] = { 0x18, 16 },
222 [SCFDR] = { 0x1c, 16 },
223 [SCTFDR] = sci_reg_invalid,
224 [SCRFDR] = sci_reg_invalid,
225 [SCSPTR] = { 0x20, 16 },
226 [SCLSR] = { 0x24, 16 },
227 [HSSRR] = sci_reg_invalid,
231 * Common SH-3 SCIF definitions.
233 [SCIx_SH3_SCIF_REGTYPE] = {
234 [SCSMR] = { 0x00, 8 },
235 [SCBRR] = { 0x02, 8 },
236 [SCSCR] = { 0x04, 8 },
237 [SCxTDR] = { 0x06, 8 },
238 [SCxSR] = { 0x08, 16 },
239 [SCxRDR] = { 0x0a, 8 },
240 [SCFCR] = { 0x0c, 8 },
241 [SCFDR] = { 0x0e, 16 },
242 [SCTFDR] = sci_reg_invalid,
243 [SCRFDR] = sci_reg_invalid,
244 [SCSPTR] = sci_reg_invalid,
245 [SCLSR] = sci_reg_invalid,
246 [HSSRR] = sci_reg_invalid,
250 * Common SH-4(A) SCIF(B) definitions.
252 [SCIx_SH4_SCIF_REGTYPE] = {
253 [SCSMR] = { 0x00, 16 },
254 [SCBRR] = { 0x04, 8 },
255 [SCSCR] = { 0x08, 16 },
256 [SCxTDR] = { 0x0c, 8 },
257 [SCxSR] = { 0x10, 16 },
258 [SCxRDR] = { 0x14, 8 },
259 [SCFCR] = { 0x18, 16 },
260 [SCFDR] = { 0x1c, 16 },
261 [SCTFDR] = sci_reg_invalid,
262 [SCRFDR] = sci_reg_invalid,
263 [SCSPTR] = { 0x20, 16 },
264 [SCLSR] = { 0x24, 16 },
265 [HSSRR] = sci_reg_invalid,
269 * Common HSCIF definitions.
271 [SCIx_HSCIF_REGTYPE] = {
272 [SCSMR] = { 0x00, 16 },
273 [SCBRR] = { 0x04, 8 },
274 [SCSCR] = { 0x08, 16 },
275 [SCxTDR] = { 0x0c, 8 },
276 [SCxSR] = { 0x10, 16 },
277 [SCxRDR] = { 0x14, 8 },
278 [SCFCR] = { 0x18, 16 },
279 [SCFDR] = { 0x1c, 16 },
280 [SCTFDR] = sci_reg_invalid,
281 [SCRFDR] = sci_reg_invalid,
282 [SCSPTR] = { 0x20, 16 },
283 [SCLSR] = { 0x24, 16 },
284 [HSSRR] = { 0x40, 16 },
288 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
291 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
292 [SCSMR] = { 0x00, 16 },
293 [SCBRR] = { 0x04, 8 },
294 [SCSCR] = { 0x08, 16 },
295 [SCxTDR] = { 0x0c, 8 },
296 [SCxSR] = { 0x10, 16 },
297 [SCxRDR] = { 0x14, 8 },
298 [SCFCR] = { 0x18, 16 },
299 [SCFDR] = { 0x1c, 16 },
300 [SCTFDR] = sci_reg_invalid,
301 [SCRFDR] = sci_reg_invalid,
302 [SCSPTR] = sci_reg_invalid,
303 [SCLSR] = { 0x24, 16 },
304 [HSSRR] = sci_reg_invalid,
308 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
311 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
312 [SCSMR] = { 0x00, 16 },
313 [SCBRR] = { 0x04, 8 },
314 [SCSCR] = { 0x08, 16 },
315 [SCxTDR] = { 0x0c, 8 },
316 [SCxSR] = { 0x10, 16 },
317 [SCxRDR] = { 0x14, 8 },
318 [SCFCR] = { 0x18, 16 },
319 [SCFDR] = { 0x1c, 16 },
320 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
321 [SCRFDR] = { 0x20, 16 },
322 [SCSPTR] = { 0x24, 16 },
323 [SCLSR] = { 0x28, 16 },
324 [HSSRR] = sci_reg_invalid,
328 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
331 [SCIx_SH7705_SCIF_REGTYPE] = {
332 [SCSMR] = { 0x00, 16 },
333 [SCBRR] = { 0x04, 8 },
334 [SCSCR] = { 0x08, 16 },
335 [SCxTDR] = { 0x20, 8 },
336 [SCxSR] = { 0x14, 16 },
337 [SCxRDR] = { 0x24, 8 },
338 [SCFCR] = { 0x18, 16 },
339 [SCFDR] = { 0x1c, 16 },
340 [SCTFDR] = sci_reg_invalid,
341 [SCRFDR] = sci_reg_invalid,
342 [SCSPTR] = sci_reg_invalid,
343 [SCLSR] = sci_reg_invalid,
344 [HSSRR] = sci_reg_invalid,
348 #define sci_getreg(up, offset) (sci_regmap[to_sci_port(up)->cfg->regtype] + offset)
351 * The "offset" here is rather misleading, in that it refers to an enum
352 * value relative to the port mapping rather than the fixed offset
353 * itself, which needs to be manually retrieved from the platform's
354 * register map for the given port.
356 static unsigned int sci_serial_in(struct uart_port *p, int offset)
358 struct plat_sci_reg *reg = sci_getreg(p, offset);
361 return ioread8(p->membase + (reg->offset << p->regshift));
362 else if (reg->size == 16)
363 return ioread16(p->membase + (reg->offset << p->regshift));
365 WARN(1, "Invalid register access\n");
370 static void sci_serial_out(struct uart_port *p, int offset, int value)
372 struct plat_sci_reg *reg = sci_getreg(p, offset);
375 iowrite8(value, p->membase + (reg->offset << p->regshift));
376 else if (reg->size == 16)
377 iowrite16(value, p->membase + (reg->offset << p->regshift));
379 WARN(1, "Invalid register access\n");
382 static int sci_probe_regmap(struct plat_sci_port *cfg)
386 cfg->regtype = SCIx_SCI_REGTYPE;
389 cfg->regtype = SCIx_IRDA_REGTYPE;
392 cfg->regtype = SCIx_SCIFA_REGTYPE;
395 cfg->regtype = SCIx_SCIFB_REGTYPE;
399 * The SH-4 is a bit of a misnomer here, although that's
400 * where this particular port layout originated. This
401 * configuration (or some slight variation thereof)
402 * remains the dominant model for all SCIFs.
404 cfg->regtype = SCIx_SH4_SCIF_REGTYPE;
407 cfg->regtype = SCIx_HSCIF_REGTYPE;
410 printk(KERN_ERR "Can't probe register map for given port\n");
417 static void sci_port_enable(struct sci_port *sci_port)
419 if (!sci_port->port.dev)
422 pm_runtime_get_sync(sci_port->port.dev);
424 clk_prepare_enable(sci_port->iclk);
425 sci_port->port.uartclk = clk_get_rate(sci_port->iclk);
426 clk_prepare_enable(sci_port->fclk);
429 static void sci_port_disable(struct sci_port *sci_port)
431 if (!sci_port->port.dev)
434 /* Cancel the break timer to ensure that the timer handler will not try
435 * to access the hardware with clocks and power disabled. Reset the
436 * break flag to make the break debouncing state machine ready for the
439 del_timer_sync(&sci_port->break_timer);
440 sci_port->break_flag = 0;
442 clk_disable_unprepare(sci_port->fclk);
443 clk_disable_unprepare(sci_port->iclk);
445 pm_runtime_put_sync(sci_port->port.dev);
448 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
450 #ifdef CONFIG_CONSOLE_POLL
451 static int sci_poll_get_char(struct uart_port *port)
453 unsigned short status;
457 status = serial_port_in(port, SCxSR);
458 if (status & SCxSR_ERRORS(port)) {
459 serial_port_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
465 if (!(status & SCxSR_RDxF(port)))
468 c = serial_port_in(port, SCxRDR);
471 serial_port_in(port, SCxSR);
472 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
478 static void sci_poll_put_char(struct uart_port *port, unsigned char c)
480 unsigned short status;
483 status = serial_port_in(port, SCxSR);
484 } while (!(status & SCxSR_TDxE(port)));
486 serial_port_out(port, SCxTDR, c);
487 serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
489 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
491 static void sci_init_pins(struct uart_port *port, unsigned int cflag)
493 struct sci_port *s = to_sci_port(port);
494 struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
497 * Use port-specific handler if provided.
499 if (s->cfg->ops && s->cfg->ops->init_pins) {
500 s->cfg->ops->init_pins(port, cflag);
505 * For the generic path SCSPTR is necessary. Bail out if that's
511 if ((s->cfg->capabilities & SCIx_HAVE_RTSCTS) &&
512 ((!(cflag & CRTSCTS)))) {
513 unsigned short status;
515 status = serial_port_in(port, SCSPTR);
516 status &= ~SCSPTR_CTSIO;
517 status |= SCSPTR_RTSIO;
518 serial_port_out(port, SCSPTR, status); /* Set RTS = 1 */
522 static int sci_txfill(struct uart_port *port)
524 struct plat_sci_reg *reg;
526 reg = sci_getreg(port, SCTFDR);
528 return serial_port_in(port, SCTFDR) & ((port->fifosize << 1) - 1);
530 reg = sci_getreg(port, SCFDR);
532 return serial_port_in(port, SCFDR) >> 8;
534 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
537 static int sci_txroom(struct uart_port *port)
539 return port->fifosize - sci_txfill(port);
542 static int sci_rxfill(struct uart_port *port)
544 struct plat_sci_reg *reg;
546 reg = sci_getreg(port, SCRFDR);
548 return serial_port_in(port, SCRFDR) & ((port->fifosize << 1) - 1);
550 reg = sci_getreg(port, SCFDR);
552 return serial_port_in(port, SCFDR) & ((port->fifosize << 1) - 1);
554 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
558 * SCI helper for checking the state of the muxed port/RXD pins.
560 static inline int sci_rxd_in(struct uart_port *port)
562 struct sci_port *s = to_sci_port(port);
564 if (s->cfg->port_reg <= 0)
567 /* Cast for ARM damage */
568 return !!__raw_readb((void __iomem *)(uintptr_t)s->cfg->port_reg);
571 /* ********************************************************************** *
572 * the interrupt related routines *
573 * ********************************************************************** */
575 static void sci_transmit_chars(struct uart_port *port)
577 struct circ_buf *xmit = &port->state->xmit;
578 unsigned int stopped = uart_tx_stopped(port);
579 unsigned short status;
583 status = serial_port_in(port, SCxSR);
584 if (!(status & SCxSR_TDxE(port))) {
585 ctrl = serial_port_in(port, SCSCR);
586 if (uart_circ_empty(xmit))
590 serial_port_out(port, SCSCR, ctrl);
594 count = sci_txroom(port);
602 } else if (!uart_circ_empty(xmit) && !stopped) {
603 c = xmit->buf[xmit->tail];
604 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
609 serial_port_out(port, SCxTDR, c);
612 } while (--count > 0);
614 serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
616 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
617 uart_write_wakeup(port);
618 if (uart_circ_empty(xmit)) {
621 ctrl = serial_port_in(port, SCSCR);
623 if (port->type != PORT_SCI) {
624 serial_port_in(port, SCxSR); /* Dummy read */
625 serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
629 serial_port_out(port, SCSCR, ctrl);
633 /* On SH3, SCIF may read end-of-break as a space->mark char */
634 #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
636 static void sci_receive_chars(struct uart_port *port)
638 struct sci_port *sci_port = to_sci_port(port);
639 struct tty_port *tport = &port->state->port;
640 int i, count, copied = 0;
641 unsigned short status;
644 status = serial_port_in(port, SCxSR);
645 if (!(status & SCxSR_RDxF(port)))
649 /* Don't copy more bytes than there is room for in the buffer */
650 count = tty_buffer_request_room(tport, sci_rxfill(port));
652 /* If for any reason we can't copy more data, we're done! */
656 if (port->type == PORT_SCI) {
657 char c = serial_port_in(port, SCxRDR);
658 if (uart_handle_sysrq_char(port, c) ||
659 sci_port->break_flag)
662 tty_insert_flip_char(tport, c, TTY_NORMAL);
664 for (i = 0; i < count; i++) {
665 char c = serial_port_in(port, SCxRDR);
667 status = serial_port_in(port, SCxSR);
668 #if defined(CONFIG_CPU_SH3)
669 /* Skip "chars" during break */
670 if (sci_port->break_flag) {
672 (status & SCxSR_FER(port))) {
677 /* Nonzero => end-of-break */
678 dev_dbg(port->dev, "debounce<%02x>\n", c);
679 sci_port->break_flag = 0;
686 #endif /* CONFIG_CPU_SH3 */
687 if (uart_handle_sysrq_char(port, c)) {
692 /* Store data and status */
693 if (status & SCxSR_FER(port)) {
695 port->icount.frame++;
696 dev_notice(port->dev, "frame error\n");
697 } else if (status & SCxSR_PER(port)) {
699 port->icount.parity++;
700 dev_notice(port->dev, "parity error\n");
704 tty_insert_flip_char(tport, c, flag);
708 serial_port_in(port, SCxSR); /* dummy read */
709 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
712 port->icount.rx += count;
716 /* Tell the rest of the system the news. New characters! */
717 tty_flip_buffer_push(tport);
719 serial_port_in(port, SCxSR); /* dummy read */
720 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
724 #define SCI_BREAK_JIFFIES (HZ/20)
727 * The sci generates interrupts during the break,
728 * 1 per millisecond or so during the break period, for 9600 baud.
729 * So dont bother disabling interrupts.
730 * But dont want more than 1 break event.
731 * Use a kernel timer to periodically poll the rx line until
732 * the break is finished.
734 static inline void sci_schedule_break_timer(struct sci_port *port)
736 mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES);
739 /* Ensure that two consecutive samples find the break over. */
740 static void sci_break_timer(unsigned long data)
742 struct sci_port *port = (struct sci_port *)data;
744 if (sci_rxd_in(&port->port) == 0) {
745 port->break_flag = 1;
746 sci_schedule_break_timer(port);
747 } else if (port->break_flag == 1) {
749 port->break_flag = 2;
750 sci_schedule_break_timer(port);
752 port->break_flag = 0;
755 static int sci_handle_errors(struct uart_port *port)
758 unsigned short status = serial_port_in(port, SCxSR);
759 struct tty_port *tport = &port->state->port;
760 struct sci_port *s = to_sci_port(port);
763 * Handle overruns, if supported.
765 if (s->cfg->overrun_bit != SCIx_NOT_SUPPORTED) {
766 if (status & (1 << s->cfg->overrun_bit)) {
767 port->icount.overrun++;
770 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
773 dev_notice(port->dev, "overrun error");
777 if (status & SCxSR_FER(port)) {
778 if (sci_rxd_in(port) == 0) {
779 /* Notify of BREAK */
780 struct sci_port *sci_port = to_sci_port(port);
782 if (!sci_port->break_flag) {
785 sci_port->break_flag = 1;
786 sci_schedule_break_timer(sci_port);
788 /* Do sysrq handling. */
789 if (uart_handle_break(port))
792 dev_dbg(port->dev, "BREAK detected\n");
794 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
800 port->icount.frame++;
802 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
805 dev_notice(port->dev, "frame error\n");
809 if (status & SCxSR_PER(port)) {
811 port->icount.parity++;
813 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
816 dev_notice(port->dev, "parity error");
820 tty_flip_buffer_push(tport);
825 static int sci_handle_fifo_overrun(struct uart_port *port)
827 struct tty_port *tport = &port->state->port;
828 struct sci_port *s = to_sci_port(port);
829 struct plat_sci_reg *reg;
832 reg = sci_getreg(port, SCLSR);
836 if ((serial_port_in(port, SCLSR) & (1 << s->cfg->overrun_bit))) {
837 serial_port_out(port, SCLSR, 0);
839 port->icount.overrun++;
841 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
842 tty_flip_buffer_push(tport);
844 dev_notice(port->dev, "overrun error\n");
851 static int sci_handle_breaks(struct uart_port *port)
854 unsigned short status = serial_port_in(port, SCxSR);
855 struct tty_port *tport = &port->state->port;
856 struct sci_port *s = to_sci_port(port);
858 if (uart_handle_break(port))
861 if (!s->break_flag && status & SCxSR_BRK(port)) {
862 #if defined(CONFIG_CPU_SH3)
869 /* Notify of BREAK */
870 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
873 dev_dbg(port->dev, "BREAK detected\n");
877 tty_flip_buffer_push(tport);
879 copied += sci_handle_fifo_overrun(port);
884 static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
886 #ifdef CONFIG_SERIAL_SH_SCI_DMA
887 struct uart_port *port = ptr;
888 struct sci_port *s = to_sci_port(port);
891 u16 scr = serial_port_in(port, SCSCR);
892 u16 ssr = serial_port_in(port, SCxSR);
894 /* Disable future Rx interrupts */
895 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
896 disable_irq_nosync(irq);
901 serial_port_out(port, SCSCR, scr);
902 /* Clear current interrupt */
903 serial_port_out(port, SCxSR, ssr & ~(1 | SCxSR_RDxF(port)));
904 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
905 jiffies, s->rx_timeout);
906 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
912 /* I think sci_receive_chars has to be called irrespective
913 * of whether the I_IXOFF is set, otherwise, how is the interrupt
916 sci_receive_chars(ptr);
921 static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
923 struct uart_port *port = ptr;
926 spin_lock_irqsave(&port->lock, flags);
927 sci_transmit_chars(port);
928 spin_unlock_irqrestore(&port->lock, flags);
933 static irqreturn_t sci_er_interrupt(int irq, void *ptr)
935 struct uart_port *port = ptr;
938 if (port->type == PORT_SCI) {
939 if (sci_handle_errors(port)) {
940 /* discard character in rx buffer */
941 serial_port_in(port, SCxSR);
942 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
945 sci_handle_fifo_overrun(port);
946 sci_rx_interrupt(irq, ptr);
949 serial_port_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
951 /* Kick the transmission */
952 sci_tx_interrupt(irq, ptr);
957 static irqreturn_t sci_br_interrupt(int irq, void *ptr)
959 struct uart_port *port = ptr;
962 sci_handle_breaks(port);
963 serial_port_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
968 static inline unsigned long port_rx_irq_mask(struct uart_port *port)
971 * Not all ports (such as SCIFA) will support REIE. Rather than
972 * special-casing the port type, we check the port initialization
973 * IRQ enable mask to see whether the IRQ is desired at all. If
974 * it's unset, it's logically inferred that there's no point in
977 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
980 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
982 unsigned short ssr_status, scr_status, err_enabled;
983 struct uart_port *port = ptr;
984 struct sci_port *s = to_sci_port(port);
985 irqreturn_t ret = IRQ_NONE;
987 ssr_status = serial_port_in(port, SCxSR);
988 scr_status = serial_port_in(port, SCSCR);
989 err_enabled = scr_status & port_rx_irq_mask(port);
992 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
994 ret = sci_tx_interrupt(irq, ptr);
997 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1000 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
1001 (scr_status & SCSCR_RIE))
1002 ret = sci_rx_interrupt(irq, ptr);
1004 /* Error Interrupt */
1005 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
1006 ret = sci_er_interrupt(irq, ptr);
1008 /* Break Interrupt */
1009 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
1010 ret = sci_br_interrupt(irq, ptr);
1016 * Here we define a transition notifier so that we can update all of our
1017 * ports' baud rate when the peripheral clock changes.
1019 static int sci_notifier(struct notifier_block *self,
1020 unsigned long phase, void *p)
1022 struct sci_port *sci_port;
1023 unsigned long flags;
1025 sci_port = container_of(self, struct sci_port, freq_transition);
1027 if ((phase == CPUFREQ_POSTCHANGE) ||
1028 (phase == CPUFREQ_RESUMECHANGE)) {
1029 struct uart_port *port = &sci_port->port;
1031 spin_lock_irqsave(&port->lock, flags);
1032 port->uartclk = clk_get_rate(sci_port->iclk);
1033 spin_unlock_irqrestore(&port->lock, flags);
1039 static struct sci_irq_desc {
1041 irq_handler_t handler;
1042 } sci_irq_desc[] = {
1044 * Split out handlers, the default case.
1048 .handler = sci_er_interrupt,
1053 .handler = sci_rx_interrupt,
1058 .handler = sci_tx_interrupt,
1063 .handler = sci_br_interrupt,
1067 * Special muxed handler.
1071 .handler = sci_mpxed_interrupt,
1075 static int sci_request_irq(struct sci_port *port)
1077 struct uart_port *up = &port->port;
1080 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1081 struct sci_irq_desc *desc;
1084 if (SCIx_IRQ_IS_MUXED(port)) {
1088 irq = port->cfg->irqs[i];
1091 * Certain port types won't support all of the
1092 * available interrupt sources.
1098 desc = sci_irq_desc + i;
1099 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1100 dev_name(up->dev), desc->desc);
1101 if (!port->irqstr[j]) {
1102 dev_err(up->dev, "Failed to allocate %s IRQ string\n",
1107 ret = request_irq(irq, desc->handler, up->irqflags,
1108 port->irqstr[j], port);
1109 if (unlikely(ret)) {
1110 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1119 free_irq(port->cfg->irqs[i], port);
1123 kfree(port->irqstr[j]);
1128 static void sci_free_irq(struct sci_port *port)
1133 * Intentionally in reverse order so we iterate over the muxed
1136 for (i = 0; i < SCIx_NR_IRQS; i++) {
1137 unsigned int irq = port->cfg->irqs[i];
1140 * Certain port types won't support all of the available
1141 * interrupt sources.
1146 free_irq(port->cfg->irqs[i], port);
1147 kfree(port->irqstr[i]);
1149 if (SCIx_IRQ_IS_MUXED(port)) {
1150 /* If there's only one IRQ, we're done. */
1156 static const char *sci_gpio_names[SCIx_NR_FNS] = {
1157 "sck", "rxd", "txd", "cts", "rts",
1160 static const char *sci_gpio_str(unsigned int index)
1162 return sci_gpio_names[index];
1165 static void sci_init_gpios(struct sci_port *port)
1167 struct uart_port *up = &port->port;
1173 for (i = 0; i < SCIx_NR_FNS; i++) {
1177 if (!port->cfg->gpios[i])
1180 desc = sci_gpio_str(i);
1182 port->gpiostr[i] = kasprintf(GFP_KERNEL, "%s:%s",
1183 dev_name(up->dev), desc);
1186 * If we've failed the allocation, we can still continue
1187 * on with a NULL string.
1189 if (!port->gpiostr[i])
1190 dev_notice(up->dev, "%s string allocation failure\n",
1193 ret = gpio_request(port->cfg->gpios[i], port->gpiostr[i]);
1194 if (unlikely(ret != 0)) {
1195 dev_notice(up->dev, "failed %s gpio request\n", desc);
1198 * If we can't get the GPIO for whatever reason,
1199 * no point in keeping the verbose string around.
1201 kfree(port->gpiostr[i]);
1206 static void sci_free_gpios(struct sci_port *port)
1210 for (i = 0; i < SCIx_NR_FNS; i++)
1211 if (port->cfg->gpios[i]) {
1212 gpio_free(port->cfg->gpios[i]);
1213 kfree(port->gpiostr[i]);
1217 static unsigned int sci_tx_empty(struct uart_port *port)
1219 unsigned short status = serial_port_in(port, SCxSR);
1220 unsigned short in_tx_fifo = sci_txfill(port);
1222 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1226 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
1227 * CTS/RTS is supported in hardware by at least one port and controlled
1228 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
1229 * handled via the ->init_pins() op, which is a bit of a one-way street,
1230 * lacking any ability to defer pin control -- this will later be
1231 * converted over to the GPIO framework).
1233 * Other modes (such as loopback) are supported generically on certain
1234 * port types, but not others. For these it's sufficient to test for the
1235 * existence of the support register and simply ignore the port type.
1237 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1239 if (mctrl & TIOCM_LOOP) {
1240 struct plat_sci_reg *reg;
1243 * Standard loopback mode for SCFCR ports.
1245 reg = sci_getreg(port, SCFCR);
1247 serial_port_out(port, SCFCR, serial_port_in(port, SCFCR) | 1);
1251 static unsigned int sci_get_mctrl(struct uart_port *port)
1254 * CTS/RTS is handled in hardware when supported, while nothing
1255 * else is wired up. Keep it simple and simply assert DSR/CAR.
1257 return TIOCM_DSR | TIOCM_CAR;
1260 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1261 static void sci_dma_tx_complete(void *arg)
1263 struct sci_port *s = arg;
1264 struct uart_port *port = &s->port;
1265 struct circ_buf *xmit = &port->state->xmit;
1266 unsigned long flags;
1268 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1270 spin_lock_irqsave(&port->lock, flags);
1272 xmit->tail += sg_dma_len(&s->sg_tx);
1273 xmit->tail &= UART_XMIT_SIZE - 1;
1275 port->icount.tx += sg_dma_len(&s->sg_tx);
1277 async_tx_ack(s->desc_tx);
1280 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1281 uart_write_wakeup(port);
1283 if (!uart_circ_empty(xmit)) {
1285 schedule_work(&s->work_tx);
1287 s->cookie_tx = -EINVAL;
1288 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1289 u16 ctrl = serial_port_in(port, SCSCR);
1290 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1294 spin_unlock_irqrestore(&port->lock, flags);
1297 /* Locking: called with port lock held */
1298 static int sci_dma_rx_push(struct sci_port *s, size_t count)
1300 struct uart_port *port = &s->port;
1301 struct tty_port *tport = &port->state->port;
1302 int i, active, room;
1304 room = tty_buffer_request_room(tport, count);
1306 if (s->active_rx == s->cookie_rx[0]) {
1308 } else if (s->active_rx == s->cookie_rx[1]) {
1311 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
1316 dev_warn(port->dev, "Rx overrun: dropping %zu bytes\n",
1321 for (i = 0; i < room; i++)
1322 tty_insert_flip_char(tport, ((u8 *)sg_virt(&s->sg_rx[active]))[i],
1325 port->icount.rx += room;
1330 static void sci_dma_rx_complete(void *arg)
1332 struct sci_port *s = arg;
1333 struct uart_port *port = &s->port;
1334 unsigned long flags;
1337 dev_dbg(port->dev, "%s(%d) active #%d\n", __func__, port->line, s->active_rx);
1339 spin_lock_irqsave(&port->lock, flags);
1341 count = sci_dma_rx_push(s, s->buf_len_rx);
1343 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
1345 spin_unlock_irqrestore(&port->lock, flags);
1348 tty_flip_buffer_push(&port->state->port);
1350 schedule_work(&s->work_rx);
1353 static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
1355 struct dma_chan *chan = s->chan_rx;
1356 struct uart_port *port = &s->port;
1359 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1360 dma_release_channel(chan);
1361 if (sg_dma_address(&s->sg_rx[0]))
1362 dma_free_coherent(port->dev, s->buf_len_rx * 2,
1363 sg_virt(&s->sg_rx[0]), sg_dma_address(&s->sg_rx[0]));
1368 static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1370 struct dma_chan *chan = s->chan_tx;
1371 struct uart_port *port = &s->port;
1374 s->cookie_tx = -EINVAL;
1375 dma_release_channel(chan);
1380 static void sci_submit_rx(struct sci_port *s)
1382 struct dma_chan *chan = s->chan_rx;
1385 for (i = 0; i < 2; i++) {
1386 struct scatterlist *sg = &s->sg_rx[i];
1387 struct dma_async_tx_descriptor *desc;
1389 desc = dmaengine_prep_slave_sg(chan,
1390 sg, 1, DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
1393 s->desc_rx[i] = desc;
1394 desc->callback = sci_dma_rx_complete;
1395 desc->callback_param = s;
1396 s->cookie_rx[i] = desc->tx_submit(desc);
1399 if (!desc || s->cookie_rx[i] < 0) {
1401 async_tx_ack(s->desc_rx[0]);
1402 s->cookie_rx[0] = -EINVAL;
1406 s->cookie_rx[i] = -EINVAL;
1408 dev_warn(s->port.dev,
1409 "failed to re-start DMA, using PIO\n");
1410 sci_rx_dma_release(s, true);
1413 dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n", __func__,
1414 s->cookie_rx[i], i);
1417 s->active_rx = s->cookie_rx[0];
1419 dma_async_issue_pending(chan);
1422 static void work_fn_rx(struct work_struct *work)
1424 struct sci_port *s = container_of(work, struct sci_port, work_rx);
1425 struct uart_port *port = &s->port;
1426 struct dma_async_tx_descriptor *desc;
1429 if (s->active_rx == s->cookie_rx[0]) {
1431 } else if (s->active_rx == s->cookie_rx[1]) {
1434 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
1437 desc = s->desc_rx[new];
1439 if (dma_async_is_tx_complete(s->chan_rx, s->active_rx, NULL, NULL) !=
1441 /* Handle incomplete DMA receive */
1442 struct dma_chan *chan = s->chan_rx;
1443 struct shdma_desc *sh_desc = container_of(desc,
1444 struct shdma_desc, async_tx);
1445 unsigned long flags;
1448 chan->device->device_control(chan, DMA_TERMINATE_ALL, 0);
1449 dev_dbg(port->dev, "Read %zu bytes with cookie %d\n",
1450 sh_desc->partial, sh_desc->cookie);
1452 spin_lock_irqsave(&port->lock, flags);
1453 count = sci_dma_rx_push(s, sh_desc->partial);
1454 spin_unlock_irqrestore(&port->lock, flags);
1457 tty_flip_buffer_push(&port->state->port);
1464 s->cookie_rx[new] = desc->tx_submit(desc);
1465 if (s->cookie_rx[new] < 0) {
1466 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1467 sci_rx_dma_release(s, true);
1471 s->active_rx = s->cookie_rx[!new];
1473 dev_dbg(port->dev, "%s: cookie %d #%d, new active #%d\n", __func__,
1474 s->cookie_rx[new], new, s->active_rx);
1477 static void work_fn_tx(struct work_struct *work)
1479 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1480 struct dma_async_tx_descriptor *desc;
1481 struct dma_chan *chan = s->chan_tx;
1482 struct uart_port *port = &s->port;
1483 struct circ_buf *xmit = &port->state->xmit;
1484 struct scatterlist *sg = &s->sg_tx;
1488 * Port xmit buffer is already mapped, and it is one page... Just adjust
1489 * offsets and lengths. Since it is a circular buffer, we have to
1490 * transmit till the end, and then the rest. Take the port lock to get a
1491 * consistent xmit buffer state.
1493 spin_lock_irq(&port->lock);
1494 sg->offset = xmit->tail & (UART_XMIT_SIZE - 1);
1495 sg_dma_address(sg) = (sg_dma_address(sg) & ~(UART_XMIT_SIZE - 1)) +
1497 sg_dma_len(sg) = min((int)CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
1498 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
1499 spin_unlock_irq(&port->lock);
1501 BUG_ON(!sg_dma_len(sg));
1503 desc = dmaengine_prep_slave_sg(chan,
1504 sg, s->sg_len_tx, DMA_MEM_TO_DEV,
1505 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1508 sci_tx_dma_release(s, true);
1512 dma_sync_sg_for_device(port->dev, sg, 1, DMA_TO_DEVICE);
1514 spin_lock_irq(&port->lock);
1516 desc->callback = sci_dma_tx_complete;
1517 desc->callback_param = s;
1518 spin_unlock_irq(&port->lock);
1519 s->cookie_tx = desc->tx_submit(desc);
1520 if (s->cookie_tx < 0) {
1521 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1523 sci_tx_dma_release(s, true);
1527 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n", __func__,
1528 xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
1530 dma_async_issue_pending(chan);
1534 static void sci_start_tx(struct uart_port *port)
1536 struct sci_port *s = to_sci_port(port);
1537 unsigned short ctrl;
1539 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1540 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1541 u16 new, scr = serial_port_in(port, SCSCR);
1545 new = scr & ~0x8000;
1547 serial_port_out(port, SCSCR, new);
1550 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
1553 schedule_work(&s->work_tx);
1557 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1558 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
1559 ctrl = serial_port_in(port, SCSCR);
1560 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
1564 static void sci_stop_tx(struct uart_port *port)
1566 unsigned short ctrl;
1568 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
1569 ctrl = serial_port_in(port, SCSCR);
1571 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1576 serial_port_out(port, SCSCR, ctrl);
1579 static void sci_start_rx(struct uart_port *port)
1581 unsigned short ctrl;
1583 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
1585 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1588 serial_port_out(port, SCSCR, ctrl);
1591 static void sci_stop_rx(struct uart_port *port)
1593 unsigned short ctrl;
1595 ctrl = serial_port_in(port, SCSCR);
1597 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1600 ctrl &= ~port_rx_irq_mask(port);
1602 serial_port_out(port, SCSCR, ctrl);
1605 static void sci_enable_ms(struct uart_port *port)
1608 * Not supported by hardware, always a nop.
1612 static void sci_break_ctl(struct uart_port *port, int break_state)
1614 struct sci_port *s = to_sci_port(port);
1615 struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
1616 unsigned short scscr, scsptr;
1618 /* check wheter the port has SCSPTR */
1621 * Not supported by hardware. Most parts couple break and rx
1622 * interrupts together, with break detection always enabled.
1627 scsptr = serial_port_in(port, SCSPTR);
1628 scscr = serial_port_in(port, SCSCR);
1630 if (break_state == -1) {
1631 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
1634 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
1638 serial_port_out(port, SCSPTR, scsptr);
1639 serial_port_out(port, SCSCR, scscr);
1642 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1643 static bool filter(struct dma_chan *chan, void *slave)
1645 struct sh_dmae_slave *param = slave;
1647 dev_dbg(chan->device->dev, "%s: slave ID %d\n", __func__,
1648 param->shdma_slave.slave_id);
1650 chan->private = ¶m->shdma_slave;
1654 static void rx_timer_fn(unsigned long arg)
1656 struct sci_port *s = (struct sci_port *)arg;
1657 struct uart_port *port = &s->port;
1658 u16 scr = serial_port_in(port, SCSCR);
1660 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1662 enable_irq(s->cfg->irqs[1]);
1664 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
1665 dev_dbg(port->dev, "DMA Rx timed out\n");
1666 schedule_work(&s->work_rx);
1669 static void sci_request_dma(struct uart_port *port)
1671 struct sci_port *s = to_sci_port(port);
1672 struct sh_dmae_slave *param;
1673 struct dma_chan *chan;
1674 dma_cap_mask_t mask;
1677 dev_dbg(port->dev, "%s: port %d\n", __func__,
1680 if (s->cfg->dma_slave_tx <= 0 || s->cfg->dma_slave_rx <= 0)
1684 dma_cap_set(DMA_SLAVE, mask);
1686 param = &s->param_tx;
1688 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_TX */
1689 param->shdma_slave.slave_id = s->cfg->dma_slave_tx;
1691 s->cookie_tx = -EINVAL;
1692 chan = dma_request_channel(mask, filter, param);
1693 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1696 sg_init_table(&s->sg_tx, 1);
1697 /* UART circular tx buffer is an aligned page. */
1698 BUG_ON((uintptr_t)port->state->xmit.buf & ~PAGE_MASK);
1699 sg_set_page(&s->sg_tx, virt_to_page(port->state->xmit.buf),
1701 (uintptr_t)port->state->xmit.buf & ~PAGE_MASK);
1702 nent = dma_map_sg(port->dev, &s->sg_tx, 1, DMA_TO_DEVICE);
1704 sci_tx_dma_release(s, false);
1706 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
1707 sg_dma_len(&s->sg_tx), port->state->xmit.buf,
1708 &sg_dma_address(&s->sg_tx));
1710 s->sg_len_tx = nent;
1712 INIT_WORK(&s->work_tx, work_fn_tx);
1715 param = &s->param_rx;
1717 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_RX */
1718 param->shdma_slave.slave_id = s->cfg->dma_slave_rx;
1720 chan = dma_request_channel(mask, filter, param);
1721 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1729 s->buf_len_rx = 2 * max(16, (int)port->fifosize);
1730 buf[0] = dma_alloc_coherent(port->dev, s->buf_len_rx * 2,
1731 &dma[0], GFP_KERNEL);
1735 "failed to allocate dma buffer, using PIO\n");
1736 sci_rx_dma_release(s, true);
1740 buf[1] = buf[0] + s->buf_len_rx;
1741 dma[1] = dma[0] + s->buf_len_rx;
1743 for (i = 0; i < 2; i++) {
1744 struct scatterlist *sg = &s->sg_rx[i];
1746 sg_init_table(sg, 1);
1747 sg_set_page(sg, virt_to_page(buf[i]), s->buf_len_rx,
1748 (uintptr_t)buf[i] & ~PAGE_MASK);
1749 sg_dma_address(sg) = dma[i];
1752 INIT_WORK(&s->work_rx, work_fn_rx);
1753 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1759 static void sci_free_dma(struct uart_port *port)
1761 struct sci_port *s = to_sci_port(port);
1764 sci_tx_dma_release(s, false);
1766 sci_rx_dma_release(s, false);
1769 static inline void sci_request_dma(struct uart_port *port)
1773 static inline void sci_free_dma(struct uart_port *port)
1778 static int sci_startup(struct uart_port *port)
1780 struct sci_port *s = to_sci_port(port);
1781 unsigned long flags;
1784 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1786 ret = sci_request_irq(s);
1787 if (unlikely(ret < 0))
1790 sci_request_dma(port);
1792 spin_lock_irqsave(&port->lock, flags);
1795 spin_unlock_irqrestore(&port->lock, flags);
1800 static void sci_shutdown(struct uart_port *port)
1802 struct sci_port *s = to_sci_port(port);
1803 unsigned long flags;
1805 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1807 spin_lock_irqsave(&port->lock, flags);
1810 spin_unlock_irqrestore(&port->lock, flags);
1816 static unsigned int sci_scbrr_calc(unsigned int algo_id, unsigned int bps,
1821 return ((freq + 16 * bps) / (16 * bps) - 1);
1823 return ((freq + 16 * bps) / (32 * bps) - 1);
1825 return (((freq * 2) + 16 * bps) / (16 * bps) - 1);
1827 return (((freq * 2) + 16 * bps) / (32 * bps) - 1);
1829 return (((freq * 1000 / 32) / bps) - 1);
1832 /* Warn, but use a safe default */
1835 return ((freq + 16 * bps) / (32 * bps) - 1);
1838 /* calculate sample rate, BRR, and clock select for HSCIF */
1839 static void sci_baud_calc_hscif(unsigned int bps, unsigned long freq,
1840 int *brr, unsigned int *srr,
1844 int min_err = 1000; /* 100% */
1846 /* Find the combination of sample rate and clock select with the
1847 smallest deviation from the desired baud rate. */
1848 for (sr = 8; sr <= 32; sr++) {
1849 for (c = 0; c <= 3; c++) {
1850 /* integerized formulas from HSCIF documentation */
1851 br = freq / (sr * (1 << (2 * c + 1)) * bps) - 1;
1852 if (br < 0 || br > 255)
1854 err = freq / ((br + 1) * bps * sr *
1855 (1 << (2 * c + 1)) / 1000) - 1000;
1856 if (min_err > err) {
1865 if (min_err == 1000) {
1874 static void sci_reset(struct uart_port *port)
1876 struct plat_sci_reg *reg;
1877 unsigned int status;
1880 status = serial_port_in(port, SCxSR);
1881 } while (!(status & SCxSR_TEND(port)));
1883 serial_port_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1885 reg = sci_getreg(port, SCFCR);
1887 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
1890 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1891 struct ktermios *old)
1893 struct sci_port *s = to_sci_port(port);
1894 struct plat_sci_reg *reg;
1895 unsigned int baud, smr_val, max_baud, cks = 0;
1897 unsigned int srr = 15;
1900 * earlyprintk comes here early on with port->uartclk set to zero.
1901 * the clock framework is not up and running at this point so here
1902 * we assume that 115200 is the maximum baud rate. please note that
1903 * the baud rate is not programmed during earlyprintk - it is assumed
1904 * that the previous boot loader has enabled required clocks and
1905 * setup the baud rate generator hardware for us already.
1907 max_baud = port->uartclk ? port->uartclk / 16 : 115200;
1909 baud = uart_get_baud_rate(port, termios, old, 0, max_baud);
1910 if (likely(baud && port->uartclk)) {
1911 if (s->cfg->scbrr_algo_id == SCBRR_ALGO_6) {
1912 sci_baud_calc_hscif(baud, port->uartclk, &t, &srr,
1915 t = sci_scbrr_calc(s->cfg->scbrr_algo_id, baud,
1917 for (cks = 0; t >= 256 && cks <= 3; cks++)
1926 smr_val = serial_port_in(port, SCSMR) & 3;
1928 if ((termios->c_cflag & CSIZE) == CS7)
1930 if (termios->c_cflag & PARENB)
1932 if (termios->c_cflag & PARODD)
1934 if (termios->c_cflag & CSTOPB)
1937 uart_update_timeout(port, termios->c_cflag, baud);
1939 dev_dbg(port->dev, "%s: SMR %x, cks %x, t %x, SCSCR %x\n",
1940 __func__, smr_val, cks, t, s->cfg->scscr);
1943 serial_port_out(port, SCSMR, (smr_val & ~3) | cks);
1944 serial_port_out(port, SCBRR, t);
1945 reg = sci_getreg(port, HSSRR);
1947 serial_port_out(port, HSSRR, srr | HSCIF_SRE);
1948 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
1950 serial_port_out(port, SCSMR, smr_val);
1952 sci_init_pins(port, termios->c_cflag);
1954 reg = sci_getreg(port, SCFCR);
1956 unsigned short ctrl = serial_port_in(port, SCFCR);
1958 if (s->cfg->capabilities & SCIx_HAVE_RTSCTS) {
1959 if (termios->c_cflag & CRTSCTS)
1966 * As we've done a sci_reset() above, ensure we don't
1967 * interfere with the FIFOs while toggling MCE. As the
1968 * reset values could still be set, simply mask them out.
1970 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
1972 serial_port_out(port, SCFCR, ctrl);
1975 serial_port_out(port, SCSCR, s->cfg->scscr);
1977 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1979 * Calculate delay for 1.5 DMA buffers: see
1980 * drivers/serial/serial_core.c::uart_update_timeout(). With 10 bits
1981 * (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above function
1982 * calculates 1 jiffie for the data plus 5 jiffies for the "slop(e)."
1983 * Then below we calculate 3 jiffies (12ms) for 1.5 DMA buffers (3 FIFO
1984 * sizes), but it has been found out experimentally, that this is not
1985 * enough: the driver too often needlessly runs on a DMA timeout. 20ms
1986 * as a minimum seem to work perfectly.
1989 s->rx_timeout = (port->timeout - HZ / 50) * s->buf_len_rx * 3 /
1992 "DMA Rx t-out %ums, tty t-out %u jiffies\n",
1993 s->rx_timeout * 1000 / HZ, port->timeout);
1994 if (s->rx_timeout < msecs_to_jiffies(20))
1995 s->rx_timeout = msecs_to_jiffies(20);
1999 if ((termios->c_cflag & CREAD) != 0)
2002 sci_port_disable(s);
2005 static void sci_pm(struct uart_port *port, unsigned int state,
2006 unsigned int oldstate)
2008 struct sci_port *sci_port = to_sci_port(port);
2012 sci_port_disable(sci_port);
2015 sci_port_enable(sci_port);
2020 static const char *sci_type(struct uart_port *port)
2022 switch (port->type) {
2040 static inline unsigned long sci_port_size(struct uart_port *port)
2043 * Pick an arbitrary size that encapsulates all of the base
2044 * registers by default. This can be optimized later, or derived
2045 * from platform resource data at such a time that ports begin to
2046 * behave more erratically.
2048 if (port->type == PORT_HSCIF)
2054 static int sci_remap_port(struct uart_port *port)
2056 unsigned long size = sci_port_size(port);
2059 * Nothing to do if there's already an established membase.
2064 if (port->flags & UPF_IOREMAP) {
2065 port->membase = ioremap_nocache(port->mapbase, size);
2066 if (unlikely(!port->membase)) {
2067 dev_err(port->dev, "can't remap port#%d\n", port->line);
2072 * For the simple (and majority of) cases where we don't
2073 * need to do any remapping, just cast the cookie
2076 port->membase = (void __iomem *)port->mapbase;
2082 static void sci_release_port(struct uart_port *port)
2084 if (port->flags & UPF_IOREMAP) {
2085 iounmap(port->membase);
2086 port->membase = NULL;
2089 release_mem_region(port->mapbase, sci_port_size(port));
2092 static int sci_request_port(struct uart_port *port)
2094 unsigned long size = sci_port_size(port);
2095 struct resource *res;
2098 res = request_mem_region(port->mapbase, size, dev_name(port->dev));
2099 if (unlikely(res == NULL))
2102 ret = sci_remap_port(port);
2103 if (unlikely(ret != 0)) {
2104 release_resource(res);
2111 static void sci_config_port(struct uart_port *port, int flags)
2113 if (flags & UART_CONFIG_TYPE) {
2114 struct sci_port *sport = to_sci_port(port);
2116 port->type = sport->cfg->type;
2117 sci_request_port(port);
2121 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2123 struct sci_port *s = to_sci_port(port);
2125 if (ser->irq != s->cfg->irqs[SCIx_TXI_IRQ] || ser->irq > nr_irqs)
2127 if (ser->baud_base < 2400)
2128 /* No paper tape reader for Mitch.. */
2134 static struct uart_ops sci_uart_ops = {
2135 .tx_empty = sci_tx_empty,
2136 .set_mctrl = sci_set_mctrl,
2137 .get_mctrl = sci_get_mctrl,
2138 .start_tx = sci_start_tx,
2139 .stop_tx = sci_stop_tx,
2140 .stop_rx = sci_stop_rx,
2141 .enable_ms = sci_enable_ms,
2142 .break_ctl = sci_break_ctl,
2143 .startup = sci_startup,
2144 .shutdown = sci_shutdown,
2145 .set_termios = sci_set_termios,
2148 .release_port = sci_release_port,
2149 .request_port = sci_request_port,
2150 .config_port = sci_config_port,
2151 .verify_port = sci_verify_port,
2152 #ifdef CONFIG_CONSOLE_POLL
2153 .poll_get_char = sci_poll_get_char,
2154 .poll_put_char = sci_poll_put_char,
2158 static int sci_init_single(struct platform_device *dev,
2159 struct sci_port *sci_port,
2161 struct plat_sci_port *p)
2163 struct uart_port *port = &sci_port->port;
2168 port->ops = &sci_uart_ops;
2169 port->iotype = UPIO_MEM;
2174 port->fifosize = 256;
2177 port->fifosize = 128;
2180 port->fifosize = 64;
2183 port->fifosize = 16;
2190 if (p->regtype == SCIx_PROBE_REGTYPE) {
2191 ret = sci_probe_regmap(p);
2197 sci_port->iclk = clk_get(&dev->dev, "sci_ick");
2198 if (IS_ERR(sci_port->iclk)) {
2199 sci_port->iclk = clk_get(&dev->dev, "peripheral_clk");
2200 if (IS_ERR(sci_port->iclk)) {
2201 dev_err(&dev->dev, "can't get iclk\n");
2202 return PTR_ERR(sci_port->iclk);
2207 * The function clock is optional, ignore it if we can't
2210 sci_port->fclk = clk_get(&dev->dev, "sci_fck");
2211 if (IS_ERR(sci_port->fclk))
2212 sci_port->fclk = NULL;
2214 port->dev = &dev->dev;
2216 sci_init_gpios(sci_port);
2218 pm_runtime_enable(&dev->dev);
2221 sci_port->break_timer.data = (unsigned long)sci_port;
2222 sci_port->break_timer.function = sci_break_timer;
2223 init_timer(&sci_port->break_timer);
2226 * Establish some sensible defaults for the error detection.
2229 p->error_mask = (p->type == PORT_SCI) ?
2230 SCI_DEFAULT_ERROR_MASK : SCIF_DEFAULT_ERROR_MASK;
2233 * Establish sensible defaults for the overrun detection, unless
2234 * the part has explicitly disabled support for it.
2236 if (p->overrun_bit != SCIx_NOT_SUPPORTED) {
2237 if (p->type == PORT_SCI)
2239 else if (p->scbrr_algo_id == SCBRR_ALGO_4)
2245 * Make the error mask inclusive of overrun detection, if
2248 p->error_mask |= (1 << p->overrun_bit);
2251 port->mapbase = p->mapbase;
2252 port->type = p->type;
2253 port->flags = p->flags;
2254 port->regshift = p->regshift;
2257 * The UART port needs an IRQ value, so we peg this to the RX IRQ
2258 * for the multi-IRQ ports, which is where we are primarily
2259 * concerned with the shutdown path synchronization.
2261 * For the muxed case there's nothing more to do.
2263 port->irq = p->irqs[SCIx_RXI_IRQ];
2266 port->serial_in = sci_serial_in;
2267 port->serial_out = sci_serial_out;
2269 if (p->dma_slave_tx > 0 && p->dma_slave_rx > 0)
2270 dev_dbg(port->dev, "DMA tx %d, rx %d\n",
2271 p->dma_slave_tx, p->dma_slave_rx);
2276 static void sci_cleanup_single(struct sci_port *port)
2278 sci_free_gpios(port);
2280 clk_put(port->iclk);
2281 clk_put(port->fclk);
2283 pm_runtime_disable(port->port.dev);
2286 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2287 static void serial_console_putchar(struct uart_port *port, int ch)
2289 sci_poll_put_char(port, ch);
2293 * Print a string to the serial port trying not to disturb
2294 * any possible real use of the port...
2296 static void serial_console_write(struct console *co, const char *s,
2299 struct sci_port *sci_port = &sci_ports[co->index];
2300 struct uart_port *port = &sci_port->port;
2301 unsigned short bits, ctrl;
2302 unsigned long flags;
2305 local_irq_save(flags);
2308 else if (oops_in_progress)
2309 locked = spin_trylock(&port->lock);
2311 spin_lock(&port->lock);
2313 /* first save the SCSCR then disable the interrupts */
2314 ctrl = serial_port_in(port, SCSCR);
2315 serial_port_out(port, SCSCR, sci_port->cfg->scscr);
2317 uart_console_write(port, s, count, serial_console_putchar);
2319 /* wait until fifo is empty and last bit has been transmitted */
2320 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
2321 while ((serial_port_in(port, SCxSR) & bits) != bits)
2324 /* restore the SCSCR */
2325 serial_port_out(port, SCSCR, ctrl);
2328 spin_unlock(&port->lock);
2329 local_irq_restore(flags);
2332 static int serial_console_setup(struct console *co, char *options)
2334 struct sci_port *sci_port;
2335 struct uart_port *port;
2343 * Refuse to handle any bogus ports.
2345 if (co->index < 0 || co->index >= SCI_NPORTS)
2348 sci_port = &sci_ports[co->index];
2349 port = &sci_port->port;
2352 * Refuse to handle uninitialized ports.
2357 ret = sci_remap_port(port);
2358 if (unlikely(ret != 0))
2362 uart_parse_options(options, &baud, &parity, &bits, &flow);
2364 return uart_set_options(port, co, baud, parity, bits, flow);
2367 static struct console serial_console = {
2369 .device = uart_console_device,
2370 .write = serial_console_write,
2371 .setup = serial_console_setup,
2372 .flags = CON_PRINTBUFFER,
2374 .data = &sci_uart_driver,
2377 static struct console early_serial_console = {
2378 .name = "early_ttySC",
2379 .write = serial_console_write,
2380 .flags = CON_PRINTBUFFER,
2384 static char early_serial_buf[32];
2386 static int sci_probe_earlyprintk(struct platform_device *pdev)
2388 struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
2390 if (early_serial_console.data)
2393 early_serial_console.index = pdev->id;
2395 sci_init_single(NULL, &sci_ports[pdev->id], pdev->id, cfg);
2397 serial_console_setup(&early_serial_console, early_serial_buf);
2399 if (!strstr(early_serial_buf, "keep"))
2400 early_serial_console.flags |= CON_BOOT;
2402 register_console(&early_serial_console);
2406 #define SCI_CONSOLE (&serial_console)
2409 static inline int sci_probe_earlyprintk(struct platform_device *pdev)
2414 #define SCI_CONSOLE NULL
2416 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
2418 static char banner[] __initdata =
2419 KERN_INFO "SuperH (H)SCI(F) driver initialized\n";
2421 static struct uart_driver sci_uart_driver = {
2422 .owner = THIS_MODULE,
2423 .driver_name = "sci",
2424 .dev_name = "ttySC",
2426 .minor = SCI_MINOR_START,
2428 .cons = SCI_CONSOLE,
2431 static int sci_remove(struct platform_device *dev)
2433 struct sci_port *port = platform_get_drvdata(dev);
2435 cpufreq_unregister_notifier(&port->freq_transition,
2436 CPUFREQ_TRANSITION_NOTIFIER);
2438 uart_remove_one_port(&sci_uart_driver, &port->port);
2440 sci_cleanup_single(port);
2445 static int sci_probe_single(struct platform_device *dev,
2447 struct plat_sci_port *p,
2448 struct sci_port *sciport)
2453 if (unlikely(index >= SCI_NPORTS)) {
2454 dev_notice(&dev->dev, "Attempting to register port "
2455 "%d when only %d are available.\n",
2456 index+1, SCI_NPORTS);
2457 dev_notice(&dev->dev, "Consider bumping "
2458 "CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
2462 ret = sci_init_single(dev, sciport, index, p);
2466 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
2468 sci_cleanup_single(sciport);
2475 static int sci_probe(struct platform_device *dev)
2477 struct plat_sci_port *p = dev_get_platdata(&dev->dev);
2478 struct sci_port *sp = &sci_ports[dev->id];
2482 * If we've come here via earlyprintk initialization, head off to
2483 * the special early probe. We don't have sufficient device state
2484 * to make it beyond this yet.
2486 if (is_early_platform_device(dev))
2487 return sci_probe_earlyprintk(dev);
2489 platform_set_drvdata(dev, sp);
2491 ret = sci_probe_single(dev, dev->id, p, sp);
2495 sp->freq_transition.notifier_call = sci_notifier;
2497 ret = cpufreq_register_notifier(&sp->freq_transition,
2498 CPUFREQ_TRANSITION_NOTIFIER);
2499 if (unlikely(ret < 0)) {
2500 sci_cleanup_single(sp);
2504 #ifdef CONFIG_SH_STANDARD_BIOS
2505 sh_bios_gdb_detach();
2511 static int sci_suspend(struct device *dev)
2513 struct sci_port *sport = dev_get_drvdata(dev);
2516 uart_suspend_port(&sci_uart_driver, &sport->port);
2521 static int sci_resume(struct device *dev)
2523 struct sci_port *sport = dev_get_drvdata(dev);
2526 uart_resume_port(&sci_uart_driver, &sport->port);
2531 static const struct dev_pm_ops sci_dev_pm_ops = {
2532 .suspend = sci_suspend,
2533 .resume = sci_resume,
2536 static struct platform_driver sci_driver = {
2538 .remove = sci_remove,
2541 .owner = THIS_MODULE,
2542 .pm = &sci_dev_pm_ops,
2546 static int __init sci_init(void)
2552 ret = uart_register_driver(&sci_uart_driver);
2553 if (likely(ret == 0)) {
2554 ret = platform_driver_register(&sci_driver);
2556 uart_unregister_driver(&sci_uart_driver);
2562 static void __exit sci_exit(void)
2564 platform_driver_unregister(&sci_driver);
2565 uart_unregister_driver(&sci_uart_driver);
2568 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2569 early_platform_init_buffer("earlyprintk", &sci_driver,
2570 early_serial_buf, ARRAY_SIZE(early_serial_buf));
2572 module_init(sci_init);
2573 module_exit(sci_exit);
2575 MODULE_LICENSE("GPL");
2576 MODULE_ALIAS("platform:sh-sci");
2577 MODULE_AUTHOR("Paul Mundt");
2578 MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");