2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
4 * Copyright (C) 2002 - 2011 Paul Mundt
5 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
7 * based off of the old drivers/char/sh-sci.c by:
9 * Copyright (C) 1999, 2000 Niibe Yutaka
10 * Copyright (C) 2000 Sugioka Toshinobu
11 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
12 * Modified to support SecureEdge. David McCullough (2002)
13 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
14 * Removed SH7300 support (Jul 2007).
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
20 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
26 #include <linux/module.h>
27 #include <linux/errno.h>
28 #include <linux/timer.h>
29 #include <linux/interrupt.h>
30 #include <linux/tty.h>
31 #include <linux/tty_flip.h>
32 #include <linux/serial.h>
33 #include <linux/major.h>
34 #include <linux/string.h>
35 #include <linux/sysrq.h>
36 #include <linux/ioport.h>
38 #include <linux/init.h>
39 #include <linux/delay.h>
40 #include <linux/console.h>
41 #include <linux/platform_device.h>
42 #include <linux/serial_sci.h>
43 #include <linux/notifier.h>
44 #include <linux/pm_runtime.h>
45 #include <linux/cpufreq.h>
46 #include <linux/clk.h>
47 #include <linux/ctype.h>
48 #include <linux/err.h>
49 #include <linux/dmaengine.h>
50 #include <linux/dma-mapping.h>
51 #include <linux/scatterlist.h>
52 #include <linux/slab.h>
53 #include <linux/gpio.h>
56 #include <asm/sh_bios.h>
62 struct uart_port port;
64 /* Platform configuration */
65 struct plat_sci_port *cfg;
68 struct timer_list break_timer;
76 char *irqstr[SCIx_NR_IRQS];
77 char *gpiostr[SCIx_NR_FNS];
79 struct dma_chan *chan_tx;
80 struct dma_chan *chan_rx;
82 #ifdef CONFIG_SERIAL_SH_SCI_DMA
83 struct dma_async_tx_descriptor *desc_tx;
84 struct dma_async_tx_descriptor *desc_rx[2];
85 dma_cookie_t cookie_tx;
86 dma_cookie_t cookie_rx[2];
87 dma_cookie_t active_rx;
88 struct scatterlist sg_tx;
89 unsigned int sg_len_tx;
90 struct scatterlist sg_rx[2];
92 struct sh_dmae_slave param_tx;
93 struct sh_dmae_slave param_rx;
94 struct work_struct work_tx;
95 struct work_struct work_rx;
96 struct timer_list rx_timer;
97 unsigned int rx_timeout;
100 struct notifier_block freq_transition;
102 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
103 unsigned short saved_smr;
104 unsigned short saved_fcr;
105 unsigned char saved_brr;
109 /* Function prototypes */
110 static void sci_start_tx(struct uart_port *port);
111 static void sci_stop_tx(struct uart_port *port);
112 static void sci_start_rx(struct uart_port *port);
114 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
116 static struct sci_port sci_ports[SCI_NPORTS];
117 static struct uart_driver sci_uart_driver;
119 static inline struct sci_port *
120 to_sci_port(struct uart_port *uart)
122 return container_of(uart, struct sci_port, port);
125 struct plat_sci_reg {
129 /* Helper for invalidating specific entries of an inherited map. */
130 #define sci_reg_invalid { .offset = 0, .size = 0 }
132 static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
133 [SCIx_PROBE_REGTYPE] = {
134 [0 ... SCIx_NR_REGS - 1] = sci_reg_invalid,
138 * Common SCI definitions, dependent on the port's regshift
141 [SCIx_SCI_REGTYPE] = {
142 [SCSMR] = { 0x00, 8 },
143 [SCBRR] = { 0x01, 8 },
144 [SCSCR] = { 0x02, 8 },
145 [SCxTDR] = { 0x03, 8 },
146 [SCxSR] = { 0x04, 8 },
147 [SCxRDR] = { 0x05, 8 },
148 [SCFCR] = sci_reg_invalid,
149 [SCFDR] = sci_reg_invalid,
150 [SCTFDR] = sci_reg_invalid,
151 [SCRFDR] = sci_reg_invalid,
152 [SCSPTR] = sci_reg_invalid,
153 [SCLSR] = sci_reg_invalid,
157 * Common definitions for legacy IrDA ports, dependent on
160 [SCIx_IRDA_REGTYPE] = {
161 [SCSMR] = { 0x00, 8 },
162 [SCBRR] = { 0x01, 8 },
163 [SCSCR] = { 0x02, 8 },
164 [SCxTDR] = { 0x03, 8 },
165 [SCxSR] = { 0x04, 8 },
166 [SCxRDR] = { 0x05, 8 },
167 [SCFCR] = { 0x06, 8 },
168 [SCFDR] = { 0x07, 16 },
169 [SCTFDR] = sci_reg_invalid,
170 [SCRFDR] = sci_reg_invalid,
171 [SCSPTR] = sci_reg_invalid,
172 [SCLSR] = sci_reg_invalid,
176 * Common SCIFA definitions.
178 [SCIx_SCIFA_REGTYPE] = {
179 [SCSMR] = { 0x00, 16 },
180 [SCBRR] = { 0x04, 8 },
181 [SCSCR] = { 0x08, 16 },
182 [SCxTDR] = { 0x20, 8 },
183 [SCxSR] = { 0x14, 16 },
184 [SCxRDR] = { 0x24, 8 },
185 [SCFCR] = { 0x18, 16 },
186 [SCFDR] = { 0x1c, 16 },
187 [SCTFDR] = sci_reg_invalid,
188 [SCRFDR] = sci_reg_invalid,
189 [SCSPTR] = sci_reg_invalid,
190 [SCLSR] = sci_reg_invalid,
194 * Common SCIFB definitions.
196 [SCIx_SCIFB_REGTYPE] = {
197 [SCSMR] = { 0x00, 16 },
198 [SCBRR] = { 0x04, 8 },
199 [SCSCR] = { 0x08, 16 },
200 [SCxTDR] = { 0x40, 8 },
201 [SCxSR] = { 0x14, 16 },
202 [SCxRDR] = { 0x60, 8 },
203 [SCFCR] = { 0x18, 16 },
204 [SCFDR] = { 0x1c, 16 },
205 [SCTFDR] = sci_reg_invalid,
206 [SCRFDR] = sci_reg_invalid,
207 [SCSPTR] = sci_reg_invalid,
208 [SCLSR] = sci_reg_invalid,
212 * Common SH-2(A) SCIF definitions for ports with FIFO data
215 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
216 [SCSMR] = { 0x00, 16 },
217 [SCBRR] = { 0x04, 8 },
218 [SCSCR] = { 0x08, 16 },
219 [SCxTDR] = { 0x0c, 8 },
220 [SCxSR] = { 0x10, 16 },
221 [SCxRDR] = { 0x14, 8 },
222 [SCFCR] = { 0x18, 16 },
223 [SCFDR] = { 0x1c, 16 },
224 [SCTFDR] = sci_reg_invalid,
225 [SCRFDR] = sci_reg_invalid,
226 [SCSPTR] = { 0x20, 16 },
227 [SCLSR] = { 0x24, 16 },
231 * Common SH-3 SCIF definitions.
233 [SCIx_SH3_SCIF_REGTYPE] = {
234 [SCSMR] = { 0x00, 8 },
235 [SCBRR] = { 0x02, 8 },
236 [SCSCR] = { 0x04, 8 },
237 [SCxTDR] = { 0x06, 8 },
238 [SCxSR] = { 0x08, 16 },
239 [SCxRDR] = { 0x0a, 8 },
240 [SCFCR] = { 0x0c, 8 },
241 [SCFDR] = { 0x0e, 16 },
242 [SCTFDR] = sci_reg_invalid,
243 [SCRFDR] = sci_reg_invalid,
244 [SCSPTR] = sci_reg_invalid,
245 [SCLSR] = sci_reg_invalid,
249 * Common SH-4(A) SCIF(B) definitions.
251 [SCIx_SH4_SCIF_REGTYPE] = {
252 [SCSMR] = { 0x00, 16 },
253 [SCBRR] = { 0x04, 8 },
254 [SCSCR] = { 0x08, 16 },
255 [SCxTDR] = { 0x0c, 8 },
256 [SCxSR] = { 0x10, 16 },
257 [SCxRDR] = { 0x14, 8 },
258 [SCFCR] = { 0x18, 16 },
259 [SCFDR] = { 0x1c, 16 },
260 [SCTFDR] = sci_reg_invalid,
261 [SCRFDR] = sci_reg_invalid,
262 [SCSPTR] = { 0x20, 16 },
263 [SCLSR] = { 0x24, 16 },
267 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
270 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
271 [SCSMR] = { 0x00, 16 },
272 [SCBRR] = { 0x04, 8 },
273 [SCSCR] = { 0x08, 16 },
274 [SCxTDR] = { 0x0c, 8 },
275 [SCxSR] = { 0x10, 16 },
276 [SCxRDR] = { 0x14, 8 },
277 [SCFCR] = { 0x18, 16 },
278 [SCFDR] = { 0x1c, 16 },
279 [SCTFDR] = sci_reg_invalid,
280 [SCRFDR] = sci_reg_invalid,
281 [SCSPTR] = sci_reg_invalid,
282 [SCLSR] = { 0x24, 16 },
286 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
289 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
290 [SCSMR] = { 0x00, 16 },
291 [SCBRR] = { 0x04, 8 },
292 [SCSCR] = { 0x08, 16 },
293 [SCxTDR] = { 0x0c, 8 },
294 [SCxSR] = { 0x10, 16 },
295 [SCxRDR] = { 0x14, 8 },
296 [SCFCR] = { 0x18, 16 },
297 [SCFDR] = { 0x1c, 16 },
298 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
299 [SCRFDR] = { 0x20, 16 },
300 [SCSPTR] = { 0x24, 16 },
301 [SCLSR] = { 0x28, 16 },
305 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
308 [SCIx_SH7705_SCIF_REGTYPE] = {
309 [SCSMR] = { 0x00, 16 },
310 [SCBRR] = { 0x04, 8 },
311 [SCSCR] = { 0x08, 16 },
312 [SCxTDR] = { 0x20, 8 },
313 [SCxSR] = { 0x14, 16 },
314 [SCxRDR] = { 0x24, 8 },
315 [SCFCR] = { 0x18, 16 },
316 [SCFDR] = { 0x1c, 16 },
317 [SCTFDR] = sci_reg_invalid,
318 [SCRFDR] = sci_reg_invalid,
319 [SCSPTR] = sci_reg_invalid,
320 [SCLSR] = sci_reg_invalid,
324 #define sci_getreg(up, offset) (sci_regmap[to_sci_port(up)->cfg->regtype] + offset)
327 * The "offset" here is rather misleading, in that it refers to an enum
328 * value relative to the port mapping rather than the fixed offset
329 * itself, which needs to be manually retrieved from the platform's
330 * register map for the given port.
332 static unsigned int sci_serial_in(struct uart_port *p, int offset)
334 struct plat_sci_reg *reg = sci_getreg(p, offset);
337 return ioread8(p->membase + (reg->offset << p->regshift));
338 else if (reg->size == 16)
339 return ioread16(p->membase + (reg->offset << p->regshift));
341 WARN(1, "Invalid register access\n");
346 static void sci_serial_out(struct uart_port *p, int offset, int value)
348 struct plat_sci_reg *reg = sci_getreg(p, offset);
351 iowrite8(value, p->membase + (reg->offset << p->regshift));
352 else if (reg->size == 16)
353 iowrite16(value, p->membase + (reg->offset << p->regshift));
355 WARN(1, "Invalid register access\n");
358 static int sci_probe_regmap(struct plat_sci_port *cfg)
362 cfg->regtype = SCIx_SCI_REGTYPE;
365 cfg->regtype = SCIx_IRDA_REGTYPE;
368 cfg->regtype = SCIx_SCIFA_REGTYPE;
371 cfg->regtype = SCIx_SCIFB_REGTYPE;
375 * The SH-4 is a bit of a misnomer here, although that's
376 * where this particular port layout originated. This
377 * configuration (or some slight variation thereof)
378 * remains the dominant model for all SCIFs.
380 cfg->regtype = SCIx_SH4_SCIF_REGTYPE;
383 printk(KERN_ERR "Can't probe register map for given port\n");
390 static void sci_port_enable(struct sci_port *sci_port)
392 if (!sci_port->port.dev)
395 pm_runtime_get_sync(sci_port->port.dev);
397 clk_enable(sci_port->iclk);
398 sci_port->port.uartclk = clk_get_rate(sci_port->iclk);
399 clk_enable(sci_port->fclk);
402 static void sci_port_disable(struct sci_port *sci_port)
404 if (!sci_port->port.dev)
407 clk_disable(sci_port->fclk);
408 clk_disable(sci_port->iclk);
410 pm_runtime_put_sync(sci_port->port.dev);
413 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
415 #ifdef CONFIG_CONSOLE_POLL
416 static int sci_poll_get_char(struct uart_port *port)
418 unsigned short status;
422 status = serial_port_in(port, SCxSR);
423 if (status & SCxSR_ERRORS(port)) {
424 serial_port_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
430 if (!(status & SCxSR_RDxF(port)))
433 c = serial_port_in(port, SCxRDR);
436 serial_port_in(port, SCxSR);
437 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
443 static void sci_poll_put_char(struct uart_port *port, unsigned char c)
445 unsigned short status;
448 status = serial_port_in(port, SCxSR);
449 } while (!(status & SCxSR_TDxE(port)));
451 serial_port_out(port, SCxTDR, c);
452 serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
454 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
456 static void sci_init_pins(struct uart_port *port, unsigned int cflag)
458 struct sci_port *s = to_sci_port(port);
459 struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
462 * Use port-specific handler if provided.
464 if (s->cfg->ops && s->cfg->ops->init_pins) {
465 s->cfg->ops->init_pins(port, cflag);
470 * For the generic path SCSPTR is necessary. Bail out if that's
476 if ((s->cfg->capabilities & SCIx_HAVE_RTSCTS) &&
477 ((!(cflag & CRTSCTS)))) {
478 unsigned short status;
480 status = serial_port_in(port, SCSPTR);
481 status &= ~SCSPTR_CTSIO;
482 status |= SCSPTR_RTSIO;
483 serial_port_out(port, SCSPTR, status); /* Set RTS = 1 */
487 static int sci_txfill(struct uart_port *port)
489 struct plat_sci_reg *reg;
491 reg = sci_getreg(port, SCTFDR);
493 return serial_port_in(port, SCTFDR) & 0xff;
495 reg = sci_getreg(port, SCFDR);
497 return serial_port_in(port, SCFDR) >> 8;
499 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
502 static int sci_txroom(struct uart_port *port)
504 return port->fifosize - sci_txfill(port);
507 static int sci_rxfill(struct uart_port *port)
509 struct plat_sci_reg *reg;
511 reg = sci_getreg(port, SCRFDR);
513 return serial_port_in(port, SCRFDR) & 0xff;
515 reg = sci_getreg(port, SCFDR);
517 return serial_port_in(port, SCFDR) & ((port->fifosize << 1) - 1);
519 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
523 * SCI helper for checking the state of the muxed port/RXD pins.
525 static inline int sci_rxd_in(struct uart_port *port)
527 struct sci_port *s = to_sci_port(port);
529 if (s->cfg->port_reg <= 0)
532 return !!__raw_readb(s->cfg->port_reg);
535 /* ********************************************************************** *
536 * the interrupt related routines *
537 * ********************************************************************** */
539 static void sci_transmit_chars(struct uart_port *port)
541 struct circ_buf *xmit = &port->state->xmit;
542 unsigned int stopped = uart_tx_stopped(port);
543 unsigned short status;
547 status = serial_port_in(port, SCxSR);
548 if (!(status & SCxSR_TDxE(port))) {
549 ctrl = serial_port_in(port, SCSCR);
550 if (uart_circ_empty(xmit))
554 serial_port_out(port, SCSCR, ctrl);
558 count = sci_txroom(port);
566 } else if (!uart_circ_empty(xmit) && !stopped) {
567 c = xmit->buf[xmit->tail];
568 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
573 serial_port_out(port, SCxTDR, c);
576 } while (--count > 0);
578 serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
580 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
581 uart_write_wakeup(port);
582 if (uart_circ_empty(xmit)) {
585 ctrl = serial_port_in(port, SCSCR);
587 if (port->type != PORT_SCI) {
588 serial_port_in(port, SCxSR); /* Dummy read */
589 serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
593 serial_port_out(port, SCSCR, ctrl);
597 /* On SH3, SCIF may read end-of-break as a space->mark char */
598 #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
600 static void sci_receive_chars(struct uart_port *port)
602 struct sci_port *sci_port = to_sci_port(port);
603 struct tty_struct *tty = port->state->port.tty;
604 int i, count, copied = 0;
605 unsigned short status;
608 status = serial_port_in(port, SCxSR);
609 if (!(status & SCxSR_RDxF(port)))
613 /* Don't copy more bytes than there is room for in the buffer */
614 count = tty_buffer_request_room(tty, sci_rxfill(port));
616 /* If for any reason we can't copy more data, we're done! */
620 if (port->type == PORT_SCI) {
621 char c = serial_port_in(port, SCxRDR);
622 if (uart_handle_sysrq_char(port, c) ||
623 sci_port->break_flag)
626 tty_insert_flip_char(tty, c, TTY_NORMAL);
628 for (i = 0; i < count; i++) {
629 char c = serial_port_in(port, SCxRDR);
631 status = serial_port_in(port, SCxSR);
632 #if defined(CONFIG_CPU_SH3)
633 /* Skip "chars" during break */
634 if (sci_port->break_flag) {
636 (status & SCxSR_FER(port))) {
641 /* Nonzero => end-of-break */
642 dev_dbg(port->dev, "debounce<%02x>\n", c);
643 sci_port->break_flag = 0;
650 #endif /* CONFIG_CPU_SH3 */
651 if (uart_handle_sysrq_char(port, c)) {
656 /* Store data and status */
657 if (status & SCxSR_FER(port)) {
659 port->icount.frame++;
660 dev_notice(port->dev, "frame error\n");
661 } else if (status & SCxSR_PER(port)) {
663 port->icount.parity++;
664 dev_notice(port->dev, "parity error\n");
668 tty_insert_flip_char(tty, c, flag);
672 serial_port_in(port, SCxSR); /* dummy read */
673 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
676 port->icount.rx += count;
680 /* Tell the rest of the system the news. New characters! */
681 tty_flip_buffer_push(tty);
683 serial_port_in(port, SCxSR); /* dummy read */
684 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
688 #define SCI_BREAK_JIFFIES (HZ/20)
691 * The sci generates interrupts during the break,
692 * 1 per millisecond or so during the break period, for 9600 baud.
693 * So dont bother disabling interrupts.
694 * But dont want more than 1 break event.
695 * Use a kernel timer to periodically poll the rx line until
696 * the break is finished.
698 static inline void sci_schedule_break_timer(struct sci_port *port)
700 mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES);
703 /* Ensure that two consecutive samples find the break over. */
704 static void sci_break_timer(unsigned long data)
706 struct sci_port *port = (struct sci_port *)data;
708 sci_port_enable(port);
710 if (sci_rxd_in(&port->port) == 0) {
711 port->break_flag = 1;
712 sci_schedule_break_timer(port);
713 } else if (port->break_flag == 1) {
715 port->break_flag = 2;
716 sci_schedule_break_timer(port);
718 port->break_flag = 0;
720 sci_port_disable(port);
723 static int sci_handle_errors(struct uart_port *port)
726 unsigned short status = serial_port_in(port, SCxSR);
727 struct tty_struct *tty = port->state->port.tty;
728 struct sci_port *s = to_sci_port(port);
731 * Handle overruns, if supported.
733 if (s->cfg->overrun_bit != SCIx_NOT_SUPPORTED) {
734 if (status & (1 << s->cfg->overrun_bit)) {
735 port->icount.overrun++;
738 if (tty_insert_flip_char(tty, 0, TTY_OVERRUN))
741 dev_notice(port->dev, "overrun error");
745 if (status & SCxSR_FER(port)) {
746 if (sci_rxd_in(port) == 0) {
747 /* Notify of BREAK */
748 struct sci_port *sci_port = to_sci_port(port);
750 if (!sci_port->break_flag) {
753 sci_port->break_flag = 1;
754 sci_schedule_break_timer(sci_port);
756 /* Do sysrq handling. */
757 if (uart_handle_break(port))
760 dev_dbg(port->dev, "BREAK detected\n");
762 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
768 port->icount.frame++;
770 if (tty_insert_flip_char(tty, 0, TTY_FRAME))
773 dev_notice(port->dev, "frame error\n");
777 if (status & SCxSR_PER(port)) {
779 port->icount.parity++;
781 if (tty_insert_flip_char(tty, 0, TTY_PARITY))
784 dev_notice(port->dev, "parity error");
788 tty_flip_buffer_push(tty);
793 static int sci_handle_fifo_overrun(struct uart_port *port)
795 struct tty_struct *tty = port->state->port.tty;
796 struct sci_port *s = to_sci_port(port);
797 struct plat_sci_reg *reg;
800 reg = sci_getreg(port, SCLSR);
804 if ((serial_port_in(port, SCLSR) & (1 << s->cfg->overrun_bit))) {
805 serial_port_out(port, SCLSR, 0);
807 port->icount.overrun++;
809 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
810 tty_flip_buffer_push(tty);
812 dev_notice(port->dev, "overrun error\n");
819 static int sci_handle_breaks(struct uart_port *port)
822 unsigned short status = serial_port_in(port, SCxSR);
823 struct tty_struct *tty = port->state->port.tty;
824 struct sci_port *s = to_sci_port(port);
826 if (uart_handle_break(port))
829 if (!s->break_flag && status & SCxSR_BRK(port)) {
830 #if defined(CONFIG_CPU_SH3)
837 /* Notify of BREAK */
838 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
841 dev_dbg(port->dev, "BREAK detected\n");
845 tty_flip_buffer_push(tty);
847 copied += sci_handle_fifo_overrun(port);
852 static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
854 #ifdef CONFIG_SERIAL_SH_SCI_DMA
855 struct uart_port *port = ptr;
856 struct sci_port *s = to_sci_port(port);
859 u16 scr = serial_port_in(port, SCSCR);
860 u16 ssr = serial_port_in(port, SCxSR);
862 /* Disable future Rx interrupts */
863 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
864 disable_irq_nosync(irq);
869 serial_port_out(port, SCSCR, scr);
870 /* Clear current interrupt */
871 serial_port_out(port, SCxSR, ssr & ~(1 | SCxSR_RDxF(port)));
872 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
873 jiffies, s->rx_timeout);
874 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
880 /* I think sci_receive_chars has to be called irrespective
881 * of whether the I_IXOFF is set, otherwise, how is the interrupt
884 sci_receive_chars(ptr);
889 static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
891 struct uart_port *port = ptr;
894 spin_lock_irqsave(&port->lock, flags);
895 sci_transmit_chars(port);
896 spin_unlock_irqrestore(&port->lock, flags);
901 static irqreturn_t sci_er_interrupt(int irq, void *ptr)
903 struct uart_port *port = ptr;
906 if (port->type == PORT_SCI) {
907 if (sci_handle_errors(port)) {
908 /* discard character in rx buffer */
909 serial_port_in(port, SCxSR);
910 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
913 sci_handle_fifo_overrun(port);
914 sci_rx_interrupt(irq, ptr);
917 serial_port_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
919 /* Kick the transmission */
920 sci_tx_interrupt(irq, ptr);
925 static irqreturn_t sci_br_interrupt(int irq, void *ptr)
927 struct uart_port *port = ptr;
930 sci_handle_breaks(port);
931 serial_port_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
936 static inline unsigned long port_rx_irq_mask(struct uart_port *port)
939 * Not all ports (such as SCIFA) will support REIE. Rather than
940 * special-casing the port type, we check the port initialization
941 * IRQ enable mask to see whether the IRQ is desired at all. If
942 * it's unset, it's logically inferred that there's no point in
945 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
948 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
950 unsigned short ssr_status, scr_status, err_enabled;
951 struct uart_port *port = ptr;
952 struct sci_port *s = to_sci_port(port);
953 irqreturn_t ret = IRQ_NONE;
955 ssr_status = serial_port_in(port, SCxSR);
956 scr_status = serial_port_in(port, SCSCR);
957 err_enabled = scr_status & port_rx_irq_mask(port);
960 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
962 ret = sci_tx_interrupt(irq, ptr);
965 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
968 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
969 (scr_status & SCSCR_RIE))
970 ret = sci_rx_interrupt(irq, ptr);
972 /* Error Interrupt */
973 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
974 ret = sci_er_interrupt(irq, ptr);
976 /* Break Interrupt */
977 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
978 ret = sci_br_interrupt(irq, ptr);
984 * Here we define a transition notifier so that we can update all of our
985 * ports' baud rate when the peripheral clock changes.
987 static int sci_notifier(struct notifier_block *self,
988 unsigned long phase, void *p)
990 struct sci_port *sci_port;
993 sci_port = container_of(self, struct sci_port, freq_transition);
995 if ((phase == CPUFREQ_POSTCHANGE) ||
996 (phase == CPUFREQ_RESUMECHANGE)) {
997 struct uart_port *port = &sci_port->port;
999 spin_lock_irqsave(&port->lock, flags);
1000 port->uartclk = clk_get_rate(sci_port->iclk);
1001 spin_unlock_irqrestore(&port->lock, flags);
1007 static struct sci_irq_desc {
1009 irq_handler_t handler;
1010 } sci_irq_desc[] = {
1012 * Split out handlers, the default case.
1016 .handler = sci_er_interrupt,
1021 .handler = sci_rx_interrupt,
1026 .handler = sci_tx_interrupt,
1031 .handler = sci_br_interrupt,
1035 * Special muxed handler.
1039 .handler = sci_mpxed_interrupt,
1043 static int sci_request_irq(struct sci_port *port)
1045 struct uart_port *up = &port->port;
1048 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1049 struct sci_irq_desc *desc;
1052 if (SCIx_IRQ_IS_MUXED(port)) {
1056 irq = port->cfg->irqs[i];
1058 desc = sci_irq_desc + i;
1059 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1060 dev_name(up->dev), desc->desc);
1061 if (!port->irqstr[j]) {
1062 dev_err(up->dev, "Failed to allocate %s IRQ string\n",
1067 ret = request_irq(irq, desc->handler, up->irqflags,
1068 port->irqstr[j], port);
1069 if (unlikely(ret)) {
1070 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1079 free_irq(port->cfg->irqs[i], port);
1083 kfree(port->irqstr[j]);
1088 static void sci_free_irq(struct sci_port *port)
1093 * Intentionally in reverse order so we iterate over the muxed
1096 for (i = 0; i < SCIx_NR_IRQS; i++) {
1097 free_irq(port->cfg->irqs[i], port);
1098 kfree(port->irqstr[i]);
1100 if (SCIx_IRQ_IS_MUXED(port)) {
1101 /* If there's only one IRQ, we're done. */
1107 static const char *sci_gpio_names[SCIx_NR_FNS] = {
1108 "sck", "rxd", "txd", "cts", "rts",
1111 static const char *sci_gpio_str(unsigned int index)
1113 return sci_gpio_names[index];
1116 static void __devinit sci_init_gpios(struct sci_port *port)
1118 struct uart_port *up = &port->port;
1124 for (i = 0; i < SCIx_NR_FNS; i++) {
1128 if (!port->cfg->gpios[i])
1131 desc = sci_gpio_str(i);
1133 port->gpiostr[i] = kasprintf(GFP_KERNEL, "%s:%s",
1134 dev_name(up->dev), desc);
1137 * If we've failed the allocation, we can still continue
1138 * on with a NULL string.
1140 if (!port->gpiostr[i])
1141 dev_notice(up->dev, "%s string allocation failure\n",
1144 ret = gpio_request(port->cfg->gpios[i], port->gpiostr[i]);
1145 if (unlikely(ret != 0)) {
1146 dev_notice(up->dev, "failed %s gpio request\n", desc);
1149 * If we can't get the GPIO for whatever reason,
1150 * no point in keeping the verbose string around.
1152 kfree(port->gpiostr[i]);
1157 static void sci_free_gpios(struct sci_port *port)
1161 for (i = 0; i < SCIx_NR_FNS; i++)
1162 if (port->cfg->gpios[i]) {
1163 gpio_free(port->cfg->gpios[i]);
1164 kfree(port->gpiostr[i]);
1168 static unsigned int sci_tx_empty(struct uart_port *port)
1170 unsigned short status = serial_port_in(port, SCxSR);
1171 unsigned short in_tx_fifo = sci_txfill(port);
1173 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1177 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
1178 * CTS/RTS is supported in hardware by at least one port and controlled
1179 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
1180 * handled via the ->init_pins() op, which is a bit of a one-way street,
1181 * lacking any ability to defer pin control -- this will later be
1182 * converted over to the GPIO framework).
1184 * Other modes (such as loopback) are supported generically on certain
1185 * port types, but not others. For these it's sufficient to test for the
1186 * existence of the support register and simply ignore the port type.
1188 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1190 if (mctrl & TIOCM_LOOP) {
1191 struct plat_sci_reg *reg;
1194 * Standard loopback mode for SCFCR ports.
1196 reg = sci_getreg(port, SCFCR);
1198 serial_port_out(port, SCFCR, serial_port_in(port, SCFCR) | 1);
1202 static unsigned int sci_get_mctrl(struct uart_port *port)
1205 * CTS/RTS is handled in hardware when supported, while nothing
1206 * else is wired up. Keep it simple and simply assert DSR/CAR.
1208 return TIOCM_DSR | TIOCM_CAR;
1211 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1212 static void sci_dma_tx_complete(void *arg)
1214 struct sci_port *s = arg;
1215 struct uart_port *port = &s->port;
1216 struct circ_buf *xmit = &port->state->xmit;
1217 unsigned long flags;
1219 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1221 spin_lock_irqsave(&port->lock, flags);
1223 xmit->tail += sg_dma_len(&s->sg_tx);
1224 xmit->tail &= UART_XMIT_SIZE - 1;
1226 port->icount.tx += sg_dma_len(&s->sg_tx);
1228 async_tx_ack(s->desc_tx);
1231 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1232 uart_write_wakeup(port);
1234 if (!uart_circ_empty(xmit)) {
1236 schedule_work(&s->work_tx);
1238 s->cookie_tx = -EINVAL;
1239 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1240 u16 ctrl = serial_port_in(port, SCSCR);
1241 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1245 spin_unlock_irqrestore(&port->lock, flags);
1248 /* Locking: called with port lock held */
1249 static int sci_dma_rx_push(struct sci_port *s, struct tty_struct *tty,
1252 struct uart_port *port = &s->port;
1253 int i, active, room;
1255 room = tty_buffer_request_room(tty, count);
1257 if (s->active_rx == s->cookie_rx[0]) {
1259 } else if (s->active_rx == s->cookie_rx[1]) {
1262 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
1267 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
1272 for (i = 0; i < room; i++)
1273 tty_insert_flip_char(tty, ((u8 *)sg_virt(&s->sg_rx[active]))[i],
1276 port->icount.rx += room;
1281 static void sci_dma_rx_complete(void *arg)
1283 struct sci_port *s = arg;
1284 struct uart_port *port = &s->port;
1285 struct tty_struct *tty = port->state->port.tty;
1286 unsigned long flags;
1289 dev_dbg(port->dev, "%s(%d) active #%d\n", __func__, port->line, s->active_rx);
1291 spin_lock_irqsave(&port->lock, flags);
1293 count = sci_dma_rx_push(s, tty, s->buf_len_rx);
1295 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
1297 spin_unlock_irqrestore(&port->lock, flags);
1300 tty_flip_buffer_push(tty);
1302 schedule_work(&s->work_rx);
1305 static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
1307 struct dma_chan *chan = s->chan_rx;
1308 struct uart_port *port = &s->port;
1311 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1312 dma_release_channel(chan);
1313 if (sg_dma_address(&s->sg_rx[0]))
1314 dma_free_coherent(port->dev, s->buf_len_rx * 2,
1315 sg_virt(&s->sg_rx[0]), sg_dma_address(&s->sg_rx[0]));
1320 static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1322 struct dma_chan *chan = s->chan_tx;
1323 struct uart_port *port = &s->port;
1326 s->cookie_tx = -EINVAL;
1327 dma_release_channel(chan);
1332 static void sci_submit_rx(struct sci_port *s)
1334 struct dma_chan *chan = s->chan_rx;
1337 for (i = 0; i < 2; i++) {
1338 struct scatterlist *sg = &s->sg_rx[i];
1339 struct dma_async_tx_descriptor *desc;
1341 desc = dmaengine_prep_slave_sg(chan,
1342 sg, 1, DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
1345 s->desc_rx[i] = desc;
1346 desc->callback = sci_dma_rx_complete;
1347 desc->callback_param = s;
1348 s->cookie_rx[i] = desc->tx_submit(desc);
1351 if (!desc || s->cookie_rx[i] < 0) {
1353 async_tx_ack(s->desc_rx[0]);
1354 s->cookie_rx[0] = -EINVAL;
1358 s->cookie_rx[i] = -EINVAL;
1360 dev_warn(s->port.dev,
1361 "failed to re-start DMA, using PIO\n");
1362 sci_rx_dma_release(s, true);
1365 dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n", __func__,
1366 s->cookie_rx[i], i);
1369 s->active_rx = s->cookie_rx[0];
1371 dma_async_issue_pending(chan);
1374 static void work_fn_rx(struct work_struct *work)
1376 struct sci_port *s = container_of(work, struct sci_port, work_rx);
1377 struct uart_port *port = &s->port;
1378 struct dma_async_tx_descriptor *desc;
1381 if (s->active_rx == s->cookie_rx[0]) {
1383 } else if (s->active_rx == s->cookie_rx[1]) {
1386 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
1389 desc = s->desc_rx[new];
1391 if (dma_async_is_tx_complete(s->chan_rx, s->active_rx, NULL, NULL) !=
1393 /* Handle incomplete DMA receive */
1394 struct tty_struct *tty = port->state->port.tty;
1395 struct dma_chan *chan = s->chan_rx;
1396 struct sh_desc *sh_desc = container_of(desc, struct sh_desc,
1398 unsigned long flags;
1401 chan->device->device_control(chan, DMA_TERMINATE_ALL, 0);
1402 dev_dbg(port->dev, "Read %u bytes with cookie %d\n",
1403 sh_desc->partial, sh_desc->cookie);
1405 spin_lock_irqsave(&port->lock, flags);
1406 count = sci_dma_rx_push(s, tty, sh_desc->partial);
1407 spin_unlock_irqrestore(&port->lock, flags);
1410 tty_flip_buffer_push(tty);
1417 s->cookie_rx[new] = desc->tx_submit(desc);
1418 if (s->cookie_rx[new] < 0) {
1419 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1420 sci_rx_dma_release(s, true);
1424 s->active_rx = s->cookie_rx[!new];
1426 dev_dbg(port->dev, "%s: cookie %d #%d, new active #%d\n", __func__,
1427 s->cookie_rx[new], new, s->active_rx);
1430 static void work_fn_tx(struct work_struct *work)
1432 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1433 struct dma_async_tx_descriptor *desc;
1434 struct dma_chan *chan = s->chan_tx;
1435 struct uart_port *port = &s->port;
1436 struct circ_buf *xmit = &port->state->xmit;
1437 struct scatterlist *sg = &s->sg_tx;
1441 * Port xmit buffer is already mapped, and it is one page... Just adjust
1442 * offsets and lengths. Since it is a circular buffer, we have to
1443 * transmit till the end, and then the rest. Take the port lock to get a
1444 * consistent xmit buffer state.
1446 spin_lock_irq(&port->lock);
1447 sg->offset = xmit->tail & (UART_XMIT_SIZE - 1);
1448 sg_dma_address(sg) = (sg_dma_address(sg) & ~(UART_XMIT_SIZE - 1)) +
1450 sg_dma_len(sg) = min((int)CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
1451 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
1452 spin_unlock_irq(&port->lock);
1454 BUG_ON(!sg_dma_len(sg));
1456 desc = dmaengine_prep_slave_sg(chan,
1457 sg, s->sg_len_tx, DMA_MEM_TO_DEV,
1458 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1461 sci_tx_dma_release(s, true);
1465 dma_sync_sg_for_device(port->dev, sg, 1, DMA_TO_DEVICE);
1467 spin_lock_irq(&port->lock);
1469 desc->callback = sci_dma_tx_complete;
1470 desc->callback_param = s;
1471 spin_unlock_irq(&port->lock);
1472 s->cookie_tx = desc->tx_submit(desc);
1473 if (s->cookie_tx < 0) {
1474 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1476 sci_tx_dma_release(s, true);
1480 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n", __func__,
1481 xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
1483 dma_async_issue_pending(chan);
1487 static void sci_start_tx(struct uart_port *port)
1489 struct sci_port *s = to_sci_port(port);
1490 unsigned short ctrl;
1492 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1493 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1494 u16 new, scr = serial_port_in(port, SCSCR);
1498 new = scr & ~0x8000;
1500 serial_port_out(port, SCSCR, new);
1503 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
1506 schedule_work(&s->work_tx);
1510 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1511 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
1512 ctrl = serial_port_in(port, SCSCR);
1513 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
1517 static void sci_stop_tx(struct uart_port *port)
1519 unsigned short ctrl;
1521 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
1522 ctrl = serial_port_in(port, SCSCR);
1524 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1529 serial_port_out(port, SCSCR, ctrl);
1532 static void sci_start_rx(struct uart_port *port)
1534 unsigned short ctrl;
1536 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
1538 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1541 serial_port_out(port, SCSCR, ctrl);
1544 static void sci_stop_rx(struct uart_port *port)
1546 unsigned short ctrl;
1548 ctrl = serial_port_in(port, SCSCR);
1550 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1553 ctrl &= ~port_rx_irq_mask(port);
1555 serial_port_out(port, SCSCR, ctrl);
1558 static void sci_enable_ms(struct uart_port *port)
1561 * Not supported by hardware, always a nop.
1565 static void sci_break_ctl(struct uart_port *port, int break_state)
1567 struct sci_port *s = to_sci_port(port);
1568 unsigned short scscr, scsptr;
1570 switch (s->cfg->regtype) {
1571 case SCIx_SH4_SCIF_REGTYPE:
1572 scsptr = serial_port_in(port, SCSPTR);
1573 scscr = serial_port_in(port, SCSCR);
1575 if (break_state == -1) {
1576 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
1579 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
1583 serial_port_out(port, SCSPTR, scsptr);
1584 serial_port_out(port, SCSCR, scscr);
1588 * Not supported by hardware. Most parts couple break and rx
1589 * interrupts together, with break detection always enabled.
1595 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1596 static bool filter(struct dma_chan *chan, void *slave)
1598 struct sh_dmae_slave *param = slave;
1600 dev_dbg(chan->device->dev, "%s: slave ID %d\n", __func__,
1603 chan->private = param;
1607 static void rx_timer_fn(unsigned long arg)
1609 struct sci_port *s = (struct sci_port *)arg;
1610 struct uart_port *port = &s->port;
1611 u16 scr = serial_port_in(port, SCSCR);
1613 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1615 enable_irq(s->cfg->irqs[1]);
1617 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
1618 dev_dbg(port->dev, "DMA Rx timed out\n");
1619 schedule_work(&s->work_rx);
1622 static void sci_request_dma(struct uart_port *port)
1624 struct sci_port *s = to_sci_port(port);
1625 struct sh_dmae_slave *param;
1626 struct dma_chan *chan;
1627 dma_cap_mask_t mask;
1630 dev_dbg(port->dev, "%s: port %d\n", __func__,
1633 if (s->cfg->dma_slave_tx <= 0 || s->cfg->dma_slave_rx <= 0)
1637 dma_cap_set(DMA_SLAVE, mask);
1639 param = &s->param_tx;
1641 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_TX */
1642 param->slave_id = s->cfg->dma_slave_tx;
1644 s->cookie_tx = -EINVAL;
1645 chan = dma_request_channel(mask, filter, param);
1646 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1649 sg_init_table(&s->sg_tx, 1);
1650 /* UART circular tx buffer is an aligned page. */
1651 BUG_ON((int)port->state->xmit.buf & ~PAGE_MASK);
1652 sg_set_page(&s->sg_tx, virt_to_page(port->state->xmit.buf),
1653 UART_XMIT_SIZE, (int)port->state->xmit.buf & ~PAGE_MASK);
1654 nent = dma_map_sg(port->dev, &s->sg_tx, 1, DMA_TO_DEVICE);
1656 sci_tx_dma_release(s, false);
1658 dev_dbg(port->dev, "%s: mapped %d@%p to %x\n", __func__,
1659 sg_dma_len(&s->sg_tx),
1660 port->state->xmit.buf, sg_dma_address(&s->sg_tx));
1662 s->sg_len_tx = nent;
1664 INIT_WORK(&s->work_tx, work_fn_tx);
1667 param = &s->param_rx;
1669 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_RX */
1670 param->slave_id = s->cfg->dma_slave_rx;
1672 chan = dma_request_channel(mask, filter, param);
1673 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1681 s->buf_len_rx = 2 * max(16, (int)port->fifosize);
1682 buf[0] = dma_alloc_coherent(port->dev, s->buf_len_rx * 2,
1683 &dma[0], GFP_KERNEL);
1687 "failed to allocate dma buffer, using PIO\n");
1688 sci_rx_dma_release(s, true);
1692 buf[1] = buf[0] + s->buf_len_rx;
1693 dma[1] = dma[0] + s->buf_len_rx;
1695 for (i = 0; i < 2; i++) {
1696 struct scatterlist *sg = &s->sg_rx[i];
1698 sg_init_table(sg, 1);
1699 sg_set_page(sg, virt_to_page(buf[i]), s->buf_len_rx,
1700 (int)buf[i] & ~PAGE_MASK);
1701 sg_dma_address(sg) = dma[i];
1704 INIT_WORK(&s->work_rx, work_fn_rx);
1705 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1711 static void sci_free_dma(struct uart_port *port)
1713 struct sci_port *s = to_sci_port(port);
1716 sci_tx_dma_release(s, false);
1718 sci_rx_dma_release(s, false);
1721 static inline void sci_request_dma(struct uart_port *port)
1725 static inline void sci_free_dma(struct uart_port *port)
1730 static int sci_startup(struct uart_port *port)
1732 struct sci_port *s = to_sci_port(port);
1735 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1737 pm_runtime_put_noidle(port->dev);
1741 ret = sci_request_irq(s);
1742 if (unlikely(ret < 0))
1745 sci_request_dma(port);
1753 static void sci_shutdown(struct uart_port *port)
1755 struct sci_port *s = to_sci_port(port);
1757 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1765 sci_port_disable(s);
1767 pm_runtime_get_noresume(port->dev);
1770 static unsigned int sci_scbrr_calc(unsigned int algo_id, unsigned int bps,
1775 return ((freq + 16 * bps) / (16 * bps) - 1);
1777 return ((freq + 16 * bps) / (32 * bps) - 1);
1779 return (((freq * 2) + 16 * bps) / (16 * bps) - 1);
1781 return (((freq * 2) + 16 * bps) / (32 * bps) - 1);
1783 return (((freq * 1000 / 32) / bps) - 1);
1786 /* Warn, but use a safe default */
1789 return ((freq + 16 * bps) / (32 * bps) - 1);
1792 static void sci_reset(struct uart_port *port)
1794 struct plat_sci_reg *reg;
1795 unsigned int status;
1798 status = serial_port_in(port, SCxSR);
1799 } while (!(status & SCxSR_TEND(port)));
1801 serial_port_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1803 reg = sci_getreg(port, SCFCR);
1805 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
1808 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1809 struct ktermios *old)
1811 struct sci_port *s = to_sci_port(port);
1812 struct plat_sci_reg *reg;
1813 unsigned int baud, smr_val, max_baud;
1817 * earlyprintk comes here early on with port->uartclk set to zero.
1818 * the clock framework is not up and running at this point so here
1819 * we assume that 115200 is the maximum baud rate. please note that
1820 * the baud rate is not programmed during earlyprintk - it is assumed
1821 * that the previous boot loader has enabled required clocks and
1822 * setup the baud rate generator hardware for us already.
1824 max_baud = port->uartclk ? port->uartclk / 16 : 115200;
1826 baud = uart_get_baud_rate(port, termios, old, 0, max_baud);
1827 if (likely(baud && port->uartclk))
1828 t = sci_scbrr_calc(s->cfg->scbrr_algo_id, baud, port->uartclk);
1834 smr_val = serial_port_in(port, SCSMR) & 3;
1836 if ((termios->c_cflag & CSIZE) == CS7)
1838 if (termios->c_cflag & PARENB)
1840 if (termios->c_cflag & PARODD)
1842 if (termios->c_cflag & CSTOPB)
1845 uart_update_timeout(port, termios->c_cflag, baud);
1847 serial_port_out(port, SCSMR, smr_val);
1849 dev_dbg(port->dev, "%s: SMR %x, t %x, SCSCR %x\n", __func__, smr_val, t,
1854 serial_port_out(port, SCSMR, (serial_port_in(port, SCSMR) & ~3) | 1);
1857 serial_port_out(port, SCSMR, serial_port_in(port, SCSMR) & ~3);
1859 serial_port_out(port, SCBRR, t);
1860 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
1863 sci_init_pins(port, termios->c_cflag);
1865 reg = sci_getreg(port, SCFCR);
1867 unsigned short ctrl = serial_port_in(port, SCFCR);
1869 if (s->cfg->capabilities & SCIx_HAVE_RTSCTS) {
1870 if (termios->c_cflag & CRTSCTS)
1877 * As we've done a sci_reset() above, ensure we don't
1878 * interfere with the FIFOs while toggling MCE. As the
1879 * reset values could still be set, simply mask them out.
1881 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
1883 serial_port_out(port, SCFCR, ctrl);
1886 serial_port_out(port, SCSCR, s->cfg->scscr);
1888 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1890 * Calculate delay for 1.5 DMA buffers: see
1891 * drivers/serial/serial_core.c::uart_update_timeout(). With 10 bits
1892 * (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above function
1893 * calculates 1 jiffie for the data plus 5 jiffies for the "slop(e)."
1894 * Then below we calculate 3 jiffies (12ms) for 1.5 DMA buffers (3 FIFO
1895 * sizes), but it has been found out experimentally, that this is not
1896 * enough: the driver too often needlessly runs on a DMA timeout. 20ms
1897 * as a minimum seem to work perfectly.
1900 s->rx_timeout = (port->timeout - HZ / 50) * s->buf_len_rx * 3 /
1903 "DMA Rx t-out %ums, tty t-out %u jiffies\n",
1904 s->rx_timeout * 1000 / HZ, port->timeout);
1905 if (s->rx_timeout < msecs_to_jiffies(20))
1906 s->rx_timeout = msecs_to_jiffies(20);
1910 if ((termios->c_cflag & CREAD) != 0)
1913 sci_port_disable(s);
1916 static const char *sci_type(struct uart_port *port)
1918 switch (port->type) {
1934 static inline unsigned long sci_port_size(struct uart_port *port)
1937 * Pick an arbitrary size that encapsulates all of the base
1938 * registers by default. This can be optimized later, or derived
1939 * from platform resource data at such a time that ports begin to
1940 * behave more erratically.
1945 static int sci_remap_port(struct uart_port *port)
1947 unsigned long size = sci_port_size(port);
1950 * Nothing to do if there's already an established membase.
1955 if (port->flags & UPF_IOREMAP) {
1956 port->membase = ioremap_nocache(port->mapbase, size);
1957 if (unlikely(!port->membase)) {
1958 dev_err(port->dev, "can't remap port#%d\n", port->line);
1963 * For the simple (and majority of) cases where we don't
1964 * need to do any remapping, just cast the cookie
1967 port->membase = (void __iomem *)port->mapbase;
1973 static void sci_release_port(struct uart_port *port)
1975 if (port->flags & UPF_IOREMAP) {
1976 iounmap(port->membase);
1977 port->membase = NULL;
1980 release_mem_region(port->mapbase, sci_port_size(port));
1983 static int sci_request_port(struct uart_port *port)
1985 unsigned long size = sci_port_size(port);
1986 struct resource *res;
1989 res = request_mem_region(port->mapbase, size, dev_name(port->dev));
1990 if (unlikely(res == NULL))
1993 ret = sci_remap_port(port);
1994 if (unlikely(ret != 0)) {
1995 release_resource(res);
2002 static void sci_config_port(struct uart_port *port, int flags)
2004 if (flags & UART_CONFIG_TYPE) {
2005 struct sci_port *sport = to_sci_port(port);
2007 port->type = sport->cfg->type;
2008 sci_request_port(port);
2012 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2014 struct sci_port *s = to_sci_port(port);
2016 if (ser->irq != s->cfg->irqs[SCIx_TXI_IRQ] || ser->irq > nr_irqs)
2018 if (ser->baud_base < 2400)
2019 /* No paper tape reader for Mitch.. */
2025 static struct uart_ops sci_uart_ops = {
2026 .tx_empty = sci_tx_empty,
2027 .set_mctrl = sci_set_mctrl,
2028 .get_mctrl = sci_get_mctrl,
2029 .start_tx = sci_start_tx,
2030 .stop_tx = sci_stop_tx,
2031 .stop_rx = sci_stop_rx,
2032 .enable_ms = sci_enable_ms,
2033 .break_ctl = sci_break_ctl,
2034 .startup = sci_startup,
2035 .shutdown = sci_shutdown,
2036 .set_termios = sci_set_termios,
2038 .release_port = sci_release_port,
2039 .request_port = sci_request_port,
2040 .config_port = sci_config_port,
2041 .verify_port = sci_verify_port,
2042 #ifdef CONFIG_CONSOLE_POLL
2043 .poll_get_char = sci_poll_get_char,
2044 .poll_put_char = sci_poll_put_char,
2048 static int __devinit sci_init_single(struct platform_device *dev,
2049 struct sci_port *sci_port,
2051 struct plat_sci_port *p)
2053 struct uart_port *port = &sci_port->port;
2058 port->ops = &sci_uart_ops;
2059 port->iotype = UPIO_MEM;
2064 port->fifosize = 256;
2067 port->fifosize = 64;
2070 port->fifosize = 16;
2077 if (p->regtype == SCIx_PROBE_REGTYPE) {
2078 ret = sci_probe_regmap(p);
2084 sci_port->iclk = clk_get(&dev->dev, "sci_ick");
2085 if (IS_ERR(sci_port->iclk)) {
2086 sci_port->iclk = clk_get(&dev->dev, "peripheral_clk");
2087 if (IS_ERR(sci_port->iclk)) {
2088 dev_err(&dev->dev, "can't get iclk\n");
2089 return PTR_ERR(sci_port->iclk);
2094 * The function clock is optional, ignore it if we can't
2097 sci_port->fclk = clk_get(&dev->dev, "sci_fck");
2098 if (IS_ERR(sci_port->fclk))
2099 sci_port->fclk = NULL;
2101 port->dev = &dev->dev;
2103 sci_init_gpios(sci_port);
2105 pm_runtime_irq_safe(&dev->dev);
2106 pm_runtime_get_noresume(&dev->dev);
2107 pm_runtime_enable(&dev->dev);
2110 sci_port->break_timer.data = (unsigned long)sci_port;
2111 sci_port->break_timer.function = sci_break_timer;
2112 init_timer(&sci_port->break_timer);
2115 * Establish some sensible defaults for the error detection.
2118 p->error_mask = (p->type == PORT_SCI) ?
2119 SCI_DEFAULT_ERROR_MASK : SCIF_DEFAULT_ERROR_MASK;
2122 * Establish sensible defaults for the overrun detection, unless
2123 * the part has explicitly disabled support for it.
2125 if (p->overrun_bit != SCIx_NOT_SUPPORTED) {
2126 if (p->type == PORT_SCI)
2128 else if (p->scbrr_algo_id == SCBRR_ALGO_4)
2134 * Make the error mask inclusive of overrun detection, if
2137 p->error_mask |= (1 << p->overrun_bit);
2140 port->mapbase = p->mapbase;
2141 port->type = p->type;
2142 port->flags = p->flags;
2143 port->regshift = p->regshift;
2146 * The UART port needs an IRQ value, so we peg this to the RX IRQ
2147 * for the multi-IRQ ports, which is where we are primarily
2148 * concerned with the shutdown path synchronization.
2150 * For the muxed case there's nothing more to do.
2152 port->irq = p->irqs[SCIx_RXI_IRQ];
2155 port->serial_in = sci_serial_in;
2156 port->serial_out = sci_serial_out;
2158 if (p->dma_slave_tx > 0 && p->dma_slave_rx > 0)
2159 dev_dbg(port->dev, "DMA tx %d, rx %d\n",
2160 p->dma_slave_tx, p->dma_slave_rx);
2165 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2166 static void serial_console_putchar(struct uart_port *port, int ch)
2168 sci_poll_put_char(port, ch);
2172 * Print a string to the serial port trying not to disturb
2173 * any possible real use of the port...
2175 static void serial_console_write(struct console *co, const char *s,
2178 struct sci_port *sci_port = &sci_ports[co->index];
2179 struct uart_port *port = &sci_port->port;
2180 unsigned short bits;
2182 sci_port_enable(sci_port);
2184 uart_console_write(port, s, count, serial_console_putchar);
2186 /* wait until fifo is empty and last bit has been transmitted */
2187 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
2188 while ((serial_port_in(port, SCxSR) & bits) != bits)
2191 sci_port_disable(sci_port);
2194 static int __devinit serial_console_setup(struct console *co, char *options)
2196 struct sci_port *sci_port;
2197 struct uart_port *port;
2205 * Refuse to handle any bogus ports.
2207 if (co->index < 0 || co->index >= SCI_NPORTS)
2210 sci_port = &sci_ports[co->index];
2211 port = &sci_port->port;
2214 * Refuse to handle uninitialized ports.
2219 ret = sci_remap_port(port);
2220 if (unlikely(ret != 0))
2223 sci_port_enable(sci_port);
2226 uart_parse_options(options, &baud, &parity, &bits, &flow);
2228 sci_port_disable(sci_port);
2230 return uart_set_options(port, co, baud, parity, bits, flow);
2233 static struct console serial_console = {
2235 .device = uart_console_device,
2236 .write = serial_console_write,
2237 .setup = serial_console_setup,
2238 .flags = CON_PRINTBUFFER,
2240 .data = &sci_uart_driver,
2243 static struct console early_serial_console = {
2244 .name = "early_ttySC",
2245 .write = serial_console_write,
2246 .flags = CON_PRINTBUFFER,
2250 static char early_serial_buf[32];
2252 static int __devinit sci_probe_earlyprintk(struct platform_device *pdev)
2254 struct plat_sci_port *cfg = pdev->dev.platform_data;
2256 if (early_serial_console.data)
2259 early_serial_console.index = pdev->id;
2261 sci_init_single(NULL, &sci_ports[pdev->id], pdev->id, cfg);
2263 serial_console_setup(&early_serial_console, early_serial_buf);
2265 if (!strstr(early_serial_buf, "keep"))
2266 early_serial_console.flags |= CON_BOOT;
2268 register_console(&early_serial_console);
2272 #define uart_console(port) ((port)->cons->index == (port)->line)
2274 static int sci_runtime_suspend(struct device *dev)
2276 struct sci_port *sci_port = dev_get_drvdata(dev);
2277 struct uart_port *port = &sci_port->port;
2279 if (uart_console(port)) {
2280 struct plat_sci_reg *reg;
2282 sci_port->saved_smr = serial_port_in(port, SCSMR);
2283 sci_port->saved_brr = serial_port_in(port, SCBRR);
2285 reg = sci_getreg(port, SCFCR);
2287 sci_port->saved_fcr = serial_port_in(port, SCFCR);
2289 sci_port->saved_fcr = 0;
2294 static int sci_runtime_resume(struct device *dev)
2296 struct sci_port *sci_port = dev_get_drvdata(dev);
2297 struct uart_port *port = &sci_port->port;
2299 if (uart_console(port)) {
2301 serial_port_out(port, SCSMR, sci_port->saved_smr);
2302 serial_port_out(port, SCBRR, sci_port->saved_brr);
2304 if (sci_port->saved_fcr)
2305 serial_port_out(port, SCFCR, sci_port->saved_fcr);
2307 serial_port_out(port, SCSCR, sci_port->cfg->scscr);
2312 #define SCI_CONSOLE (&serial_console)
2315 static inline int __devinit sci_probe_earlyprintk(struct platform_device *pdev)
2320 #define SCI_CONSOLE NULL
2321 #define sci_runtime_suspend NULL
2322 #define sci_runtime_resume NULL
2324 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
2326 static char banner[] __initdata =
2327 KERN_INFO "SuperH SCI(F) driver initialized\n";
2329 static struct uart_driver sci_uart_driver = {
2330 .owner = THIS_MODULE,
2331 .driver_name = "sci",
2332 .dev_name = "ttySC",
2334 .minor = SCI_MINOR_START,
2336 .cons = SCI_CONSOLE,
2339 static int sci_remove(struct platform_device *dev)
2341 struct sci_port *port = platform_get_drvdata(dev);
2343 cpufreq_unregister_notifier(&port->freq_transition,
2344 CPUFREQ_TRANSITION_NOTIFIER);
2346 sci_free_gpios(port);
2348 uart_remove_one_port(&sci_uart_driver, &port->port);
2350 clk_put(port->iclk);
2351 clk_put(port->fclk);
2353 pm_runtime_disable(&dev->dev);
2357 static int __devinit sci_probe_single(struct platform_device *dev,
2359 struct plat_sci_port *p,
2360 struct sci_port *sciport)
2365 if (unlikely(index >= SCI_NPORTS)) {
2366 dev_notice(&dev->dev, "Attempting to register port "
2367 "%d when only %d are available.\n",
2368 index+1, SCI_NPORTS);
2369 dev_notice(&dev->dev, "Consider bumping "
2370 "CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
2374 ret = sci_init_single(dev, sciport, index, p);
2378 return uart_add_one_port(&sci_uart_driver, &sciport->port);
2381 static int __devinit sci_probe(struct platform_device *dev)
2383 struct plat_sci_port *p = dev->dev.platform_data;
2384 struct sci_port *sp = &sci_ports[dev->id];
2388 * If we've come here via earlyprintk initialization, head off to
2389 * the special early probe. We don't have sufficient device state
2390 * to make it beyond this yet.
2392 if (is_early_platform_device(dev))
2393 return sci_probe_earlyprintk(dev);
2395 platform_set_drvdata(dev, sp);
2397 ret = sci_probe_single(dev, dev->id, p, sp);
2401 sp->freq_transition.notifier_call = sci_notifier;
2403 ret = cpufreq_register_notifier(&sp->freq_transition,
2404 CPUFREQ_TRANSITION_NOTIFIER);
2405 if (unlikely(ret < 0))
2408 #ifdef CONFIG_SH_STANDARD_BIOS
2409 sh_bios_gdb_detach();
2419 static int sci_suspend(struct device *dev)
2421 struct sci_port *sport = dev_get_drvdata(dev);
2424 uart_suspend_port(&sci_uart_driver, &sport->port);
2429 static int sci_resume(struct device *dev)
2431 struct sci_port *sport = dev_get_drvdata(dev);
2434 uart_resume_port(&sci_uart_driver, &sport->port);
2439 static const struct dev_pm_ops sci_dev_pm_ops = {
2440 .runtime_suspend = sci_runtime_suspend,
2441 .runtime_resume = sci_runtime_resume,
2442 .suspend = sci_suspend,
2443 .resume = sci_resume,
2446 static struct platform_driver sci_driver = {
2448 .remove = sci_remove,
2451 .owner = THIS_MODULE,
2452 .pm = &sci_dev_pm_ops,
2456 static int __init sci_init(void)
2462 ret = uart_register_driver(&sci_uart_driver);
2463 if (likely(ret == 0)) {
2464 ret = platform_driver_register(&sci_driver);
2466 uart_unregister_driver(&sci_uart_driver);
2472 static void __exit sci_exit(void)
2474 platform_driver_unregister(&sci_driver);
2475 uart_unregister_driver(&sci_uart_driver);
2478 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2479 early_platform_init_buffer("earlyprintk", &sci_driver,
2480 early_serial_buf, ARRAY_SIZE(early_serial_buf));
2482 module_init(sci_init);
2483 module_exit(sci_exit);
2485 MODULE_LICENSE("GPL");
2486 MODULE_ALIAS("platform:sh-sci");
2487 MODULE_AUTHOR("Paul Mundt");
2488 MODULE_DESCRIPTION("SuperH SCI(F) serial driver");