2 * NXP (Philips) SCC+++(SCN+++) serial driver
4 * Copyright (C) 2012 Alexander Shiyan <shc_work@mail.ru>
6 * Based on sc26xx.c, by Thomas Bogendörfer (tsbogend@alpha.franken.de)
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
14 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
18 #include <linux/err.h>
19 #include <linux/module.h>
20 #include <linux/device.h>
21 #include <linux/console.h>
22 #include <linux/serial_core.h>
23 #include <linux/serial.h>
25 #include <linux/tty.h>
26 #include <linux/tty_flip.h>
27 #include <linux/spinlock.h>
28 #include <linux/platform_device.h>
29 #include <linux/platform_data/serial-sccnxp.h>
31 #define SCCNXP_NAME "uart-sccnxp"
32 #define SCCNXP_MAJOR 204
33 #define SCCNXP_MINOR 205
35 #define SCCNXP_MR_REG (0x00)
36 # define MR0_BAUD_NORMAL (0 << 0)
37 # define MR0_BAUD_EXT1 (1 << 0)
38 # define MR0_BAUD_EXT2 (5 << 0)
39 # define MR0_FIFO (1 << 3)
40 # define MR0_TXLVL (1 << 4)
41 # define MR1_BITS_5 (0 << 0)
42 # define MR1_BITS_6 (1 << 0)
43 # define MR1_BITS_7 (2 << 0)
44 # define MR1_BITS_8 (3 << 0)
45 # define MR1_PAR_EVN (0 << 2)
46 # define MR1_PAR_ODD (1 << 2)
47 # define MR1_PAR_NO (4 << 2)
48 # define MR2_STOP1 (7 << 0)
49 # define MR2_STOP2 (0xf << 0)
50 #define SCCNXP_SR_REG (0x01)
51 #define SCCNXP_CSR_REG SCCNXP_SR_REG
52 # define SR_RXRDY (1 << 0)
53 # define SR_FULL (1 << 1)
54 # define SR_TXRDY (1 << 2)
55 # define SR_TXEMT (1 << 3)
56 # define SR_OVR (1 << 4)
57 # define SR_PE (1 << 5)
58 # define SR_FE (1 << 6)
59 # define SR_BRK (1 << 7)
60 #define SCCNXP_CR_REG (0x02)
61 # define CR_RX_ENABLE (1 << 0)
62 # define CR_RX_DISABLE (1 << 1)
63 # define CR_TX_ENABLE (1 << 2)
64 # define CR_TX_DISABLE (1 << 3)
65 # define CR_CMD_MRPTR1 (0x01 << 4)
66 # define CR_CMD_RX_RESET (0x02 << 4)
67 # define CR_CMD_TX_RESET (0x03 << 4)
68 # define CR_CMD_STATUS_RESET (0x04 << 4)
69 # define CR_CMD_BREAK_RESET (0x05 << 4)
70 # define CR_CMD_START_BREAK (0x06 << 4)
71 # define CR_CMD_STOP_BREAK (0x07 << 4)
72 # define CR_CMD_MRPTR0 (0x0b << 4)
73 #define SCCNXP_RHR_REG (0x03)
74 #define SCCNXP_THR_REG SCCNXP_RHR_REG
75 #define SCCNXP_IPCR_REG (0x04)
76 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG
77 # define ACR_BAUD0 (0 << 7)
78 # define ACR_BAUD1 (1 << 7)
79 # define ACR_TIMER_MODE (6 << 4)
80 #define SCCNXP_ISR_REG (0x05)
81 #define SCCNXP_IMR_REG SCCNXP_ISR_REG
82 # define IMR_TXRDY (1 << 0)
83 # define IMR_RXRDY (1 << 1)
84 # define ISR_TXRDY(x) (1 << ((x * 4) + 0))
85 # define ISR_RXRDY(x) (1 << ((x * 4) + 1))
86 #define SCCNXP_IPR_REG (0x0d)
87 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG
88 #define SCCNXP_SOP_REG (0x0e)
89 #define SCCNXP_ROP_REG (0x0f)
92 #define MCTRL_MASK(sig) (0xf << (sig))
93 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
94 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
96 /* Supported chip types */
98 SCCNXP_TYPE_SC2681 = 2681,
99 SCCNXP_TYPE_SC2691 = 2691,
100 SCCNXP_TYPE_SC2692 = 2692,
101 SCCNXP_TYPE_SC2891 = 2891,
102 SCCNXP_TYPE_SC2892 = 2892,
103 SCCNXP_TYPE_SC28202 = 28202,
104 SCCNXP_TYPE_SC68681 = 68681,
105 SCCNXP_TYPE_SC68692 = 68692,
109 struct uart_driver uart;
110 struct uart_port port[SCCNXP_MAX_UARTS];
111 bool opened[SCCNXP_MAX_UARTS];
121 #define SCCNXP_HAVE_IO 0x00000001
122 #define SCCNXP_HAVE_MR0 0x00000002
124 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
125 struct console console;
131 struct timer_list timer;
133 struct sccnxp_pdata pdata;
136 static inline u8 sccnxp_raw_read(void __iomem *base, u8 reg, u8 shift)
138 return readb(base + (reg << shift));
141 static inline void sccnxp_raw_write(void __iomem *base, u8 reg, u8 shift, u8 v)
143 writeb(v, base + (reg << shift));
146 static inline u8 sccnxp_read(struct uart_port *port, u8 reg)
148 struct sccnxp_port *s = dev_get_drvdata(port->dev);
150 return sccnxp_raw_read(port->membase, reg & s->addr_mask,
154 static inline void sccnxp_write(struct uart_port *port, u8 reg, u8 v)
156 struct sccnxp_port *s = dev_get_drvdata(port->dev);
158 sccnxp_raw_write(port->membase, reg & s->addr_mask, port->regshift, v);
161 static inline u8 sccnxp_port_read(struct uart_port *port, u8 reg)
163 return sccnxp_read(port, (port->line << 3) + reg);
166 static inline void sccnxp_port_write(struct uart_port *port, u8 reg, u8 v)
168 sccnxp_write(port, (port->line << 3) + reg, v);
171 static int sccnxp_update_best_err(int a, int b, int *besterr)
173 int err = abs(a - b);
175 if ((*besterr < 0) || (*besterr > err)) {
183 static const struct {
189 { 0, ACR_BAUD0, MR0_BAUD_NORMAL, 50, },
190 { 0, ACR_BAUD1, MR0_BAUD_NORMAL, 75, },
191 { 1, ACR_BAUD0, MR0_BAUD_NORMAL, 110, },
192 { 2, ACR_BAUD0, MR0_BAUD_NORMAL, 134, },
193 { 3, ACR_BAUD1, MR0_BAUD_NORMAL, 150, },
194 { 3, ACR_BAUD0, MR0_BAUD_NORMAL, 200, },
195 { 4, ACR_BAUD0, MR0_BAUD_NORMAL, 300, },
196 { 0, ACR_BAUD1, MR0_BAUD_EXT1, 450, },
197 { 1, ACR_BAUD0, MR0_BAUD_EXT2, 880, },
198 { 3, ACR_BAUD1, MR0_BAUD_EXT1, 900, },
199 { 5, ACR_BAUD0, MR0_BAUD_NORMAL, 600, },
200 { 7, ACR_BAUD0, MR0_BAUD_NORMAL, 1050, },
201 { 2, ACR_BAUD0, MR0_BAUD_EXT2, 1076, },
202 { 6, ACR_BAUD0, MR0_BAUD_NORMAL, 1200, },
203 { 10, ACR_BAUD1, MR0_BAUD_NORMAL, 1800, },
204 { 7, ACR_BAUD1, MR0_BAUD_NORMAL, 2000, },
205 { 8, ACR_BAUD0, MR0_BAUD_NORMAL, 2400, },
206 { 5, ACR_BAUD1, MR0_BAUD_EXT1, 3600, },
207 { 9, ACR_BAUD0, MR0_BAUD_NORMAL, 4800, },
208 { 10, ACR_BAUD0, MR0_BAUD_NORMAL, 7200, },
209 { 11, ACR_BAUD0, MR0_BAUD_NORMAL, 9600, },
210 { 8, ACR_BAUD0, MR0_BAUD_EXT1, 14400, },
211 { 12, ACR_BAUD1, MR0_BAUD_NORMAL, 19200, },
212 { 9, ACR_BAUD0, MR0_BAUD_EXT1, 28800, },
213 { 12, ACR_BAUD0, MR0_BAUD_NORMAL, 38400, },
214 { 11, ACR_BAUD0, MR0_BAUD_EXT1, 57600, },
215 { 12, ACR_BAUD1, MR0_BAUD_EXT1, 115200, },
216 { 12, ACR_BAUD0, MR0_BAUD_EXT1, 230400, },
220 static int sccnxp_set_baud(struct uart_port *port, int baud)
222 struct sccnxp_port *s = dev_get_drvdata(port->dev);
223 int div_std, tmp_baud, bestbaud = baud, besterr = -1;
224 u8 i, acr = 0, csr = 0, mr0 = 0;
226 /* Find best baud from table */
227 for (i = 0; baud_std[i].baud && besterr; i++) {
228 if (baud_std[i].mr0 && !(s->flags & SCCNXP_HAVE_MR0))
230 div_std = DIV_ROUND_CLOSEST(s->freq_std, baud_std[i].baud);
231 tmp_baud = DIV_ROUND_CLOSEST(port->uartclk, div_std);
232 if (!sccnxp_update_best_err(baud, tmp_baud, &besterr)) {
233 acr = baud_std[i].acr;
234 csr = baud_std[i].csr;
235 mr0 = baud_std[i].mr0;
240 if (s->flags & SCCNXP_HAVE_MR0) {
241 /* Enable FIFO, set half level for TX */
242 mr0 |= MR0_FIFO | MR0_TXLVL;
244 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_MRPTR0);
245 sccnxp_port_write(port, SCCNXP_MR_REG, mr0);
248 sccnxp_port_write(port, SCCNXP_ACR_REG, acr | ACR_TIMER_MODE);
249 sccnxp_port_write(port, SCCNXP_CSR_REG, (csr << 4) | csr);
251 if (baud != bestbaud)
252 dev_dbg(port->dev, "Baudrate desired: %i, calculated: %i\n",
258 static void sccnxp_enable_irq(struct uart_port *port, int mask)
260 struct sccnxp_port *s = dev_get_drvdata(port->dev);
262 s->imr |= mask << (port->line * 4);
263 sccnxp_write(port, SCCNXP_IMR_REG, s->imr);
266 static void sccnxp_disable_irq(struct uart_port *port, int mask)
268 struct sccnxp_port *s = dev_get_drvdata(port->dev);
270 s->imr &= ~(mask << (port->line * 4));
271 sccnxp_write(port, SCCNXP_IMR_REG, s->imr);
274 static void sccnxp_set_bit(struct uart_port *port, int sig, int state)
277 struct sccnxp_port *s = dev_get_drvdata(port->dev);
279 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(sig)) {
280 bitmask = 1 << MCTRL_OBIT(s->pdata.mctrl_cfg[port->line], sig);
282 sccnxp_write(port, SCCNXP_SOP_REG, bitmask);
284 sccnxp_write(port, SCCNXP_ROP_REG, bitmask);
288 static void sccnxp_handle_rx(struct uart_port *port)
291 unsigned int ch, flag;
294 sr = sccnxp_port_read(port, SCCNXP_SR_REG);
295 if (!(sr & SR_RXRDY))
297 sr &= SR_PE | SR_FE | SR_OVR | SR_BRK;
299 ch = sccnxp_port_read(port, SCCNXP_RHR_REG);
307 sccnxp_port_write(port, SCCNXP_CR_REG,
309 if (uart_handle_break(port))
311 } else if (sr & SR_PE)
312 port->icount.parity++;
314 port->icount.frame++;
315 else if (sr & SR_OVR) {
316 port->icount.overrun++;
317 sccnxp_port_write(port, SCCNXP_CR_REG,
318 CR_CMD_STATUS_RESET);
321 sr &= port->read_status_mask;
328 else if (sr & SR_OVR)
332 if (uart_handle_sysrq_char(port, ch))
335 if (sr & port->ignore_status_mask)
338 uart_insert_char(port, sr, SR_OVR, ch, flag);
341 tty_flip_buffer_push(&port->state->port);
344 static void sccnxp_handle_tx(struct uart_port *port)
347 struct circ_buf *xmit = &port->state->xmit;
348 struct sccnxp_port *s = dev_get_drvdata(port->dev);
350 if (unlikely(port->x_char)) {
351 sccnxp_port_write(port, SCCNXP_THR_REG, port->x_char);
357 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
358 /* Disable TX if FIFO is empty */
359 if (sccnxp_port_read(port, SCCNXP_SR_REG) & SR_TXEMT) {
360 sccnxp_disable_irq(port, IMR_TXRDY);
362 /* Set direction to input */
363 if (s->flags & SCCNXP_HAVE_IO)
364 sccnxp_set_bit(port, DIR_OP, 0);
369 while (!uart_circ_empty(xmit)) {
370 sr = sccnxp_port_read(port, SCCNXP_SR_REG);
371 if (!(sr & SR_TXRDY))
374 sccnxp_port_write(port, SCCNXP_THR_REG, xmit->buf[xmit->tail]);
375 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
379 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
380 uart_write_wakeup(port);
383 static void sccnxp_handle_events(struct sccnxp_port *s)
389 isr = sccnxp_read(&s->port[0], SCCNXP_ISR_REG);
394 for (i = 0; i < s->uart.nr; i++) {
395 if (s->opened[i] && (isr & ISR_RXRDY(i)))
396 sccnxp_handle_rx(&s->port[i]);
397 if (s->opened[i] && (isr & ISR_TXRDY(i)))
398 sccnxp_handle_tx(&s->port[i]);
403 static void sccnxp_timer(unsigned long data)
405 struct sccnxp_port *s = (struct sccnxp_port *)data;
408 spin_lock_irqsave(&s->lock, flags);
409 sccnxp_handle_events(s);
410 spin_unlock_irqrestore(&s->lock, flags);
412 if (!timer_pending(&s->timer))
413 mod_timer(&s->timer, jiffies +
414 usecs_to_jiffies(s->pdata.poll_time_us));
417 static irqreturn_t sccnxp_ist(int irq, void *dev_id)
419 struct sccnxp_port *s = (struct sccnxp_port *)dev_id;
422 spin_lock_irqsave(&s->lock, flags);
423 sccnxp_handle_events(s);
424 spin_unlock_irqrestore(&s->lock, flags);
429 static void sccnxp_start_tx(struct uart_port *port)
431 struct sccnxp_port *s = dev_get_drvdata(port->dev);
434 spin_lock_irqsave(&s->lock, flags);
436 /* Set direction to output */
437 if (s->flags & SCCNXP_HAVE_IO)
438 sccnxp_set_bit(port, DIR_OP, 1);
440 sccnxp_enable_irq(port, IMR_TXRDY);
442 spin_unlock_irqrestore(&s->lock, flags);
445 static void sccnxp_stop_tx(struct uart_port *port)
450 static void sccnxp_stop_rx(struct uart_port *port)
452 struct sccnxp_port *s = dev_get_drvdata(port->dev);
455 spin_lock_irqsave(&s->lock, flags);
456 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_DISABLE);
457 spin_unlock_irqrestore(&s->lock, flags);
460 static unsigned int sccnxp_tx_empty(struct uart_port *port)
464 struct sccnxp_port *s = dev_get_drvdata(port->dev);
466 spin_lock_irqsave(&s->lock, flags);
467 val = sccnxp_port_read(port, SCCNXP_SR_REG);
468 spin_unlock_irqrestore(&s->lock, flags);
470 return (val & SR_TXEMT) ? TIOCSER_TEMT : 0;
473 static void sccnxp_enable_ms(struct uart_port *port)
478 static void sccnxp_set_mctrl(struct uart_port *port, unsigned int mctrl)
480 struct sccnxp_port *s = dev_get_drvdata(port->dev);
483 if (!(s->flags & SCCNXP_HAVE_IO))
486 spin_lock_irqsave(&s->lock, flags);
488 sccnxp_set_bit(port, DTR_OP, mctrl & TIOCM_DTR);
489 sccnxp_set_bit(port, RTS_OP, mctrl & TIOCM_RTS);
491 spin_unlock_irqrestore(&s->lock, flags);
494 static unsigned int sccnxp_get_mctrl(struct uart_port *port)
498 struct sccnxp_port *s = dev_get_drvdata(port->dev);
499 unsigned int mctrl = TIOCM_DSR | TIOCM_CTS | TIOCM_CAR;
501 if (!(s->flags & SCCNXP_HAVE_IO))
504 spin_lock_irqsave(&s->lock, flags);
506 ipr = ~sccnxp_read(port, SCCNXP_IPCR_REG);
508 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(DSR_IP)) {
509 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line],
512 mctrl |= (ipr & bitmask) ? TIOCM_DSR : 0;
514 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(CTS_IP)) {
515 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line],
518 mctrl |= (ipr & bitmask) ? TIOCM_CTS : 0;
520 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(DCD_IP)) {
521 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line],
524 mctrl |= (ipr & bitmask) ? TIOCM_CAR : 0;
526 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(RNG_IP)) {
527 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line],
530 mctrl |= (ipr & bitmask) ? TIOCM_RNG : 0;
533 spin_unlock_irqrestore(&s->lock, flags);
538 static void sccnxp_break_ctl(struct uart_port *port, int break_state)
540 struct sccnxp_port *s = dev_get_drvdata(port->dev);
543 spin_lock_irqsave(&s->lock, flags);
544 sccnxp_port_write(port, SCCNXP_CR_REG, break_state ?
545 CR_CMD_START_BREAK : CR_CMD_STOP_BREAK);
546 spin_unlock_irqrestore(&s->lock, flags);
549 static void sccnxp_set_termios(struct uart_port *port,
550 struct ktermios *termios, struct ktermios *old)
552 struct sccnxp_port *s = dev_get_drvdata(port->dev);
557 spin_lock_irqsave(&s->lock, flags);
559 /* Mask termios capabilities we don't support */
560 termios->c_cflag &= ~CMSPAR;
562 /* Disable RX & TX, reset break condition, status and FIFOs */
563 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_RX_RESET |
564 CR_RX_DISABLE | CR_TX_DISABLE);
565 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_TX_RESET);
566 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_STATUS_RESET);
567 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_BREAK_RESET);
570 switch (termios->c_cflag & CSIZE) {
587 if (termios->c_cflag & PARENB) {
588 if (termios->c_cflag & PARODD)
594 mr2 = (termios->c_cflag & CSTOPB) ? MR2_STOP2 : MR2_STOP1;
596 /* Update desired format */
597 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_MRPTR1);
598 sccnxp_port_write(port, SCCNXP_MR_REG, mr1);
599 sccnxp_port_write(port, SCCNXP_MR_REG, mr2);
601 /* Set read status mask */
602 port->read_status_mask = SR_OVR;
603 if (termios->c_iflag & INPCK)
604 port->read_status_mask |= SR_PE | SR_FE;
605 if (termios->c_iflag & (BRKINT | PARMRK))
606 port->read_status_mask |= SR_BRK;
608 /* Set status ignore mask */
609 port->ignore_status_mask = 0;
610 if (termios->c_iflag & IGNBRK)
611 port->ignore_status_mask |= SR_BRK;
612 if (!(termios->c_cflag & CREAD))
613 port->ignore_status_mask |= SR_PE | SR_OVR | SR_FE | SR_BRK;
616 baud = uart_get_baud_rate(port, termios, old, 50,
617 (s->flags & SCCNXP_HAVE_MR0) ?
619 baud = sccnxp_set_baud(port, baud);
621 /* Update timeout according to new baud rate */
622 uart_update_timeout(port, termios->c_cflag, baud);
624 /* Report actual baudrate back to core */
625 if (tty_termios_baud_rate(termios))
626 tty_termios_encode_baud_rate(termios, baud, baud);
629 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_ENABLE | CR_TX_ENABLE);
631 spin_unlock_irqrestore(&s->lock, flags);
634 static int sccnxp_startup(struct uart_port *port)
636 struct sccnxp_port *s = dev_get_drvdata(port->dev);
639 spin_lock_irqsave(&s->lock, flags);
641 if (s->flags & SCCNXP_HAVE_IO) {
642 /* Outputs are controlled manually */
643 sccnxp_write(port, SCCNXP_OPCR_REG, 0);
646 /* Reset break condition, status and FIFOs */
647 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_RX_RESET);
648 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_TX_RESET);
649 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_STATUS_RESET);
650 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_BREAK_RESET);
653 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_ENABLE | CR_TX_ENABLE);
655 /* Enable RX interrupt */
656 sccnxp_enable_irq(port, IMR_RXRDY);
658 s->opened[port->line] = 1;
660 spin_unlock_irqrestore(&s->lock, flags);
665 static void sccnxp_shutdown(struct uart_port *port)
667 struct sccnxp_port *s = dev_get_drvdata(port->dev);
670 spin_lock_irqsave(&s->lock, flags);
672 s->opened[port->line] = 0;
674 /* Disable interrupts */
675 sccnxp_disable_irq(port, IMR_TXRDY | IMR_RXRDY);
677 /* Disable TX & RX */
678 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_DISABLE | CR_TX_DISABLE);
680 /* Leave direction to input */
681 if (s->flags & SCCNXP_HAVE_IO)
682 sccnxp_set_bit(port, DIR_OP, 0);
684 spin_unlock_irqrestore(&s->lock, flags);
687 static const char *sccnxp_type(struct uart_port *port)
689 struct sccnxp_port *s = dev_get_drvdata(port->dev);
691 return (port->type == PORT_SC26XX) ? s->name : NULL;
694 static void sccnxp_release_port(struct uart_port *port)
699 static int sccnxp_request_port(struct uart_port *port)
705 static void sccnxp_config_port(struct uart_port *port, int flags)
707 if (flags & UART_CONFIG_TYPE)
708 port->type = PORT_SC26XX;
711 static int sccnxp_verify_port(struct uart_port *port, struct serial_struct *s)
713 if ((s->type == PORT_UNKNOWN) || (s->type == PORT_SC26XX))
715 if (s->irq == port->irq)
721 static const struct uart_ops sccnxp_ops = {
722 .tx_empty = sccnxp_tx_empty,
723 .set_mctrl = sccnxp_set_mctrl,
724 .get_mctrl = sccnxp_get_mctrl,
725 .stop_tx = sccnxp_stop_tx,
726 .start_tx = sccnxp_start_tx,
727 .stop_rx = sccnxp_stop_rx,
728 .enable_ms = sccnxp_enable_ms,
729 .break_ctl = sccnxp_break_ctl,
730 .startup = sccnxp_startup,
731 .shutdown = sccnxp_shutdown,
732 .set_termios = sccnxp_set_termios,
734 .release_port = sccnxp_release_port,
735 .request_port = sccnxp_request_port,
736 .config_port = sccnxp_config_port,
737 .verify_port = sccnxp_verify_port,
740 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
741 static void sccnxp_console_putchar(struct uart_port *port, int c)
746 if (sccnxp_port_read(port, SCCNXP_SR_REG) & SR_TXRDY) {
747 sccnxp_port_write(port, SCCNXP_THR_REG, c);
754 static void sccnxp_console_write(struct console *co, const char *c, unsigned n)
756 struct sccnxp_port *s = (struct sccnxp_port *)co->data;
757 struct uart_port *port = &s->port[co->index];
760 spin_lock_irqsave(&s->lock, flags);
761 uart_console_write(port, c, n, sccnxp_console_putchar);
762 spin_unlock_irqrestore(&s->lock, flags);
765 static int sccnxp_console_setup(struct console *co, char *options)
767 struct sccnxp_port *s = (struct sccnxp_port *)co->data;
768 struct uart_port *port = &s->port[(co->index > 0) ? co->index : 0];
769 int baud = 9600, bits = 8, parity = 'n', flow = 'n';
772 uart_parse_options(options, &baud, &parity, &bits, &flow);
774 return uart_set_options(port, co, baud, parity, bits, flow);
778 static int sccnxp_probe(struct platform_device *pdev)
780 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
781 int chiptype = pdev->id_entry->driver_data;
782 struct sccnxp_pdata *pdata = dev_get_platdata(&pdev->dev);
783 int i, ret, fifosize, freq_min, freq_max;
784 struct sccnxp_port *s;
785 void __iomem *membase;
788 dev_err(&pdev->dev, "Missing memory resource data\n");
789 return -EADDRNOTAVAIL;
792 dev_set_name(&pdev->dev, SCCNXP_NAME);
794 s = devm_kzalloc(&pdev->dev, sizeof(struct sccnxp_port), GFP_KERNEL);
796 dev_err(&pdev->dev, "Error allocating port structure\n");
799 platform_set_drvdata(pdev, s);
801 spin_lock_init(&s->lock);
803 /* Individual chip settings */
805 case SCCNXP_TYPE_SC2681:
808 s->freq_std = 3686400;
810 s->flags = SCCNXP_HAVE_IO;
815 case SCCNXP_TYPE_SC2691:
818 s->freq_std = 3686400;
825 case SCCNXP_TYPE_SC2692:
828 s->freq_std = 3686400;
830 s->flags = SCCNXP_HAVE_IO;
835 case SCCNXP_TYPE_SC2891:
838 s->freq_std = 3686400;
840 s->flags = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0;
845 case SCCNXP_TYPE_SC2892:
848 s->freq_std = 3686400;
850 s->flags = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0;
855 case SCCNXP_TYPE_SC28202:
858 s->freq_std = 14745600;
860 s->flags = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0;
865 case SCCNXP_TYPE_SC68681:
868 s->freq_std = 3686400;
870 s->flags = SCCNXP_HAVE_IO;
875 case SCCNXP_TYPE_SC68692:
878 s->freq_std = 3686400;
880 s->flags = SCCNXP_HAVE_IO;
886 dev_err(&pdev->dev, "Unsupported chip type %i\n", chiptype);
893 "No platform data supplied, using defaults\n");
894 s->pdata.frequency = s->freq_std;
896 memcpy(&s->pdata, pdata, sizeof(struct sccnxp_pdata));
898 if (s->pdata.poll_time_us) {
899 dev_info(&pdev->dev, "Using poll mode, resolution %u usecs\n",
900 s->pdata.poll_time_us);
905 s->irq = platform_get_irq(pdev, 0);
907 dev_err(&pdev->dev, "Missing irq resource data\n");
913 /* Check input frequency */
914 if ((s->pdata.frequency < freq_min) ||
915 (s->pdata.frequency > freq_max)) {
916 dev_err(&pdev->dev, "Frequency out of bounds\n");
921 membase = devm_ioremap_resource(&pdev->dev, res);
922 if (IS_ERR(membase)) {
923 ret = PTR_ERR(membase);
927 s->uart.owner = THIS_MODULE;
928 s->uart.dev_name = "ttySC";
929 s->uart.major = SCCNXP_MAJOR;
930 s->uart.minor = SCCNXP_MINOR;
931 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
932 s->uart.cons = &s->console;
933 s->uart.cons->device = uart_console_device;
934 s->uart.cons->write = sccnxp_console_write;
935 s->uart.cons->setup = sccnxp_console_setup;
936 s->uart.cons->flags = CON_PRINTBUFFER;
937 s->uart.cons->index = -1;
938 s->uart.cons->data = s;
939 strcpy(s->uart.cons->name, "ttySC");
941 ret = uart_register_driver(&s->uart);
943 dev_err(&pdev->dev, "Registering UART driver failed\n");
947 for (i = 0; i < s->uart.nr; i++) {
949 s->port[i].dev = &pdev->dev;
950 s->port[i].irq = s->irq;
951 s->port[i].type = PORT_SC26XX;
952 s->port[i].fifosize = fifosize;
953 s->port[i].flags = UPF_SKIP_TEST | UPF_FIXED_TYPE;
954 s->port[i].iotype = UPIO_MEM;
955 s->port[i].mapbase = res->start;
956 s->port[i].membase = membase;
957 s->port[i].regshift = s->pdata.reg_shift;
958 s->port[i].uartclk = s->pdata.frequency;
959 s->port[i].ops = &sccnxp_ops;
960 uart_add_one_port(&s->uart, &s->port[i]);
961 /* Set direction to input */
962 if (s->flags & SCCNXP_HAVE_IO)
963 sccnxp_set_bit(&s->port[i], DIR_OP, 0);
966 /* Disable interrupts */
968 sccnxp_write(&s->port[0], SCCNXP_IMR_REG, 0);
970 /* Board specific configure */
975 ret = devm_request_threaded_irq(&pdev->dev, s->irq, NULL,
977 IRQF_TRIGGER_FALLING |
979 dev_name(&pdev->dev), s);
983 dev_err(&pdev->dev, "Unable to reguest IRQ %i\n", s->irq);
985 init_timer(&s->timer);
986 setup_timer(&s->timer, sccnxp_timer, (unsigned long)s);
987 mod_timer(&s->timer, jiffies +
988 usecs_to_jiffies(s->pdata.poll_time_us));
993 platform_set_drvdata(pdev, NULL);
998 static int sccnxp_remove(struct platform_device *pdev)
1001 struct sccnxp_port *s = platform_get_drvdata(pdev);
1004 devm_free_irq(&pdev->dev, s->irq, s);
1006 del_timer_sync(&s->timer);
1008 for (i = 0; i < s->uart.nr; i++)
1009 uart_remove_one_port(&s->uart, &s->port[i]);
1011 uart_unregister_driver(&s->uart);
1012 platform_set_drvdata(pdev, NULL);
1020 static const struct platform_device_id sccnxp_id_table[] = {
1021 { "sc2681", SCCNXP_TYPE_SC2681 },
1022 { "sc2691", SCCNXP_TYPE_SC2691 },
1023 { "sc2692", SCCNXP_TYPE_SC2692 },
1024 { "sc2891", SCCNXP_TYPE_SC2891 },
1025 { "sc2892", SCCNXP_TYPE_SC2892 },
1026 { "sc28202", SCCNXP_TYPE_SC28202 },
1027 { "sc68681", SCCNXP_TYPE_SC68681 },
1028 { "sc68692", SCCNXP_TYPE_SC68692 },
1031 MODULE_DEVICE_TABLE(platform, sccnxp_id_table);
1033 static struct platform_driver sccnxp_uart_driver = {
1035 .name = SCCNXP_NAME,
1036 .owner = THIS_MODULE,
1038 .probe = sccnxp_probe,
1039 .remove = sccnxp_remove,
1040 .id_table = sccnxp_id_table,
1042 module_platform_driver(sccnxp_uart_driver);
1044 MODULE_LICENSE("GPL v2");
1045 MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>");
1046 MODULE_DESCRIPTION("SCCNXP serial driver");