Pileus Git - ~andy/linux/blob - drivers/tty/serial/pch_uart.c

   1 /*
   2  *Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
   3  *
   4  *This program is free software; you can redistribute it and/or modify
   5  *it under the terms of the GNU General Public License as published by
   6  *the Free Software Foundation; version 2 of the License.
   7  *
   8  *This program is distributed in the hope that it will be useful,
   9  *but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  *MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  *GNU General Public License for more details.
  12  *
  13  *You should have received a copy of the GNU General Public License
  14  *along with this program; if not, write to the Free Software
  15  *Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307, USA.
  16  */
  17 #include <linux/kernel.h>
  18 #include <linux/serial_reg.h>
  19 #include <linux/slab.h>
  20 #include <linux/module.h>
  21 #include <linux/pci.h>
  22 #include <linux/serial_core.h>
  23 #include <linux/tty.h>
  24 #include <linux/tty_flip.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/io.h>
  27 #include <linux/dmi.h>
  28 #include <linux/console.h>
  29 #include <linux/nmi.h>
  30 #include <linux/delay.h>
  31
  32 #include <linux/debugfs.h>
  33 #include <linux/dmaengine.h>
  34 #include <linux/pch_dma.h>
  35
  36 enum {
  37         PCH_UART_HANDLED_RX_INT_SHIFT,
  38         PCH_UART_HANDLED_TX_INT_SHIFT,
  39         PCH_UART_HANDLED_RX_ERR_INT_SHIFT,
  40         PCH_UART_HANDLED_RX_TRG_INT_SHIFT,
  41         PCH_UART_HANDLED_MS_INT_SHIFT,
  42         PCH_UART_HANDLED_LS_INT_SHIFT,
  43 };
  44
  45 enum {
  46         PCH_UART_8LINE,
  47         PCH_UART_2LINE,
  48 };
  49
  50 #define PCH_UART_DRIVER_DEVICE "ttyPCH"
  51
  52 /* Set the max number of UART port
  53  * Intel EG20T PCH: 4 port
  54  * LAPIS Semiconductor ML7213 IOH: 3 port
  55  * LAPIS Semiconductor ML7223 IOH: 2 port
  56 */
  57 #define PCH_UART_NR     4
  58
  59 #define PCH_UART_HANDLED_RX_INT (1<<((PCH_UART_HANDLED_RX_INT_SHIFT)<<1))
  60 #define PCH_UART_HANDLED_TX_INT (1<<((PCH_UART_HANDLED_TX_INT_SHIFT)<<1))
  61 #define PCH_UART_HANDLED_RX_ERR_INT     (1<<((\
  62                                         PCH_UART_HANDLED_RX_ERR_INT_SHIFT)<<1))
  63 #define PCH_UART_HANDLED_RX_TRG_INT     (1<<((\
  64                                         PCH_UART_HANDLED_RX_TRG_INT_SHIFT)<<1))
  65 #define PCH_UART_HANDLED_MS_INT (1<<((PCH_UART_HANDLED_MS_INT_SHIFT)<<1))
  66
  67 #define PCH_UART_HANDLED_LS_INT (1<<((PCH_UART_HANDLED_LS_INT_SHIFT)<<1))
  68
  69 #define PCH_UART_RBR            0x00
  70 #define PCH_UART_THR            0x00
  71
  72 #define PCH_UART_IER_MASK       (PCH_UART_IER_ERBFI|PCH_UART_IER_ETBEI|\
  73                                 PCH_UART_IER_ELSI|PCH_UART_IER_EDSSI)
  74 #define PCH_UART_IER_ERBFI      0x00000001
  75 #define PCH_UART_IER_ETBEI      0x00000002
  76 #define PCH_UART_IER_ELSI       0x00000004
  77 #define PCH_UART_IER_EDSSI      0x00000008
  78
  79 #define PCH_UART_IIR_IP                 0x00000001
  80 #define PCH_UART_IIR_IID                0x00000006
  81 #define PCH_UART_IIR_MSI                0x00000000
  82 #define PCH_UART_IIR_TRI                0x00000002
  83 #define PCH_UART_IIR_RRI                0x00000004
  84 #define PCH_UART_IIR_REI                0x00000006
  85 #define PCH_UART_IIR_TOI                0x00000008
  86 #define PCH_UART_IIR_FIFO256            0x00000020
  87 #define PCH_UART_IIR_FIFO64             PCH_UART_IIR_FIFO256
  88 #define PCH_UART_IIR_FE                 0x000000C0
  89
  90 #define PCH_UART_FCR_FIFOE              0x00000001
  91 #define PCH_UART_FCR_RFR                0x00000002
  92 #define PCH_UART_FCR_TFR                0x00000004
  93 #define PCH_UART_FCR_DMS                0x00000008
  94 #define PCH_UART_FCR_FIFO256            0x00000020
  95 #define PCH_UART_FCR_RFTL               0x000000C0
  96
  97 #define PCH_UART_FCR_RFTL1              0x00000000
  98 #define PCH_UART_FCR_RFTL64             0x00000040
  99 #define PCH_UART_FCR_RFTL128            0x00000080
 100 #define PCH_UART_FCR_RFTL224            0x000000C0
 101 #define PCH_UART_FCR_RFTL16             PCH_UART_FCR_RFTL64
 102 #define PCH_UART_FCR_RFTL32             PCH_UART_FCR_RFTL128
 103 #define PCH_UART_FCR_RFTL56             PCH_UART_FCR_RFTL224
 104 #define PCH_UART_FCR_RFTL4              PCH_UART_FCR_RFTL64
 105 #define PCH_UART_FCR_RFTL8              PCH_UART_FCR_RFTL128
 106 #define PCH_UART_FCR_RFTL14             PCH_UART_FCR_RFTL224
 107 #define PCH_UART_FCR_RFTL_SHIFT         6
 108
 109 #define PCH_UART_LCR_WLS        0x00000003
 110 #define PCH_UART_LCR_STB        0x00000004
 111 #define PCH_UART_LCR_PEN        0x00000008
 112 #define PCH_UART_LCR_EPS        0x00000010
 113 #define PCH_UART_LCR_SP         0x00000020
 114 #define PCH_UART_LCR_SB         0x00000040
 115 #define PCH_UART_LCR_DLAB       0x00000080
 116 #define PCH_UART_LCR_NP         0x00000000
 117 #define PCH_UART_LCR_OP         PCH_UART_LCR_PEN
 118 #define PCH_UART_LCR_EP         (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS)
 119 #define PCH_UART_LCR_1P         (PCH_UART_LCR_PEN | PCH_UART_LCR_SP)
 120 #define PCH_UART_LCR_0P         (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS |\
 121                                 PCH_UART_LCR_SP)
 122
 123 #define PCH_UART_LCR_5BIT       0x00000000
 124 #define PCH_UART_LCR_6BIT       0x00000001
 125 #define PCH_UART_LCR_7BIT       0x00000002
 126 #define PCH_UART_LCR_8BIT       0x00000003
 127
 128 #define PCH_UART_MCR_DTR        0x00000001
 129 #define PCH_UART_MCR_RTS        0x00000002
 130 #define PCH_UART_MCR_OUT        0x0000000C
 131 #define PCH_UART_MCR_LOOP       0x00000010
 132 #define PCH_UART_MCR_AFE        0x00000020
 133
 134 #define PCH_UART_LSR_DR         0x00000001
 135 #define PCH_UART_LSR_ERR        (1<<7)
 136
 137 #define PCH_UART_MSR_DCTS       0x00000001
 138 #define PCH_UART_MSR_DDSR       0x00000002
 139 #define PCH_UART_MSR_TERI       0x00000004
 140 #define PCH_UART_MSR_DDCD       0x00000008
 141 #define PCH_UART_MSR_CTS        0x00000010
 142 #define PCH_UART_MSR_DSR        0x00000020
 143 #define PCH_UART_MSR_RI         0x00000040
 144 #define PCH_UART_MSR_DCD        0x00000080
 145 #define PCH_UART_MSR_DELTA      (PCH_UART_MSR_DCTS | PCH_UART_MSR_DDSR |\
 146                                 PCH_UART_MSR_TERI | PCH_UART_MSR_DDCD)
 147
 148 #define PCH_UART_DLL            0x00
 149 #define PCH_UART_DLM            0x01
 150
 151 #define PCH_UART_BRCSR          0x0E
 152
 153 #define PCH_UART_IID_RLS        (PCH_UART_IIR_REI)
 154 #define PCH_UART_IID_RDR        (PCH_UART_IIR_RRI)
 155 #define PCH_UART_IID_RDR_TO     (PCH_UART_IIR_RRI | PCH_UART_IIR_TOI)
 156 #define PCH_UART_IID_THRE       (PCH_UART_IIR_TRI)
 157 #define PCH_UART_IID_MS         (PCH_UART_IIR_MSI)
 158
 159 #define PCH_UART_HAL_PARITY_NONE        (PCH_UART_LCR_NP)
 160 #define PCH_UART_HAL_PARITY_ODD         (PCH_UART_LCR_OP)
 161 #define PCH_UART_HAL_PARITY_EVEN        (PCH_UART_LCR_EP)
 162 #define PCH_UART_HAL_PARITY_FIX1        (PCH_UART_LCR_1P)
 163 #define PCH_UART_HAL_PARITY_FIX0        (PCH_UART_LCR_0P)
 164 #define PCH_UART_HAL_5BIT               (PCH_UART_LCR_5BIT)
 165 #define PCH_UART_HAL_6BIT               (PCH_UART_LCR_6BIT)
 166 #define PCH_UART_HAL_7BIT               (PCH_UART_LCR_7BIT)
 167 #define PCH_UART_HAL_8BIT               (PCH_UART_LCR_8BIT)
 168 #define PCH_UART_HAL_STB1               0
 169 #define PCH_UART_HAL_STB2               (PCH_UART_LCR_STB)
 170
 171 #define PCH_UART_HAL_CLR_TX_FIFO        (PCH_UART_FCR_TFR)
 172 #define PCH_UART_HAL_CLR_RX_FIFO        (PCH_UART_FCR_RFR)
 173 #define PCH_UART_HAL_CLR_ALL_FIFO       (PCH_UART_HAL_CLR_TX_FIFO | \
 174                                         PCH_UART_HAL_CLR_RX_FIFO)
 175
 176 #define PCH_UART_HAL_DMA_MODE0          0
 177 #define PCH_UART_HAL_FIFO_DIS           0
 178 #define PCH_UART_HAL_FIFO16             (PCH_UART_FCR_FIFOE)
 179 #define PCH_UART_HAL_FIFO256            (PCH_UART_FCR_FIFOE | \
 180                                         PCH_UART_FCR_FIFO256)
 181 #define PCH_UART_HAL_FIFO64             (PCH_UART_HAL_FIFO256)
 182 #define PCH_UART_HAL_TRIGGER1           (PCH_UART_FCR_RFTL1)
 183 #define PCH_UART_HAL_TRIGGER64          (PCH_UART_FCR_RFTL64)
 184 #define PCH_UART_HAL_TRIGGER128         (PCH_UART_FCR_RFTL128)
 185 #define PCH_UART_HAL_TRIGGER224         (PCH_UART_FCR_RFTL224)
 186 #define PCH_UART_HAL_TRIGGER16          (PCH_UART_FCR_RFTL16)
 187 #define PCH_UART_HAL_TRIGGER32          (PCH_UART_FCR_RFTL32)
 188 #define PCH_UART_HAL_TRIGGER56          (PCH_UART_FCR_RFTL56)
 189 #define PCH_UART_HAL_TRIGGER4           (PCH_UART_FCR_RFTL4)
 190 #define PCH_UART_HAL_TRIGGER8           (PCH_UART_FCR_RFTL8)
 191 #define PCH_UART_HAL_TRIGGER14          (PCH_UART_FCR_RFTL14)
 192 #define PCH_UART_HAL_TRIGGER_L          (PCH_UART_FCR_RFTL64)
 193 #define PCH_UART_HAL_TRIGGER_M          (PCH_UART_FCR_RFTL128)
 194 #define PCH_UART_HAL_TRIGGER_H          (PCH_UART_FCR_RFTL224)
 195
 196 #define PCH_UART_HAL_RX_INT             (PCH_UART_IER_ERBFI)
 197 #define PCH_UART_HAL_TX_INT             (PCH_UART_IER_ETBEI)
 198 #define PCH_UART_HAL_RX_ERR_INT         (PCH_UART_IER_ELSI)
 199 #define PCH_UART_HAL_MS_INT             (PCH_UART_IER_EDSSI)
 200 #define PCH_UART_HAL_ALL_INT            (PCH_UART_IER_MASK)
 201
 202 #define PCH_UART_HAL_DTR                (PCH_UART_MCR_DTR)
 203 #define PCH_UART_HAL_RTS                (PCH_UART_MCR_RTS)
 204 #define PCH_UART_HAL_OUT                (PCH_UART_MCR_OUT)
 205 #define PCH_UART_HAL_LOOP               (PCH_UART_MCR_LOOP)
 206 #define PCH_UART_HAL_AFE                (PCH_UART_MCR_AFE)
 207
 208 #define PCI_VENDOR_ID_ROHM              0x10DB
 209
 210 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
 211
 212 #define DEFAULT_UARTCLK   1843200 /*   1.8432 MHz */
 213 #define CMITC_UARTCLK   192000000 /* 192.0000 MHz */
 214 #define FRI2_64_UARTCLK  64000000 /*  64.0000 MHz */
 215 #define FRI2_48_UARTCLK  48000000 /*  48.0000 MHz */
 216 #define NTC1_UARTCLK     64000000 /*  64.0000 MHz */
 217
 218 struct pch_uart_buffer {
 219         unsigned char *buf;
 220         int size;
 221 };
 222
 223 struct eg20t_port {
 224         struct uart_port port;
 225         int port_type;
 226         void __iomem *membase;
 227         resource_size_t mapbase;
 228         unsigned int iobase;
 229         struct pci_dev *pdev;
 230         int fifo_size;
 231         int uartclk;
 232         int start_tx;
 233         int start_rx;
 234         int tx_empty;
 235         int trigger;
 236         int trigger_level;
 237         struct pch_uart_buffer rxbuf;
 238         unsigned int dmsr;
 239         unsigned int fcr;
 240         unsigned int mcr;
 241         unsigned int use_dma;
 242         struct dma_async_tx_descriptor  *desc_tx;
 243         struct dma_async_tx_descriptor  *desc_rx;
 244         struct pch_dma_slave            param_tx;
 245         struct pch_dma_slave            param_rx;
 246         struct dma_chan                 *chan_tx;
 247         struct dma_chan                 *chan_rx;
 248         struct scatterlist              *sg_tx_p;
 249         int                             nent;
 250         struct scatterlist              sg_rx;
 251         int                             tx_dma_use;
 252         void                            *rx_buf_virt;
 253         dma_addr_t                      rx_buf_dma;
 254
 255         struct dentry   *debugfs;
 256 };
 257
 258 /**
 259  * struct pch_uart_driver_data - private data structure for UART-DMA
 260  * @port_type:                  The number of DMA channel
 261  * @line_no:                    UART port line number (0, 1, 2...)
 262  */
 263 struct pch_uart_driver_data {
 264         int port_type;
 265         int line_no;
 266 };
 267
 268 enum pch_uart_num_t {
 269         pch_et20t_uart0 = 0,
 270         pch_et20t_uart1,
 271         pch_et20t_uart2,
 272         pch_et20t_uart3,
 273         pch_ml7213_uart0,
 274         pch_ml7213_uart1,
 275         pch_ml7213_uart2,
 276         pch_ml7223_uart0,
 277         pch_ml7223_uart1,
 278         pch_ml7831_uart0,
 279         pch_ml7831_uart1,
 280 };
 281
 282 static struct pch_uart_driver_data drv_dat[] = {
 283         [pch_et20t_uart0] = {PCH_UART_8LINE, 0},
 284         [pch_et20t_uart1] = {PCH_UART_2LINE, 1},
 285         [pch_et20t_uart2] = {PCH_UART_2LINE, 2},
 286         [pch_et20t_uart3] = {PCH_UART_2LINE, 3},
 287         [pch_ml7213_uart0] = {PCH_UART_8LINE, 0},
 288         [pch_ml7213_uart1] = {PCH_UART_2LINE, 1},
 289         [pch_ml7213_uart2] = {PCH_UART_2LINE, 2},
 290         [pch_ml7223_uart0] = {PCH_UART_8LINE, 0},
 291         [pch_ml7223_uart1] = {PCH_UART_2LINE, 1},
 292         [pch_ml7831_uart0] = {PCH_UART_8LINE, 0},
 293         [pch_ml7831_uart1] = {PCH_UART_2LINE, 1},
 294 };
 295
 296 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
 297 static struct eg20t_port *pch_uart_ports[PCH_UART_NR];
 298 #endif
 299 static unsigned int default_baud = 9600;
 300 static unsigned int user_uartclk = 0;
 301 static const int trigger_level_256[4] = { 1, 64, 128, 224 };
 302 static const int trigger_level_64[4] = { 1, 16, 32, 56 };
 303 static const int trigger_level_16[4] = { 1, 4, 8, 14 };
 304 static const int trigger_level_1[4] = { 1, 1, 1, 1 };
 305
 306 #ifdef CONFIG_DEBUG_FS
 307
 308 #define PCH_REGS_BUFSIZE        1024
 309
 310
 311 static ssize_t port_show_regs(struct file *file, char __user *user_buf,
 312                                 size_t count, loff_t *ppos)
 313 {
 314         struct eg20t_port *priv = file->private_data;
 315         char *buf;
 316         u32 len = 0;
 317         ssize_t ret;
 318         unsigned char lcr;
 319
 320         buf = kzalloc(PCH_REGS_BUFSIZE, GFP_KERNEL);
 321         if (!buf)
 322                 return 0;
 323
 324         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 325                         "PCH EG20T port[%d] regs:\n", priv->port.line);
 326
 327         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 328                         "=================================\n");
 329         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 330                         "IER: \t0x%02x\n", ioread8(priv->membase + UART_IER));
 331         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 332                         "IIR: \t0x%02x\n", ioread8(priv->membase + UART_IIR));
 333         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 334                         "LCR: \t0x%02x\n", ioread8(priv->membase + UART_LCR));
 335         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 336                         "MCR: \t0x%02x\n", ioread8(priv->membase + UART_MCR));
 337         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 338                         "LSR: \t0x%02x\n", ioread8(priv->membase + UART_LSR));
 339         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 340                         "MSR: \t0x%02x\n", ioread8(priv->membase + UART_MSR));
 341         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 342                         "BRCSR: \t0x%02x\n",
 343                         ioread8(priv->membase + PCH_UART_BRCSR));
 344
 345         lcr = ioread8(priv->membase + UART_LCR);
 346         iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
 347         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 348                         "DLL: \t0x%02x\n", ioread8(priv->membase + UART_DLL));
 349         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 350                         "DLM: \t0x%02x\n", ioread8(priv->membase + UART_DLM));
 351         iowrite8(lcr, priv->membase + UART_LCR);
 352
 353         if (len > PCH_REGS_BUFSIZE)
 354                 len = PCH_REGS_BUFSIZE;
 355
 356         ret =  simple_read_from_buffer(user_buf, count, ppos, buf, len);
 357         kfree(buf);
 358         return ret;
 359 }
 360
 361 static const struct file_operations port_regs_ops = {
 362         .owner          = THIS_MODULE,
 363         .open           = simple_open,
 364         .read           = port_show_regs,
 365         .llseek         = default_llseek,
 366 };
 367 #endif  /* CONFIG_DEBUG_FS */
 368
 369 /* Return UART clock, checking for board specific clocks. */
 370 static int pch_uart_get_uartclk(void)
 371 {
 372         const char *cmp;
 373
 374         if (user_uartclk)
 375                 return user_uartclk;
 376
 377         cmp = dmi_get_system_info(DMI_BOARD_NAME);
 378         if (cmp && strstr(cmp, "CM-iTC"))
 379                 return CMITC_UARTCLK;
 380
 381         cmp = dmi_get_system_info(DMI_BIOS_VERSION);
 382         if (cmp && strnstr(cmp, "FRI2", 4))
 383                 return FRI2_64_UARTCLK;
 384
 385         cmp = dmi_get_system_info(DMI_PRODUCT_NAME);
 386         if (cmp && strstr(cmp, "Fish River Island II"))
 387                 return FRI2_48_UARTCLK;
 388
 389         /* Kontron COMe-mTT10 (nanoETXexpress-TT) */
 390         cmp = dmi_get_system_info(DMI_BOARD_NAME);
 391         if (cmp && (strstr(cmp, "COMe-mTT") ||
 392                     strstr(cmp, "nanoETXexpress-TT")))
 393                 return NTC1_UARTCLK;
 394
 395         return DEFAULT_UARTCLK;
 396 }
 397
 398 static void pch_uart_hal_enable_interrupt(struct eg20t_port *priv,
 399                                           unsigned int flag)
 400 {
 401         u8 ier = ioread8(priv->membase + UART_IER);
 402         ier |= flag & PCH_UART_IER_MASK;
 403         iowrite8(ier, priv->membase + UART_IER);
 404 }
 405
 406 static void pch_uart_hal_disable_interrupt(struct eg20t_port *priv,
 407                                            unsigned int flag)
 408 {
 409         u8 ier = ioread8(priv->membase + UART_IER);
 410         ier &= ~(flag & PCH_UART_IER_MASK);
 411         iowrite8(ier, priv->membase + UART_IER);
 412 }
 413
 414 static int pch_uart_hal_set_line(struct eg20t_port *priv, int baud,
 415                                  unsigned int parity, unsigned int bits,
 416                                  unsigned int stb)
 417 {
 418         unsigned int dll, dlm, lcr;
 419         int div;
 420
 421         div = DIV_ROUND_CLOSEST(priv->uartclk / 16, baud);
 422         if (div < 0 || USHRT_MAX <= div) {
 423                 dev_err(priv->port.dev, "Invalid Baud(div=0x%x)\n", div);
 424                 return -EINVAL;
 425         }
 426
 427         dll = (unsigned int)div & 0x00FFU;
 428         dlm = ((unsigned int)div >> 8) & 0x00FFU;
 429
 430         if (parity & ~(PCH_UART_LCR_PEN | PCH_UART_LCR_EPS | PCH_UART_LCR_SP)) {
 431                 dev_err(priv->port.dev, "Invalid parity(0x%x)\n", parity);
 432                 return -EINVAL;
 433         }
 434
 435         if (bits & ~PCH_UART_LCR_WLS) {
 436                 dev_err(priv->port.dev, "Invalid bits(0x%x)\n", bits);
 437                 return -EINVAL;
 438         }
 439
 440         if (stb & ~PCH_UART_LCR_STB) {
 441                 dev_err(priv->port.dev, "Invalid STB(0x%x)\n", stb);
 442                 return -EINVAL;
 443         }
 444
 445         lcr = parity;
 446         lcr |= bits;
 447         lcr |= stb;
 448
 449         dev_dbg(priv->port.dev, "%s:baud = %d, div = %04x, lcr = %02x (%lu)\n",
 450                  __func__, baud, div, lcr, jiffies);
 451         iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
 452         iowrite8(dll, priv->membase + PCH_UART_DLL);
 453         iowrite8(dlm, priv->membase + PCH_UART_DLM);
 454         iowrite8(lcr, priv->membase + UART_LCR);
 455
 456         return 0;
 457 }
 458
 459 static int pch_uart_hal_fifo_reset(struct eg20t_port *priv,
 460                                     unsigned int flag)
 461 {
 462         if (flag & ~(PCH_UART_FCR_TFR | PCH_UART_FCR_RFR)) {
 463                 dev_err(priv->port.dev, "%s:Invalid flag(0x%x)\n",
 464                         __func__, flag);
 465                 return -EINVAL;
 466         }
 467
 468         iowrite8(PCH_UART_FCR_FIFOE | priv->fcr, priv->membase + UART_FCR);
 469         iowrite8(PCH_UART_FCR_FIFOE | priv->fcr | flag,
 470                  priv->membase + UART_FCR);
 471         iowrite8(priv->fcr, priv->membase + UART_FCR);
 472
 473         return 0;
 474 }
 475
 476 static int pch_uart_hal_set_fifo(struct eg20t_port *priv,
 477                                  unsigned int dmamode,
 478                                  unsigned int fifo_size, unsigned int trigger)
 479 {
 480         u8 fcr;
 481
 482         if (dmamode & ~PCH_UART_FCR_DMS) {
 483                 dev_err(priv->port.dev, "%s:Invalid DMA Mode(0x%x)\n",
 484                         __func__, dmamode);
 485                 return -EINVAL;
 486         }
 487
 488         if (fifo_size & ~(PCH_UART_FCR_FIFOE | PCH_UART_FCR_FIFO256)) {
 489                 dev_err(priv->port.dev, "%s:Invalid FIFO SIZE(0x%x)\n",
 490                         __func__, fifo_size);
 491                 return -EINVAL;
 492         }
 493
 494         if (trigger & ~PCH_UART_FCR_RFTL) {
 495                 dev_err(priv->port.dev, "%s:Invalid TRIGGER(0x%x)\n",
 496                         __func__, trigger);
 497                 return -EINVAL;
 498         }
 499
 500         switch (priv->fifo_size) {
 501         case 256:
 502                 priv->trigger_level =
 503                     trigger_level_256[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 504                 break;
 505         case 64:
 506                 priv->trigger_level =
 507                     trigger_level_64[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 508                 break;
 509         case 16:
 510                 priv->trigger_level =
 511                     trigger_level_16[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 512                 break;
 513         default:
 514                 priv->trigger_level =
 515                     trigger_level_1[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 516                 break;
 517         }
 518         fcr =
 519             dmamode | fifo_size | trigger | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR;
 520         iowrite8(PCH_UART_FCR_FIFOE, priv->membase + UART_FCR);
 521         iowrite8(PCH_UART_FCR_FIFOE | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR,
 522                  priv->membase + UART_FCR);
 523         iowrite8(fcr, priv->membase + UART_FCR);
 524         priv->fcr = fcr;
 525
 526         return 0;
 527 }
 528
 529 static u8 pch_uart_hal_get_modem(struct eg20t_port *priv)
 530 {
 531         unsigned int msr = ioread8(priv->membase + UART_MSR);
 532         priv->dmsr = msr & PCH_UART_MSR_DELTA;
 533         return (u8)msr;
 534 }
 535
 536 static void pch_uart_hal_write(struct eg20t_port *priv,
 537                               const unsigned char *buf, int tx_size)
 538 {
 539         int i;
 540         unsigned int thr;
 541
 542         for (i = 0; i < tx_size;) {
 543                 thr = buf[i++];
 544                 iowrite8(thr, priv->membase + PCH_UART_THR);
 545         }
 546 }
 547
 548 static int pch_uart_hal_read(struct eg20t_port *priv, unsigned char *buf,
 549                              int rx_size)
 550 {
 551         int i;
 552         u8 rbr, lsr;
 553
 554         lsr = ioread8(priv->membase + UART_LSR);
 555         for (i = 0, lsr = ioread8(priv->membase + UART_LSR);
 556              i < rx_size && lsr & UART_LSR_DR;
 557              lsr = ioread8(priv->membase + UART_LSR)) {
 558                 rbr = ioread8(priv->membase + PCH_UART_RBR);
 559                 buf[i++] = rbr;
 560         }
 561         return i;
 562 }
 563
 564 static unsigned char pch_uart_hal_get_iid(struct eg20t_port *priv)
 565 {
 566         return ioread8(priv->membase + UART_IIR) &\
 567                       (PCH_UART_IIR_IID | PCH_UART_IIR_TOI | PCH_UART_IIR_IP);
 568 }
 569
 570 static u8 pch_uart_hal_get_line_status(struct eg20t_port *priv)
 571 {
 572         return ioread8(priv->membase + UART_LSR);
 573 }
 574
 575 static void pch_uart_hal_set_break(struct eg20t_port *priv, int on)
 576 {
 577         unsigned int lcr;
 578
 579         lcr = ioread8(priv->membase + UART_LCR);
 580         if (on)
 581                 lcr |= PCH_UART_LCR_SB;
 582         else
 583                 lcr &= ~PCH_UART_LCR_SB;
 584
 585         iowrite8(lcr, priv->membase + UART_LCR);
 586 }
 587
 588 static int push_rx(struct eg20t_port *priv, const unsigned char *buf,
 589                    int size)
 590 {
 591         struct uart_port *port;
 592         struct tty_struct *tty;
 593
 594         port = &priv->port;
 595         tty = tty_port_tty_get(&port->state->port);
 596         if (!tty) {
 597                 dev_dbg(priv->port.dev, "%s:tty is busy now", __func__);
 598                 return -EBUSY;
 599         }
 600
 601         tty_insert_flip_string(tty, buf, size);
 602         tty_flip_buffer_push(tty);
 603         tty_kref_put(tty);
 604
 605         return 0;
 606 }
 607
 608 static int pop_tx_x(struct eg20t_port *priv, unsigned char *buf)
 609 {
 610         int ret = 0;
 611         struct uart_port *port = &priv->port;
 612
 613         if (port->x_char) {
 614                 dev_dbg(priv->port.dev, "%s:X character send %02x (%lu)\n",
 615                         __func__, port->x_char, jiffies);
 616                 buf[0] = port->x_char;
 617                 port->x_char = 0;
 618                 ret = 1;
 619         }
 620
 621         return ret;
 622 }
 623
 624 static int dma_push_rx(struct eg20t_port *priv, int size)
 625 {
 626         struct tty_struct *tty;
 627         int room;
 628         struct uart_port *port = &priv->port;
 629
 630         port = &priv->port;
 631         tty = tty_port_tty_get(&port->state->port);
 632         if (!tty) {
 633                 dev_dbg(priv->port.dev, "%s:tty is busy now", __func__);
 634                 return 0;
 635         }
 636
 637         room = tty_buffer_request_room(tty, size);
 638
 639         if (room < size)
 640                 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
 641                          size - room);
 642         if (!room)
 643                 return room;
 644
 645         tty_insert_flip_string(tty, sg_virt(&priv->sg_rx), size);
 646
 647         port->icount.rx += room;
 648         tty_kref_put(tty);
 649
 650         return room;
 651 }
 652
 653 static void pch_free_dma(struct uart_port *port)
 654 {
 655         struct eg20t_port *priv;
 656         priv = container_of(port, struct eg20t_port, port);
 657
 658         if (priv->chan_tx) {
 659                 dma_release_channel(priv->chan_tx);
 660                 priv->chan_tx = NULL;
 661         }
 662         if (priv->chan_rx) {
 663                 dma_release_channel(priv->chan_rx);
 664                 priv->chan_rx = NULL;
 665         }
 666
 667         if (priv->rx_buf_dma) {
 668                 dma_free_coherent(port->dev, port->fifosize, priv->rx_buf_virt,
 669                                   priv->rx_buf_dma);
 670                 priv->rx_buf_virt = NULL;
 671                 priv->rx_buf_dma = 0;
 672         }
 673
 674         return;
 675 }
 676
 677 static bool filter(struct dma_chan *chan, void *slave)
 678 {
 679         struct pch_dma_slave *param = slave;
 680
 681         if ((chan->chan_id == param->chan_id) && (param->dma_dev ==
 682                                                   chan->device->dev)) {
 683                 chan->private = param;
 684                 return true;
 685         } else {
 686                 return false;
 687         }
 688 }
 689
 690 static void pch_request_dma(struct uart_port *port)
 691 {
 692         dma_cap_mask_t mask;
 693         struct dma_chan *chan;
 694         struct pci_dev *dma_dev;
 695         struct pch_dma_slave *param;
 696         struct eg20t_port *priv =
 697                                 container_of(port, struct eg20t_port, port);
 698         dma_cap_zero(mask);
 699         dma_cap_set(DMA_SLAVE, mask);
 700
 701         dma_dev = pci_get_bus_and_slot(priv->pdev->bus->number,
 702                                        PCI_DEVFN(0xa, 0)); /* Get DMA's dev
 703                                                                 information */
 704         /* Set Tx DMA */
 705         param = &priv->param_tx;
 706         param->dma_dev = &dma_dev->dev;
 707         param->chan_id = priv->port.line * 2; /* Tx = 0, 2, 4, ... */
 708
 709         param->tx_reg = port->mapbase + UART_TX;
 710         chan = dma_request_channel(mask, filter, param);
 711         if (!chan) {
 712                 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Tx)\n",
 713                         __func__);
 714                 return;
 715         }
 716         priv->chan_tx = chan;
 717
 718         /* Set Rx DMA */
 719         param = &priv->param_rx;
 720         param->dma_dev = &dma_dev->dev;
 721         param->chan_id = priv->port.line * 2 + 1; /* Rx = Tx + 1 */
 722
 723         param->rx_reg = port->mapbase + UART_RX;
 724         chan = dma_request_channel(mask, filter, param);
 725         if (!chan) {
 726                 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Rx)\n",
 727                         __func__);
 728                 dma_release_channel(priv->chan_tx);
 729                 priv->chan_tx = NULL;
 730                 return;
 731         }
 732
 733         /* Get Consistent memory for DMA */
 734         priv->rx_buf_virt = dma_alloc_coherent(port->dev, port->fifosize,
 735                                     &priv->rx_buf_dma, GFP_KERNEL);
 736         priv->chan_rx = chan;
 737 }
 738
 739 static void pch_dma_rx_complete(void *arg)
 740 {
 741         struct eg20t_port *priv = arg;
 742         struct uart_port *port = &priv->port;
 743         struct tty_struct *tty = tty_port_tty_get(&port->state->port);
 744         int count;
 745
 746         if (!tty) {
 747                 dev_dbg(priv->port.dev, "%s:tty is busy now", __func__);
 748                 return;
 749         }
 750
 751         dma_sync_sg_for_cpu(port->dev, &priv->sg_rx, 1, DMA_FROM_DEVICE);
 752         count = dma_push_rx(priv, priv->trigger_level);
 753         if (count)
 754                 tty_flip_buffer_push(tty);
 755         tty_kref_put(tty);
 756         async_tx_ack(priv->desc_rx);
 757         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT);
 758 }
 759
 760 static void pch_dma_tx_complete(void *arg)
 761 {
 762         struct eg20t_port *priv = arg;
 763         struct uart_port *port = &priv->port;
 764         struct circ_buf *xmit = &port->state->xmit;
 765         struct scatterlist *sg = priv->sg_tx_p;
 766         int i;
 767
 768         for (i = 0; i < priv->nent; i++, sg++) {
 769                 xmit->tail += sg_dma_len(sg);
 770                 port->icount.tx += sg_dma_len(sg);
 771         }
 772         xmit->tail &= UART_XMIT_SIZE - 1;
 773         async_tx_ack(priv->desc_tx);
 774         dma_unmap_sg(port->dev, sg, priv->nent, DMA_TO_DEVICE);
 775         priv->tx_dma_use = 0;
 776         priv->nent = 0;
 777         kfree(priv->sg_tx_p);
 778         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
 779 }
 780
 781 static int pop_tx(struct eg20t_port *priv, int size)
 782 {
 783         int count = 0;
 784         struct uart_port *port = &priv->port;
 785         struct circ_buf *xmit = &port->state->xmit;
 786
 787         if (uart_tx_stopped(port) || uart_circ_empty(xmit) || count >= size)
 788                 goto pop_tx_end;
 789
 790         do {
 791                 int cnt_to_end =
 792                     CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
 793                 int sz = min(size - count, cnt_to_end);
 794                 pch_uart_hal_write(priv, &xmit->buf[xmit->tail], sz);
 795                 xmit->tail = (xmit->tail + sz) & (UART_XMIT_SIZE - 1);
 796                 count += sz;
 797         } while (!uart_circ_empty(xmit) && count < size);
 798
 799 pop_tx_end:
 800         dev_dbg(priv->port.dev, "%d characters. Remained %d characters.(%lu)\n",
 801                  count, size - count, jiffies);
 802
 803         return count;
 804 }
 805
 806 static int handle_rx_to(struct eg20t_port *priv)
 807 {
 808         struct pch_uart_buffer *buf;
 809         int rx_size;
 810         int ret;
 811         if (!priv->start_rx) {
 812                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT);
 813                 return 0;
 814         }
 815         buf = &priv->rxbuf;
 816         do {
 817                 rx_size = pch_uart_hal_read(priv, buf->buf, buf->size);
 818                 ret = push_rx(priv, buf->buf, rx_size);
 819                 if (ret)
 820                         return 0;
 821         } while (rx_size == buf->size);
 822
 823         return PCH_UART_HANDLED_RX_INT;
 824 }
 825
 826 static int handle_rx(struct eg20t_port *priv)
 827 {
 828         return handle_rx_to(priv);
 829 }
 830
 831 static int dma_handle_rx(struct eg20t_port *priv)
 832 {
 833         struct uart_port *port = &priv->port;
 834         struct dma_async_tx_descriptor *desc;
 835         struct scatterlist *sg;
 836
 837         priv = container_of(port, struct eg20t_port, port);
 838         sg = &priv->sg_rx;
 839
 840         sg_init_table(&priv->sg_rx, 1); /* Initialize SG table */
 841
 842         sg_dma_len(sg) = priv->trigger_level;
 843
 844         sg_set_page(&priv->sg_rx, virt_to_page(priv->rx_buf_virt),
 845                      sg_dma_len(sg), (unsigned long)priv->rx_buf_virt &
 846                      ~PAGE_MASK);
 847
 848         sg_dma_address(sg) = priv->rx_buf_dma;
 849
 850         desc = dmaengine_prep_slave_sg(priv->chan_rx,
 851                         sg, 1, DMA_DEV_TO_MEM,
 852                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 853
 854         if (!desc)
 855                 return 0;
 856
 857         priv->desc_rx = desc;
 858         desc->callback = pch_dma_rx_complete;
 859         desc->callback_param = priv;
 860         desc->tx_submit(desc);
 861         dma_async_issue_pending(priv->chan_rx);
 862
 863         return PCH_UART_HANDLED_RX_INT;
 864 }
 865
 866 static unsigned int handle_tx(struct eg20t_port *priv)
 867 {
 868         struct uart_port *port = &priv->port;
 869         struct circ_buf *xmit = &port->state->xmit;
 870         int fifo_size;
 871         int tx_size;
 872         int size;
 873         int tx_empty;
 874
 875         if (!priv->start_tx) {
 876                 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
 877                         __func__, jiffies);
 878                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 879                 priv->tx_empty = 1;
 880                 return 0;
 881         }
 882
 883         fifo_size = max(priv->fifo_size, 1);
 884         tx_empty = 1;
 885         if (pop_tx_x(priv, xmit->buf)) {
 886                 pch_uart_hal_write(priv, xmit->buf, 1);
 887                 port->icount.tx++;
 888                 tx_empty = 0;
 889                 fifo_size--;
 890         }
 891         size = min(xmit->head - xmit->tail, fifo_size);
 892         if (size < 0)
 893                 size = fifo_size;
 894
 895         tx_size = pop_tx(priv, size);
 896         if (tx_size > 0) {
 897                 port->icount.tx += tx_size;
 898                 tx_empty = 0;
 899         }
 900
 901         priv->tx_empty = tx_empty;
 902
 903         if (tx_empty) {
 904                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 905                 uart_write_wakeup(port);
 906         }
 907
 908         return PCH_UART_HANDLED_TX_INT;
 909 }
 910
 911 static unsigned int dma_handle_tx(struct eg20t_port *priv)
 912 {
 913         struct uart_port *port = &priv->port;
 914         struct circ_buf *xmit = &port->state->xmit;
 915         struct scatterlist *sg;
 916         int nent;
 917         int fifo_size;
 918         int tx_empty;
 919         struct dma_async_tx_descriptor *desc;
 920         int num;
 921         int i;
 922         int bytes;
 923         int size;
 924         int rem;
 925
 926         if (!priv->start_tx) {
 927                 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
 928                         __func__, jiffies);
 929                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 930                 priv->tx_empty = 1;
 931                 return 0;
 932         }
 933
 934         if (priv->tx_dma_use) {
 935                 dev_dbg(priv->port.dev, "%s:Tx is not completed. (%lu)\n",
 936                         __func__, jiffies);
 937                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 938                 priv->tx_empty = 1;
 939                 return 0;
 940         }
 941
 942         fifo_size = max(priv->fifo_size, 1);
 943         tx_empty = 1;
 944         if (pop_tx_x(priv, xmit->buf)) {
 945                 pch_uart_hal_write(priv, xmit->buf, 1);
 946                 port->icount.tx++;
 947                 tx_empty = 0;
 948                 fifo_size--;
 949         }
 950
 951         bytes = min((int)CIRC_CNT(xmit->head, xmit->tail,
 952                              UART_XMIT_SIZE), CIRC_CNT_TO_END(xmit->head,
 953                              xmit->tail, UART_XMIT_SIZE));
 954         if (!bytes) {
 955                 dev_dbg(priv->port.dev, "%s 0 bytes return\n", __func__);
 956                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 957                 uart_write_wakeup(port);
 958                 return 0;
 959         }
 960
 961         if (bytes > fifo_size) {
 962                 num = bytes / fifo_size + 1;
 963                 size = fifo_size;
 964                 rem = bytes % fifo_size;
 965         } else {
 966                 num = 1;
 967                 size = bytes;
 968                 rem = bytes;
 969         }
 970
 971         dev_dbg(priv->port.dev, "%s num=%d size=%d rem=%d\n",
 972                 __func__, num, size, rem);
 973
 974         priv->tx_dma_use = 1;
 975
 976         priv->sg_tx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC);
 977
 978         sg_init_table(priv->sg_tx_p, num); /* Initialize SG table */
 979         sg = priv->sg_tx_p;
 980
 981         for (i = 0; i < num; i++, sg++) {
 982                 if (i == (num - 1))
 983                         sg_set_page(sg, virt_to_page(xmit->buf),
 984                                     rem, fifo_size * i);
 985                 else
 986                         sg_set_page(sg, virt_to_page(xmit->buf),
 987                                     size, fifo_size * i);
 988         }
 989
 990         sg = priv->sg_tx_p;
 991         nent = dma_map_sg(port->dev, sg, num, DMA_TO_DEVICE);
 992         if (!nent) {
 993                 dev_err(priv->port.dev, "%s:dma_map_sg Failed\n", __func__);
 994                 return 0;
 995         }
 996         priv->nent = nent;
 997
 998         for (i = 0; i < nent; i++, sg++) {
 999                 sg->offset = (xmit->tail & (UART_XMIT_SIZE - 1)) +
1000                               fifo_size * i;
1001                 sg_dma_address(sg) = (sg_dma_address(sg) &
1002                                     ~(UART_XMIT_SIZE - 1)) + sg->offset;
1003                 if (i == (nent - 1))
1004                         sg_dma_len(sg) = rem;
1005                 else
1006                         sg_dma_len(sg) = size;
1007         }
1008
1009         desc = dmaengine_prep_slave_sg(priv->chan_tx,
1010                                         priv->sg_tx_p, nent, DMA_MEM_TO_DEV,
1011                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1012         if (!desc) {
1013                 dev_err(priv->port.dev, "%s:device_prep_slave_sg Failed\n",
1014                         __func__);
1015                 return 0;
1016         }
1017         dma_sync_sg_for_device(port->dev, priv->sg_tx_p, nent, DMA_TO_DEVICE);
1018         priv->desc_tx = desc;
1019         desc->callback = pch_dma_tx_complete;
1020         desc->callback_param = priv;
1021
1022         desc->tx_submit(desc);
1023
1024         dma_async_issue_pending(priv->chan_tx);
1025
1026         return PCH_UART_HANDLED_TX_INT;
1027 }
1028
1029 static void pch_uart_err_ir(struct eg20t_port *priv, unsigned int lsr)
1030 {
1031         u8 fcr = ioread8(priv->membase + UART_FCR);
1032
1033         /* Reset FIFO */
1034         fcr |= UART_FCR_CLEAR_RCVR;
1035         iowrite8(fcr, priv->membase + UART_FCR);
1036
1037         if (lsr & PCH_UART_LSR_ERR)
1038                 dev_err(&priv->pdev->dev, "Error data in FIFO\n");
1039
1040         if (lsr & UART_LSR_FE)
1041                 dev_err(&priv->pdev->dev, "Framing Error\n");
1042
1043         if (lsr & UART_LSR_PE)
1044                 dev_err(&priv->pdev->dev, "Parity Error\n");
1045
1046         if (lsr & UART_LSR_OE)
1047                 dev_err(&priv->pdev->dev, "Overrun Error\n");
1048 }
1049
1050 static irqreturn_t pch_uart_interrupt(int irq, void *dev_id)
1051 {
1052         struct eg20t_port *priv = dev_id;
1053         unsigned int handled;
1054         u8 lsr;
1055         int ret = 0;
1056         unsigned char iid;
1057         unsigned long flags;
1058         int next = 1;
1059         u8 msr;
1060
1061         spin_lock_irqsave(&priv->port.lock, flags);
1062         handled = 0;
1063         while (next) {
1064                 iid = pch_uart_hal_get_iid(priv);
1065                 if (iid & PCH_UART_IIR_IP) /* No Interrupt */
1066                         break;
1067                 switch (iid) {
1068                 case PCH_UART_IID_RLS:  /* Receiver Line Status */
1069                         lsr = pch_uart_hal_get_line_status(priv);
1070                         if (lsr & (PCH_UART_LSR_ERR | UART_LSR_FE |
1071                                                 UART_LSR_PE | UART_LSR_OE)) {
1072                                 pch_uart_err_ir(priv, lsr);
1073                                 ret = PCH_UART_HANDLED_RX_ERR_INT;
1074                         } else {
1075                                 ret = PCH_UART_HANDLED_LS_INT;
1076                         }
1077                         break;
1078                 case PCH_UART_IID_RDR:  /* Received Data Ready */
1079                         if (priv->use_dma) {
1080                                 pch_uart_hal_disable_interrupt(priv,
1081                                                         PCH_UART_HAL_RX_INT);
1082                                 ret = dma_handle_rx(priv);
1083                                 if (!ret)
1084                                         pch_uart_hal_enable_interrupt(priv,
1085                                                         PCH_UART_HAL_RX_INT);
1086                         } else {
1087                                 ret = handle_rx(priv);
1088                         }
1089                         break;
1090                 case PCH_UART_IID_RDR_TO:       /* Received Data Ready
1091                                                    (FIFO Timeout) */
1092                         ret = handle_rx_to(priv);
1093                         break;
1094                 case PCH_UART_IID_THRE: /* Transmitter Holding Register
1095                                                    Empty */
1096                         if (priv->use_dma)
1097                                 ret = dma_handle_tx(priv);
1098                         else
1099                                 ret = handle_tx(priv);
1100                         break;
1101                 case PCH_UART_IID_MS:   /* Modem Status */
1102                         msr = pch_uart_hal_get_modem(priv);
1103                         next = 0; /* MS ir prioirty is the lowest. So, MS ir
1104                                      means final interrupt */
1105                         if ((msr & UART_MSR_ANY_DELTA) == 0)
1106                                 break;
1107                         ret |= PCH_UART_HANDLED_MS_INT;
1108                         break;
1109                 default:        /* Never junp to this label */
1110                         dev_err(priv->port.dev, "%s:iid=%02x (%lu)\n", __func__,
1111                                 iid, jiffies);
1112                         ret = -1;
1113                         next = 0;
1114                         break;
1115                 }
1116                 handled |= (unsigned int)ret;
1117         }
1118
1119         spin_unlock_irqrestore(&priv->port.lock, flags);
1120         return IRQ_RETVAL(handled);
1121 }
1122
1123 /* This function tests whether the transmitter fifo and shifter for the port
1124                                                 described by 'port' is empty. */
1125 static unsigned int pch_uart_tx_empty(struct uart_port *port)
1126 {
1127         struct eg20t_port *priv;
1128
1129         priv = container_of(port, struct eg20t_port, port);
1130         if (priv->tx_empty)
1131                 return TIOCSER_TEMT;
1132         else
1133                 return 0;
1134 }
1135
1136 /* Returns the current state of modem control inputs. */
1137 static unsigned int pch_uart_get_mctrl(struct uart_port *port)
1138 {
1139         struct eg20t_port *priv;
1140         u8 modem;
1141         unsigned int ret = 0;
1142
1143         priv = container_of(port, struct eg20t_port, port);
1144         modem = pch_uart_hal_get_modem(priv);
1145
1146         if (modem & UART_MSR_DCD)
1147                 ret |= TIOCM_CAR;
1148
1149         if (modem & UART_MSR_RI)
1150                 ret |= TIOCM_RNG;
1151
1152         if (modem & UART_MSR_DSR)
1153                 ret |= TIOCM_DSR;
1154
1155         if (modem & UART_MSR_CTS)
1156                 ret |= TIOCM_CTS;
1157
1158         return ret;
1159 }
1160
1161 static void pch_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1162 {
1163         u32 mcr = 0;
1164         struct eg20t_port *priv = container_of(port, struct eg20t_port, port);
1165
1166         if (mctrl & TIOCM_DTR)
1167                 mcr |= UART_MCR_DTR;
1168         if (mctrl & TIOCM_RTS)
1169                 mcr |= UART_MCR_RTS;
1170         if (mctrl & TIOCM_LOOP)
1171                 mcr |= UART_MCR_LOOP;
1172
1173         if (priv->mcr & UART_MCR_AFE)
1174                 mcr |= UART_MCR_AFE;
1175
1176         if (mctrl)
1177                 iowrite8(mcr, priv->membase + UART_MCR);
1178 }
1179
1180 static void pch_uart_stop_tx(struct uart_port *port)
1181 {
1182         struct eg20t_port *priv;
1183         priv = container_of(port, struct eg20t_port, port);
1184         priv->start_tx = 0;
1185         priv->tx_dma_use = 0;
1186 }
1187
1188 static void pch_uart_start_tx(struct uart_port *port)
1189 {
1190         struct eg20t_port *priv;
1191
1192         priv = container_of(port, struct eg20t_port, port);
1193
1194         if (priv->use_dma) {
1195                 if (priv->tx_dma_use) {
1196                         dev_dbg(priv->port.dev, "%s : Tx DMA is NOT empty.\n",
1197                                 __func__);
1198                         return;
1199                 }
1200         }
1201
1202         priv->start_tx = 1;
1203         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
1204 }
1205
1206 static void pch_uart_stop_rx(struct uart_port *port)
1207 {
1208         struct eg20t_port *priv;
1209         priv = container_of(port, struct eg20t_port, port);
1210         priv->start_rx = 0;
1211         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT);
1212 }
1213
1214 /* Enable the modem status interrupts. */
1215 static void pch_uart_enable_ms(struct uart_port *port)
1216 {
1217         struct eg20t_port *priv;
1218         priv = container_of(port, struct eg20t_port, port);
1219         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_MS_INT);
1220 }
1221
1222 /* Control the transmission of a break signal. */
1223 static void pch_uart_break_ctl(struct uart_port *port, int ctl)
1224 {
1225         struct eg20t_port *priv;
1226         unsigned long flags;
1227
1228         priv = container_of(port, struct eg20t_port, port);
1229         spin_lock_irqsave(&port->lock, flags);
1230         pch_uart_hal_set_break(priv, ctl);
1231         spin_unlock_irqrestore(&port->lock, flags);
1232 }
1233
1234 /* Grab any interrupt resources and initialise any low level driver state. */
1235 static int pch_uart_startup(struct uart_port *port)
1236 {
1237         struct eg20t_port *priv;
1238         int ret;
1239         int fifo_size;
1240         int trigger_level;
1241
1242         priv = container_of(port, struct eg20t_port, port);
1243         priv->tx_empty = 1;
1244
1245         if (port->uartclk)
1246                 priv->uartclk = port->uartclk;
1247         else
1248                 port->uartclk = priv->uartclk;
1249
1250         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1251         ret = pch_uart_hal_set_line(priv, default_baud,
1252                               PCH_UART_HAL_PARITY_NONE, PCH_UART_HAL_8BIT,
1253                               PCH_UART_HAL_STB1);
1254         if (ret)
1255                 return ret;
1256
1257         switch (priv->fifo_size) {
1258         case 256:
1259                 fifo_size = PCH_UART_HAL_FIFO256;
1260                 break;
1261         case 64:
1262                 fifo_size = PCH_UART_HAL_FIFO64;
1263                 break;
1264         case 16:
1265                 fifo_size = PCH_UART_HAL_FIFO16;
1266         case 1:
1267         default:
1268                 fifo_size = PCH_UART_HAL_FIFO_DIS;
1269                 break;
1270         }
1271
1272         switch (priv->trigger) {
1273         case PCH_UART_HAL_TRIGGER1:
1274                 trigger_level = 1;
1275                 break;
1276         case PCH_UART_HAL_TRIGGER_L:
1277                 trigger_level = priv->fifo_size / 4;
1278                 break;
1279         case PCH_UART_HAL_TRIGGER_M:
1280                 trigger_level = priv->fifo_size / 2;
1281                 break;
1282         case PCH_UART_HAL_TRIGGER_H:
1283         default:
1284                 trigger_level = priv->fifo_size - (priv->fifo_size / 8);
1285                 break;
1286         }
1287
1288         priv->trigger_level = trigger_level;
1289         ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1290                                     fifo_size, priv->trigger);
1291         if (ret < 0)
1292                 return ret;
1293
1294         ret = request_irq(priv->port.irq, pch_uart_interrupt, IRQF_SHARED,
1295                         KBUILD_MODNAME, priv);
1296         if (ret < 0)
1297                 return ret;
1298
1299         if (priv->use_dma)
1300                 pch_request_dma(port);
1301
1302         priv->start_rx = 1;
1303         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT);
1304         uart_update_timeout(port, CS8, default_baud);
1305
1306         return 0;
1307 }
1308
1309 static void pch_uart_shutdown(struct uart_port *port)
1310 {
1311         struct eg20t_port *priv;
1312         int ret;
1313
1314         priv = container_of(port, struct eg20t_port, port);
1315         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1316         pch_uart_hal_fifo_reset(priv, PCH_UART_HAL_CLR_ALL_FIFO);
1317         ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1318                               PCH_UART_HAL_FIFO_DIS, PCH_UART_HAL_TRIGGER1);
1319         if (ret)
1320                 dev_err(priv->port.dev,
1321                         "pch_uart_hal_set_fifo Failed(ret=%d)\n", ret);
1322
1323         pch_free_dma(port);
1324
1325         free_irq(priv->port.irq, priv);
1326 }
1327
1328 /* Change the port parameters, including word length, parity, stop
1329  *bits.  Update read_status_mask and ignore_status_mask to indicate
1330  *the types of events we are interested in receiving.  */
1331 static void pch_uart_set_termios(struct uart_port *port,
1332                                  struct ktermios *termios, struct ktermios *old)
1333 {
1334         int baud;
1335         int rtn;
1336         unsigned int parity, bits, stb;
1337         struct eg20t_port *priv;
1338         unsigned long flags;
1339
1340         priv = container_of(port, struct eg20t_port, port);
1341         switch (termios->c_cflag & CSIZE) {
1342         case CS5:
1343                 bits = PCH_UART_HAL_5BIT;
1344                 break;
1345         case CS6:
1346                 bits = PCH_UART_HAL_6BIT;
1347                 break;
1348         case CS7:
1349                 bits = PCH_UART_HAL_7BIT;
1350                 break;
1351         default:                /* CS8 */
1352                 bits = PCH_UART_HAL_8BIT;
1353                 break;
1354         }
1355         if (termios->c_cflag & CSTOPB)
1356                 stb = PCH_UART_HAL_STB2;
1357         else
1358                 stb = PCH_UART_HAL_STB1;
1359
1360         if (termios->c_cflag & PARENB) {
1361                 if (!(termios->c_cflag & PARODD))
1362                         parity = PCH_UART_HAL_PARITY_ODD;
1363                 else
1364                         parity = PCH_UART_HAL_PARITY_EVEN;
1365
1366         } else
1367                 parity = PCH_UART_HAL_PARITY_NONE;
1368
1369         /* Only UART0 has auto hardware flow function */
1370         if ((termios->c_cflag & CRTSCTS) && (priv->fifo_size == 256))
1371                 priv->mcr |= UART_MCR_AFE;
1372         else
1373                 priv->mcr &= ~UART_MCR_AFE;
1374
1375         termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */
1376
1377         baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
1378
1379         spin_lock_irqsave(&port->lock, flags);
1380
1381         uart_update_timeout(port, termios->c_cflag, baud);
1382         rtn = pch_uart_hal_set_line(priv, baud, parity, bits, stb);
1383         if (rtn)
1384                 goto out;
1385
1386         pch_uart_set_mctrl(&priv->port, priv->port.mctrl);
1387         /* Don't rewrite B0 */
1388         if (tty_termios_baud_rate(termios))
1389                 tty_termios_encode_baud_rate(termios, baud, baud);
1390
1391 out:
1392         spin_unlock_irqrestore(&port->lock, flags);
1393 }
1394
1395 static const char *pch_uart_type(struct uart_port *port)
1396 {
1397         return KBUILD_MODNAME;
1398 }
1399
1400 static void pch_uart_release_port(struct uart_port *port)
1401 {
1402         struct eg20t_port *priv;
1403
1404         priv = container_of(port, struct eg20t_port, port);
1405         pci_iounmap(priv->pdev, priv->membase);
1406         pci_release_regions(priv->pdev);
1407 }
1408
1409 static int pch_uart_request_port(struct uart_port *port)
1410 {
1411         struct eg20t_port *priv;
1412         int ret;
1413         void __iomem *membase;
1414
1415         priv = container_of(port, struct eg20t_port, port);
1416         ret = pci_request_regions(priv->pdev, KBUILD_MODNAME);
1417         if (ret < 0)
1418                 return -EBUSY;
1419
1420         membase = pci_iomap(priv->pdev, 1, 0);
1421         if (!membase) {
1422                 pci_release_regions(priv->pdev);
1423                 return -EBUSY;
1424         }
1425         priv->membase = port->membase = membase;
1426
1427         return 0;
1428 }
1429
1430 static void pch_uart_config_port(struct uart_port *port, int type)
1431 {
1432         struct eg20t_port *priv;
1433
1434         priv = container_of(port, struct eg20t_port, port);
1435         if (type & UART_CONFIG_TYPE) {
1436                 port->type = priv->port_type;
1437                 pch_uart_request_port(port);
1438         }
1439 }
1440
1441 static int pch_uart_verify_port(struct uart_port *port,
1442                                 struct serial_struct *serinfo)
1443 {
1444         struct eg20t_port *priv;
1445
1446         priv = container_of(port, struct eg20t_port, port);
1447         if (serinfo->flags & UPF_LOW_LATENCY) {
1448                 dev_info(priv->port.dev,
1449                         "PCH UART : Use PIO Mode (without DMA)\n");
1450                 priv->use_dma = 0;
1451                 serinfo->flags &= ~UPF_LOW_LATENCY;
1452         } else {
1453 #ifndef CONFIG_PCH_DMA
1454                 dev_err(priv->port.dev, "%s : PCH DMA is not Loaded.\n",
1455                         __func__);
1456                 return -EOPNOTSUPP;
1457 #endif
1458                 dev_info(priv->port.dev, "PCH UART : Use DMA Mode\n");
1459                 if (!priv->use_dma)
1460                         pch_request_dma(port);
1461                 priv->use_dma = 1;
1462         }
1463
1464         return 0;
1465 }
1466
1467 static struct uart_ops pch_uart_ops = {
1468         .tx_empty = pch_uart_tx_empty,
1469         .set_mctrl = pch_uart_set_mctrl,
1470         .get_mctrl = pch_uart_get_mctrl,
1471         .stop_tx = pch_uart_stop_tx,
1472         .start_tx = pch_uart_start_tx,
1473         .stop_rx = pch_uart_stop_rx,
1474         .enable_ms = pch_uart_enable_ms,
1475         .break_ctl = pch_uart_break_ctl,
1476         .startup = pch_uart_startup,
1477         .shutdown = pch_uart_shutdown,
1478         .set_termios = pch_uart_set_termios,
1479 /*      .pm             = pch_uart_pm,          Not supported yet */
1480 /*      .set_wake       = pch_uart_set_wake,    Not supported yet */
1481         .type = pch_uart_type,
1482         .release_port = pch_uart_release_port,
1483         .request_port = pch_uart_request_port,
1484         .config_port = pch_uart_config_port,
1485         .verify_port = pch_uart_verify_port
1486 };
1487
1488 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1489
1490 /*
1491  *      Wait for transmitter & holding register to empty
1492  */
1493 static void wait_for_xmitr(struct eg20t_port *up, int bits)
1494 {
1495         unsigned int status, tmout = 10000;
1496
1497         /* Wait up to 10ms for the character(s) to be sent. */
1498         for (;;) {
1499                 status = ioread8(up->membase + UART_LSR);
1500
1501                 if ((status & bits) == bits)
1502                         break;
1503                 if (--tmout == 0)
1504                         break;
1505                 udelay(1);
1506         }
1507
1508         /* Wait up to 1s for flow control if necessary */
1509         if (up->port.flags & UPF_CONS_FLOW) {
1510                 unsigned int tmout;
1511                 for (tmout = 1000000; tmout; tmout--) {
1512                         unsigned int msr = ioread8(up->membase + UART_MSR);
1513                         if (msr & UART_MSR_CTS)
1514                                 break;
1515                         udelay(1);
1516                         touch_nmi_watchdog();
1517                 }
1518         }
1519 }
1520
1521 static void pch_console_putchar(struct uart_port *port, int ch)
1522 {
1523         struct eg20t_port *priv =
1524                 container_of(port, struct eg20t_port, port);
1525
1526         wait_for_xmitr(priv, UART_LSR_THRE);
1527         iowrite8(ch, priv->membase + PCH_UART_THR);
1528 }
1529
1530 /*
1531  *      Print a string to the serial port trying not to disturb
1532  *      any possible real use of the port...
1533  *
1534  *      The console_lock must be held when we get here.
1535  */
1536 static void
1537 pch_console_write(struct console *co, const char *s, unsigned int count)
1538 {
1539         struct eg20t_port *priv;
1540         unsigned long flags;
1541         u8 ier;
1542         int locked = 1;
1543
1544         priv = pch_uart_ports[co->index];
1545
1546         touch_nmi_watchdog();
1547
1548         local_irq_save(flags);
1549         if (priv->port.sysrq) {
1550                 /* serial8250_handle_port() already took the lock */
1551                 locked = 0;
1552         } else if (oops_in_progress) {
1553                 locked = spin_trylock(&priv->port.lock);
1554         } else
1555                 spin_lock(&priv->port.lock);
1556
1557         /*
1558          *      First save the IER then disable the interrupts
1559          */
1560         ier = ioread8(priv->membase + UART_IER);
1561
1562         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1563
1564         uart_console_write(&priv->port, s, count, pch_console_putchar);
1565
1566         /*
1567          *      Finally, wait for transmitter to become empty
1568          *      and restore the IER
1569          */
1570         wait_for_xmitr(priv, BOTH_EMPTY);
1571         iowrite8(ier, priv->membase + UART_IER);
1572
1573         if (locked)
1574                 spin_unlock(&priv->port.lock);
1575         local_irq_restore(flags);
1576 }
1577
1578 static int __init pch_console_setup(struct console *co, char *options)
1579 {
1580         struct uart_port *port;
1581         int baud = default_baud;
1582         int bits = 8;
1583         int parity = 'n';
1584         int flow = 'n';
1585
1586         /*
1587          * Check whether an invalid uart number has been specified, and
1588          * if so, search for the first available port that does have
1589          * console support.
1590          */
1591         if (co->index >= PCH_UART_NR)
1592                 co->index = 0;
1593         port = &pch_uart_ports[co->index]->port;
1594
1595         if (!port || (!port->iobase && !port->membase))
1596                 return -ENODEV;
1597
1598         port->uartclk = pch_uart_get_uartclk();
1599
1600         if (options)
1601                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1602
1603         return uart_set_options(port, co, baud, parity, bits, flow);
1604 }
1605
1606 static struct uart_driver pch_uart_driver;
1607
1608 static struct console pch_console = {
1609         .name           = PCH_UART_DRIVER_DEVICE,
1610         .write          = pch_console_write,
1611         .device         = uart_console_device,
1612         .setup          = pch_console_setup,
1613         .flags          = CON_PRINTBUFFER | CON_ANYTIME,
1614         .index          = -1,
1615         .data           = &pch_uart_driver,
1616 };
1617
1618 #define PCH_CONSOLE     (&pch_console)
1619 #else
1620 #define PCH_CONSOLE     NULL
1621 #endif
1622
1623 static struct uart_driver pch_uart_driver = {
1624         .owner = THIS_MODULE,
1625         .driver_name = KBUILD_MODNAME,
1626         .dev_name = PCH_UART_DRIVER_DEVICE,
1627         .major = 0,
1628         .minor = 0,
1629         .nr = PCH_UART_NR,
1630         .cons = PCH_CONSOLE,
1631 };
1632
1633 static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev,
1634                                              const struct pci_device_id *id)
1635 {
1636         struct eg20t_port *priv;
1637         int ret;
1638         unsigned int iobase;
1639         unsigned int mapbase;
1640         unsigned char *rxbuf;
1641         int fifosize;
1642         int port_type;
1643         struct pch_uart_driver_data *board;
1644         char name[32];  /* for debugfs file name */
1645
1646         board = &drv_dat[id->driver_data];
1647         port_type = board->port_type;
1648
1649         priv = kzalloc(sizeof(struct eg20t_port), GFP_KERNEL);
1650         if (priv == NULL)
1651                 goto init_port_alloc_err;
1652
1653         rxbuf = (unsigned char *)__get_free_page(GFP_KERNEL);
1654         if (!rxbuf)
1655                 goto init_port_free_txbuf;
1656
1657         switch (port_type) {
1658         case PORT_UNKNOWN:
1659                 fifosize = 256; /* EG20T/ML7213: UART0 */
1660                 break;
1661         case PORT_8250:
1662                 fifosize = 64; /* EG20T:UART1~3  ML7213: UART1~2*/
1663                 break;
1664         default:
1665                 dev_err(&pdev->dev, "Invalid Port Type(=%d)\n", port_type);
1666                 goto init_port_hal_free;
1667         }
1668
1669         pci_enable_msi(pdev);
1670         pci_set_master(pdev);
1671
1672         iobase = pci_resource_start(pdev, 0);
1673         mapbase = pci_resource_start(pdev, 1);
1674         priv->mapbase = mapbase;
1675         priv->iobase = iobase;
1676         priv->pdev = pdev;
1677         priv->tx_empty = 1;
1678         priv->rxbuf.buf = rxbuf;
1679         priv->rxbuf.size = PAGE_SIZE;
1680
1681         priv->fifo_size = fifosize;
1682         priv->uartclk = pch_uart_get_uartclk();
1683         priv->port_type = PORT_MAX_8250 + port_type + 1;
1684         priv->port.dev = &pdev->dev;
1685         priv->port.iobase = iobase;
1686         priv->port.membase = NULL;
1687         priv->port.mapbase = mapbase;
1688         priv->port.irq = pdev->irq;
1689         priv->port.iotype = UPIO_PORT;
1690         priv->port.ops = &pch_uart_ops;
1691         priv->port.flags = UPF_BOOT_AUTOCONF;
1692         priv->port.fifosize = fifosize;
1693         priv->port.line = board->line_no;
1694         priv->trigger = PCH_UART_HAL_TRIGGER_M;
1695
1696         spin_lock_init(&priv->port.lock);
1697
1698         pci_set_drvdata(pdev, priv);
1699         priv->trigger_level = 1;
1700         priv->fcr = 0;
1701
1702 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1703         pch_uart_ports[board->line_no] = priv;
1704 #endif
1705         ret = uart_add_one_port(&pch_uart_driver, &priv->port);
1706         if (ret < 0)
1707                 goto init_port_hal_free;
1708
1709 #ifdef CONFIG_DEBUG_FS
1710         snprintf(name, sizeof(name), "uart%d_regs", board->line_no);
1711         priv->debugfs = debugfs_create_file(name, S_IFREG | S_IRUGO,
1712                                 NULL, priv, &port_regs_ops);
1713 #endif
1714
1715         return priv;
1716
1717 init_port_hal_free:
1718 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1719         pch_uart_ports[board->line_no] = NULL;
1720 #endif
1721         free_page((unsigned long)rxbuf);
1722 init_port_free_txbuf:
1723         kfree(priv);
1724 init_port_alloc_err:
1725
1726         return NULL;
1727 }
1728
1729 static void pch_uart_exit_port(struct eg20t_port *priv)
1730 {
1731
1732 #ifdef CONFIG_DEBUG_FS
1733         if (priv->debugfs)
1734                 debugfs_remove(priv->debugfs);
1735 #endif
1736         uart_remove_one_port(&pch_uart_driver, &priv->port);
1737         pci_set_drvdata(priv->pdev, NULL);
1738         free_page((unsigned long)priv->rxbuf.buf);
1739 }
1740
1741 static void pch_uart_pci_remove(struct pci_dev *pdev)
1742 {
1743         struct eg20t_port *priv = pci_get_drvdata(pdev);
1744
1745         pci_disable_msi(pdev);
1746
1747 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1748         pch_uart_ports[priv->port.line] = NULL;
1749 #endif
1750         pch_uart_exit_port(priv);
1751         pci_disable_device(pdev);
1752         kfree(priv);
1753         return;
1754 }
1755 #ifdef CONFIG_PM
1756 static int pch_uart_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1757 {
1758         struct eg20t_port *priv = pci_get_drvdata(pdev);
1759
1760         uart_suspend_port(&pch_uart_driver, &priv->port);
1761
1762         pci_save_state(pdev);
1763         pci_set_power_state(pdev, pci_choose_state(pdev, state));
1764         return 0;
1765 }
1766
1767 static int pch_uart_pci_resume(struct pci_dev *pdev)
1768 {
1769         struct eg20t_port *priv = pci_get_drvdata(pdev);
1770         int ret;
1771
1772         pci_set_power_state(pdev, PCI_D0);
1773         pci_restore_state(pdev);
1774
1775         ret = pci_enable_device(pdev);
1776         if (ret) {
1777                 dev_err(&pdev->dev,
1778                 "%s-pci_enable_device failed(ret=%d) ", __func__, ret);
1779                 return ret;
1780         }
1781
1782         uart_resume_port(&pch_uart_driver, &priv->port);
1783
1784         return 0;
1785 }
1786 #else
1787 #define pch_uart_pci_suspend NULL
1788 #define pch_uart_pci_resume NULL
1789 #endif
1790
1791 static DEFINE_PCI_DEVICE_TABLE(pch_uart_pci_id) = {
1792         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8811),
1793          .driver_data = pch_et20t_uart0},
1794         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8812),
1795          .driver_data = pch_et20t_uart1},
1796         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8813),
1797          .driver_data = pch_et20t_uart2},
1798         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8814),
1799          .driver_data = pch_et20t_uart3},
1800         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8027),
1801          .driver_data = pch_ml7213_uart0},
1802         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8028),
1803          .driver_data = pch_ml7213_uart1},
1804         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8029),
1805          .driver_data = pch_ml7213_uart2},
1806         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800C),
1807          .driver_data = pch_ml7223_uart0},
1808         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800D),
1809          .driver_data = pch_ml7223_uart1},
1810         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8811),
1811          .driver_data = pch_ml7831_uart0},
1812         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8812),
1813          .driver_data = pch_ml7831_uart1},
1814         {0,},
1815 };
1816
1817 static int __devinit pch_uart_pci_probe(struct pci_dev *pdev,
1818                                         const struct pci_device_id *id)
1819 {
1820         int ret;
1821         struct eg20t_port *priv;
1822
1823         ret = pci_enable_device(pdev);
1824         if (ret < 0)
1825                 goto probe_error;
1826
1827         priv = pch_uart_init_port(pdev, id);
1828         if (!priv) {
1829                 ret = -EBUSY;
1830                 goto probe_disable_device;
1831         }
1832         pci_set_drvdata(pdev, priv);
1833
1834         return ret;
1835
1836 probe_disable_device:
1837         pci_disable_msi(pdev);
1838         pci_disable_device(pdev);
1839 probe_error:
1840         return ret;
1841 }
1842
1843 static struct pci_driver pch_uart_pci_driver = {
1844         .name = "pch_uart",
1845         .id_table = pch_uart_pci_id,
1846         .probe = pch_uart_pci_probe,
1847         .remove = __devexit_p(pch_uart_pci_remove),
1848         .suspend = pch_uart_pci_suspend,
1849         .resume = pch_uart_pci_resume,
1850 };
1851
1852 static int __init pch_uart_module_init(void)
1853 {
1854         int ret;
1855
1856         /* register as UART driver */
1857         ret = uart_register_driver(&pch_uart_driver);
1858         if (ret < 0)
1859                 return ret;
1860
1861         /* register as PCI driver */
1862         ret = pci_register_driver(&pch_uart_pci_driver);
1863         if (ret < 0)
1864                 uart_unregister_driver(&pch_uart_driver);
1865
1866         return ret;
1867 }
1868 module_init(pch_uart_module_init);
1869
1870 static void __exit pch_uart_module_exit(void)
1871 {
1872         pci_unregister_driver(&pch_uart_pci_driver);
1873         uart_unregister_driver(&pch_uart_driver);
1874 }
1875 module_exit(pch_uart_module_exit);
1876
1877 MODULE_LICENSE("GPL v2");
1878 MODULE_DESCRIPTION("Intel EG20T PCH UART PCI Driver");
1879 module_param(default_baud, uint, S_IRUGO);
1880 MODULE_PARM_DESC(default_baud,
1881                  "Default BAUD for initial driver state and console (default 9600)");
1882 module_param(user_uartclk, uint, S_IRUGO);
1883 MODULE_PARM_DESC(user_uartclk,
1884                  "Override UART default or board specific UART clock");