Pileus Git - ~andy/linux/blob - drivers/tty/serial/lpc32xx_hs.c

   1 /*
   2  * High Speed Serial Ports on NXP LPC32xx SoC
   3  *
   4  * Authors: Kevin Wells <kevin.wells@nxp.com>
   5  *          Roland Stigge <stigge@antcom.de>
   6  *
   7  * Copyright (C) 2010 NXP Semiconductors
   8  * Copyright (C) 2012 Roland Stigge
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  */
  20
  21 #include <linux/module.h>
  22 #include <linux/ioport.h>
  23 #include <linux/init.h>
  24 #include <linux/console.h>
  25 #include <linux/sysrq.h>
  26 #include <linux/tty.h>
  27 #include <linux/tty_flip.h>
  28 #include <linux/serial_core.h>
  29 #include <linux/serial.h>
  30 #include <linux/platform_device.h>
  31 #include <linux/delay.h>
  32 #include <linux/nmi.h>
  33 #include <linux/io.h>
  34 #include <linux/irq.h>
  35 #include <linux/gpio.h>
  36 #include <linux/of.h>
  37 #include <mach/platform.h>
  38 #include <mach/hardware.h>
  39
  40 /*
  41  * High Speed UART register offsets
  42  */
  43 #define LPC32XX_HSUART_FIFO(x)                  ((x) + 0x00)
  44 #define LPC32XX_HSUART_LEVEL(x)                 ((x) + 0x04)
  45 #define LPC32XX_HSUART_IIR(x)                   ((x) + 0x08)
  46 #define LPC32XX_HSUART_CTRL(x)                  ((x) + 0x0C)
  47 #define LPC32XX_HSUART_RATE(x)                  ((x) + 0x10)
  48
  49 #define LPC32XX_HSU_BREAK_DATA                  (1 << 10)
  50 #define LPC32XX_HSU_ERROR_DATA                  (1 << 9)
  51 #define LPC32XX_HSU_RX_EMPTY                    (1 << 8)
  52
  53 #define LPC32XX_HSU_TX_LEV(n)                   (((n) >> 8) & 0xFF)
  54 #define LPC32XX_HSU_RX_LEV(n)                   ((n) & 0xFF)
  55
  56 #define LPC32XX_HSU_TX_INT_SET                  (1 << 6)
  57 #define LPC32XX_HSU_RX_OE_INT                   (1 << 5)
  58 #define LPC32XX_HSU_BRK_INT                     (1 << 4)
  59 #define LPC32XX_HSU_FE_INT                      (1 << 3)
  60 #define LPC32XX_HSU_RX_TIMEOUT_INT              (1 << 2)
  61 #define LPC32XX_HSU_RX_TRIG_INT                 (1 << 1)
  62 #define LPC32XX_HSU_TX_INT                      (1 << 0)
  63
  64 #define LPC32XX_HSU_HRTS_INV                    (1 << 21)
  65 #define LPC32XX_HSU_HRTS_TRIG_8B                (0x0 << 19)
  66 #define LPC32XX_HSU_HRTS_TRIG_16B               (0x1 << 19)
  67 #define LPC32XX_HSU_HRTS_TRIG_32B               (0x2 << 19)
  68 #define LPC32XX_HSU_HRTS_TRIG_48B               (0x3 << 19)
  69 #define LPC32XX_HSU_HRTS_EN                     (1 << 18)
  70 #define LPC32XX_HSU_TMO_DISABLED                (0x0 << 16)
  71 #define LPC32XX_HSU_TMO_INACT_4B                (0x1 << 16)
  72 #define LPC32XX_HSU_TMO_INACT_8B                (0x2 << 16)
  73 #define LPC32XX_HSU_TMO_INACT_16B               (0x3 << 16)
  74 #define LPC32XX_HSU_HCTS_INV                    (1 << 15)
  75 #define LPC32XX_HSU_HCTS_EN                     (1 << 14)
  76 #define LPC32XX_HSU_OFFSET(n)                   ((n) << 9)
  77 #define LPC32XX_HSU_BREAK                       (1 << 8)
  78 #define LPC32XX_HSU_ERR_INT_EN                  (1 << 7)
  79 #define LPC32XX_HSU_RX_INT_EN                   (1 << 6)
  80 #define LPC32XX_HSU_TX_INT_EN                   (1 << 5)
  81 #define LPC32XX_HSU_RX_TL1B                     (0x0 << 2)
  82 #define LPC32XX_HSU_RX_TL4B                     (0x1 << 2)
  83 #define LPC32XX_HSU_RX_TL8B                     (0x2 << 2)
  84 #define LPC32XX_HSU_RX_TL16B                    (0x3 << 2)
  85 #define LPC32XX_HSU_RX_TL32B                    (0x4 << 2)
  86 #define LPC32XX_HSU_RX_TL48B                    (0x5 << 2)
  87 #define LPC32XX_HSU_TX_TLEMPTY                  (0x0 << 0)
  88 #define LPC32XX_HSU_TX_TL0B                     (0x0 << 0)
  89 #define LPC32XX_HSU_TX_TL4B                     (0x1 << 0)
  90 #define LPC32XX_HSU_TX_TL8B                     (0x2 << 0)
  91 #define LPC32XX_HSU_TX_TL16B                    (0x3 << 0)
  92
  93 #define MODNAME "lpc32xx_hsuart"
  94
  95 struct lpc32xx_hsuart_port {
  96         struct uart_port port;
  97 };
  98
  99 #define FIFO_READ_LIMIT 128
 100 #define MAX_PORTS 3
 101 #define LPC32XX_TTY_NAME "ttyTX"
 102 static struct lpc32xx_hsuart_port lpc32xx_hs_ports[MAX_PORTS];
 103
 104 #ifdef CONFIG_SERIAL_HS_LPC32XX_CONSOLE
 105 static void wait_for_xmit_empty(struct uart_port *port)
 106 {
 107         unsigned int timeout = 10000;
 108
 109         do {
 110                 if (LPC32XX_HSU_TX_LEV(readl(LPC32XX_HSUART_LEVEL(
 111                                                         port->membase))) == 0)
 112                         break;
 113                 if (--timeout == 0)
 114                         break;
 115                 udelay(1);
 116         } while (1);
 117 }
 118
 119 static void wait_for_xmit_ready(struct uart_port *port)
 120 {
 121         unsigned int timeout = 10000;
 122
 123         while (1) {
 124                 if (LPC32XX_HSU_TX_LEV(readl(LPC32XX_HSUART_LEVEL(
 125                                                         port->membase))) < 32)
 126                         break;
 127                 if (--timeout == 0)
 128                         break;
 129                 udelay(1);
 130         }
 131 }
 132
 133 static void lpc32xx_hsuart_console_putchar(struct uart_port *port, int ch)
 134 {
 135         wait_for_xmit_ready(port);
 136         writel((u32)ch, LPC32XX_HSUART_FIFO(port->membase));
 137 }
 138
 139 static void lpc32xx_hsuart_console_write(struct console *co, const char *s,
 140                                          unsigned int count)
 141 {
 142         struct lpc32xx_hsuart_port *up = &lpc32xx_hs_ports[co->index];
 143         unsigned long flags;
 144         int locked = 1;
 145
 146         touch_nmi_watchdog();
 147         local_irq_save(flags);
 148         if (up->port.sysrq)
 149                 locked = 0;
 150         else if (oops_in_progress)
 151                 locked = spin_trylock(&up->port.lock);
 152         else
 153                 spin_lock(&up->port.lock);
 154
 155         uart_console_write(&up->port, s, count, lpc32xx_hsuart_console_putchar);
 156         wait_for_xmit_empty(&up->port);
 157
 158         if (locked)
 159                 spin_unlock(&up->port.lock);
 160         local_irq_restore(flags);
 161 }
 162
 163 static int __init lpc32xx_hsuart_console_setup(struct console *co,
 164                                                char *options)
 165 {
 166         struct uart_port *port;
 167         int baud = 115200;
 168         int bits = 8;
 169         int parity = 'n';
 170         int flow = 'n';
 171
 172         if (co->index >= MAX_PORTS)
 173                 co->index = 0;
 174
 175         port = &lpc32xx_hs_ports[co->index].port;
 176         if (!port->membase)
 177                 return -ENODEV;
 178
 179         if (options)
 180                 uart_parse_options(options, &baud, &parity, &bits, &flow);
 181
 182         return uart_set_options(port, co, baud, parity, bits, flow);
 183 }
 184
 185 static struct uart_driver lpc32xx_hsuart_reg;
 186 static struct console lpc32xx_hsuart_console = {
 187         .name           = LPC32XX_TTY_NAME,
 188         .write          = lpc32xx_hsuart_console_write,
 189         .device         = uart_console_device,
 190         .setup          = lpc32xx_hsuart_console_setup,
 191         .flags          = CON_PRINTBUFFER,
 192         .index          = -1,
 193         .data           = &lpc32xx_hsuart_reg,
 194 };
 195
 196 static int __init lpc32xx_hsuart_console_init(void)
 197 {
 198         register_console(&lpc32xx_hsuart_console);
 199         return 0;
 200 }
 201 console_initcall(lpc32xx_hsuart_console_init);
 202
 203 #define LPC32XX_HSUART_CONSOLE (&lpc32xx_hsuart_console)
 204 #else
 205 #define LPC32XX_HSUART_CONSOLE NULL
 206 #endif
 207
 208 static struct uart_driver lpc32xx_hs_reg = {
 209         .owner          = THIS_MODULE,
 210         .driver_name    = MODNAME,
 211         .dev_name       = LPC32XX_TTY_NAME,
 212         .nr             = MAX_PORTS,
 213         .cons           = LPC32XX_HSUART_CONSOLE,
 214 };
 215 static int uarts_registered;
 216
 217 static unsigned int __serial_get_clock_div(unsigned long uartclk,
 218                                            unsigned long rate)
 219 {
 220         u32 div, goodrate, hsu_rate, l_hsu_rate, comprate;
 221         u32 rate_diff;
 222
 223         /* Find the closest divider to get the desired clock rate */
 224         div = uartclk / rate;
 225         goodrate = hsu_rate = (div / 14) - 1;
 226         if (hsu_rate != 0)
 227                 hsu_rate--;
 228
 229         /* Tweak divider */
 230         l_hsu_rate = hsu_rate + 3;
 231         rate_diff = 0xFFFFFFFF;
 232
 233         while (hsu_rate < l_hsu_rate) {
 234                 comprate = uartclk / ((hsu_rate + 1) * 14);
 235                 if (abs(comprate - rate) < rate_diff) {
 236                         goodrate = hsu_rate;
 237                         rate_diff = abs(comprate - rate);
 238                 }
 239
 240                 hsu_rate++;
 241         }
 242         if (hsu_rate > 0xFF)
 243                 hsu_rate = 0xFF;
 244
 245         return goodrate;
 246 }
 247
 248 static void __serial_uart_flush(struct uart_port *port)
 249 {
 250         u32 tmp;
 251         int cnt = 0;
 252
 253         while ((readl(LPC32XX_HSUART_LEVEL(port->membase)) > 0) &&
 254                (cnt++ < FIFO_READ_LIMIT))
 255                 tmp = readl(LPC32XX_HSUART_FIFO(port->membase));
 256 }
 257
 258 static void __serial_lpc32xx_rx(struct uart_port *port)
 259 {
 260         struct tty_port *tport = &port->state->port;
 261         unsigned int tmp, flag;
 262
 263         /* Read data from FIFO and push into terminal */
 264         tmp = readl(LPC32XX_HSUART_FIFO(port->membase));
 265         while (!(tmp & LPC32XX_HSU_RX_EMPTY)) {
 266                 flag = TTY_NORMAL;
 267                 port->icount.rx++;
 268
 269                 if (tmp & LPC32XX_HSU_ERROR_DATA) {
 270                         /* Framing error */
 271                         writel(LPC32XX_HSU_FE_INT,
 272                                LPC32XX_HSUART_IIR(port->membase));
 273                         port->icount.frame++;
 274                         flag = TTY_FRAME;
 275                         tty_insert_flip_char(tport, 0, TTY_FRAME);
 276                 }
 277
 278                 tty_insert_flip_char(tport, (tmp & 0xFF), flag);
 279
 280                 tmp = readl(LPC32XX_HSUART_FIFO(port->membase));
 281         }
 282         tty_flip_buffer_push(tport);
 283 }
 284
 285 static void __serial_lpc32xx_tx(struct uart_port *port)
 286 {
 287         struct circ_buf *xmit = &port->state->xmit;
 288         unsigned int tmp;
 289
 290         if (port->x_char) {
 291                 writel((u32)port->x_char, LPC32XX_HSUART_FIFO(port->membase));
 292                 port->icount.tx++;
 293                 port->x_char = 0;
 294                 return;
 295         }
 296
 297         if (uart_circ_empty(xmit) || uart_tx_stopped(port))
 298                 goto exit_tx;
 299
 300         /* Transfer data */
 301         while (LPC32XX_HSU_TX_LEV(readl(
 302                 LPC32XX_HSUART_LEVEL(port->membase))) < 64) {
 303                 writel((u32) xmit->buf[xmit->tail],
 304                        LPC32XX_HSUART_FIFO(port->membase));
 305                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 306                 port->icount.tx++;
 307                 if (uart_circ_empty(xmit))
 308                         break;
 309         }
 310
 311         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 312                 uart_write_wakeup(port);
 313
 314 exit_tx:
 315         if (uart_circ_empty(xmit)) {
 316                 tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
 317                 tmp &= ~LPC32XX_HSU_TX_INT_EN;
 318                 writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
 319         }
 320 }
 321
 322 static irqreturn_t serial_lpc32xx_interrupt(int irq, void *dev_id)
 323 {
 324         struct uart_port *port = dev_id;
 325         struct tty_port *tport = &port->state->port;
 326         u32 status;
 327
 328         spin_lock(&port->lock);
 329
 330         /* Read UART status and clear latched interrupts */
 331         status = readl(LPC32XX_HSUART_IIR(port->membase));
 332
 333         if (status & LPC32XX_HSU_BRK_INT) {
 334                 /* Break received */
 335                 writel(LPC32XX_HSU_BRK_INT, LPC32XX_HSUART_IIR(port->membase));
 336                 port->icount.brk++;
 337                 uart_handle_break(port);
 338         }
 339
 340         /* Framing error */
 341         if (status & LPC32XX_HSU_FE_INT)
 342                 writel(LPC32XX_HSU_FE_INT, LPC32XX_HSUART_IIR(port->membase));
 343
 344         if (status & LPC32XX_HSU_RX_OE_INT) {
 345                 /* Receive FIFO overrun */
 346                 writel(LPC32XX_HSU_RX_OE_INT,
 347                        LPC32XX_HSUART_IIR(port->membase));
 348                 port->icount.overrun++;
 349                 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
 350                 tty_schedule_flip(tport);
 351         }
 352
 353         /* Data received? */
 354         if (status & (LPC32XX_HSU_RX_TIMEOUT_INT | LPC32XX_HSU_RX_TRIG_INT))
 355                 __serial_lpc32xx_rx(port);
 356
 357         /* Transmit data request? */
 358         if ((status & LPC32XX_HSU_TX_INT) && (!uart_tx_stopped(port))) {
 359                 writel(LPC32XX_HSU_TX_INT, LPC32XX_HSUART_IIR(port->membase));
 360                 __serial_lpc32xx_tx(port);
 361         }
 362
 363         spin_unlock(&port->lock);
 364
 365         return IRQ_HANDLED;
 366 }
 367
 368 /* port->lock is not held.  */
 369 static unsigned int serial_lpc32xx_tx_empty(struct uart_port *port)
 370 {
 371         unsigned int ret = 0;
 372
 373         if (LPC32XX_HSU_TX_LEV(readl(LPC32XX_HSUART_LEVEL(port->membase))) == 0)
 374                 ret = TIOCSER_TEMT;
 375
 376         return ret;
 377 }
 378
 379 /* port->lock held by caller.  */
 380 static void serial_lpc32xx_set_mctrl(struct uart_port *port,
 381                                      unsigned int mctrl)
 382 {
 383         /* No signals are supported on HS UARTs */
 384 }
 385
 386 /* port->lock is held by caller and interrupts are disabled.  */
 387 static unsigned int serial_lpc32xx_get_mctrl(struct uart_port *port)
 388 {
 389         /* No signals are supported on HS UARTs */
 390         return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
 391 }
 392
 393 /* port->lock held by caller.  */
 394 static void serial_lpc32xx_stop_tx(struct uart_port *port)
 395 {
 396         u32 tmp;
 397
 398         tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
 399         tmp &= ~LPC32XX_HSU_TX_INT_EN;
 400         writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
 401 }
 402
 403 /* port->lock held by caller.  */
 404 static void serial_lpc32xx_start_tx(struct uart_port *port)
 405 {
 406         u32 tmp;
 407
 408         __serial_lpc32xx_tx(port);
 409         tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
 410         tmp |= LPC32XX_HSU_TX_INT_EN;
 411         writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
 412 }
 413
 414 /* port->lock held by caller.  */
 415 static void serial_lpc32xx_stop_rx(struct uart_port *port)
 416 {
 417         u32 tmp;
 418
 419         tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
 420         tmp &= ~(LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN);
 421         writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
 422
 423         writel((LPC32XX_HSU_BRK_INT | LPC32XX_HSU_RX_OE_INT |
 424                 LPC32XX_HSU_FE_INT), LPC32XX_HSUART_IIR(port->membase));
 425 }
 426
 427 /* port->lock held by caller.  */
 428 static void serial_lpc32xx_enable_ms(struct uart_port *port)
 429 {
 430         /* Modem status is not supported */
 431 }
 432
 433 /* port->lock is not held.  */
 434 static void serial_lpc32xx_break_ctl(struct uart_port *port,
 435                                      int break_state)
 436 {
 437         unsigned long flags;
 438         u32 tmp;
 439
 440         spin_lock_irqsave(&port->lock, flags);
 441         tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
 442         if (break_state != 0)
 443                 tmp |= LPC32XX_HSU_BREAK;
 444         else
 445                 tmp &= ~LPC32XX_HSU_BREAK;
 446         writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
 447         spin_unlock_irqrestore(&port->lock, flags);
 448 }
 449
 450 /* LPC3250 Errata HSUART.1: Hang workaround via loopback mode on inactivity */
 451 static void lpc32xx_loopback_set(resource_size_t mapbase, int state)
 452 {
 453         int bit;
 454         u32 tmp;
 455
 456         switch (mapbase) {
 457         case LPC32XX_HS_UART1_BASE:
 458                 bit = 0;
 459                 break;
 460         case LPC32XX_HS_UART2_BASE:
 461                 bit = 1;
 462                 break;
 463         case LPC32XX_HS_UART7_BASE:
 464                 bit = 6;
 465                 break;
 466         default:
 467                 WARN(1, "lpc32xx_hs: Warning: Unknown port at %08x\n", mapbase);
 468                 return;
 469         }
 470
 471         tmp = readl(LPC32XX_UARTCTL_CLOOP);
 472         if (state)
 473                 tmp |= (1 << bit);
 474         else
 475                 tmp &= ~(1 << bit);
 476         writel(tmp, LPC32XX_UARTCTL_CLOOP);
 477 }
 478
 479 /* port->lock is not held.  */
 480 static int serial_lpc32xx_startup(struct uart_port *port)
 481 {
 482         int retval;
 483         unsigned long flags;
 484         u32 tmp;
 485
 486         spin_lock_irqsave(&port->lock, flags);
 487
 488         __serial_uart_flush(port);
 489
 490         writel((LPC32XX_HSU_TX_INT | LPC32XX_HSU_FE_INT |
 491                 LPC32XX_HSU_BRK_INT | LPC32XX_HSU_RX_OE_INT),
 492                LPC32XX_HSUART_IIR(port->membase));
 493
 494         writel(0xFF, LPC32XX_HSUART_RATE(port->membase));
 495
 496         /*
 497          * Set receiver timeout, HSU offset of 20, no break, no interrupts,
 498          * and default FIFO trigger levels
 499          */
 500         tmp = LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B |
 501                 LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B;
 502         writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
 503
 504         lpc32xx_loopback_set(port->mapbase, 0); /* get out of loopback mode */
 505
 506         spin_unlock_irqrestore(&port->lock, flags);
 507
 508         retval = request_irq(port->irq, serial_lpc32xx_interrupt,
 509                              0, MODNAME, port);
 510         if (!retval)
 511                 writel((tmp | LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN),
 512                        LPC32XX_HSUART_CTRL(port->membase));
 513
 514         return retval;
 515 }
 516
 517 /* port->lock is not held.  */
 518 static void serial_lpc32xx_shutdown(struct uart_port *port)
 519 {
 520         u32 tmp;
 521         unsigned long flags;
 522
 523         spin_lock_irqsave(&port->lock, flags);
 524
 525         tmp = LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B |
 526                 LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B;
 527         writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
 528
 529         lpc32xx_loopback_set(port->mapbase, 1); /* go to loopback mode */
 530
 531         spin_unlock_irqrestore(&port->lock, flags);
 532
 533         free_irq(port->irq, port);
 534 }
 535
 536 /* port->lock is not held.  */
 537 static void serial_lpc32xx_set_termios(struct uart_port *port,
 538                                        struct ktermios *termios,
 539                                        struct ktermios *old)
 540 {
 541         unsigned long flags;
 542         unsigned int baud, quot;
 543         u32 tmp;
 544
 545         /* Always 8-bit, no parity, 1 stop bit */
 546         termios->c_cflag &= ~(CSIZE | CSTOPB | PARENB | PARODD);
 547         termios->c_cflag |= CS8;
 548
 549         termios->c_cflag &= ~(HUPCL | CMSPAR | CLOCAL | CRTSCTS);
 550
 551         baud = uart_get_baud_rate(port, termios, old, 0,
 552                                   port->uartclk / 14);
 553
 554         quot = __serial_get_clock_div(port->uartclk, baud);
 555
 556         spin_lock_irqsave(&port->lock, flags);
 557
 558         /* Ignore characters? */
 559         tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
 560         if ((termios->c_cflag & CREAD) == 0)
 561                 tmp &= ~(LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN);
 562         else
 563                 tmp |= LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN;
 564         writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
 565
 566         writel(quot, LPC32XX_HSUART_RATE(port->membase));
 567
 568         uart_update_timeout(port, termios->c_cflag, baud);
 569
 570         spin_unlock_irqrestore(&port->lock, flags);
 571
 572         /* Don't rewrite B0 */
 573         if (tty_termios_baud_rate(termios))
 574                 tty_termios_encode_baud_rate(termios, baud, baud);
 575 }
 576
 577 static const char *serial_lpc32xx_type(struct uart_port *port)
 578 {
 579         return MODNAME;
 580 }
 581
 582 static void serial_lpc32xx_release_port(struct uart_port *port)
 583 {
 584         if ((port->iotype == UPIO_MEM32) && (port->mapbase)) {
 585                 if (port->flags & UPF_IOREMAP) {
 586                         iounmap(port->membase);
 587                         port->membase = NULL;
 588                 }
 589
 590                 release_mem_region(port->mapbase, SZ_4K);
 591         }
 592 }
 593
 594 static int serial_lpc32xx_request_port(struct uart_port *port)
 595 {
 596         int ret = -ENODEV;
 597
 598         if ((port->iotype == UPIO_MEM32) && (port->mapbase)) {
 599                 ret = 0;
 600
 601                 if (!request_mem_region(port->mapbase, SZ_4K, MODNAME))
 602                         ret = -EBUSY;
 603                 else if (port->flags & UPF_IOREMAP) {
 604                         port->membase = ioremap(port->mapbase, SZ_4K);
 605                         if (!port->membase) {
 606                                 release_mem_region(port->mapbase, SZ_4K);
 607                                 ret = -ENOMEM;
 608                         }
 609                 }
 610         }
 611
 612         return ret;
 613 }
 614
 615 static void serial_lpc32xx_config_port(struct uart_port *port, int uflags)
 616 {
 617         int ret;
 618
 619         ret = serial_lpc32xx_request_port(port);
 620         if (ret < 0)
 621                 return;
 622         port->type = PORT_UART00;
 623         port->fifosize = 64;
 624
 625         __serial_uart_flush(port);
 626
 627         writel((LPC32XX_HSU_TX_INT | LPC32XX_HSU_FE_INT |
 628                 LPC32XX_HSU_BRK_INT | LPC32XX_HSU_RX_OE_INT),
 629                LPC32XX_HSUART_IIR(port->membase));
 630
 631         writel(0xFF, LPC32XX_HSUART_RATE(port->membase));
 632
 633         /* Set receiver timeout, HSU offset of 20, no break, no interrupts,
 634            and default FIFO trigger levels */
 635         writel(LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B |
 636                LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B,
 637                LPC32XX_HSUART_CTRL(port->membase));
 638 }
 639
 640 static int serial_lpc32xx_verify_port(struct uart_port *port,
 641                                       struct serial_struct *ser)
 642 {
 643         int ret = 0;
 644
 645         if (ser->type != PORT_UART00)
 646                 ret = -EINVAL;
 647
 648         return ret;
 649 }
 650
 651 static struct uart_ops serial_lpc32xx_pops = {
 652         .tx_empty       = serial_lpc32xx_tx_empty,
 653         .set_mctrl      = serial_lpc32xx_set_mctrl,
 654         .get_mctrl      = serial_lpc32xx_get_mctrl,
 655         .stop_tx        = serial_lpc32xx_stop_tx,
 656         .start_tx       = serial_lpc32xx_start_tx,
 657         .stop_rx        = serial_lpc32xx_stop_rx,
 658         .enable_ms      = serial_lpc32xx_enable_ms,
 659         .break_ctl      = serial_lpc32xx_break_ctl,
 660         .startup        = serial_lpc32xx_startup,
 661         .shutdown       = serial_lpc32xx_shutdown,
 662         .set_termios    = serial_lpc32xx_set_termios,
 663         .type           = serial_lpc32xx_type,
 664         .release_port   = serial_lpc32xx_release_port,
 665         .request_port   = serial_lpc32xx_request_port,
 666         .config_port    = serial_lpc32xx_config_port,
 667         .verify_port    = serial_lpc32xx_verify_port,
 668 };
 669
 670 /*
 671  * Register a set of serial devices attached to a platform device
 672  */
 673 static int serial_hs_lpc32xx_probe(struct platform_device *pdev)
 674 {
 675         struct lpc32xx_hsuart_port *p = &lpc32xx_hs_ports[uarts_registered];
 676         int ret = 0;
 677         struct resource *res;
 678
 679         if (uarts_registered >= MAX_PORTS) {
 680                 dev_err(&pdev->dev,
 681                         "Error: Number of possible ports exceeded (%d)!\n",
 682                         uarts_registered + 1);
 683                 return -ENXIO;
 684         }
 685
 686         memset(p, 0, sizeof(*p));
 687
 688         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 689         if (!res) {
 690                 dev_err(&pdev->dev,
 691                         "Error getting mem resource for HS UART port %d\n",
 692                         uarts_registered);
 693                 return -ENXIO;
 694         }
 695         p->port.mapbase = res->start;
 696         p->port.membase = NULL;
 697
 698         p->port.irq = platform_get_irq(pdev, 0);
 699         if (p->port.irq < 0) {
 700                 dev_err(&pdev->dev, "Error getting irq for HS UART port %d\n",
 701                         uarts_registered);
 702                 return p->port.irq;
 703         }
 704
 705         p->port.iotype = UPIO_MEM32;
 706         p->port.uartclk = LPC32XX_MAIN_OSC_FREQ;
 707         p->port.regshift = 2;
 708         p->port.flags = UPF_BOOT_AUTOCONF | UPF_FIXED_PORT | UPF_IOREMAP;
 709         p->port.dev = &pdev->dev;
 710         p->port.ops = &serial_lpc32xx_pops;
 711         p->port.line = uarts_registered++;
 712         spin_lock_init(&p->port.lock);
 713
 714         /* send port to loopback mode by default */
 715         lpc32xx_loopback_set(p->port.mapbase, 1);
 716
 717         ret = uart_add_one_port(&lpc32xx_hs_reg, &p->port);
 718
 719         platform_set_drvdata(pdev, p);
 720
 721         return ret;
 722 }
 723
 724 /*
 725  * Remove serial ports registered against a platform device.
 726  */
 727 static int serial_hs_lpc32xx_remove(struct platform_device *pdev)
 728 {
 729         struct lpc32xx_hsuart_port *p = platform_get_drvdata(pdev);
 730
 731         uart_remove_one_port(&lpc32xx_hs_reg, &p->port);
 732
 733         return 0;
 734 }
 735
 736
 737 #ifdef CONFIG_PM
 738 static int serial_hs_lpc32xx_suspend(struct platform_device *pdev,
 739                                      pm_message_t state)
 740 {
 741         struct lpc32xx_hsuart_port *p = platform_get_drvdata(pdev);
 742
 743         uart_suspend_port(&lpc32xx_hs_reg, &p->port);
 744
 745         return 0;
 746 }
 747
 748 static int serial_hs_lpc32xx_resume(struct platform_device *pdev)
 749 {
 750         struct lpc32xx_hsuart_port *p = platform_get_drvdata(pdev);
 751
 752         uart_resume_port(&lpc32xx_hs_reg, &p->port);
 753
 754         return 0;
 755 }
 756 #else
 757 #define serial_hs_lpc32xx_suspend       NULL
 758 #define serial_hs_lpc32xx_resume        NULL
 759 #endif
 760
 761 static const struct of_device_id serial_hs_lpc32xx_dt_ids[] = {
 762         { .compatible = "nxp,lpc3220-hsuart" },
 763         { /* sentinel */ }
 764 };
 765
 766 MODULE_DEVICE_TABLE(of, serial_hs_lpc32xx_dt_ids);
 767
 768 static struct platform_driver serial_hs_lpc32xx_driver = {
 769         .probe          = serial_hs_lpc32xx_probe,
 770         .remove         = serial_hs_lpc32xx_remove,
 771         .suspend        = serial_hs_lpc32xx_suspend,
 772         .resume         = serial_hs_lpc32xx_resume,
 773         .driver         = {
 774                 .name   = MODNAME,
 775                 .owner  = THIS_MODULE,
 776                 .of_match_table = serial_hs_lpc32xx_dt_ids,
 777         },
 778 };
 779
 780 static int __init lpc32xx_hsuart_init(void)
 781 {
 782         int ret;
 783
 784         ret = uart_register_driver(&lpc32xx_hs_reg);
 785         if (ret)
 786                 return ret;
 787
 788         ret = platform_driver_register(&serial_hs_lpc32xx_driver);
 789         if (ret)
 790                 uart_unregister_driver(&lpc32xx_hs_reg);
 791
 792         return ret;
 793 }
 794
 795 static void __exit lpc32xx_hsuart_exit(void)
 796 {
 797         platform_driver_unregister(&serial_hs_lpc32xx_driver);
 798         uart_unregister_driver(&lpc32xx_hs_reg);
 799 }
 800
 801 module_init(lpc32xx_hsuart_init);
 802 module_exit(lpc32xx_hsuart_exit);
 803
 804 MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>");
 805 MODULE_AUTHOR("Roland Stigge <stigge@antcom.de>");
 806 MODULE_DESCRIPTION("NXP LPC32XX High Speed UART driver");
 807 MODULE_LICENSE("GPL");