2 * Driver for CPM (SCC/SMC) serial ports; core driver
4 * Based on arch/ppc/cpm2_io/uart.c by Dan Malek
5 * Based on ppc8xx.c by Thomas Gleixner
6 * Based on drivers/serial/amba.c by Russell King
8 * Maintainer: Kumar Gala (galak@kernel.crashing.org) (CPM2)
9 * Pantelis Antoniou (panto@intracom.gr) (CPM1)
11 * Copyright (C) 2004, 2007 Freescale Semiconductor, Inc.
12 * (C) 2004 Intracom, S.A.
13 * (C) 2005-2006 MontaVista Software, Inc.
14 * Vitaly Bordug <vbordug@ru.mvista.com>
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or
19 * (at your option) any later version.
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
32 #include <linux/module.h>
33 #include <linux/tty.h>
34 #include <linux/tty_flip.h>
35 #include <linux/ioport.h>
36 #include <linux/init.h>
37 #include <linux/serial.h>
38 #include <linux/console.h>
39 #include <linux/sysrq.h>
40 #include <linux/device.h>
41 #include <linux/bootmem.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/fs_uart_pd.h>
44 #include <linux/of_address.h>
45 #include <linux/of_irq.h>
46 #include <linux/of_platform.h>
47 #include <linux/gpio.h>
48 #include <linux/of_gpio.h>
49 #include <linux/clk.h>
53 #include <asm/delay.h>
54 #include <asm/fs_pd.h>
57 #if defined(CONFIG_SERIAL_CPM_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
61 #include <linux/serial_core.h>
62 #include <linux/kernel.h>
67 /**************************************************************/
69 static int cpm_uart_tx_pump(struct uart_port *port);
70 static void cpm_uart_init_smc(struct uart_cpm_port *pinfo);
71 static void cpm_uart_init_scc(struct uart_cpm_port *pinfo);
72 static void cpm_uart_initbd(struct uart_cpm_port *pinfo);
74 /**************************************************************/
76 #define HW_BUF_SPD_THRESHOLD 2400
79 * Check, if transmit buffers are processed
81 static unsigned int cpm_uart_tx_empty(struct uart_port *port)
83 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
84 cbd_t __iomem *bdp = pinfo->tx_bd_base;
88 if (in_be16(&bdp->cbd_sc) & BD_SC_READY)
91 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP) {
98 pr_debug("CPM uart[%d]:tx_empty: %d\n", port->line, ret);
103 static void cpm_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
105 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
107 if (pinfo->gpios[GPIO_RTS] >= 0)
108 gpio_set_value(pinfo->gpios[GPIO_RTS], !(mctrl & TIOCM_RTS));
110 if (pinfo->gpios[GPIO_DTR] >= 0)
111 gpio_set_value(pinfo->gpios[GPIO_DTR], !(mctrl & TIOCM_DTR));
114 static unsigned int cpm_uart_get_mctrl(struct uart_port *port)
116 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
117 unsigned int mctrl = TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
119 if (pinfo->gpios[GPIO_CTS] >= 0) {
120 if (gpio_get_value(pinfo->gpios[GPIO_CTS]))
124 if (pinfo->gpios[GPIO_DSR] >= 0) {
125 if (gpio_get_value(pinfo->gpios[GPIO_DSR]))
129 if (pinfo->gpios[GPIO_DCD] >= 0) {
130 if (gpio_get_value(pinfo->gpios[GPIO_DCD]))
134 if (pinfo->gpios[GPIO_RI] >= 0) {
135 if (!gpio_get_value(pinfo->gpios[GPIO_RI]))
145 static void cpm_uart_stop_tx(struct uart_port *port)
147 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
148 smc_t __iomem *smcp = pinfo->smcp;
149 scc_t __iomem *sccp = pinfo->sccp;
151 pr_debug("CPM uart[%d]:stop tx\n", port->line);
154 clrbits8(&smcp->smc_smcm, SMCM_TX);
156 clrbits16(&sccp->scc_sccm, UART_SCCM_TX);
162 static void cpm_uart_start_tx(struct uart_port *port)
164 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
165 smc_t __iomem *smcp = pinfo->smcp;
166 scc_t __iomem *sccp = pinfo->sccp;
168 pr_debug("CPM uart[%d]:start tx\n", port->line);
171 if (in_8(&smcp->smc_smcm) & SMCM_TX)
174 if (in_be16(&sccp->scc_sccm) & UART_SCCM_TX)
178 if (cpm_uart_tx_pump(port) != 0) {
180 setbits8(&smcp->smc_smcm, SMCM_TX);
182 setbits16(&sccp->scc_sccm, UART_SCCM_TX);
190 static void cpm_uart_stop_rx(struct uart_port *port)
192 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
193 smc_t __iomem *smcp = pinfo->smcp;
194 scc_t __iomem *sccp = pinfo->sccp;
196 pr_debug("CPM uart[%d]:stop rx\n", port->line);
199 clrbits8(&smcp->smc_smcm, SMCM_RX);
201 clrbits16(&sccp->scc_sccm, UART_SCCM_RX);
205 * Enable Modem status interrupts
207 static void cpm_uart_enable_ms(struct uart_port *port)
209 pr_debug("CPM uart[%d]:enable ms\n", port->line);
215 static void cpm_uart_break_ctl(struct uart_port *port, int break_state)
217 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
219 pr_debug("CPM uart[%d]:break ctrl, break_state: %d\n", port->line,
223 cpm_line_cr_cmd(pinfo, CPM_CR_STOP_TX);
225 cpm_line_cr_cmd(pinfo, CPM_CR_RESTART_TX);
229 * Transmit characters, refill buffer descriptor, if possible
231 static void cpm_uart_int_tx(struct uart_port *port)
233 pr_debug("CPM uart[%d]:TX INT\n", port->line);
235 cpm_uart_tx_pump(port);
238 #ifdef CONFIG_CONSOLE_POLL
239 static int serial_polled;
245 static void cpm_uart_int_rx(struct uart_port *port)
250 struct tty_port *tport = &port->state->port;
251 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
256 pr_debug("CPM uart[%d]:RX INT\n", port->line);
258 /* Just loop through the closed BDs and copy the characters into
263 #ifdef CONFIG_CONSOLE_POLL
264 if (unlikely(serial_polled)) {
270 status = in_be16(&bdp->cbd_sc);
271 /* If this one is empty, return happy */
272 if (status & BD_SC_EMPTY)
275 /* get number of characters, and check spce in flip-buffer */
276 i = in_be16(&bdp->cbd_datlen);
278 /* If we have not enough room in tty flip buffer, then we try
279 * later, which will be the next rx-interrupt or a timeout
281 if (tty_buffer_request_room(tport, i) < i) {
282 printk(KERN_WARNING "No room in flip buffer\n");
287 cp = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), pinfo);
289 /* loop through the buffer */
296 (BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_OV))
298 if (uart_handle_sysrq_char(port, ch))
300 #ifdef CONFIG_CONSOLE_POLL
301 if (unlikely(serial_polled)) {
307 tty_insert_flip_char(tport, ch, flg);
309 } /* End while (i--) */
311 /* This BD is ready to be used again. Clear status. get next */
312 clrbits16(&bdp->cbd_sc, BD_SC_BR | BD_SC_FR | BD_SC_PR |
313 BD_SC_OV | BD_SC_ID);
314 setbits16(&bdp->cbd_sc, BD_SC_EMPTY);
316 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP)
317 bdp = pinfo->rx_bd_base;
323 /* Write back buffer pointer */
326 /* activate BH processing */
327 tty_flip_buffer_push(tport);
331 /* Error processing */
335 if (status & BD_SC_BR)
337 if (status & BD_SC_PR)
338 port->icount.parity++;
339 if (status & BD_SC_FR)
340 port->icount.frame++;
341 if (status & BD_SC_OV)
342 port->icount.overrun++;
344 /* Mask out ignored conditions */
345 status &= port->read_status_mask;
347 /* Handle the remaining ones */
348 if (status & BD_SC_BR)
350 else if (status & BD_SC_PR)
352 else if (status & BD_SC_FR)
355 /* overrun does not affect the current character ! */
356 if (status & BD_SC_OV) {
359 /* We skip this buffer */
360 /* CHECK: Is really nothing senseful there */
361 /* ASSUMPTION: it contains nothing valid */
371 * Asynchron mode interrupt handler
373 static irqreturn_t cpm_uart_int(int irq, void *data)
376 struct uart_port *port = data;
377 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
378 smc_t __iomem *smcp = pinfo->smcp;
379 scc_t __iomem *sccp = pinfo->sccp;
381 pr_debug("CPM uart[%d]:IRQ\n", port->line);
384 events = in_8(&smcp->smc_smce);
385 out_8(&smcp->smc_smce, events);
386 if (events & SMCM_BRKE)
387 uart_handle_break(port);
388 if (events & SMCM_RX)
389 cpm_uart_int_rx(port);
390 if (events & SMCM_TX)
391 cpm_uart_int_tx(port);
393 events = in_be16(&sccp->scc_scce);
394 out_be16(&sccp->scc_scce, events);
395 if (events & UART_SCCM_BRKE)
396 uart_handle_break(port);
397 if (events & UART_SCCM_RX)
398 cpm_uart_int_rx(port);
399 if (events & UART_SCCM_TX)
400 cpm_uart_int_tx(port);
402 return (events) ? IRQ_HANDLED : IRQ_NONE;
405 static int cpm_uart_startup(struct uart_port *port)
408 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
410 pr_debug("CPM uart[%d]:startup\n", port->line);
412 /* If the port is not the console, make sure rx is disabled. */
413 if (!(pinfo->flags & FLAG_CONSOLE)) {
414 /* Disable UART rx */
416 clrbits16(&pinfo->smcp->smc_smcmr, SMCMR_REN);
417 clrbits8(&pinfo->smcp->smc_smcm, SMCM_RX);
419 clrbits32(&pinfo->sccp->scc_gsmrl, SCC_GSMRL_ENR);
420 clrbits16(&pinfo->sccp->scc_sccm, UART_SCCM_RX);
422 cpm_uart_initbd(pinfo);
423 cpm_line_cr_cmd(pinfo, CPM_CR_INIT_TRX);
425 /* Install interrupt handler. */
426 retval = request_irq(port->irq, cpm_uart_int, 0, "cpm_uart", port);
432 setbits8(&pinfo->smcp->smc_smcm, SMCM_RX);
433 setbits16(&pinfo->smcp->smc_smcmr, (SMCMR_REN | SMCMR_TEN));
435 setbits16(&pinfo->sccp->scc_sccm, UART_SCCM_RX);
436 setbits32(&pinfo->sccp->scc_gsmrl, (SCC_GSMRL_ENR | SCC_GSMRL_ENT));
442 inline void cpm_uart_wait_until_send(struct uart_cpm_port *pinfo)
444 set_current_state(TASK_UNINTERRUPTIBLE);
445 schedule_timeout(pinfo->wait_closing);
451 static void cpm_uart_shutdown(struct uart_port *port)
453 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
455 pr_debug("CPM uart[%d]:shutdown\n", port->line);
457 /* free interrupt handler */
458 free_irq(port->irq, port);
460 /* If the port is not the console, disable Rx and Tx. */
461 if (!(pinfo->flags & FLAG_CONSOLE)) {
462 /* Wait for all the BDs marked sent */
463 while(!cpm_uart_tx_empty(port)) {
464 set_current_state(TASK_UNINTERRUPTIBLE);
468 if (pinfo->wait_closing)
469 cpm_uart_wait_until_send(pinfo);
473 smc_t __iomem *smcp = pinfo->smcp;
474 clrbits16(&smcp->smc_smcmr, SMCMR_REN | SMCMR_TEN);
475 clrbits8(&smcp->smc_smcm, SMCM_RX | SMCM_TX);
477 scc_t __iomem *sccp = pinfo->sccp;
478 clrbits32(&sccp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT);
479 clrbits16(&sccp->scc_sccm, UART_SCCM_TX | UART_SCCM_RX);
482 /* Shut them really down and reinit buffer descriptors */
484 out_be16(&pinfo->smcup->smc_brkcr, 0);
485 cpm_line_cr_cmd(pinfo, CPM_CR_STOP_TX);
487 out_be16(&pinfo->sccup->scc_brkcr, 0);
488 cpm_line_cr_cmd(pinfo, CPM_CR_GRA_STOP_TX);
491 cpm_uart_initbd(pinfo);
495 static void cpm_uart_set_termios(struct uart_port *port,
496 struct ktermios *termios,
497 struct ktermios *old)
501 u16 cval, scval, prev_mode;
503 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
504 smc_t __iomem *smcp = pinfo->smcp;
505 scc_t __iomem *sccp = pinfo->sccp;
508 pr_debug("CPM uart[%d]:set_termios\n", port->line);
510 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
511 if (baud < HW_BUF_SPD_THRESHOLD ||
512 (pinfo->port.state && pinfo->port.state->port.low_latency))
513 pinfo->rx_fifosize = 1;
515 pinfo->rx_fifosize = RX_BUF_SIZE;
517 /* MAXIDL is the timeout after which a receive buffer is closed
518 * when not full if no more characters are received.
519 * We calculate it from the baudrate so that the duration is
520 * always the same at standard rates: about 4ms.
522 maxidl = baud / 2400;
528 /* Character length programmed into the mode register is the
529 * sum of: 1 start bit, number of data bits, 0 or 1 parity bit,
530 * 1 or 2 stop bits, minus 1.
531 * The value 'bits' counts this for us.
537 switch (termios->c_cflag & CSIZE) {
550 /* Never happens, but GCC is too dumb to figure it out */
557 if (termios->c_cflag & CSTOPB) {
558 cval |= SMCMR_SL; /* Two stops */
559 scval |= SCU_PSMR_SL;
563 if (termios->c_cflag & PARENB) {
565 scval |= SCU_PSMR_PEN;
567 if (!(termios->c_cflag & PARODD)) {
568 cval |= SMCMR_PM_EVEN;
569 scval |= (SCU_PSMR_REVP | SCU_PSMR_TEVP);
576 uart_update_timeout(port, termios->c_cflag, baud);
579 * Set up parity check flag
581 #define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK))
583 port->read_status_mask = (BD_SC_EMPTY | BD_SC_OV);
584 if (termios->c_iflag & INPCK)
585 port->read_status_mask |= BD_SC_FR | BD_SC_PR;
586 if ((termios->c_iflag & BRKINT) || (termios->c_iflag & PARMRK))
587 port->read_status_mask |= BD_SC_BR;
590 * Characters to ignore
592 port->ignore_status_mask = 0;
593 if (termios->c_iflag & IGNPAR)
594 port->ignore_status_mask |= BD_SC_PR | BD_SC_FR;
595 if (termios->c_iflag & IGNBRK) {
596 port->ignore_status_mask |= BD_SC_BR;
598 * If we're ignore parity and break indicators, ignore
599 * overruns too. (For real raw support).
601 if (termios->c_iflag & IGNPAR)
602 port->ignore_status_mask |= BD_SC_OV;
605 * !!! ignore all characters if CREAD is not set
607 if ((termios->c_cflag & CREAD) == 0)
608 port->read_status_mask &= ~BD_SC_EMPTY;
610 spin_lock_irqsave(&port->lock, flags);
612 /* Start bit has not been added (so don't, because we would just
613 * subtract it later), and we need to add one for the number of
614 * stops bits (there is always at least one).
619 * MRBLR can be changed while an SMC/SCC is operating only
620 * if it is done in a single bus cycle with one 16-bit move
621 * (not two 8-bit bus cycles back-to-back). This occurs when
622 * the cp shifts control to the next RxBD, so the change does
623 * not take effect immediately. To guarantee the exact RxBD
624 * on which the change occurs, change MRBLR only while the
625 * SMC/SCC receiver is disabled.
627 out_be16(&pinfo->smcup->smc_mrblr, pinfo->rx_fifosize);
628 out_be16(&pinfo->smcup->smc_maxidl, maxidl);
630 /* Set the mode register. We want to keep a copy of the
631 * enables, because we want to put them back if they were
634 prev_mode = in_be16(&smcp->smc_smcmr) & (SMCMR_REN | SMCMR_TEN);
635 /* Output in *one* operation, so we don't interrupt RX/TX if they
636 * were already enabled. */
637 out_be16(&smcp->smc_smcmr, smcr_mk_clen(bits) | cval |
638 SMCMR_SM_UART | prev_mode);
640 out_be16(&pinfo->sccup->scc_genscc.scc_mrblr, pinfo->rx_fifosize);
641 out_be16(&pinfo->sccup->scc_maxidl, maxidl);
642 out_be16(&sccp->scc_psmr, (sbits << 12) | scval);
646 clk_set_rate(pinfo->clk, baud);
648 cpm_set_brg(pinfo->brg - 1, baud);
649 spin_unlock_irqrestore(&port->lock, flags);
652 static const char *cpm_uart_type(struct uart_port *port)
654 pr_debug("CPM uart[%d]:uart_type\n", port->line);
656 return port->type == PORT_CPM ? "CPM UART" : NULL;
660 * verify the new serial_struct (for TIOCSSERIAL).
662 static int cpm_uart_verify_port(struct uart_port *port,
663 struct serial_struct *ser)
667 pr_debug("CPM uart[%d]:verify_port\n", port->line);
669 if (ser->type != PORT_UNKNOWN && ser->type != PORT_CPM)
671 if (ser->irq < 0 || ser->irq >= nr_irqs)
673 if (ser->baud_base < 9600)
679 * Transmit characters, refill buffer descriptor, if possible
681 static int cpm_uart_tx_pump(struct uart_port *port)
686 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
687 struct circ_buf *xmit = &port->state->xmit;
689 /* Handle xon/xoff */
691 /* Pick next descriptor and fill from buffer */
694 p = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), pinfo);
698 out_be16(&bdp->cbd_datlen, 1);
699 setbits16(&bdp->cbd_sc, BD_SC_READY);
701 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP)
702 bdp = pinfo->tx_bd_base;
712 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
713 cpm_uart_stop_tx(port);
717 /* Pick next descriptor and fill from buffer */
720 while (!(in_be16(&bdp->cbd_sc) & BD_SC_READY) &&
721 xmit->tail != xmit->head) {
723 p = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), pinfo);
724 while (count < pinfo->tx_fifosize) {
725 *p++ = xmit->buf[xmit->tail];
726 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
729 if (xmit->head == xmit->tail)
732 out_be16(&bdp->cbd_datlen, count);
733 setbits16(&bdp->cbd_sc, BD_SC_READY);
735 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP)
736 bdp = pinfo->tx_bd_base;
742 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
743 uart_write_wakeup(port);
745 if (uart_circ_empty(xmit)) {
746 cpm_uart_stop_tx(port);
754 * init buffer descriptors
756 static void cpm_uart_initbd(struct uart_cpm_port *pinfo)
762 pr_debug("CPM uart[%d]:initbd\n", pinfo->port.line);
764 /* Set the physical address of the host memory
765 * buffers in the buffer descriptors, and the
766 * virtual address for us to work with.
768 mem_addr = pinfo->mem_addr;
769 bdp = pinfo->rx_cur = pinfo->rx_bd_base;
770 for (i = 0; i < (pinfo->rx_nrfifos - 1); i++, bdp++) {
771 out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo));
772 out_be16(&bdp->cbd_sc, BD_SC_EMPTY | BD_SC_INTRPT);
773 mem_addr += pinfo->rx_fifosize;
776 out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo));
777 out_be16(&bdp->cbd_sc, BD_SC_WRAP | BD_SC_EMPTY | BD_SC_INTRPT);
779 /* Set the physical address of the host memory
780 * buffers in the buffer descriptors, and the
781 * virtual address for us to work with.
783 mem_addr = pinfo->mem_addr + L1_CACHE_ALIGN(pinfo->rx_nrfifos * pinfo->rx_fifosize);
784 bdp = pinfo->tx_cur = pinfo->tx_bd_base;
785 for (i = 0; i < (pinfo->tx_nrfifos - 1); i++, bdp++) {
786 out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo));
787 out_be16(&bdp->cbd_sc, BD_SC_INTRPT);
788 mem_addr += pinfo->tx_fifosize;
791 out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo));
792 out_be16(&bdp->cbd_sc, BD_SC_WRAP | BD_SC_INTRPT);
795 static void cpm_uart_init_scc(struct uart_cpm_port *pinfo)
798 scc_uart_t __iomem *sup;
800 pr_debug("CPM uart[%d]:init_scc\n", pinfo->port.line);
806 out_be16(&pinfo->sccup->scc_genscc.scc_rbase,
807 (u8 __iomem *)pinfo->rx_bd_base - DPRAM_BASE);
808 out_be16(&pinfo->sccup->scc_genscc.scc_tbase,
809 (u8 __iomem *)pinfo->tx_bd_base - DPRAM_BASE);
811 /* Set up the uart parameters in the
815 cpm_set_scc_fcr(sup);
817 out_be16(&sup->scc_genscc.scc_mrblr, pinfo->rx_fifosize);
818 out_be16(&sup->scc_maxidl, 0x10);
819 out_be16(&sup->scc_brkcr, 1);
820 out_be16(&sup->scc_parec, 0);
821 out_be16(&sup->scc_frmec, 0);
822 out_be16(&sup->scc_nosec, 0);
823 out_be16(&sup->scc_brkec, 0);
824 out_be16(&sup->scc_uaddr1, 0);
825 out_be16(&sup->scc_uaddr2, 0);
826 out_be16(&sup->scc_toseq, 0);
827 out_be16(&sup->scc_char1, 0x8000);
828 out_be16(&sup->scc_char2, 0x8000);
829 out_be16(&sup->scc_char3, 0x8000);
830 out_be16(&sup->scc_char4, 0x8000);
831 out_be16(&sup->scc_char5, 0x8000);
832 out_be16(&sup->scc_char6, 0x8000);
833 out_be16(&sup->scc_char7, 0x8000);
834 out_be16(&sup->scc_char8, 0x8000);
835 out_be16(&sup->scc_rccm, 0xc0ff);
837 /* Send the CPM an initialize command.
839 cpm_line_cr_cmd(pinfo, CPM_CR_INIT_TRX);
841 /* Set UART mode, 8 bit, no parity, one stop.
842 * Enable receive and transmit.
844 out_be32(&scp->scc_gsmrh, 0);
845 out_be32(&scp->scc_gsmrl,
846 SCC_GSMRL_MODE_UART | SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16);
848 /* Enable rx interrupts and clear all pending events. */
849 out_be16(&scp->scc_sccm, 0);
850 out_be16(&scp->scc_scce, 0xffff);
851 out_be16(&scp->scc_dsr, 0x7e7e);
852 out_be16(&scp->scc_psmr, 0x3000);
854 setbits32(&scp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT);
857 static void cpm_uart_init_smc(struct uart_cpm_port *pinfo)
860 smc_uart_t __iomem *up;
862 pr_debug("CPM uart[%d]:init_smc\n", pinfo->port.line);
868 out_be16(&pinfo->smcup->smc_rbase,
869 (u8 __iomem *)pinfo->rx_bd_base - DPRAM_BASE);
870 out_be16(&pinfo->smcup->smc_tbase,
871 (u8 __iomem *)pinfo->tx_bd_base - DPRAM_BASE);
874 * In case SMC1 is being relocated...
876 #if defined (CONFIG_I2C_SPI_SMC1_UCODE_PATCH)
877 out_be16(&up->smc_rbptr, in_be16(&pinfo->smcup->smc_rbase));
878 out_be16(&up->smc_tbptr, in_be16(&pinfo->smcup->smc_tbase));
879 out_be32(&up->smc_rstate, 0);
880 out_be32(&up->smc_tstate, 0);
881 out_be16(&up->smc_brkcr, 1); /* number of break chars */
882 out_be16(&up->smc_brkec, 0);
885 /* Set up the uart parameters in the
890 /* Using idle character time requires some additional tuning. */
891 out_be16(&up->smc_mrblr, pinfo->rx_fifosize);
892 out_be16(&up->smc_maxidl, 0x10);
893 out_be16(&up->smc_brklen, 0);
894 out_be16(&up->smc_brkec, 0);
895 out_be16(&up->smc_brkcr, 1);
897 cpm_line_cr_cmd(pinfo, CPM_CR_INIT_TRX);
899 /* Set UART mode, 8 bit, no parity, one stop.
900 * Enable receive and transmit.
902 out_be16(&sp->smc_smcmr, smcr_mk_clen(9) | SMCMR_SM_UART);
904 /* Enable only rx interrupts clear all pending events. */
905 out_8(&sp->smc_smcm, 0);
906 out_8(&sp->smc_smce, 0xff);
908 setbits16(&sp->smc_smcmr, SMCMR_REN | SMCMR_TEN);
912 * Initialize port. This is called from early_console stuff
913 * so we have to be careful here !
915 static int cpm_uart_request_port(struct uart_port *port)
917 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
920 pr_debug("CPM uart[%d]:request port\n", port->line);
922 if (pinfo->flags & FLAG_CONSOLE)
926 clrbits8(&pinfo->smcp->smc_smcm, SMCM_RX | SMCM_TX);
927 clrbits16(&pinfo->smcp->smc_smcmr, SMCMR_REN | SMCMR_TEN);
929 clrbits16(&pinfo->sccp->scc_sccm, UART_SCCM_TX | UART_SCCM_RX);
930 clrbits32(&pinfo->sccp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT);
933 ret = cpm_uart_allocbuf(pinfo, 0);
938 cpm_uart_initbd(pinfo);
940 cpm_uart_init_smc(pinfo);
942 cpm_uart_init_scc(pinfo);
947 static void cpm_uart_release_port(struct uart_port *port)
949 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
951 if (!(pinfo->flags & FLAG_CONSOLE))
952 cpm_uart_freebuf(pinfo);
956 * Configure/autoconfigure the port.
958 static void cpm_uart_config_port(struct uart_port *port, int flags)
960 pr_debug("CPM uart[%d]:config_port\n", port->line);
962 if (flags & UART_CONFIG_TYPE) {
963 port->type = PORT_CPM;
964 cpm_uart_request_port(port);
968 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_CPM_CONSOLE)
970 * Write a string to the serial port
971 * Note that this is called with interrupts already disabled
973 static void cpm_uart_early_write(struct uart_cpm_port *pinfo,
974 const char *string, u_int count)
977 cbd_t __iomem *bdp, *bdbase;
978 unsigned char *cpm_outp_addr;
980 /* Get the address of the host memory buffer.
983 bdbase = pinfo->tx_bd_base;
986 * Now, do each character. This is not as bad as it looks
987 * since this is a holding FIFO and not a transmitting FIFO.
988 * We could add the complexity of filling the entire transmit
989 * buffer, but we would just wait longer between accesses......
991 for (i = 0; i < count; i++, string++) {
992 /* Wait for transmitter fifo to empty.
993 * Ready indicates output is ready, and xmt is doing
994 * that, not that it is ready for us to send.
996 while ((in_be16(&bdp->cbd_sc) & BD_SC_READY) != 0)
999 /* Send the character out.
1000 * If the buffer address is in the CPM DPRAM, don't
1003 cpm_outp_addr = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr),
1005 *cpm_outp_addr = *string;
1007 out_be16(&bdp->cbd_datlen, 1);
1008 setbits16(&bdp->cbd_sc, BD_SC_READY);
1010 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP)
1015 /* if a LF, also do CR... */
1016 if (*string == 10) {
1017 while ((in_be16(&bdp->cbd_sc) & BD_SC_READY) != 0)
1020 cpm_outp_addr = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr),
1022 *cpm_outp_addr = 13;
1024 out_be16(&bdp->cbd_datlen, 1);
1025 setbits16(&bdp->cbd_sc, BD_SC_READY);
1027 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP)
1035 * Finally, Wait for transmitter & holding register to empty
1036 * and restore the IER
1038 while ((in_be16(&bdp->cbd_sc) & BD_SC_READY) != 0)
1041 pinfo->tx_cur = bdp;
1045 #ifdef CONFIG_CONSOLE_POLL
1046 /* Serial polling routines for writing and reading from the uart while
1047 * in an interrupt or debug context.
1050 #define GDB_BUF_SIZE 512 /* power of 2, please */
1052 static char poll_buf[GDB_BUF_SIZE];
1054 static int poll_chars;
1056 static int poll_wait_key(char *obuf, struct uart_cpm_port *pinfo)
1059 volatile cbd_t *bdp;
1062 /* Get the address of the host memory buffer.
1064 bdp = pinfo->rx_cur;
1065 while (bdp->cbd_sc & BD_SC_EMPTY)
1068 /* If the buffer address is in the CPM DPRAM, don't
1071 cp = cpm2cpu_addr(bdp->cbd_bufaddr, pinfo);
1074 i = c = bdp->cbd_datlen;
1079 bdp->cbd_sc &= ~(BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_OV | BD_SC_ID);
1080 bdp->cbd_sc |= BD_SC_EMPTY;
1082 if (bdp->cbd_sc & BD_SC_WRAP)
1083 bdp = pinfo->rx_bd_base;
1086 pinfo->rx_cur = (cbd_t *)bdp;
1091 static int cpm_get_poll_char(struct uart_port *port)
1093 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
1095 if (!serial_polled) {
1099 if (poll_chars <= 0) {
1100 poll_chars = poll_wait_key(poll_buf, pinfo);
1107 static void cpm_put_poll_char(struct uart_port *port,
1110 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
1114 cpm_uart_early_write(pinfo, ch, 1);
1116 #endif /* CONFIG_CONSOLE_POLL */
1118 static struct uart_ops cpm_uart_pops = {
1119 .tx_empty = cpm_uart_tx_empty,
1120 .set_mctrl = cpm_uart_set_mctrl,
1121 .get_mctrl = cpm_uart_get_mctrl,
1122 .stop_tx = cpm_uart_stop_tx,
1123 .start_tx = cpm_uart_start_tx,
1124 .stop_rx = cpm_uart_stop_rx,
1125 .enable_ms = cpm_uart_enable_ms,
1126 .break_ctl = cpm_uart_break_ctl,
1127 .startup = cpm_uart_startup,
1128 .shutdown = cpm_uart_shutdown,
1129 .set_termios = cpm_uart_set_termios,
1130 .type = cpm_uart_type,
1131 .release_port = cpm_uart_release_port,
1132 .request_port = cpm_uart_request_port,
1133 .config_port = cpm_uart_config_port,
1134 .verify_port = cpm_uart_verify_port,
1135 #ifdef CONFIG_CONSOLE_POLL
1136 .poll_get_char = cpm_get_poll_char,
1137 .poll_put_char = cpm_put_poll_char,
1141 struct uart_cpm_port cpm_uart_ports[UART_NR];
1143 static int cpm_uart_init_port(struct device_node *np,
1144 struct uart_cpm_port *pinfo)
1147 void __iomem *mem, *pram;
1152 data = of_get_property(np, "clock", NULL);
1154 struct clk *clk = clk_get(NULL, (const char*)data);
1159 data = of_get_property(np, "fsl,cpm-brg", &len);
1160 if (!data || len != 4) {
1161 printk(KERN_ERR "CPM UART %s has no/invalid "
1162 "fsl,cpm-brg property.\n", np->name);
1168 data = of_get_property(np, "fsl,cpm-command", &len);
1169 if (!data || len != 4) {
1170 printk(KERN_ERR "CPM UART %s has no/invalid "
1171 "fsl,cpm-command property.\n", np->name);
1174 pinfo->command = *data;
1176 mem = of_iomap(np, 0);
1180 if (of_device_is_compatible(np, "fsl,cpm1-scc-uart") ||
1181 of_device_is_compatible(np, "fsl,cpm2-scc-uart")) {
1183 pinfo->sccup = pram = cpm_uart_map_pram(pinfo, np);
1184 } else if (of_device_is_compatible(np, "fsl,cpm1-smc-uart") ||
1185 of_device_is_compatible(np, "fsl,cpm2-smc-uart")) {
1186 pinfo->flags |= FLAG_SMC;
1188 pinfo->smcup = pram = cpm_uart_map_pram(pinfo, np);
1199 pinfo->tx_nrfifos = TX_NUM_FIFO;
1200 pinfo->tx_fifosize = TX_BUF_SIZE;
1201 pinfo->rx_nrfifos = RX_NUM_FIFO;
1202 pinfo->rx_fifosize = RX_BUF_SIZE;
1204 pinfo->port.uartclk = ppc_proc_freq;
1205 pinfo->port.mapbase = (unsigned long)mem;
1206 pinfo->port.type = PORT_CPM;
1207 pinfo->port.ops = &cpm_uart_pops,
1208 pinfo->port.iotype = UPIO_MEM;
1209 pinfo->port.fifosize = pinfo->tx_nrfifos * pinfo->tx_fifosize;
1210 spin_lock_init(&pinfo->port.lock);
1212 pinfo->port.irq = irq_of_parse_and_map(np, 0);
1213 if (pinfo->port.irq == NO_IRQ) {
1218 for (i = 0; i < NUM_GPIOS; i++) {
1221 pinfo->gpios[i] = -1;
1223 gpio = of_get_gpio(np, i);
1225 if (gpio_is_valid(gpio)) {
1226 ret = gpio_request(gpio, "cpm_uart");
1228 pr_err("can't request gpio #%d: %d\n", i, ret);
1231 if (i == GPIO_RTS || i == GPIO_DTR)
1232 ret = gpio_direction_output(gpio, 0);
1234 ret = gpio_direction_input(gpio);
1236 pr_err("can't set direction for gpio #%d: %d\n",
1241 pinfo->gpios[i] = gpio;
1245 #ifdef CONFIG_PPC_EARLY_DEBUG_CPM
1249 return cpm_uart_request_port(&pinfo->port);
1252 cpm_uart_unmap_pram(pinfo, pram);
1258 #ifdef CONFIG_SERIAL_CPM_CONSOLE
1260 * Print a string to the serial port trying not to disturb
1261 * any possible real use of the port...
1263 * Note that this is called with interrupts already disabled
1265 static void cpm_uart_console_write(struct console *co, const char *s,
1268 struct uart_cpm_port *pinfo = &cpm_uart_ports[co->index];
1269 unsigned long flags;
1270 int nolock = oops_in_progress;
1272 if (unlikely(nolock)) {
1273 local_irq_save(flags);
1275 spin_lock_irqsave(&pinfo->port.lock, flags);
1278 cpm_uart_early_write(pinfo, s, count);
1280 if (unlikely(nolock)) {
1281 local_irq_restore(flags);
1283 spin_unlock_irqrestore(&pinfo->port.lock, flags);
1288 static int __init cpm_uart_console_setup(struct console *co, char *options)
1295 struct uart_cpm_port *pinfo;
1296 struct uart_port *port;
1298 struct device_node *np = NULL;
1301 if (co->index >= UART_NR) {
1302 printk(KERN_ERR "cpm_uart: console index %d too high\n",
1308 np = of_find_node_by_type(np, "serial");
1312 if (!of_device_is_compatible(np, "fsl,cpm1-smc-uart") &&
1313 !of_device_is_compatible(np, "fsl,cpm1-scc-uart") &&
1314 !of_device_is_compatible(np, "fsl,cpm2-smc-uart") &&
1315 !of_device_is_compatible(np, "fsl,cpm2-scc-uart"))
1317 } while (i++ != co->index);
1319 pinfo = &cpm_uart_ports[co->index];
1321 pinfo->flags |= FLAG_CONSOLE;
1322 port = &pinfo->port;
1324 ret = cpm_uart_init_port(np, pinfo);
1330 uart_parse_options(options, &baud, &parity, &bits, &flow);
1332 if ((baud = uart_baudrate()) == -1)
1336 if (IS_SMC(pinfo)) {
1337 out_be16(&pinfo->smcup->smc_brkcr, 0);
1338 cpm_line_cr_cmd(pinfo, CPM_CR_STOP_TX);
1339 clrbits8(&pinfo->smcp->smc_smcm, SMCM_RX | SMCM_TX);
1340 clrbits16(&pinfo->smcp->smc_smcmr, SMCMR_REN | SMCMR_TEN);
1342 out_be16(&pinfo->sccup->scc_brkcr, 0);
1343 cpm_line_cr_cmd(pinfo, CPM_CR_GRA_STOP_TX);
1344 clrbits16(&pinfo->sccp->scc_sccm, UART_SCCM_TX | UART_SCCM_RX);
1345 clrbits32(&pinfo->sccp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT);
1348 ret = cpm_uart_allocbuf(pinfo, 1);
1353 cpm_uart_initbd(pinfo);
1356 cpm_uart_init_smc(pinfo);
1358 cpm_uart_init_scc(pinfo);
1360 uart_set_options(port, co, baud, parity, bits, flow);
1361 cpm_line_cr_cmd(pinfo, CPM_CR_RESTART_TX);
1366 static struct uart_driver cpm_reg;
1367 static struct console cpm_scc_uart_console = {
1369 .write = cpm_uart_console_write,
1370 .device = uart_console_device,
1371 .setup = cpm_uart_console_setup,
1372 .flags = CON_PRINTBUFFER,
1377 static int __init cpm_uart_console_init(void)
1379 register_console(&cpm_scc_uart_console);
1383 console_initcall(cpm_uart_console_init);
1385 #define CPM_UART_CONSOLE &cpm_scc_uart_console
1387 #define CPM_UART_CONSOLE NULL
1390 static struct uart_driver cpm_reg = {
1391 .owner = THIS_MODULE,
1392 .driver_name = "ttyCPM",
1393 .dev_name = "ttyCPM",
1394 .major = SERIAL_CPM_MAJOR,
1395 .minor = SERIAL_CPM_MINOR,
1396 .cons = CPM_UART_CONSOLE,
1400 static int probe_index;
1402 static int cpm_uart_probe(struct platform_device *ofdev)
1404 int index = probe_index++;
1405 struct uart_cpm_port *pinfo = &cpm_uart_ports[index];
1408 pinfo->port.line = index;
1410 if (index >= UART_NR)
1413 platform_set_drvdata(ofdev, pinfo);
1415 /* initialize the device pointer for the port */
1416 pinfo->port.dev = &ofdev->dev;
1418 ret = cpm_uart_init_port(ofdev->dev.of_node, pinfo);
1422 return uart_add_one_port(&cpm_reg, &pinfo->port);
1425 static int cpm_uart_remove(struct platform_device *ofdev)
1427 struct uart_cpm_port *pinfo = platform_get_drvdata(ofdev);
1428 return uart_remove_one_port(&cpm_reg, &pinfo->port);
1431 static struct of_device_id cpm_uart_match[] = {
1433 .compatible = "fsl,cpm1-smc-uart",
1436 .compatible = "fsl,cpm1-scc-uart",
1439 .compatible = "fsl,cpm2-smc-uart",
1442 .compatible = "fsl,cpm2-scc-uart",
1447 static struct platform_driver cpm_uart_driver = {
1450 .owner = THIS_MODULE,
1451 .of_match_table = cpm_uart_match,
1453 .probe = cpm_uart_probe,
1454 .remove = cpm_uart_remove,
1457 static int __init cpm_uart_init(void)
1459 int ret = uart_register_driver(&cpm_reg);
1463 ret = platform_driver_register(&cpm_uart_driver);
1465 uart_unregister_driver(&cpm_reg);
1470 static void __exit cpm_uart_exit(void)
1472 platform_driver_unregister(&cpm_uart_driver);
1473 uart_unregister_driver(&cpm_reg);
1476 module_init(cpm_uart_init);
1477 module_exit(cpm_uart_exit);
1479 MODULE_AUTHOR("Kumar Gala/Antoniou Pantelis");
1480 MODULE_DESCRIPTION("CPM SCC/SMC port driver $Revision: 0.01 $");
1481 MODULE_LICENSE("GPL");
1482 MODULE_ALIAS_CHARDEV(SERIAL_CPM_MAJOR, SERIAL_CPM_MINOR);