Pileus Git - ~andy/linux/blob - drivers/tty/serial/8250/8250_pci.c

   1 /*
   2  *  Probe module for 8250/16550-type PCI serial ports.
   3  *
   4  *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
   5  *
   6  *  Copyright (C) 2001 Russell King, All Rights Reserved.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License.
  11  */
  12 #undef DEBUG
  13 #include <linux/module.h>
  14 #include <linux/pci.h>
  15 #include <linux/string.h>
  16 #include <linux/kernel.h>
  17 #include <linux/slab.h>
  18 #include <linux/delay.h>
  19 #include <linux/tty.h>
  20 #include <linux/serial_reg.h>
  21 #include <linux/serial_core.h>
  22 #include <linux/8250_pci.h>
  23 #include <linux/bitops.h>
  24
  25 #include <asm/byteorder.h>
  26 #include <asm/io.h>
  27
  28 #include "8250.h"
  29
  30 /*
  31  * init function returns:
  32  *  > 0 - number of ports
  33  *  = 0 - use board->num_ports
  34  *  < 0 - error
  35  */
  36 struct pci_serial_quirk {
  37         u32     vendor;
  38         u32     device;
  39         u32     subvendor;
  40         u32     subdevice;
  41         int     (*probe)(struct pci_dev *dev);
  42         int     (*init)(struct pci_dev *dev);
  43         int     (*setup)(struct serial_private *,
  44                          const struct pciserial_board *,
  45                          struct uart_8250_port *, int);
  46         void    (*exit)(struct pci_dev *dev);
  47 };
  48
  49 #define PCI_NUM_BAR_RESOURCES   6
  50
  51 struct serial_private {
  52         struct pci_dev          *dev;
  53         unsigned int            nr;
  54         void __iomem            *remapped_bar[PCI_NUM_BAR_RESOURCES];
  55         struct pci_serial_quirk *quirk;
  56         int                     line[0];
  57 };
  58
  59 static int pci_default_setup(struct serial_private*,
  60           const struct pciserial_board*, struct uart_8250_port *, int);
  61
  62 static void moan_device(const char *str, struct pci_dev *dev)
  63 {
  64         dev_err(&dev->dev,
  65                "%s: %s\n"
  66                "Please send the output of lspci -vv, this\n"
  67                "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
  68                "manufacturer and name of serial board or\n"
  69                "modem board to rmk+serial@arm.linux.org.uk.\n",
  70                pci_name(dev), str, dev->vendor, dev->device,
  71                dev->subsystem_vendor, dev->subsystem_device);
  72 }
  73
  74 static int
  75 setup_port(struct serial_private *priv, struct uart_8250_port *port,
  76            int bar, int offset, int regshift)
  77 {
  78         struct pci_dev *dev = priv->dev;
  79         unsigned long base, len;
  80
  81         if (bar >= PCI_NUM_BAR_RESOURCES)
  82                 return -EINVAL;
  83
  84         base = pci_resource_start(dev, bar);
  85
  86         if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
  87                 len =  pci_resource_len(dev, bar);
  88
  89                 if (!priv->remapped_bar[bar])
  90                         priv->remapped_bar[bar] = ioremap_nocache(base, len);
  91                 if (!priv->remapped_bar[bar])
  92                         return -ENOMEM;
  93
  94                 port->port.iotype = UPIO_MEM;
  95                 port->port.iobase = 0;
  96                 port->port.mapbase = base + offset;
  97                 port->port.membase = priv->remapped_bar[bar] + offset;
  98                 port->port.regshift = regshift;
  99         } else {
 100                 port->port.iotype = UPIO_PORT;
 101                 port->port.iobase = base + offset;
 102                 port->port.mapbase = 0;
 103                 port->port.membase = NULL;
 104                 port->port.regshift = 0;
 105         }
 106         return 0;
 107 }
 108
 109 /*
 110  * ADDI-DATA GmbH communication cards <info@addi-data.com>
 111  */
 112 static int addidata_apci7800_setup(struct serial_private *priv,
 113                                 const struct pciserial_board *board,
 114                                 struct uart_8250_port *port, int idx)
 115 {
 116         unsigned int bar = 0, offset = board->first_offset;
 117         bar = FL_GET_BASE(board->flags);
 118
 119         if (idx < 2) {
 120                 offset += idx * board->uart_offset;
 121         } else if ((idx >= 2) && (idx < 4)) {
 122                 bar += 1;
 123                 offset += ((idx - 2) * board->uart_offset);
 124         } else if ((idx >= 4) && (idx < 6)) {
 125                 bar += 2;
 126                 offset += ((idx - 4) * board->uart_offset);
 127         } else if (idx >= 6) {
 128                 bar += 3;
 129                 offset += ((idx - 6) * board->uart_offset);
 130         }
 131
 132         return setup_port(priv, port, bar, offset, board->reg_shift);
 133 }
 134
 135 /*
 136  * AFAVLAB uses a different mixture of BARs and offsets
 137  * Not that ugly ;) -- HW
 138  */
 139 static int
 140 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
 141               struct uart_8250_port *port, int idx)
 142 {
 143         unsigned int bar, offset = board->first_offset;
 144
 145         bar = FL_GET_BASE(board->flags);
 146         if (idx < 4)
 147                 bar += idx;
 148         else {
 149                 bar = 4;
 150                 offset += (idx - 4) * board->uart_offset;
 151         }
 152
 153         return setup_port(priv, port, bar, offset, board->reg_shift);
 154 }
 155
 156 /*
 157  * HP's Remote Management Console.  The Diva chip came in several
 158  * different versions.  N-class, L2000 and A500 have two Diva chips, each
 159  * with 3 UARTs (the third UART on the second chip is unused).  Superdome
 160  * and Keystone have one Diva chip with 3 UARTs.  Some later machines have
 161  * one Diva chip, but it has been expanded to 5 UARTs.
 162  */
 163 static int pci_hp_diva_init(struct pci_dev *dev)
 164 {
 165         int rc = 0;
 166
 167         switch (dev->subsystem_device) {
 168         case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
 169         case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
 170         case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
 171         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
 172                 rc = 3;
 173                 break;
 174         case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
 175                 rc = 2;
 176                 break;
 177         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
 178                 rc = 4;
 179                 break;
 180         case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
 181         case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
 182                 rc = 1;
 183                 break;
 184         }
 185
 186         return rc;
 187 }
 188
 189 /*
 190  * HP's Diva chip puts the 4th/5th serial port further out, and
 191  * some serial ports are supposed to be hidden on certain models.
 192  */
 193 static int
 194 pci_hp_diva_setup(struct serial_private *priv,
 195                 const struct pciserial_board *board,
 196                 struct uart_8250_port *port, int idx)
 197 {
 198         unsigned int offset = board->first_offset;
 199         unsigned int bar = FL_GET_BASE(board->flags);
 200
 201         switch (priv->dev->subsystem_device) {
 202         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
 203                 if (idx == 3)
 204                         idx++;
 205                 break;
 206         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
 207                 if (idx > 0)
 208                         idx++;
 209                 if (idx > 2)
 210                         idx++;
 211                 break;
 212         }
 213         if (idx > 2)
 214                 offset = 0x18;
 215
 216         offset += idx * board->uart_offset;
 217
 218         return setup_port(priv, port, bar, offset, board->reg_shift);
 219 }
 220
 221 /*
 222  * Added for EKF Intel i960 serial boards
 223  */
 224 static int pci_inteli960ni_init(struct pci_dev *dev)
 225 {
 226         unsigned long oldval;
 227
 228         if (!(dev->subsystem_device & 0x1000))
 229                 return -ENODEV;
 230
 231         /* is firmware started? */
 232         pci_read_config_dword(dev, 0x44, (void *)&oldval);
 233         if (oldval == 0x00001000L) { /* RESET value */
 234                 dev_dbg(&dev->dev, "Local i960 firmware missing\n");
 235                 return -ENODEV;
 236         }
 237         return 0;
 238 }
 239
 240 /*
 241  * Some PCI serial cards using the PLX 9050 PCI interface chip require
 242  * that the card interrupt be explicitly enabled or disabled.  This
 243  * seems to be mainly needed on card using the PLX which also use I/O
 244  * mapped memory.
 245  */
 246 static int pci_plx9050_init(struct pci_dev *dev)
 247 {
 248         u8 irq_config;
 249         void __iomem *p;
 250
 251         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
 252                 moan_device("no memory in bar 0", dev);
 253                 return 0;
 254         }
 255
 256         irq_config = 0x41;
 257         if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
 258             dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
 259                 irq_config = 0x43;
 260
 261         if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
 262             (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
 263                 /*
 264                  * As the megawolf cards have the int pins active
 265                  * high, and have 2 UART chips, both ints must be
 266                  * enabled on the 9050. Also, the UARTS are set in
 267                  * 16450 mode by default, so we have to enable the
 268                  * 16C950 'enhanced' mode so that we can use the
 269                  * deep FIFOs
 270                  */
 271                 irq_config = 0x5b;
 272         /*
 273          * enable/disable interrupts
 274          */
 275         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
 276         if (p == NULL)
 277                 return -ENOMEM;
 278         writel(irq_config, p + 0x4c);
 279
 280         /*
 281          * Read the register back to ensure that it took effect.
 282          */
 283         readl(p + 0x4c);
 284         iounmap(p);
 285
 286         return 0;
 287 }
 288
 289 static void pci_plx9050_exit(struct pci_dev *dev)
 290 {
 291         u8 __iomem *p;
 292
 293         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
 294                 return;
 295
 296         /*
 297          * disable interrupts
 298          */
 299         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
 300         if (p != NULL) {
 301                 writel(0, p + 0x4c);
 302
 303                 /*
 304                  * Read the register back to ensure that it took effect.
 305                  */
 306                 readl(p + 0x4c);
 307                 iounmap(p);
 308         }
 309 }
 310
 311 #define NI8420_INT_ENABLE_REG   0x38
 312 #define NI8420_INT_ENABLE_BIT   0x2000
 313
 314 static void pci_ni8420_exit(struct pci_dev *dev)
 315 {
 316         void __iomem *p;
 317         unsigned long base, len;
 318         unsigned int bar = 0;
 319
 320         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 321                 moan_device("no memory in bar", dev);
 322                 return;
 323         }
 324
 325         base = pci_resource_start(dev, bar);
 326         len =  pci_resource_len(dev, bar);
 327         p = ioremap_nocache(base, len);
 328         if (p == NULL)
 329                 return;
 330
 331         /* Disable the CPU Interrupt */
 332         writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
 333                p + NI8420_INT_ENABLE_REG);
 334         iounmap(p);
 335 }
 336
 337
 338 /* MITE registers */
 339 #define MITE_IOWBSR1    0xc4
 340 #define MITE_IOWCR1     0xf4
 341 #define MITE_LCIMR1     0x08
 342 #define MITE_LCIMR2     0x10
 343
 344 #define MITE_LCIMR2_CLR_CPU_IE  (1 << 30)
 345
 346 static void pci_ni8430_exit(struct pci_dev *dev)
 347 {
 348         void __iomem *p;
 349         unsigned long base, len;
 350         unsigned int bar = 0;
 351
 352         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 353                 moan_device("no memory in bar", dev);
 354                 return;
 355         }
 356
 357         base = pci_resource_start(dev, bar);
 358         len =  pci_resource_len(dev, bar);
 359         p = ioremap_nocache(base, len);
 360         if (p == NULL)
 361                 return;
 362
 363         /* Disable the CPU Interrupt */
 364         writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
 365         iounmap(p);
 366 }
 367
 368 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
 369 static int
 370 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
 371                 struct uart_8250_port *port, int idx)
 372 {
 373         unsigned int bar, offset = board->first_offset;
 374
 375         bar = 0;
 376
 377         if (idx < 4) {
 378                 /* first four channels map to 0, 0x100, 0x200, 0x300 */
 379                 offset += idx * board->uart_offset;
 380         } else if (idx < 8) {
 381                 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
 382                 offset += idx * board->uart_offset + 0xC00;
 383         } else /* we have only 8 ports on PMC-OCTALPRO */
 384                 return 1;
 385
 386         return setup_port(priv, port, bar, offset, board->reg_shift);
 387 }
 388
 389 /*
 390 * This does initialization for PMC OCTALPRO cards:
 391 * maps the device memory, resets the UARTs (needed, bc
 392 * if the module is removed and inserted again, the card
 393 * is in the sleep mode) and enables global interrupt.
 394 */
 395
 396 /* global control register offset for SBS PMC-OctalPro */
 397 #define OCT_REG_CR_OFF          0x500
 398
 399 static int sbs_init(struct pci_dev *dev)
 400 {
 401         u8 __iomem *p;
 402
 403         p = pci_ioremap_bar(dev, 0);
 404
 405         if (p == NULL)
 406                 return -ENOMEM;
 407         /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
 408         writeb(0x10, p + OCT_REG_CR_OFF);
 409         udelay(50);
 410         writeb(0x0, p + OCT_REG_CR_OFF);
 411
 412         /* Set bit-2 (INTENABLE) of Control Register */
 413         writeb(0x4, p + OCT_REG_CR_OFF);
 414         iounmap(p);
 415
 416         return 0;
 417 }
 418
 419 /*
 420  * Disables the global interrupt of PMC-OctalPro
 421  */
 422
 423 static void sbs_exit(struct pci_dev *dev)
 424 {
 425         u8 __iomem *p;
 426
 427         p = pci_ioremap_bar(dev, 0);
 428         /* FIXME: What if resource_len < OCT_REG_CR_OFF */
 429         if (p != NULL)
 430                 writeb(0, p + OCT_REG_CR_OFF);
 431         iounmap(p);
 432 }
 433
 434 /*
 435  * SIIG serial cards have an PCI interface chip which also controls
 436  * the UART clocking frequency. Each UART can be clocked independently
 437  * (except cards equipped with 4 UARTs) and initial clocking settings
 438  * are stored in the EEPROM chip. It can cause problems because this
 439  * version of serial driver doesn't support differently clocked UART's
 440  * on single PCI card. To prevent this, initialization functions set
 441  * high frequency clocking for all UART's on given card. It is safe (I
 442  * hope) because it doesn't touch EEPROM settings to prevent conflicts
 443  * with other OSes (like M$ DOS).
 444  *
 445  *  SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
 446  *
 447  * There is two family of SIIG serial cards with different PCI
 448  * interface chip and different configuration methods:
 449  *     - 10x cards have control registers in IO and/or memory space;
 450  *     - 20x cards have control registers in standard PCI configuration space.
 451  *
 452  * Note: all 10x cards have PCI device ids 0x10..
 453  *       all 20x cards have PCI device ids 0x20..
 454  *
 455  * There are also Quartet Serial cards which use Oxford Semiconductor
 456  * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
 457  *
 458  * Note: some SIIG cards are probed by the parport_serial object.
 459  */
 460
 461 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
 462 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
 463
 464 static int pci_siig10x_init(struct pci_dev *dev)
 465 {
 466         u16 data;
 467         void __iomem *p;
 468
 469         switch (dev->device & 0xfff8) {
 470         case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
 471                 data = 0xffdf;
 472                 break;
 473         case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
 474                 data = 0xf7ff;
 475                 break;
 476         default:                        /* 1S1P, 4S */
 477                 data = 0xfffb;
 478                 break;
 479         }
 480
 481         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
 482         if (p == NULL)
 483                 return -ENOMEM;
 484
 485         writew(readw(p + 0x28) & data, p + 0x28);
 486         readw(p + 0x28);
 487         iounmap(p);
 488         return 0;
 489 }
 490
 491 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
 492 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
 493
 494 static int pci_siig20x_init(struct pci_dev *dev)
 495 {
 496         u8 data;
 497
 498         /* Change clock frequency for the first UART. */
 499         pci_read_config_byte(dev, 0x6f, &data);
 500         pci_write_config_byte(dev, 0x6f, data & 0xef);
 501
 502         /* If this card has 2 UART, we have to do the same with second UART. */
 503         if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
 504             ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
 505                 pci_read_config_byte(dev, 0x73, &data);
 506                 pci_write_config_byte(dev, 0x73, data & 0xef);
 507         }
 508         return 0;
 509 }
 510
 511 static int pci_siig_init(struct pci_dev *dev)
 512 {
 513         unsigned int type = dev->device & 0xff00;
 514
 515         if (type == 0x1000)
 516                 return pci_siig10x_init(dev);
 517         else if (type == 0x2000)
 518                 return pci_siig20x_init(dev);
 519
 520         moan_device("Unknown SIIG card", dev);
 521         return -ENODEV;
 522 }
 523
 524 static int pci_siig_setup(struct serial_private *priv,
 525                           const struct pciserial_board *board,
 526                           struct uart_8250_port *port, int idx)
 527 {
 528         unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
 529
 530         if (idx > 3) {
 531                 bar = 4;
 532                 offset = (idx - 4) * 8;
 533         }
 534
 535         return setup_port(priv, port, bar, offset, 0);
 536 }
 537
 538 /*
 539  * Timedia has an explosion of boards, and to avoid the PCI table from
 540  * growing *huge*, we use this function to collapse some 70 entries
 541  * in the PCI table into one, for sanity's and compactness's sake.
 542  */
 543 static const unsigned short timedia_single_port[] = {
 544         0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
 545 };
 546
 547 static const unsigned short timedia_dual_port[] = {
 548         0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
 549         0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
 550         0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
 551         0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
 552         0xD079, 0
 553 };
 554
 555 static const unsigned short timedia_quad_port[] = {
 556         0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
 557         0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
 558         0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
 559         0xB157, 0
 560 };
 561
 562 static const unsigned short timedia_eight_port[] = {
 563         0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
 564         0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
 565 };
 566
 567 static const struct timedia_struct {
 568         int num;
 569         const unsigned short *ids;
 570 } timedia_data[] = {
 571         { 1, timedia_single_port },
 572         { 2, timedia_dual_port },
 573         { 4, timedia_quad_port },
 574         { 8, timedia_eight_port }
 575 };
 576
 577 /*
 578  * There are nearly 70 different Timedia/SUNIX PCI serial devices.  Instead of
 579  * listing them individually, this driver merely grabs them all with
 580  * PCI_ANY_ID.  Some of these devices, however, also feature a parallel port,
 581  * and should be left free to be claimed by parport_serial instead.
 582  */
 583 static int pci_timedia_probe(struct pci_dev *dev)
 584 {
 585         /*
 586          * Check the third digit of the subdevice ID
 587          * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
 588          */
 589         if ((dev->subsystem_device & 0x00f0) >= 0x70) {
 590                 dev_info(&dev->dev,
 591                         "ignoring Timedia subdevice %04x for parport_serial\n",
 592                         dev->subsystem_device);
 593                 return -ENODEV;
 594         }
 595
 596         return 0;
 597 }
 598
 599 static int pci_timedia_init(struct pci_dev *dev)
 600 {
 601         const unsigned short *ids;
 602         int i, j;
 603
 604         for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
 605                 ids = timedia_data[i].ids;
 606                 for (j = 0; ids[j]; j++)
 607                         if (dev->subsystem_device == ids[j])
 608                                 return timedia_data[i].num;
 609         }
 610         return 0;
 611 }
 612
 613 /*
 614  * Timedia/SUNIX uses a mixture of BARs and offsets
 615  * Ugh, this is ugly as all hell --- TYT
 616  */
 617 static int
 618 pci_timedia_setup(struct serial_private *priv,
 619                   const struct pciserial_board *board,
 620                   struct uart_8250_port *port, int idx)
 621 {
 622         unsigned int bar = 0, offset = board->first_offset;
 623
 624         switch (idx) {
 625         case 0:
 626                 bar = 0;
 627                 break;
 628         case 1:
 629                 offset = board->uart_offset;
 630                 bar = 0;
 631                 break;
 632         case 2:
 633                 bar = 1;
 634                 break;
 635         case 3:
 636                 offset = board->uart_offset;
 637                 /* FALLTHROUGH */
 638         case 4: /* BAR 2 */
 639         case 5: /* BAR 3 */
 640         case 6: /* BAR 4 */
 641         case 7: /* BAR 5 */
 642                 bar = idx - 2;
 643         }
 644
 645         return setup_port(priv, port, bar, offset, board->reg_shift);
 646 }
 647
 648 /*
 649  * Some Titan cards are also a little weird
 650  */
 651 static int
 652 titan_400l_800l_setup(struct serial_private *priv,
 653                       const struct pciserial_board *board,
 654                       struct uart_8250_port *port, int idx)
 655 {
 656         unsigned int bar, offset = board->first_offset;
 657
 658         switch (idx) {
 659         case 0:
 660                 bar = 1;
 661                 break;
 662         case 1:
 663                 bar = 2;
 664                 break;
 665         default:
 666                 bar = 4;
 667                 offset = (idx - 2) * board->uart_offset;
 668         }
 669
 670         return setup_port(priv, port, bar, offset, board->reg_shift);
 671 }
 672
 673 static int pci_xircom_init(struct pci_dev *dev)
 674 {
 675         msleep(100);
 676         return 0;
 677 }
 678
 679 static int pci_ni8420_init(struct pci_dev *dev)
 680 {
 681         void __iomem *p;
 682         unsigned long base, len;
 683         unsigned int bar = 0;
 684
 685         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 686                 moan_device("no memory in bar", dev);
 687                 return 0;
 688         }
 689
 690         base = pci_resource_start(dev, bar);
 691         len =  pci_resource_len(dev, bar);
 692         p = ioremap_nocache(base, len);
 693         if (p == NULL)
 694                 return -ENOMEM;
 695
 696         /* Enable CPU Interrupt */
 697         writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
 698                p + NI8420_INT_ENABLE_REG);
 699
 700         iounmap(p);
 701         return 0;
 702 }
 703
 704 #define MITE_IOWBSR1_WSIZE      0xa
 705 #define MITE_IOWBSR1_WIN_OFFSET 0x800
 706 #define MITE_IOWBSR1_WENAB      (1 << 7)
 707 #define MITE_LCIMR1_IO_IE_0     (1 << 24)
 708 #define MITE_LCIMR2_SET_CPU_IE  (1 << 31)
 709 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
 710
 711 static int pci_ni8430_init(struct pci_dev *dev)
 712 {
 713         void __iomem *p;
 714         unsigned long base, len;
 715         u32 device_window;
 716         unsigned int bar = 0;
 717
 718         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 719                 moan_device("no memory in bar", dev);
 720                 return 0;
 721         }
 722
 723         base = pci_resource_start(dev, bar);
 724         len =  pci_resource_len(dev, bar);
 725         p = ioremap_nocache(base, len);
 726         if (p == NULL)
 727                 return -ENOMEM;
 728
 729         /* Set device window address and size in BAR0 */
 730         device_window = ((base + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
 731                         | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
 732         writel(device_window, p + MITE_IOWBSR1);
 733
 734         /* Set window access to go to RAMSEL IO address space */
 735         writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
 736                p + MITE_IOWCR1);
 737
 738         /* Enable IO Bus Interrupt 0 */
 739         writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
 740
 741         /* Enable CPU Interrupt */
 742         writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
 743
 744         iounmap(p);
 745         return 0;
 746 }
 747
 748 /* UART Port Control Register */
 749 #define NI8430_PORTCON  0x0f
 750 #define NI8430_PORTCON_TXVR_ENABLE      (1 << 3)
 751
 752 static int
 753 pci_ni8430_setup(struct serial_private *priv,
 754                  const struct pciserial_board *board,
 755                  struct uart_8250_port *port, int idx)
 756 {
 757         void __iomem *p;
 758         unsigned long base, len;
 759         unsigned int bar, offset = board->first_offset;
 760
 761         if (idx >= board->num_ports)
 762                 return 1;
 763
 764         bar = FL_GET_BASE(board->flags);
 765         offset += idx * board->uart_offset;
 766
 767         base = pci_resource_start(priv->dev, bar);
 768         len =  pci_resource_len(priv->dev, bar);
 769         p = ioremap_nocache(base, len);
 770
 771         /* enable the transceiver */
 772         writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
 773                p + offset + NI8430_PORTCON);
 774
 775         iounmap(p);
 776
 777         return setup_port(priv, port, bar, offset, board->reg_shift);
 778 }
 779
 780 static int pci_netmos_9900_setup(struct serial_private *priv,
 781                                 const struct pciserial_board *board,
 782                                 struct uart_8250_port *port, int idx)
 783 {
 784         unsigned int bar;
 785
 786         if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) &&
 787             (priv->dev->subsystem_device & 0xff00) == 0x3000) {
 788                 /* netmos apparently orders BARs by datasheet layout, so serial
 789                  * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
 790                  */
 791                 bar = 3 * idx;
 792
 793                 return setup_port(priv, port, bar, 0, board->reg_shift);
 794         } else {
 795                 return pci_default_setup(priv, board, port, idx);
 796         }
 797 }
 798
 799 /* the 99xx series comes with a range of device IDs and a variety
 800  * of capabilities:
 801  *
 802  * 9900 has varying capabilities and can cascade to sub-controllers
 803  *   (cascading should be purely internal)
 804  * 9904 is hardwired with 4 serial ports
 805  * 9912 and 9922 are hardwired with 2 serial ports
 806  */
 807 static int pci_netmos_9900_numports(struct pci_dev *dev)
 808 {
 809         unsigned int c = dev->class;
 810         unsigned int pi;
 811         unsigned short sub_serports;
 812
 813         pi = (c & 0xff);
 814
 815         if (pi == 2) {
 816                 return 1;
 817         } else if ((pi == 0) &&
 818                            (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
 819                 /* two possibilities: 0x30ps encodes number of parallel and
 820                  * serial ports, or 0x1000 indicates *something*. This is not
 821                  * immediately obvious, since the 2s1p+4s configuration seems
 822                  * to offer all functionality on functions 0..2, while still
 823                  * advertising the same function 3 as the 4s+2s1p config.
 824                  */
 825                 sub_serports = dev->subsystem_device & 0xf;
 826                 if (sub_serports > 0) {
 827                         return sub_serports;
 828                 } else {
 829                         dev_err(&dev->dev, "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
 830                         return 0;
 831                 }
 832         }
 833
 834         moan_device("unknown NetMos/Mostech program interface", dev);
 835         return 0;
 836 }
 837
 838 static int pci_netmos_init(struct pci_dev *dev)
 839 {
 840         /* subdevice 0x00PS means <P> parallel, <S> serial */
 841         unsigned int num_serial = dev->subsystem_device & 0xf;
 842
 843         if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
 844                 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
 845                 return 0;
 846
 847         if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
 848                         dev->subsystem_device == 0x0299)
 849                 return 0;
 850
 851         switch (dev->device) { /* FALLTHROUGH on all */
 852                 case PCI_DEVICE_ID_NETMOS_9904:
 853                 case PCI_DEVICE_ID_NETMOS_9912:
 854                 case PCI_DEVICE_ID_NETMOS_9922:
 855                 case PCI_DEVICE_ID_NETMOS_9900:
 856                         num_serial = pci_netmos_9900_numports(dev);
 857                         break;
 858
 859                 default:
 860                         if (num_serial == 0 ) {
 861                                 moan_device("unknown NetMos/Mostech device", dev);
 862                         }
 863         }
 864
 865         if (num_serial == 0)
 866                 return -ENODEV;
 867
 868         return num_serial;
 869 }
 870
 871 /*
 872  * These chips are available with optionally one parallel port and up to
 873  * two serial ports. Unfortunately they all have the same product id.
 874  *
 875  * Basic configuration is done over a region of 32 I/O ports. The base
 876  * ioport is called INTA or INTC, depending on docs/other drivers.
 877  *
 878  * The region of the 32 I/O ports is configured in POSIO0R...
 879  */
 880
 881 /* registers */
 882 #define ITE_887x_MISCR          0x9c
 883 #define ITE_887x_INTCBAR        0x78
 884 #define ITE_887x_UARTBAR        0x7c
 885 #define ITE_887x_PS0BAR         0x10
 886 #define ITE_887x_POSIO0         0x60
 887
 888 /* I/O space size */
 889 #define ITE_887x_IOSIZE         32
 890 /* I/O space size (bits 26-24; 8 bytes = 011b) */
 891 #define ITE_887x_POSIO_IOSIZE_8         (3 << 24)
 892 /* I/O space size (bits 26-24; 32 bytes = 101b) */
 893 #define ITE_887x_POSIO_IOSIZE_32        (5 << 24)
 894 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
 895 #define ITE_887x_POSIO_SPEED            (3 << 29)
 896 /* enable IO_Space bit */
 897 #define ITE_887x_POSIO_ENABLE           (1 << 31)
 898
 899 static int pci_ite887x_init(struct pci_dev *dev)
 900 {
 901         /* inta_addr are the configuration addresses of the ITE */
 902         static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
 903                                                         0x200, 0x280, 0 };
 904         int ret, i, type;
 905         struct resource *iobase = NULL;
 906         u32 miscr, uartbar, ioport;
 907
 908         /* search for the base-ioport */
 909         i = 0;
 910         while (inta_addr[i] && iobase == NULL) {
 911                 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
 912                                                                 "ite887x");
 913                 if (iobase != NULL) {
 914                         /* write POSIO0R - speed | size | ioport */
 915                         pci_write_config_dword(dev, ITE_887x_POSIO0,
 916                                 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
 917                                 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
 918                         /* write INTCBAR - ioport */
 919                         pci_write_config_dword(dev, ITE_887x_INTCBAR,
 920                                                                 inta_addr[i]);
 921                         ret = inb(inta_addr[i]);
 922                         if (ret != 0xff) {
 923                                 /* ioport connected */
 924                                 break;
 925                         }
 926                         release_region(iobase->start, ITE_887x_IOSIZE);
 927                         iobase = NULL;
 928                 }
 929                 i++;
 930         }
 931
 932         if (!inta_addr[i]) {
 933                 dev_err(&dev->dev, "ite887x: could not find iobase\n");
 934                 return -ENODEV;
 935         }
 936
 937         /* start of undocumented type checking (see parport_pc.c) */
 938         type = inb(iobase->start + 0x18) & 0x0f;
 939
 940         switch (type) {
 941         case 0x2:       /* ITE8871 (1P) */
 942         case 0xa:       /* ITE8875 (1P) */
 943                 ret = 0;
 944                 break;
 945         case 0xe:       /* ITE8872 (2S1P) */
 946                 ret = 2;
 947                 break;
 948         case 0x6:       /* ITE8873 (1S) */
 949                 ret = 1;
 950                 break;
 951         case 0x8:       /* ITE8874 (2S) */
 952                 ret = 2;
 953                 break;
 954         default:
 955                 moan_device("Unknown ITE887x", dev);
 956                 ret = -ENODEV;
 957         }
 958
 959         /* configure all serial ports */
 960         for (i = 0; i < ret; i++) {
 961                 /* read the I/O port from the device */
 962                 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
 963                                                                 &ioport);
 964                 ioport &= 0x0000FF00;   /* the actual base address */
 965                 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
 966                         ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
 967                         ITE_887x_POSIO_IOSIZE_8 | ioport);
 968
 969                 /* write the ioport to the UARTBAR */
 970                 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
 971                 uartbar &= ~(0xffff << (16 * i));       /* clear half the reg */
 972                 uartbar |= (ioport << (16 * i));        /* set the ioport */
 973                 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
 974
 975                 /* get current config */
 976                 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
 977                 /* disable interrupts (UARTx_Routing[3:0]) */
 978                 miscr &= ~(0xf << (12 - 4 * i));
 979                 /* activate the UART (UARTx_En) */
 980                 miscr |= 1 << (23 - i);
 981                 /* write new config with activated UART */
 982                 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
 983         }
 984
 985         if (ret <= 0) {
 986                 /* the device has no UARTs if we get here */
 987                 release_region(iobase->start, ITE_887x_IOSIZE);
 988         }
 989
 990         return ret;
 991 }
 992
 993 static void pci_ite887x_exit(struct pci_dev *dev)
 994 {
 995         u32 ioport;
 996         /* the ioport is bit 0-15 in POSIO0R */
 997         pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
 998         ioport &= 0xffff;
 999         release_region(ioport, ITE_887x_IOSIZE);
1000 }
1001
1002 /*
1003  * Oxford Semiconductor Inc.
1004  * Check that device is part of the Tornado range of devices, then determine
1005  * the number of ports available on the device.
1006  */
1007 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1008 {
1009         u8 __iomem *p;
1010         unsigned long deviceID;
1011         unsigned int  number_uarts = 0;
1012
1013         /* OxSemi Tornado devices are all 0xCxxx */
1014         if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1015             (dev->device & 0xF000) != 0xC000)
1016                 return 0;
1017
1018         p = pci_iomap(dev, 0, 5);
1019         if (p == NULL)
1020                 return -ENOMEM;
1021
1022         deviceID = ioread32(p);
1023         /* Tornado device */
1024         if (deviceID == 0x07000200) {
1025                 number_uarts = ioread8(p + 4);
1026                 dev_dbg(&dev->dev,
1027                         "%d ports detected on Oxford PCI Express device\n",
1028                         number_uarts);
1029         }
1030         pci_iounmap(dev, p);
1031         return number_uarts;
1032 }
1033
1034 static int pci_asix_setup(struct serial_private *priv,
1035                   const struct pciserial_board *board,
1036                   struct uart_8250_port *port, int idx)
1037 {
1038         port->bugs |= UART_BUG_PARITY;
1039         return pci_default_setup(priv, board, port, idx);
1040 }
1041
1042 /* Quatech devices have their own extra interface features */
1043
1044 struct quatech_feature {
1045         u16 devid;
1046         bool amcc;
1047 };
1048
1049 #define QPCR_TEST_FOR1          0x3F
1050 #define QPCR_TEST_GET1          0x00
1051 #define QPCR_TEST_FOR2          0x40
1052 #define QPCR_TEST_GET2          0x40
1053 #define QPCR_TEST_FOR3          0x80
1054 #define QPCR_TEST_GET3          0x40
1055 #define QPCR_TEST_FOR4          0xC0
1056 #define QPCR_TEST_GET4          0x80
1057
1058 #define QOPR_CLOCK_X1           0x0000
1059 #define QOPR_CLOCK_X2           0x0001
1060 #define QOPR_CLOCK_X4           0x0002
1061 #define QOPR_CLOCK_X8           0x0003
1062 #define QOPR_CLOCK_RATE_MASK    0x0003
1063
1064
1065 static struct quatech_feature quatech_cards[] = {
1066         { PCI_DEVICE_ID_QUATECH_QSC100,   1 },
1067         { PCI_DEVICE_ID_QUATECH_DSC100,   1 },
1068         { PCI_DEVICE_ID_QUATECH_DSC100E,  0 },
1069         { PCI_DEVICE_ID_QUATECH_DSC200,   1 },
1070         { PCI_DEVICE_ID_QUATECH_DSC200E,  0 },
1071         { PCI_DEVICE_ID_QUATECH_ESC100D,  1 },
1072         { PCI_DEVICE_ID_QUATECH_ESC100M,  1 },
1073         { PCI_DEVICE_ID_QUATECH_QSCP100,  1 },
1074         { PCI_DEVICE_ID_QUATECH_DSCP100,  1 },
1075         { PCI_DEVICE_ID_QUATECH_QSCP200,  1 },
1076         { PCI_DEVICE_ID_QUATECH_DSCP200,  1 },
1077         { PCI_DEVICE_ID_QUATECH_ESCLP100, 0 },
1078         { PCI_DEVICE_ID_QUATECH_QSCLP100, 0 },
1079         { PCI_DEVICE_ID_QUATECH_DSCLP100, 0 },
1080         { PCI_DEVICE_ID_QUATECH_SSCLP100, 0 },
1081         { PCI_DEVICE_ID_QUATECH_QSCLP200, 0 },
1082         { PCI_DEVICE_ID_QUATECH_DSCLP200, 0 },
1083         { PCI_DEVICE_ID_QUATECH_SSCLP200, 0 },
1084         { PCI_DEVICE_ID_QUATECH_SPPXP_100, 0 },
1085         { 0, }
1086 };
1087
1088 static int pci_quatech_amcc(u16 devid)
1089 {
1090         struct quatech_feature *qf = &quatech_cards[0];
1091         while (qf->devid) {
1092                 if (qf->devid == devid)
1093                         return qf->amcc;
1094                 qf++;
1095         }
1096         pr_err("quatech: unknown port type '0x%04X'.\n", devid);
1097         return 0;
1098 };
1099
1100 static int pci_quatech_rqopr(struct uart_8250_port *port)
1101 {
1102         unsigned long base = port->port.iobase;
1103         u8 LCR, val;
1104
1105         LCR = inb(base + UART_LCR);
1106         outb(0xBF, base + UART_LCR);
1107         val = inb(base + UART_SCR);
1108         outb(LCR, base + UART_LCR);
1109         return val;
1110 }
1111
1112 static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr)
1113 {
1114         unsigned long base = port->port.iobase;
1115         u8 LCR, val;
1116
1117         LCR = inb(base + UART_LCR);
1118         outb(0xBF, base + UART_LCR);
1119         val = inb(base + UART_SCR);
1120         outb(qopr, base + UART_SCR);
1121         outb(LCR, base + UART_LCR);
1122 }
1123
1124 static int pci_quatech_rqmcr(struct uart_8250_port *port)
1125 {
1126         unsigned long base = port->port.iobase;
1127         u8 LCR, val, qmcr;
1128
1129         LCR = inb(base + UART_LCR);
1130         outb(0xBF, base + UART_LCR);
1131         val = inb(base + UART_SCR);
1132         outb(val | 0x10, base + UART_SCR);
1133         qmcr = inb(base + UART_MCR);
1134         outb(val, base + UART_SCR);
1135         outb(LCR, base + UART_LCR);
1136
1137         return qmcr;
1138 }
1139
1140 static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr)
1141 {
1142         unsigned long base = port->port.iobase;
1143         u8 LCR, val;
1144
1145         LCR = inb(base + UART_LCR);
1146         outb(0xBF, base + UART_LCR);
1147         val = inb(base + UART_SCR);
1148         outb(val | 0x10, base + UART_SCR);
1149         outb(qmcr, base + UART_MCR);
1150         outb(val, base + UART_SCR);
1151         outb(LCR, base + UART_LCR);
1152 }
1153
1154 static int pci_quatech_has_qmcr(struct uart_8250_port *port)
1155 {
1156         unsigned long base = port->port.iobase;
1157         u8 LCR, val;
1158
1159         LCR = inb(base + UART_LCR);
1160         outb(0xBF, base + UART_LCR);
1161         val = inb(base + UART_SCR);
1162         if (val & 0x20) {
1163                 outb(0x80, UART_LCR);
1164                 if (!(inb(UART_SCR) & 0x20)) {
1165                         outb(LCR, base + UART_LCR);
1166                         return 1;
1167                 }
1168         }
1169         return 0;
1170 }
1171
1172 static int pci_quatech_test(struct uart_8250_port *port)
1173 {
1174         u8 reg;
1175         u8 qopr = pci_quatech_rqopr(port);
1176         pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1);
1177         reg = pci_quatech_rqopr(port) & 0xC0;
1178         if (reg != QPCR_TEST_GET1)
1179                 return -EINVAL;
1180         pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2);
1181         reg = pci_quatech_rqopr(port) & 0xC0;
1182         if (reg != QPCR_TEST_GET2)
1183                 return -EINVAL;
1184         pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3);
1185         reg = pci_quatech_rqopr(port) & 0xC0;
1186         if (reg != QPCR_TEST_GET3)
1187                 return -EINVAL;
1188         pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4);
1189         reg = pci_quatech_rqopr(port) & 0xC0;
1190         if (reg != QPCR_TEST_GET4)
1191                 return -EINVAL;
1192
1193         pci_quatech_wqopr(port, qopr);
1194         return 0;
1195 }
1196
1197 static int pci_quatech_clock(struct uart_8250_port *port)
1198 {
1199         u8 qopr, reg, set;
1200         unsigned long clock;
1201
1202         if (pci_quatech_test(port) < 0)
1203                 return 1843200;
1204
1205         qopr = pci_quatech_rqopr(port);
1206
1207         pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8);
1208         reg = pci_quatech_rqopr(port);
1209         if (reg & QOPR_CLOCK_X8) {
1210                 clock = 1843200;
1211                 goto out;
1212         }
1213         pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8);
1214         reg = pci_quatech_rqopr(port);
1215         if (!(reg & QOPR_CLOCK_X8)) {
1216                 clock = 1843200;
1217                 goto out;
1218         }
1219         reg &= QOPR_CLOCK_X8;
1220         if (reg == QOPR_CLOCK_X2) {
1221                 clock =  3685400;
1222                 set = QOPR_CLOCK_X2;
1223         } else if (reg == QOPR_CLOCK_X4) {
1224                 clock = 7372800;
1225                 set = QOPR_CLOCK_X4;
1226         } else if (reg == QOPR_CLOCK_X8) {
1227                 clock = 14745600;
1228                 set = QOPR_CLOCK_X8;
1229         } else {
1230                 clock = 1843200;
1231                 set = QOPR_CLOCK_X1;
1232         }
1233         qopr &= ~QOPR_CLOCK_RATE_MASK;
1234         qopr |= set;
1235
1236 out:
1237         pci_quatech_wqopr(port, qopr);
1238         return clock;
1239 }
1240
1241 static int pci_quatech_rs422(struct uart_8250_port *port)
1242 {
1243         u8 qmcr;
1244         int rs422 = 0;
1245
1246         if (!pci_quatech_has_qmcr(port))
1247                 return 0;
1248         qmcr = pci_quatech_rqmcr(port);
1249         pci_quatech_wqmcr(port, 0xFF);
1250         if (pci_quatech_rqmcr(port))
1251                 rs422 = 1;
1252         pci_quatech_wqmcr(port, qmcr);
1253         return rs422;
1254 }
1255
1256 static int pci_quatech_init(struct pci_dev *dev)
1257 {
1258         if (pci_quatech_amcc(dev->device)) {
1259                 unsigned long base = pci_resource_start(dev, 0);
1260                 if (base) {
1261                         u32 tmp;
1262                         outl(inl(base + 0x38) | 0x00002000, base + 0x38);
1263                         tmp = inl(base + 0x3c);
1264                         outl(tmp | 0x01000000, base + 0x3c);
1265                         outl(tmp &= ~0x01000000, base + 0x3c);
1266                 }
1267         }
1268         return 0;
1269 }
1270
1271 static int pci_quatech_setup(struct serial_private *priv,
1272                   const struct pciserial_board *board,
1273                   struct uart_8250_port *port, int idx)
1274 {
1275         /* Needed by pci_quatech calls below */
1276         port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags));
1277         /* Set up the clocking */
1278         port->port.uartclk = pci_quatech_clock(port);
1279         /* For now just warn about RS422 */
1280         if (pci_quatech_rs422(port))
1281                 pr_warn("quatech: software control of RS422 features not currently supported.\n");
1282         return pci_default_setup(priv, board, port, idx);
1283 }
1284
1285 static void pci_quatech_exit(struct pci_dev *dev)
1286 {
1287 }
1288
1289 static int pci_default_setup(struct serial_private *priv,
1290                   const struct pciserial_board *board,
1291                   struct uart_8250_port *port, int idx)
1292 {
1293         unsigned int bar, offset = board->first_offset, maxnr;
1294
1295         bar = FL_GET_BASE(board->flags);
1296         if (board->flags & FL_BASE_BARS)
1297                 bar += idx;
1298         else
1299                 offset += idx * board->uart_offset;
1300
1301         maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1302                 (board->reg_shift + 3);
1303
1304         if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1305                 return 1;
1306
1307         return setup_port(priv, port, bar, offset, board->reg_shift);
1308 }
1309
1310 static int pci_pericom_setup(struct serial_private *priv,
1311                   const struct pciserial_board *board,
1312                   struct uart_8250_port *port, int idx)
1313 {
1314         unsigned int bar, offset = board->first_offset, maxnr;
1315
1316         bar = FL_GET_BASE(board->flags);
1317         if (board->flags & FL_BASE_BARS)
1318                 bar += idx;
1319         else
1320                 offset += idx * board->uart_offset;
1321
1322         maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1323                 (board->reg_shift + 3);
1324
1325         if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1326                 return 1;
1327
1328         port->port.uartclk = 14745600;
1329
1330         return setup_port(priv, port, bar, offset, board->reg_shift);
1331 }
1332
1333 static int
1334 ce4100_serial_setup(struct serial_private *priv,
1335                   const struct pciserial_board *board,
1336                   struct uart_8250_port *port, int idx)
1337 {
1338         int ret;
1339
1340         ret = setup_port(priv, port, idx, 0, board->reg_shift);
1341         port->port.iotype = UPIO_MEM32;
1342         port->port.type = PORT_XSCALE;
1343         port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1344         port->port.regshift = 2;
1345
1346         return ret;
1347 }
1348
1349 #define PCI_DEVICE_ID_INTEL_BYT_UART1   0x0f0a
1350 #define PCI_DEVICE_ID_INTEL_BYT_UART2   0x0f0c
1351
1352 #define BYT_PRV_CLK                     0x800
1353 #define BYT_PRV_CLK_EN                  (1 << 0)
1354 #define BYT_PRV_CLK_M_VAL_SHIFT         1
1355 #define BYT_PRV_CLK_N_VAL_SHIFT         16
1356 #define BYT_PRV_CLK_UPDATE              (1 << 31)
1357
1358 #define BYT_GENERAL_REG                 0x808
1359 #define BYT_GENERAL_DIS_RTS_N_OVERRIDE  (1 << 3)
1360
1361 #define BYT_TX_OVF_INT                  0x820
1362 #define BYT_TX_OVF_INT_MASK             (1 << 1)
1363
1364 static void
1365 byt_set_termios(struct uart_port *p, struct ktermios *termios,
1366                 struct ktermios *old)
1367 {
1368         unsigned int baud = tty_termios_baud_rate(termios);
1369         unsigned int m = 6912;
1370         unsigned int n = 15625;
1371         u32 reg;
1372
1373         /* For baud rates 1M, 2M, 3M and 4M the dividers must be adjusted. */
1374         if (baud == 1000000 || baud == 2000000 || baud == 4000000) {
1375                 m = 64;
1376                 n = 100;
1377
1378                 p->uartclk = 64000000;
1379         } else if (baud == 3000000) {
1380                 m = 48;
1381                 n = 100;
1382
1383                 p->uartclk = 48000000;
1384         } else {
1385                 p->uartclk = 44236800;
1386         }
1387
1388         /* Reset the clock */
1389         reg = (m << BYT_PRV_CLK_M_VAL_SHIFT) | (n << BYT_PRV_CLK_N_VAL_SHIFT);
1390         writel(reg, p->membase + BYT_PRV_CLK);
1391         reg |= BYT_PRV_CLK_EN | BYT_PRV_CLK_UPDATE;
1392         writel(reg, p->membase + BYT_PRV_CLK);
1393
1394         /*
1395          * If auto-handshake mechanism is not enabled,
1396          * disable rts_n override
1397          */
1398         reg = readl(p->membase + BYT_GENERAL_REG);
1399         reg &= ~BYT_GENERAL_DIS_RTS_N_OVERRIDE;
1400         if (termios->c_cflag & CRTSCTS)
1401                 reg |= BYT_GENERAL_DIS_RTS_N_OVERRIDE;
1402         writel(reg, p->membase + BYT_GENERAL_REG);
1403
1404         serial8250_do_set_termios(p, termios, old);
1405 }
1406
1407 static bool byt_dma_filter(struct dma_chan *chan, void *param)
1408 {
1409         return chan->chan_id == *(int *)param;
1410 }
1411
1412 static int
1413 byt_serial_setup(struct serial_private *priv,
1414                  const struct pciserial_board *board,
1415                  struct uart_8250_port *port, int idx)
1416 {
1417         struct uart_8250_dma *dma;
1418         int ret;
1419
1420         dma = devm_kzalloc(port->port.dev, sizeof(*dma), GFP_KERNEL);
1421         if (!dma)
1422                 return -ENOMEM;
1423
1424         switch (priv->dev->device) {
1425         case PCI_DEVICE_ID_INTEL_BYT_UART1:
1426                 dma->rx_chan_id = 3;
1427                 dma->tx_chan_id = 2;
1428                 break;
1429         case PCI_DEVICE_ID_INTEL_BYT_UART2:
1430                 dma->rx_chan_id = 5;
1431                 dma->tx_chan_id = 4;
1432                 break;
1433         default:
1434                 return -EINVAL;
1435         }
1436
1437         dma->rxconf.slave_id = dma->rx_chan_id;
1438         dma->rxconf.src_maxburst = 16;
1439
1440         dma->txconf.slave_id = dma->tx_chan_id;
1441         dma->txconf.dst_maxburst = 16;
1442
1443         dma->fn = byt_dma_filter;
1444         dma->rx_param = &dma->rx_chan_id;
1445         dma->tx_param = &dma->tx_chan_id;
1446
1447         ret = pci_default_setup(priv, board, port, idx);
1448         port->port.iotype = UPIO_MEM;
1449         port->port.type = PORT_16550A;
1450         port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1451         port->port.set_termios = byt_set_termios;
1452         port->port.fifosize = 64;
1453         port->tx_loadsz = 64;
1454         port->dma = dma;
1455         port->capabilities = UART_CAP_FIFO | UART_CAP_AFE;
1456
1457         /* Disable Tx counter interrupts */
1458         writel(BYT_TX_OVF_INT_MASK, port->port.membase + BYT_TX_OVF_INT);
1459
1460         return ret;
1461 }
1462
1463 static int
1464 pci_omegapci_setup(struct serial_private *priv,
1465                       const struct pciserial_board *board,
1466                       struct uart_8250_port *port, int idx)
1467 {
1468         return setup_port(priv, port, 2, idx * 8, 0);
1469 }
1470
1471 static int
1472 pci_brcm_trumanage_setup(struct serial_private *priv,
1473                          const struct pciserial_board *board,
1474                          struct uart_8250_port *port, int idx)
1475 {
1476         int ret = pci_default_setup(priv, board, port, idx);
1477
1478         port->port.type = PORT_BRCM_TRUMANAGE;
1479         port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1480         return ret;
1481 }
1482
1483 static int pci_fintek_setup(struct serial_private *priv,
1484                             const struct pciserial_board *board,
1485                             struct uart_8250_port *port, int idx)
1486 {
1487         struct pci_dev *pdev = priv->dev;
1488         unsigned long base;
1489         unsigned long iobase;
1490         unsigned long ciobase = 0;
1491         u8 config_base;
1492
1493         /*
1494          * We are supposed to be able to read these from the PCI config space,
1495          * but the values there don't seem to match what we need to use, so
1496          * just use these hard-coded values for now, as they are correct.
1497          */
1498         switch (idx) {
1499         case 0: iobase = 0xe000; config_base = 0x40; break;
1500         case 1: iobase = 0xe008; config_base = 0x48; break;
1501         case 2: iobase = 0xe010; config_base = 0x50; break;
1502         case 3: iobase = 0xe018; config_base = 0x58; break;
1503         case 4: iobase = 0xe020; config_base = 0x60; break;
1504         case 5: iobase = 0xe028; config_base = 0x68; break;
1505         case 6: iobase = 0xe030; config_base = 0x70; break;
1506         case 7: iobase = 0xe038; config_base = 0x78; break;
1507         case 8: iobase = 0xe040; config_base = 0x80; break;
1508         case 9: iobase = 0xe048; config_base = 0x88; break;
1509         case 10: iobase = 0xe050; config_base = 0x90; break;
1510         case 11: iobase = 0xe058; config_base = 0x98; break;
1511         default:
1512                 /* Unknown number of ports, get out of here */
1513                 return -EINVAL;
1514         }
1515
1516         if (idx < 4) {
1517                 base = pci_resource_start(priv->dev, 3);
1518                 ciobase = (int)(base + (0x8 * idx));
1519         }
1520
1521         dev_dbg(&pdev->dev, "%s: idx=%d iobase=0x%lx ciobase=0x%lx config_base=0x%2x\n",
1522                 __func__, idx, iobase, ciobase, config_base);
1523
1524         /* Enable UART I/O port */
1525         pci_write_config_byte(pdev, config_base + 0x00, 0x01);
1526
1527         /* Select 128-byte FIFO and 8x FIFO threshold */
1528         pci_write_config_byte(pdev, config_base + 0x01, 0x33);
1529
1530         /* LSB UART */
1531         pci_write_config_byte(pdev, config_base + 0x04, (u8)(iobase & 0xff));
1532
1533         /* MSB UART */
1534         pci_write_config_byte(pdev, config_base + 0x05, (u8)((iobase & 0xff00) >> 8));
1535
1536         /* irq number, this usually fails, but the spec says to do it anyway. */
1537         pci_write_config_byte(pdev, config_base + 0x06, pdev->irq);
1538
1539         port->port.iotype = UPIO_PORT;
1540         port->port.iobase = iobase;
1541         port->port.mapbase = 0;
1542         port->port.membase = NULL;
1543         port->port.regshift = 0;
1544
1545         return 0;
1546 }
1547
1548 static int skip_tx_en_setup(struct serial_private *priv,
1549                         const struct pciserial_board *board,
1550                         struct uart_8250_port *port, int idx)
1551 {
1552         port->port.flags |= UPF_NO_TXEN_TEST;
1553         dev_dbg(&priv->dev->dev,
1554                 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n",
1555                 priv->dev->vendor, priv->dev->device,
1556                 priv->dev->subsystem_vendor, priv->dev->subsystem_device);
1557
1558         return pci_default_setup(priv, board, port, idx);
1559 }
1560
1561 static void kt_handle_break(struct uart_port *p)
1562 {
1563         struct uart_8250_port *up =
1564                 container_of(p, struct uart_8250_port, port);
1565         /*
1566          * On receipt of a BI, serial device in Intel ME (Intel
1567          * management engine) needs to have its fifos cleared for sane
1568          * SOL (Serial Over Lan) output.
1569          */
1570         serial8250_clear_and_reinit_fifos(up);
1571 }
1572
1573 static unsigned int kt_serial_in(struct uart_port *p, int offset)
1574 {
1575         struct uart_8250_port *up =
1576                 container_of(p, struct uart_8250_port, port);
1577         unsigned int val;
1578
1579         /*
1580          * When the Intel ME (management engine) gets reset its serial
1581          * port registers could return 0 momentarily.  Functions like
1582          * serial8250_console_write, read and save the IER, perform
1583          * some operation and then restore it.  In order to avoid
1584          * setting IER register inadvertently to 0, if the value read
1585          * is 0, double check with ier value in uart_8250_port and use
1586          * that instead.  up->ier should be the same value as what is
1587          * currently configured.
1588          */
1589         val = inb(p->iobase + offset);
1590         if (offset == UART_IER) {
1591                 if (val == 0)
1592                         val = up->ier;
1593         }
1594         return val;
1595 }
1596
1597 static int kt_serial_setup(struct serial_private *priv,
1598                            const struct pciserial_board *board,
1599                            struct uart_8250_port *port, int idx)
1600 {
1601         port->port.flags |= UPF_BUG_THRE;
1602         port->port.serial_in = kt_serial_in;
1603         port->port.handle_break = kt_handle_break;
1604         return skip_tx_en_setup(priv, board, port, idx);
1605 }
1606
1607 static int pci_eg20t_init(struct pci_dev *dev)
1608 {
1609 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1610         return -ENODEV;
1611 #else
1612         return 0;
1613 #endif
1614 }
1615
1616 static int
1617 pci_xr17c154_setup(struct serial_private *priv,
1618                   const struct pciserial_board *board,
1619                   struct uart_8250_port *port, int idx)
1620 {
1621         port->port.flags |= UPF_EXAR_EFR;
1622         return pci_default_setup(priv, board, port, idx);
1623 }
1624
1625 static int
1626 pci_xr17v35x_setup(struct serial_private *priv,
1627                   const struct pciserial_board *board,
1628                   struct uart_8250_port *port, int idx)
1629 {
1630         u8 __iomem *p;
1631
1632         p = pci_ioremap_bar(priv->dev, 0);
1633         if (p == NULL)
1634                 return -ENOMEM;
1635
1636         port->port.flags |= UPF_EXAR_EFR;
1637
1638         /*
1639          * Setup Multipurpose Input/Output pins.
1640          */
1641         if (idx == 0) {
1642                 writeb(0x00, p + 0x8f); /*MPIOINT[7:0]*/
1643                 writeb(0x00, p + 0x90); /*MPIOLVL[7:0]*/
1644                 writeb(0x00, p + 0x91); /*MPIO3T[7:0]*/
1645                 writeb(0x00, p + 0x92); /*MPIOINV[7:0]*/
1646                 writeb(0x00, p + 0x93); /*MPIOSEL[7:0]*/
1647                 writeb(0x00, p + 0x94); /*MPIOOD[7:0]*/
1648                 writeb(0x00, p + 0x95); /*MPIOINT[15:8]*/
1649                 writeb(0x00, p + 0x96); /*MPIOLVL[15:8]*/
1650                 writeb(0x00, p + 0x97); /*MPIO3T[15:8]*/
1651                 writeb(0x00, p + 0x98); /*MPIOINV[15:8]*/
1652                 writeb(0x00, p + 0x99); /*MPIOSEL[15:8]*/
1653                 writeb(0x00, p + 0x9a); /*MPIOOD[15:8]*/
1654         }
1655         writeb(0x00, p + UART_EXAR_8XMODE);
1656         writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1657         writeb(128, p + UART_EXAR_TXTRG);
1658         writeb(128, p + UART_EXAR_RXTRG);
1659         iounmap(p);
1660
1661         return pci_default_setup(priv, board, port, idx);
1662 }
1663
1664 #define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004
1665 #define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002
1666 #define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a
1667 #define PCI_DEVICE_ID_COMMTECH_2328PCI335 0x000b
1668
1669 static int
1670 pci_fastcom335_setup(struct serial_private *priv,
1671                   const struct pciserial_board *board,
1672                   struct uart_8250_port *port, int idx)
1673 {
1674         u8 __iomem *p;
1675
1676         p = pci_ioremap_bar(priv->dev, 0);
1677         if (p == NULL)
1678                 return -ENOMEM;
1679
1680         port->port.flags |= UPF_EXAR_EFR;
1681
1682         /*
1683          * Setup Multipurpose Input/Output pins.
1684          */
1685         if (idx == 0) {
1686                 switch (priv->dev->device) {
1687                 case PCI_DEVICE_ID_COMMTECH_4222PCI335:
1688                 case PCI_DEVICE_ID_COMMTECH_4224PCI335:
1689                         writeb(0x78, p + 0x90); /* MPIOLVL[7:0] */
1690                         writeb(0x00, p + 0x92); /* MPIOINV[7:0] */
1691                         writeb(0x00, p + 0x93); /* MPIOSEL[7:0] */
1692                         break;
1693                 case PCI_DEVICE_ID_COMMTECH_2324PCI335:
1694                 case PCI_DEVICE_ID_COMMTECH_2328PCI335:
1695                         writeb(0x00, p + 0x90); /* MPIOLVL[7:0] */
1696                         writeb(0xc0, p + 0x92); /* MPIOINV[7:0] */
1697                         writeb(0xc0, p + 0x93); /* MPIOSEL[7:0] */
1698                         break;
1699                 }
1700                 writeb(0x00, p + 0x8f); /* MPIOINT[7:0] */
1701                 writeb(0x00, p + 0x91); /* MPIO3T[7:0] */
1702                 writeb(0x00, p + 0x94); /* MPIOOD[7:0] */
1703         }
1704         writeb(0x00, p + UART_EXAR_8XMODE);
1705         writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1706         writeb(32, p + UART_EXAR_TXTRG);
1707         writeb(32, p + UART_EXAR_RXTRG);
1708         iounmap(p);
1709
1710         return pci_default_setup(priv, board, port, idx);
1711 }
1712
1713 static int
1714 pci_wch_ch353_setup(struct serial_private *priv,
1715                     const struct pciserial_board *board,
1716                     struct uart_8250_port *port, int idx)
1717 {
1718         port->port.flags |= UPF_FIXED_TYPE;
1719         port->port.type = PORT_16550A;
1720         return pci_default_setup(priv, board, port, idx);
1721 }
1722
1723 #define PCI_VENDOR_ID_SBSMODULARIO      0x124B
1724 #define PCI_SUBVENDOR_ID_SBSMODULARIO   0x124B
1725 #define PCI_DEVICE_ID_OCTPRO            0x0001
1726 #define PCI_SUBDEVICE_ID_OCTPRO232      0x0108
1727 #define PCI_SUBDEVICE_ID_OCTPRO422      0x0208
1728 #define PCI_SUBDEVICE_ID_POCTAL232      0x0308
1729 #define PCI_SUBDEVICE_ID_POCTAL422      0x0408
1730 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00   0x2500
1731 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30   0x2530
1732 #define PCI_VENDOR_ID_ADVANTECH         0x13fe
1733 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
1734 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
1735 #define PCI_DEVICE_ID_TITAN_200I        0x8028
1736 #define PCI_DEVICE_ID_TITAN_400I        0x8048
1737 #define PCI_DEVICE_ID_TITAN_800I        0x8088
1738 #define PCI_DEVICE_ID_TITAN_800EH       0xA007
1739 #define PCI_DEVICE_ID_TITAN_800EHB      0xA008
1740 #define PCI_DEVICE_ID_TITAN_400EH       0xA009
1741 #define PCI_DEVICE_ID_TITAN_100E        0xA010
1742 #define PCI_DEVICE_ID_TITAN_200E        0xA012
1743 #define PCI_DEVICE_ID_TITAN_400E        0xA013
1744 #define PCI_DEVICE_ID_TITAN_800E        0xA014
1745 #define PCI_DEVICE_ID_TITAN_200EI       0xA016
1746 #define PCI_DEVICE_ID_TITAN_200EISI     0xA017
1747 #define PCI_DEVICE_ID_TITAN_200V3       0xA306
1748 #define PCI_DEVICE_ID_TITAN_400V3       0xA310
1749 #define PCI_DEVICE_ID_TITAN_410V3       0xA312
1750 #define PCI_DEVICE_ID_TITAN_800V3       0xA314
1751 #define PCI_DEVICE_ID_TITAN_800V3B      0xA315
1752 #define PCI_DEVICE_ID_OXSEMI_16PCI958   0x9538
1753 #define PCIE_DEVICE_ID_NEO_2_OX_IBM     0x00F6
1754 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA  0xc001
1755 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
1756 #define PCI_VENDOR_ID_WCH               0x4348
1757 #define PCI_DEVICE_ID_WCH_CH352_2S      0x3253
1758 #define PCI_DEVICE_ID_WCH_CH353_4S      0x3453
1759 #define PCI_DEVICE_ID_WCH_CH353_2S1PF   0x5046
1760 #define PCI_DEVICE_ID_WCH_CH353_2S1P    0x7053
1761 #define PCI_VENDOR_ID_AGESTAR           0x5372
1762 #define PCI_DEVICE_ID_AGESTAR_9375      0x6872
1763 #define PCI_VENDOR_ID_ASIX              0x9710
1764 #define PCI_DEVICE_ID_COMMTECH_4224PCIE 0x0020
1765 #define PCI_DEVICE_ID_COMMTECH_4228PCIE 0x0021
1766 #define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022
1767 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
1768 #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e
1769
1770 #define PCI_VENDOR_ID_SUNIX             0x1fd4
1771 #define PCI_DEVICE_ID_SUNIX_1999        0x1999
1772
1773
1774 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1775 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
1776 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588
1777
1778 /*
1779  * Master list of serial port init/setup/exit quirks.
1780  * This does not describe the general nature of the port.
1781  * (ie, baud base, number and location of ports, etc)
1782  *
1783  * This list is ordered alphabetically by vendor then device.
1784  * Specific entries must come before more generic entries.
1785  */
1786 static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
1787         /*
1788         * ADDI-DATA GmbH communication cards <info@addi-data.com>
1789         */
1790         {
1791                 .vendor         = PCI_VENDOR_ID_AMCC,
1792                 .device         = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
1793                 .subvendor      = PCI_ANY_ID,
1794                 .subdevice      = PCI_ANY_ID,
1795                 .setup          = addidata_apci7800_setup,
1796         },
1797         /*
1798          * AFAVLAB cards - these may be called via parport_serial
1799          *  It is not clear whether this applies to all products.
1800          */
1801         {
1802                 .vendor         = PCI_VENDOR_ID_AFAVLAB,
1803                 .device         = PCI_ANY_ID,
1804                 .subvendor      = PCI_ANY_ID,
1805                 .subdevice      = PCI_ANY_ID,
1806                 .setup          = afavlab_setup,
1807         },
1808         /*
1809          * HP Diva
1810          */
1811         {
1812                 .vendor         = PCI_VENDOR_ID_HP,
1813                 .device         = PCI_DEVICE_ID_HP_DIVA,
1814                 .subvendor      = PCI_ANY_ID,
1815                 .subdevice      = PCI_ANY_ID,
1816                 .init           = pci_hp_diva_init,
1817                 .setup          = pci_hp_diva_setup,
1818         },
1819         /*
1820          * Intel
1821          */
1822         {
1823                 .vendor         = PCI_VENDOR_ID_INTEL,
1824                 .device         = PCI_DEVICE_ID_INTEL_80960_RP,
1825                 .subvendor      = 0xe4bf,
1826                 .subdevice      = PCI_ANY_ID,
1827                 .init           = pci_inteli960ni_init,
1828                 .setup          = pci_default_setup,
1829         },
1830         {
1831                 .vendor         = PCI_VENDOR_ID_INTEL,
1832                 .device         = PCI_DEVICE_ID_INTEL_8257X_SOL,
1833                 .subvendor      = PCI_ANY_ID,
1834                 .subdevice      = PCI_ANY_ID,
1835                 .setup          = skip_tx_en_setup,
1836         },
1837         {
1838                 .vendor         = PCI_VENDOR_ID_INTEL,
1839                 .device         = PCI_DEVICE_ID_INTEL_82573L_SOL,
1840                 .subvendor      = PCI_ANY_ID,
1841                 .subdevice      = PCI_ANY_ID,
1842                 .setup          = skip_tx_en_setup,
1843         },
1844         {
1845                 .vendor         = PCI_VENDOR_ID_INTEL,
1846                 .device         = PCI_DEVICE_ID_INTEL_82573E_SOL,
1847                 .subvendor      = PCI_ANY_ID,
1848                 .subdevice      = PCI_ANY_ID,
1849                 .setup          = skip_tx_en_setup,
1850         },
1851         {
1852                 .vendor         = PCI_VENDOR_ID_INTEL,
1853                 .device         = PCI_DEVICE_ID_INTEL_CE4100_UART,
1854                 .subvendor      = PCI_ANY_ID,
1855                 .subdevice      = PCI_ANY_ID,
1856                 .setup          = ce4100_serial_setup,
1857         },
1858         {
1859                 .vendor         = PCI_VENDOR_ID_INTEL,
1860                 .device         = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
1861                 .subvendor      = PCI_ANY_ID,
1862                 .subdevice      = PCI_ANY_ID,
1863                 .setup          = kt_serial_setup,
1864         },
1865         {
1866                 .vendor         = PCI_VENDOR_ID_INTEL,
1867                 .device         = PCI_DEVICE_ID_INTEL_BYT_UART1,
1868                 .subvendor      = PCI_ANY_ID,
1869                 .subdevice      = PCI_ANY_ID,
1870                 .setup          = byt_serial_setup,
1871         },
1872         {
1873                 .vendor         = PCI_VENDOR_ID_INTEL,
1874                 .device         = PCI_DEVICE_ID_INTEL_BYT_UART2,
1875                 .subvendor      = PCI_ANY_ID,
1876                 .subdevice      = PCI_ANY_ID,
1877                 .setup          = byt_serial_setup,
1878         },
1879         /*
1880          * ITE
1881          */
1882         {
1883                 .vendor         = PCI_VENDOR_ID_ITE,
1884                 .device         = PCI_DEVICE_ID_ITE_8872,
1885                 .subvendor      = PCI_ANY_ID,
1886                 .subdevice      = PCI_ANY_ID,
1887                 .init           = pci_ite887x_init,
1888                 .setup          = pci_default_setup,
1889                 .exit           = pci_ite887x_exit,
1890         },
1891         /*
1892          * National Instruments
1893          */
1894         {
1895                 .vendor         = PCI_VENDOR_ID_NI,
1896                 .device         = PCI_DEVICE_ID_NI_PCI23216,
1897                 .subvendor      = PCI_ANY_ID,
1898                 .subdevice      = PCI_ANY_ID,
1899                 .init           = pci_ni8420_init,
1900                 .setup          = pci_default_setup,
1901                 .exit           = pci_ni8420_exit,
1902         },
1903         {
1904                 .vendor         = PCI_VENDOR_ID_NI,
1905                 .device         = PCI_DEVICE_ID_NI_PCI2328,
1906                 .subvendor      = PCI_ANY_ID,
1907                 .subdevice      = PCI_ANY_ID,
1908                 .init           = pci_ni8420_init,
1909                 .setup          = pci_default_setup,
1910                 .exit           = pci_ni8420_exit,
1911         },
1912         {
1913                 .vendor         = PCI_VENDOR_ID_NI,
1914                 .device         = PCI_DEVICE_ID_NI_PCI2324,
1915                 .subvendor      = PCI_ANY_ID,
1916                 .subdevice      = PCI_ANY_ID,
1917                 .init           = pci_ni8420_init,
1918                 .setup          = pci_default_setup,
1919                 .exit           = pci_ni8420_exit,
1920         },
1921         {
1922                 .vendor         = PCI_VENDOR_ID_NI,
1923                 .device         = PCI_DEVICE_ID_NI_PCI2322,
1924                 .subvendor      = PCI_ANY_ID,
1925                 .subdevice      = PCI_ANY_ID,
1926                 .init           = pci_ni8420_init,
1927                 .setup          = pci_default_setup,
1928                 .exit           = pci_ni8420_exit,
1929         },
1930         {
1931                 .vendor         = PCI_VENDOR_ID_NI,
1932                 .device         = PCI_DEVICE_ID_NI_PCI2324I,
1933                 .subvendor      = PCI_ANY_ID,
1934                 .subdevice      = PCI_ANY_ID,
1935                 .init           = pci_ni8420_init,
1936                 .setup          = pci_default_setup,
1937                 .exit           = pci_ni8420_exit,
1938         },
1939         {
1940                 .vendor         = PCI_VENDOR_ID_NI,
1941                 .device         = PCI_DEVICE_ID_NI_PCI2322I,
1942                 .subvendor      = PCI_ANY_ID,
1943                 .subdevice      = PCI_ANY_ID,
1944                 .init           = pci_ni8420_init,
1945                 .setup          = pci_default_setup,
1946                 .exit           = pci_ni8420_exit,
1947         },
1948         {
1949                 .vendor         = PCI_VENDOR_ID_NI,
1950                 .device         = PCI_DEVICE_ID_NI_PXI8420_23216,
1951                 .subvendor      = PCI_ANY_ID,
1952                 .subdevice      = PCI_ANY_ID,
1953                 .init           = pci_ni8420_init,
1954                 .setup          = pci_default_setup,
1955                 .exit           = pci_ni8420_exit,
1956         },
1957         {
1958                 .vendor         = PCI_VENDOR_ID_NI,
1959                 .device         = PCI_DEVICE_ID_NI_PXI8420_2328,
1960                 .subvendor      = PCI_ANY_ID,
1961                 .subdevice      = PCI_ANY_ID,
1962                 .init           = pci_ni8420_init,
1963                 .setup          = pci_default_setup,
1964                 .exit           = pci_ni8420_exit,
1965         },
1966         {
1967                 .vendor         = PCI_VENDOR_ID_NI,
1968                 .device         = PCI_DEVICE_ID_NI_PXI8420_2324,
1969                 .subvendor      = PCI_ANY_ID,
1970                 .subdevice      = PCI_ANY_ID,
1971                 .init           = pci_ni8420_init,
1972                 .setup          = pci_default_setup,
1973                 .exit           = pci_ni8420_exit,
1974         },
1975         {
1976                 .vendor         = PCI_VENDOR_ID_NI,
1977                 .device         = PCI_DEVICE_ID_NI_PXI8420_2322,
1978                 .subvendor      = PCI_ANY_ID,
1979                 .subdevice      = PCI_ANY_ID,
1980                 .init           = pci_ni8420_init,
1981                 .setup          = pci_default_setup,
1982                 .exit           = pci_ni8420_exit,
1983         },
1984         {
1985                 .vendor         = PCI_VENDOR_ID_NI,
1986                 .device         = PCI_DEVICE_ID_NI_PXI8422_2324,
1987                 .subvendor      = PCI_ANY_ID,
1988                 .subdevice      = PCI_ANY_ID,
1989                 .init           = pci_ni8420_init,
1990                 .setup          = pci_default_setup,
1991                 .exit           = pci_ni8420_exit,
1992         },
1993         {
1994                 .vendor         = PCI_VENDOR_ID_NI,
1995                 .device         = PCI_DEVICE_ID_NI_PXI8422_2322,
1996                 .subvendor      = PCI_ANY_ID,
1997                 .subdevice      = PCI_ANY_ID,
1998                 .init           = pci_ni8420_init,
1999                 .setup          = pci_default_setup,
2000                 .exit           = pci_ni8420_exit,
2001         },
2002         {
2003                 .vendor         = PCI_VENDOR_ID_NI,
2004                 .device         = PCI_ANY_ID,
2005                 .subvendor      = PCI_ANY_ID,
2006                 .subdevice      = PCI_ANY_ID,
2007                 .init           = pci_ni8430_init,
2008                 .setup          = pci_ni8430_setup,
2009                 .exit           = pci_ni8430_exit,
2010         },
2011         /* Quatech */
2012         {
2013                 .vendor         = PCI_VENDOR_ID_QUATECH,
2014                 .device         = PCI_ANY_ID,
2015                 .subvendor      = PCI_ANY_ID,
2016                 .subdevice      = PCI_ANY_ID,
2017                 .init           = pci_quatech_init,
2018                 .setup          = pci_quatech_setup,
2019                 .exit           = pci_quatech_exit,
2020         },
2021         /*
2022          * Panacom
2023          */
2024         {
2025                 .vendor         = PCI_VENDOR_ID_PANACOM,
2026                 .device         = PCI_DEVICE_ID_PANACOM_QUADMODEM,
2027                 .subvendor      = PCI_ANY_ID,
2028                 .subdevice      = PCI_ANY_ID,
2029                 .init           = pci_plx9050_init,
2030                 .setup          = pci_default_setup,
2031                 .exit           = pci_plx9050_exit,
2032         },
2033         {
2034                 .vendor         = PCI_VENDOR_ID_PANACOM,
2035                 .device         = PCI_DEVICE_ID_PANACOM_DUALMODEM,
2036                 .subvendor      = PCI_ANY_ID,
2037                 .subdevice      = PCI_ANY_ID,
2038                 .init           = pci_plx9050_init,
2039                 .setup          = pci_default_setup,
2040                 .exit           = pci_plx9050_exit,
2041         },
2042         /*
2043          * Pericom
2044          */
2045         {
2046                 .vendor         = 0x12d8,
2047                 .device         = 0x7952,
2048                 .subvendor      = PCI_ANY_ID,
2049                 .subdevice      = PCI_ANY_ID,
2050                 .setup          = pci_pericom_setup,
2051         },
2052         {
2053                 .vendor         = 0x12d8,
2054                 .device         = 0x7954,
2055                 .subvendor      = PCI_ANY_ID,
2056                 .subdevice      = PCI_ANY_ID,
2057                 .setup          = pci_pericom_setup,
2058         },
2059         {
2060                 .vendor         = 0x12d8,
2061                 .device         = 0x7958,
2062                 .subvendor      = PCI_ANY_ID,
2063                 .subdevice      = PCI_ANY_ID,
2064                 .setup          = pci_pericom_setup,
2065         },
2066
2067         /*
2068          * PLX
2069          */
2070         {
2071                 .vendor         = PCI_VENDOR_ID_PLX,
2072                 .device         = PCI_DEVICE_ID_PLX_9030,
2073                 .subvendor      = PCI_SUBVENDOR_ID_PERLE,
2074                 .subdevice      = PCI_ANY_ID,
2075                 .setup          = pci_default_setup,
2076         },
2077         {
2078                 .vendor         = PCI_VENDOR_ID_PLX,
2079                 .device         = PCI_DEVICE_ID_PLX_9050,
2080                 .subvendor      = PCI_SUBVENDOR_ID_EXSYS,
2081                 .subdevice      = PCI_SUBDEVICE_ID_EXSYS_4055,
2082                 .init           = pci_plx9050_init,
2083                 .setup          = pci_default_setup,
2084                 .exit           = pci_plx9050_exit,
2085         },
2086         {
2087                 .vendor         = PCI_VENDOR_ID_PLX,
2088                 .device         = PCI_DEVICE_ID_PLX_9050,
2089                 .subvendor      = PCI_SUBVENDOR_ID_KEYSPAN,
2090                 .subdevice      = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
2091                 .init           = pci_plx9050_init,
2092                 .setup          = pci_default_setup,
2093                 .exit           = pci_plx9050_exit,
2094         },
2095         {
2096                 .vendor         = PCI_VENDOR_ID_PLX,
2097                 .device         = PCI_DEVICE_ID_PLX_ROMULUS,
2098                 .subvendor      = PCI_VENDOR_ID_PLX,
2099                 .subdevice      = PCI_DEVICE_ID_PLX_ROMULUS,
2100                 .init           = pci_plx9050_init,
2101                 .setup          = pci_default_setup,
2102                 .exit           = pci_plx9050_exit,
2103         },
2104         /*
2105          * SBS Technologies, Inc., PMC-OCTALPRO 232
2106          */
2107         {
2108                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
2109                 .device         = PCI_DEVICE_ID_OCTPRO,
2110                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
2111                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO232,
2112                 .init           = sbs_init,
2113                 .setup          = sbs_setup,
2114                 .exit           = sbs_exit,
2115         },
2116         /*
2117          * SBS Technologies, Inc., PMC-OCTALPRO 422
2118          */
2119         {
2120                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
2121                 .device         = PCI_DEVICE_ID_OCTPRO,
2122                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
2123                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO422,
2124                 .init           = sbs_init,
2125                 .setup          = sbs_setup,
2126                 .exit           = sbs_exit,
2127         },
2128         /*
2129          * SBS Technologies, Inc., P-Octal 232
2130          */
2131         {
2132                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
2133                 .device         = PCI_DEVICE_ID_OCTPRO,
2134                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
2135                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL232,
2136                 .init           = sbs_init,
2137                 .setup          = sbs_setup,
2138                 .exit           = sbs_exit,
2139         },
2140         /*
2141          * SBS Technologies, Inc., P-Octal 422
2142          */
2143         {
2144                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
2145                 .device         = PCI_DEVICE_ID_OCTPRO,
2146                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
2147                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL422,
2148                 .init           = sbs_init,
2149                 .setup          = sbs_setup,
2150                 .exit           = sbs_exit,
2151         },
2152         /*
2153          * SIIG cards - these may be called via parport_serial
2154          */
2155         {
2156                 .vendor         = PCI_VENDOR_ID_SIIG,
2157                 .device         = PCI_ANY_ID,
2158                 .subvendor      = PCI_ANY_ID,
2159                 .subdevice      = PCI_ANY_ID,
2160                 .init           = pci_siig_init,
2161                 .setup          = pci_siig_setup,
2162         },
2163         /*
2164          * Titan cards
2165          */
2166         {
2167                 .vendor         = PCI_VENDOR_ID_TITAN,
2168                 .device         = PCI_DEVICE_ID_TITAN_400L,
2169                 .subvendor      = PCI_ANY_ID,
2170                 .subdevice      = PCI_ANY_ID,
2171                 .setup          = titan_400l_800l_setup,
2172         },
2173         {
2174                 .vendor         = PCI_VENDOR_ID_TITAN,
2175                 .device         = PCI_DEVICE_ID_TITAN_800L,
2176                 .subvendor      = PCI_ANY_ID,
2177                 .subdevice      = PCI_ANY_ID,
2178                 .setup          = titan_400l_800l_setup,
2179         },
2180         /*
2181          * Timedia cards
2182          */
2183         {
2184                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
2185                 .device         = PCI_DEVICE_ID_TIMEDIA_1889,
2186                 .subvendor      = PCI_VENDOR_ID_TIMEDIA,
2187                 .subdevice      = PCI_ANY_ID,
2188                 .probe          = pci_timedia_probe,
2189                 .init           = pci_timedia_init,
2190                 .setup          = pci_timedia_setup,
2191         },
2192         {
2193                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
2194                 .device         = PCI_ANY_ID,
2195                 .subvendor      = PCI_ANY_ID,
2196                 .subdevice      = PCI_ANY_ID,
2197                 .setup          = pci_timedia_setup,
2198         },
2199         /*
2200          * SUNIX (Timedia) cards
2201          * Do not "probe" for these cards as there is at least one combination
2202          * card that should be handled by parport_pc that doesn't match the
2203          * rule in pci_timedia_probe.
2204          * It is part number is MIO5079A but its subdevice ID is 0x0102.
2205          * There are some boards with part number SER5037AL that report
2206          * subdevice ID 0x0002.
2207          */
2208         {
2209                 .vendor         = PCI_VENDOR_ID_SUNIX,
2210                 .device         = PCI_DEVICE_ID_SUNIX_1999,
2211                 .subvendor      = PCI_VENDOR_ID_SUNIX,
2212                 .subdevice      = PCI_ANY_ID,
2213                 .init           = pci_timedia_init,
2214                 .setup          = pci_timedia_setup,
2215         },
2216         /*
2217          * Exar cards
2218          */
2219         {
2220                 .vendor = PCI_VENDOR_ID_EXAR,
2221                 .device = PCI_DEVICE_ID_EXAR_XR17C152,
2222                 .subvendor      = PCI_ANY_ID,
2223                 .subdevice      = PCI_ANY_ID,
2224                 .setup          = pci_xr17c154_setup,
2225         },
2226         {
2227                 .vendor = PCI_VENDOR_ID_EXAR,
2228                 .device = PCI_DEVICE_ID_EXAR_XR17C154,
2229                 .subvendor      = PCI_ANY_ID,
2230                 .subdevice      = PCI_ANY_ID,
2231                 .setup          = pci_xr17c154_setup,
2232         },
2233         {
2234                 .vendor = PCI_VENDOR_ID_EXAR,
2235                 .device = PCI_DEVICE_ID_EXAR_XR17C158,
2236                 .subvendor      = PCI_ANY_ID,
2237                 .subdevice      = PCI_ANY_ID,
2238                 .setup          = pci_xr17c154_setup,
2239         },
2240         {
2241                 .vendor = PCI_VENDOR_ID_EXAR,
2242                 .device = PCI_DEVICE_ID_EXAR_XR17V352,
2243                 .subvendor      = PCI_ANY_ID,
2244                 .subdevice      = PCI_ANY_ID,
2245                 .setup          = pci_xr17v35x_setup,
2246         },
2247         {
2248                 .vendor = PCI_VENDOR_ID_EXAR,
2249                 .device = PCI_DEVICE_ID_EXAR_XR17V354,
2250                 .subvendor      = PCI_ANY_ID,
2251                 .subdevice      = PCI_ANY_ID,
2252                 .setup          = pci_xr17v35x_setup,
2253         },
2254         {
2255                 .vendor = PCI_VENDOR_ID_EXAR,
2256                 .device = PCI_DEVICE_ID_EXAR_XR17V358,
2257                 .subvendor      = PCI_ANY_ID,
2258                 .subdevice      = PCI_ANY_ID,
2259                 .setup          = pci_xr17v35x_setup,
2260         },
2261         /*
2262          * Xircom cards
2263          */
2264         {
2265                 .vendor         = PCI_VENDOR_ID_XIRCOM,
2266                 .device         = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2267                 .subvendor      = PCI_ANY_ID,
2268                 .subdevice      = PCI_ANY_ID,
2269                 .init           = pci_xircom_init,
2270                 .setup          = pci_default_setup,
2271         },
2272         /*
2273          * Netmos cards - these may be called via parport_serial
2274          */
2275         {
2276                 .vendor         = PCI_VENDOR_ID_NETMOS,
2277                 .device         = PCI_ANY_ID,
2278                 .subvendor      = PCI_ANY_ID,
2279                 .subdevice      = PCI_ANY_ID,
2280                 .init           = pci_netmos_init,
2281                 .setup          = pci_netmos_9900_setup,
2282         },
2283         /*
2284          * For Oxford Semiconductor Tornado based devices
2285          */
2286         {
2287                 .vendor         = PCI_VENDOR_ID_OXSEMI,
2288                 .device         = PCI_ANY_ID,
2289                 .subvendor      = PCI_ANY_ID,
2290                 .subdevice      = PCI_ANY_ID,
2291                 .init           = pci_oxsemi_tornado_init,
2292                 .setup          = pci_default_setup,
2293         },
2294         {
2295                 .vendor         = PCI_VENDOR_ID_MAINPINE,
2296                 .device         = PCI_ANY_ID,
2297                 .subvendor      = PCI_ANY_ID,
2298                 .subdevice      = PCI_ANY_ID,
2299                 .init           = pci_oxsemi_tornado_init,
2300                 .setup          = pci_default_setup,
2301         },
2302         {
2303                 .vendor         = PCI_VENDOR_ID_DIGI,
2304                 .device         = PCIE_DEVICE_ID_NEO_2_OX_IBM,
2305                 .subvendor              = PCI_SUBVENDOR_ID_IBM,
2306                 .subdevice              = PCI_ANY_ID,
2307                 .init                   = pci_oxsemi_tornado_init,
2308                 .setup          = pci_default_setup,
2309         },
2310         {
2311                 .vendor         = PCI_VENDOR_ID_INTEL,
2312                 .device         = 0x8811,
2313                 .subvendor      = PCI_ANY_ID,
2314                 .subdevice      = PCI_ANY_ID,
2315                 .init           = pci_eg20t_init,
2316                 .setup          = pci_default_setup,
2317         },
2318         {
2319                 .vendor         = PCI_VENDOR_ID_INTEL,
2320                 .device         = 0x8812,
2321                 .subvendor      = PCI_ANY_ID,
2322                 .subdevice      = PCI_ANY_ID,
2323                 .init           = pci_eg20t_init,
2324                 .setup          = pci_default_setup,
2325         },
2326         {
2327                 .vendor         = PCI_VENDOR_ID_INTEL,
2328                 .device         = 0x8813,
2329                 .subvendor      = PCI_ANY_ID,
2330                 .subdevice      = PCI_ANY_ID,
2331                 .init           = pci_eg20t_init,
2332                 .setup          = pci_default_setup,
2333         },
2334         {
2335                 .vendor         = PCI_VENDOR_ID_INTEL,
2336                 .device         = 0x8814,
2337                 .subvendor      = PCI_ANY_ID,
2338                 .subdevice      = PCI_ANY_ID,
2339                 .init           = pci_eg20t_init,
2340                 .setup          = pci_default_setup,
2341         },
2342         {
2343                 .vendor         = 0x10DB,
2344                 .device         = 0x8027,
2345                 .subvendor      = PCI_ANY_ID,
2346                 .subdevice      = PCI_ANY_ID,
2347                 .init           = pci_eg20t_init,
2348                 .setup          = pci_default_setup,
2349         },
2350         {
2351                 .vendor         = 0x10DB,
2352                 .device         = 0x8028,
2353                 .subvendor      = PCI_ANY_ID,
2354                 .subdevice      = PCI_ANY_ID,
2355                 .init           = pci_eg20t_init,
2356                 .setup          = pci_default_setup,
2357         },
2358         {
2359                 .vendor         = 0x10DB,
2360                 .device         = 0x8029,
2361                 .subvendor      = PCI_ANY_ID,
2362                 .subdevice      = PCI_ANY_ID,
2363                 .init           = pci_eg20t_init,
2364                 .setup          = pci_default_setup,
2365         },
2366         {
2367                 .vendor         = 0x10DB,
2368                 .device         = 0x800C,
2369                 .subvendor      = PCI_ANY_ID,
2370                 .subdevice      = PCI_ANY_ID,
2371                 .init           = pci_eg20t_init,
2372                 .setup          = pci_default_setup,
2373         },
2374         {
2375                 .vendor         = 0x10DB,
2376                 .device         = 0x800D,
2377                 .subvendor      = PCI_ANY_ID,
2378                 .subdevice      = PCI_ANY_ID,
2379                 .init           = pci_eg20t_init,
2380                 .setup          = pci_default_setup,
2381         },
2382         /*
2383          * Cronyx Omega PCI (PLX-chip based)
2384          */
2385         {
2386                 .vendor         = PCI_VENDOR_ID_PLX,
2387                 .device         = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
2388                 .subvendor      = PCI_ANY_ID,
2389                 .subdevice      = PCI_ANY_ID,
2390                 .setup          = pci_omegapci_setup,
2391         },
2392         /* WCH CH353 2S1P card (16550 clone) */
2393         {
2394                 .vendor         = PCI_VENDOR_ID_WCH,
2395                 .device         = PCI_DEVICE_ID_WCH_CH353_2S1P,
2396                 .subvendor      = PCI_ANY_ID,
2397                 .subdevice      = PCI_ANY_ID,
2398                 .setup          = pci_wch_ch353_setup,
2399         },
2400         /* WCH CH353 4S card (16550 clone) */
2401         {
2402                 .vendor         = PCI_VENDOR_ID_WCH,
2403                 .device         = PCI_DEVICE_ID_WCH_CH353_4S,
2404                 .subvendor      = PCI_ANY_ID,
2405                 .subdevice      = PCI_ANY_ID,
2406                 .setup          = pci_wch_ch353_setup,
2407         },
2408         /* WCH CH353 2S1PF card (16550 clone) */
2409         {
2410                 .vendor         = PCI_VENDOR_ID_WCH,
2411                 .device         = PCI_DEVICE_ID_WCH_CH353_2S1PF,
2412                 .subvendor      = PCI_ANY_ID,
2413                 .subdevice      = PCI_ANY_ID,
2414                 .setup          = pci_wch_ch353_setup,
2415         },
2416         /* WCH CH352 2S card (16550 clone) */
2417         {
2418                 .vendor         = PCI_VENDOR_ID_WCH,
2419                 .device         = PCI_DEVICE_ID_WCH_CH352_2S,
2420                 .subvendor      = PCI_ANY_ID,
2421                 .subdevice      = PCI_ANY_ID,
2422                 .setup          = pci_wch_ch353_setup,
2423         },
2424         /*
2425          * ASIX devices with FIFO bug
2426          */
2427         {
2428                 .vendor         = PCI_VENDOR_ID_ASIX,
2429                 .device         = PCI_ANY_ID,
2430                 .subvendor      = PCI_ANY_ID,
2431                 .subdevice      = PCI_ANY_ID,
2432                 .setup          = pci_asix_setup,
2433         },
2434         /*
2435          * Commtech, Inc. Fastcom adapters
2436          *
2437          */
2438         {
2439                 .vendor = PCI_VENDOR_ID_COMMTECH,
2440                 .device = PCI_DEVICE_ID_COMMTECH_4222PCI335,
2441                 .subvendor      = PCI_ANY_ID,
2442                 .subdevice      = PCI_ANY_ID,
2443                 .setup          = pci_fastcom335_setup,
2444         },
2445         {
2446                 .vendor = PCI_VENDOR_ID_COMMTECH,
2447                 .device = PCI_DEVICE_ID_COMMTECH_4224PCI335,
2448                 .subvendor      = PCI_ANY_ID,
2449                 .subdevice      = PCI_ANY_ID,
2450                 .setup          = pci_fastcom335_setup,
2451         },
2452         {
2453                 .vendor = PCI_VENDOR_ID_COMMTECH,
2454                 .device = PCI_DEVICE_ID_COMMTECH_2324PCI335,
2455                 .subvendor      = PCI_ANY_ID,
2456                 .subdevice      = PCI_ANY_ID,
2457                 .setup          = pci_fastcom335_setup,
2458         },
2459         {
2460                 .vendor = PCI_VENDOR_ID_COMMTECH,
2461                 .device = PCI_DEVICE_ID_COMMTECH_2328PCI335,
2462                 .subvendor      = PCI_ANY_ID,
2463                 .subdevice      = PCI_ANY_ID,
2464                 .setup          = pci_fastcom335_setup,
2465         },
2466         {
2467                 .vendor = PCI_VENDOR_ID_COMMTECH,
2468                 .device = PCI_DEVICE_ID_COMMTECH_4222PCIE,
2469                 .subvendor      = PCI_ANY_ID,
2470                 .subdevice      = PCI_ANY_ID,
2471                 .setup          = pci_xr17v35x_setup,
2472         },
2473         {
2474                 .vendor = PCI_VENDOR_ID_COMMTECH,
2475                 .device = PCI_DEVICE_ID_COMMTECH_4224PCIE,
2476                 .subvendor      = PCI_ANY_ID,
2477                 .subdevice      = PCI_ANY_ID,
2478                 .setup          = pci_xr17v35x_setup,
2479         },
2480         {
2481                 .vendor = PCI_VENDOR_ID_COMMTECH,
2482                 .device = PCI_DEVICE_ID_COMMTECH_4228PCIE,
2483                 .subvendor      = PCI_ANY_ID,
2484                 .subdevice      = PCI_ANY_ID,
2485                 .setup          = pci_xr17v35x_setup,
2486         },
2487         /*
2488          * Broadcom TruManage (NetXtreme)
2489          */
2490         {
2491                 .vendor         = PCI_VENDOR_ID_BROADCOM,
2492                 .device         = PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
2493                 .subvendor      = PCI_ANY_ID,
2494                 .subdevice      = PCI_ANY_ID,
2495                 .setup          = pci_brcm_trumanage_setup,
2496         },
2497         {
2498                 .vendor         = 0x1c29,
2499                 .device         = 0x1104,
2500                 .subvendor      = PCI_ANY_ID,
2501                 .subdevice      = PCI_ANY_ID,
2502                 .setup          = pci_fintek_setup,
2503         },
2504         {
2505                 .vendor         = 0x1c29,
2506                 .device         = 0x1108,
2507                 .subvendor      = PCI_ANY_ID,
2508                 .subdevice      = PCI_ANY_ID,
2509                 .setup          = pci_fintek_setup,
2510         },
2511         {
2512                 .vendor         = 0x1c29,
2513                 .device         = 0x1112,
2514                 .subvendor      = PCI_ANY_ID,
2515                 .subdevice      = PCI_ANY_ID,
2516                 .setup          = pci_fintek_setup,
2517         },
2518
2519         /*
2520          * Default "match everything" terminator entry
2521          */
2522         {
2523                 .vendor         = PCI_ANY_ID,
2524                 .device         = PCI_ANY_ID,
2525                 .subvendor      = PCI_ANY_ID,
2526                 .subdevice      = PCI_ANY_ID,
2527                 .setup          = pci_default_setup,
2528         }
2529 };
2530
2531 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
2532 {
2533         return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
2534 }
2535
2536 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
2537 {
2538         struct pci_serial_quirk *quirk;
2539
2540         for (quirk = pci_serial_quirks; ; quirk++)
2541                 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
2542                     quirk_id_matches(quirk->device, dev->device) &&
2543                     quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
2544                     quirk_id_matches(quirk->subdevice, dev->subsystem_device))
2545                         break;
2546         return quirk;
2547 }
2548
2549 static inline int get_pci_irq(struct pci_dev *dev,
2550                                 const struct pciserial_board *board)
2551 {
2552         if (board->flags & FL_NOIRQ)
2553                 return 0;
2554         else
2555                 return dev->irq;
2556 }
2557
2558 /*
2559  * This is the configuration table for all of the PCI serial boards
2560  * which we support.  It is directly indexed by the pci_board_num_t enum
2561  * value, which is encoded in the pci_device_id PCI probe table's
2562  * driver_data member.
2563  *
2564  * The makeup of these names are:
2565  *  pbn_bn{_bt}_n_baud{_offsetinhex}
2566  *
2567  *  bn          = PCI BAR number
2568  *  bt          = Index using PCI BARs
2569  *  n           = number of serial ports
2570  *  baud        = baud rate
2571  *  offsetinhex = offset for each sequential port (in hex)
2572  *
2573  * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
2574  *
2575  * Please note: in theory if n = 1, _bt infix should make no difference.
2576  * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
2577  */
2578 enum pci_board_num_t {
2579         pbn_default = 0,
2580
2581         pbn_b0_1_115200,
2582         pbn_b0_2_115200,
2583         pbn_b0_4_115200,
2584         pbn_b0_5_115200,
2585         pbn_b0_8_115200,
2586
2587         pbn_b0_1_921600,
2588         pbn_b0_2_921600,
2589         pbn_b0_4_921600,
2590
2591         pbn_b0_2_1130000,
2592
2593         pbn_b0_4_1152000,
2594
2595         pbn_b0_2_1152000_200,
2596         pbn_b0_4_1152000_200,
2597         pbn_b0_8_1152000_200,
2598
2599         pbn_b0_2_1843200,
2600         pbn_b0_4_1843200,
2601
2602         pbn_b0_2_1843200_200,
2603         pbn_b0_4_1843200_200,
2604         pbn_b0_8_1843200_200,
2605
2606         pbn_b0_1_4000000,
2607
2608         pbn_b0_bt_1_115200,
2609         pbn_b0_bt_2_115200,
2610         pbn_b0_bt_4_115200,
2611         pbn_b0_bt_8_115200,
2612
2613         pbn_b0_bt_1_460800,
2614         pbn_b0_bt_2_460800,
2615         pbn_b0_bt_4_460800,
2616
2617         pbn_b0_bt_1_921600,
2618         pbn_b0_bt_2_921600,
2619         pbn_b0_bt_4_921600,
2620         pbn_b0_bt_8_921600,
2621
2622         pbn_b1_1_115200,
2623         pbn_b1_2_115200,
2624         pbn_b1_4_115200,
2625         pbn_b1_8_115200,
2626         pbn_b1_16_115200,
2627
2628         pbn_b1_1_921600,
2629         pbn_b1_2_921600,
2630         pbn_b1_4_921600,
2631         pbn_b1_8_921600,
2632
2633         pbn_b1_2_1250000,
2634
2635         pbn_b1_bt_1_115200,
2636         pbn_b1_bt_2_115200,
2637         pbn_b1_bt_4_115200,
2638
2639         pbn_b1_bt_2_921600,
2640
2641         pbn_b1_1_1382400,
2642         pbn_b1_2_1382400,
2643         pbn_b1_4_1382400,
2644         pbn_b1_8_1382400,
2645
2646         pbn_b2_1_115200,
2647         pbn_b2_2_115200,
2648         pbn_b2_4_115200,
2649         pbn_b2_8_115200,
2650
2651         pbn_b2_1_460800,
2652         pbn_b2_4_460800,
2653         pbn_b2_8_460800,
2654         pbn_b2_16_460800,
2655
2656         pbn_b2_1_921600,
2657         pbn_b2_4_921600,
2658         pbn_b2_8_921600,
2659
2660         pbn_b2_8_1152000,
2661
2662         pbn_b2_bt_1_115200,
2663         pbn_b2_bt_2_115200,
2664         pbn_b2_bt_4_115200,
2665
2666         pbn_b2_bt_2_921600,
2667         pbn_b2_bt_4_921600,
2668
2669         pbn_b3_2_115200,
2670         pbn_b3_4_115200,
2671         pbn_b3_8_115200,
2672
2673         pbn_b4_bt_2_921600,
2674         pbn_b4_bt_4_921600,
2675         pbn_b4_bt_8_921600,
2676
2677         /*
2678          * Board-specific versions.
2679          */
2680         pbn_panacom,
2681         pbn_panacom2,
2682         pbn_panacom4,
2683         pbn_plx_romulus,
2684         pbn_oxsemi,
2685         pbn_oxsemi_1_4000000,
2686         pbn_oxsemi_2_4000000,
2687         pbn_oxsemi_4_4000000,
2688         pbn_oxsemi_8_4000000,
2689         pbn_intel_i960,
2690         pbn_sgi_ioc3,
2691         pbn_computone_4,
2692         pbn_computone_6,
2693         pbn_computone_8,
2694         pbn_sbsxrsio,
2695         pbn_exar_XR17C152,
2696         pbn_exar_XR17C154,
2697         pbn_exar_XR17C158,
2698         pbn_exar_XR17V352,
2699         pbn_exar_XR17V354,
2700         pbn_exar_XR17V358,
2701         pbn_exar_ibm_saturn,
2702         pbn_pasemi_1682M,
2703         pbn_ni8430_2,
2704         pbn_ni8430_4,
2705         pbn_ni8430_8,
2706         pbn_ni8430_16,
2707         pbn_ADDIDATA_PCIe_1_3906250,
2708         pbn_ADDIDATA_PCIe_2_3906250,
2709         pbn_ADDIDATA_PCIe_4_3906250,
2710         pbn_ADDIDATA_PCIe_8_3906250,
2711         pbn_ce4100_1_115200,
2712         pbn_byt,
2713         pbn_omegapci,
2714         pbn_NETMOS9900_2s_115200,
2715         pbn_brcm_trumanage,
2716         pbn_fintek_4,
2717         pbn_fintek_8,
2718         pbn_fintek_12,
2719 };
2720
2721 /*
2722  * uart_offset - the space between channels
2723  * reg_shift   - describes how the UART registers are mapped
2724  *               to PCI memory by the card.
2725  * For example IER register on SBS, Inc. PMC-OctPro is located at
2726  * offset 0x10 from the UART base, while UART_IER is defined as 1
2727  * in include/linux/serial_reg.h,
2728  * see first lines of serial_in() and serial_out() in 8250.c
2729 */
2730
2731 static struct pciserial_board pci_boards[] = {
2732         [pbn_default] = {
2733                 .flags          = FL_BASE0,
2734                 .num_ports      = 1,
2735                 .base_baud      = 115200,
2736                 .uart_offset    = 8,
2737         },
2738         [pbn_b0_1_115200] = {
2739                 .flags          = FL_BASE0,
2740                 .num_ports      = 1,
2741                 .base_baud      = 115200,
2742                 .uart_offset    = 8,
2743         },
2744         [pbn_b0_2_115200] = {
2745                 .flags          = FL_BASE0,
2746                 .num_ports      = 2,
2747                 .base_baud      = 115200,
2748                 .uart_offset    = 8,
2749         },
2750         [pbn_b0_4_115200] = {
2751                 .flags          = FL_BASE0,
2752                 .num_ports      = 4,
2753                 .base_baud      = 115200,
2754                 .uart_offset    = 8,
2755         },
2756         [pbn_b0_5_115200] = {
2757                 .flags          = FL_BASE0,
2758                 .num_ports      = 5,
2759                 .base_baud      = 115200,
2760                 .uart_offset    = 8,
2761         },
2762         [pbn_b0_8_115200] = {
2763                 .flags          = FL_BASE0,
2764                 .num_ports      = 8,
2765                 .base_baud      = 115200,
2766                 .uart_offset    = 8,
2767         },
2768         [pbn_b0_1_921600] = {
2769                 .flags          = FL_BASE0,
2770                 .num_ports      = 1,
2771                 .base_baud      = 921600,
2772                 .uart_offset    = 8,
2773         },
2774         [pbn_b0_2_921600] = {
2775                 .flags          = FL_BASE0,
2776                 .num_ports      = 2,
2777                 .base_baud      = 921600,
2778                 .uart_offset    = 8,
2779         },
2780         [pbn_b0_4_921600] = {
2781                 .flags          = FL_BASE0,
2782                 .num_ports      = 4,
2783                 .base_baud      = 921600,
2784                 .uart_offset    = 8,
2785         },
2786
2787         [pbn_b0_2_1130000] = {
2788                 .flags          = FL_BASE0,
2789                 .num_ports      = 2,
2790                 .base_baud      = 1130000,
2791                 .uart_offset    = 8,
2792         },
2793
2794         [pbn_b0_4_1152000] = {
2795                 .flags          = FL_BASE0,
2796                 .num_ports      = 4,
2797                 .base_baud      = 1152000,
2798                 .uart_offset    = 8,
2799         },
2800
2801         [pbn_b0_2_1152000_200] = {
2802                 .flags          = FL_BASE0,
2803                 .num_ports      = 2,
2804                 .base_baud      = 1152000,
2805                 .uart_offset    = 0x200,
2806         },
2807
2808         [pbn_b0_4_1152000_200] = {
2809                 .flags          = FL_BASE0,
2810                 .num_ports      = 4,
2811                 .base_baud      = 1152000,
2812                 .uart_offset    = 0x200,
2813         },
2814
2815         [pbn_b0_8_1152000_200] = {
2816                 .flags          = FL_BASE0,
2817                 .num_ports      = 8,
2818                 .base_baud      = 1152000,
2819                 .uart_offset    = 0x200,
2820         },
2821
2822         [pbn_b0_2_1843200] = {
2823                 .flags          = FL_BASE0,
2824                 .num_ports      = 2,
2825                 .base_baud      = 1843200,
2826                 .uart_offset    = 8,
2827         },
2828         [pbn_b0_4_1843200] = {
2829                 .flags          = FL_BASE0,
2830                 .num_ports      = 4,
2831                 .base_baud      = 1843200,
2832                 .uart_offset    = 8,
2833         },
2834
2835         [pbn_b0_2_1843200_200] = {
2836                 .flags          = FL_BASE0,
2837                 .num_ports      = 2,
2838                 .base_baud      = 1843200,
2839                 .uart_offset    = 0x200,
2840         },
2841         [pbn_b0_4_1843200_200] = {
2842                 .flags          = FL_BASE0,
2843                 .num_ports      = 4,
2844                 .base_baud      = 1843200,
2845                 .uart_offset    = 0x200,
2846         },
2847         [pbn_b0_8_1843200_200] = {
2848                 .flags          = FL_BASE0,
2849                 .num_ports      = 8,
2850                 .base_baud      = 1843200,
2851                 .uart_offset    = 0x200,
2852         },
2853         [pbn_b0_1_4000000] = {
2854                 .flags          = FL_BASE0,
2855                 .num_ports      = 1,
2856                 .base_baud      = 4000000,
2857                 .uart_offset    = 8,
2858         },
2859
2860         [pbn_b0_bt_1_115200] = {
2861                 .flags          = FL_BASE0|FL_BASE_BARS,
2862                 .num_ports      = 1,
2863                 .base_baud      = 115200,
2864                 .uart_offset    = 8,
2865         },
2866         [pbn_b0_bt_2_115200] = {
2867                 .flags          = FL_BASE0|FL_BASE_BARS,
2868                 .num_ports      = 2,
2869                 .base_baud      = 115200,
2870                 .uart_offset    = 8,
2871         },
2872         [pbn_b0_bt_4_115200] = {
2873                 .flags          = FL_BASE0|FL_BASE_BARS,
2874                 .num_ports      = 4,
2875                 .base_baud      = 115200,
2876                 .uart_offset    = 8,
2877         },
2878         [pbn_b0_bt_8_115200] = {
2879                 .flags          = FL_BASE0|FL_BASE_BARS,
2880                 .num_ports      = 8,
2881                 .base_baud      = 115200,
2882                 .uart_offset    = 8,
2883         },
2884
2885         [pbn_b0_bt_1_460800] = {
2886                 .flags          = FL_BASE0|FL_BASE_BARS,
2887                 .num_ports      = 1,
2888                 .base_baud      = 460800,
2889                 .uart_offset    = 8,
2890         },
2891         [pbn_b0_bt_2_460800] = {
2892                 .flags          = FL_BASE0|FL_BASE_BARS,
2893                 .num_ports      = 2,
2894                 .base_baud      = 460800,
2895                 .uart_offset    = 8,
2896         },
2897         [pbn_b0_bt_4_460800] = {
2898                 .flags          = FL_BASE0|FL_BASE_BARS,
2899                 .num_ports      = 4,
2900                 .base_baud      = 460800,
2901                 .uart_offset    = 8,
2902         },
2903
2904         [pbn_b0_bt_1_921600] = {
2905                 .flags          = FL_BASE0|FL_BASE_BARS,
2906                 .num_ports      = 1,
2907                 .base_baud      = 921600,
2908                 .uart_offset    = 8,
2909         },
2910         [pbn_b0_bt_2_921600] = {
2911                 .flags          = FL_BASE0|FL_BASE_BARS,
2912                 .num_ports      = 2,
2913                 .base_baud      = 921600,
2914                 .uart_offset    = 8,
2915         },
2916         [pbn_b0_bt_4_921600] = {
2917                 .flags          = FL_BASE0|FL_BASE_BARS,
2918                 .num_ports      = 4,
2919                 .base_baud      = 921600,
2920                 .uart_offset    = 8,
2921         },
2922         [pbn_b0_bt_8_921600] = {
2923                 .flags          = FL_BASE0|FL_BASE_BARS,
2924                 .num_ports      = 8,
2925                 .base_baud      = 921600,
2926                 .uart_offset    = 8,
2927         },
2928
2929         [pbn_b1_1_115200] = {
2930                 .flags          = FL_BASE1,
2931                 .num_ports      = 1,
2932                 .base_baud      = 115200,
2933                 .uart_offset    = 8,
2934         },
2935         [pbn_b1_2_115200] = {
2936                 .flags          = FL_BASE1,
2937                 .num_ports      = 2,
2938                 .base_baud      = 115200,
2939                 .uart_offset    = 8,
2940         },
2941         [pbn_b1_4_115200] = {
2942                 .flags          = FL_BASE1,
2943                 .num_ports      = 4,
2944                 .base_baud      = 115200,
2945                 .uart_offset    = 8,
2946         },
2947         [pbn_b1_8_115200] = {
2948                 .flags          = FL_BASE1,
2949                 .num_ports      = 8,
2950                 .base_baud      = 115200,
2951                 .uart_offset    = 8,
2952         },
2953         [pbn_b1_16_115200] = {
2954                 .flags          = FL_BASE1,
2955                 .num_ports      = 16,
2956                 .base_baud      = 115200,
2957                 .uart_offset    = 8,
2958         },
2959
2960         [pbn_b1_1_921600] = {
2961                 .flags          = FL_BASE1,
2962                 .num_ports      = 1,
2963                 .base_baud      = 921600,
2964                 .uart_offset    = 8,
2965         },
2966         [pbn_b1_2_921600] = {
2967                 .flags          = FL_BASE1,
2968                 .num_ports      = 2,
2969                 .base_baud      = 921600,
2970                 .uart_offset    = 8,
2971         },
2972         [pbn_b1_4_921600] = {
2973                 .flags          = FL_BASE1,
2974                 .num_ports      = 4,
2975                 .base_baud      = 921600,
2976                 .uart_offset    = 8,
2977         },
2978         [pbn_b1_8_921600] = {
2979                 .flags          = FL_BASE1,
2980                 .num_ports      = 8,
2981                 .base_baud      = 921600,
2982                 .uart_offset    = 8,
2983         },
2984         [pbn_b1_2_1250000] = {
2985                 .flags          = FL_BASE1,
2986                 .num_ports      = 2,
2987                 .base_baud      = 1250000,
2988                 .uart_offset    = 8,
2989         },
2990
2991         [pbn_b1_bt_1_115200] = {
2992                 .flags          = FL_BASE1|FL_BASE_BARS,
2993                 .num_ports      = 1,
2994                 .base_baud      = 115200,
2995                 .uart_offset    = 8,
2996         },
2997         [pbn_b1_bt_2_115200] = {
2998                 .flags          = FL_BASE1|FL_BASE_BARS,
2999                 .num_ports      = 2,
3000                 .base_baud      = 115200,
3001                 .uart_offset    = 8,
3002         },
3003         [pbn_b1_bt_4_115200] = {
3004                 .flags          = FL_BASE1|FL_BASE_BARS,
3005                 .num_ports      = 4,
3006                 .base_baud      = 115200,
3007                 .uart_offset    = 8,
3008         },
3009
3010         [pbn_b1_bt_2_921600] = {
3011                 .flags          = FL_BASE1|FL_BASE_BARS,
3012                 .num_ports      = 2,
3013                 .base_baud      = 921600,
3014                 .uart_offset    = 8,
3015         },
3016
3017         [pbn_b1_1_1382400] = {
3018                 .flags          = FL_BASE1,
3019                 .num_ports      = 1,
3020                 .base_baud      = 1382400,
3021                 .uart_offset    = 8,
3022         },
3023         [pbn_b1_2_1382400] = {
3024                 .flags          = FL_BASE1,
3025                 .num_ports      = 2,
3026                 .base_baud      = 1382400,
3027                 .uart_offset    = 8,
3028         },
3029         [pbn_b1_4_1382400] = {
3030                 .flags          = FL_BASE1,
3031                 .num_ports      = 4,
3032                 .base_baud      = 1382400,
3033                 .uart_offset    = 8,
3034         },
3035         [pbn_b1_8_1382400] = {
3036                 .flags          = FL_BASE1,
3037                 .num_ports      = 8,
3038                 .base_baud      = 1382400,
3039                 .uart_offset    = 8,
3040         },
3041
3042         [pbn_b2_1_115200] = {
3043                 .flags          = FL_BASE2,
3044                 .num_ports      = 1,
3045                 .base_baud      = 115200,
3046                 .uart_offset    = 8,
3047         },
3048         [pbn_b2_2_115200] = {
3049                 .flags          = FL_BASE2,
3050                 .num_ports      = 2,
3051                 .base_baud      = 115200,
3052                 .uart_offset    = 8,
3053         },
3054         [pbn_b2_4_115200] = {
3055                 .flags          = FL_BASE2,
3056                 .num_ports      = 4,
3057                 .base_baud      = 115200,
3058                 .uart_offset    = 8,
3059         },
3060         [pbn_b2_8_115200] = {
3061                 .flags          = FL_BASE2,
3062                 .num_ports      = 8,
3063                 .base_baud      = 115200,
3064                 .uart_offset    = 8,
3065         },
3066
3067         [pbn_b2_1_460800] = {
3068                 .flags          = FL_BASE2,
3069                 .num_ports      = 1,
3070                 .base_baud      = 460800,
3071                 .uart_offset    = 8,
3072         },
3073         [pbn_b2_4_460800] = {
3074                 .flags          = FL_BASE2,
3075                 .num_ports      = 4,
3076                 .base_baud      = 460800,
3077                 .uart_offset    = 8,
3078         },
3079         [pbn_b2_8_460800] = {
3080                 .flags          = FL_BASE2,
3081                 .num_ports      = 8,
3082                 .base_baud      = 460800,
3083                 .uart_offset    = 8,
3084         },
3085         [pbn_b2_16_460800] = {
3086                 .flags          = FL_BASE2,
3087                 .num_ports      = 16,
3088                 .base_baud      = 460800,
3089                 .uart_offset    = 8,
3090          },
3091
3092         [pbn_b2_1_921600] = {
3093                 .flags          = FL_BASE2,
3094                 .num_ports      = 1,
3095                 .base_baud      = 921600,
3096                 .uart_offset    = 8,
3097         },
3098         [pbn_b2_4_921600] = {
3099                 .flags          = FL_BASE2,
3100                 .num_ports      = 4,
3101                 .base_baud      = 921600,
3102                 .uart_offset    = 8,
3103         },
3104         [pbn_b2_8_921600] = {
3105                 .flags          = FL_BASE2,
3106                 .num_ports      = 8,
3107                 .base_baud      = 921600,
3108                 .uart_offset    = 8,
3109         },
3110
3111         [pbn_b2_8_1152000] = {
3112                 .flags          = FL_BASE2,
3113                 .num_ports      = 8,
3114                 .base_baud      = 1152000,
3115                 .uart_offset    = 8,
3116         },
3117
3118         [pbn_b2_bt_1_115200] = {
3119                 .flags          = FL_BASE2|FL_BASE_BARS,
3120                 .num_ports      = 1,
3121                 .base_baud      = 115200,
3122                 .uart_offset    = 8,
3123         },
3124         [pbn_b2_bt_2_115200] = {
3125                 .flags          = FL_BASE2|FL_BASE_BARS,
3126                 .num_ports      = 2,
3127                 .base_baud      = 115200,
3128                 .uart_offset    = 8,
3129         },
3130         [pbn_b2_bt_4_115200] = {
3131                 .flags          = FL_BASE2|FL_BASE_BARS,
3132                 .num_ports      = 4,
3133                 .base_baud      = 115200,
3134                 .uart_offset    = 8,
3135         },
3136
3137         [pbn_b2_bt_2_921600] = {
3138                 .flags          = FL_BASE2|FL_BASE_BARS,
3139                 .num_ports      = 2,
3140                 .base_baud      = 921600,
3141                 .uart_offset    = 8,
3142         },
3143         [pbn_b2_bt_4_921600] = {
3144                 .flags          = FL_BASE2|FL_BASE_BARS,
3145                 .num_ports      = 4,
3146                 .base_baud      = 921600,
3147                 .uart_offset    = 8,
3148         },
3149
3150         [pbn_b3_2_115200] = {
3151                 .flags          = FL_BASE3,
3152                 .num_ports      = 2,
3153                 .base_baud      = 115200,
3154                 .uart_offset    = 8,
3155         },
3156         [pbn_b3_4_115200] = {
3157                 .flags          = FL_BASE3,
3158                 .num_ports      = 4,
3159                 .base_baud      = 115200,
3160                 .uart_offset    = 8,
3161         },
3162         [pbn_b3_8_115200] = {
3163                 .flags          = FL_BASE3,
3164                 .num_ports      = 8,
3165                 .base_baud      = 115200,
3166                 .uart_offset    = 8,
3167         },
3168
3169         [pbn_b4_bt_2_921600] = {
3170                 .flags          = FL_BASE4,
3171                 .num_ports      = 2,
3172                 .base_baud      = 921600,
3173                 .uart_offset    = 8,
3174         },
3175         [pbn_b4_bt_4_921600] = {
3176                 .flags          = FL_BASE4,
3177                 .num_ports      = 4,
3178                 .base_baud      = 921600,
3179                 .uart_offset    = 8,
3180         },
3181         [pbn_b4_bt_8_921600] = {
3182                 .flags          = FL_BASE4,
3183                 .num_ports      = 8,
3184                 .base_baud      = 921600,
3185                 .uart_offset    = 8,
3186         },
3187
3188         /*
3189          * Entries following this are board-specific.
3190          */
3191
3192         /*
3193          * Panacom - IOMEM
3194          */
3195         [pbn_panacom] = {
3196                 .flags          = FL_BASE2,
3197                 .num_ports      = 2,
3198                 .base_baud      = 921600,
3199                 .uart_offset    = 0x400,
3200                 .reg_shift      = 7,
3201         },
3202         [pbn_panacom2] = {
3203                 .flags          = FL_BASE2|FL_BASE_BARS,
3204                 .num_ports      = 2,
3205                 .base_baud      = 921600,
3206                 .uart_offset    = 0x400,
3207                 .reg_shift      = 7,
3208         },
3209         [pbn_panacom4] = {
3210                 .flags          = FL_BASE2|FL_BASE_BARS,
3211                 .num_ports      = 4,
3212                 .base_baud      = 921600,
3213                 .uart_offset    = 0x400,
3214                 .reg_shift      = 7,
3215         },
3216
3217         /* I think this entry is broken - the first_offset looks wrong --rmk */
3218         [pbn_plx_romulus] = {
3219                 .flags          = FL_BASE2,
3220                 .num_ports      = 4,
3221                 .base_baud      = 921600,
3222                 .uart_offset    = 8 << 2,
3223                 .reg_shift      = 2,
3224                 .first_offset   = 0x03,
3225         },
3226
3227         /*
3228          * This board uses the size of PCI Base region 0 to
3229          * signal now many ports are available
3230          */
3231         [pbn_oxsemi] = {
3232                 .flags          = FL_BASE0|FL_REGION_SZ_CAP,
3233                 .num_ports      = 32,
3234                 .base_baud      = 115200,
3235                 .uart_offset    = 8,
3236         },
3237         [pbn_oxsemi_1_4000000] = {
3238                 .flags          = FL_BASE0,
3239                 .num_ports      = 1,
3240                 .base_baud      = 4000000,
3241                 .uart_offset    = 0x200,
3242                 .first_offset   = 0x1000,
3243         },
3244         [pbn_oxsemi_2_4000000] = {
3245                 .flags          = FL_BASE0,
3246                 .num_ports      = 2,
3247                 .base_baud      = 4000000,
3248                 .uart_offset    = 0x200,
3249                 .first_offset   = 0x1000,
3250         },
3251         [pbn_oxsemi_4_4000000] = {
3252                 .flags          = FL_BASE0,
3253                 .num_ports      = 4,
3254                 .base_baud      = 4000000,
3255                 .uart_offset    = 0x200,
3256                 .first_offset   = 0x1000,
3257         },
3258         [pbn_oxsemi_8_4000000] = {
3259                 .flags          = FL_BASE0,
3260                 .num_ports      = 8,
3261                 .base_baud      = 4000000,
3262                 .uart_offset    = 0x200,
3263                 .first_offset   = 0x1000,
3264         },
3265
3266
3267         /*
3268          * EKF addition for i960 Boards form EKF with serial port.
3269          * Max 256 ports.
3270          */
3271         [pbn_intel_i960] = {
3272                 .flags          = FL_BASE0,
3273                 .num_ports      = 32,
3274                 .base_baud      = 921600,
3275                 .uart_offset    = 8 << 2,
3276                 .reg_shift      = 2,
3277                 .first_offset   = 0x10000,
3278         },
3279         [pbn_sgi_ioc3] = {
3280                 .flags          = FL_BASE0|FL_NOIRQ,
3281                 .num_ports      = 1,
3282                 .base_baud      = 458333,
3283                 .uart_offset    = 8,
3284                 .reg_shift      = 0,
3285                 .first_offset   = 0x20178,
3286         },
3287
3288         /*
3289          * Computone - uses IOMEM.
3290          */
3291         [pbn_computone_4] = {
3292                 .flags          = FL_BASE0,
3293                 .num_ports      = 4,
3294                 .base_baud      = 921600,
3295                 .uart_offset    = 0x40,
3296                 .reg_shift      = 2,
3297                 .first_offset   = 0x200,
3298         },
3299         [pbn_computone_6] = {
3300                 .flags          = FL_BASE0,
3301                 .num_ports      = 6,
3302                 .base_baud      = 921600,
3303                 .uart_offset    = 0x40,
3304                 .reg_shift      = 2,
3305                 .first_offset   = 0x200,
3306         },
3307         [pbn_computone_8] = {
3308                 .flags          = FL_BASE0,
3309                 .num_ports      = 8,
3310                 .base_baud      = 921600,
3311                 .uart_offset    = 0x40,
3312                 .reg_shift      = 2,
3313                 .first_offset   = 0x200,
3314         },
3315         [pbn_sbsxrsio] = {
3316                 .flags          = FL_BASE0,
3317                 .num_ports      = 8,
3318                 .base_baud      = 460800,
3319                 .uart_offset    = 256,
3320                 .reg_shift      = 4,
3321         },
3322         /*
3323          * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3324          *  Only basic 16550A support.
3325          *  XR17C15[24] are not tested, but they should work.
3326          */
3327         [pbn_exar_XR17C152] = {
3328                 .flags          = FL_BASE0,
3329                 .num_ports      = 2,
3330                 .base_baud      = 921600,
3331                 .uart_offset    = 0x200,
3332         },
3333         [pbn_exar_XR17C154] = {
3334                 .flags          = FL_BASE0,
3335                 .num_ports      = 4,
3336                 .base_baud      = 921600,
3337                 .uart_offset    = 0x200,
3338         },
3339         [pbn_exar_XR17C158] = {
3340                 .flags          = FL_BASE0,
3341                 .num_ports      = 8,
3342                 .base_baud      = 921600,
3343                 .uart_offset    = 0x200,
3344         },
3345         [pbn_exar_XR17V352] = {
3346                 .flags          = FL_BASE0,
3347                 .num_ports      = 2,
3348                 .base_baud      = 7812500,
3349                 .uart_offset    = 0x400,
3350                 .reg_shift      = 0,
3351                 .first_offset   = 0,
3352         },
3353         [pbn_exar_XR17V354] = {
3354                 .flags          = FL_BASE0,
3355                 .num_ports      = 4,
3356                 .base_baud      = 7812500,
3357                 .uart_offset    = 0x400,
3358                 .reg_shift      = 0,
3359                 .first_offset   = 0,
3360         },
3361         [pbn_exar_XR17V358] = {
3362                 .flags          = FL_BASE0,
3363                 .num_ports      = 8,
3364                 .base_baud      = 7812500,
3365                 .uart_offset    = 0x400,
3366                 .reg_shift      = 0,
3367                 .first_offset   = 0,
3368         },
3369         [pbn_exar_ibm_saturn] = {
3370                 .flags          = FL_BASE0,
3371                 .num_ports      = 1,
3372                 .base_baud      = 921600,
3373                 .uart_offset    = 0x200,
3374         },
3375
3376         /*
3377          * PA Semi PWRficient PA6T-1682M on-chip UART
3378          */
3379         [pbn_pasemi_1682M] = {
3380                 .flags          = FL_BASE0,
3381                 .num_ports      = 1,
3382                 .base_baud      = 8333333,
3383         },
3384         /*
3385          * National Instruments 843x
3386          */
3387         [pbn_ni8430_16] = {
3388                 .flags          = FL_BASE0,
3389                 .num_ports      = 16,
3390                 .base_baud      = 3686400,
3391                 .uart_offset    = 0x10,
3392                 .first_offset   = 0x800,
3393         },
3394         [pbn_ni8430_8] = {
3395                 .flags          = FL_BASE0,
3396                 .num_ports      = 8,
3397                 .base_baud      = 3686400,
3398                 .uart_offset    = 0x10,
3399                 .first_offset   = 0x800,
3400         },
3401         [pbn_ni8430_4] = {
3402                 .flags          = FL_BASE0,
3403                 .num_ports      = 4,
3404                 .base_baud      = 3686400,
3405                 .uart_offset    = 0x10,
3406                 .first_offset   = 0x800,
3407         },
3408         [pbn_ni8430_2] = {
3409                 .flags          = FL_BASE0,
3410                 .num_ports      = 2,
3411                 .base_baud      = 3686400,
3412                 .uart_offset    = 0x10,
3413                 .first_offset   = 0x800,
3414         },
3415         /*
3416          * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
3417          */
3418         [pbn_ADDIDATA_PCIe_1_3906250] = {
3419                 .flags          = FL_BASE0,
3420                 .num_ports      = 1,
3421                 .base_baud      = 3906250,
3422                 .uart_offset    = 0x200,
3423                 .first_offset   = 0x1000,
3424         },
3425         [pbn_ADDIDATA_PCIe_2_3906250] = {
3426                 .flags          = FL_BASE0,
3427                 .num_ports      = 2,
3428                 .base_baud      = 3906250,
3429                 .uart_offset    = 0x200,
3430                 .first_offset   = 0x1000,
3431         },
3432         [pbn_ADDIDATA_PCIe_4_3906250] = {
3433                 .flags          = FL_BASE0,
3434                 .num_ports      = 4,
3435                 .base_baud      = 3906250,
3436                 .uart_offset    = 0x200,
3437                 .first_offset   = 0x1000,
3438         },
3439         [pbn_ADDIDATA_PCIe_8_3906250] = {
3440                 .flags          = FL_BASE0,
3441                 .num_ports      = 8,
3442                 .base_baud      = 3906250,
3443                 .uart_offset    = 0x200,
3444                 .first_offset   = 0x1000,
3445         },
3446         [pbn_ce4100_1_115200] = {
3447                 .flags          = FL_BASE_BARS,
3448                 .num_ports      = 2,
3449                 .base_baud      = 921600,
3450                 .reg_shift      = 2,
3451         },
3452         [pbn_byt] = {
3453                 .flags          = FL_BASE0,
3454                 .num_ports      = 1,
3455                 .base_baud      = 2764800,
3456                 .uart_offset    = 0x80,
3457                 .reg_shift      = 2,
3458         },
3459         [pbn_omegapci] = {
3460                 .flags          = FL_BASE0,
3461                 .num_ports      = 8,
3462                 .base_baud      = 115200,
3463                 .uart_offset    = 0x200,
3464         },
3465         [pbn_NETMOS9900_2s_115200] = {
3466                 .flags          = FL_BASE0,
3467                 .num_ports      = 2,
3468                 .base_baud      = 115200,
3469         },
3470         [pbn_brcm_trumanage] = {
3471                 .flags          = FL_BASE0,
3472                 .num_ports      = 1,
3473                 .reg_shift      = 2,
3474                 .base_baud      = 115200,
3475         },
3476         [pbn_fintek_4] = {
3477                 .num_ports      = 4,
3478                 .uart_offset    = 8,
3479                 .base_baud      = 115200,
3480                 .first_offset   = 0x40,
3481         },
3482         [pbn_fintek_8] = {
3483                 .num_ports      = 8,
3484                 .uart_offset    = 8,
3485                 .base_baud      = 115200,
3486                 .first_offset   = 0x40,
3487         },
3488         [pbn_fintek_12] = {
3489                 .num_ports      = 12,
3490                 .uart_offset    = 8,
3491                 .base_baud      = 115200,
3492                 .first_offset   = 0x40,
3493         },
3494 };
3495
3496 static const struct pci_device_id blacklist[] = {
3497         /* softmodems */
3498         { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
3499         { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
3500         { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
3501
3502         /* multi-io cards handled by parport_serial */
3503         { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */
3504 };
3505
3506 /*
3507  * Given a complete unknown PCI device, try to use some heuristics to
3508  * guess what the configuration might be, based on the pitiful PCI
3509  * serial specs.  Returns 0 on success, 1 on failure.
3510  */
3511 static int
3512 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
3513 {
3514         const struct pci_device_id *bldev;
3515         int num_iomem, num_port, first_port = -1, i;
3516
3517         /*
3518          * If it is not a communications device or the programming
3519          * interface is greater than 6, give up.
3520          *
3521          * (Should we try to make guesses for multiport serial devices
3522          * later?)
3523          */
3524         if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
3525              ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
3526             (dev->class & 0xff) > 6)
3527                 return -ENODEV;
3528
3529         /*
3530          * Do not access blacklisted devices that are known not to
3531          * feature serial ports or are handled by other modules.
3532          */
3533         for (bldev = blacklist;
3534              bldev < blacklist + ARRAY_SIZE(blacklist);
3535              bldev++) {
3536                 if (dev->vendor == bldev->vendor &&
3537                     dev->device == bldev->device)
3538                         return -ENODEV;
3539         }
3540
3541         num_iomem = num_port = 0;
3542         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3543                 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
3544                         num_port++;
3545                         if (first_port == -1)
3546                                 first_port = i;
3547                 }
3548                 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
3549                         num_iomem++;
3550         }
3551
3552         /*
3553          * If there is 1 or 0 iomem regions, and exactly one port,
3554          * use it.  We guess the number of ports based on the IO
3555          * region size.
3556          */
3557         if (num_iomem <= 1 && num_port == 1) {
3558                 board->flags = first_port;
3559                 board->num_ports = pci_resource_len(dev, first_port) / 8;
3560                 return 0;
3561         }
3562
3563         /*
3564          * Now guess if we've got a board which indexes by BARs.
3565          * Each IO BAR should be 8 bytes, and they should follow
3566          * consecutively.
3567          */
3568         first_port = -1;
3569         num_port = 0;
3570         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3571                 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
3572                     pci_resource_len(dev, i) == 8 &&
3573                     (first_port == -1 || (first_port + num_port) == i)) {
3574                         num_port++;
3575                         if (first_port == -1)
3576                                 first_port = i;
3577                 }
3578         }
3579
3580         if (num_port > 1) {
3581                 board->flags = first_port | FL_BASE_BARS;
3582                 board->num_ports = num_port;
3583                 return 0;
3584         }
3585
3586         return -ENODEV;
3587 }
3588
3589 static inline int
3590 serial_pci_matches(const struct pciserial_board *board,
3591                    const struct pciserial_board *guessed)
3592 {
3593         return
3594             board->num_ports == guessed->num_ports &&
3595             board->base_baud == guessed->base_baud &&
3596             board->uart_offset == guessed->uart_offset &&
3597             board->reg_shift == guessed->reg_shift &&
3598             board->first_offset == guessed->first_offset;
3599 }
3600
3601 struct serial_private *
3602 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
3603 {
3604         struct uart_8250_port uart;
3605         struct serial_private *priv;
3606         struct pci_serial_quirk *quirk;
3607         int rc, nr_ports, i;
3608
3609         nr_ports = board->num_ports;
3610
3611         /*
3612          * Find an init and setup quirks.
3613          */
3614         quirk = find_quirk(dev);
3615
3616         /*
3617          * Run the new-style initialization function.
3618          * The initialization function returns:
3619          *  <0  - error
3620          *   0  - use board->num_ports
3621          *  >0  - number of ports
3622          */
3623         if (quirk->init) {
3624                 rc = quirk->init(dev);
3625                 if (rc < 0) {
3626                         priv = ERR_PTR(rc);
3627                         goto err_out;
3628                 }
3629                 if (rc)
3630                         nr_ports = rc;
3631         }
3632
3633         priv = kzalloc(sizeof(struct serial_private) +
3634                        sizeof(unsigned int) * nr_ports,
3635                        GFP_KERNEL);
3636         if (!priv) {
3637                 priv = ERR_PTR(-ENOMEM);
3638                 goto err_deinit;
3639         }
3640
3641         priv->dev = dev;
3642         priv->quirk = quirk;
3643
3644         memset(&uart, 0, sizeof(uart));
3645         uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
3646         uart.port.uartclk = board->base_baud * 16;
3647         uart.port.irq = get_pci_irq(dev, board);
3648         uart.port.dev = &dev->dev;
3649
3650         for (i = 0; i < nr_ports; i++) {
3651                 if (quirk->setup(priv, board, &uart, i))
3652                         break;
3653
3654                 dev_dbg(&dev->dev, "Setup PCI port: port %lx, irq %d, type %d\n",
3655                         uart.port.iobase, uart.port.irq, uart.port.iotype);
3656
3657                 priv->line[i] = serial8250_register_8250_port(&uart);
3658                 if (priv->line[i] < 0) {
3659                         dev_err(&dev->dev,
3660                                 "Couldn't register serial port %lx, irq %d, type %d, error %d\n",
3661                                 uart.port.iobase, uart.port.irq,
3662                                 uart.port.iotype, priv->line[i]);
3663                         break;
3664                 }
3665         }
3666         priv->nr = i;
3667         return priv;
3668
3669 err_deinit:
3670         if (quirk->exit)
3671                 quirk->exit(dev);
3672 err_out:
3673         return priv;
3674 }
3675 EXPORT_SYMBOL_GPL(pciserial_init_ports);
3676
3677 void pciserial_remove_ports(struct serial_private *priv)
3678 {
3679         struct pci_serial_quirk *quirk;
3680         int i;
3681
3682         for (i = 0; i < priv->nr; i++)
3683                 serial8250_unregister_port(priv->line[i]);
3684
3685         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3686                 if (priv->remapped_bar[i])
3687                         iounmap(priv->remapped_bar[i]);
3688                 priv->remapped_bar[i] = NULL;
3689         }
3690
3691         /*
3692          * Find the exit quirks.
3693          */
3694         quirk = find_quirk(priv->dev);
3695         if (quirk->exit)
3696                 quirk->exit(priv->dev);
3697
3698         kfree(priv);
3699 }
3700 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
3701
3702 void pciserial_suspend_ports(struct serial_private *priv)
3703 {
3704         int i;
3705
3706         for (i = 0; i < priv->nr; i++)
3707                 if (priv->line[i] >= 0)
3708                         serial8250_suspend_port(priv->line[i]);
3709
3710         /*
3711          * Ensure that every init quirk is properly torn down
3712          */
3713         if (priv->quirk->exit)
3714                 priv->quirk->exit(priv->dev);
3715 }
3716 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
3717
3718 void pciserial_resume_ports(struct serial_private *priv)
3719 {
3720         int i;
3721
3722         /*
3723          * Ensure that the board is correctly configured.
3724          */
3725         if (priv->quirk->init)
3726                 priv->quirk->init(priv->dev);
3727
3728         for (i = 0; i < priv->nr; i++)
3729                 if (priv->line[i] >= 0)
3730                         serial8250_resume_port(priv->line[i]);
3731 }
3732 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
3733
3734 /*
3735  * Probe one serial board.  Unfortunately, there is no rhyme nor reason
3736  * to the arrangement of serial ports on a PCI card.
3737  */
3738 static int
3739 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
3740 {
3741         struct pci_serial_quirk *quirk;
3742         struct serial_private *priv;
3743         const struct pciserial_board *board;
3744         struct pciserial_board tmp;
3745         int rc;
3746
3747         quirk = find_quirk(dev);
3748         if (quirk->probe) {
3749                 rc = quirk->probe(dev);
3750                 if (rc)
3751                         return rc;
3752         }
3753
3754         if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
3755                 dev_err(&dev->dev, "invalid driver_data: %ld\n",
3756                         ent->driver_data);
3757                 return -EINVAL;
3758         }
3759
3760         board = &pci_boards[ent->driver_data];
3761
3762         rc = pci_enable_device(dev);
3763         pci_save_state(dev);
3764         if (rc)
3765                 return rc;
3766
3767         if (ent->driver_data == pbn_default) {
3768                 /*
3769                  * Use a copy of the pci_board entry for this;
3770                  * avoid changing entries in the table.
3771                  */
3772                 memcpy(&tmp, board, sizeof(struct pciserial_board));
3773                 board = &tmp;
3774
3775                 /*
3776                  * We matched one of our class entries.  Try to
3777                  * determine the parameters of this board.
3778                  */
3779                 rc = serial_pci_guess_board(dev, &tmp);
3780                 if (rc)
3781                         goto disable;
3782         } else {
3783                 /*
3784                  * We matched an explicit entry.  If we are able to
3785                  * detect this boards settings with our heuristic,
3786                  * then we no longer need this entry.
3787                  */
3788                 memcpy(&tmp, &pci_boards[pbn_default],
3789                        sizeof(struct pciserial_board));
3790                 rc = serial_pci_guess_board(dev, &tmp);
3791                 if (rc == 0 && serial_pci_matches(board, &tmp))
3792                         moan_device("Redundant entry in serial pci_table.",
3793                                     dev);
3794         }
3795
3796         priv = pciserial_init_ports(dev, board);
3797         if (!IS_ERR(priv)) {
3798                 pci_set_drvdata(dev, priv);
3799                 return 0;
3800         }
3801
3802         rc = PTR_ERR(priv);
3803
3804  disable:
3805         pci_disable_device(dev);
3806         return rc;
3807 }
3808
3809 static void pciserial_remove_one(struct pci_dev *dev)
3810 {
3811         struct serial_private *priv = pci_get_drvdata(dev);
3812
3813         pciserial_remove_ports(priv);
3814
3815         pci_disable_device(dev);
3816 }
3817
3818 #ifdef CONFIG_PM
3819 static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
3820 {
3821         struct serial_private *priv = pci_get_drvdata(dev);
3822
3823         if (priv)
3824                 pciserial_suspend_ports(priv);
3825
3826         pci_save_state(dev);
3827         pci_set_power_state(dev, pci_choose_state(dev, state));
3828         return 0;
3829 }
3830
3831 static int pciserial_resume_one(struct pci_dev *dev)
3832 {
3833         int err;
3834         struct serial_private *priv = pci_get_drvdata(dev);
3835
3836         pci_set_power_state(dev, PCI_D0);
3837         pci_restore_state(dev);
3838
3839         if (priv) {
3840                 /*
3841                  * The device may have been disabled.  Re-enable it.
3842                  */
3843                 err = pci_enable_device(dev);
3844                 /* FIXME: We cannot simply error out here */
3845                 if (err)
3846                         dev_err(&dev->dev, "Unable to re-enable ports, trying to continue.\n");
3847                 pciserial_resume_ports(priv);
3848         }
3849         return 0;
3850 }
3851 #endif
3852
3853 static struct pci_device_id serial_pci_tbl[] = {
3854         /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
3855         {       PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
3856                 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
3857                 pbn_b2_8_921600 },
3858         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3859                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3860                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
3861                 pbn_b1_8_1382400 },
3862         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3863                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3864                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
3865                 pbn_b1_4_1382400 },
3866         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3867                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3868                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
3869                 pbn_b1_2_1382400 },
3870         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3871                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3872                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
3873                 pbn_b1_8_1382400 },
3874         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3875                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3876                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
3877                 pbn_b1_4_1382400 },
3878         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3879                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3880                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
3881                 pbn_b1_2_1382400 },
3882         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3883                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3884                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
3885                 pbn_b1_8_921600 },
3886         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3887                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3888                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
3889                 pbn_b1_8_921600 },
3890         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3891                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3892                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
3893                 pbn_b1_4_921600 },
3894         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3895                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3896                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
3897                 pbn_b1_4_921600 },
3898         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3899                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3900                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
3901                 pbn_b1_2_921600 },
3902         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3903                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3904                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
3905                 pbn_b1_8_921600 },
3906         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3907                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3908                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
3909                 pbn_b1_8_921600 },
3910         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3911                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3912                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
3913                 pbn_b1_4_921600 },
3914         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3915                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3916                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
3917                 pbn_b1_2_1250000 },
3918         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3919                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3920                 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
3921                 pbn_b0_2_1843200 },
3922         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3923                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3924                 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
3925                 pbn_b0_4_1843200 },
3926         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3927                 PCI_VENDOR_ID_AFAVLAB,
3928                 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
3929                 pbn_b0_4_1152000 },
3930         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3931                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3932                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
3933                 pbn_b0_2_1843200_200 },
3934         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3935                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3936                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
3937                 pbn_b0_4_1843200_200 },
3938         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3939                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3940                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
3941                 pbn_b0_8_1843200_200 },
3942         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3943                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3944                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
3945                 pbn_b0_2_1843200_200 },
3946         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3947                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3948                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
3949                 pbn_b0_4_1843200_200 },
3950         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3951                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3952                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
3953                 pbn_b0_8_1843200_200 },
3954         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3955                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3956                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
3957                 pbn_b0_2_1843200_200 },
3958         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3959                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3960                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
3961                 pbn_b0_4_1843200_200 },
3962         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3963                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3964                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
3965                 pbn_b0_8_1843200_200 },
3966         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3967                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3968                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
3969                 pbn_b0_2_1843200_200 },
3970         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3971                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3972                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
3973                 pbn_b0_4_1843200_200 },
3974         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3975                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3976                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
3977                 pbn_b0_8_1843200_200 },
3978         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3979                 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT,
3980                 0, 0, pbn_exar_ibm_saturn },
3981
3982         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
3983                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3984                 pbn_b2_bt_1_115200 },
3985         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
3986                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3987                 pbn_b2_bt_2_115200 },
3988         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
3989                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3990                 pbn_b2_bt_4_115200 },
3991         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
3992                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3993                 pbn_b2_bt_2_115200 },
3994         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
3995                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3996                 pbn_b2_bt_4_115200 },
3997         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
3998                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3999                 pbn_b2_8_115200 },
4000         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
4001                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4002                 pbn_b2_8_460800 },
4003         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
4004                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4005                 pbn_b2_8_115200 },
4006
4007         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
4008                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4009                 pbn_b2_bt_2_115200 },
4010         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
4011                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4012                 pbn_b2_bt_2_921600 },
4013         /*
4014          * VScom SPCOM800, from sl@s.pl
4015          */
4016         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
4017                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4018                 pbn_b2_8_921600 },
4019         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
4020                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4021                 pbn_b2_4_921600 },
4022         /* Unknown card - subdevice 0x1584 */
4023         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4024                 PCI_VENDOR_ID_PLX,
4025                 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
4026                 pbn_b2_4_115200 },
4027         /* Unknown card - subdevice 0x1588 */
4028         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4029                 PCI_VENDOR_ID_PLX,
4030                 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0,
4031                 pbn_b2_8_115200 },
4032         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4033                 PCI_SUBVENDOR_ID_KEYSPAN,
4034                 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
4035                 pbn_panacom },
4036         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
4037                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4038                 pbn_panacom4 },
4039         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
4040                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4041                 pbn_panacom2 },
4042         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4043                 PCI_VENDOR_ID_ESDGMBH,
4044                 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
4045                 pbn_b2_4_115200 },
4046         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4047                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4048                 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
4049                 pbn_b2_4_460800 },
4050         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4051                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4052                 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
4053                 pbn_b2_8_460800 },
4054         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4055                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4056                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
4057                 pbn_b2_16_460800 },
4058         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4059                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4060                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
4061                 pbn_b2_16_460800 },
4062         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4063                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4064                 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
4065                 pbn_b2_4_460800 },
4066         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4067                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4068                 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
4069                 pbn_b2_8_460800 },
4070         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4071                 PCI_SUBVENDOR_ID_EXSYS,
4072                 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
4073                 pbn_b2_4_115200 },
4074         /*
4075          * Megawolf Romulus PCI Serial Card, from Mike Hudson
4076          * (Exoray@isys.ca)
4077          */
4078         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
4079                 0x10b5, 0x106a, 0, 0,
4080                 pbn_plx_romulus },
4081         /*
4082          * Quatech cards. These actually have configurable clocks but for
4083          * now we just use the default.
4084          *
4085          * 100 series are RS232, 200 series RS422,
4086          */
4087         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
4088                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4089                 pbn_b1_4_115200 },
4090         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
4091                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4092                 pbn_b1_2_115200 },
4093         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E,
4094                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4095                 pbn_b2_2_115200 },
4096         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200,
4097                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4098                 pbn_b1_2_115200 },
4099         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E,
4100                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4101                 pbn_b2_2_115200 },
4102         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200,
4103                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4104                 pbn_b1_4_115200 },
4105         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
4106                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4107                 pbn_b1_8_115200 },
4108         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
4109                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4110                 pbn_b1_8_115200 },
4111         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100,
4112                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4113                 pbn_b1_4_115200 },
4114         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100,
4115                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4116                 pbn_b1_2_115200 },
4117         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200,
4118                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4119                 pbn_b1_4_115200 },
4120         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200,
4121                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4122                 pbn_b1_2_115200 },
4123         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100,
4124                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4125                 pbn_b2_4_115200 },
4126         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100,
4127                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4128                 pbn_b2_2_115200 },
4129         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100,
4130                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4131                 pbn_b2_1_115200 },
4132         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200,
4133                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4134                 pbn_b2_4_115200 },
4135         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200,
4136                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4137                 pbn_b2_2_115200 },
4138         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200,
4139                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4140                 pbn_b2_1_115200 },
4141         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100,
4142                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4143                 pbn_b0_8_115200 },
4144
4145         {       PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
4146                 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
4147                 0, 0,
4148                 pbn_b0_4_921600 },
4149         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4150                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
4151                 0, 0,
4152                 pbn_b0_4_1152000 },
4153         {       PCI_VENDOR_ID_OXSEMI, 0x9505,
4154                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4155                 pbn_b0_bt_2_921600 },
4156
4157                 /*
4158                  * The below card is a little controversial since it is the
4159                  * subject of a PCI vendor/device ID clash.  (See
4160                  * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
4161                  * For now just used the hex ID 0x950a.
4162                  */
4163         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
4164                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00,
4165                 0, 0, pbn_b0_2_115200 },
4166         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
4167                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30,
4168                 0, 0, pbn_b0_2_115200 },
4169         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
4170                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4171                 pbn_b0_2_1130000 },
4172         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
4173                 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
4174                 pbn_b0_1_921600 },
4175         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4176                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4177                 pbn_b0_4_115200 },
4178         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
4179                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4180                 pbn_b0_bt_2_921600 },
4181         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
4182                 PCI_ANY_ID , PCI_ANY_ID, 0, 0,
4183                 pbn_b2_8_1152000 },
4184
4185         /*
4186          * Oxford Semiconductor Inc. Tornado PCI express device range.
4187          */
4188         {       PCI_VENDOR_ID_OXSEMI, 0xc101,    /* OXPCIe952 1 Legacy UART */
4189                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4190                 pbn_b0_1_4000000 },
4191         {       PCI_VENDOR_ID_OXSEMI, 0xc105,    /* OXPCIe952 1 Legacy UART */
4192                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4193                 pbn_b0_1_4000000 },
4194         {       PCI_VENDOR_ID_OXSEMI, 0xc11b,    /* OXPCIe952 1 Native UART */
4195                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4196                 pbn_oxsemi_1_4000000 },
4197         {       PCI_VENDOR_ID_OXSEMI, 0xc11f,    /* OXPCIe952 1 Native UART */
4198                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4199                 pbn_oxsemi_1_4000000 },
4200         {       PCI_VENDOR_ID_OXSEMI, 0xc120,    /* OXPCIe952 1 Legacy UART */
4201                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4202                 pbn_b0_1_4000000 },
4203         {       PCI_VENDOR_ID_OXSEMI, 0xc124,    /* OXPCIe952 1 Legacy UART */
4204                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4205                 pbn_b0_1_4000000 },
4206         {       PCI_VENDOR_ID_OXSEMI, 0xc138,    /* OXPCIe952 1 Native UART */
4207                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4208                 pbn_oxsemi_1_4000000 },
4209         {       PCI_VENDOR_ID_OXSEMI, 0xc13d,    /* OXPCIe952 1 Native UART */
4210                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4211                 pbn_oxsemi_1_4000000 },
4212         {       PCI_VENDOR_ID_OXSEMI, 0xc140,    /* OXPCIe952 1 Legacy UART */
4213                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4214                 pbn_b0_1_4000000 },
4215         {       PCI_VENDOR_ID_OXSEMI, 0xc141,    /* OXPCIe952 1 Legacy UART */
4216                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4217                 pbn_b0_1_4000000 },
4218         {       PCI_VENDOR_ID_OXSEMI, 0xc144,    /* OXPCIe952 1 Legacy UART */
4219                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4220                 pbn_b0_1_4000000 },
4221         {       PCI_VENDOR_ID_OXSEMI, 0xc145,    /* OXPCIe952 1 Legacy UART */
4222                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4223                 pbn_b0_1_4000000 },
4224         {       PCI_VENDOR_ID_OXSEMI, 0xc158,    /* OXPCIe952 2 Native UART */
4225                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4226                 pbn_oxsemi_2_4000000 },
4227         {       PCI_VENDOR_ID_OXSEMI, 0xc15d,    /* OXPCIe952 2 Native UART */
4228                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4229                 pbn_oxsemi_2_4000000 },
4230         {       PCI_VENDOR_ID_OXSEMI, 0xc208,    /* OXPCIe954 4 Native UART */
4231                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4232                 pbn_oxsemi_4_4000000 },
4233         {       PCI_VENDOR_ID_OXSEMI, 0xc20d,    /* OXPCIe954 4 Native UART */
4234                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4235                 pbn_oxsemi_4_4000000 },
4236         {       PCI_VENDOR_ID_OXSEMI, 0xc308,    /* OXPCIe958 8 Native UART */
4237                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4238                 pbn_oxsemi_8_4000000 },
4239         {       PCI_VENDOR_ID_OXSEMI, 0xc30d,    /* OXPCIe958 8 Native UART */
4240                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4241                 pbn_oxsemi_8_4000000 },
4242         {       PCI_VENDOR_ID_OXSEMI, 0xc40b,    /* OXPCIe200 1 Native UART */
4243                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4244                 pbn_oxsemi_1_4000000 },
4245         {       PCI_VENDOR_ID_OXSEMI, 0xc40f,    /* OXPCIe200 1 Native UART */
4246                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4247                 pbn_oxsemi_1_4000000 },
4248         {       PCI_VENDOR_ID_OXSEMI, 0xc41b,    /* OXPCIe200 1 Native UART */
4249                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4250                 pbn_oxsemi_1_4000000 },
4251         {       PCI_VENDOR_ID_OXSEMI, 0xc41f,    /* OXPCIe200 1 Native UART */
4252                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4253                 pbn_oxsemi_1_4000000 },
4254         {       PCI_VENDOR_ID_OXSEMI, 0xc42b,    /* OXPCIe200 1 Native UART */
4255                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4256                 pbn_oxsemi_1_4000000 },
4257         {       PCI_VENDOR_ID_OXSEMI, 0xc42f,    /* OXPCIe200 1 Native UART */
4258                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4259                 pbn_oxsemi_1_4000000 },
4260         {       PCI_VENDOR_ID_OXSEMI, 0xc43b,    /* OXPCIe200 1 Native UART */
4261                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4262                 pbn_oxsemi_1_4000000 },
4263         {       PCI_VENDOR_ID_OXSEMI, 0xc43f,    /* OXPCIe200 1 Native UART */
4264                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4265                 pbn_oxsemi_1_4000000 },
4266         {       PCI_VENDOR_ID_OXSEMI, 0xc44b,    /* OXPCIe200 1 Native UART */
4267                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4268                 pbn_oxsemi_1_4000000 },
4269         {       PCI_VENDOR_ID_OXSEMI, 0xc44f,    /* OXPCIe200 1 Native UART */
4270                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4271                 pbn_oxsemi_1_4000000 },
4272         {       PCI_VENDOR_ID_OXSEMI, 0xc45b,    /* OXPCIe200 1 Native UART */
4273                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4274                 pbn_oxsemi_1_4000000 },
4275         {       PCI_VENDOR_ID_OXSEMI, 0xc45f,    /* OXPCIe200 1 Native UART */
4276                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4277                 pbn_oxsemi_1_4000000 },
4278         {       PCI_VENDOR_ID_OXSEMI, 0xc46b,    /* OXPCIe200 1 Native UART */
4279                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4280                 pbn_oxsemi_1_4000000 },
4281         {       PCI_VENDOR_ID_OXSEMI, 0xc46f,    /* OXPCIe200 1 Native UART */
4282                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4283                 pbn_oxsemi_1_4000000 },
4284         {       PCI_VENDOR_ID_OXSEMI, 0xc47b,    /* OXPCIe200 1 Native UART */
4285                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4286                 pbn_oxsemi_1_4000000 },
4287         {       PCI_VENDOR_ID_OXSEMI, 0xc47f,    /* OXPCIe200 1 Native UART */
4288                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4289                 pbn_oxsemi_1_4000000 },
4290         {       PCI_VENDOR_ID_OXSEMI, 0xc48b,    /* OXPCIe200 1 Native UART */
4291                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4292                 pbn_oxsemi_1_4000000 },
4293         {       PCI_VENDOR_ID_OXSEMI, 0xc48f,    /* OXPCIe200 1 Native UART */
4294                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4295                 pbn_oxsemi_1_4000000 },
4296         {       PCI_VENDOR_ID_OXSEMI, 0xc49b,    /* OXPCIe200 1 Native UART */
4297                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4298                 pbn_oxsemi_1_4000000 },
4299         {       PCI_VENDOR_ID_OXSEMI, 0xc49f,    /* OXPCIe200 1 Native UART */
4300                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4301                 pbn_oxsemi_1_4000000 },
4302         {       PCI_VENDOR_ID_OXSEMI, 0xc4ab,    /* OXPCIe200 1 Native UART */
4303                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4304                 pbn_oxsemi_1_4000000 },
4305         {       PCI_VENDOR_ID_OXSEMI, 0xc4af,    /* OXPCIe200 1 Native UART */
4306                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4307                 pbn_oxsemi_1_4000000 },
4308         {       PCI_VENDOR_ID_OXSEMI, 0xc4bb,    /* OXPCIe200 1 Native UART */
4309                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4310                 pbn_oxsemi_1_4000000 },
4311         {       PCI_VENDOR_ID_OXSEMI, 0xc4bf,    /* OXPCIe200 1 Native UART */
4312                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4313                 pbn_oxsemi_1_4000000 },
4314         {       PCI_VENDOR_ID_OXSEMI, 0xc4cb,    /* OXPCIe200 1 Native UART */
4315                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4316                 pbn_oxsemi_1_4000000 },
4317         {       PCI_VENDOR_ID_OXSEMI, 0xc4cf,    /* OXPCIe200 1 Native UART */
4318                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4319                 pbn_oxsemi_1_4000000 },
4320         /*
4321          * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
4322          */
4323         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
4324                 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
4325                 pbn_oxsemi_1_4000000 },
4326         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
4327                 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
4328                 pbn_oxsemi_2_4000000 },
4329         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
4330                 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
4331                 pbn_oxsemi_4_4000000 },
4332         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
4333                 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
4334                 pbn_oxsemi_8_4000000 },
4335
4336         /*
4337          * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
4338          */
4339         {       PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
4340                 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
4341                 pbn_oxsemi_2_4000000 },
4342
4343         /*
4344          * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
4345          * from skokodyn@yahoo.com
4346          */
4347         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4348                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
4349                 pbn_sbsxrsio },
4350         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4351                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
4352                 pbn_sbsxrsio },
4353         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4354                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
4355                 pbn_sbsxrsio },
4356         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4357                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
4358                 pbn_sbsxrsio },
4359
4360         /*
4361          * Digitan DS560-558, from jimd@esoft.com
4362          */
4363         {       PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
4364                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4365                 pbn_b1_1_115200 },
4366
4367         /*
4368          * Titan Electronic cards
4369          *  The 400L and 800L have a custom setup quirk.
4370          */
4371         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
4372                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4373                 pbn_b0_1_921600 },
4374         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
4375                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4376                 pbn_b0_2_921600 },
4377         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
4378                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4379                 pbn_b0_4_921600 },
4380         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
4381                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4382                 pbn_b0_4_921600 },
4383         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
4384                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4385                 pbn_b1_1_921600 },
4386         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
4387                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4388                 pbn_b1_bt_2_921600 },
4389         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
4390                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4391                 pbn_b0_bt_4_921600 },
4392         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
4393                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4394                 pbn_b0_bt_8_921600 },
4395         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
4396                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4397                 pbn_b4_bt_2_921600 },
4398         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
4399                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4400                 pbn_b4_bt_4_921600 },
4401         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
4402                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4403                 pbn_b4_bt_8_921600 },
4404         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
4405                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4406                 pbn_b0_4_921600 },
4407         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
4408                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4409                 pbn_b0_4_921600 },
4410         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
4411                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4412                 pbn_b0_4_921600 },
4413         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
4414                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4415                 pbn_oxsemi_1_4000000 },
4416         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
4417                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4418                 pbn_oxsemi_2_4000000 },
4419         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
4420                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4421                 pbn_oxsemi_4_4000000 },
4422         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
4423                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4424                 pbn_oxsemi_8_4000000 },
4425         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
4426                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4427                 pbn_oxsemi_2_4000000 },
4428         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
4429                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4430                 pbn_oxsemi_2_4000000 },
4431         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3,
4432                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4433                 pbn_b0_bt_2_921600 },
4434         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
4435                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4436                 pbn_b0_4_921600 },
4437         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
4438                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4439                 pbn_b0_4_921600 },
4440         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
4441                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4442                 pbn_b0_4_921600 },
4443         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
4444                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4445                 pbn_b0_4_921600 },
4446
4447         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
4448                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4449                 pbn_b2_1_460800 },
4450         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
4451                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4452                 pbn_b2_1_460800 },
4453         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
4454                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4455                 pbn_b2_1_460800 },
4456         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
4457                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4458                 pbn_b2_bt_2_921600 },
4459         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
4460                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4461                 pbn_b2_bt_2_921600 },
4462         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
4463                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4464                 pbn_b2_bt_2_921600 },
4465         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
4466                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4467                 pbn_b2_bt_4_921600 },
4468         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
4469                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4470                 pbn_b2_bt_4_921600 },
4471         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
4472                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4473                 pbn_b2_bt_4_921600 },
4474         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
4475                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4476                 pbn_b0_1_921600 },
4477         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
4478                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4479                 pbn_b0_1_921600 },
4480         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
4481                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4482                 pbn_b0_1_921600 },
4483         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
4484                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4485                 pbn_b0_bt_2_921600 },
4486         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
4487                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4488                 pbn_b0_bt_2_921600 },
4489         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
4490                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4491                 pbn_b0_bt_2_921600 },
4492         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
4493                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4494                 pbn_b0_bt_4_921600 },
4495         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
4496                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4497                 pbn_b0_bt_4_921600 },
4498         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
4499                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4500                 pbn_b0_bt_4_921600 },
4501         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
4502                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4503                 pbn_b0_bt_8_921600 },
4504         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
4505                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4506                 pbn_b0_bt_8_921600 },
4507         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
4508                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4509                 pbn_b0_bt_8_921600 },
4510
4511         /*
4512          * Computone devices submitted by Doug McNash dmcnash@computone.com
4513          */
4514         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4515                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
4516                 0, 0, pbn_computone_4 },
4517         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4518                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
4519                 0, 0, pbn_computone_8 },
4520         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4521                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
4522                 0, 0, pbn_computone_6 },
4523
4524         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
4525                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4526                 pbn_oxsemi },
4527         {       PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
4528                 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
4529                 pbn_b0_bt_1_921600 },
4530
4531         /*
4532          * SUNIX (TIMEDIA)
4533          */
4534         {       PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4535                 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4536                 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xffff00,
4537                 pbn_b0_bt_1_921600 },
4538
4539         {       PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4540                 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4541                 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
4542                 pbn_b0_bt_1_921600 },
4543
4544         /*
4545          * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
4546          */
4547         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
4548                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4549                 pbn_b0_bt_8_115200 },
4550         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
4551                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4552                 pbn_b0_bt_8_115200 },
4553
4554         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
4555                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4556                 pbn_b0_bt_2_115200 },
4557         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
4558                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4559                 pbn_b0_bt_2_115200 },
4560         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
4561                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4562                 pbn_b0_bt_2_115200 },
4563         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
4564                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4565                 pbn_b0_bt_2_115200 },
4566         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
4567                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4568                 pbn_b0_bt_2_115200 },
4569         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
4570                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4571                 pbn_b0_bt_4_460800 },
4572         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
4573                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4574                 pbn_b0_bt_4_460800 },
4575         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
4576                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4577                 pbn_b0_bt_2_460800 },
4578         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
4579                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4580                 pbn_b0_bt_2_460800 },
4581         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
4582                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4583                 pbn_b0_bt_2_460800 },
4584         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
4585                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4586                 pbn_b0_bt_1_115200 },
4587         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
4588                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4589                 pbn_b0_bt_1_460800 },
4590
4591         /*
4592          * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
4593          * Cards are identified by their subsystem vendor IDs, which
4594          * (in hex) match the model number.
4595          *
4596          * Note that JC140x are RS422/485 cards which require ox950
4597          * ACR = 0x10, and as such are not currently fully supported.
4598          */
4599         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4600                 0x1204, 0x0004, 0, 0,
4601                 pbn_b0_4_921600 },
4602         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4603                 0x1208, 0x0004, 0, 0,
4604                 pbn_b0_4_921600 },
4605 /*      {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4606                 0x1402, 0x0002, 0, 0,
4607                 pbn_b0_2_921600 }, */
4608 /*      {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4609                 0x1404, 0x0004, 0, 0,
4610                 pbn_b0_4_921600 }, */
4611         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
4612                 0x1208, 0x0004, 0, 0,
4613                 pbn_b0_4_921600 },
4614
4615         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4616                 0x1204, 0x0004, 0, 0,
4617                 pbn_b0_4_921600 },
4618         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4619                 0x1208, 0x0004, 0, 0,
4620                 pbn_b0_4_921600 },
4621         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
4622                 0x1208, 0x0004, 0, 0,
4623                 pbn_b0_4_921600 },
4624         /*
4625          * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
4626          */
4627         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
4628                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4629                 pbn_b1_1_1382400 },
4630
4631         /*
4632          * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
4633          */
4634         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
4635                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4636                 pbn_b1_1_1382400 },
4637
4638         /*
4639          * RAStel 2 port modem, gerg@moreton.com.au
4640          */
4641         {       PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
4642                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4643                 pbn_b2_bt_2_115200 },
4644
4645         /*
4646          * EKF addition for i960 Boards form EKF with serial port
4647          */
4648         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
4649                 0xE4BF, PCI_ANY_ID, 0, 0,
4650                 pbn_intel_i960 },
4651
4652         /*
4653          * Xircom Cardbus/Ethernet combos
4654          */
4655         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
4656                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4657                 pbn_b0_1_115200 },
4658         /*
4659          * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
4660          */
4661         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
4662                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4663                 pbn_b0_1_115200 },
4664
4665         /*
4666          * Untested PCI modems, sent in from various folks...
4667          */
4668
4669         /*
4670          * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
4671          */
4672         {       PCI_VENDOR_ID_ROCKWELL, 0x1004,
4673                 0x1048, 0x1500, 0, 0,
4674                 pbn_b1_1_115200 },
4675
4676         {       PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
4677                 0xFF00, 0, 0, 0,
4678                 pbn_sgi_ioc3 },
4679
4680         /*
4681          * HP Diva card
4682          */
4683         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
4684                 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
4685                 pbn_b1_1_115200 },
4686         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
4687                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4688                 pbn_b0_5_115200 },
4689         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
4690                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4691                 pbn_b2_1_115200 },
4692
4693         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
4694                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4695                 pbn_b3_2_115200 },
4696         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
4697                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4698                 pbn_b3_4_115200 },
4699         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
4700                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4701                 pbn_b3_8_115200 },
4702
4703         /*
4704          * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
4705          */
4706         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4707                 PCI_ANY_ID, PCI_ANY_ID,
4708                 0,
4709                 0, pbn_exar_XR17C152 },
4710         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4711                 PCI_ANY_ID, PCI_ANY_ID,
4712                 0,
4713                 0, pbn_exar_XR17C154 },
4714         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4715                 PCI_ANY_ID, PCI_ANY_ID,
4716                 0,
4717                 0, pbn_exar_XR17C158 },
4718         /*
4719          * Exar Corp. XR17V35[248] Dual/Quad/Octal PCIe UARTs
4720          */
4721         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V352,
4722                 PCI_ANY_ID, PCI_ANY_ID,
4723                 0,
4724                 0, pbn_exar_XR17V352 },
4725         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V354,
4726                 PCI_ANY_ID, PCI_ANY_ID,
4727                 0,
4728                 0, pbn_exar_XR17V354 },
4729         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V358,
4730                 PCI_ANY_ID, PCI_ANY_ID,
4731                 0,
4732                 0, pbn_exar_XR17V358 },
4733
4734         /*
4735          * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
4736          */
4737         {       PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
4738                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4739                 pbn_b0_1_115200 },
4740         /*
4741          * ITE
4742          */
4743         {       PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
4744                 PCI_ANY_ID, PCI_ANY_ID,
4745                 0, 0,
4746                 pbn_b1_bt_1_115200 },
4747
4748         /*
4749          * IntaShield IS-200
4750          */
4751         {       PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
4752                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,   /* 135a.0811 */
4753                 pbn_b2_2_115200 },
4754         /*
4755          * IntaShield IS-400
4756          */
4757         {       PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
4758                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,    /* 135a.0dc0 */
4759                 pbn_b2_4_115200 },
4760         /*
4761          * Perle PCI-RAS cards
4762          */
4763         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4764                 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
4765                 0, 0, pbn_b2_4_921600 },
4766         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4767                 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
4768                 0, 0, pbn_b2_8_921600 },
4769
4770         /*
4771          * Mainpine series cards: Fairly standard layout but fools
4772          * parts of the autodetect in some cases and uses otherwise
4773          * unmatched communications subclasses in the PCI Express case
4774          */
4775
4776         {       /* RockForceDUO */
4777                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4778                 PCI_VENDOR_ID_MAINPINE, 0x0200,
4779                 0, 0, pbn_b0_2_115200 },
4780         {       /* RockForceQUATRO */
4781                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4782                 PCI_VENDOR_ID_MAINPINE, 0x0300,
4783                 0, 0, pbn_b0_4_115200 },
4784         {       /* RockForceDUO+ */
4785                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4786                 PCI_VENDOR_ID_MAINPINE, 0x0400,
4787                 0, 0, pbn_b0_2_115200 },
4788         {       /* RockForceQUATRO+ */
4789                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4790                 PCI_VENDOR_ID_MAINPINE, 0x0500,
4791                 0, 0, pbn_b0_4_115200 },
4792         {       /* RockForce+ */
4793                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4794                 PCI_VENDOR_ID_MAINPINE, 0x0600,
4795                 0, 0, pbn_b0_2_115200 },
4796         {       /* RockForce+ */
4797                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4798                 PCI_VENDOR_ID_MAINPINE, 0x0700,
4799                 0, 0, pbn_b0_4_115200 },
4800         {       /* RockForceOCTO+ */
4801                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4802                 PCI_VENDOR_ID_MAINPINE, 0x0800,
4803                 0, 0, pbn_b0_8_115200 },
4804         {       /* RockForceDUO+ */
4805                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4806                 PCI_VENDOR_ID_MAINPINE, 0x0C00,
4807                 0, 0, pbn_b0_2_115200 },
4808         {       /* RockForceQUARTRO+ */
4809                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4810                 PCI_VENDOR_ID_MAINPINE, 0x0D00,
4811                 0, 0, pbn_b0_4_115200 },
4812         {       /* RockForceOCTO+ */
4813                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4814                 PCI_VENDOR_ID_MAINPINE, 0x1D00,
4815                 0, 0, pbn_b0_8_115200 },
4816         {       /* RockForceD1 */
4817                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4818                 PCI_VENDOR_ID_MAINPINE, 0x2000,
4819                 0, 0, pbn_b0_1_115200 },
4820         {       /* RockForceF1 */
4821                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4822                 PCI_VENDOR_ID_MAINPINE, 0x2100,
4823                 0, 0, pbn_b0_1_115200 },
4824         {       /* RockForceD2 */
4825                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4826                 PCI_VENDOR_ID_MAINPINE, 0x2200,
4827                 0, 0, pbn_b0_2_115200 },
4828         {       /* RockForceF2 */
4829                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4830                 PCI_VENDOR_ID_MAINPINE, 0x2300,
4831                 0, 0, pbn_b0_2_115200 },
4832         {       /* RockForceD4 */
4833                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4834                 PCI_VENDOR_ID_MAINPINE, 0x2400,
4835                 0, 0, pbn_b0_4_115200 },
4836         {       /* RockForceF4 */
4837                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4838                 PCI_VENDOR_ID_MAINPINE, 0x2500,
4839                 0, 0, pbn_b0_4_115200 },
4840         {       /* RockForceD8 */
4841                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4842                 PCI_VENDOR_ID_MAINPINE, 0x2600,
4843                 0, 0, pbn_b0_8_115200 },
4844         {       /* RockForceF8 */
4845                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4846                 PCI_VENDOR_ID_MAINPINE, 0x2700,
4847                 0, 0, pbn_b0_8_115200 },
4848         {       /* IQ Express D1 */
4849                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4850                 PCI_VENDOR_ID_MAINPINE, 0x3000,
4851                 0, 0, pbn_b0_1_115200 },
4852         {       /* IQ Express F1 */
4853                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4854                 PCI_VENDOR_ID_MAINPINE, 0x3100,
4855                 0, 0, pbn_b0_1_115200 },
4856         {       /* IQ Express D2 */
4857                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4858                 PCI_VENDOR_ID_MAINPINE, 0x3200,
4859                 0, 0, pbn_b0_2_115200 },
4860         {       /* IQ Express F2 */
4861                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4862                 PCI_VENDOR_ID_MAINPINE, 0x3300,
4863                 0, 0, pbn_b0_2_115200 },
4864         {       /* IQ Express D4 */
4865                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4866                 PCI_VENDOR_ID_MAINPINE, 0x3400,
4867                 0, 0, pbn_b0_4_115200 },
4868         {       /* IQ Express F4 */
4869                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4870                 PCI_VENDOR_ID_MAINPINE, 0x3500,
4871                 0, 0, pbn_b0_4_115200 },
4872         {       /* IQ Express D8 */
4873                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4874                 PCI_VENDOR_ID_MAINPINE, 0x3C00,
4875                 0, 0, pbn_b0_8_115200 },
4876         {       /* IQ Express F8 */
4877                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4878                 PCI_VENDOR_ID_MAINPINE, 0x3D00,
4879                 0, 0, pbn_b0_8_115200 },
4880
4881
4882         /*
4883          * PA Semi PA6T-1682M on-chip UART
4884          */
4885         {       PCI_VENDOR_ID_PASEMI, 0xa004,
4886                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4887                 pbn_pasemi_1682M },
4888
4889         /*
4890          * National Instruments
4891          */
4892         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
4893                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4894                 pbn_b1_16_115200 },
4895         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
4896                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4897                 pbn_b1_8_115200 },
4898         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
4899                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4900                 pbn_b1_bt_4_115200 },
4901         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
4902                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4903                 pbn_b1_bt_2_115200 },
4904         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
4905                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4906                 pbn_b1_bt_4_115200 },
4907         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
4908                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4909                 pbn_b1_bt_2_115200 },
4910         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
4911                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4912                 pbn_b1_16_115200 },
4913         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
4914                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4915                 pbn_b1_8_115200 },
4916         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
4917                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4918                 pbn_b1_bt_4_115200 },
4919         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
4920                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4921                 pbn_b1_bt_2_115200 },
4922         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
4923                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4924                 pbn_b1_bt_4_115200 },
4925         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
4926                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4927                 pbn_b1_bt_2_115200 },
4928         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
4929                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4930                 pbn_ni8430_2 },
4931         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
4932                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4933                 pbn_ni8430_2 },
4934         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
4935                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4936                 pbn_ni8430_4 },
4937         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
4938                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4939                 pbn_ni8430_4 },
4940         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
4941                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4942                 pbn_ni8430_8 },
4943         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
4944                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4945                 pbn_ni8430_8 },
4946         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
4947                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4948                 pbn_ni8430_16 },
4949         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
4950                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4951                 pbn_ni8430_16 },
4952         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
4953                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4954                 pbn_ni8430_2 },
4955         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
4956                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4957                 pbn_ni8430_2 },
4958         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
4959                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4960                 pbn_ni8430_4 },
4961         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
4962                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4963                 pbn_ni8430_4 },
4964
4965         /*
4966         * ADDI-DATA GmbH communication cards <info@addi-data.com>
4967         */
4968         {       PCI_VENDOR_ID_ADDIDATA,
4969                 PCI_DEVICE_ID_ADDIDATA_APCI7500,
4970                 PCI_ANY_ID,
4971                 PCI_ANY_ID,
4972                 0,
4973                 0,
4974                 pbn_b0_4_115200 },
4975
4976         {       PCI_VENDOR_ID_ADDIDATA,
4977                 PCI_DEVICE_ID_ADDIDATA_APCI7420,
4978                 PCI_ANY_ID,
4979                 PCI_ANY_ID,
4980                 0,
4981                 0,
4982                 pbn_b0_2_115200 },
4983
4984         {       PCI_VENDOR_ID_ADDIDATA,
4985                 PCI_DEVICE_ID_ADDIDATA_APCI7300,
4986                 PCI_ANY_ID,
4987                 PCI_ANY_ID,
4988                 0,
4989                 0,
4990                 pbn_b0_1_115200 },
4991
4992         {       PCI_VENDOR_ID_AMCC,
4993                 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
4994                 PCI_ANY_ID,
4995                 PCI_ANY_ID,
4996                 0,
4997                 0,
4998                 pbn_b1_8_115200 },
4999
5000         {       PCI_VENDOR_ID_ADDIDATA,
5001                 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
5002                 PCI_ANY_ID,
5003                 PCI_ANY_ID,
5004                 0,
5005                 0,
5006                 pbn_b0_4_115200 },
5007
5008         {       PCI_VENDOR_ID_ADDIDATA,
5009                 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
5010                 PCI_ANY_ID,
5011                 PCI_ANY_ID,
5012                 0,
5013                 0,
5014                 pbn_b0_2_115200 },
5015
5016         {       PCI_VENDOR_ID_ADDIDATA,
5017                 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
5018                 PCI_ANY_ID,
5019                 PCI_ANY_ID,
5020                 0,
5021                 0,
5022                 pbn_b0_1_115200 },
5023
5024         {       PCI_VENDOR_ID_ADDIDATA,
5025                 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
5026                 PCI_ANY_ID,
5027                 PCI_ANY_ID,
5028                 0,
5029                 0,
5030                 pbn_b0_4_115200 },
5031
5032         {       PCI_VENDOR_ID_ADDIDATA,
5033                 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
5034                 PCI_ANY_ID,
5035                 PCI_ANY_ID,
5036                 0,
5037                 0,
5038                 pbn_b0_2_115200 },
5039
5040         {       PCI_VENDOR_ID_ADDIDATA,
5041                 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
5042                 PCI_ANY_ID,
5043                 PCI_ANY_ID,
5044                 0,
5045                 0,
5046                 pbn_b0_1_115200 },
5047
5048         {       PCI_VENDOR_ID_ADDIDATA,
5049                 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
5050                 PCI_ANY_ID,
5051                 PCI_ANY_ID,
5052                 0,
5053                 0,
5054                 pbn_b0_8_115200 },
5055
5056         {       PCI_VENDOR_ID_ADDIDATA,
5057                 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
5058                 PCI_ANY_ID,
5059                 PCI_ANY_ID,
5060                 0,
5061                 0,
5062                 pbn_ADDIDATA_PCIe_4_3906250 },
5063
5064         {       PCI_VENDOR_ID_ADDIDATA,
5065                 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
5066                 PCI_ANY_ID,
5067                 PCI_ANY_ID,
5068                 0,
5069                 0,
5070                 pbn_ADDIDATA_PCIe_2_3906250 },
5071
5072         {       PCI_VENDOR_ID_ADDIDATA,
5073                 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
5074                 PCI_ANY_ID,
5075                 PCI_ANY_ID,
5076                 0,
5077                 0,
5078                 pbn_ADDIDATA_PCIe_1_3906250 },
5079
5080         {       PCI_VENDOR_ID_ADDIDATA,
5081                 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
5082                 PCI_ANY_ID,
5083                 PCI_ANY_ID,
5084                 0,
5085                 0,
5086                 pbn_ADDIDATA_PCIe_8_3906250 },
5087
5088         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
5089                 PCI_VENDOR_ID_IBM, 0x0299,
5090                 0, 0, pbn_b0_bt_2_115200 },
5091
5092         /*
5093          * other NetMos 9835 devices are most likely handled by the
5094          * parport_serial driver, check drivers/parport/parport_serial.c
5095          * before adding them here.
5096          */
5097
5098         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
5099                 0xA000, 0x1000,
5100                 0, 0, pbn_b0_1_115200 },
5101
5102         /* the 9901 is a rebranded 9912 */
5103         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
5104                 0xA000, 0x1000,
5105                 0, 0, pbn_b0_1_115200 },
5106
5107         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
5108                 0xA000, 0x1000,
5109                 0, 0, pbn_b0_1_115200 },
5110
5111         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
5112                 0xA000, 0x1000,
5113                 0, 0, pbn_b0_1_115200 },
5114
5115         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5116                 0xA000, 0x1000,
5117                 0, 0, pbn_b0_1_115200 },
5118
5119         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5120                 0xA000, 0x3002,
5121                 0, 0, pbn_NETMOS9900_2s_115200 },
5122
5123         /*
5124          * Best Connectivity and Rosewill PCI Multi I/O cards
5125          */
5126
5127         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5128                 0xA000, 0x1000,
5129                 0, 0, pbn_b0_1_115200 },
5130
5131         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5132                 0xA000, 0x3002,
5133                 0, 0, pbn_b0_bt_2_115200 },
5134
5135         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5136                 0xA000, 0x3004,
5137                 0, 0, pbn_b0_bt_4_115200 },
5138         /* Intel CE4100 */
5139         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
5140                 PCI_ANY_ID,  PCI_ANY_ID, 0, 0,
5141                 pbn_ce4100_1_115200 },
5142         /* Intel BayTrail */
5143         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART1,
5144                 PCI_ANY_ID,  PCI_ANY_ID,
5145                 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5146                 pbn_byt },
5147         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART2,
5148                 PCI_ANY_ID,  PCI_ANY_ID,
5149                 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5150                 pbn_byt },
5151
5152         /*
5153          * Cronyx Omega PCI
5154          */
5155         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
5156                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5157                 pbn_omegapci },
5158
5159         /*
5160          * Broadcom TruManage
5161          */
5162         {       PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
5163                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5164                 pbn_brcm_trumanage },
5165
5166         /*
5167          * AgeStar as-prs2-009
5168          */
5169         {       PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375,
5170                 PCI_ANY_ID, PCI_ANY_ID,
5171                 0, 0, pbn_b0_bt_2_115200 },
5172
5173         /*
5174          * WCH CH353 series devices: The 2S1P is handled by parport_serial
5175          * so not listed here.
5176          */
5177         {       PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S,
5178                 PCI_ANY_ID, PCI_ANY_ID,
5179                 0, 0, pbn_b0_bt_4_115200 },
5180
5181         {       PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF,
5182                 PCI_ANY_ID, PCI_ANY_ID,
5183                 0, 0, pbn_b0_bt_2_115200 },
5184
5185         {       PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH352_2S,
5186                 PCI_ANY_ID, PCI_ANY_ID,
5187                 0, 0, pbn_b0_bt_2_115200 },
5188
5189         /*
5190          * Commtech, Inc. Fastcom adapters
5191          */
5192         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCI335,
5193                 PCI_ANY_ID, PCI_ANY_ID,
5194                 0,
5195                 0, pbn_b0_2_1152000_200 },
5196         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCI335,
5197                 PCI_ANY_ID, PCI_ANY_ID,
5198                 0,
5199                 0, pbn_b0_4_1152000_200 },
5200         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2324PCI335,
5201                 PCI_ANY_ID, PCI_ANY_ID,
5202                 0,
5203                 0, pbn_b0_4_1152000_200 },
5204         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2328PCI335,
5205                 PCI_ANY_ID, PCI_ANY_ID,
5206                 0,
5207                 0, pbn_b0_8_1152000_200 },
5208         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCIE,
5209                 PCI_ANY_ID, PCI_ANY_ID,
5210                 0,
5211                 0, pbn_exar_XR17V352 },
5212         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCIE,
5213                 PCI_ANY_ID, PCI_ANY_ID,
5214                 0,
5215                 0, pbn_exar_XR17V354 },
5216         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4228PCIE,
5217                 PCI_ANY_ID, PCI_ANY_ID,
5218                 0,
5219                 0, pbn_exar_XR17V358 },
5220
5221         /* Fintek PCI serial cards */
5222         { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 },
5223         { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 },
5224         { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 },
5225
5226         /*
5227          * These entries match devices with class COMMUNICATION_SERIAL,
5228          * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
5229          */
5230         {       PCI_ANY_ID, PCI_ANY_ID,
5231                 PCI_ANY_ID, PCI_ANY_ID,
5232                 PCI_CLASS_COMMUNICATION_SERIAL << 8,
5233                 0xffff00, pbn_default },
5234         {       PCI_ANY_ID, PCI_ANY_ID,
5235                 PCI_ANY_ID, PCI_ANY_ID,
5236                 PCI_CLASS_COMMUNICATION_MODEM << 8,
5237                 0xffff00, pbn_default },
5238         {       PCI_ANY_ID, PCI_ANY_ID,
5239                 PCI_ANY_ID, PCI_ANY_ID,
5240                 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
5241                 0xffff00, pbn_default },
5242         { 0, }
5243 };
5244
5245 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
5246                                                 pci_channel_state_t state)
5247 {
5248         struct serial_private *priv = pci_get_drvdata(dev);
5249
5250         if (state == pci_channel_io_perm_failure)
5251                 return PCI_ERS_RESULT_DISCONNECT;
5252
5253         if (priv)
5254                 pciserial_suspend_ports(priv);
5255
5256         pci_disable_device(dev);
5257
5258         return PCI_ERS_RESULT_NEED_RESET;
5259 }
5260
5261 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
5262 {
5263         int rc;
5264
5265         rc = pci_enable_device(dev);
5266
5267         if (rc)
5268                 return PCI_ERS_RESULT_DISCONNECT;
5269
5270         pci_restore_state(dev);
5271         pci_save_state(dev);
5272
5273         return PCI_ERS_RESULT_RECOVERED;
5274 }
5275
5276 static void serial8250_io_resume(struct pci_dev *dev)
5277 {
5278         struct serial_private *priv = pci_get_drvdata(dev);
5279
5280         if (priv)
5281                 pciserial_resume_ports(priv);
5282 }
5283
5284 static const struct pci_error_handlers serial8250_err_handler = {
5285         .error_detected = serial8250_io_error_detected,
5286         .slot_reset = serial8250_io_slot_reset,
5287         .resume = serial8250_io_resume,
5288 };
5289
5290 static struct pci_driver serial_pci_driver = {
5291         .name           = "serial",
5292         .probe          = pciserial_init_one,
5293         .remove         = pciserial_remove_one,
5294 #ifdef CONFIG_PM
5295         .suspend        = pciserial_suspend_one,
5296         .resume         = pciserial_resume_one,
5297 #endif
5298         .id_table       = serial_pci_tbl,
5299         .err_handler    = &serial8250_err_handler,
5300 };
5301
5302 module_pci_driver(serial_pci_driver);
5303
5304 MODULE_LICENSE("GPL");
5305 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
5306 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);