2 * Probe module for 8250/16550-type PCI serial ports.
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 * Copyright (C) 2001 Russell King, All Rights Reserved.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License.
12 #include <linux/module.h>
13 #include <linux/init.h>
14 #include <linux/pci.h>
15 #include <linux/string.h>
16 #include <linux/kernel.h>
17 #include <linux/slab.h>
18 #include <linux/delay.h>
19 #include <linux/tty.h>
20 #include <linux/serial_reg.h>
21 #include <linux/serial_core.h>
22 #include <linux/8250_pci.h>
23 #include <linux/bitops.h>
25 #include <asm/byteorder.h>
30 #undef SERIAL_DEBUG_PCI
33 * init function returns:
34 * > 0 - number of ports
35 * = 0 - use board->num_ports
38 struct pci_serial_quirk {
43 int (*probe)(struct pci_dev *dev);
44 int (*init)(struct pci_dev *dev);
45 int (*setup)(struct serial_private *,
46 const struct pciserial_board *,
47 struct uart_port *, int);
48 void (*exit)(struct pci_dev *dev);
51 #define PCI_NUM_BAR_RESOURCES 6
53 struct serial_private {
56 void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES];
57 struct pci_serial_quirk *quirk;
61 static int pci_default_setup(struct serial_private*,
62 const struct pciserial_board*, struct uart_port*, int);
64 static void moan_device(const char *str, struct pci_dev *dev)
68 "Please send the output of lspci -vv, this\n"
69 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
70 "manufacturer and name of serial board or\n"
71 "modem board to rmk+serial@arm.linux.org.uk.\n",
72 pci_name(dev), str, dev->vendor, dev->device,
73 dev->subsystem_vendor, dev->subsystem_device);
77 setup_port(struct serial_private *priv, struct uart_port *port,
78 int bar, int offset, int regshift)
80 struct pci_dev *dev = priv->dev;
81 unsigned long base, len;
83 if (bar >= PCI_NUM_BAR_RESOURCES)
86 base = pci_resource_start(dev, bar);
88 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
89 len = pci_resource_len(dev, bar);
91 if (!priv->remapped_bar[bar])
92 priv->remapped_bar[bar] = ioremap_nocache(base, len);
93 if (!priv->remapped_bar[bar])
96 port->iotype = UPIO_MEM;
98 port->mapbase = base + offset;
99 port->membase = priv->remapped_bar[bar] + offset;
100 port->regshift = regshift;
102 port->iotype = UPIO_PORT;
103 port->iobase = base + offset;
105 port->membase = NULL;
112 * ADDI-DATA GmbH communication cards <info@addi-data.com>
114 static int addidata_apci7800_setup(struct serial_private *priv,
115 const struct pciserial_board *board,
116 struct uart_port *port, int idx)
118 unsigned int bar = 0, offset = board->first_offset;
119 bar = FL_GET_BASE(board->flags);
122 offset += idx * board->uart_offset;
123 } else if ((idx >= 2) && (idx < 4)) {
125 offset += ((idx - 2) * board->uart_offset);
126 } else if ((idx >= 4) && (idx < 6)) {
128 offset += ((idx - 4) * board->uart_offset);
129 } else if (idx >= 6) {
131 offset += ((idx - 6) * board->uart_offset);
134 return setup_port(priv, port, bar, offset, board->reg_shift);
138 * AFAVLAB uses a different mixture of BARs and offsets
139 * Not that ugly ;) -- HW
142 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
143 struct uart_port *port, int idx)
145 unsigned int bar, offset = board->first_offset;
147 bar = FL_GET_BASE(board->flags);
152 offset += (idx - 4) * board->uart_offset;
155 return setup_port(priv, port, bar, offset, board->reg_shift);
159 * HP's Remote Management Console. The Diva chip came in several
160 * different versions. N-class, L2000 and A500 have two Diva chips, each
161 * with 3 UARTs (the third UART on the second chip is unused). Superdome
162 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
163 * one Diva chip, but it has been expanded to 5 UARTs.
165 static int pci_hp_diva_init(struct pci_dev *dev)
169 switch (dev->subsystem_device) {
170 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
171 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
172 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
173 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
176 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
179 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
182 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
183 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
192 * HP's Diva chip puts the 4th/5th serial port further out, and
193 * some serial ports are supposed to be hidden on certain models.
196 pci_hp_diva_setup(struct serial_private *priv,
197 const struct pciserial_board *board,
198 struct uart_port *port, int idx)
200 unsigned int offset = board->first_offset;
201 unsigned int bar = FL_GET_BASE(board->flags);
203 switch (priv->dev->subsystem_device) {
204 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
208 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
218 offset += idx * board->uart_offset;
220 return setup_port(priv, port, bar, offset, board->reg_shift);
224 * Added for EKF Intel i960 serial boards
226 static int pci_inteli960ni_init(struct pci_dev *dev)
228 unsigned long oldval;
230 if (!(dev->subsystem_device & 0x1000))
233 /* is firmware started? */
234 pci_read_config_dword(dev, 0x44, (void *)&oldval);
235 if (oldval == 0x00001000L) { /* RESET value */
236 printk(KERN_DEBUG "Local i960 firmware missing");
243 * Some PCI serial cards using the PLX 9050 PCI interface chip require
244 * that the card interrupt be explicitly enabled or disabled. This
245 * seems to be mainly needed on card using the PLX which also use I/O
248 static int pci_plx9050_init(struct pci_dev *dev)
253 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
254 moan_device("no memory in bar 0", dev);
259 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
260 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
263 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
264 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
266 * As the megawolf cards have the int pins active
267 * high, and have 2 UART chips, both ints must be
268 * enabled on the 9050. Also, the UARTS are set in
269 * 16450 mode by default, so we have to enable the
270 * 16C950 'enhanced' mode so that we can use the
275 * enable/disable interrupts
277 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
280 writel(irq_config, p + 0x4c);
283 * Read the register back to ensure that it took effect.
291 static void __devexit pci_plx9050_exit(struct pci_dev *dev)
295 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
301 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
306 * Read the register back to ensure that it took effect.
313 #define NI8420_INT_ENABLE_REG 0x38
314 #define NI8420_INT_ENABLE_BIT 0x2000
316 static void __devexit pci_ni8420_exit(struct pci_dev *dev)
319 unsigned long base, len;
320 unsigned int bar = 0;
322 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
323 moan_device("no memory in bar", dev);
327 base = pci_resource_start(dev, bar);
328 len = pci_resource_len(dev, bar);
329 p = ioremap_nocache(base, len);
333 /* Disable the CPU Interrupt */
334 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
335 p + NI8420_INT_ENABLE_REG);
341 #define MITE_IOWBSR1 0xc4
342 #define MITE_IOWCR1 0xf4
343 #define MITE_LCIMR1 0x08
344 #define MITE_LCIMR2 0x10
346 #define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
348 static void __devexit pci_ni8430_exit(struct pci_dev *dev)
351 unsigned long base, len;
352 unsigned int bar = 0;
354 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
355 moan_device("no memory in bar", dev);
359 base = pci_resource_start(dev, bar);
360 len = pci_resource_len(dev, bar);
361 p = ioremap_nocache(base, len);
365 /* Disable the CPU Interrupt */
366 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
370 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
372 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
373 struct uart_port *port, int idx)
375 unsigned int bar, offset = board->first_offset;
380 /* first four channels map to 0, 0x100, 0x200, 0x300 */
381 offset += idx * board->uart_offset;
382 } else if (idx < 8) {
383 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
384 offset += idx * board->uart_offset + 0xC00;
385 } else /* we have only 8 ports on PMC-OCTALPRO */
388 return setup_port(priv, port, bar, offset, board->reg_shift);
392 * This does initialization for PMC OCTALPRO cards:
393 * maps the device memory, resets the UARTs (needed, bc
394 * if the module is removed and inserted again, the card
395 * is in the sleep mode) and enables global interrupt.
398 /* global control register offset for SBS PMC-OctalPro */
399 #define OCT_REG_CR_OFF 0x500
401 static int sbs_init(struct pci_dev *dev)
405 p = pci_ioremap_bar(dev, 0);
409 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
410 writeb(0x10, p + OCT_REG_CR_OFF);
412 writeb(0x0, p + OCT_REG_CR_OFF);
414 /* Set bit-2 (INTENABLE) of Control Register */
415 writeb(0x4, p + OCT_REG_CR_OFF);
422 * Disables the global interrupt of PMC-OctalPro
425 static void __devexit sbs_exit(struct pci_dev *dev)
429 p = pci_ioremap_bar(dev, 0);
430 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
432 writeb(0, p + OCT_REG_CR_OFF);
437 * SIIG serial cards have an PCI interface chip which also controls
438 * the UART clocking frequency. Each UART can be clocked independently
439 * (except cards equipped with 4 UARTs) and initial clocking settings
440 * are stored in the EEPROM chip. It can cause problems because this
441 * version of serial driver doesn't support differently clocked UART's
442 * on single PCI card. To prevent this, initialization functions set
443 * high frequency clocking for all UART's on given card. It is safe (I
444 * hope) because it doesn't touch EEPROM settings to prevent conflicts
445 * with other OSes (like M$ DOS).
447 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
449 * There is two family of SIIG serial cards with different PCI
450 * interface chip and different configuration methods:
451 * - 10x cards have control registers in IO and/or memory space;
452 * - 20x cards have control registers in standard PCI configuration space.
454 * Note: all 10x cards have PCI device ids 0x10..
455 * all 20x cards have PCI device ids 0x20..
457 * There are also Quartet Serial cards which use Oxford Semiconductor
458 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
460 * Note: some SIIG cards are probed by the parport_serial object.
463 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
464 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
466 static int pci_siig10x_init(struct pci_dev *dev)
471 switch (dev->device & 0xfff8) {
472 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
475 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
478 default: /* 1S1P, 4S */
483 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
487 writew(readw(p + 0x28) & data, p + 0x28);
493 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
494 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
496 static int pci_siig20x_init(struct pci_dev *dev)
500 /* Change clock frequency for the first UART. */
501 pci_read_config_byte(dev, 0x6f, &data);
502 pci_write_config_byte(dev, 0x6f, data & 0xef);
504 /* If this card has 2 UART, we have to do the same with second UART. */
505 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
506 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
507 pci_read_config_byte(dev, 0x73, &data);
508 pci_write_config_byte(dev, 0x73, data & 0xef);
513 static int pci_siig_init(struct pci_dev *dev)
515 unsigned int type = dev->device & 0xff00;
518 return pci_siig10x_init(dev);
519 else if (type == 0x2000)
520 return pci_siig20x_init(dev);
522 moan_device("Unknown SIIG card", dev);
526 static int pci_siig_setup(struct serial_private *priv,
527 const struct pciserial_board *board,
528 struct uart_port *port, int idx)
530 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
534 offset = (idx - 4) * 8;
537 return setup_port(priv, port, bar, offset, 0);
541 * Timedia has an explosion of boards, and to avoid the PCI table from
542 * growing *huge*, we use this function to collapse some 70 entries
543 * in the PCI table into one, for sanity's and compactness's sake.
545 static const unsigned short timedia_single_port[] = {
546 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
549 static const unsigned short timedia_dual_port[] = {
550 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
551 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
552 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
553 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
557 static const unsigned short timedia_quad_port[] = {
558 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
559 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
560 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
564 static const unsigned short timedia_eight_port[] = {
565 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
566 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
569 static const struct timedia_struct {
571 const unsigned short *ids;
573 { 1, timedia_single_port },
574 { 2, timedia_dual_port },
575 { 4, timedia_quad_port },
576 { 8, timedia_eight_port }
580 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of
581 * listing them individually, this driver merely grabs them all with
582 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port,
583 * and should be left free to be claimed by parport_serial instead.
585 static int pci_timedia_probe(struct pci_dev *dev)
588 * Check the third digit of the subdevice ID
589 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
591 if ((dev->subsystem_device & 0x00f0) >= 0x70) {
593 "ignoring Timedia subdevice %04x for parport_serial\n",
594 dev->subsystem_device);
601 static int pci_timedia_init(struct pci_dev *dev)
603 const unsigned short *ids;
606 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
607 ids = timedia_data[i].ids;
608 for (j = 0; ids[j]; j++)
609 if (dev->subsystem_device == ids[j])
610 return timedia_data[i].num;
616 * Timedia/SUNIX uses a mixture of BARs and offsets
617 * Ugh, this is ugly as all hell --- TYT
620 pci_timedia_setup(struct serial_private *priv,
621 const struct pciserial_board *board,
622 struct uart_port *port, int idx)
624 unsigned int bar = 0, offset = board->first_offset;
631 offset = board->uart_offset;
638 offset = board->uart_offset;
647 return setup_port(priv, port, bar, offset, board->reg_shift);
651 * Some Titan cards are also a little weird
654 titan_400l_800l_setup(struct serial_private *priv,
655 const struct pciserial_board *board,
656 struct uart_port *port, int idx)
658 unsigned int bar, offset = board->first_offset;
669 offset = (idx - 2) * board->uart_offset;
672 return setup_port(priv, port, bar, offset, board->reg_shift);
675 static int pci_xircom_init(struct pci_dev *dev)
681 static int pci_ni8420_init(struct pci_dev *dev)
684 unsigned long base, len;
685 unsigned int bar = 0;
687 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
688 moan_device("no memory in bar", dev);
692 base = pci_resource_start(dev, bar);
693 len = pci_resource_len(dev, bar);
694 p = ioremap_nocache(base, len);
698 /* Enable CPU Interrupt */
699 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
700 p + NI8420_INT_ENABLE_REG);
706 #define MITE_IOWBSR1_WSIZE 0xa
707 #define MITE_IOWBSR1_WIN_OFFSET 0x800
708 #define MITE_IOWBSR1_WENAB (1 << 7)
709 #define MITE_LCIMR1_IO_IE_0 (1 << 24)
710 #define MITE_LCIMR2_SET_CPU_IE (1 << 31)
711 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
713 static int pci_ni8430_init(struct pci_dev *dev)
716 unsigned long base, len;
718 unsigned int bar = 0;
720 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
721 moan_device("no memory in bar", dev);
725 base = pci_resource_start(dev, bar);
726 len = pci_resource_len(dev, bar);
727 p = ioremap_nocache(base, len);
731 /* Set device window address and size in BAR0 */
732 device_window = ((base + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
733 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
734 writel(device_window, p + MITE_IOWBSR1);
736 /* Set window access to go to RAMSEL IO address space */
737 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
740 /* Enable IO Bus Interrupt 0 */
741 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
743 /* Enable CPU Interrupt */
744 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
750 /* UART Port Control Register */
751 #define NI8430_PORTCON 0x0f
752 #define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
755 pci_ni8430_setup(struct serial_private *priv,
756 const struct pciserial_board *board,
757 struct uart_port *port, int idx)
760 unsigned long base, len;
761 unsigned int bar, offset = board->first_offset;
763 if (idx >= board->num_ports)
766 bar = FL_GET_BASE(board->flags);
767 offset += idx * board->uart_offset;
769 base = pci_resource_start(priv->dev, bar);
770 len = pci_resource_len(priv->dev, bar);
771 p = ioremap_nocache(base, len);
773 /* enable the transceiver */
774 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
775 p + offset + NI8430_PORTCON);
779 return setup_port(priv, port, bar, offset, board->reg_shift);
782 static int pci_netmos_9900_setup(struct serial_private *priv,
783 const struct pciserial_board *board,
784 struct uart_port *port, int idx)
788 if ((priv->dev->subsystem_device & 0xff00) == 0x3000) {
789 /* netmos apparently orders BARs by datasheet layout, so serial
790 * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
794 return setup_port(priv, port, bar, 0, board->reg_shift);
796 return pci_default_setup(priv, board, port, idx);
800 /* the 99xx series comes with a range of device IDs and a variety
803 * 9900 has varying capabilities and can cascade to sub-controllers
804 * (cascading should be purely internal)
805 * 9904 is hardwired with 4 serial ports
806 * 9912 and 9922 are hardwired with 2 serial ports
808 static int pci_netmos_9900_numports(struct pci_dev *dev)
810 unsigned int c = dev->class;
812 unsigned short sub_serports;
818 } else if ((pi == 0) &&
819 (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
820 /* two possibilities: 0x30ps encodes number of parallel and
821 * serial ports, or 0x1000 indicates *something*. This is not
822 * immediately obvious, since the 2s1p+4s configuration seems
823 * to offer all functionality on functions 0..2, while still
824 * advertising the same function 3 as the 4s+2s1p config.
826 sub_serports = dev->subsystem_device & 0xf;
827 if (sub_serports > 0) {
830 printk(KERN_NOTICE "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
835 moan_device("unknown NetMos/Mostech program interface", dev);
839 static int pci_netmos_init(struct pci_dev *dev)
841 /* subdevice 0x00PS means <P> parallel, <S> serial */
842 unsigned int num_serial = dev->subsystem_device & 0xf;
844 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
845 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
848 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
849 dev->subsystem_device == 0x0299)
852 switch (dev->device) { /* FALLTHROUGH on all */
853 case PCI_DEVICE_ID_NETMOS_9904:
854 case PCI_DEVICE_ID_NETMOS_9912:
855 case PCI_DEVICE_ID_NETMOS_9922:
856 case PCI_DEVICE_ID_NETMOS_9900:
857 num_serial = pci_netmos_9900_numports(dev);
861 if (num_serial == 0 ) {
862 moan_device("unknown NetMos/Mostech device", dev);
873 * These chips are available with optionally one parallel port and up to
874 * two serial ports. Unfortunately they all have the same product id.
876 * Basic configuration is done over a region of 32 I/O ports. The base
877 * ioport is called INTA or INTC, depending on docs/other drivers.
879 * The region of the 32 I/O ports is configured in POSIO0R...
883 #define ITE_887x_MISCR 0x9c
884 #define ITE_887x_INTCBAR 0x78
885 #define ITE_887x_UARTBAR 0x7c
886 #define ITE_887x_PS0BAR 0x10
887 #define ITE_887x_POSIO0 0x60
890 #define ITE_887x_IOSIZE 32
891 /* I/O space size (bits 26-24; 8 bytes = 011b) */
892 #define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
893 /* I/O space size (bits 26-24; 32 bytes = 101b) */
894 #define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
895 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
896 #define ITE_887x_POSIO_SPEED (3 << 29)
897 /* enable IO_Space bit */
898 #define ITE_887x_POSIO_ENABLE (1 << 31)
900 static int pci_ite887x_init(struct pci_dev *dev)
902 /* inta_addr are the configuration addresses of the ITE */
903 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
906 struct resource *iobase = NULL;
907 u32 miscr, uartbar, ioport;
909 /* search for the base-ioport */
911 while (inta_addr[i] && iobase == NULL) {
912 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
914 if (iobase != NULL) {
915 /* write POSIO0R - speed | size | ioport */
916 pci_write_config_dword(dev, ITE_887x_POSIO0,
917 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
918 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
919 /* write INTCBAR - ioport */
920 pci_write_config_dword(dev, ITE_887x_INTCBAR,
922 ret = inb(inta_addr[i]);
924 /* ioport connected */
927 release_region(iobase->start, ITE_887x_IOSIZE);
934 printk(KERN_ERR "ite887x: could not find iobase\n");
938 /* start of undocumented type checking (see parport_pc.c) */
939 type = inb(iobase->start + 0x18) & 0x0f;
942 case 0x2: /* ITE8871 (1P) */
943 case 0xa: /* ITE8875 (1P) */
946 case 0xe: /* ITE8872 (2S1P) */
949 case 0x6: /* ITE8873 (1S) */
952 case 0x8: /* ITE8874 (2S) */
956 moan_device("Unknown ITE887x", dev);
960 /* configure all serial ports */
961 for (i = 0; i < ret; i++) {
962 /* read the I/O port from the device */
963 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
965 ioport &= 0x0000FF00; /* the actual base address */
966 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
967 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
968 ITE_887x_POSIO_IOSIZE_8 | ioport);
970 /* write the ioport to the UARTBAR */
971 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
972 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
973 uartbar |= (ioport << (16 * i)); /* set the ioport */
974 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
976 /* get current config */
977 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
978 /* disable interrupts (UARTx_Routing[3:0]) */
979 miscr &= ~(0xf << (12 - 4 * i));
980 /* activate the UART (UARTx_En) */
981 miscr |= 1 << (23 - i);
982 /* write new config with activated UART */
983 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
987 /* the device has no UARTs if we get here */
988 release_region(iobase->start, ITE_887x_IOSIZE);
994 static void __devexit pci_ite887x_exit(struct pci_dev *dev)
997 /* the ioport is bit 0-15 in POSIO0R */
998 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
1000 release_region(ioport, ITE_887x_IOSIZE);
1004 * Oxford Semiconductor Inc.
1005 * Check that device is part of the Tornado range of devices, then determine
1006 * the number of ports available on the device.
1008 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1011 unsigned long deviceID;
1012 unsigned int number_uarts = 0;
1014 /* OxSemi Tornado devices are all 0xCxxx */
1015 if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1016 (dev->device & 0xF000) != 0xC000)
1019 p = pci_iomap(dev, 0, 5);
1023 deviceID = ioread32(p);
1024 /* Tornado device */
1025 if (deviceID == 0x07000200) {
1026 number_uarts = ioread8(p + 4);
1028 "%d ports detected on Oxford PCI Express device\n",
1031 pci_iounmap(dev, p);
1032 return number_uarts;
1036 pci_default_setup(struct serial_private *priv,
1037 const struct pciserial_board *board,
1038 struct uart_port *port, int idx)
1040 unsigned int bar, offset = board->first_offset, maxnr;
1042 bar = FL_GET_BASE(board->flags);
1043 if (board->flags & FL_BASE_BARS)
1046 offset += idx * board->uart_offset;
1048 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1049 (board->reg_shift + 3);
1051 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1054 return setup_port(priv, port, bar, offset, board->reg_shift);
1058 ce4100_serial_setup(struct serial_private *priv,
1059 const struct pciserial_board *board,
1060 struct uart_port *port, int idx)
1064 ret = setup_port(priv, port, 0, 0, board->reg_shift);
1065 port->iotype = UPIO_MEM32;
1066 port->type = PORT_XSCALE;
1067 port->flags = (port->flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1074 pci_omegapci_setup(struct serial_private *priv,
1075 const struct pciserial_board *board,
1076 struct uart_port *port, int idx)
1078 return setup_port(priv, port, 2, idx * 8, 0);
1081 static int skip_tx_en_setup(struct serial_private *priv,
1082 const struct pciserial_board *board,
1083 struct uart_port *port, int idx)
1085 port->flags |= UPF_NO_TXEN_TEST;
1086 printk(KERN_DEBUG "serial8250: skipping TxEn test for device "
1087 "[%04x:%04x] subsystem [%04x:%04x]\n",
1090 priv->dev->subsystem_vendor,
1091 priv->dev->subsystem_device);
1093 return pci_default_setup(priv, board, port, idx);
1096 static void kt_handle_break(struct uart_port *p)
1098 struct uart_8250_port *up =
1099 container_of(p, struct uart_8250_port, port);
1101 * On receipt of a BI, serial device in Intel ME (Intel
1102 * management engine) needs to have its fifos cleared for sane
1103 * SOL (Serial Over Lan) output.
1105 serial8250_clear_and_reinit_fifos(up);
1108 static unsigned int kt_serial_in(struct uart_port *p, int offset)
1110 struct uart_8250_port *up =
1111 container_of(p, struct uart_8250_port, port);
1115 * When the Intel ME (management engine) gets reset its serial
1116 * port registers could return 0 momentarily. Functions like
1117 * serial8250_console_write, read and save the IER, perform
1118 * some operation and then restore it. In order to avoid
1119 * setting IER register inadvertently to 0, if the value read
1120 * is 0, double check with ier value in uart_8250_port and use
1121 * that instead. up->ier should be the same value as what is
1122 * currently configured.
1124 val = inb(p->iobase + offset);
1125 if (offset == UART_IER) {
1132 static int kt_serial_setup(struct serial_private *priv,
1133 const struct pciserial_board *board,
1134 struct uart_port *port, int idx)
1136 port->flags |= UPF_BUG_THRE;
1137 port->serial_in = kt_serial_in;
1138 port->handle_break = kt_handle_break;
1139 return skip_tx_en_setup(priv, board, port, idx);
1142 static int pci_eg20t_init(struct pci_dev *dev)
1144 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1152 pci_xr17c154_setup(struct serial_private *priv,
1153 const struct pciserial_board *board,
1154 struct uart_port *port, int idx)
1156 port->flags |= UPF_EXAR_EFR;
1157 return pci_default_setup(priv, board, port, idx);
1160 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B
1161 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
1162 #define PCI_DEVICE_ID_OCTPRO 0x0001
1163 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
1164 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
1165 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308
1166 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408
1167 #define PCI_VENDOR_ID_ADVANTECH 0x13fe
1168 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
1169 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
1170 #define PCI_DEVICE_ID_TITAN_200I 0x8028
1171 #define PCI_DEVICE_ID_TITAN_400I 0x8048
1172 #define PCI_DEVICE_ID_TITAN_800I 0x8088
1173 #define PCI_DEVICE_ID_TITAN_800EH 0xA007
1174 #define PCI_DEVICE_ID_TITAN_800EHB 0xA008
1175 #define PCI_DEVICE_ID_TITAN_400EH 0xA009
1176 #define PCI_DEVICE_ID_TITAN_100E 0xA010
1177 #define PCI_DEVICE_ID_TITAN_200E 0xA012
1178 #define PCI_DEVICE_ID_TITAN_400E 0xA013
1179 #define PCI_DEVICE_ID_TITAN_800E 0xA014
1180 #define PCI_DEVICE_ID_TITAN_200EI 0xA016
1181 #define PCI_DEVICE_ID_TITAN_200EISI 0xA017
1182 #define PCI_DEVICE_ID_TITAN_400V3 0xA310
1183 #define PCI_DEVICE_ID_TITAN_410V3 0xA312
1184 #define PCI_DEVICE_ID_TITAN_800V3 0xA314
1185 #define PCI_DEVICE_ID_TITAN_800V3B 0xA315
1186 #define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538
1187 #define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6
1188 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001
1189 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
1191 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1192 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
1195 * Master list of serial port init/setup/exit quirks.
1196 * This does not describe the general nature of the port.
1197 * (ie, baud base, number and location of ports, etc)
1199 * This list is ordered alphabetically by vendor then device.
1200 * Specific entries must come before more generic entries.
1202 static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
1204 * ADDI-DATA GmbH communication cards <info@addi-data.com>
1207 .vendor = PCI_VENDOR_ID_ADDIDATA_OLD,
1208 .device = PCI_DEVICE_ID_ADDIDATA_APCI7800,
1209 .subvendor = PCI_ANY_ID,
1210 .subdevice = PCI_ANY_ID,
1211 .setup = addidata_apci7800_setup,
1214 * AFAVLAB cards - these may be called via parport_serial
1215 * It is not clear whether this applies to all products.
1218 .vendor = PCI_VENDOR_ID_AFAVLAB,
1219 .device = PCI_ANY_ID,
1220 .subvendor = PCI_ANY_ID,
1221 .subdevice = PCI_ANY_ID,
1222 .setup = afavlab_setup,
1228 .vendor = PCI_VENDOR_ID_HP,
1229 .device = PCI_DEVICE_ID_HP_DIVA,
1230 .subvendor = PCI_ANY_ID,
1231 .subdevice = PCI_ANY_ID,
1232 .init = pci_hp_diva_init,
1233 .setup = pci_hp_diva_setup,
1239 .vendor = PCI_VENDOR_ID_INTEL,
1240 .device = PCI_DEVICE_ID_INTEL_80960_RP,
1241 .subvendor = 0xe4bf,
1242 .subdevice = PCI_ANY_ID,
1243 .init = pci_inteli960ni_init,
1244 .setup = pci_default_setup,
1247 .vendor = PCI_VENDOR_ID_INTEL,
1248 .device = PCI_DEVICE_ID_INTEL_8257X_SOL,
1249 .subvendor = PCI_ANY_ID,
1250 .subdevice = PCI_ANY_ID,
1251 .setup = skip_tx_en_setup,
1254 .vendor = PCI_VENDOR_ID_INTEL,
1255 .device = PCI_DEVICE_ID_INTEL_82573L_SOL,
1256 .subvendor = PCI_ANY_ID,
1257 .subdevice = PCI_ANY_ID,
1258 .setup = skip_tx_en_setup,
1261 .vendor = PCI_VENDOR_ID_INTEL,
1262 .device = PCI_DEVICE_ID_INTEL_82573E_SOL,
1263 .subvendor = PCI_ANY_ID,
1264 .subdevice = PCI_ANY_ID,
1265 .setup = skip_tx_en_setup,
1268 .vendor = PCI_VENDOR_ID_INTEL,
1269 .device = PCI_DEVICE_ID_INTEL_CE4100_UART,
1270 .subvendor = PCI_ANY_ID,
1271 .subdevice = PCI_ANY_ID,
1272 .setup = ce4100_serial_setup,
1275 .vendor = PCI_VENDOR_ID_INTEL,
1276 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
1277 .subvendor = PCI_ANY_ID,
1278 .subdevice = PCI_ANY_ID,
1279 .setup = kt_serial_setup,
1285 .vendor = PCI_VENDOR_ID_ITE,
1286 .device = PCI_DEVICE_ID_ITE_8872,
1287 .subvendor = PCI_ANY_ID,
1288 .subdevice = PCI_ANY_ID,
1289 .init = pci_ite887x_init,
1290 .setup = pci_default_setup,
1291 .exit = __devexit_p(pci_ite887x_exit),
1294 * National Instruments
1297 .vendor = PCI_VENDOR_ID_NI,
1298 .device = PCI_DEVICE_ID_NI_PCI23216,
1299 .subvendor = PCI_ANY_ID,
1300 .subdevice = PCI_ANY_ID,
1301 .init = pci_ni8420_init,
1302 .setup = pci_default_setup,
1303 .exit = __devexit_p(pci_ni8420_exit),
1306 .vendor = PCI_VENDOR_ID_NI,
1307 .device = PCI_DEVICE_ID_NI_PCI2328,
1308 .subvendor = PCI_ANY_ID,
1309 .subdevice = PCI_ANY_ID,
1310 .init = pci_ni8420_init,
1311 .setup = pci_default_setup,
1312 .exit = __devexit_p(pci_ni8420_exit),
1315 .vendor = PCI_VENDOR_ID_NI,
1316 .device = PCI_DEVICE_ID_NI_PCI2324,
1317 .subvendor = PCI_ANY_ID,
1318 .subdevice = PCI_ANY_ID,
1319 .init = pci_ni8420_init,
1320 .setup = pci_default_setup,
1321 .exit = __devexit_p(pci_ni8420_exit),
1324 .vendor = PCI_VENDOR_ID_NI,
1325 .device = PCI_DEVICE_ID_NI_PCI2322,
1326 .subvendor = PCI_ANY_ID,
1327 .subdevice = PCI_ANY_ID,
1328 .init = pci_ni8420_init,
1329 .setup = pci_default_setup,
1330 .exit = __devexit_p(pci_ni8420_exit),
1333 .vendor = PCI_VENDOR_ID_NI,
1334 .device = PCI_DEVICE_ID_NI_PCI2324I,
1335 .subvendor = PCI_ANY_ID,
1336 .subdevice = PCI_ANY_ID,
1337 .init = pci_ni8420_init,
1338 .setup = pci_default_setup,
1339 .exit = __devexit_p(pci_ni8420_exit),
1342 .vendor = PCI_VENDOR_ID_NI,
1343 .device = PCI_DEVICE_ID_NI_PCI2322I,
1344 .subvendor = PCI_ANY_ID,
1345 .subdevice = PCI_ANY_ID,
1346 .init = pci_ni8420_init,
1347 .setup = pci_default_setup,
1348 .exit = __devexit_p(pci_ni8420_exit),
1351 .vendor = PCI_VENDOR_ID_NI,
1352 .device = PCI_DEVICE_ID_NI_PXI8420_23216,
1353 .subvendor = PCI_ANY_ID,
1354 .subdevice = PCI_ANY_ID,
1355 .init = pci_ni8420_init,
1356 .setup = pci_default_setup,
1357 .exit = __devexit_p(pci_ni8420_exit),
1360 .vendor = PCI_VENDOR_ID_NI,
1361 .device = PCI_DEVICE_ID_NI_PXI8420_2328,
1362 .subvendor = PCI_ANY_ID,
1363 .subdevice = PCI_ANY_ID,
1364 .init = pci_ni8420_init,
1365 .setup = pci_default_setup,
1366 .exit = __devexit_p(pci_ni8420_exit),
1369 .vendor = PCI_VENDOR_ID_NI,
1370 .device = PCI_DEVICE_ID_NI_PXI8420_2324,
1371 .subvendor = PCI_ANY_ID,
1372 .subdevice = PCI_ANY_ID,
1373 .init = pci_ni8420_init,
1374 .setup = pci_default_setup,
1375 .exit = __devexit_p(pci_ni8420_exit),
1378 .vendor = PCI_VENDOR_ID_NI,
1379 .device = PCI_DEVICE_ID_NI_PXI8420_2322,
1380 .subvendor = PCI_ANY_ID,
1381 .subdevice = PCI_ANY_ID,
1382 .init = pci_ni8420_init,
1383 .setup = pci_default_setup,
1384 .exit = __devexit_p(pci_ni8420_exit),
1387 .vendor = PCI_VENDOR_ID_NI,
1388 .device = PCI_DEVICE_ID_NI_PXI8422_2324,
1389 .subvendor = PCI_ANY_ID,
1390 .subdevice = PCI_ANY_ID,
1391 .init = pci_ni8420_init,
1392 .setup = pci_default_setup,
1393 .exit = __devexit_p(pci_ni8420_exit),
1396 .vendor = PCI_VENDOR_ID_NI,
1397 .device = PCI_DEVICE_ID_NI_PXI8422_2322,
1398 .subvendor = PCI_ANY_ID,
1399 .subdevice = PCI_ANY_ID,
1400 .init = pci_ni8420_init,
1401 .setup = pci_default_setup,
1402 .exit = __devexit_p(pci_ni8420_exit),
1405 .vendor = PCI_VENDOR_ID_NI,
1406 .device = PCI_ANY_ID,
1407 .subvendor = PCI_ANY_ID,
1408 .subdevice = PCI_ANY_ID,
1409 .init = pci_ni8430_init,
1410 .setup = pci_ni8430_setup,
1411 .exit = __devexit_p(pci_ni8430_exit),
1417 .vendor = PCI_VENDOR_ID_PANACOM,
1418 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
1419 .subvendor = PCI_ANY_ID,
1420 .subdevice = PCI_ANY_ID,
1421 .init = pci_plx9050_init,
1422 .setup = pci_default_setup,
1423 .exit = __devexit_p(pci_plx9050_exit),
1426 .vendor = PCI_VENDOR_ID_PANACOM,
1427 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
1428 .subvendor = PCI_ANY_ID,
1429 .subdevice = PCI_ANY_ID,
1430 .init = pci_plx9050_init,
1431 .setup = pci_default_setup,
1432 .exit = __devexit_p(pci_plx9050_exit),
1438 .vendor = PCI_VENDOR_ID_PLX,
1439 .device = PCI_DEVICE_ID_PLX_9030,
1440 .subvendor = PCI_SUBVENDOR_ID_PERLE,
1441 .subdevice = PCI_ANY_ID,
1442 .setup = pci_default_setup,
1445 .vendor = PCI_VENDOR_ID_PLX,
1446 .device = PCI_DEVICE_ID_PLX_9050,
1447 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
1448 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
1449 .init = pci_plx9050_init,
1450 .setup = pci_default_setup,
1451 .exit = __devexit_p(pci_plx9050_exit),
1454 .vendor = PCI_VENDOR_ID_PLX,
1455 .device = PCI_DEVICE_ID_PLX_9050,
1456 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
1457 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
1458 .init = pci_plx9050_init,
1459 .setup = pci_default_setup,
1460 .exit = __devexit_p(pci_plx9050_exit),
1463 .vendor = PCI_VENDOR_ID_PLX,
1464 .device = PCI_DEVICE_ID_PLX_9050,
1465 .subvendor = PCI_VENDOR_ID_PLX,
1466 .subdevice = PCI_SUBDEVICE_ID_UNKNOWN_0x1584,
1467 .init = pci_plx9050_init,
1468 .setup = pci_default_setup,
1469 .exit = __devexit_p(pci_plx9050_exit),
1472 .vendor = PCI_VENDOR_ID_PLX,
1473 .device = PCI_DEVICE_ID_PLX_ROMULUS,
1474 .subvendor = PCI_VENDOR_ID_PLX,
1475 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
1476 .init = pci_plx9050_init,
1477 .setup = pci_default_setup,
1478 .exit = __devexit_p(pci_plx9050_exit),
1481 * SBS Technologies, Inc., PMC-OCTALPRO 232
1484 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1485 .device = PCI_DEVICE_ID_OCTPRO,
1486 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1487 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
1490 .exit = __devexit_p(sbs_exit),
1493 * SBS Technologies, Inc., PMC-OCTALPRO 422
1496 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1497 .device = PCI_DEVICE_ID_OCTPRO,
1498 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1499 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
1502 .exit = __devexit_p(sbs_exit),
1505 * SBS Technologies, Inc., P-Octal 232
1508 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1509 .device = PCI_DEVICE_ID_OCTPRO,
1510 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1511 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
1514 .exit = __devexit_p(sbs_exit),
1517 * SBS Technologies, Inc., P-Octal 422
1520 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1521 .device = PCI_DEVICE_ID_OCTPRO,
1522 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1523 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
1526 .exit = __devexit_p(sbs_exit),
1529 * SIIG cards - these may be called via parport_serial
1532 .vendor = PCI_VENDOR_ID_SIIG,
1533 .device = PCI_ANY_ID,
1534 .subvendor = PCI_ANY_ID,
1535 .subdevice = PCI_ANY_ID,
1536 .init = pci_siig_init,
1537 .setup = pci_siig_setup,
1543 .vendor = PCI_VENDOR_ID_TITAN,
1544 .device = PCI_DEVICE_ID_TITAN_400L,
1545 .subvendor = PCI_ANY_ID,
1546 .subdevice = PCI_ANY_ID,
1547 .setup = titan_400l_800l_setup,
1550 .vendor = PCI_VENDOR_ID_TITAN,
1551 .device = PCI_DEVICE_ID_TITAN_800L,
1552 .subvendor = PCI_ANY_ID,
1553 .subdevice = PCI_ANY_ID,
1554 .setup = titan_400l_800l_setup,
1560 .vendor = PCI_VENDOR_ID_TIMEDIA,
1561 .device = PCI_DEVICE_ID_TIMEDIA_1889,
1562 .subvendor = PCI_VENDOR_ID_TIMEDIA,
1563 .subdevice = PCI_ANY_ID,
1564 .probe = pci_timedia_probe,
1565 .init = pci_timedia_init,
1566 .setup = pci_timedia_setup,
1569 .vendor = PCI_VENDOR_ID_TIMEDIA,
1570 .device = PCI_ANY_ID,
1571 .subvendor = PCI_ANY_ID,
1572 .subdevice = PCI_ANY_ID,
1573 .setup = pci_timedia_setup,
1579 .vendor = PCI_VENDOR_ID_EXAR,
1580 .device = PCI_DEVICE_ID_EXAR_XR17C152,
1581 .subvendor = PCI_ANY_ID,
1582 .subdevice = PCI_ANY_ID,
1583 .setup = pci_xr17c154_setup,
1586 .vendor = PCI_VENDOR_ID_EXAR,
1587 .device = PCI_DEVICE_ID_EXAR_XR17C154,
1588 .subvendor = PCI_ANY_ID,
1589 .subdevice = PCI_ANY_ID,
1590 .setup = pci_xr17c154_setup,
1593 .vendor = PCI_VENDOR_ID_EXAR,
1594 .device = PCI_DEVICE_ID_EXAR_XR17C158,
1595 .subvendor = PCI_ANY_ID,
1596 .subdevice = PCI_ANY_ID,
1597 .setup = pci_xr17c154_setup,
1603 .vendor = PCI_VENDOR_ID_XIRCOM,
1604 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
1605 .subvendor = PCI_ANY_ID,
1606 .subdevice = PCI_ANY_ID,
1607 .init = pci_xircom_init,
1608 .setup = pci_default_setup,
1611 * Netmos cards - these may be called via parport_serial
1614 .vendor = PCI_VENDOR_ID_NETMOS,
1615 .device = PCI_ANY_ID,
1616 .subvendor = PCI_ANY_ID,
1617 .subdevice = PCI_ANY_ID,
1618 .init = pci_netmos_init,
1619 .setup = pci_netmos_9900_setup,
1622 * For Oxford Semiconductor Tornado based devices
1625 .vendor = PCI_VENDOR_ID_OXSEMI,
1626 .device = PCI_ANY_ID,
1627 .subvendor = PCI_ANY_ID,
1628 .subdevice = PCI_ANY_ID,
1629 .init = pci_oxsemi_tornado_init,
1630 .setup = pci_default_setup,
1633 .vendor = PCI_VENDOR_ID_MAINPINE,
1634 .device = PCI_ANY_ID,
1635 .subvendor = PCI_ANY_ID,
1636 .subdevice = PCI_ANY_ID,
1637 .init = pci_oxsemi_tornado_init,
1638 .setup = pci_default_setup,
1641 .vendor = PCI_VENDOR_ID_DIGI,
1642 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM,
1643 .subvendor = PCI_SUBVENDOR_ID_IBM,
1644 .subdevice = PCI_ANY_ID,
1645 .init = pci_oxsemi_tornado_init,
1646 .setup = pci_default_setup,
1649 .vendor = PCI_VENDOR_ID_INTEL,
1651 .subvendor = PCI_ANY_ID,
1652 .subdevice = PCI_ANY_ID,
1653 .init = pci_eg20t_init,
1654 .setup = pci_default_setup,
1657 .vendor = PCI_VENDOR_ID_INTEL,
1659 .subvendor = PCI_ANY_ID,
1660 .subdevice = PCI_ANY_ID,
1661 .init = pci_eg20t_init,
1662 .setup = pci_default_setup,
1665 .vendor = PCI_VENDOR_ID_INTEL,
1667 .subvendor = PCI_ANY_ID,
1668 .subdevice = PCI_ANY_ID,
1669 .init = pci_eg20t_init,
1670 .setup = pci_default_setup,
1673 .vendor = PCI_VENDOR_ID_INTEL,
1675 .subvendor = PCI_ANY_ID,
1676 .subdevice = PCI_ANY_ID,
1677 .init = pci_eg20t_init,
1678 .setup = pci_default_setup,
1683 .subvendor = PCI_ANY_ID,
1684 .subdevice = PCI_ANY_ID,
1685 .init = pci_eg20t_init,
1686 .setup = pci_default_setup,
1691 .subvendor = PCI_ANY_ID,
1692 .subdevice = PCI_ANY_ID,
1693 .init = pci_eg20t_init,
1694 .setup = pci_default_setup,
1699 .subvendor = PCI_ANY_ID,
1700 .subdevice = PCI_ANY_ID,
1701 .init = pci_eg20t_init,
1702 .setup = pci_default_setup,
1707 .subvendor = PCI_ANY_ID,
1708 .subdevice = PCI_ANY_ID,
1709 .init = pci_eg20t_init,
1710 .setup = pci_default_setup,
1715 .subvendor = PCI_ANY_ID,
1716 .subdevice = PCI_ANY_ID,
1717 .init = pci_eg20t_init,
1718 .setup = pci_default_setup,
1721 * Cronyx Omega PCI (PLX-chip based)
1724 .vendor = PCI_VENDOR_ID_PLX,
1725 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
1726 .subvendor = PCI_ANY_ID,
1727 .subdevice = PCI_ANY_ID,
1728 .setup = pci_omegapci_setup,
1731 * Default "match everything" terminator entry
1734 .vendor = PCI_ANY_ID,
1735 .device = PCI_ANY_ID,
1736 .subvendor = PCI_ANY_ID,
1737 .subdevice = PCI_ANY_ID,
1738 .setup = pci_default_setup,
1742 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
1744 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
1747 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
1749 struct pci_serial_quirk *quirk;
1751 for (quirk = pci_serial_quirks; ; quirk++)
1752 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
1753 quirk_id_matches(quirk->device, dev->device) &&
1754 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
1755 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
1760 static inline int get_pci_irq(struct pci_dev *dev,
1761 const struct pciserial_board *board)
1763 if (board->flags & FL_NOIRQ)
1770 * This is the configuration table for all of the PCI serial boards
1771 * which we support. It is directly indexed by the pci_board_num_t enum
1772 * value, which is encoded in the pci_device_id PCI probe table's
1773 * driver_data member.
1775 * The makeup of these names are:
1776 * pbn_bn{_bt}_n_baud{_offsetinhex}
1778 * bn = PCI BAR number
1779 * bt = Index using PCI BARs
1780 * n = number of serial ports
1782 * offsetinhex = offset for each sequential port (in hex)
1784 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
1786 * Please note: in theory if n = 1, _bt infix should make no difference.
1787 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
1789 enum pci_board_num_t {
1809 pbn_b0_2_1843200_200,
1810 pbn_b0_4_1843200_200,
1811 pbn_b0_8_1843200_200,
1885 * Board-specific versions.
1893 pbn_oxsemi_1_4000000,
1894 pbn_oxsemi_2_4000000,
1895 pbn_oxsemi_4_4000000,
1896 pbn_oxsemi_8_4000000,
1906 pbn_exar_ibm_saturn,
1912 pbn_ADDIDATA_PCIe_1_3906250,
1913 pbn_ADDIDATA_PCIe_2_3906250,
1914 pbn_ADDIDATA_PCIe_4_3906250,
1915 pbn_ADDIDATA_PCIe_8_3906250,
1916 pbn_ce4100_1_115200,
1918 pbn_NETMOS9900_2s_115200,
1922 * uart_offset - the space between channels
1923 * reg_shift - describes how the UART registers are mapped
1924 * to PCI memory by the card.
1925 * For example IER register on SBS, Inc. PMC-OctPro is located at
1926 * offset 0x10 from the UART base, while UART_IER is defined as 1
1927 * in include/linux/serial_reg.h,
1928 * see first lines of serial_in() and serial_out() in 8250.c
1931 static struct pciserial_board pci_boards[] __devinitdata = {
1935 .base_baud = 115200,
1938 [pbn_b0_1_115200] = {
1941 .base_baud = 115200,
1944 [pbn_b0_2_115200] = {
1947 .base_baud = 115200,
1950 [pbn_b0_4_115200] = {
1953 .base_baud = 115200,
1956 [pbn_b0_5_115200] = {
1959 .base_baud = 115200,
1962 [pbn_b0_8_115200] = {
1965 .base_baud = 115200,
1968 [pbn_b0_1_921600] = {
1971 .base_baud = 921600,
1974 [pbn_b0_2_921600] = {
1977 .base_baud = 921600,
1980 [pbn_b0_4_921600] = {
1983 .base_baud = 921600,
1987 [pbn_b0_2_1130000] = {
1990 .base_baud = 1130000,
1994 [pbn_b0_4_1152000] = {
1997 .base_baud = 1152000,
2001 [pbn_b0_2_1843200] = {
2004 .base_baud = 1843200,
2007 [pbn_b0_4_1843200] = {
2010 .base_baud = 1843200,
2014 [pbn_b0_2_1843200_200] = {
2017 .base_baud = 1843200,
2018 .uart_offset = 0x200,
2020 [pbn_b0_4_1843200_200] = {
2023 .base_baud = 1843200,
2024 .uart_offset = 0x200,
2026 [pbn_b0_8_1843200_200] = {
2029 .base_baud = 1843200,
2030 .uart_offset = 0x200,
2032 [pbn_b0_1_4000000] = {
2035 .base_baud = 4000000,
2039 [pbn_b0_bt_1_115200] = {
2040 .flags = FL_BASE0|FL_BASE_BARS,
2042 .base_baud = 115200,
2045 [pbn_b0_bt_2_115200] = {
2046 .flags = FL_BASE0|FL_BASE_BARS,
2048 .base_baud = 115200,
2051 [pbn_b0_bt_4_115200] = {
2052 .flags = FL_BASE0|FL_BASE_BARS,
2054 .base_baud = 115200,
2057 [pbn_b0_bt_8_115200] = {
2058 .flags = FL_BASE0|FL_BASE_BARS,
2060 .base_baud = 115200,
2064 [pbn_b0_bt_1_460800] = {
2065 .flags = FL_BASE0|FL_BASE_BARS,
2067 .base_baud = 460800,
2070 [pbn_b0_bt_2_460800] = {
2071 .flags = FL_BASE0|FL_BASE_BARS,
2073 .base_baud = 460800,
2076 [pbn_b0_bt_4_460800] = {
2077 .flags = FL_BASE0|FL_BASE_BARS,
2079 .base_baud = 460800,
2083 [pbn_b0_bt_1_921600] = {
2084 .flags = FL_BASE0|FL_BASE_BARS,
2086 .base_baud = 921600,
2089 [pbn_b0_bt_2_921600] = {
2090 .flags = FL_BASE0|FL_BASE_BARS,
2092 .base_baud = 921600,
2095 [pbn_b0_bt_4_921600] = {
2096 .flags = FL_BASE0|FL_BASE_BARS,
2098 .base_baud = 921600,
2101 [pbn_b0_bt_8_921600] = {
2102 .flags = FL_BASE0|FL_BASE_BARS,
2104 .base_baud = 921600,
2108 [pbn_b1_1_115200] = {
2111 .base_baud = 115200,
2114 [pbn_b1_2_115200] = {
2117 .base_baud = 115200,
2120 [pbn_b1_4_115200] = {
2123 .base_baud = 115200,
2126 [pbn_b1_8_115200] = {
2129 .base_baud = 115200,
2132 [pbn_b1_16_115200] = {
2135 .base_baud = 115200,
2139 [pbn_b1_1_921600] = {
2142 .base_baud = 921600,
2145 [pbn_b1_2_921600] = {
2148 .base_baud = 921600,
2151 [pbn_b1_4_921600] = {
2154 .base_baud = 921600,
2157 [pbn_b1_8_921600] = {
2160 .base_baud = 921600,
2163 [pbn_b1_2_1250000] = {
2166 .base_baud = 1250000,
2170 [pbn_b1_bt_1_115200] = {
2171 .flags = FL_BASE1|FL_BASE_BARS,
2173 .base_baud = 115200,
2176 [pbn_b1_bt_2_115200] = {
2177 .flags = FL_BASE1|FL_BASE_BARS,
2179 .base_baud = 115200,
2182 [pbn_b1_bt_4_115200] = {
2183 .flags = FL_BASE1|FL_BASE_BARS,
2185 .base_baud = 115200,
2189 [pbn_b1_bt_2_921600] = {
2190 .flags = FL_BASE1|FL_BASE_BARS,
2192 .base_baud = 921600,
2196 [pbn_b1_1_1382400] = {
2199 .base_baud = 1382400,
2202 [pbn_b1_2_1382400] = {
2205 .base_baud = 1382400,
2208 [pbn_b1_4_1382400] = {
2211 .base_baud = 1382400,
2214 [pbn_b1_8_1382400] = {
2217 .base_baud = 1382400,
2221 [pbn_b2_1_115200] = {
2224 .base_baud = 115200,
2227 [pbn_b2_2_115200] = {
2230 .base_baud = 115200,
2233 [pbn_b2_4_115200] = {
2236 .base_baud = 115200,
2239 [pbn_b2_8_115200] = {
2242 .base_baud = 115200,
2246 [pbn_b2_1_460800] = {
2249 .base_baud = 460800,
2252 [pbn_b2_4_460800] = {
2255 .base_baud = 460800,
2258 [pbn_b2_8_460800] = {
2261 .base_baud = 460800,
2264 [pbn_b2_16_460800] = {
2267 .base_baud = 460800,
2271 [pbn_b2_1_921600] = {
2274 .base_baud = 921600,
2277 [pbn_b2_4_921600] = {
2280 .base_baud = 921600,
2283 [pbn_b2_8_921600] = {
2286 .base_baud = 921600,
2290 [pbn_b2_8_1152000] = {
2293 .base_baud = 1152000,
2297 [pbn_b2_bt_1_115200] = {
2298 .flags = FL_BASE2|FL_BASE_BARS,
2300 .base_baud = 115200,
2303 [pbn_b2_bt_2_115200] = {
2304 .flags = FL_BASE2|FL_BASE_BARS,
2306 .base_baud = 115200,
2309 [pbn_b2_bt_4_115200] = {
2310 .flags = FL_BASE2|FL_BASE_BARS,
2312 .base_baud = 115200,
2316 [pbn_b2_bt_2_921600] = {
2317 .flags = FL_BASE2|FL_BASE_BARS,
2319 .base_baud = 921600,
2322 [pbn_b2_bt_4_921600] = {
2323 .flags = FL_BASE2|FL_BASE_BARS,
2325 .base_baud = 921600,
2329 [pbn_b3_2_115200] = {
2332 .base_baud = 115200,
2335 [pbn_b3_4_115200] = {
2338 .base_baud = 115200,
2341 [pbn_b3_8_115200] = {
2344 .base_baud = 115200,
2348 [pbn_b4_bt_2_921600] = {
2351 .base_baud = 921600,
2354 [pbn_b4_bt_4_921600] = {
2357 .base_baud = 921600,
2360 [pbn_b4_bt_8_921600] = {
2363 .base_baud = 921600,
2368 * Entries following this are board-specific.
2377 .base_baud = 921600,
2378 .uart_offset = 0x400,
2382 .flags = FL_BASE2|FL_BASE_BARS,
2384 .base_baud = 921600,
2385 .uart_offset = 0x400,
2389 .flags = FL_BASE2|FL_BASE_BARS,
2391 .base_baud = 921600,
2392 .uart_offset = 0x400,
2396 [pbn_exsys_4055] = {
2399 .base_baud = 115200,
2403 /* I think this entry is broken - the first_offset looks wrong --rmk */
2404 [pbn_plx_romulus] = {
2407 .base_baud = 921600,
2408 .uart_offset = 8 << 2,
2410 .first_offset = 0x03,
2414 * This board uses the size of PCI Base region 0 to
2415 * signal now many ports are available
2418 .flags = FL_BASE0|FL_REGION_SZ_CAP,
2420 .base_baud = 115200,
2423 [pbn_oxsemi_1_4000000] = {
2426 .base_baud = 4000000,
2427 .uart_offset = 0x200,
2428 .first_offset = 0x1000,
2430 [pbn_oxsemi_2_4000000] = {
2433 .base_baud = 4000000,
2434 .uart_offset = 0x200,
2435 .first_offset = 0x1000,
2437 [pbn_oxsemi_4_4000000] = {
2440 .base_baud = 4000000,
2441 .uart_offset = 0x200,
2442 .first_offset = 0x1000,
2444 [pbn_oxsemi_8_4000000] = {
2447 .base_baud = 4000000,
2448 .uart_offset = 0x200,
2449 .first_offset = 0x1000,
2454 * EKF addition for i960 Boards form EKF with serial port.
2457 [pbn_intel_i960] = {
2460 .base_baud = 921600,
2461 .uart_offset = 8 << 2,
2463 .first_offset = 0x10000,
2466 .flags = FL_BASE0|FL_NOIRQ,
2468 .base_baud = 458333,
2471 .first_offset = 0x20178,
2475 * Computone - uses IOMEM.
2477 [pbn_computone_4] = {
2480 .base_baud = 921600,
2481 .uart_offset = 0x40,
2483 .first_offset = 0x200,
2485 [pbn_computone_6] = {
2488 .base_baud = 921600,
2489 .uart_offset = 0x40,
2491 .first_offset = 0x200,
2493 [pbn_computone_8] = {
2496 .base_baud = 921600,
2497 .uart_offset = 0x40,
2499 .first_offset = 0x200,
2504 .base_baud = 460800,
2509 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
2510 * Only basic 16550A support.
2511 * XR17C15[24] are not tested, but they should work.
2513 [pbn_exar_XR17C152] = {
2516 .base_baud = 921600,
2517 .uart_offset = 0x200,
2519 [pbn_exar_XR17C154] = {
2522 .base_baud = 921600,
2523 .uart_offset = 0x200,
2525 [pbn_exar_XR17C158] = {
2528 .base_baud = 921600,
2529 .uart_offset = 0x200,
2531 [pbn_exar_ibm_saturn] = {
2534 .base_baud = 921600,
2535 .uart_offset = 0x200,
2539 * PA Semi PWRficient PA6T-1682M on-chip UART
2541 [pbn_pasemi_1682M] = {
2544 .base_baud = 8333333,
2547 * National Instruments 843x
2552 .base_baud = 3686400,
2553 .uart_offset = 0x10,
2554 .first_offset = 0x800,
2559 .base_baud = 3686400,
2560 .uart_offset = 0x10,
2561 .first_offset = 0x800,
2566 .base_baud = 3686400,
2567 .uart_offset = 0x10,
2568 .first_offset = 0x800,
2573 .base_baud = 3686400,
2574 .uart_offset = 0x10,
2575 .first_offset = 0x800,
2578 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
2580 [pbn_ADDIDATA_PCIe_1_3906250] = {
2583 .base_baud = 3906250,
2584 .uart_offset = 0x200,
2585 .first_offset = 0x1000,
2587 [pbn_ADDIDATA_PCIe_2_3906250] = {
2590 .base_baud = 3906250,
2591 .uart_offset = 0x200,
2592 .first_offset = 0x1000,
2594 [pbn_ADDIDATA_PCIe_4_3906250] = {
2597 .base_baud = 3906250,
2598 .uart_offset = 0x200,
2599 .first_offset = 0x1000,
2601 [pbn_ADDIDATA_PCIe_8_3906250] = {
2604 .base_baud = 3906250,
2605 .uart_offset = 0x200,
2606 .first_offset = 0x1000,
2608 [pbn_ce4100_1_115200] = {
2611 .base_baud = 921600,
2617 .base_baud = 115200,
2618 .uart_offset = 0x200,
2620 [pbn_NETMOS9900_2s_115200] = {
2623 .base_baud = 115200,
2627 static const struct pci_device_id softmodem_blacklist[] = {
2628 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
2629 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
2630 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
2634 * Given a complete unknown PCI device, try to use some heuristics to
2635 * guess what the configuration might be, based on the pitiful PCI
2636 * serial specs. Returns 0 on success, 1 on failure.
2638 static int __devinit
2639 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
2641 const struct pci_device_id *blacklist;
2642 int num_iomem, num_port, first_port = -1, i;
2645 * If it is not a communications device or the programming
2646 * interface is greater than 6, give up.
2648 * (Should we try to make guesses for multiport serial devices
2651 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
2652 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
2653 (dev->class & 0xff) > 6)
2657 * Do not access blacklisted devices that are known not to
2658 * feature serial ports.
2660 for (blacklist = softmodem_blacklist;
2661 blacklist < softmodem_blacklist + ARRAY_SIZE(softmodem_blacklist);
2663 if (dev->vendor == blacklist->vendor &&
2664 dev->device == blacklist->device)
2668 num_iomem = num_port = 0;
2669 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2670 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
2672 if (first_port == -1)
2675 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
2680 * If there is 1 or 0 iomem regions, and exactly one port,
2681 * use it. We guess the number of ports based on the IO
2684 if (num_iomem <= 1 && num_port == 1) {
2685 board->flags = first_port;
2686 board->num_ports = pci_resource_len(dev, first_port) / 8;
2691 * Now guess if we've got a board which indexes by BARs.
2692 * Each IO BAR should be 8 bytes, and they should follow
2697 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2698 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
2699 pci_resource_len(dev, i) == 8 &&
2700 (first_port == -1 || (first_port + num_port) == i)) {
2702 if (first_port == -1)
2708 board->flags = first_port | FL_BASE_BARS;
2709 board->num_ports = num_port;
2717 serial_pci_matches(const struct pciserial_board *board,
2718 const struct pciserial_board *guessed)
2721 board->num_ports == guessed->num_ports &&
2722 board->base_baud == guessed->base_baud &&
2723 board->uart_offset == guessed->uart_offset &&
2724 board->reg_shift == guessed->reg_shift &&
2725 board->first_offset == guessed->first_offset;
2728 struct serial_private *
2729 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
2731 struct uart_port serial_port;
2732 struct serial_private *priv;
2733 struct pci_serial_quirk *quirk;
2734 int rc, nr_ports, i;
2736 nr_ports = board->num_ports;
2739 * Find an init and setup quirks.
2741 quirk = find_quirk(dev);
2744 * Run the new-style initialization function.
2745 * The initialization function returns:
2747 * 0 - use board->num_ports
2748 * >0 - number of ports
2751 rc = quirk->init(dev);
2760 priv = kzalloc(sizeof(struct serial_private) +
2761 sizeof(unsigned int) * nr_ports,
2764 priv = ERR_PTR(-ENOMEM);
2769 priv->quirk = quirk;
2771 memset(&serial_port, 0, sizeof(struct uart_port));
2772 serial_port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
2773 serial_port.uartclk = board->base_baud * 16;
2774 serial_port.irq = get_pci_irq(dev, board);
2775 serial_port.dev = &dev->dev;
2777 for (i = 0; i < nr_ports; i++) {
2778 if (quirk->setup(priv, board, &serial_port, i))
2781 #ifdef SERIAL_DEBUG_PCI
2782 printk(KERN_DEBUG "Setup PCI port: port %lx, irq %d, type %d\n",
2783 serial_port.iobase, serial_port.irq, serial_port.iotype);
2786 priv->line[i] = serial8250_register_port(&serial_port);
2787 if (priv->line[i] < 0) {
2788 printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
2801 EXPORT_SYMBOL_GPL(pciserial_init_ports);
2803 void pciserial_remove_ports(struct serial_private *priv)
2805 struct pci_serial_quirk *quirk;
2808 for (i = 0; i < priv->nr; i++)
2809 serial8250_unregister_port(priv->line[i]);
2811 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2812 if (priv->remapped_bar[i])
2813 iounmap(priv->remapped_bar[i]);
2814 priv->remapped_bar[i] = NULL;
2818 * Find the exit quirks.
2820 quirk = find_quirk(priv->dev);
2822 quirk->exit(priv->dev);
2826 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
2828 void pciserial_suspend_ports(struct serial_private *priv)
2832 for (i = 0; i < priv->nr; i++)
2833 if (priv->line[i] >= 0)
2834 serial8250_suspend_port(priv->line[i]);
2837 * Ensure that every init quirk is properly torn down
2839 if (priv->quirk->exit)
2840 priv->quirk->exit(priv->dev);
2842 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
2844 void pciserial_resume_ports(struct serial_private *priv)
2849 * Ensure that the board is correctly configured.
2851 if (priv->quirk->init)
2852 priv->quirk->init(priv->dev);
2854 for (i = 0; i < priv->nr; i++)
2855 if (priv->line[i] >= 0)
2856 serial8250_resume_port(priv->line[i]);
2858 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
2861 * Probe one serial board. Unfortunately, there is no rhyme nor reason
2862 * to the arrangement of serial ports on a PCI card.
2864 static int __devinit
2865 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
2867 struct pci_serial_quirk *quirk;
2868 struct serial_private *priv;
2869 const struct pciserial_board *board;
2870 struct pciserial_board tmp;
2873 quirk = find_quirk(dev);
2875 rc = quirk->probe(dev);
2880 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
2881 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
2886 board = &pci_boards[ent->driver_data];
2888 rc = pci_enable_device(dev);
2889 pci_save_state(dev);
2893 if (ent->driver_data == pbn_default) {
2895 * Use a copy of the pci_board entry for this;
2896 * avoid changing entries in the table.
2898 memcpy(&tmp, board, sizeof(struct pciserial_board));
2902 * We matched one of our class entries. Try to
2903 * determine the parameters of this board.
2905 rc = serial_pci_guess_board(dev, &tmp);
2910 * We matched an explicit entry. If we are able to
2911 * detect this boards settings with our heuristic,
2912 * then we no longer need this entry.
2914 memcpy(&tmp, &pci_boards[pbn_default],
2915 sizeof(struct pciserial_board));
2916 rc = serial_pci_guess_board(dev, &tmp);
2917 if (rc == 0 && serial_pci_matches(board, &tmp))
2918 moan_device("Redundant entry in serial pci_table.",
2922 priv = pciserial_init_ports(dev, board);
2923 if (!IS_ERR(priv)) {
2924 pci_set_drvdata(dev, priv);
2931 pci_disable_device(dev);
2935 static void __devexit pciserial_remove_one(struct pci_dev *dev)
2937 struct serial_private *priv = pci_get_drvdata(dev);
2939 pci_set_drvdata(dev, NULL);
2941 pciserial_remove_ports(priv);
2943 pci_disable_device(dev);
2947 static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
2949 struct serial_private *priv = pci_get_drvdata(dev);
2952 pciserial_suspend_ports(priv);
2954 pci_save_state(dev);
2955 pci_set_power_state(dev, pci_choose_state(dev, state));
2959 static int pciserial_resume_one(struct pci_dev *dev)
2962 struct serial_private *priv = pci_get_drvdata(dev);
2964 pci_set_power_state(dev, PCI_D0);
2965 pci_restore_state(dev);
2969 * The device may have been disabled. Re-enable it.
2971 err = pci_enable_device(dev);
2972 /* FIXME: We cannot simply error out here */
2974 printk(KERN_ERR "pciserial: Unable to re-enable ports, trying to continue.\n");
2975 pciserial_resume_ports(priv);
2981 static struct pci_device_id serial_pci_tbl[] = {
2982 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
2983 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
2984 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
2986 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2987 PCI_SUBVENDOR_ID_CONNECT_TECH,
2988 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2990 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2991 PCI_SUBVENDOR_ID_CONNECT_TECH,
2992 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2994 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2995 PCI_SUBVENDOR_ID_CONNECT_TECH,
2996 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2998 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2999 PCI_SUBVENDOR_ID_CONNECT_TECH,
3000 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
3002 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3003 PCI_SUBVENDOR_ID_CONNECT_TECH,
3004 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
3006 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3007 PCI_SUBVENDOR_ID_CONNECT_TECH,
3008 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
3010 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3011 PCI_SUBVENDOR_ID_CONNECT_TECH,
3012 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
3014 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3015 PCI_SUBVENDOR_ID_CONNECT_TECH,
3016 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
3018 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3019 PCI_SUBVENDOR_ID_CONNECT_TECH,
3020 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
3022 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3023 PCI_SUBVENDOR_ID_CONNECT_TECH,
3024 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
3026 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3027 PCI_SUBVENDOR_ID_CONNECT_TECH,
3028 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
3030 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3031 PCI_SUBVENDOR_ID_CONNECT_TECH,
3032 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
3034 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3035 PCI_SUBVENDOR_ID_CONNECT_TECH,
3036 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
3038 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3039 PCI_SUBVENDOR_ID_CONNECT_TECH,
3040 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
3042 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3043 PCI_SUBVENDOR_ID_CONNECT_TECH,
3044 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
3046 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3047 PCI_SUBVENDOR_ID_CONNECT_TECH,
3048 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
3050 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3051 PCI_SUBVENDOR_ID_CONNECT_TECH,
3052 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
3054 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3055 PCI_VENDOR_ID_AFAVLAB,
3056 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
3058 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3059 PCI_SUBVENDOR_ID_CONNECT_TECH,
3060 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
3061 pbn_b0_2_1843200_200 },
3062 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3063 PCI_SUBVENDOR_ID_CONNECT_TECH,
3064 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
3065 pbn_b0_4_1843200_200 },
3066 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3067 PCI_SUBVENDOR_ID_CONNECT_TECH,
3068 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
3069 pbn_b0_8_1843200_200 },
3070 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3071 PCI_SUBVENDOR_ID_CONNECT_TECH,
3072 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
3073 pbn_b0_2_1843200_200 },
3074 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3075 PCI_SUBVENDOR_ID_CONNECT_TECH,
3076 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
3077 pbn_b0_4_1843200_200 },
3078 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3079 PCI_SUBVENDOR_ID_CONNECT_TECH,
3080 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
3081 pbn_b0_8_1843200_200 },
3082 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3083 PCI_SUBVENDOR_ID_CONNECT_TECH,
3084 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
3085 pbn_b0_2_1843200_200 },
3086 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3087 PCI_SUBVENDOR_ID_CONNECT_TECH,
3088 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
3089 pbn_b0_4_1843200_200 },
3090 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3091 PCI_SUBVENDOR_ID_CONNECT_TECH,
3092 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
3093 pbn_b0_8_1843200_200 },
3094 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3095 PCI_SUBVENDOR_ID_CONNECT_TECH,
3096 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
3097 pbn_b0_2_1843200_200 },
3098 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3099 PCI_SUBVENDOR_ID_CONNECT_TECH,
3100 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
3101 pbn_b0_4_1843200_200 },
3102 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3103 PCI_SUBVENDOR_ID_CONNECT_TECH,
3104 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
3105 pbn_b0_8_1843200_200 },
3106 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3107 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT,
3108 0, 0, pbn_exar_ibm_saturn },
3110 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
3111 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3112 pbn_b2_bt_1_115200 },
3113 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
3114 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3115 pbn_b2_bt_2_115200 },
3116 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
3117 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3118 pbn_b2_bt_4_115200 },
3119 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
3120 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3121 pbn_b2_bt_2_115200 },
3122 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
3123 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3124 pbn_b2_bt_4_115200 },
3125 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
3126 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3128 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
3129 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3131 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
3132 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3135 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
3136 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3137 pbn_b2_bt_2_115200 },
3138 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
3139 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3140 pbn_b2_bt_2_921600 },
3142 * VScom SPCOM800, from sl@s.pl
3144 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
3145 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3147 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
3148 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3150 /* Unknown card - subdevice 0x1584 */
3151 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3153 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
3155 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3156 PCI_SUBVENDOR_ID_KEYSPAN,
3157 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
3159 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
3160 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3162 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
3163 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3165 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3166 PCI_VENDOR_ID_ESDGMBH,
3167 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
3169 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3170 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3171 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
3173 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3174 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3175 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
3177 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3178 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3179 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
3181 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3182 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3183 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
3185 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3186 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
3187 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
3189 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3190 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
3191 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
3193 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3194 PCI_SUBVENDOR_ID_EXSYS,
3195 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
3198 * Megawolf Romulus PCI Serial Card, from Mike Hudson
3201 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
3202 0x10b5, 0x106a, 0, 0,
3204 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
3205 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3207 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
3208 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3210 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
3211 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3213 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
3214 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3216 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
3217 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
3220 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3221 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
3224 { PCI_VENDOR_ID_OXSEMI, 0x9505,
3225 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3226 pbn_b0_bt_2_921600 },
3229 * The below card is a little controversial since it is the
3230 * subject of a PCI vendor/device ID clash. (See
3231 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
3232 * For now just used the hex ID 0x950a.
3234 { PCI_VENDOR_ID_OXSEMI, 0x950a,
3235 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_SERIAL, 0, 0,
3237 { PCI_VENDOR_ID_OXSEMI, 0x950a,
3238 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3240 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
3241 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
3243 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3244 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3246 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
3247 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3248 pbn_b0_bt_2_921600 },
3249 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
3250 PCI_ANY_ID , PCI_ANY_ID, 0, 0,
3254 * Oxford Semiconductor Inc. Tornado PCI express device range.
3256 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
3257 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3259 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
3260 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3262 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
3263 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3264 pbn_oxsemi_1_4000000 },
3265 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
3266 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3267 pbn_oxsemi_1_4000000 },
3268 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
3269 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3271 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
3272 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3274 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
3275 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3276 pbn_oxsemi_1_4000000 },
3277 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
3278 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3279 pbn_oxsemi_1_4000000 },
3280 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
3281 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3283 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
3284 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3286 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
3287 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3289 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
3290 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3292 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
3293 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3294 pbn_oxsemi_2_4000000 },
3295 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
3296 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3297 pbn_oxsemi_2_4000000 },
3298 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
3299 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3300 pbn_oxsemi_4_4000000 },
3301 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
3302 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3303 pbn_oxsemi_4_4000000 },
3304 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
3305 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3306 pbn_oxsemi_8_4000000 },
3307 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
3308 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3309 pbn_oxsemi_8_4000000 },
3310 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
3311 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3312 pbn_oxsemi_1_4000000 },
3313 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
3314 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3315 pbn_oxsemi_1_4000000 },
3316 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
3317 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3318 pbn_oxsemi_1_4000000 },
3319 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
3320 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3321 pbn_oxsemi_1_4000000 },
3322 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
3323 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3324 pbn_oxsemi_1_4000000 },
3325 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
3326 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3327 pbn_oxsemi_1_4000000 },
3328 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
3329 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3330 pbn_oxsemi_1_4000000 },
3331 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
3332 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3333 pbn_oxsemi_1_4000000 },
3334 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
3335 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3336 pbn_oxsemi_1_4000000 },
3337 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
3338 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3339 pbn_oxsemi_1_4000000 },
3340 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
3341 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3342 pbn_oxsemi_1_4000000 },
3343 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
3344 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3345 pbn_oxsemi_1_4000000 },
3346 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
3347 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3348 pbn_oxsemi_1_4000000 },
3349 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
3350 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3351 pbn_oxsemi_1_4000000 },
3352 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
3353 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3354 pbn_oxsemi_1_4000000 },
3355 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
3356 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3357 pbn_oxsemi_1_4000000 },
3358 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
3359 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3360 pbn_oxsemi_1_4000000 },
3361 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
3362 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3363 pbn_oxsemi_1_4000000 },
3364 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
3365 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3366 pbn_oxsemi_1_4000000 },
3367 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
3368 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3369 pbn_oxsemi_1_4000000 },
3370 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
3371 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3372 pbn_oxsemi_1_4000000 },
3373 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
3374 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3375 pbn_oxsemi_1_4000000 },
3376 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
3377 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3378 pbn_oxsemi_1_4000000 },
3379 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
3380 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3381 pbn_oxsemi_1_4000000 },
3382 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
3383 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3384 pbn_oxsemi_1_4000000 },
3385 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
3386 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3387 pbn_oxsemi_1_4000000 },
3389 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
3391 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
3392 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
3393 pbn_oxsemi_1_4000000 },
3394 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
3395 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
3396 pbn_oxsemi_2_4000000 },
3397 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
3398 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
3399 pbn_oxsemi_4_4000000 },
3400 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
3401 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
3402 pbn_oxsemi_8_4000000 },
3405 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
3407 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
3408 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
3409 pbn_oxsemi_2_4000000 },
3412 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
3413 * from skokodyn@yahoo.com
3415 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3416 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
3418 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3419 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
3421 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3422 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
3424 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3425 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
3429 * Digitan DS560-558, from jimd@esoft.com
3431 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
3432 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3436 * Titan Electronic cards
3437 * The 400L and 800L have a custom setup quirk.
3439 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
3440 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3442 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
3443 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3445 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
3446 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3448 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
3449 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3451 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
3452 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3454 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
3455 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3456 pbn_b1_bt_2_921600 },
3457 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
3458 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3459 pbn_b0_bt_4_921600 },
3460 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
3461 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3462 pbn_b0_bt_8_921600 },
3463 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
3464 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3465 pbn_b4_bt_2_921600 },
3466 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
3467 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3468 pbn_b4_bt_4_921600 },
3469 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
3470 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3471 pbn_b4_bt_8_921600 },
3472 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
3473 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3475 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
3476 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3478 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
3479 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3481 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
3482 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3483 pbn_oxsemi_1_4000000 },
3484 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
3485 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3486 pbn_oxsemi_2_4000000 },
3487 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
3488 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3489 pbn_oxsemi_4_4000000 },
3490 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
3491 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3492 pbn_oxsemi_8_4000000 },
3493 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
3494 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3495 pbn_oxsemi_2_4000000 },
3496 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
3497 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3498 pbn_oxsemi_2_4000000 },
3499 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
3500 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3502 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
3503 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3505 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
3506 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3508 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
3509 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3512 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
3513 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3515 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
3516 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3518 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
3519 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3521 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
3522 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3523 pbn_b2_bt_2_921600 },
3524 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
3525 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3526 pbn_b2_bt_2_921600 },
3527 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
3528 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3529 pbn_b2_bt_2_921600 },
3530 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
3531 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3532 pbn_b2_bt_4_921600 },
3533 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
3534 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3535 pbn_b2_bt_4_921600 },
3536 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
3537 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3538 pbn_b2_bt_4_921600 },
3539 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
3540 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3542 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
3543 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3545 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
3546 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3548 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
3549 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3550 pbn_b0_bt_2_921600 },
3551 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
3552 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3553 pbn_b0_bt_2_921600 },
3554 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
3555 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3556 pbn_b0_bt_2_921600 },
3557 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
3558 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3559 pbn_b0_bt_4_921600 },
3560 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
3561 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3562 pbn_b0_bt_4_921600 },
3563 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
3564 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3565 pbn_b0_bt_4_921600 },
3566 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
3567 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3568 pbn_b0_bt_8_921600 },
3569 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
3570 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3571 pbn_b0_bt_8_921600 },
3572 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
3573 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3574 pbn_b0_bt_8_921600 },
3577 * Computone devices submitted by Doug McNash dmcnash@computone.com
3579 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3580 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
3581 0, 0, pbn_computone_4 },
3582 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3583 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
3584 0, 0, pbn_computone_8 },
3585 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3586 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
3587 0, 0, pbn_computone_6 },
3589 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
3590 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3592 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
3593 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
3594 pbn_b0_bt_1_921600 },
3597 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
3599 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
3600 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3601 pbn_b0_bt_8_115200 },
3602 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
3603 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3604 pbn_b0_bt_8_115200 },
3606 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
3607 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3608 pbn_b0_bt_2_115200 },
3609 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
3610 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3611 pbn_b0_bt_2_115200 },
3612 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
3613 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3614 pbn_b0_bt_2_115200 },
3615 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
3616 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3617 pbn_b0_bt_2_115200 },
3618 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
3619 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3620 pbn_b0_bt_2_115200 },
3621 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
3622 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3623 pbn_b0_bt_4_460800 },
3624 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
3625 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3626 pbn_b0_bt_4_460800 },
3627 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
3628 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3629 pbn_b0_bt_2_460800 },
3630 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
3631 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3632 pbn_b0_bt_2_460800 },
3633 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
3634 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3635 pbn_b0_bt_2_460800 },
3636 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
3637 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3638 pbn_b0_bt_1_115200 },
3639 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
3640 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3641 pbn_b0_bt_1_460800 },
3644 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
3645 * Cards are identified by their subsystem vendor IDs, which
3646 * (in hex) match the model number.
3648 * Note that JC140x are RS422/485 cards which require ox950
3649 * ACR = 0x10, and as such are not currently fully supported.
3651 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3652 0x1204, 0x0004, 0, 0,
3654 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3655 0x1208, 0x0004, 0, 0,
3657 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3658 0x1402, 0x0002, 0, 0,
3659 pbn_b0_2_921600 }, */
3660 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3661 0x1404, 0x0004, 0, 0,
3662 pbn_b0_4_921600 }, */
3663 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
3664 0x1208, 0x0004, 0, 0,
3667 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
3668 0x1204, 0x0004, 0, 0,
3670 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
3671 0x1208, 0x0004, 0, 0,
3673 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
3674 0x1208, 0x0004, 0, 0,
3677 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
3679 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
3680 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3684 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
3686 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
3687 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3691 * RAStel 2 port modem, gerg@moreton.com.au
3693 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
3694 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3695 pbn_b2_bt_2_115200 },
3698 * EKF addition for i960 Boards form EKF with serial port
3700 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
3701 0xE4BF, PCI_ANY_ID, 0, 0,
3705 * Xircom Cardbus/Ethernet combos
3707 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
3708 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3711 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
3713 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
3714 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3718 * Untested PCI modems, sent in from various folks...
3722 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
3724 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
3725 0x1048, 0x1500, 0, 0,
3728 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
3735 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
3736 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
3738 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
3739 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3741 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
3742 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3745 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
3746 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3748 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
3749 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3751 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
3752 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3756 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3758 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3759 PCI_ANY_ID, PCI_ANY_ID,
3761 0, pbn_exar_XR17C152 },
3762 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3763 PCI_ANY_ID, PCI_ANY_ID,
3765 0, pbn_exar_XR17C154 },
3766 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3767 PCI_ANY_ID, PCI_ANY_ID,
3769 0, pbn_exar_XR17C158 },
3772 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
3774 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
3775 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3780 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
3781 PCI_ANY_ID, PCI_ANY_ID,
3783 pbn_b1_bt_1_115200 },
3788 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
3789 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
3794 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
3795 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
3798 * Perle PCI-RAS cards
3800 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3801 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
3802 0, 0, pbn_b2_4_921600 },
3803 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3804 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
3805 0, 0, pbn_b2_8_921600 },
3808 * Mainpine series cards: Fairly standard layout but fools
3809 * parts of the autodetect in some cases and uses otherwise
3810 * unmatched communications subclasses in the PCI Express case
3813 { /* RockForceDUO */
3814 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3815 PCI_VENDOR_ID_MAINPINE, 0x0200,
3816 0, 0, pbn_b0_2_115200 },
3817 { /* RockForceQUATRO */
3818 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3819 PCI_VENDOR_ID_MAINPINE, 0x0300,
3820 0, 0, pbn_b0_4_115200 },
3821 { /* RockForceDUO+ */
3822 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3823 PCI_VENDOR_ID_MAINPINE, 0x0400,
3824 0, 0, pbn_b0_2_115200 },
3825 { /* RockForceQUATRO+ */
3826 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3827 PCI_VENDOR_ID_MAINPINE, 0x0500,
3828 0, 0, pbn_b0_4_115200 },
3830 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3831 PCI_VENDOR_ID_MAINPINE, 0x0600,
3832 0, 0, pbn_b0_2_115200 },
3834 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3835 PCI_VENDOR_ID_MAINPINE, 0x0700,
3836 0, 0, pbn_b0_4_115200 },
3837 { /* RockForceOCTO+ */
3838 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3839 PCI_VENDOR_ID_MAINPINE, 0x0800,
3840 0, 0, pbn_b0_8_115200 },
3841 { /* RockForceDUO+ */
3842 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3843 PCI_VENDOR_ID_MAINPINE, 0x0C00,
3844 0, 0, pbn_b0_2_115200 },
3845 { /* RockForceQUARTRO+ */
3846 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3847 PCI_VENDOR_ID_MAINPINE, 0x0D00,
3848 0, 0, pbn_b0_4_115200 },
3849 { /* RockForceOCTO+ */
3850 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3851 PCI_VENDOR_ID_MAINPINE, 0x1D00,
3852 0, 0, pbn_b0_8_115200 },
3854 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3855 PCI_VENDOR_ID_MAINPINE, 0x2000,
3856 0, 0, pbn_b0_1_115200 },
3858 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3859 PCI_VENDOR_ID_MAINPINE, 0x2100,
3860 0, 0, pbn_b0_1_115200 },
3862 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3863 PCI_VENDOR_ID_MAINPINE, 0x2200,
3864 0, 0, pbn_b0_2_115200 },
3866 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3867 PCI_VENDOR_ID_MAINPINE, 0x2300,
3868 0, 0, pbn_b0_2_115200 },
3870 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3871 PCI_VENDOR_ID_MAINPINE, 0x2400,
3872 0, 0, pbn_b0_4_115200 },
3874 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3875 PCI_VENDOR_ID_MAINPINE, 0x2500,
3876 0, 0, pbn_b0_4_115200 },
3878 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3879 PCI_VENDOR_ID_MAINPINE, 0x2600,
3880 0, 0, pbn_b0_8_115200 },
3882 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3883 PCI_VENDOR_ID_MAINPINE, 0x2700,
3884 0, 0, pbn_b0_8_115200 },
3885 { /* IQ Express D1 */
3886 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3887 PCI_VENDOR_ID_MAINPINE, 0x3000,
3888 0, 0, pbn_b0_1_115200 },
3889 { /* IQ Express F1 */
3890 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3891 PCI_VENDOR_ID_MAINPINE, 0x3100,
3892 0, 0, pbn_b0_1_115200 },
3893 { /* IQ Express D2 */
3894 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3895 PCI_VENDOR_ID_MAINPINE, 0x3200,
3896 0, 0, pbn_b0_2_115200 },
3897 { /* IQ Express F2 */
3898 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3899 PCI_VENDOR_ID_MAINPINE, 0x3300,
3900 0, 0, pbn_b0_2_115200 },
3901 { /* IQ Express D4 */
3902 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3903 PCI_VENDOR_ID_MAINPINE, 0x3400,
3904 0, 0, pbn_b0_4_115200 },
3905 { /* IQ Express F4 */
3906 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3907 PCI_VENDOR_ID_MAINPINE, 0x3500,
3908 0, 0, pbn_b0_4_115200 },
3909 { /* IQ Express D8 */
3910 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3911 PCI_VENDOR_ID_MAINPINE, 0x3C00,
3912 0, 0, pbn_b0_8_115200 },
3913 { /* IQ Express F8 */
3914 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3915 PCI_VENDOR_ID_MAINPINE, 0x3D00,
3916 0, 0, pbn_b0_8_115200 },
3920 * PA Semi PA6T-1682M on-chip UART
3922 { PCI_VENDOR_ID_PASEMI, 0xa004,
3923 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3927 * National Instruments
3929 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
3930 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3932 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
3933 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3935 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
3936 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3937 pbn_b1_bt_4_115200 },
3938 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
3939 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3940 pbn_b1_bt_2_115200 },
3941 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
3942 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3943 pbn_b1_bt_4_115200 },
3944 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
3945 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3946 pbn_b1_bt_2_115200 },
3947 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
3948 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3950 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
3951 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3953 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
3954 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3955 pbn_b1_bt_4_115200 },
3956 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
3957 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3958 pbn_b1_bt_2_115200 },
3959 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
3960 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3961 pbn_b1_bt_4_115200 },
3962 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
3963 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3964 pbn_b1_bt_2_115200 },
3965 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
3966 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3968 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
3969 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3971 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
3972 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3974 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
3975 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3977 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
3978 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3980 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
3981 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3983 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
3984 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3986 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
3987 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3989 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
3990 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3992 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
3993 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3995 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
3996 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3998 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
3999 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4003 * ADDI-DATA GmbH communication cards <info@addi-data.com>
4005 { PCI_VENDOR_ID_ADDIDATA,
4006 PCI_DEVICE_ID_ADDIDATA_APCI7500,
4013 { PCI_VENDOR_ID_ADDIDATA,
4014 PCI_DEVICE_ID_ADDIDATA_APCI7420,
4021 { PCI_VENDOR_ID_ADDIDATA,
4022 PCI_DEVICE_ID_ADDIDATA_APCI7300,
4029 { PCI_VENDOR_ID_ADDIDATA_OLD,
4030 PCI_DEVICE_ID_ADDIDATA_APCI7800,
4037 { PCI_VENDOR_ID_ADDIDATA,
4038 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
4045 { PCI_VENDOR_ID_ADDIDATA,
4046 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
4053 { PCI_VENDOR_ID_ADDIDATA,
4054 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
4061 { PCI_VENDOR_ID_ADDIDATA,
4062 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
4069 { PCI_VENDOR_ID_ADDIDATA,
4070 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
4077 { PCI_VENDOR_ID_ADDIDATA,
4078 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
4085 { PCI_VENDOR_ID_ADDIDATA,
4086 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
4093 { PCI_VENDOR_ID_ADDIDATA,
4094 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
4099 pbn_ADDIDATA_PCIe_4_3906250 },
4101 { PCI_VENDOR_ID_ADDIDATA,
4102 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
4107 pbn_ADDIDATA_PCIe_2_3906250 },
4109 { PCI_VENDOR_ID_ADDIDATA,
4110 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
4115 pbn_ADDIDATA_PCIe_1_3906250 },
4117 { PCI_VENDOR_ID_ADDIDATA,
4118 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
4123 pbn_ADDIDATA_PCIe_8_3906250 },
4125 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
4126 PCI_VENDOR_ID_IBM, 0x0299,
4127 0, 0, pbn_b0_bt_2_115200 },
4129 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
4131 0, 0, pbn_b0_1_115200 },
4133 /* the 9901 is a rebranded 9912 */
4134 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
4136 0, 0, pbn_b0_1_115200 },
4138 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
4140 0, 0, pbn_b0_1_115200 },
4142 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
4144 0, 0, pbn_b0_1_115200 },
4146 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
4148 0, 0, pbn_b0_1_115200 },
4150 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
4152 0, 0, pbn_NETMOS9900_2s_115200 },
4155 * Best Connectivity and Rosewill PCI Multi I/O cards
4158 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
4160 0, 0, pbn_b0_1_115200 },
4162 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
4164 0, 0, pbn_b0_bt_2_115200 },
4166 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
4168 0, 0, pbn_b0_bt_4_115200 },
4170 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
4171 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4172 pbn_ce4100_1_115200 },
4177 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
4178 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4182 * These entries match devices with class COMMUNICATION_SERIAL,
4183 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
4185 { PCI_ANY_ID, PCI_ANY_ID,
4186 PCI_ANY_ID, PCI_ANY_ID,
4187 PCI_CLASS_COMMUNICATION_SERIAL << 8,
4188 0xffff00, pbn_default },
4189 { PCI_ANY_ID, PCI_ANY_ID,
4190 PCI_ANY_ID, PCI_ANY_ID,
4191 PCI_CLASS_COMMUNICATION_MODEM << 8,
4192 0xffff00, pbn_default },
4193 { PCI_ANY_ID, PCI_ANY_ID,
4194 PCI_ANY_ID, PCI_ANY_ID,
4195 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
4196 0xffff00, pbn_default },
4200 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
4201 pci_channel_state_t state)
4203 struct serial_private *priv = pci_get_drvdata(dev);
4205 if (state == pci_channel_io_perm_failure)
4206 return PCI_ERS_RESULT_DISCONNECT;
4209 pciserial_suspend_ports(priv);
4211 pci_disable_device(dev);
4213 return PCI_ERS_RESULT_NEED_RESET;
4216 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
4220 rc = pci_enable_device(dev);
4223 return PCI_ERS_RESULT_DISCONNECT;
4225 pci_restore_state(dev);
4226 pci_save_state(dev);
4228 return PCI_ERS_RESULT_RECOVERED;
4231 static void serial8250_io_resume(struct pci_dev *dev)
4233 struct serial_private *priv = pci_get_drvdata(dev);
4236 pciserial_resume_ports(priv);
4239 static struct pci_error_handlers serial8250_err_handler = {
4240 .error_detected = serial8250_io_error_detected,
4241 .slot_reset = serial8250_io_slot_reset,
4242 .resume = serial8250_io_resume,
4245 static struct pci_driver serial_pci_driver = {
4247 .probe = pciserial_init_one,
4248 .remove = __devexit_p(pciserial_remove_one),
4250 .suspend = pciserial_suspend_one,
4251 .resume = pciserial_resume_one,
4253 .id_table = serial_pci_tbl,
4254 .err_handler = &serial8250_err_handler,
4257 static int __init serial8250_pci_init(void)
4259 return pci_register_driver(&serial_pci_driver);
4262 static void __exit serial8250_pci_exit(void)
4264 pci_unregister_driver(&serial_pci_driver);
4267 module_init(serial8250_pci_init);
4268 module_exit(serial8250_pci_exit);
4270 MODULE_LICENSE("GPL");
4271 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
4272 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);