Pileus Git - ~andy/linux/blob - drivers/tty/serial/8250/8250_pci.c

   1 /*
   2  *  Probe module for 8250/16550-type PCI serial ports.
   3  *
   4  *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
   5  *
   6  *  Copyright (C) 2001 Russell King, All Rights Reserved.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License.
  11  */
  12 #include <linux/module.h>
  13 #include <linux/init.h>
  14 #include <linux/pci.h>
  15 #include <linux/string.h>
  16 #include <linux/kernel.h>
  17 #include <linux/slab.h>
  18 #include <linux/delay.h>
  19 #include <linux/tty.h>
  20 #include <linux/serial_reg.h>
  21 #include <linux/serial_core.h>
  22 #include <linux/8250_pci.h>
  23 #include <linux/bitops.h>
  24
  25 #include <asm/byteorder.h>
  26 #include <asm/io.h>
  27
  28 #include "8250.h"
  29
  30 #undef SERIAL_DEBUG_PCI
  31
  32 /*
  33  * init function returns:
  34  *  > 0 - number of ports
  35  *  = 0 - use board->num_ports
  36  *  < 0 - error
  37  */
  38 struct pci_serial_quirk {
  39         u32     vendor;
  40         u32     device;
  41         u32     subvendor;
  42         u32     subdevice;
  43         int     (*probe)(struct pci_dev *dev);
  44         int     (*init)(struct pci_dev *dev);
  45         int     (*setup)(struct serial_private *,
  46                          const struct pciserial_board *,
  47                          struct uart_8250_port *, int);
  48         void    (*exit)(struct pci_dev *dev);
  49 };
  50
  51 #define PCI_NUM_BAR_RESOURCES   6
  52
  53 struct serial_private {
  54         struct pci_dev          *dev;
  55         unsigned int            nr;
  56         void __iomem            *remapped_bar[PCI_NUM_BAR_RESOURCES];
  57         struct pci_serial_quirk *quirk;
  58         int                     line[0];
  59 };
  60
  61 static int pci_default_setup(struct serial_private*,
  62           const struct pciserial_board*, struct uart_8250_port *, int);
  63
  64 static void moan_device(const char *str, struct pci_dev *dev)
  65 {
  66         printk(KERN_WARNING
  67                "%s: %s\n"
  68                "Please send the output of lspci -vv, this\n"
  69                "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
  70                "manufacturer and name of serial board or\n"
  71                "modem board to rmk+serial@arm.linux.org.uk.\n",
  72                pci_name(dev), str, dev->vendor, dev->device,
  73                dev->subsystem_vendor, dev->subsystem_device);
  74 }
  75
  76 static int
  77 setup_port(struct serial_private *priv, struct uart_8250_port *port,
  78            int bar, int offset, int regshift)
  79 {
  80         struct pci_dev *dev = priv->dev;
  81         unsigned long base, len;
  82
  83         if (bar >= PCI_NUM_BAR_RESOURCES)
  84                 return -EINVAL;
  85
  86         base = pci_resource_start(dev, bar);
  87
  88         if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
  89                 len =  pci_resource_len(dev, bar);
  90
  91                 if (!priv->remapped_bar[bar])
  92                         priv->remapped_bar[bar] = ioremap_nocache(base, len);
  93                 if (!priv->remapped_bar[bar])
  94                         return -ENOMEM;
  95
  96                 port->port.iotype = UPIO_MEM;
  97                 port->port.iobase = 0;
  98                 port->port.mapbase = base + offset;
  99                 port->port.membase = priv->remapped_bar[bar] + offset;
 100                 port->port.regshift = regshift;
 101         } else {
 102                 port->port.iotype = UPIO_PORT;
 103                 port->port.iobase = base + offset;
 104                 port->port.mapbase = 0;
 105                 port->port.membase = NULL;
 106                 port->port.regshift = 0;
 107         }
 108         return 0;
 109 }
 110
 111 /*
 112  * ADDI-DATA GmbH communication cards <info@addi-data.com>
 113  */
 114 static int addidata_apci7800_setup(struct serial_private *priv,
 115                                 const struct pciserial_board *board,
 116                                 struct uart_8250_port *port, int idx)
 117 {
 118         unsigned int bar = 0, offset = board->first_offset;
 119         bar = FL_GET_BASE(board->flags);
 120
 121         if (idx < 2) {
 122                 offset += idx * board->uart_offset;
 123         } else if ((idx >= 2) && (idx < 4)) {
 124                 bar += 1;
 125                 offset += ((idx - 2) * board->uart_offset);
 126         } else if ((idx >= 4) && (idx < 6)) {
 127                 bar += 2;
 128                 offset += ((idx - 4) * board->uart_offset);
 129         } else if (idx >= 6) {
 130                 bar += 3;
 131                 offset += ((idx - 6) * board->uart_offset);
 132         }
 133
 134         return setup_port(priv, port, bar, offset, board->reg_shift);
 135 }
 136
 137 /*
 138  * AFAVLAB uses a different mixture of BARs and offsets
 139  * Not that ugly ;) -- HW
 140  */
 141 static int
 142 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
 143               struct uart_8250_port *port, int idx)
 144 {
 145         unsigned int bar, offset = board->first_offset;
 146
 147         bar = FL_GET_BASE(board->flags);
 148         if (idx < 4)
 149                 bar += idx;
 150         else {
 151                 bar = 4;
 152                 offset += (idx - 4) * board->uart_offset;
 153         }
 154
 155         return setup_port(priv, port, bar, offset, board->reg_shift);
 156 }
 157
 158 /*
 159  * HP's Remote Management Console.  The Diva chip came in several
 160  * different versions.  N-class, L2000 and A500 have two Diva chips, each
 161  * with 3 UARTs (the third UART on the second chip is unused).  Superdome
 162  * and Keystone have one Diva chip with 3 UARTs.  Some later machines have
 163  * one Diva chip, but it has been expanded to 5 UARTs.
 164  */
 165 static int pci_hp_diva_init(struct pci_dev *dev)
 166 {
 167         int rc = 0;
 168
 169         switch (dev->subsystem_device) {
 170         case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
 171         case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
 172         case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
 173         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
 174                 rc = 3;
 175                 break;
 176         case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
 177                 rc = 2;
 178                 break;
 179         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
 180                 rc = 4;
 181                 break;
 182         case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
 183         case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
 184                 rc = 1;
 185                 break;
 186         }
 187
 188         return rc;
 189 }
 190
 191 /*
 192  * HP's Diva chip puts the 4th/5th serial port further out, and
 193  * some serial ports are supposed to be hidden on certain models.
 194  */
 195 static int
 196 pci_hp_diva_setup(struct serial_private *priv,
 197                 const struct pciserial_board *board,
 198                 struct uart_8250_port *port, int idx)
 199 {
 200         unsigned int offset = board->first_offset;
 201         unsigned int bar = FL_GET_BASE(board->flags);
 202
 203         switch (priv->dev->subsystem_device) {
 204         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
 205                 if (idx == 3)
 206                         idx++;
 207                 break;
 208         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
 209                 if (idx > 0)
 210                         idx++;
 211                 if (idx > 2)
 212                         idx++;
 213                 break;
 214         }
 215         if (idx > 2)
 216                 offset = 0x18;
 217
 218         offset += idx * board->uart_offset;
 219
 220         return setup_port(priv, port, bar, offset, board->reg_shift);
 221 }
 222
 223 /*
 224  * Added for EKF Intel i960 serial boards
 225  */
 226 static int pci_inteli960ni_init(struct pci_dev *dev)
 227 {
 228         unsigned long oldval;
 229
 230         if (!(dev->subsystem_device & 0x1000))
 231                 return -ENODEV;
 232
 233         /* is firmware started? */
 234         pci_read_config_dword(dev, 0x44, (void *)&oldval);
 235         if (oldval == 0x00001000L) { /* RESET value */
 236                 printk(KERN_DEBUG "Local i960 firmware missing");
 237                 return -ENODEV;
 238         }
 239         return 0;
 240 }
 241
 242 /*
 243  * Some PCI serial cards using the PLX 9050 PCI interface chip require
 244  * that the card interrupt be explicitly enabled or disabled.  This
 245  * seems to be mainly needed on card using the PLX which also use I/O
 246  * mapped memory.
 247  */
 248 static int pci_plx9050_init(struct pci_dev *dev)
 249 {
 250         u8 irq_config;
 251         void __iomem *p;
 252
 253         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
 254                 moan_device("no memory in bar 0", dev);
 255                 return 0;
 256         }
 257
 258         irq_config = 0x41;
 259         if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
 260             dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
 261                 irq_config = 0x43;
 262
 263         if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
 264             (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
 265                 /*
 266                  * As the megawolf cards have the int pins active
 267                  * high, and have 2 UART chips, both ints must be
 268                  * enabled on the 9050. Also, the UARTS are set in
 269                  * 16450 mode by default, so we have to enable the
 270                  * 16C950 'enhanced' mode so that we can use the
 271                  * deep FIFOs
 272                  */
 273                 irq_config = 0x5b;
 274         /*
 275          * enable/disable interrupts
 276          */
 277         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
 278         if (p == NULL)
 279                 return -ENOMEM;
 280         writel(irq_config, p + 0x4c);
 281
 282         /*
 283          * Read the register back to ensure that it took effect.
 284          */
 285         readl(p + 0x4c);
 286         iounmap(p);
 287
 288         return 0;
 289 }
 290
 291 static void __devexit pci_plx9050_exit(struct pci_dev *dev)
 292 {
 293         u8 __iomem *p;
 294
 295         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
 296                 return;
 297
 298         /*
 299          * disable interrupts
 300          */
 301         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
 302         if (p != NULL) {
 303                 writel(0, p + 0x4c);
 304
 305                 /*
 306                  * Read the register back to ensure that it took effect.
 307                  */
 308                 readl(p + 0x4c);
 309                 iounmap(p);
 310         }
 311 }
 312
 313 #define NI8420_INT_ENABLE_REG   0x38
 314 #define NI8420_INT_ENABLE_BIT   0x2000
 315
 316 static void __devexit pci_ni8420_exit(struct pci_dev *dev)
 317 {
 318         void __iomem *p;
 319         unsigned long base, len;
 320         unsigned int bar = 0;
 321
 322         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 323                 moan_device("no memory in bar", dev);
 324                 return;
 325         }
 326
 327         base = pci_resource_start(dev, bar);
 328         len =  pci_resource_len(dev, bar);
 329         p = ioremap_nocache(base, len);
 330         if (p == NULL)
 331                 return;
 332
 333         /* Disable the CPU Interrupt */
 334         writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
 335                p + NI8420_INT_ENABLE_REG);
 336         iounmap(p);
 337 }
 338
 339
 340 /* MITE registers */
 341 #define MITE_IOWBSR1    0xc4
 342 #define MITE_IOWCR1     0xf4
 343 #define MITE_LCIMR1     0x08
 344 #define MITE_LCIMR2     0x10
 345
 346 #define MITE_LCIMR2_CLR_CPU_IE  (1 << 30)
 347
 348 static void __devexit pci_ni8430_exit(struct pci_dev *dev)
 349 {
 350         void __iomem *p;
 351         unsigned long base, len;
 352         unsigned int bar = 0;
 353
 354         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 355                 moan_device("no memory in bar", dev);
 356                 return;
 357         }
 358
 359         base = pci_resource_start(dev, bar);
 360         len =  pci_resource_len(dev, bar);
 361         p = ioremap_nocache(base, len);
 362         if (p == NULL)
 363                 return;
 364
 365         /* Disable the CPU Interrupt */
 366         writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
 367         iounmap(p);
 368 }
 369
 370 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
 371 static int
 372 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
 373                 struct uart_8250_port *port, int idx)
 374 {
 375         unsigned int bar, offset = board->first_offset;
 376
 377         bar = 0;
 378
 379         if (idx < 4) {
 380                 /* first four channels map to 0, 0x100, 0x200, 0x300 */
 381                 offset += idx * board->uart_offset;
 382         } else if (idx < 8) {
 383                 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
 384                 offset += idx * board->uart_offset + 0xC00;
 385         } else /* we have only 8 ports on PMC-OCTALPRO */
 386                 return 1;
 387
 388         return setup_port(priv, port, bar, offset, board->reg_shift);
 389 }
 390
 391 /*
 392 * This does initialization for PMC OCTALPRO cards:
 393 * maps the device memory, resets the UARTs (needed, bc
 394 * if the module is removed and inserted again, the card
 395 * is in the sleep mode) and enables global interrupt.
 396 */
 397
 398 /* global control register offset for SBS PMC-OctalPro */
 399 #define OCT_REG_CR_OFF          0x500
 400
 401 static int sbs_init(struct pci_dev *dev)
 402 {
 403         u8 __iomem *p;
 404
 405         p = pci_ioremap_bar(dev, 0);
 406
 407         if (p == NULL)
 408                 return -ENOMEM;
 409         /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
 410         writeb(0x10, p + OCT_REG_CR_OFF);
 411         udelay(50);
 412         writeb(0x0, p + OCT_REG_CR_OFF);
 413
 414         /* Set bit-2 (INTENABLE) of Control Register */
 415         writeb(0x4, p + OCT_REG_CR_OFF);
 416         iounmap(p);
 417
 418         return 0;
 419 }
 420
 421 /*
 422  * Disables the global interrupt of PMC-OctalPro
 423  */
 424
 425 static void __devexit sbs_exit(struct pci_dev *dev)
 426 {
 427         u8 __iomem *p;
 428
 429         p = pci_ioremap_bar(dev, 0);
 430         /* FIXME: What if resource_len < OCT_REG_CR_OFF */
 431         if (p != NULL)
 432                 writeb(0, p + OCT_REG_CR_OFF);
 433         iounmap(p);
 434 }
 435
 436 /*
 437  * SIIG serial cards have an PCI interface chip which also controls
 438  * the UART clocking frequency. Each UART can be clocked independently
 439  * (except cards equipped with 4 UARTs) and initial clocking settings
 440  * are stored in the EEPROM chip. It can cause problems because this
 441  * version of serial driver doesn't support differently clocked UART's
 442  * on single PCI card. To prevent this, initialization functions set
 443  * high frequency clocking for all UART's on given card. It is safe (I
 444  * hope) because it doesn't touch EEPROM settings to prevent conflicts
 445  * with other OSes (like M$ DOS).
 446  *
 447  *  SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
 448  *
 449  * There is two family of SIIG serial cards with different PCI
 450  * interface chip and different configuration methods:
 451  *     - 10x cards have control registers in IO and/or memory space;
 452  *     - 20x cards have control registers in standard PCI configuration space.
 453  *
 454  * Note: all 10x cards have PCI device ids 0x10..
 455  *       all 20x cards have PCI device ids 0x20..
 456  *
 457  * There are also Quartet Serial cards which use Oxford Semiconductor
 458  * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
 459  *
 460  * Note: some SIIG cards are probed by the parport_serial object.
 461  */
 462
 463 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
 464 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
 465
 466 static int pci_siig10x_init(struct pci_dev *dev)
 467 {
 468         u16 data;
 469         void __iomem *p;
 470
 471         switch (dev->device & 0xfff8) {
 472         case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
 473                 data = 0xffdf;
 474                 break;
 475         case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
 476                 data = 0xf7ff;
 477                 break;
 478         default:                        /* 1S1P, 4S */
 479                 data = 0xfffb;
 480                 break;
 481         }
 482
 483         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
 484         if (p == NULL)
 485                 return -ENOMEM;
 486
 487         writew(readw(p + 0x28) & data, p + 0x28);
 488         readw(p + 0x28);
 489         iounmap(p);
 490         return 0;
 491 }
 492
 493 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
 494 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
 495
 496 static int pci_siig20x_init(struct pci_dev *dev)
 497 {
 498         u8 data;
 499
 500         /* Change clock frequency for the first UART. */
 501         pci_read_config_byte(dev, 0x6f, &data);
 502         pci_write_config_byte(dev, 0x6f, data & 0xef);
 503
 504         /* If this card has 2 UART, we have to do the same with second UART. */
 505         if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
 506             ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
 507                 pci_read_config_byte(dev, 0x73, &data);
 508                 pci_write_config_byte(dev, 0x73, data & 0xef);
 509         }
 510         return 0;
 511 }
 512
 513 static int pci_siig_init(struct pci_dev *dev)
 514 {
 515         unsigned int type = dev->device & 0xff00;
 516
 517         if (type == 0x1000)
 518                 return pci_siig10x_init(dev);
 519         else if (type == 0x2000)
 520                 return pci_siig20x_init(dev);
 521
 522         moan_device("Unknown SIIG card", dev);
 523         return -ENODEV;
 524 }
 525
 526 static int pci_siig_setup(struct serial_private *priv,
 527                           const struct pciserial_board *board,
 528                           struct uart_8250_port *port, int idx)
 529 {
 530         unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
 531
 532         if (idx > 3) {
 533                 bar = 4;
 534                 offset = (idx - 4) * 8;
 535         }
 536
 537         return setup_port(priv, port, bar, offset, 0);
 538 }
 539
 540 /*
 541  * Timedia has an explosion of boards, and to avoid the PCI table from
 542  * growing *huge*, we use this function to collapse some 70 entries
 543  * in the PCI table into one, for sanity's and compactness's sake.
 544  */
 545 static const unsigned short timedia_single_port[] = {
 546         0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
 547 };
 548
 549 static const unsigned short timedia_dual_port[] = {
 550         0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
 551         0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
 552         0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
 553         0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
 554         0xD079, 0
 555 };
 556
 557 static const unsigned short timedia_quad_port[] = {
 558         0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
 559         0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
 560         0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
 561         0xB157, 0
 562 };
 563
 564 static const unsigned short timedia_eight_port[] = {
 565         0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
 566         0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
 567 };
 568
 569 static const struct timedia_struct {
 570         int num;
 571         const unsigned short *ids;
 572 } timedia_data[] = {
 573         { 1, timedia_single_port },
 574         { 2, timedia_dual_port },
 575         { 4, timedia_quad_port },
 576         { 8, timedia_eight_port }
 577 };
 578
 579 /*
 580  * There are nearly 70 different Timedia/SUNIX PCI serial devices.  Instead of
 581  * listing them individually, this driver merely grabs them all with
 582  * PCI_ANY_ID.  Some of these devices, however, also feature a parallel port,
 583  * and should be left free to be claimed by parport_serial instead.
 584  */
 585 static int pci_timedia_probe(struct pci_dev *dev)
 586 {
 587         /*
 588          * Check the third digit of the subdevice ID
 589          * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
 590          */
 591         if ((dev->subsystem_device & 0x00f0) >= 0x70) {
 592                 dev_info(&dev->dev,
 593                         "ignoring Timedia subdevice %04x for parport_serial\n",
 594                         dev->subsystem_device);
 595                 return -ENODEV;
 596         }
 597
 598         return 0;
 599 }
 600
 601 static int pci_timedia_init(struct pci_dev *dev)
 602 {
 603         const unsigned short *ids;
 604         int i, j;
 605
 606         for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
 607                 ids = timedia_data[i].ids;
 608                 for (j = 0; ids[j]; j++)
 609                         if (dev->subsystem_device == ids[j])
 610                                 return timedia_data[i].num;
 611         }
 612         return 0;
 613 }
 614
 615 /*
 616  * Timedia/SUNIX uses a mixture of BARs and offsets
 617  * Ugh, this is ugly as all hell --- TYT
 618  */
 619 static int
 620 pci_timedia_setup(struct serial_private *priv,
 621                   const struct pciserial_board *board,
 622                   struct uart_8250_port *port, int idx)
 623 {
 624         unsigned int bar = 0, offset = board->first_offset;
 625
 626         switch (idx) {
 627         case 0:
 628                 bar = 0;
 629                 break;
 630         case 1:
 631                 offset = board->uart_offset;
 632                 bar = 0;
 633                 break;
 634         case 2:
 635                 bar = 1;
 636                 break;
 637         case 3:
 638                 offset = board->uart_offset;
 639                 /* FALLTHROUGH */
 640         case 4: /* BAR 2 */
 641         case 5: /* BAR 3 */
 642         case 6: /* BAR 4 */
 643         case 7: /* BAR 5 */
 644                 bar = idx - 2;
 645         }
 646
 647         return setup_port(priv, port, bar, offset, board->reg_shift);
 648 }
 649
 650 /*
 651  * Some Titan cards are also a little weird
 652  */
 653 static int
 654 titan_400l_800l_setup(struct serial_private *priv,
 655                       const struct pciserial_board *board,
 656                       struct uart_8250_port *port, int idx)
 657 {
 658         unsigned int bar, offset = board->first_offset;
 659
 660         switch (idx) {
 661         case 0:
 662                 bar = 1;
 663                 break;
 664         case 1:
 665                 bar = 2;
 666                 break;
 667         default:
 668                 bar = 4;
 669                 offset = (idx - 2) * board->uart_offset;
 670         }
 671
 672         return setup_port(priv, port, bar, offset, board->reg_shift);
 673 }
 674
 675 static int pci_xircom_init(struct pci_dev *dev)
 676 {
 677         msleep(100);
 678         return 0;
 679 }
 680
 681 static int pci_ni8420_init(struct pci_dev *dev)
 682 {
 683         void __iomem *p;
 684         unsigned long base, len;
 685         unsigned int bar = 0;
 686
 687         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 688                 moan_device("no memory in bar", dev);
 689                 return 0;
 690         }
 691
 692         base = pci_resource_start(dev, bar);
 693         len =  pci_resource_len(dev, bar);
 694         p = ioremap_nocache(base, len);
 695         if (p == NULL)
 696                 return -ENOMEM;
 697
 698         /* Enable CPU Interrupt */
 699         writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
 700                p + NI8420_INT_ENABLE_REG);
 701
 702         iounmap(p);
 703         return 0;
 704 }
 705
 706 #define MITE_IOWBSR1_WSIZE      0xa
 707 #define MITE_IOWBSR1_WIN_OFFSET 0x800
 708 #define MITE_IOWBSR1_WENAB      (1 << 7)
 709 #define MITE_LCIMR1_IO_IE_0     (1 << 24)
 710 #define MITE_LCIMR2_SET_CPU_IE  (1 << 31)
 711 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
 712
 713 static int pci_ni8430_init(struct pci_dev *dev)
 714 {
 715         void __iomem *p;
 716         unsigned long base, len;
 717         u32 device_window;
 718         unsigned int bar = 0;
 719
 720         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 721                 moan_device("no memory in bar", dev);
 722                 return 0;
 723         }
 724
 725         base = pci_resource_start(dev, bar);
 726         len =  pci_resource_len(dev, bar);
 727         p = ioremap_nocache(base, len);
 728         if (p == NULL)
 729                 return -ENOMEM;
 730
 731         /* Set device window address and size in BAR0 */
 732         device_window = ((base + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
 733                         | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
 734         writel(device_window, p + MITE_IOWBSR1);
 735
 736         /* Set window access to go to RAMSEL IO address space */
 737         writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
 738                p + MITE_IOWCR1);
 739
 740         /* Enable IO Bus Interrupt 0 */
 741         writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
 742
 743         /* Enable CPU Interrupt */
 744         writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
 745
 746         iounmap(p);
 747         return 0;
 748 }
 749
 750 /* UART Port Control Register */
 751 #define NI8430_PORTCON  0x0f
 752 #define NI8430_PORTCON_TXVR_ENABLE      (1 << 3)
 753
 754 static int
 755 pci_ni8430_setup(struct serial_private *priv,
 756                  const struct pciserial_board *board,
 757                  struct uart_8250_port *port, int idx)
 758 {
 759         void __iomem *p;
 760         unsigned long base, len;
 761         unsigned int bar, offset = board->first_offset;
 762
 763         if (idx >= board->num_ports)
 764                 return 1;
 765
 766         bar = FL_GET_BASE(board->flags);
 767         offset += idx * board->uart_offset;
 768
 769         base = pci_resource_start(priv->dev, bar);
 770         len =  pci_resource_len(priv->dev, bar);
 771         p = ioremap_nocache(base, len);
 772
 773         /* enable the transceiver */
 774         writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
 775                p + offset + NI8430_PORTCON);
 776
 777         iounmap(p);
 778
 779         return setup_port(priv, port, bar, offset, board->reg_shift);
 780 }
 781
 782 static int pci_netmos_9900_setup(struct serial_private *priv,
 783                                 const struct pciserial_board *board,
 784                                 struct uart_8250_port *port, int idx)
 785 {
 786         unsigned int bar;
 787
 788         if ((priv->dev->subsystem_device & 0xff00) == 0x3000) {
 789                 /* netmos apparently orders BARs by datasheet layout, so serial
 790                  * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
 791                  */
 792                 bar = 3 * idx;
 793
 794                 return setup_port(priv, port, bar, 0, board->reg_shift);
 795         } else {
 796                 return pci_default_setup(priv, board, port, idx);
 797         }
 798 }
 799
 800 /* the 99xx series comes with a range of device IDs and a variety
 801  * of capabilities:
 802  *
 803  * 9900 has varying capabilities and can cascade to sub-controllers
 804  *   (cascading should be purely internal)
 805  * 9904 is hardwired with 4 serial ports
 806  * 9912 and 9922 are hardwired with 2 serial ports
 807  */
 808 static int pci_netmos_9900_numports(struct pci_dev *dev)
 809 {
 810         unsigned int c = dev->class;
 811         unsigned int pi;
 812         unsigned short sub_serports;
 813
 814         pi = (c & 0xff);
 815
 816         if (pi == 2) {
 817                 return 1;
 818         } else if ((pi == 0) &&
 819                            (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
 820                 /* two possibilities: 0x30ps encodes number of parallel and
 821                  * serial ports, or 0x1000 indicates *something*. This is not
 822                  * immediately obvious, since the 2s1p+4s configuration seems
 823                  * to offer all functionality on functions 0..2, while still
 824                  * advertising the same function 3 as the 4s+2s1p config.
 825                  */
 826                 sub_serports = dev->subsystem_device & 0xf;
 827                 if (sub_serports > 0) {
 828                         return sub_serports;
 829                 } else {
 830                         printk(KERN_NOTICE "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
 831                         return 0;
 832                 }
 833         }
 834
 835         moan_device("unknown NetMos/Mostech program interface", dev);
 836         return 0;
 837 }
 838
 839 static int pci_netmos_init(struct pci_dev *dev)
 840 {
 841         /* subdevice 0x00PS means <P> parallel, <S> serial */
 842         unsigned int num_serial = dev->subsystem_device & 0xf;
 843
 844         if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
 845                 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
 846                 return 0;
 847
 848         if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
 849                         dev->subsystem_device == 0x0299)
 850                 return 0;
 851
 852         switch (dev->device) { /* FALLTHROUGH on all */
 853                 case PCI_DEVICE_ID_NETMOS_9904:
 854                 case PCI_DEVICE_ID_NETMOS_9912:
 855                 case PCI_DEVICE_ID_NETMOS_9922:
 856                 case PCI_DEVICE_ID_NETMOS_9900:
 857                         num_serial = pci_netmos_9900_numports(dev);
 858                         break;
 859
 860                 default:
 861                         if (num_serial == 0 ) {
 862                                 moan_device("unknown NetMos/Mostech device", dev);
 863                         }
 864         }
 865
 866         if (num_serial == 0)
 867                 return -ENODEV;
 868
 869         return num_serial;
 870 }
 871
 872 /*
 873  * These chips are available with optionally one parallel port and up to
 874  * two serial ports. Unfortunately they all have the same product id.
 875  *
 876  * Basic configuration is done over a region of 32 I/O ports. The base
 877  * ioport is called INTA or INTC, depending on docs/other drivers.
 878  *
 879  * The region of the 32 I/O ports is configured in POSIO0R...
 880  */
 881
 882 /* registers */
 883 #define ITE_887x_MISCR          0x9c
 884 #define ITE_887x_INTCBAR        0x78
 885 #define ITE_887x_UARTBAR        0x7c
 886 #define ITE_887x_PS0BAR         0x10
 887 #define ITE_887x_POSIO0         0x60
 888
 889 /* I/O space size */
 890 #define ITE_887x_IOSIZE         32
 891 /* I/O space size (bits 26-24; 8 bytes = 011b) */
 892 #define ITE_887x_POSIO_IOSIZE_8         (3 << 24)
 893 /* I/O space size (bits 26-24; 32 bytes = 101b) */
 894 #define ITE_887x_POSIO_IOSIZE_32        (5 << 24)
 895 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
 896 #define ITE_887x_POSIO_SPEED            (3 << 29)
 897 /* enable IO_Space bit */
 898 #define ITE_887x_POSIO_ENABLE           (1 << 31)
 899
 900 static int pci_ite887x_init(struct pci_dev *dev)
 901 {
 902         /* inta_addr are the configuration addresses of the ITE */
 903         static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
 904                                                         0x200, 0x280, 0 };
 905         int ret, i, type;
 906         struct resource *iobase = NULL;
 907         u32 miscr, uartbar, ioport;
 908
 909         /* search for the base-ioport */
 910         i = 0;
 911         while (inta_addr[i] && iobase == NULL) {
 912                 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
 913                                                                 "ite887x");
 914                 if (iobase != NULL) {
 915                         /* write POSIO0R - speed | size | ioport */
 916                         pci_write_config_dword(dev, ITE_887x_POSIO0,
 917                                 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
 918                                 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
 919                         /* write INTCBAR - ioport */
 920                         pci_write_config_dword(dev, ITE_887x_INTCBAR,
 921                                                                 inta_addr[i]);
 922                         ret = inb(inta_addr[i]);
 923                         if (ret != 0xff) {
 924                                 /* ioport connected */
 925                                 break;
 926                         }
 927                         release_region(iobase->start, ITE_887x_IOSIZE);
 928                         iobase = NULL;
 929                 }
 930                 i++;
 931         }
 932
 933         if (!inta_addr[i]) {
 934                 printk(KERN_ERR "ite887x: could not find iobase\n");
 935                 return -ENODEV;
 936         }
 937
 938         /* start of undocumented type checking (see parport_pc.c) */
 939         type = inb(iobase->start + 0x18) & 0x0f;
 940
 941         switch (type) {
 942         case 0x2:       /* ITE8871 (1P) */
 943         case 0xa:       /* ITE8875 (1P) */
 944                 ret = 0;
 945                 break;
 946         case 0xe:       /* ITE8872 (2S1P) */
 947                 ret = 2;
 948                 break;
 949         case 0x6:       /* ITE8873 (1S) */
 950                 ret = 1;
 951                 break;
 952         case 0x8:       /* ITE8874 (2S) */
 953                 ret = 2;
 954                 break;
 955         default:
 956                 moan_device("Unknown ITE887x", dev);
 957                 ret = -ENODEV;
 958         }
 959
 960         /* configure all serial ports */
 961         for (i = 0; i < ret; i++) {
 962                 /* read the I/O port from the device */
 963                 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
 964                                                                 &ioport);
 965                 ioport &= 0x0000FF00;   /* the actual base address */
 966                 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
 967                         ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
 968                         ITE_887x_POSIO_IOSIZE_8 | ioport);
 969
 970                 /* write the ioport to the UARTBAR */
 971                 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
 972                 uartbar &= ~(0xffff << (16 * i));       /* clear half the reg */
 973                 uartbar |= (ioport << (16 * i));        /* set the ioport */
 974                 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
 975
 976                 /* get current config */
 977                 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
 978                 /* disable interrupts (UARTx_Routing[3:0]) */
 979                 miscr &= ~(0xf << (12 - 4 * i));
 980                 /* activate the UART (UARTx_En) */
 981                 miscr |= 1 << (23 - i);
 982                 /* write new config with activated UART */
 983                 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
 984         }
 985
 986         if (ret <= 0) {
 987                 /* the device has no UARTs if we get here */
 988                 release_region(iobase->start, ITE_887x_IOSIZE);
 989         }
 990
 991         return ret;
 992 }
 993
 994 static void __devexit pci_ite887x_exit(struct pci_dev *dev)
 995 {
 996         u32 ioport;
 997         /* the ioport is bit 0-15 in POSIO0R */
 998         pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
 999         ioport &= 0xffff;
1000         release_region(ioport, ITE_887x_IOSIZE);
1001 }
1002
1003 /*
1004  * Oxford Semiconductor Inc.
1005  * Check that device is part of the Tornado range of devices, then determine
1006  * the number of ports available on the device.
1007  */
1008 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1009 {
1010         u8 __iomem *p;
1011         unsigned long deviceID;
1012         unsigned int  number_uarts = 0;
1013
1014         /* OxSemi Tornado devices are all 0xCxxx */
1015         if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1016             (dev->device & 0xF000) != 0xC000)
1017                 return 0;
1018
1019         p = pci_iomap(dev, 0, 5);
1020         if (p == NULL)
1021                 return -ENOMEM;
1022
1023         deviceID = ioread32(p);
1024         /* Tornado device */
1025         if (deviceID == 0x07000200) {
1026                 number_uarts = ioread8(p + 4);
1027                 printk(KERN_DEBUG
1028                         "%d ports detected on Oxford PCI Express device\n",
1029                                                                 number_uarts);
1030         }
1031         pci_iounmap(dev, p);
1032         return number_uarts;
1033 }
1034
1035 static int pci_asix_setup(struct serial_private *priv,
1036                   const struct pciserial_board *board,
1037                   struct uart_8250_port *port, int idx)
1038 {
1039         port->bugs |= UART_BUG_PARITY;
1040         return pci_default_setup(priv, board, port, idx);
1041 }
1042
1043 static int pci_default_setup(struct serial_private *priv,
1044                   const struct pciserial_board *board,
1045                   struct uart_8250_port *port, int idx)
1046 {
1047         unsigned int bar, offset = board->first_offset, maxnr;
1048
1049         bar = FL_GET_BASE(board->flags);
1050         if (board->flags & FL_BASE_BARS)
1051                 bar += idx;
1052         else
1053                 offset += idx * board->uart_offset;
1054
1055         maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1056                 (board->reg_shift + 3);
1057
1058         if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1059                 return 1;
1060
1061         return setup_port(priv, port, bar, offset, board->reg_shift);
1062 }
1063
1064 static int
1065 ce4100_serial_setup(struct serial_private *priv,
1066                   const struct pciserial_board *board,
1067                   struct uart_8250_port *port, int idx)
1068 {
1069         int ret;
1070
1071         ret = setup_port(priv, port, 0, 0, board->reg_shift);
1072         port->port.iotype = UPIO_MEM32;
1073         port->port.type = PORT_XSCALE;
1074         port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1075         port->port.regshift = 2;
1076
1077         return ret;
1078 }
1079
1080 static int
1081 pci_omegapci_setup(struct serial_private *priv,
1082                       const struct pciserial_board *board,
1083                       struct uart_8250_port *port, int idx)
1084 {
1085         return setup_port(priv, port, 2, idx * 8, 0);
1086 }
1087
1088 static int skip_tx_en_setup(struct serial_private *priv,
1089                         const struct pciserial_board *board,
1090                         struct uart_8250_port *port, int idx)
1091 {
1092         port->port.flags |= UPF_NO_TXEN_TEST;
1093         printk(KERN_DEBUG "serial8250: skipping TxEn test for device "
1094                           "[%04x:%04x] subsystem [%04x:%04x]\n",
1095                           priv->dev->vendor,
1096                           priv->dev->device,
1097                           priv->dev->subsystem_vendor,
1098                           priv->dev->subsystem_device);
1099
1100         return pci_default_setup(priv, board, port, idx);
1101 }
1102
1103 static void kt_handle_break(struct uart_port *p)
1104 {
1105         struct uart_8250_port *up =
1106                 container_of(p, struct uart_8250_port, port);
1107         /*
1108          * On receipt of a BI, serial device in Intel ME (Intel
1109          * management engine) needs to have its fifos cleared for sane
1110          * SOL (Serial Over Lan) output.
1111          */
1112         serial8250_clear_and_reinit_fifos(up);
1113 }
1114
1115 static unsigned int kt_serial_in(struct uart_port *p, int offset)
1116 {
1117         struct uart_8250_port *up =
1118                 container_of(p, struct uart_8250_port, port);
1119         unsigned int val;
1120
1121         /*
1122          * When the Intel ME (management engine) gets reset its serial
1123          * port registers could return 0 momentarily.  Functions like
1124          * serial8250_console_write, read and save the IER, perform
1125          * some operation and then restore it.  In order to avoid
1126          * setting IER register inadvertently to 0, if the value read
1127          * is 0, double check with ier value in uart_8250_port and use
1128          * that instead.  up->ier should be the same value as what is
1129          * currently configured.
1130          */
1131         val = inb(p->iobase + offset);
1132         if (offset == UART_IER) {
1133                 if (val == 0)
1134                         val = up->ier;
1135         }
1136         return val;
1137 }
1138
1139 static int kt_serial_setup(struct serial_private *priv,
1140                            const struct pciserial_board *board,
1141                            struct uart_8250_port *port, int idx)
1142 {
1143         port->port.flags |= UPF_BUG_THRE;
1144         port->port.serial_in = kt_serial_in;
1145         port->port.handle_break = kt_handle_break;
1146         return skip_tx_en_setup(priv, board, port, idx);
1147 }
1148
1149 static int pci_eg20t_init(struct pci_dev *dev)
1150 {
1151 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1152         return -ENODEV;
1153 #else
1154         return 0;
1155 #endif
1156 }
1157
1158 static int
1159 pci_xr17c154_setup(struct serial_private *priv,
1160                   const struct pciserial_board *board,
1161                   struct uart_8250_port *port, int idx)
1162 {
1163         port->port.flags |= UPF_EXAR_EFR;
1164         return pci_default_setup(priv, board, port, idx);
1165 }
1166
1167 static int
1168 pci_wch_ch353_setup(struct serial_private *priv,
1169                     const struct pciserial_board *board,
1170                     struct uart_8250_port *port, int idx)
1171 {
1172         port->port.flags |= UPF_FIXED_TYPE;
1173         port->port.type = PORT_16550A;
1174         return pci_default_setup(priv, board, port, idx);
1175 }
1176
1177 #define PCI_VENDOR_ID_SBSMODULARIO      0x124B
1178 #define PCI_SUBVENDOR_ID_SBSMODULARIO   0x124B
1179 #define PCI_DEVICE_ID_OCTPRO            0x0001
1180 #define PCI_SUBDEVICE_ID_OCTPRO232      0x0108
1181 #define PCI_SUBDEVICE_ID_OCTPRO422      0x0208
1182 #define PCI_SUBDEVICE_ID_POCTAL232      0x0308
1183 #define PCI_SUBDEVICE_ID_POCTAL422      0x0408
1184 #define PCI_VENDOR_ID_ADVANTECH         0x13fe
1185 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
1186 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
1187 #define PCI_DEVICE_ID_TITAN_200I        0x8028
1188 #define PCI_DEVICE_ID_TITAN_400I        0x8048
1189 #define PCI_DEVICE_ID_TITAN_800I        0x8088
1190 #define PCI_DEVICE_ID_TITAN_800EH       0xA007
1191 #define PCI_DEVICE_ID_TITAN_800EHB      0xA008
1192 #define PCI_DEVICE_ID_TITAN_400EH       0xA009
1193 #define PCI_DEVICE_ID_TITAN_100E        0xA010
1194 #define PCI_DEVICE_ID_TITAN_200E        0xA012
1195 #define PCI_DEVICE_ID_TITAN_400E        0xA013
1196 #define PCI_DEVICE_ID_TITAN_800E        0xA014
1197 #define PCI_DEVICE_ID_TITAN_200EI       0xA016
1198 #define PCI_DEVICE_ID_TITAN_200EISI     0xA017
1199 #define PCI_DEVICE_ID_TITAN_400V3       0xA310
1200 #define PCI_DEVICE_ID_TITAN_410V3       0xA312
1201 #define PCI_DEVICE_ID_TITAN_800V3       0xA314
1202 #define PCI_DEVICE_ID_TITAN_800V3B      0xA315
1203 #define PCI_DEVICE_ID_OXSEMI_16PCI958   0x9538
1204 #define PCIE_DEVICE_ID_NEO_2_OX_IBM     0x00F6
1205 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA  0xc001
1206 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
1207 #define PCI_VENDOR_ID_AGESTAR           0x5372
1208 #define PCI_DEVICE_ID_AGESTAR_9375      0x6872
1209 #define PCI_VENDOR_ID_ASIX              0x9710
1210
1211 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1212 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
1213
1214 /*
1215  * Master list of serial port init/setup/exit quirks.
1216  * This does not describe the general nature of the port.
1217  * (ie, baud base, number and location of ports, etc)
1218  *
1219  * This list is ordered alphabetically by vendor then device.
1220  * Specific entries must come before more generic entries.
1221  */
1222 static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
1223         /*
1224         * ADDI-DATA GmbH communication cards <info@addi-data.com>
1225         */
1226         {
1227                 .vendor         = PCI_VENDOR_ID_ADDIDATA_OLD,
1228                 .device         = PCI_DEVICE_ID_ADDIDATA_APCI7800,
1229                 .subvendor      = PCI_ANY_ID,
1230                 .subdevice      = PCI_ANY_ID,
1231                 .setup          = addidata_apci7800_setup,
1232         },
1233         /*
1234          * AFAVLAB cards - these may be called via parport_serial
1235          *  It is not clear whether this applies to all products.
1236          */
1237         {
1238                 .vendor         = PCI_VENDOR_ID_AFAVLAB,
1239                 .device         = PCI_ANY_ID,
1240                 .subvendor      = PCI_ANY_ID,
1241                 .subdevice      = PCI_ANY_ID,
1242                 .setup          = afavlab_setup,
1243         },
1244         /*
1245          * HP Diva
1246          */
1247         {
1248                 .vendor         = PCI_VENDOR_ID_HP,
1249                 .device         = PCI_DEVICE_ID_HP_DIVA,
1250                 .subvendor      = PCI_ANY_ID,
1251                 .subdevice      = PCI_ANY_ID,
1252                 .init           = pci_hp_diva_init,
1253                 .setup          = pci_hp_diva_setup,
1254         },
1255         /*
1256          * Intel
1257          */
1258         {
1259                 .vendor         = PCI_VENDOR_ID_INTEL,
1260                 .device         = PCI_DEVICE_ID_INTEL_80960_RP,
1261                 .subvendor      = 0xe4bf,
1262                 .subdevice      = PCI_ANY_ID,
1263                 .init           = pci_inteli960ni_init,
1264                 .setup          = pci_default_setup,
1265         },
1266         {
1267                 .vendor         = PCI_VENDOR_ID_INTEL,
1268                 .device         = PCI_DEVICE_ID_INTEL_8257X_SOL,
1269                 .subvendor      = PCI_ANY_ID,
1270                 .subdevice      = PCI_ANY_ID,
1271                 .setup          = skip_tx_en_setup,
1272         },
1273         {
1274                 .vendor         = PCI_VENDOR_ID_INTEL,
1275                 .device         = PCI_DEVICE_ID_INTEL_82573L_SOL,
1276                 .subvendor      = PCI_ANY_ID,
1277                 .subdevice      = PCI_ANY_ID,
1278                 .setup          = skip_tx_en_setup,
1279         },
1280         {
1281                 .vendor         = PCI_VENDOR_ID_INTEL,
1282                 .device         = PCI_DEVICE_ID_INTEL_82573E_SOL,
1283                 .subvendor      = PCI_ANY_ID,
1284                 .subdevice      = PCI_ANY_ID,
1285                 .setup          = skip_tx_en_setup,
1286         },
1287         {
1288                 .vendor         = PCI_VENDOR_ID_INTEL,
1289                 .device         = PCI_DEVICE_ID_INTEL_CE4100_UART,
1290                 .subvendor      = PCI_ANY_ID,
1291                 .subdevice      = PCI_ANY_ID,
1292                 .setup          = ce4100_serial_setup,
1293         },
1294         {
1295                 .vendor         = PCI_VENDOR_ID_INTEL,
1296                 .device         = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
1297                 .subvendor      = PCI_ANY_ID,
1298                 .subdevice      = PCI_ANY_ID,
1299                 .setup          = kt_serial_setup,
1300         },
1301         /*
1302          * ITE
1303          */
1304         {
1305                 .vendor         = PCI_VENDOR_ID_ITE,
1306                 .device         = PCI_DEVICE_ID_ITE_8872,
1307                 .subvendor      = PCI_ANY_ID,
1308                 .subdevice      = PCI_ANY_ID,
1309                 .init           = pci_ite887x_init,
1310                 .setup          = pci_default_setup,
1311                 .exit           = __devexit_p(pci_ite887x_exit),
1312         },
1313         /*
1314          * National Instruments
1315          */
1316         {
1317                 .vendor         = PCI_VENDOR_ID_NI,
1318                 .device         = PCI_DEVICE_ID_NI_PCI23216,
1319                 .subvendor      = PCI_ANY_ID,
1320                 .subdevice      = PCI_ANY_ID,
1321                 .init           = pci_ni8420_init,
1322                 .setup          = pci_default_setup,
1323                 .exit           = __devexit_p(pci_ni8420_exit),
1324         },
1325         {
1326                 .vendor         = PCI_VENDOR_ID_NI,
1327                 .device         = PCI_DEVICE_ID_NI_PCI2328,
1328                 .subvendor      = PCI_ANY_ID,
1329                 .subdevice      = PCI_ANY_ID,
1330                 .init           = pci_ni8420_init,
1331                 .setup          = pci_default_setup,
1332                 .exit           = __devexit_p(pci_ni8420_exit),
1333         },
1334         {
1335                 .vendor         = PCI_VENDOR_ID_NI,
1336                 .device         = PCI_DEVICE_ID_NI_PCI2324,
1337                 .subvendor      = PCI_ANY_ID,
1338                 .subdevice      = PCI_ANY_ID,
1339                 .init           = pci_ni8420_init,
1340                 .setup          = pci_default_setup,
1341                 .exit           = __devexit_p(pci_ni8420_exit),
1342         },
1343         {
1344                 .vendor         = PCI_VENDOR_ID_NI,
1345                 .device         = PCI_DEVICE_ID_NI_PCI2322,
1346                 .subvendor      = PCI_ANY_ID,
1347                 .subdevice      = PCI_ANY_ID,
1348                 .init           = pci_ni8420_init,
1349                 .setup          = pci_default_setup,
1350                 .exit           = __devexit_p(pci_ni8420_exit),
1351         },
1352         {
1353                 .vendor         = PCI_VENDOR_ID_NI,
1354                 .device         = PCI_DEVICE_ID_NI_PCI2324I,
1355                 .subvendor      = PCI_ANY_ID,
1356                 .subdevice      = PCI_ANY_ID,
1357                 .init           = pci_ni8420_init,
1358                 .setup          = pci_default_setup,
1359                 .exit           = __devexit_p(pci_ni8420_exit),
1360         },
1361         {
1362                 .vendor         = PCI_VENDOR_ID_NI,
1363                 .device         = PCI_DEVICE_ID_NI_PCI2322I,
1364                 .subvendor      = PCI_ANY_ID,
1365                 .subdevice      = PCI_ANY_ID,
1366                 .init           = pci_ni8420_init,
1367                 .setup          = pci_default_setup,
1368                 .exit           = __devexit_p(pci_ni8420_exit),
1369         },
1370         {
1371                 .vendor         = PCI_VENDOR_ID_NI,
1372                 .device         = PCI_DEVICE_ID_NI_PXI8420_23216,
1373                 .subvendor      = PCI_ANY_ID,
1374                 .subdevice      = PCI_ANY_ID,
1375                 .init           = pci_ni8420_init,
1376                 .setup          = pci_default_setup,
1377                 .exit           = __devexit_p(pci_ni8420_exit),
1378         },
1379         {
1380                 .vendor         = PCI_VENDOR_ID_NI,
1381                 .device         = PCI_DEVICE_ID_NI_PXI8420_2328,
1382                 .subvendor      = PCI_ANY_ID,
1383                 .subdevice      = PCI_ANY_ID,
1384                 .init           = pci_ni8420_init,
1385                 .setup          = pci_default_setup,
1386                 .exit           = __devexit_p(pci_ni8420_exit),
1387         },
1388         {
1389                 .vendor         = PCI_VENDOR_ID_NI,
1390                 .device         = PCI_DEVICE_ID_NI_PXI8420_2324,
1391                 .subvendor      = PCI_ANY_ID,
1392                 .subdevice      = PCI_ANY_ID,
1393                 .init           = pci_ni8420_init,
1394                 .setup          = pci_default_setup,
1395                 .exit           = __devexit_p(pci_ni8420_exit),
1396         },
1397         {
1398                 .vendor         = PCI_VENDOR_ID_NI,
1399                 .device         = PCI_DEVICE_ID_NI_PXI8420_2322,
1400                 .subvendor      = PCI_ANY_ID,
1401                 .subdevice      = PCI_ANY_ID,
1402                 .init           = pci_ni8420_init,
1403                 .setup          = pci_default_setup,
1404                 .exit           = __devexit_p(pci_ni8420_exit),
1405         },
1406         {
1407                 .vendor         = PCI_VENDOR_ID_NI,
1408                 .device         = PCI_DEVICE_ID_NI_PXI8422_2324,
1409                 .subvendor      = PCI_ANY_ID,
1410                 .subdevice      = PCI_ANY_ID,
1411                 .init           = pci_ni8420_init,
1412                 .setup          = pci_default_setup,
1413                 .exit           = __devexit_p(pci_ni8420_exit),
1414         },
1415         {
1416                 .vendor         = PCI_VENDOR_ID_NI,
1417                 .device         = PCI_DEVICE_ID_NI_PXI8422_2322,
1418                 .subvendor      = PCI_ANY_ID,
1419                 .subdevice      = PCI_ANY_ID,
1420                 .init           = pci_ni8420_init,
1421                 .setup          = pci_default_setup,
1422                 .exit           = __devexit_p(pci_ni8420_exit),
1423         },
1424         {
1425                 .vendor         = PCI_VENDOR_ID_NI,
1426                 .device         = PCI_ANY_ID,
1427                 .subvendor      = PCI_ANY_ID,
1428                 .subdevice      = PCI_ANY_ID,
1429                 .init           = pci_ni8430_init,
1430                 .setup          = pci_ni8430_setup,
1431                 .exit           = __devexit_p(pci_ni8430_exit),
1432         },
1433         /*
1434          * Panacom
1435          */
1436         {
1437                 .vendor         = PCI_VENDOR_ID_PANACOM,
1438                 .device         = PCI_DEVICE_ID_PANACOM_QUADMODEM,
1439                 .subvendor      = PCI_ANY_ID,
1440                 .subdevice      = PCI_ANY_ID,
1441                 .init           = pci_plx9050_init,
1442                 .setup          = pci_default_setup,
1443                 .exit           = __devexit_p(pci_plx9050_exit),
1444         },
1445         {
1446                 .vendor         = PCI_VENDOR_ID_PANACOM,
1447                 .device         = PCI_DEVICE_ID_PANACOM_DUALMODEM,
1448                 .subvendor      = PCI_ANY_ID,
1449                 .subdevice      = PCI_ANY_ID,
1450                 .init           = pci_plx9050_init,
1451                 .setup          = pci_default_setup,
1452                 .exit           = __devexit_p(pci_plx9050_exit),
1453         },
1454         /*
1455          * PLX
1456          */
1457         {
1458                 .vendor         = PCI_VENDOR_ID_PLX,
1459                 .device         = PCI_DEVICE_ID_PLX_9030,
1460                 .subvendor      = PCI_SUBVENDOR_ID_PERLE,
1461                 .subdevice      = PCI_ANY_ID,
1462                 .setup          = pci_default_setup,
1463         },
1464         {
1465                 .vendor         = PCI_VENDOR_ID_PLX,
1466                 .device         = PCI_DEVICE_ID_PLX_9050,
1467                 .subvendor      = PCI_SUBVENDOR_ID_EXSYS,
1468                 .subdevice      = PCI_SUBDEVICE_ID_EXSYS_4055,
1469                 .init           = pci_plx9050_init,
1470                 .setup          = pci_default_setup,
1471                 .exit           = __devexit_p(pci_plx9050_exit),
1472         },
1473         {
1474                 .vendor         = PCI_VENDOR_ID_PLX,
1475                 .device         = PCI_DEVICE_ID_PLX_9050,
1476                 .subvendor      = PCI_SUBVENDOR_ID_KEYSPAN,
1477                 .subdevice      = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
1478                 .init           = pci_plx9050_init,
1479                 .setup          = pci_default_setup,
1480                 .exit           = __devexit_p(pci_plx9050_exit),
1481         },
1482         {
1483                 .vendor         = PCI_VENDOR_ID_PLX,
1484                 .device         = PCI_DEVICE_ID_PLX_9050,
1485                 .subvendor      = PCI_VENDOR_ID_PLX,
1486                 .subdevice      = PCI_SUBDEVICE_ID_UNKNOWN_0x1584,
1487                 .init           = pci_plx9050_init,
1488                 .setup          = pci_default_setup,
1489                 .exit           = __devexit_p(pci_plx9050_exit),
1490         },
1491         {
1492                 .vendor         = PCI_VENDOR_ID_PLX,
1493                 .device         = PCI_DEVICE_ID_PLX_ROMULUS,
1494                 .subvendor      = PCI_VENDOR_ID_PLX,
1495                 .subdevice      = PCI_DEVICE_ID_PLX_ROMULUS,
1496                 .init           = pci_plx9050_init,
1497                 .setup          = pci_default_setup,
1498                 .exit           = __devexit_p(pci_plx9050_exit),
1499         },
1500         /*
1501          * SBS Technologies, Inc., PMC-OCTALPRO 232
1502          */
1503         {
1504                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
1505                 .device         = PCI_DEVICE_ID_OCTPRO,
1506                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
1507                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO232,
1508                 .init           = sbs_init,
1509                 .setup          = sbs_setup,
1510                 .exit           = __devexit_p(sbs_exit),
1511         },
1512         /*
1513          * SBS Technologies, Inc., PMC-OCTALPRO 422
1514          */
1515         {
1516                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
1517                 .device         = PCI_DEVICE_ID_OCTPRO,
1518                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
1519                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO422,
1520                 .init           = sbs_init,
1521                 .setup          = sbs_setup,
1522                 .exit           = __devexit_p(sbs_exit),
1523         },
1524         /*
1525          * SBS Technologies, Inc., P-Octal 232
1526          */
1527         {
1528                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
1529                 .device         = PCI_DEVICE_ID_OCTPRO,
1530                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
1531                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL232,
1532                 .init           = sbs_init,
1533                 .setup          = sbs_setup,
1534                 .exit           = __devexit_p(sbs_exit),
1535         },
1536         /*
1537          * SBS Technologies, Inc., P-Octal 422
1538          */
1539         {
1540                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
1541                 .device         = PCI_DEVICE_ID_OCTPRO,
1542                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
1543                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL422,
1544                 .init           = sbs_init,
1545                 .setup          = sbs_setup,
1546                 .exit           = __devexit_p(sbs_exit),
1547         },
1548         /*
1549          * SIIG cards - these may be called via parport_serial
1550          */
1551         {
1552                 .vendor         = PCI_VENDOR_ID_SIIG,
1553                 .device         = PCI_ANY_ID,
1554                 .subvendor      = PCI_ANY_ID,
1555                 .subdevice      = PCI_ANY_ID,
1556                 .init           = pci_siig_init,
1557                 .setup          = pci_siig_setup,
1558         },
1559         /*
1560          * Titan cards
1561          */
1562         {
1563                 .vendor         = PCI_VENDOR_ID_TITAN,
1564                 .device         = PCI_DEVICE_ID_TITAN_400L,
1565                 .subvendor      = PCI_ANY_ID,
1566                 .subdevice      = PCI_ANY_ID,
1567                 .setup          = titan_400l_800l_setup,
1568         },
1569         {
1570                 .vendor         = PCI_VENDOR_ID_TITAN,
1571                 .device         = PCI_DEVICE_ID_TITAN_800L,
1572                 .subvendor      = PCI_ANY_ID,
1573                 .subdevice      = PCI_ANY_ID,
1574                 .setup          = titan_400l_800l_setup,
1575         },
1576         /*
1577          * Timedia cards
1578          */
1579         {
1580                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
1581                 .device         = PCI_DEVICE_ID_TIMEDIA_1889,
1582                 .subvendor      = PCI_VENDOR_ID_TIMEDIA,
1583                 .subdevice      = PCI_ANY_ID,
1584                 .probe          = pci_timedia_probe,
1585                 .init           = pci_timedia_init,
1586                 .setup          = pci_timedia_setup,
1587         },
1588         {
1589                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
1590                 .device         = PCI_ANY_ID,
1591                 .subvendor      = PCI_ANY_ID,
1592                 .subdevice      = PCI_ANY_ID,
1593                 .setup          = pci_timedia_setup,
1594         },
1595         /*
1596          * Exar cards
1597          */
1598         {
1599                 .vendor = PCI_VENDOR_ID_EXAR,
1600                 .device = PCI_DEVICE_ID_EXAR_XR17C152,
1601                 .subvendor      = PCI_ANY_ID,
1602                 .subdevice      = PCI_ANY_ID,
1603                 .setup          = pci_xr17c154_setup,
1604         },
1605         {
1606                 .vendor = PCI_VENDOR_ID_EXAR,
1607                 .device = PCI_DEVICE_ID_EXAR_XR17C154,
1608                 .subvendor      = PCI_ANY_ID,
1609                 .subdevice      = PCI_ANY_ID,
1610                 .setup          = pci_xr17c154_setup,
1611         },
1612         {
1613                 .vendor = PCI_VENDOR_ID_EXAR,
1614                 .device = PCI_DEVICE_ID_EXAR_XR17C158,
1615                 .subvendor      = PCI_ANY_ID,
1616                 .subdevice      = PCI_ANY_ID,
1617                 .setup          = pci_xr17c154_setup,
1618         },
1619         /*
1620          * Xircom cards
1621          */
1622         {
1623                 .vendor         = PCI_VENDOR_ID_XIRCOM,
1624                 .device         = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
1625                 .subvendor      = PCI_ANY_ID,
1626                 .subdevice      = PCI_ANY_ID,
1627                 .init           = pci_xircom_init,
1628                 .setup          = pci_default_setup,
1629         },
1630         /*
1631          * Netmos cards - these may be called via parport_serial
1632          */
1633         {
1634                 .vendor         = PCI_VENDOR_ID_NETMOS,
1635                 .device         = PCI_ANY_ID,
1636                 .subvendor      = PCI_ANY_ID,
1637                 .subdevice      = PCI_ANY_ID,
1638                 .init           = pci_netmos_init,
1639                 .setup          = pci_netmos_9900_setup,
1640         },
1641         /*
1642          * For Oxford Semiconductor Tornado based devices
1643          */
1644         {
1645                 .vendor         = PCI_VENDOR_ID_OXSEMI,
1646                 .device         = PCI_ANY_ID,
1647                 .subvendor      = PCI_ANY_ID,
1648                 .subdevice      = PCI_ANY_ID,
1649                 .init           = pci_oxsemi_tornado_init,
1650                 .setup          = pci_default_setup,
1651         },
1652         {
1653                 .vendor         = PCI_VENDOR_ID_MAINPINE,
1654                 .device         = PCI_ANY_ID,
1655                 .subvendor      = PCI_ANY_ID,
1656                 .subdevice      = PCI_ANY_ID,
1657                 .init           = pci_oxsemi_tornado_init,
1658                 .setup          = pci_default_setup,
1659         },
1660         {
1661                 .vendor         = PCI_VENDOR_ID_DIGI,
1662                 .device         = PCIE_DEVICE_ID_NEO_2_OX_IBM,
1663                 .subvendor              = PCI_SUBVENDOR_ID_IBM,
1664                 .subdevice              = PCI_ANY_ID,
1665                 .init                   = pci_oxsemi_tornado_init,
1666                 .setup          = pci_default_setup,
1667         },
1668         {
1669                 .vendor         = PCI_VENDOR_ID_INTEL,
1670                 .device         = 0x8811,
1671                 .subvendor      = PCI_ANY_ID,
1672                 .subdevice      = PCI_ANY_ID,
1673                 .init           = pci_eg20t_init,
1674                 .setup          = pci_default_setup,
1675         },
1676         {
1677                 .vendor         = PCI_VENDOR_ID_INTEL,
1678                 .device         = 0x8812,
1679                 .subvendor      = PCI_ANY_ID,
1680                 .subdevice      = PCI_ANY_ID,
1681                 .init           = pci_eg20t_init,
1682                 .setup          = pci_default_setup,
1683         },
1684         {
1685                 .vendor         = PCI_VENDOR_ID_INTEL,
1686                 .device         = 0x8813,
1687                 .subvendor      = PCI_ANY_ID,
1688                 .subdevice      = PCI_ANY_ID,
1689                 .init           = pci_eg20t_init,
1690                 .setup          = pci_default_setup,
1691         },
1692         {
1693                 .vendor         = PCI_VENDOR_ID_INTEL,
1694                 .device         = 0x8814,
1695                 .subvendor      = PCI_ANY_ID,
1696                 .subdevice      = PCI_ANY_ID,
1697                 .init           = pci_eg20t_init,
1698                 .setup          = pci_default_setup,
1699         },
1700         {
1701                 .vendor         = 0x10DB,
1702                 .device         = 0x8027,
1703                 .subvendor      = PCI_ANY_ID,
1704                 .subdevice      = PCI_ANY_ID,
1705                 .init           = pci_eg20t_init,
1706                 .setup          = pci_default_setup,
1707         },
1708         {
1709                 .vendor         = 0x10DB,
1710                 .device         = 0x8028,
1711                 .subvendor      = PCI_ANY_ID,
1712                 .subdevice      = PCI_ANY_ID,
1713                 .init           = pci_eg20t_init,
1714                 .setup          = pci_default_setup,
1715         },
1716         {
1717                 .vendor         = 0x10DB,
1718                 .device         = 0x8029,
1719                 .subvendor      = PCI_ANY_ID,
1720                 .subdevice      = PCI_ANY_ID,
1721                 .init           = pci_eg20t_init,
1722                 .setup          = pci_default_setup,
1723         },
1724         {
1725                 .vendor         = 0x10DB,
1726                 .device         = 0x800C,
1727                 .subvendor      = PCI_ANY_ID,
1728                 .subdevice      = PCI_ANY_ID,
1729                 .init           = pci_eg20t_init,
1730                 .setup          = pci_default_setup,
1731         },
1732         {
1733                 .vendor         = 0x10DB,
1734                 .device         = 0x800D,
1735                 .subvendor      = PCI_ANY_ID,
1736                 .subdevice      = PCI_ANY_ID,
1737                 .init           = pci_eg20t_init,
1738                 .setup          = pci_default_setup,
1739         },
1740         /*
1741          * Cronyx Omega PCI (PLX-chip based)
1742          */
1743         {
1744                 .vendor         = PCI_VENDOR_ID_PLX,
1745                 .device         = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
1746                 .subvendor      = PCI_ANY_ID,
1747                 .subdevice      = PCI_ANY_ID,
1748                 .setup          = pci_omegapci_setup,
1749         },
1750         /* WCH CH353 2S1P card (16550 clone) */
1751         {
1752                 .vendor         = 0x4348,
1753                 .device         = 0x7053,
1754                 .subvendor      = 0x4348,
1755                 .subdevice      = 0x3253,
1756                 .setup          = pci_wch_ch353_setup,
1757         },
1758         /*
1759          * ASIX devices with FIFO bug
1760          */
1761         {
1762                 .vendor         = PCI_VENDOR_ID_ASIX,
1763                 .device         = PCI_ANY_ID,
1764                 .subvendor      = PCI_ANY_ID,
1765                 .subdevice      = PCI_ANY_ID,
1766                 .setup          = pci_asix_setup,
1767         },
1768         /*
1769          * Default "match everything" terminator entry
1770          */
1771         {
1772                 .vendor         = PCI_ANY_ID,
1773                 .device         = PCI_ANY_ID,
1774                 .subvendor      = PCI_ANY_ID,
1775                 .subdevice      = PCI_ANY_ID,
1776                 .setup          = pci_default_setup,
1777         }
1778 };
1779
1780 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
1781 {
1782         return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
1783 }
1784
1785 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
1786 {
1787         struct pci_serial_quirk *quirk;
1788
1789         for (quirk = pci_serial_quirks; ; quirk++)
1790                 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
1791                     quirk_id_matches(quirk->device, dev->device) &&
1792                     quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
1793                     quirk_id_matches(quirk->subdevice, dev->subsystem_device))
1794                         break;
1795         return quirk;
1796 }
1797
1798 static inline int get_pci_irq(struct pci_dev *dev,
1799                                 const struct pciserial_board *board)
1800 {
1801         if (board->flags & FL_NOIRQ)
1802                 return 0;
1803         else
1804                 return dev->irq;
1805 }
1806
1807 /*
1808  * This is the configuration table for all of the PCI serial boards
1809  * which we support.  It is directly indexed by the pci_board_num_t enum
1810  * value, which is encoded in the pci_device_id PCI probe table's
1811  * driver_data member.
1812  *
1813  * The makeup of these names are:
1814  *  pbn_bn{_bt}_n_baud{_offsetinhex}
1815  *
1816  *  bn          = PCI BAR number
1817  *  bt          = Index using PCI BARs
1818  *  n           = number of serial ports
1819  *  baud        = baud rate
1820  *  offsetinhex = offset for each sequential port (in hex)
1821  *
1822  * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
1823  *
1824  * Please note: in theory if n = 1, _bt infix should make no difference.
1825  * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
1826  */
1827 enum pci_board_num_t {
1828         pbn_default = 0,
1829
1830         pbn_b0_1_115200,
1831         pbn_b0_2_115200,
1832         pbn_b0_4_115200,
1833         pbn_b0_5_115200,
1834         pbn_b0_8_115200,
1835
1836         pbn_b0_1_921600,
1837         pbn_b0_2_921600,
1838         pbn_b0_4_921600,
1839
1840         pbn_b0_2_1130000,
1841
1842         pbn_b0_4_1152000,
1843
1844         pbn_b0_2_1843200,
1845         pbn_b0_4_1843200,
1846
1847         pbn_b0_2_1843200_200,
1848         pbn_b0_4_1843200_200,
1849         pbn_b0_8_1843200_200,
1850
1851         pbn_b0_1_4000000,
1852
1853         pbn_b0_bt_1_115200,
1854         pbn_b0_bt_2_115200,
1855         pbn_b0_bt_4_115200,
1856         pbn_b0_bt_8_115200,
1857
1858         pbn_b0_bt_1_460800,
1859         pbn_b0_bt_2_460800,
1860         pbn_b0_bt_4_460800,
1861
1862         pbn_b0_bt_1_921600,
1863         pbn_b0_bt_2_921600,
1864         pbn_b0_bt_4_921600,
1865         pbn_b0_bt_8_921600,
1866
1867         pbn_b1_1_115200,
1868         pbn_b1_2_115200,
1869         pbn_b1_4_115200,
1870         pbn_b1_8_115200,
1871         pbn_b1_16_115200,
1872
1873         pbn_b1_1_921600,
1874         pbn_b1_2_921600,
1875         pbn_b1_4_921600,
1876         pbn_b1_8_921600,
1877
1878         pbn_b1_2_1250000,
1879
1880         pbn_b1_bt_1_115200,
1881         pbn_b1_bt_2_115200,
1882         pbn_b1_bt_4_115200,
1883
1884         pbn_b1_bt_2_921600,
1885
1886         pbn_b1_1_1382400,
1887         pbn_b1_2_1382400,
1888         pbn_b1_4_1382400,
1889         pbn_b1_8_1382400,
1890
1891         pbn_b2_1_115200,
1892         pbn_b2_2_115200,
1893         pbn_b2_4_115200,
1894         pbn_b2_8_115200,
1895
1896         pbn_b2_1_460800,
1897         pbn_b2_4_460800,
1898         pbn_b2_8_460800,
1899         pbn_b2_16_460800,
1900
1901         pbn_b2_1_921600,
1902         pbn_b2_4_921600,
1903         pbn_b2_8_921600,
1904
1905         pbn_b2_8_1152000,
1906
1907         pbn_b2_bt_1_115200,
1908         pbn_b2_bt_2_115200,
1909         pbn_b2_bt_4_115200,
1910
1911         pbn_b2_bt_2_921600,
1912         pbn_b2_bt_4_921600,
1913
1914         pbn_b3_2_115200,
1915         pbn_b3_4_115200,
1916         pbn_b3_8_115200,
1917
1918         pbn_b4_bt_2_921600,
1919         pbn_b4_bt_4_921600,
1920         pbn_b4_bt_8_921600,
1921
1922         /*
1923          * Board-specific versions.
1924          */
1925         pbn_panacom,
1926         pbn_panacom2,
1927         pbn_panacom4,
1928         pbn_plx_romulus,
1929         pbn_oxsemi,
1930         pbn_oxsemi_1_4000000,
1931         pbn_oxsemi_2_4000000,
1932         pbn_oxsemi_4_4000000,
1933         pbn_oxsemi_8_4000000,
1934         pbn_intel_i960,
1935         pbn_sgi_ioc3,
1936         pbn_computone_4,
1937         pbn_computone_6,
1938         pbn_computone_8,
1939         pbn_sbsxrsio,
1940         pbn_exar_XR17C152,
1941         pbn_exar_XR17C154,
1942         pbn_exar_XR17C158,
1943         pbn_exar_ibm_saturn,
1944         pbn_pasemi_1682M,
1945         pbn_ni8430_2,
1946         pbn_ni8430_4,
1947         pbn_ni8430_8,
1948         pbn_ni8430_16,
1949         pbn_ADDIDATA_PCIe_1_3906250,
1950         pbn_ADDIDATA_PCIe_2_3906250,
1951         pbn_ADDIDATA_PCIe_4_3906250,
1952         pbn_ADDIDATA_PCIe_8_3906250,
1953         pbn_ce4100_1_115200,
1954         pbn_omegapci,
1955         pbn_NETMOS9900_2s_115200,
1956 };
1957
1958 /*
1959  * uart_offset - the space between channels
1960  * reg_shift   - describes how the UART registers are mapped
1961  *               to PCI memory by the card.
1962  * For example IER register on SBS, Inc. PMC-OctPro is located at
1963  * offset 0x10 from the UART base, while UART_IER is defined as 1
1964  * in include/linux/serial_reg.h,
1965  * see first lines of serial_in() and serial_out() in 8250.c
1966 */
1967
1968 static struct pciserial_board pci_boards[] __devinitdata = {
1969         [pbn_default] = {
1970                 .flags          = FL_BASE0,
1971                 .num_ports      = 1,
1972                 .base_baud      = 115200,
1973                 .uart_offset    = 8,
1974         },
1975         [pbn_b0_1_115200] = {
1976                 .flags          = FL_BASE0,
1977                 .num_ports      = 1,
1978                 .base_baud      = 115200,
1979                 .uart_offset    = 8,
1980         },
1981         [pbn_b0_2_115200] = {
1982                 .flags          = FL_BASE0,
1983                 .num_ports      = 2,
1984                 .base_baud      = 115200,
1985                 .uart_offset    = 8,
1986         },
1987         [pbn_b0_4_115200] = {
1988                 .flags          = FL_BASE0,
1989                 .num_ports      = 4,
1990                 .base_baud      = 115200,
1991                 .uart_offset    = 8,
1992         },
1993         [pbn_b0_5_115200] = {
1994                 .flags          = FL_BASE0,
1995                 .num_ports      = 5,
1996                 .base_baud      = 115200,
1997                 .uart_offset    = 8,
1998         },
1999         [pbn_b0_8_115200] = {
2000                 .flags          = FL_BASE0,
2001                 .num_ports      = 8,
2002                 .base_baud      = 115200,
2003                 .uart_offset    = 8,
2004         },
2005         [pbn_b0_1_921600] = {
2006                 .flags          = FL_BASE0,
2007                 .num_ports      = 1,
2008                 .base_baud      = 921600,
2009                 .uart_offset    = 8,
2010         },
2011         [pbn_b0_2_921600] = {
2012                 .flags          = FL_BASE0,
2013                 .num_ports      = 2,
2014                 .base_baud      = 921600,
2015                 .uart_offset    = 8,
2016         },
2017         [pbn_b0_4_921600] = {
2018                 .flags          = FL_BASE0,
2019                 .num_ports      = 4,
2020                 .base_baud      = 921600,
2021                 .uart_offset    = 8,
2022         },
2023
2024         [pbn_b0_2_1130000] = {
2025                 .flags          = FL_BASE0,
2026                 .num_ports      = 2,
2027                 .base_baud      = 1130000,
2028                 .uart_offset    = 8,
2029         },
2030
2031         [pbn_b0_4_1152000] = {
2032                 .flags          = FL_BASE0,
2033                 .num_ports      = 4,
2034                 .base_baud      = 1152000,
2035                 .uart_offset    = 8,
2036         },
2037
2038         [pbn_b0_2_1843200] = {
2039                 .flags          = FL_BASE0,
2040                 .num_ports      = 2,
2041                 .base_baud      = 1843200,
2042                 .uart_offset    = 8,
2043         },
2044         [pbn_b0_4_1843200] = {
2045                 .flags          = FL_BASE0,
2046                 .num_ports      = 4,
2047                 .base_baud      = 1843200,
2048                 .uart_offset    = 8,
2049         },
2050
2051         [pbn_b0_2_1843200_200] = {
2052                 .flags          = FL_BASE0,
2053                 .num_ports      = 2,
2054                 .base_baud      = 1843200,
2055                 .uart_offset    = 0x200,
2056         },
2057         [pbn_b0_4_1843200_200] = {
2058                 .flags          = FL_BASE0,
2059                 .num_ports      = 4,
2060                 .base_baud      = 1843200,
2061                 .uart_offset    = 0x200,
2062         },
2063         [pbn_b0_8_1843200_200] = {
2064                 .flags          = FL_BASE0,
2065                 .num_ports      = 8,
2066                 .base_baud      = 1843200,
2067                 .uart_offset    = 0x200,
2068         },
2069         [pbn_b0_1_4000000] = {
2070                 .flags          = FL_BASE0,
2071                 .num_ports      = 1,
2072                 .base_baud      = 4000000,
2073                 .uart_offset    = 8,
2074         },
2075
2076         [pbn_b0_bt_1_115200] = {
2077                 .flags          = FL_BASE0|FL_BASE_BARS,
2078                 .num_ports      = 1,
2079                 .base_baud      = 115200,
2080                 .uart_offset    = 8,
2081         },
2082         [pbn_b0_bt_2_115200] = {
2083                 .flags          = FL_BASE0|FL_BASE_BARS,
2084                 .num_ports      = 2,
2085                 .base_baud      = 115200,
2086                 .uart_offset    = 8,
2087         },
2088         [pbn_b0_bt_4_115200] = {
2089                 .flags          = FL_BASE0|FL_BASE_BARS,
2090                 .num_ports      = 4,
2091                 .base_baud      = 115200,
2092                 .uart_offset    = 8,
2093         },
2094         [pbn_b0_bt_8_115200] = {
2095                 .flags          = FL_BASE0|FL_BASE_BARS,
2096                 .num_ports      = 8,
2097                 .base_baud      = 115200,
2098                 .uart_offset    = 8,
2099         },
2100
2101         [pbn_b0_bt_1_460800] = {
2102                 .flags          = FL_BASE0|FL_BASE_BARS,
2103                 .num_ports      = 1,
2104                 .base_baud      = 460800,
2105                 .uart_offset    = 8,
2106         },
2107         [pbn_b0_bt_2_460800] = {
2108                 .flags          = FL_BASE0|FL_BASE_BARS,
2109                 .num_ports      = 2,
2110                 .base_baud      = 460800,
2111                 .uart_offset    = 8,
2112         },
2113         [pbn_b0_bt_4_460800] = {
2114                 .flags          = FL_BASE0|FL_BASE_BARS,
2115                 .num_ports      = 4,
2116                 .base_baud      = 460800,
2117                 .uart_offset    = 8,
2118         },
2119
2120         [pbn_b0_bt_1_921600] = {
2121                 .flags          = FL_BASE0|FL_BASE_BARS,
2122                 .num_ports      = 1,
2123                 .base_baud      = 921600,
2124                 .uart_offset    = 8,
2125         },
2126         [pbn_b0_bt_2_921600] = {
2127                 .flags          = FL_BASE0|FL_BASE_BARS,
2128                 .num_ports      = 2,
2129                 .base_baud      = 921600,
2130                 .uart_offset    = 8,
2131         },
2132         [pbn_b0_bt_4_921600] = {
2133                 .flags          = FL_BASE0|FL_BASE_BARS,
2134                 .num_ports      = 4,
2135                 .base_baud      = 921600,
2136                 .uart_offset    = 8,
2137         },
2138         [pbn_b0_bt_8_921600] = {
2139                 .flags          = FL_BASE0|FL_BASE_BARS,
2140                 .num_ports      = 8,
2141                 .base_baud      = 921600,
2142                 .uart_offset    = 8,
2143         },
2144
2145         [pbn_b1_1_115200] = {
2146                 .flags          = FL_BASE1,
2147                 .num_ports      = 1,
2148                 .base_baud      = 115200,
2149                 .uart_offset    = 8,
2150         },
2151         [pbn_b1_2_115200] = {
2152                 .flags          = FL_BASE1,
2153                 .num_ports      = 2,
2154                 .base_baud      = 115200,
2155                 .uart_offset    = 8,
2156         },
2157         [pbn_b1_4_115200] = {
2158                 .flags          = FL_BASE1,
2159                 .num_ports      = 4,
2160                 .base_baud      = 115200,
2161                 .uart_offset    = 8,
2162         },
2163         [pbn_b1_8_115200] = {
2164                 .flags          = FL_BASE1,
2165                 .num_ports      = 8,
2166                 .base_baud      = 115200,
2167                 .uart_offset    = 8,
2168         },
2169         [pbn_b1_16_115200] = {
2170                 .flags          = FL_BASE1,
2171                 .num_ports      = 16,
2172                 .base_baud      = 115200,
2173                 .uart_offset    = 8,
2174         },
2175
2176         [pbn_b1_1_921600] = {
2177                 .flags          = FL_BASE1,
2178                 .num_ports      = 1,
2179                 .base_baud      = 921600,
2180                 .uart_offset    = 8,
2181         },
2182         [pbn_b1_2_921600] = {
2183                 .flags          = FL_BASE1,
2184                 .num_ports      = 2,
2185                 .base_baud      = 921600,
2186                 .uart_offset    = 8,
2187         },
2188         [pbn_b1_4_921600] = {
2189                 .flags          = FL_BASE1,
2190                 .num_ports      = 4,
2191                 .base_baud      = 921600,
2192                 .uart_offset    = 8,
2193         },
2194         [pbn_b1_8_921600] = {
2195                 .flags          = FL_BASE1,
2196                 .num_ports      = 8,
2197                 .base_baud      = 921600,
2198                 .uart_offset    = 8,
2199         },
2200         [pbn_b1_2_1250000] = {
2201                 .flags          = FL_BASE1,
2202                 .num_ports      = 2,
2203                 .base_baud      = 1250000,
2204                 .uart_offset    = 8,
2205         },
2206
2207         [pbn_b1_bt_1_115200] = {
2208                 .flags          = FL_BASE1|FL_BASE_BARS,
2209                 .num_ports      = 1,
2210                 .base_baud      = 115200,
2211                 .uart_offset    = 8,
2212         },
2213         [pbn_b1_bt_2_115200] = {
2214                 .flags          = FL_BASE1|FL_BASE_BARS,
2215                 .num_ports      = 2,
2216                 .base_baud      = 115200,
2217                 .uart_offset    = 8,
2218         },
2219         [pbn_b1_bt_4_115200] = {
2220                 .flags          = FL_BASE1|FL_BASE_BARS,
2221                 .num_ports      = 4,
2222                 .base_baud      = 115200,
2223                 .uart_offset    = 8,
2224         },
2225
2226         [pbn_b1_bt_2_921600] = {
2227                 .flags          = FL_BASE1|FL_BASE_BARS,
2228                 .num_ports      = 2,
2229                 .base_baud      = 921600,
2230                 .uart_offset    = 8,
2231         },
2232
2233         [pbn_b1_1_1382400] = {
2234                 .flags          = FL_BASE1,
2235                 .num_ports      = 1,
2236                 .base_baud      = 1382400,
2237                 .uart_offset    = 8,
2238         },
2239         [pbn_b1_2_1382400] = {
2240                 .flags          = FL_BASE1,
2241                 .num_ports      = 2,
2242                 .base_baud      = 1382400,
2243                 .uart_offset    = 8,
2244         },
2245         [pbn_b1_4_1382400] = {
2246                 .flags          = FL_BASE1,
2247                 .num_ports      = 4,
2248                 .base_baud      = 1382400,
2249                 .uart_offset    = 8,
2250         },
2251         [pbn_b1_8_1382400] = {
2252                 .flags          = FL_BASE1,
2253                 .num_ports      = 8,
2254                 .base_baud      = 1382400,
2255                 .uart_offset    = 8,
2256         },
2257
2258         [pbn_b2_1_115200] = {
2259                 .flags          = FL_BASE2,
2260                 .num_ports      = 1,
2261                 .base_baud      = 115200,
2262                 .uart_offset    = 8,
2263         },
2264         [pbn_b2_2_115200] = {
2265                 .flags          = FL_BASE2,
2266                 .num_ports      = 2,
2267                 .base_baud      = 115200,
2268                 .uart_offset    = 8,
2269         },
2270         [pbn_b2_4_115200] = {
2271                 .flags          = FL_BASE2,
2272                 .num_ports      = 4,
2273                 .base_baud      = 115200,
2274                 .uart_offset    = 8,
2275         },
2276         [pbn_b2_8_115200] = {
2277                 .flags          = FL_BASE2,
2278                 .num_ports      = 8,
2279                 .base_baud      = 115200,
2280                 .uart_offset    = 8,
2281         },
2282
2283         [pbn_b2_1_460800] = {
2284                 .flags          = FL_BASE2,
2285                 .num_ports      = 1,
2286                 .base_baud      = 460800,
2287                 .uart_offset    = 8,
2288         },
2289         [pbn_b2_4_460800] = {
2290                 .flags          = FL_BASE2,
2291                 .num_ports      = 4,
2292                 .base_baud      = 460800,
2293                 .uart_offset    = 8,
2294         },
2295         [pbn_b2_8_460800] = {
2296                 .flags          = FL_BASE2,
2297                 .num_ports      = 8,
2298                 .base_baud      = 460800,
2299                 .uart_offset    = 8,
2300         },
2301         [pbn_b2_16_460800] = {
2302                 .flags          = FL_BASE2,
2303                 .num_ports      = 16,
2304                 .base_baud      = 460800,
2305                 .uart_offset    = 8,
2306          },
2307
2308         [pbn_b2_1_921600] = {
2309                 .flags          = FL_BASE2,
2310                 .num_ports      = 1,
2311                 .base_baud      = 921600,
2312                 .uart_offset    = 8,
2313         },
2314         [pbn_b2_4_921600] = {
2315                 .flags          = FL_BASE2,
2316                 .num_ports      = 4,
2317                 .base_baud      = 921600,
2318                 .uart_offset    = 8,
2319         },
2320         [pbn_b2_8_921600] = {
2321                 .flags          = FL_BASE2,
2322                 .num_ports      = 8,
2323                 .base_baud      = 921600,
2324                 .uart_offset    = 8,
2325         },
2326
2327         [pbn_b2_8_1152000] = {
2328                 .flags          = FL_BASE2,
2329                 .num_ports      = 8,
2330                 .base_baud      = 1152000,
2331                 .uart_offset    = 8,
2332         },
2333
2334         [pbn_b2_bt_1_115200] = {
2335                 .flags          = FL_BASE2|FL_BASE_BARS,
2336                 .num_ports      = 1,
2337                 .base_baud      = 115200,
2338                 .uart_offset    = 8,
2339         },
2340         [pbn_b2_bt_2_115200] = {
2341                 .flags          = FL_BASE2|FL_BASE_BARS,
2342                 .num_ports      = 2,
2343                 .base_baud      = 115200,
2344                 .uart_offset    = 8,
2345         },
2346         [pbn_b2_bt_4_115200] = {
2347                 .flags          = FL_BASE2|FL_BASE_BARS,
2348                 .num_ports      = 4,
2349                 .base_baud      = 115200,
2350                 .uart_offset    = 8,
2351         },
2352
2353         [pbn_b2_bt_2_921600] = {
2354                 .flags          = FL_BASE2|FL_BASE_BARS,
2355                 .num_ports      = 2,
2356                 .base_baud      = 921600,
2357                 .uart_offset    = 8,
2358         },
2359         [pbn_b2_bt_4_921600] = {
2360                 .flags          = FL_BASE2|FL_BASE_BARS,
2361                 .num_ports      = 4,
2362                 .base_baud      = 921600,
2363                 .uart_offset    = 8,
2364         },
2365
2366         [pbn_b3_2_115200] = {
2367                 .flags          = FL_BASE3,
2368                 .num_ports      = 2,
2369                 .base_baud      = 115200,
2370                 .uart_offset    = 8,
2371         },
2372         [pbn_b3_4_115200] = {
2373                 .flags          = FL_BASE3,
2374                 .num_ports      = 4,
2375                 .base_baud      = 115200,
2376                 .uart_offset    = 8,
2377         },
2378         [pbn_b3_8_115200] = {
2379                 .flags          = FL_BASE3,
2380                 .num_ports      = 8,
2381                 .base_baud      = 115200,
2382                 .uart_offset    = 8,
2383         },
2384
2385         [pbn_b4_bt_2_921600] = {
2386                 .flags          = FL_BASE4,
2387                 .num_ports      = 2,
2388                 .base_baud      = 921600,
2389                 .uart_offset    = 8,
2390         },
2391         [pbn_b4_bt_4_921600] = {
2392                 .flags          = FL_BASE4,
2393                 .num_ports      = 4,
2394                 .base_baud      = 921600,
2395                 .uart_offset    = 8,
2396         },
2397         [pbn_b4_bt_8_921600] = {
2398                 .flags          = FL_BASE4,
2399                 .num_ports      = 8,
2400                 .base_baud      = 921600,
2401                 .uart_offset    = 8,
2402         },
2403
2404         /*
2405          * Entries following this are board-specific.
2406          */
2407
2408         /*
2409          * Panacom - IOMEM
2410          */
2411         [pbn_panacom] = {
2412                 .flags          = FL_BASE2,
2413                 .num_ports      = 2,
2414                 .base_baud      = 921600,
2415                 .uart_offset    = 0x400,
2416                 .reg_shift      = 7,
2417         },
2418         [pbn_panacom2] = {
2419                 .flags          = FL_BASE2|FL_BASE_BARS,
2420                 .num_ports      = 2,
2421                 .base_baud      = 921600,
2422                 .uart_offset    = 0x400,
2423                 .reg_shift      = 7,
2424         },
2425         [pbn_panacom4] = {
2426                 .flags          = FL_BASE2|FL_BASE_BARS,
2427                 .num_ports      = 4,
2428                 .base_baud      = 921600,
2429                 .uart_offset    = 0x400,
2430                 .reg_shift      = 7,
2431         },
2432
2433         /* I think this entry is broken - the first_offset looks wrong --rmk */
2434         [pbn_plx_romulus] = {
2435                 .flags          = FL_BASE2,
2436                 .num_ports      = 4,
2437                 .base_baud      = 921600,
2438                 .uart_offset    = 8 << 2,
2439                 .reg_shift      = 2,
2440                 .first_offset   = 0x03,
2441         },
2442
2443         /*
2444          * This board uses the size of PCI Base region 0 to
2445          * signal now many ports are available
2446          */
2447         [pbn_oxsemi] = {
2448                 .flags          = FL_BASE0|FL_REGION_SZ_CAP,
2449                 .num_ports      = 32,
2450                 .base_baud      = 115200,
2451                 .uart_offset    = 8,
2452         },
2453         [pbn_oxsemi_1_4000000] = {
2454                 .flags          = FL_BASE0,
2455                 .num_ports      = 1,
2456                 .base_baud      = 4000000,
2457                 .uart_offset    = 0x200,
2458                 .first_offset   = 0x1000,
2459         },
2460         [pbn_oxsemi_2_4000000] = {
2461                 .flags          = FL_BASE0,
2462                 .num_ports      = 2,
2463                 .base_baud      = 4000000,
2464                 .uart_offset    = 0x200,
2465                 .first_offset   = 0x1000,
2466         },
2467         [pbn_oxsemi_4_4000000] = {
2468                 .flags          = FL_BASE0,
2469                 .num_ports      = 4,
2470                 .base_baud      = 4000000,
2471                 .uart_offset    = 0x200,
2472                 .first_offset   = 0x1000,
2473         },
2474         [pbn_oxsemi_8_4000000] = {
2475                 .flags          = FL_BASE0,
2476                 .num_ports      = 8,
2477                 .base_baud      = 4000000,
2478                 .uart_offset    = 0x200,
2479                 .first_offset   = 0x1000,
2480         },
2481
2482
2483         /*
2484          * EKF addition for i960 Boards form EKF with serial port.
2485          * Max 256 ports.
2486          */
2487         [pbn_intel_i960] = {
2488                 .flags          = FL_BASE0,
2489                 .num_ports      = 32,
2490                 .base_baud      = 921600,
2491                 .uart_offset    = 8 << 2,
2492                 .reg_shift      = 2,
2493                 .first_offset   = 0x10000,
2494         },
2495         [pbn_sgi_ioc3] = {
2496                 .flags          = FL_BASE0|FL_NOIRQ,
2497                 .num_ports      = 1,
2498                 .base_baud      = 458333,
2499                 .uart_offset    = 8,
2500                 .reg_shift      = 0,
2501                 .first_offset   = 0x20178,
2502         },
2503
2504         /*
2505          * Computone - uses IOMEM.
2506          */
2507         [pbn_computone_4] = {
2508                 .flags          = FL_BASE0,
2509                 .num_ports      = 4,
2510                 .base_baud      = 921600,
2511                 .uart_offset    = 0x40,
2512                 .reg_shift      = 2,
2513                 .first_offset   = 0x200,
2514         },
2515         [pbn_computone_6] = {
2516                 .flags          = FL_BASE0,
2517                 .num_ports      = 6,
2518                 .base_baud      = 921600,
2519                 .uart_offset    = 0x40,
2520                 .reg_shift      = 2,
2521                 .first_offset   = 0x200,
2522         },
2523         [pbn_computone_8] = {
2524                 .flags          = FL_BASE0,
2525                 .num_ports      = 8,
2526                 .base_baud      = 921600,
2527                 .uart_offset    = 0x40,
2528                 .reg_shift      = 2,
2529                 .first_offset   = 0x200,
2530         },
2531         [pbn_sbsxrsio] = {
2532                 .flags          = FL_BASE0,
2533                 .num_ports      = 8,
2534                 .base_baud      = 460800,
2535                 .uart_offset    = 256,
2536                 .reg_shift      = 4,
2537         },
2538         /*
2539          * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
2540          *  Only basic 16550A support.
2541          *  XR17C15[24] are not tested, but they should work.
2542          */
2543         [pbn_exar_XR17C152] = {
2544                 .flags          = FL_BASE0,
2545                 .num_ports      = 2,
2546                 .base_baud      = 921600,
2547                 .uart_offset    = 0x200,
2548         },
2549         [pbn_exar_XR17C154] = {
2550                 .flags          = FL_BASE0,
2551                 .num_ports      = 4,
2552                 .base_baud      = 921600,
2553                 .uart_offset    = 0x200,
2554         },
2555         [pbn_exar_XR17C158] = {
2556                 .flags          = FL_BASE0,
2557                 .num_ports      = 8,
2558                 .base_baud      = 921600,
2559                 .uart_offset    = 0x200,
2560         },
2561         [pbn_exar_ibm_saturn] = {
2562                 .flags          = FL_BASE0,
2563                 .num_ports      = 1,
2564                 .base_baud      = 921600,
2565                 .uart_offset    = 0x200,
2566         },
2567
2568         /*
2569          * PA Semi PWRficient PA6T-1682M on-chip UART
2570          */
2571         [pbn_pasemi_1682M] = {
2572                 .flags          = FL_BASE0,
2573                 .num_ports      = 1,
2574                 .base_baud      = 8333333,
2575         },
2576         /*
2577          * National Instruments 843x
2578          */
2579         [pbn_ni8430_16] = {
2580                 .flags          = FL_BASE0,
2581                 .num_ports      = 16,
2582                 .base_baud      = 3686400,
2583                 .uart_offset    = 0x10,
2584                 .first_offset   = 0x800,
2585         },
2586         [pbn_ni8430_8] = {
2587                 .flags          = FL_BASE0,
2588                 .num_ports      = 8,
2589                 .base_baud      = 3686400,
2590                 .uart_offset    = 0x10,
2591                 .first_offset   = 0x800,
2592         },
2593         [pbn_ni8430_4] = {
2594                 .flags          = FL_BASE0,
2595                 .num_ports      = 4,
2596                 .base_baud      = 3686400,
2597                 .uart_offset    = 0x10,
2598                 .first_offset   = 0x800,
2599         },
2600         [pbn_ni8430_2] = {
2601                 .flags          = FL_BASE0,
2602                 .num_ports      = 2,
2603                 .base_baud      = 3686400,
2604                 .uart_offset    = 0x10,
2605                 .first_offset   = 0x800,
2606         },
2607         /*
2608          * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
2609          */
2610         [pbn_ADDIDATA_PCIe_1_3906250] = {
2611                 .flags          = FL_BASE0,
2612                 .num_ports      = 1,
2613                 .base_baud      = 3906250,
2614                 .uart_offset    = 0x200,
2615                 .first_offset   = 0x1000,
2616         },
2617         [pbn_ADDIDATA_PCIe_2_3906250] = {
2618                 .flags          = FL_BASE0,
2619                 .num_ports      = 2,
2620                 .base_baud      = 3906250,
2621                 .uart_offset    = 0x200,
2622                 .first_offset   = 0x1000,
2623         },
2624         [pbn_ADDIDATA_PCIe_4_3906250] = {
2625                 .flags          = FL_BASE0,
2626                 .num_ports      = 4,
2627                 .base_baud      = 3906250,
2628                 .uart_offset    = 0x200,
2629                 .first_offset   = 0x1000,
2630         },
2631         [pbn_ADDIDATA_PCIe_8_3906250] = {
2632                 .flags          = FL_BASE0,
2633                 .num_ports      = 8,
2634                 .base_baud      = 3906250,
2635                 .uart_offset    = 0x200,
2636                 .first_offset   = 0x1000,
2637         },
2638         [pbn_ce4100_1_115200] = {
2639                 .flags          = FL_BASE0,
2640                 .num_ports      = 1,
2641                 .base_baud      = 921600,
2642                 .reg_shift      = 2,
2643         },
2644         [pbn_omegapci] = {
2645                 .flags          = FL_BASE0,
2646                 .num_ports      = 8,
2647                 .base_baud      = 115200,
2648                 .uart_offset    = 0x200,
2649         },
2650         [pbn_NETMOS9900_2s_115200] = {
2651                 .flags          = FL_BASE0,
2652                 .num_ports      = 2,
2653                 .base_baud      = 115200,
2654         },
2655 };
2656
2657 static const struct pci_device_id blacklist[] = {
2658         /* softmodems */
2659         { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
2660         { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
2661         { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
2662
2663         /* multi-io cards handled by parport_serial */
2664         { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */
2665 };
2666
2667 /*
2668  * Given a complete unknown PCI device, try to use some heuristics to
2669  * guess what the configuration might be, based on the pitiful PCI
2670  * serial specs.  Returns 0 on success, 1 on failure.
2671  */
2672 static int __devinit
2673 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
2674 {
2675         const struct pci_device_id *bldev;
2676         int num_iomem, num_port, first_port = -1, i;
2677
2678         /*
2679          * If it is not a communications device or the programming
2680          * interface is greater than 6, give up.
2681          *
2682          * (Should we try to make guesses for multiport serial devices
2683          * later?)
2684          */
2685         if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
2686              ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
2687             (dev->class & 0xff) > 6)
2688                 return -ENODEV;
2689
2690         /*
2691          * Do not access blacklisted devices that are known not to
2692          * feature serial ports or are handled by other modules.
2693          */
2694         for (bldev = blacklist;
2695              bldev < blacklist + ARRAY_SIZE(blacklist);
2696              bldev++) {
2697                 if (dev->vendor == bldev->vendor &&
2698                     dev->device == bldev->device)
2699                         return -ENODEV;
2700         }
2701
2702         num_iomem = num_port = 0;
2703         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2704                 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
2705                         num_port++;
2706                         if (first_port == -1)
2707                                 first_port = i;
2708                 }
2709                 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
2710                         num_iomem++;
2711         }
2712
2713         /*
2714          * If there is 1 or 0 iomem regions, and exactly one port,
2715          * use it.  We guess the number of ports based on the IO
2716          * region size.
2717          */
2718         if (num_iomem <= 1 && num_port == 1) {
2719                 board->flags = first_port;
2720                 board->num_ports = pci_resource_len(dev, first_port) / 8;
2721                 return 0;
2722         }
2723
2724         /*
2725          * Now guess if we've got a board which indexes by BARs.
2726          * Each IO BAR should be 8 bytes, and they should follow
2727          * consecutively.
2728          */
2729         first_port = -1;
2730         num_port = 0;
2731         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2732                 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
2733                     pci_resource_len(dev, i) == 8 &&
2734                     (first_port == -1 || (first_port + num_port) == i)) {
2735                         num_port++;
2736                         if (first_port == -1)
2737                                 first_port = i;
2738                 }
2739         }
2740
2741         if (num_port > 1) {
2742                 board->flags = first_port | FL_BASE_BARS;
2743                 board->num_ports = num_port;
2744                 return 0;
2745         }
2746
2747         return -ENODEV;
2748 }
2749
2750 static inline int
2751 serial_pci_matches(const struct pciserial_board *board,
2752                    const struct pciserial_board *guessed)
2753 {
2754         return
2755             board->num_ports == guessed->num_ports &&
2756             board->base_baud == guessed->base_baud &&
2757             board->uart_offset == guessed->uart_offset &&
2758             board->reg_shift == guessed->reg_shift &&
2759             board->first_offset == guessed->first_offset;
2760 }
2761
2762 struct serial_private *
2763 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
2764 {
2765         struct uart_8250_port uart;
2766         struct serial_private *priv;
2767         struct pci_serial_quirk *quirk;
2768         int rc, nr_ports, i;
2769
2770         nr_ports = board->num_ports;
2771
2772         /*
2773          * Find an init and setup quirks.
2774          */
2775         quirk = find_quirk(dev);
2776
2777         /*
2778          * Run the new-style initialization function.
2779          * The initialization function returns:
2780          *  <0  - error
2781          *   0  - use board->num_ports
2782          *  >0  - number of ports
2783          */
2784         if (quirk->init) {
2785                 rc = quirk->init(dev);
2786                 if (rc < 0) {
2787                         priv = ERR_PTR(rc);
2788                         goto err_out;
2789                 }
2790                 if (rc)
2791                         nr_ports = rc;
2792         }
2793
2794         priv = kzalloc(sizeof(struct serial_private) +
2795                        sizeof(unsigned int) * nr_ports,
2796                        GFP_KERNEL);
2797         if (!priv) {
2798                 priv = ERR_PTR(-ENOMEM);
2799                 goto err_deinit;
2800         }
2801
2802         priv->dev = dev;
2803         priv->quirk = quirk;
2804
2805         memset(&uart, 0, sizeof(uart));
2806         uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
2807         uart.port.uartclk = board->base_baud * 16;
2808         uart.port.irq = get_pci_irq(dev, board);
2809         uart.port.dev = &dev->dev;
2810
2811         for (i = 0; i < nr_ports; i++) {
2812                 if (quirk->setup(priv, board, &uart, i))
2813                         break;
2814
2815 #ifdef SERIAL_DEBUG_PCI
2816                 printk(KERN_DEBUG "Setup PCI port: port %lx, irq %d, type %d\n",
2817                        uart.port.iobase, uart.port.irq, uart.port.iotype);
2818 #endif
2819
2820                 priv->line[i] = serial8250_register_8250_port(&uart);
2821                 if (priv->line[i] < 0) {
2822                         printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
2823                         break;
2824                 }
2825         }
2826         priv->nr = i;
2827         return priv;
2828
2829 err_deinit:
2830         if (quirk->exit)
2831                 quirk->exit(dev);
2832 err_out:
2833         return priv;
2834 }
2835 EXPORT_SYMBOL_GPL(pciserial_init_ports);
2836
2837 void pciserial_remove_ports(struct serial_private *priv)
2838 {
2839         struct pci_serial_quirk *quirk;
2840         int i;
2841
2842         for (i = 0; i < priv->nr; i++)
2843                 serial8250_unregister_port(priv->line[i]);
2844
2845         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2846                 if (priv->remapped_bar[i])
2847                         iounmap(priv->remapped_bar[i]);
2848                 priv->remapped_bar[i] = NULL;
2849         }
2850
2851         /*
2852          * Find the exit quirks.
2853          */
2854         quirk = find_quirk(priv->dev);
2855         if (quirk->exit)
2856                 quirk->exit(priv->dev);
2857
2858         kfree(priv);
2859 }
2860 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
2861
2862 void pciserial_suspend_ports(struct serial_private *priv)
2863 {
2864         int i;
2865
2866         for (i = 0; i < priv->nr; i++)
2867                 if (priv->line[i] >= 0)
2868                         serial8250_suspend_port(priv->line[i]);
2869
2870         /*
2871          * Ensure that every init quirk is properly torn down
2872          */
2873         if (priv->quirk->exit)
2874                 priv->quirk->exit(priv->dev);
2875 }
2876 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
2877
2878 void pciserial_resume_ports(struct serial_private *priv)
2879 {
2880         int i;
2881
2882         /*
2883          * Ensure that the board is correctly configured.
2884          */
2885         if (priv->quirk->init)
2886                 priv->quirk->init(priv->dev);
2887
2888         for (i = 0; i < priv->nr; i++)
2889                 if (priv->line[i] >= 0)
2890                         serial8250_resume_port(priv->line[i]);
2891 }
2892 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
2893
2894 /*
2895  * Probe one serial board.  Unfortunately, there is no rhyme nor reason
2896  * to the arrangement of serial ports on a PCI card.
2897  */
2898 static int __devinit
2899 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
2900 {
2901         struct pci_serial_quirk *quirk;
2902         struct serial_private *priv;
2903         const struct pciserial_board *board;
2904         struct pciserial_board tmp;
2905         int rc;
2906
2907         quirk = find_quirk(dev);
2908         if (quirk->probe) {
2909                 rc = quirk->probe(dev);
2910                 if (rc)
2911                         return rc;
2912         }
2913
2914         if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
2915                 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
2916                         ent->driver_data);
2917                 return -EINVAL;
2918         }
2919
2920         board = &pci_boards[ent->driver_data];
2921
2922         rc = pci_enable_device(dev);
2923         pci_save_state(dev);
2924         if (rc)
2925                 return rc;
2926
2927         if (ent->driver_data == pbn_default) {
2928                 /*
2929                  * Use a copy of the pci_board entry for this;
2930                  * avoid changing entries in the table.
2931                  */
2932                 memcpy(&tmp, board, sizeof(struct pciserial_board));
2933                 board = &tmp;
2934
2935                 /*
2936                  * We matched one of our class entries.  Try to
2937                  * determine the parameters of this board.
2938                  */
2939                 rc = serial_pci_guess_board(dev, &tmp);
2940                 if (rc)
2941                         goto disable;
2942         } else {
2943                 /*
2944                  * We matched an explicit entry.  If we are able to
2945                  * detect this boards settings with our heuristic,
2946                  * then we no longer need this entry.
2947                  */
2948                 memcpy(&tmp, &pci_boards[pbn_default],
2949                        sizeof(struct pciserial_board));
2950                 rc = serial_pci_guess_board(dev, &tmp);
2951                 if (rc == 0 && serial_pci_matches(board, &tmp))
2952                         moan_device("Redundant entry in serial pci_table.",
2953                                     dev);
2954         }
2955
2956         priv = pciserial_init_ports(dev, board);
2957         if (!IS_ERR(priv)) {
2958                 pci_set_drvdata(dev, priv);
2959                 return 0;
2960         }
2961
2962         rc = PTR_ERR(priv);
2963
2964  disable:
2965         pci_disable_device(dev);
2966         return rc;
2967 }
2968
2969 static void __devexit pciserial_remove_one(struct pci_dev *dev)
2970 {
2971         struct serial_private *priv = pci_get_drvdata(dev);
2972
2973         pci_set_drvdata(dev, NULL);
2974
2975         pciserial_remove_ports(priv);
2976
2977         pci_disable_device(dev);
2978 }
2979
2980 #ifdef CONFIG_PM
2981 static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
2982 {
2983         struct serial_private *priv = pci_get_drvdata(dev);
2984
2985         if (priv)
2986                 pciserial_suspend_ports(priv);
2987
2988         pci_save_state(dev);
2989         pci_set_power_state(dev, pci_choose_state(dev, state));
2990         return 0;
2991 }
2992
2993 static int pciserial_resume_one(struct pci_dev *dev)
2994 {
2995         int err;
2996         struct serial_private *priv = pci_get_drvdata(dev);
2997
2998         pci_set_power_state(dev, PCI_D0);
2999         pci_restore_state(dev);
3000
3001         if (priv) {
3002                 /*
3003                  * The device may have been disabled.  Re-enable it.
3004                  */
3005                 err = pci_enable_device(dev);
3006                 /* FIXME: We cannot simply error out here */
3007                 if (err)
3008                         printk(KERN_ERR "pciserial: Unable to re-enable ports, trying to continue.\n");
3009                 pciserial_resume_ports(priv);
3010         }
3011         return 0;
3012 }
3013 #endif
3014
3015 static struct pci_device_id serial_pci_tbl[] = {
3016         /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
3017         {       PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
3018                 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
3019                 pbn_b2_8_921600 },
3020         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3021                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3022                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
3023                 pbn_b1_8_1382400 },
3024         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3025                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3026                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
3027                 pbn_b1_4_1382400 },
3028         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3029                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3030                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
3031                 pbn_b1_2_1382400 },
3032         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3033                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3034                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
3035                 pbn_b1_8_1382400 },
3036         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3037                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3038                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
3039                 pbn_b1_4_1382400 },
3040         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3041                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3042                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
3043                 pbn_b1_2_1382400 },
3044         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3045                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3046                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
3047                 pbn_b1_8_921600 },
3048         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3049                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3050                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
3051                 pbn_b1_8_921600 },
3052         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3053                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3054                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
3055                 pbn_b1_4_921600 },
3056         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3057                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3058                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
3059                 pbn_b1_4_921600 },
3060         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3061                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3062                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
3063                 pbn_b1_2_921600 },
3064         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3065                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3066                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
3067                 pbn_b1_8_921600 },
3068         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3069                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3070                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
3071                 pbn_b1_8_921600 },
3072         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3073                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3074                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
3075                 pbn_b1_4_921600 },
3076         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3077                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3078                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
3079                 pbn_b1_2_1250000 },
3080         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3081                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3082                 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
3083                 pbn_b0_2_1843200 },
3084         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3085                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3086                 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
3087                 pbn_b0_4_1843200 },
3088         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3089                 PCI_VENDOR_ID_AFAVLAB,
3090                 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
3091                 pbn_b0_4_1152000 },
3092         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3093                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3094                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
3095                 pbn_b0_2_1843200_200 },
3096         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3097                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3098                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
3099                 pbn_b0_4_1843200_200 },
3100         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3101                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3102                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
3103                 pbn_b0_8_1843200_200 },
3104         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3105                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3106                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
3107                 pbn_b0_2_1843200_200 },
3108         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3109                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3110                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
3111                 pbn_b0_4_1843200_200 },
3112         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3113                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3114                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
3115                 pbn_b0_8_1843200_200 },
3116         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3117                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3118                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
3119                 pbn_b0_2_1843200_200 },
3120         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3121                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3122                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
3123                 pbn_b0_4_1843200_200 },
3124         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3125                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3126                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
3127                 pbn_b0_8_1843200_200 },
3128         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3129                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3130                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
3131                 pbn_b0_2_1843200_200 },
3132         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3133                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3134                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
3135                 pbn_b0_4_1843200_200 },
3136         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3137                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3138                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
3139                 pbn_b0_8_1843200_200 },
3140         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3141                 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT,
3142                 0, 0, pbn_exar_ibm_saturn },
3143
3144         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
3145                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3146                 pbn_b2_bt_1_115200 },
3147         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
3148                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3149                 pbn_b2_bt_2_115200 },
3150         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
3151                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3152                 pbn_b2_bt_4_115200 },
3153         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
3154                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3155                 pbn_b2_bt_2_115200 },
3156         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
3157                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3158                 pbn_b2_bt_4_115200 },
3159         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
3160                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3161                 pbn_b2_8_115200 },
3162         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
3163                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3164                 pbn_b2_8_460800 },
3165         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
3166                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3167                 pbn_b2_8_115200 },
3168
3169         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
3170                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3171                 pbn_b2_bt_2_115200 },
3172         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
3173                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3174                 pbn_b2_bt_2_921600 },
3175         /*
3176          * VScom SPCOM800, from sl@s.pl
3177          */
3178         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
3179                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3180                 pbn_b2_8_921600 },
3181         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
3182                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3183                 pbn_b2_4_921600 },
3184         /* Unknown card - subdevice 0x1584 */
3185         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3186                 PCI_VENDOR_ID_PLX,
3187                 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
3188                 pbn_b0_4_115200 },
3189         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3190                 PCI_SUBVENDOR_ID_KEYSPAN,
3191                 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
3192                 pbn_panacom },
3193         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
3194                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3195                 pbn_panacom4 },
3196         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
3197                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3198                 pbn_panacom2 },
3199         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3200                 PCI_VENDOR_ID_ESDGMBH,
3201                 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
3202                 pbn_b2_4_115200 },
3203         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3204                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3205                 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
3206                 pbn_b2_4_460800 },
3207         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3208                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3209                 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
3210                 pbn_b2_8_460800 },
3211         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3212                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3213                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
3214                 pbn_b2_16_460800 },
3215         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3216                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3217                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
3218                 pbn_b2_16_460800 },
3219         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3220                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
3221                 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
3222                 pbn_b2_4_460800 },
3223         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3224                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
3225                 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
3226                 pbn_b2_8_460800 },
3227         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3228                 PCI_SUBVENDOR_ID_EXSYS,
3229                 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
3230                 pbn_b2_4_115200 },
3231         /*
3232          * Megawolf Romulus PCI Serial Card, from Mike Hudson
3233          * (Exoray@isys.ca)
3234          */
3235         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
3236                 0x10b5, 0x106a, 0, 0,
3237                 pbn_plx_romulus },
3238         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
3239                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3240                 pbn_b1_4_115200 },
3241         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
3242                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3243                 pbn_b1_2_115200 },
3244         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
3245                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3246                 pbn_b1_8_115200 },
3247         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
3248                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3249                 pbn_b1_8_115200 },
3250         {       PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
3251                 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
3252                 0, 0,
3253                 pbn_b0_4_921600 },
3254         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3255                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
3256                 0, 0,
3257                 pbn_b0_4_1152000 },
3258         {       PCI_VENDOR_ID_OXSEMI, 0x9505,
3259                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3260                 pbn_b0_bt_2_921600 },
3261
3262                 /*
3263                  * The below card is a little controversial since it is the
3264                  * subject of a PCI vendor/device ID clash.  (See
3265                  * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
3266                  * For now just used the hex ID 0x950a.
3267                  */
3268         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
3269                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_SERIAL, 0, 0,
3270                 pbn_b0_2_115200 },
3271         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
3272                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3273                 pbn_b0_2_1130000 },
3274         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
3275                 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
3276                 pbn_b0_1_921600 },
3277         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3278                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3279                 pbn_b0_4_115200 },
3280         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
3281                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3282                 pbn_b0_bt_2_921600 },
3283         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
3284                 PCI_ANY_ID , PCI_ANY_ID, 0, 0,
3285                 pbn_b2_8_1152000 },
3286
3287         /*
3288          * Oxford Semiconductor Inc. Tornado PCI express device range.
3289          */
3290         {       PCI_VENDOR_ID_OXSEMI, 0xc101,    /* OXPCIe952 1 Legacy UART */
3291                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3292                 pbn_b0_1_4000000 },
3293         {       PCI_VENDOR_ID_OXSEMI, 0xc105,    /* OXPCIe952 1 Legacy UART */
3294                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3295                 pbn_b0_1_4000000 },
3296         {       PCI_VENDOR_ID_OXSEMI, 0xc11b,    /* OXPCIe952 1 Native UART */
3297                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3298                 pbn_oxsemi_1_4000000 },
3299         {       PCI_VENDOR_ID_OXSEMI, 0xc11f,    /* OXPCIe952 1 Native UART */
3300                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3301                 pbn_oxsemi_1_4000000 },
3302         {       PCI_VENDOR_ID_OXSEMI, 0xc120,    /* OXPCIe952 1 Legacy UART */
3303                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3304                 pbn_b0_1_4000000 },
3305         {       PCI_VENDOR_ID_OXSEMI, 0xc124,    /* OXPCIe952 1 Legacy UART */
3306                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3307                 pbn_b0_1_4000000 },
3308         {       PCI_VENDOR_ID_OXSEMI, 0xc138,    /* OXPCIe952 1 Native UART */
3309                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3310                 pbn_oxsemi_1_4000000 },
3311         {       PCI_VENDOR_ID_OXSEMI, 0xc13d,    /* OXPCIe952 1 Native UART */
3312                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3313                 pbn_oxsemi_1_4000000 },
3314         {       PCI_VENDOR_ID_OXSEMI, 0xc140,    /* OXPCIe952 1 Legacy UART */
3315                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3316                 pbn_b0_1_4000000 },
3317         {       PCI_VENDOR_ID_OXSEMI, 0xc141,    /* OXPCIe952 1 Legacy UART */
3318                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3319                 pbn_b0_1_4000000 },
3320         {       PCI_VENDOR_ID_OXSEMI, 0xc144,    /* OXPCIe952 1 Legacy UART */
3321                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3322                 pbn_b0_1_4000000 },
3323         {       PCI_VENDOR_ID_OXSEMI, 0xc145,    /* OXPCIe952 1 Legacy UART */
3324                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3325                 pbn_b0_1_4000000 },
3326         {       PCI_VENDOR_ID_OXSEMI, 0xc158,    /* OXPCIe952 2 Native UART */
3327                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3328                 pbn_oxsemi_2_4000000 },
3329         {       PCI_VENDOR_ID_OXSEMI, 0xc15d,    /* OXPCIe952 2 Native UART */
3330                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3331                 pbn_oxsemi_2_4000000 },
3332         {       PCI_VENDOR_ID_OXSEMI, 0xc208,    /* OXPCIe954 4 Native UART */
3333                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3334                 pbn_oxsemi_4_4000000 },
3335         {       PCI_VENDOR_ID_OXSEMI, 0xc20d,    /* OXPCIe954 4 Native UART */
3336                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3337                 pbn_oxsemi_4_4000000 },
3338         {       PCI_VENDOR_ID_OXSEMI, 0xc308,    /* OXPCIe958 8 Native UART */
3339                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3340                 pbn_oxsemi_8_4000000 },
3341         {       PCI_VENDOR_ID_OXSEMI, 0xc30d,    /* OXPCIe958 8 Native UART */
3342                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3343                 pbn_oxsemi_8_4000000 },
3344         {       PCI_VENDOR_ID_OXSEMI, 0xc40b,    /* OXPCIe200 1 Native UART */
3345                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3346                 pbn_oxsemi_1_4000000 },
3347         {       PCI_VENDOR_ID_OXSEMI, 0xc40f,    /* OXPCIe200 1 Native UART */
3348                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3349                 pbn_oxsemi_1_4000000 },
3350         {       PCI_VENDOR_ID_OXSEMI, 0xc41b,    /* OXPCIe200 1 Native UART */
3351                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3352                 pbn_oxsemi_1_4000000 },
3353         {       PCI_VENDOR_ID_OXSEMI, 0xc41f,    /* OXPCIe200 1 Native UART */
3354                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3355                 pbn_oxsemi_1_4000000 },
3356         {       PCI_VENDOR_ID_OXSEMI, 0xc42b,    /* OXPCIe200 1 Native UART */
3357                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3358                 pbn_oxsemi_1_4000000 },
3359         {       PCI_VENDOR_ID_OXSEMI, 0xc42f,    /* OXPCIe200 1 Native UART */
3360                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3361                 pbn_oxsemi_1_4000000 },
3362         {       PCI_VENDOR_ID_OXSEMI, 0xc43b,    /* OXPCIe200 1 Native UART */
3363                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3364                 pbn_oxsemi_1_4000000 },
3365         {       PCI_VENDOR_ID_OXSEMI, 0xc43f,    /* OXPCIe200 1 Native UART */
3366                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3367                 pbn_oxsemi_1_4000000 },
3368         {       PCI_VENDOR_ID_OXSEMI, 0xc44b,    /* OXPCIe200 1 Native UART */
3369                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3370                 pbn_oxsemi_1_4000000 },
3371         {       PCI_VENDOR_ID_OXSEMI, 0xc44f,    /* OXPCIe200 1 Native UART */
3372                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3373                 pbn_oxsemi_1_4000000 },
3374         {       PCI_VENDOR_ID_OXSEMI, 0xc45b,    /* OXPCIe200 1 Native UART */
3375                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3376                 pbn_oxsemi_1_4000000 },
3377         {       PCI_VENDOR_ID_OXSEMI, 0xc45f,    /* OXPCIe200 1 Native UART */
3378                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3379                 pbn_oxsemi_1_4000000 },
3380         {       PCI_VENDOR_ID_OXSEMI, 0xc46b,    /* OXPCIe200 1 Native UART */
3381                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3382                 pbn_oxsemi_1_4000000 },
3383         {       PCI_VENDOR_ID_OXSEMI, 0xc46f,    /* OXPCIe200 1 Native UART */
3384                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3385                 pbn_oxsemi_1_4000000 },
3386         {       PCI_VENDOR_ID_OXSEMI, 0xc47b,    /* OXPCIe200 1 Native UART */
3387                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3388                 pbn_oxsemi_1_4000000 },
3389         {       PCI_VENDOR_ID_OXSEMI, 0xc47f,    /* OXPCIe200 1 Native UART */
3390                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3391                 pbn_oxsemi_1_4000000 },
3392         {       PCI_VENDOR_ID_OXSEMI, 0xc48b,    /* OXPCIe200 1 Native UART */
3393                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3394                 pbn_oxsemi_1_4000000 },
3395         {       PCI_VENDOR_ID_OXSEMI, 0xc48f,    /* OXPCIe200 1 Native UART */
3396                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3397                 pbn_oxsemi_1_4000000 },
3398         {       PCI_VENDOR_ID_OXSEMI, 0xc49b,    /* OXPCIe200 1 Native UART */
3399                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3400                 pbn_oxsemi_1_4000000 },
3401         {       PCI_VENDOR_ID_OXSEMI, 0xc49f,    /* OXPCIe200 1 Native UART */
3402                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3403                 pbn_oxsemi_1_4000000 },
3404         {       PCI_VENDOR_ID_OXSEMI, 0xc4ab,    /* OXPCIe200 1 Native UART */
3405                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3406                 pbn_oxsemi_1_4000000 },
3407         {       PCI_VENDOR_ID_OXSEMI, 0xc4af,    /* OXPCIe200 1 Native UART */
3408                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3409                 pbn_oxsemi_1_4000000 },
3410         {       PCI_VENDOR_ID_OXSEMI, 0xc4bb,    /* OXPCIe200 1 Native UART */
3411                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3412                 pbn_oxsemi_1_4000000 },
3413         {       PCI_VENDOR_ID_OXSEMI, 0xc4bf,    /* OXPCIe200 1 Native UART */
3414                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3415                 pbn_oxsemi_1_4000000 },
3416         {       PCI_VENDOR_ID_OXSEMI, 0xc4cb,    /* OXPCIe200 1 Native UART */
3417                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3418                 pbn_oxsemi_1_4000000 },
3419         {       PCI_VENDOR_ID_OXSEMI, 0xc4cf,    /* OXPCIe200 1 Native UART */
3420                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3421                 pbn_oxsemi_1_4000000 },
3422         /*
3423          * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
3424          */
3425         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
3426                 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
3427                 pbn_oxsemi_1_4000000 },
3428         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
3429                 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
3430                 pbn_oxsemi_2_4000000 },
3431         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
3432                 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
3433                 pbn_oxsemi_4_4000000 },
3434         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
3435                 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
3436                 pbn_oxsemi_8_4000000 },
3437
3438         /*
3439          * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
3440          */
3441         {       PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
3442                 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
3443                 pbn_oxsemi_2_4000000 },
3444
3445         /*
3446          * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
3447          * from skokodyn@yahoo.com
3448          */
3449         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3450                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
3451                 pbn_sbsxrsio },
3452         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3453                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
3454                 pbn_sbsxrsio },
3455         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3456                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
3457                 pbn_sbsxrsio },
3458         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3459                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
3460                 pbn_sbsxrsio },
3461
3462         /*
3463          * Digitan DS560-558, from jimd@esoft.com
3464          */
3465         {       PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
3466                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3467                 pbn_b1_1_115200 },
3468
3469         /*
3470          * Titan Electronic cards
3471          *  The 400L and 800L have a custom setup quirk.
3472          */
3473         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
3474                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3475                 pbn_b0_1_921600 },
3476         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
3477                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3478                 pbn_b0_2_921600 },
3479         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
3480                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3481                 pbn_b0_4_921600 },
3482         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
3483                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3484                 pbn_b0_4_921600 },
3485         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
3486                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3487                 pbn_b1_1_921600 },
3488         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
3489                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3490                 pbn_b1_bt_2_921600 },
3491         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
3492                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3493                 pbn_b0_bt_4_921600 },
3494         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
3495                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3496                 pbn_b0_bt_8_921600 },
3497         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
3498                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3499                 pbn_b4_bt_2_921600 },
3500         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
3501                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3502                 pbn_b4_bt_4_921600 },
3503         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
3504                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3505                 pbn_b4_bt_8_921600 },
3506         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
3507                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3508                 pbn_b0_4_921600 },
3509         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
3510                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3511                 pbn_b0_4_921600 },
3512         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
3513                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3514                 pbn_b0_4_921600 },
3515         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
3516                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3517                 pbn_oxsemi_1_4000000 },
3518         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
3519                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3520                 pbn_oxsemi_2_4000000 },
3521         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
3522                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3523                 pbn_oxsemi_4_4000000 },
3524         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
3525                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3526                 pbn_oxsemi_8_4000000 },
3527         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
3528                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3529                 pbn_oxsemi_2_4000000 },
3530         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
3531                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3532                 pbn_oxsemi_2_4000000 },
3533         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
3534                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3535                 pbn_b0_4_921600 },
3536         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
3537                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3538                 pbn_b0_4_921600 },
3539         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
3540                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3541                 pbn_b0_4_921600 },
3542         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
3543                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3544                 pbn_b0_4_921600 },
3545
3546         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
3547                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3548                 pbn_b2_1_460800 },
3549         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
3550                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3551                 pbn_b2_1_460800 },
3552         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
3553                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3554                 pbn_b2_1_460800 },
3555         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
3556                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3557                 pbn_b2_bt_2_921600 },
3558         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
3559                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3560                 pbn_b2_bt_2_921600 },
3561         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
3562                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3563                 pbn_b2_bt_2_921600 },
3564         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
3565                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3566                 pbn_b2_bt_4_921600 },
3567         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
3568                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3569                 pbn_b2_bt_4_921600 },
3570         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
3571                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3572                 pbn_b2_bt_4_921600 },
3573         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
3574                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3575                 pbn_b0_1_921600 },
3576         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
3577                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3578                 pbn_b0_1_921600 },
3579         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
3580                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3581                 pbn_b0_1_921600 },
3582         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
3583                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3584                 pbn_b0_bt_2_921600 },
3585         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
3586                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3587                 pbn_b0_bt_2_921600 },
3588         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
3589                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3590                 pbn_b0_bt_2_921600 },
3591         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
3592                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3593                 pbn_b0_bt_4_921600 },
3594         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
3595                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3596                 pbn_b0_bt_4_921600 },
3597         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
3598                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3599                 pbn_b0_bt_4_921600 },
3600         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
3601                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3602                 pbn_b0_bt_8_921600 },
3603         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
3604                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3605                 pbn_b0_bt_8_921600 },
3606         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
3607                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3608                 pbn_b0_bt_8_921600 },
3609
3610         /*
3611          * Computone devices submitted by Doug McNash dmcnash@computone.com
3612          */
3613         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3614                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
3615                 0, 0, pbn_computone_4 },
3616         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3617                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
3618                 0, 0, pbn_computone_8 },
3619         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3620                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
3621                 0, 0, pbn_computone_6 },
3622
3623         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
3624                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3625                 pbn_oxsemi },
3626         {       PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
3627                 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
3628                 pbn_b0_bt_1_921600 },
3629
3630         /*
3631          * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
3632          */
3633         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
3634                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3635                 pbn_b0_bt_8_115200 },
3636         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
3637                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3638                 pbn_b0_bt_8_115200 },
3639
3640         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
3641                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3642                 pbn_b0_bt_2_115200 },
3643         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
3644                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3645                 pbn_b0_bt_2_115200 },
3646         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
3647                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3648                 pbn_b0_bt_2_115200 },
3649         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
3650                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3651                 pbn_b0_bt_2_115200 },
3652         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
3653                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3654                 pbn_b0_bt_2_115200 },
3655         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
3656                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3657                 pbn_b0_bt_4_460800 },
3658         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
3659                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3660                 pbn_b0_bt_4_460800 },
3661         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
3662                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3663                 pbn_b0_bt_2_460800 },
3664         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
3665                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3666                 pbn_b0_bt_2_460800 },
3667         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
3668                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3669                 pbn_b0_bt_2_460800 },
3670         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
3671                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3672                 pbn_b0_bt_1_115200 },
3673         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
3674                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3675                 pbn_b0_bt_1_460800 },
3676
3677         /*
3678          * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
3679          * Cards are identified by their subsystem vendor IDs, which
3680          * (in hex) match the model number.
3681          *
3682          * Note that JC140x are RS422/485 cards which require ox950
3683          * ACR = 0x10, and as such are not currently fully supported.
3684          */
3685         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3686                 0x1204, 0x0004, 0, 0,
3687                 pbn_b0_4_921600 },
3688         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3689                 0x1208, 0x0004, 0, 0,
3690                 pbn_b0_4_921600 },
3691 /*      {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3692                 0x1402, 0x0002, 0, 0,
3693                 pbn_b0_2_921600 }, */
3694 /*      {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3695                 0x1404, 0x0004, 0, 0,
3696                 pbn_b0_4_921600 }, */
3697         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
3698                 0x1208, 0x0004, 0, 0,
3699                 pbn_b0_4_921600 },
3700
3701         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
3702                 0x1204, 0x0004, 0, 0,
3703                 pbn_b0_4_921600 },
3704         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
3705                 0x1208, 0x0004, 0, 0,
3706                 pbn_b0_4_921600 },
3707         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
3708                 0x1208, 0x0004, 0, 0,
3709                 pbn_b0_4_921600 },
3710         /*
3711          * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
3712          */
3713         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
3714                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3715                 pbn_b1_1_1382400 },
3716
3717         /*
3718          * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
3719          */
3720         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
3721                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3722                 pbn_b1_1_1382400 },
3723
3724         /*
3725          * RAStel 2 port modem, gerg@moreton.com.au
3726          */
3727         {       PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
3728                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3729                 pbn_b2_bt_2_115200 },
3730
3731         /*
3732          * EKF addition for i960 Boards form EKF with serial port
3733          */
3734         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
3735                 0xE4BF, PCI_ANY_ID, 0, 0,
3736                 pbn_intel_i960 },
3737
3738         /*
3739          * Xircom Cardbus/Ethernet combos
3740          */
3741         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
3742                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3743                 pbn_b0_1_115200 },
3744         /*
3745          * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
3746          */
3747         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
3748                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3749                 pbn_b0_1_115200 },
3750
3751         /*
3752          * Untested PCI modems, sent in from various folks...
3753          */
3754
3755         /*
3756          * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
3757          */
3758         {       PCI_VENDOR_ID_ROCKWELL, 0x1004,
3759                 0x1048, 0x1500, 0, 0,
3760                 pbn_b1_1_115200 },
3761
3762         {       PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
3763                 0xFF00, 0, 0, 0,
3764                 pbn_sgi_ioc3 },
3765
3766         /*
3767          * HP Diva card
3768          */
3769         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
3770                 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
3771                 pbn_b1_1_115200 },
3772         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
3773                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3774                 pbn_b0_5_115200 },
3775         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
3776                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3777                 pbn_b2_1_115200 },
3778
3779         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
3780                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3781                 pbn_b3_2_115200 },
3782         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
3783                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3784                 pbn_b3_4_115200 },
3785         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
3786                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3787                 pbn_b3_8_115200 },
3788
3789         /*
3790          * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3791          */
3792         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3793                 PCI_ANY_ID, PCI_ANY_ID,
3794                 0,
3795                 0, pbn_exar_XR17C152 },
3796         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3797                 PCI_ANY_ID, PCI_ANY_ID,
3798                 0,
3799                 0, pbn_exar_XR17C154 },
3800         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3801                 PCI_ANY_ID, PCI_ANY_ID,
3802                 0,
3803                 0, pbn_exar_XR17C158 },
3804
3805         /*
3806          * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
3807          */
3808         {       PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
3809                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3810                 pbn_b0_1_115200 },
3811         /*
3812          * ITE
3813          */
3814         {       PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
3815                 PCI_ANY_ID, PCI_ANY_ID,
3816                 0, 0,
3817                 pbn_b1_bt_1_115200 },
3818
3819         /*
3820          * IntaShield IS-200
3821          */
3822         {       PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
3823                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,   /* 135a.0811 */
3824                 pbn_b2_2_115200 },
3825         /*
3826          * IntaShield IS-400
3827          */
3828         {       PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
3829                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,    /* 135a.0dc0 */
3830                 pbn_b2_4_115200 },
3831         /*
3832          * Perle PCI-RAS cards
3833          */
3834         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3835                 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
3836                 0, 0, pbn_b2_4_921600 },
3837         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3838                 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
3839                 0, 0, pbn_b2_8_921600 },
3840
3841         /*
3842          * Mainpine series cards: Fairly standard layout but fools
3843          * parts of the autodetect in some cases and uses otherwise
3844          * unmatched communications subclasses in the PCI Express case
3845          */
3846
3847         {       /* RockForceDUO */
3848                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3849                 PCI_VENDOR_ID_MAINPINE, 0x0200,
3850                 0, 0, pbn_b0_2_115200 },
3851         {       /* RockForceQUATRO */
3852                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3853                 PCI_VENDOR_ID_MAINPINE, 0x0300,
3854                 0, 0, pbn_b0_4_115200 },
3855         {       /* RockForceDUO+ */
3856                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3857                 PCI_VENDOR_ID_MAINPINE, 0x0400,
3858                 0, 0, pbn_b0_2_115200 },
3859         {       /* RockForceQUATRO+ */
3860                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3861                 PCI_VENDOR_ID_MAINPINE, 0x0500,
3862                 0, 0, pbn_b0_4_115200 },
3863         {       /* RockForce+ */
3864                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3865                 PCI_VENDOR_ID_MAINPINE, 0x0600,
3866                 0, 0, pbn_b0_2_115200 },
3867         {       /* RockForce+ */
3868                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3869                 PCI_VENDOR_ID_MAINPINE, 0x0700,
3870                 0, 0, pbn_b0_4_115200 },
3871         {       /* RockForceOCTO+ */
3872                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3873                 PCI_VENDOR_ID_MAINPINE, 0x0800,
3874                 0, 0, pbn_b0_8_115200 },
3875         {       /* RockForceDUO+ */
3876                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3877                 PCI_VENDOR_ID_MAINPINE, 0x0C00,
3878                 0, 0, pbn_b0_2_115200 },
3879         {       /* RockForceQUARTRO+ */
3880                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3881                 PCI_VENDOR_ID_MAINPINE, 0x0D00,
3882                 0, 0, pbn_b0_4_115200 },
3883         {       /* RockForceOCTO+ */
3884                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3885                 PCI_VENDOR_ID_MAINPINE, 0x1D00,
3886                 0, 0, pbn_b0_8_115200 },
3887         {       /* RockForceD1 */
3888                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3889                 PCI_VENDOR_ID_MAINPINE, 0x2000,
3890                 0, 0, pbn_b0_1_115200 },
3891         {       /* RockForceF1 */
3892                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3893                 PCI_VENDOR_ID_MAINPINE, 0x2100,
3894                 0, 0, pbn_b0_1_115200 },
3895         {       /* RockForceD2 */
3896                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3897                 PCI_VENDOR_ID_MAINPINE, 0x2200,
3898                 0, 0, pbn_b0_2_115200 },
3899         {       /* RockForceF2 */
3900                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3901                 PCI_VENDOR_ID_MAINPINE, 0x2300,
3902                 0, 0, pbn_b0_2_115200 },
3903         {       /* RockForceD4 */
3904                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3905                 PCI_VENDOR_ID_MAINPINE, 0x2400,
3906                 0, 0, pbn_b0_4_115200 },
3907         {       /* RockForceF4 */
3908                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3909                 PCI_VENDOR_ID_MAINPINE, 0x2500,
3910                 0, 0, pbn_b0_4_115200 },
3911         {       /* RockForceD8 */
3912                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3913                 PCI_VENDOR_ID_MAINPINE, 0x2600,
3914                 0, 0, pbn_b0_8_115200 },
3915         {       /* RockForceF8 */
3916                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3917                 PCI_VENDOR_ID_MAINPINE, 0x2700,
3918                 0, 0, pbn_b0_8_115200 },
3919         {       /* IQ Express D1 */
3920                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3921                 PCI_VENDOR_ID_MAINPINE, 0x3000,
3922                 0, 0, pbn_b0_1_115200 },
3923         {       /* IQ Express F1 */
3924                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3925                 PCI_VENDOR_ID_MAINPINE, 0x3100,
3926                 0, 0, pbn_b0_1_115200 },
3927         {       /* IQ Express D2 */
3928                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3929                 PCI_VENDOR_ID_MAINPINE, 0x3200,
3930                 0, 0, pbn_b0_2_115200 },
3931         {       /* IQ Express F2 */
3932                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3933                 PCI_VENDOR_ID_MAINPINE, 0x3300,
3934                 0, 0, pbn_b0_2_115200 },
3935         {       /* IQ Express D4 */
3936                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3937                 PCI_VENDOR_ID_MAINPINE, 0x3400,
3938                 0, 0, pbn_b0_4_115200 },
3939         {       /* IQ Express F4 */
3940                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3941                 PCI_VENDOR_ID_MAINPINE, 0x3500,
3942                 0, 0, pbn_b0_4_115200 },
3943         {       /* IQ Express D8 */
3944                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3945                 PCI_VENDOR_ID_MAINPINE, 0x3C00,
3946                 0, 0, pbn_b0_8_115200 },
3947         {       /* IQ Express F8 */
3948                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3949                 PCI_VENDOR_ID_MAINPINE, 0x3D00,
3950                 0, 0, pbn_b0_8_115200 },
3951
3952
3953         /*
3954          * PA Semi PA6T-1682M on-chip UART
3955          */
3956         {       PCI_VENDOR_ID_PASEMI, 0xa004,
3957                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3958                 pbn_pasemi_1682M },
3959
3960         /*
3961          * National Instruments
3962          */
3963         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
3964                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3965                 pbn_b1_16_115200 },
3966         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
3967                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3968                 pbn_b1_8_115200 },
3969         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
3970                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3971                 pbn_b1_bt_4_115200 },
3972         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
3973                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3974                 pbn_b1_bt_2_115200 },
3975         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
3976                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3977                 pbn_b1_bt_4_115200 },
3978         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
3979                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3980                 pbn_b1_bt_2_115200 },
3981         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
3982                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3983                 pbn_b1_16_115200 },
3984         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
3985                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3986                 pbn_b1_8_115200 },
3987         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
3988                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3989                 pbn_b1_bt_4_115200 },
3990         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
3991                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3992                 pbn_b1_bt_2_115200 },
3993         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
3994                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3995                 pbn_b1_bt_4_115200 },
3996         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
3997                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3998                 pbn_b1_bt_2_115200 },
3999         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
4000                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4001                 pbn_ni8430_2 },
4002         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
4003                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4004                 pbn_ni8430_2 },
4005         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
4006                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4007                 pbn_ni8430_4 },
4008         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
4009                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4010                 pbn_ni8430_4 },
4011         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
4012                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4013                 pbn_ni8430_8 },
4014         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
4015                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4016                 pbn_ni8430_8 },
4017         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
4018                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4019                 pbn_ni8430_16 },
4020         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
4021                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4022                 pbn_ni8430_16 },
4023         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
4024                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4025                 pbn_ni8430_2 },
4026         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
4027                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4028                 pbn_ni8430_2 },
4029         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
4030                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4031                 pbn_ni8430_4 },
4032         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
4033                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4034                 pbn_ni8430_4 },
4035
4036         /*
4037         * ADDI-DATA GmbH communication cards <info@addi-data.com>
4038         */
4039         {       PCI_VENDOR_ID_ADDIDATA,
4040                 PCI_DEVICE_ID_ADDIDATA_APCI7500,
4041                 PCI_ANY_ID,
4042                 PCI_ANY_ID,
4043                 0,
4044                 0,
4045                 pbn_b0_4_115200 },
4046
4047         {       PCI_VENDOR_ID_ADDIDATA,
4048                 PCI_DEVICE_ID_ADDIDATA_APCI7420,
4049                 PCI_ANY_ID,
4050                 PCI_ANY_ID,
4051                 0,
4052                 0,
4053                 pbn_b0_2_115200 },
4054
4055         {       PCI_VENDOR_ID_ADDIDATA,
4056                 PCI_DEVICE_ID_ADDIDATA_APCI7300,
4057                 PCI_ANY_ID,
4058                 PCI_ANY_ID,
4059                 0,
4060                 0,
4061                 pbn_b0_1_115200 },
4062
4063         {       PCI_VENDOR_ID_ADDIDATA_OLD,
4064                 PCI_DEVICE_ID_ADDIDATA_APCI7800,
4065                 PCI_ANY_ID,
4066                 PCI_ANY_ID,
4067                 0,
4068                 0,
4069                 pbn_b1_8_115200 },
4070
4071         {       PCI_VENDOR_ID_ADDIDATA,
4072                 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
4073                 PCI_ANY_ID,
4074                 PCI_ANY_ID,
4075                 0,
4076                 0,
4077                 pbn_b0_4_115200 },
4078
4079         {       PCI_VENDOR_ID_ADDIDATA,
4080                 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
4081                 PCI_ANY_ID,
4082                 PCI_ANY_ID,
4083                 0,
4084                 0,
4085                 pbn_b0_2_115200 },
4086
4087         {       PCI_VENDOR_ID_ADDIDATA,
4088                 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
4089                 PCI_ANY_ID,
4090                 PCI_ANY_ID,
4091                 0,
4092                 0,
4093                 pbn_b0_1_115200 },
4094
4095         {       PCI_VENDOR_ID_ADDIDATA,
4096                 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
4097                 PCI_ANY_ID,
4098                 PCI_ANY_ID,
4099                 0,
4100                 0,
4101                 pbn_b0_4_115200 },
4102
4103         {       PCI_VENDOR_ID_ADDIDATA,
4104                 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
4105                 PCI_ANY_ID,
4106                 PCI_ANY_ID,
4107                 0,
4108                 0,
4109                 pbn_b0_2_115200 },
4110
4111         {       PCI_VENDOR_ID_ADDIDATA,
4112                 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
4113                 PCI_ANY_ID,
4114                 PCI_ANY_ID,
4115                 0,
4116                 0,
4117                 pbn_b0_1_115200 },
4118
4119         {       PCI_VENDOR_ID_ADDIDATA,
4120                 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
4121                 PCI_ANY_ID,
4122                 PCI_ANY_ID,
4123                 0,
4124                 0,
4125                 pbn_b0_8_115200 },
4126
4127         {       PCI_VENDOR_ID_ADDIDATA,
4128                 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
4129                 PCI_ANY_ID,
4130                 PCI_ANY_ID,
4131                 0,
4132                 0,
4133                 pbn_ADDIDATA_PCIe_4_3906250 },
4134
4135         {       PCI_VENDOR_ID_ADDIDATA,
4136                 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
4137                 PCI_ANY_ID,
4138                 PCI_ANY_ID,
4139                 0,
4140                 0,
4141                 pbn_ADDIDATA_PCIe_2_3906250 },
4142
4143         {       PCI_VENDOR_ID_ADDIDATA,
4144                 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
4145                 PCI_ANY_ID,
4146                 PCI_ANY_ID,
4147                 0,
4148                 0,
4149                 pbn_ADDIDATA_PCIe_1_3906250 },
4150
4151         {       PCI_VENDOR_ID_ADDIDATA,
4152                 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
4153                 PCI_ANY_ID,
4154                 PCI_ANY_ID,
4155                 0,
4156                 0,
4157                 pbn_ADDIDATA_PCIe_8_3906250 },
4158
4159         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
4160                 PCI_VENDOR_ID_IBM, 0x0299,
4161                 0, 0, pbn_b0_bt_2_115200 },
4162
4163         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
4164                 0xA000, 0x1000,
4165                 0, 0, pbn_b0_1_115200 },
4166
4167         /* the 9901 is a rebranded 9912 */
4168         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
4169                 0xA000, 0x1000,
4170                 0, 0, pbn_b0_1_115200 },
4171
4172         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
4173                 0xA000, 0x1000,
4174                 0, 0, pbn_b0_1_115200 },
4175
4176         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
4177                 0xA000, 0x1000,
4178                 0, 0, pbn_b0_1_115200 },
4179
4180         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
4181                 0xA000, 0x1000,
4182                 0, 0, pbn_b0_1_115200 },
4183
4184         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
4185                 0xA000, 0x3002,
4186                 0, 0, pbn_NETMOS9900_2s_115200 },
4187
4188         /*
4189          * Best Connectivity and Rosewill PCI Multi I/O cards
4190          */
4191
4192         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
4193                 0xA000, 0x1000,
4194                 0, 0, pbn_b0_1_115200 },
4195
4196         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
4197                 0xA000, 0x3002,
4198                 0, 0, pbn_b0_bt_2_115200 },
4199
4200         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
4201                 0xA000, 0x3004,
4202                 0, 0, pbn_b0_bt_4_115200 },
4203         /* Intel CE4100 */
4204         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
4205                 PCI_ANY_ID,  PCI_ANY_ID, 0, 0,
4206                 pbn_ce4100_1_115200 },
4207
4208         /*
4209          * Cronyx Omega PCI
4210          */
4211         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
4212                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4213                 pbn_omegapci },
4214
4215         /*
4216          * AgeStar as-prs2-009
4217          */
4218         {       PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375,
4219                 PCI_ANY_ID, PCI_ANY_ID,
4220                 0, 0, pbn_b0_bt_2_115200 },
4221         /*
4222          * These entries match devices with class COMMUNICATION_SERIAL,
4223          * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
4224          */
4225         {       PCI_ANY_ID, PCI_ANY_ID,
4226                 PCI_ANY_ID, PCI_ANY_ID,
4227                 PCI_CLASS_COMMUNICATION_SERIAL << 8,
4228                 0xffff00, pbn_default },
4229         {       PCI_ANY_ID, PCI_ANY_ID,
4230                 PCI_ANY_ID, PCI_ANY_ID,
4231                 PCI_CLASS_COMMUNICATION_MODEM << 8,
4232                 0xffff00, pbn_default },
4233         {       PCI_ANY_ID, PCI_ANY_ID,
4234                 PCI_ANY_ID, PCI_ANY_ID,
4235                 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
4236                 0xffff00, pbn_default },
4237         { 0, }
4238 };
4239
4240 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
4241                                                 pci_channel_state_t state)
4242 {
4243         struct serial_private *priv = pci_get_drvdata(dev);
4244
4245         if (state == pci_channel_io_perm_failure)
4246                 return PCI_ERS_RESULT_DISCONNECT;
4247
4248         if (priv)
4249                 pciserial_suspend_ports(priv);
4250
4251         pci_disable_device(dev);
4252
4253         return PCI_ERS_RESULT_NEED_RESET;
4254 }
4255
4256 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
4257 {
4258         int rc;
4259
4260         rc = pci_enable_device(dev);
4261
4262         if (rc)
4263                 return PCI_ERS_RESULT_DISCONNECT;
4264
4265         pci_restore_state(dev);
4266         pci_save_state(dev);
4267
4268         return PCI_ERS_RESULT_RECOVERED;
4269 }
4270
4271 static void serial8250_io_resume(struct pci_dev *dev)
4272 {
4273         struct serial_private *priv = pci_get_drvdata(dev);
4274
4275         if (priv)
4276                 pciserial_resume_ports(priv);
4277 }
4278
4279 static struct pci_error_handlers serial8250_err_handler = {
4280         .error_detected = serial8250_io_error_detected,
4281         .slot_reset = serial8250_io_slot_reset,
4282         .resume = serial8250_io_resume,
4283 };
4284
4285 static struct pci_driver serial_pci_driver = {
4286         .name           = "serial",
4287         .probe          = pciserial_init_one,
4288         .remove         = __devexit_p(pciserial_remove_one),
4289 #ifdef CONFIG_PM
4290         .suspend        = pciserial_suspend_one,
4291         .resume         = pciserial_resume_one,
4292 #endif
4293         .id_table       = serial_pci_tbl,
4294         .err_handler    = &serial8250_err_handler,
4295 };
4296
4297 static int __init serial8250_pci_init(void)
4298 {
4299         return pci_register_driver(&serial_pci_driver);
4300 }
4301
4302 static void __exit serial8250_pci_exit(void)
4303 {
4304         pci_unregister_driver(&serial_pci_driver);
4305 }
4306
4307 module_init(serial8250_pci_init);
4308 module_exit(serial8250_pci_exit);
4309
4310 MODULE_LICENSE("GPL");
4311 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
4312 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);