Pileus Git - ~andy/linux/blob - drivers/tty/serial/8250/8250_pci.c

   1 /*
   2  *  Probe module for 8250/16550-type PCI serial ports.
   3  *
   4  *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
   5  *
   6  *  Copyright (C) 2001 Russell King, All Rights Reserved.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License.
  11  */
  12 #undef DEBUG
  13 #include <linux/module.h>
  14 #include <linux/init.h>
  15 #include <linux/pci.h>
  16 #include <linux/string.h>
  17 #include <linux/kernel.h>
  18 #include <linux/slab.h>
  19 #include <linux/delay.h>
  20 #include <linux/tty.h>
  21 #include <linux/serial_reg.h>
  22 #include <linux/serial_core.h>
  23 #include <linux/8250_pci.h>
  24 #include <linux/bitops.h>
  25
  26 #include <asm/byteorder.h>
  27 #include <asm/io.h>
  28
  29 #include "8250.h"
  30
  31 /*
  32  * init function returns:
  33  *  > 0 - number of ports
  34  *  = 0 - use board->num_ports
  35  *  < 0 - error
  36  */
  37 struct pci_serial_quirk {
  38         u32     vendor;
  39         u32     device;
  40         u32     subvendor;
  41         u32     subdevice;
  42         int     (*probe)(struct pci_dev *dev);
  43         int     (*init)(struct pci_dev *dev);
  44         int     (*setup)(struct serial_private *,
  45                          const struct pciserial_board *,
  46                          struct uart_8250_port *, int);
  47         void    (*exit)(struct pci_dev *dev);
  48 };
  49
  50 #define PCI_NUM_BAR_RESOURCES   6
  51
  52 struct serial_private {
  53         struct pci_dev          *dev;
  54         unsigned int            nr;
  55         void __iomem            *remapped_bar[PCI_NUM_BAR_RESOURCES];
  56         struct pci_serial_quirk *quirk;
  57         int                     line[0];
  58 };
  59
  60 static int pci_default_setup(struct serial_private*,
  61           const struct pciserial_board*, struct uart_8250_port *, int);
  62
  63 static void moan_device(const char *str, struct pci_dev *dev)
  64 {
  65         dev_err(&dev->dev,
  66                "%s: %s\n"
  67                "Please send the output of lspci -vv, this\n"
  68                "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
  69                "manufacturer and name of serial board or\n"
  70                "modem board to rmk+serial@arm.linux.org.uk.\n",
  71                pci_name(dev), str, dev->vendor, dev->device,
  72                dev->subsystem_vendor, dev->subsystem_device);
  73 }
  74
  75 static int
  76 setup_port(struct serial_private *priv, struct uart_8250_port *port,
  77            int bar, int offset, int regshift)
  78 {
  79         struct pci_dev *dev = priv->dev;
  80         unsigned long base, len;
  81
  82         if (bar >= PCI_NUM_BAR_RESOURCES)
  83                 return -EINVAL;
  84
  85         base = pci_resource_start(dev, bar);
  86
  87         if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
  88                 len =  pci_resource_len(dev, bar);
  89
  90                 if (!priv->remapped_bar[bar])
  91                         priv->remapped_bar[bar] = ioremap_nocache(base, len);
  92                 if (!priv->remapped_bar[bar])
  93                         return -ENOMEM;
  94
  95                 port->port.iotype = UPIO_MEM;
  96                 port->port.iobase = 0;
  97                 port->port.mapbase = base + offset;
  98                 port->port.membase = priv->remapped_bar[bar] + offset;
  99                 port->port.regshift = regshift;
 100         } else {
 101                 port->port.iotype = UPIO_PORT;
 102                 port->port.iobase = base + offset;
 103                 port->port.mapbase = 0;
 104                 port->port.membase = NULL;
 105                 port->port.regshift = 0;
 106         }
 107         return 0;
 108 }
 109
 110 /*
 111  * ADDI-DATA GmbH communication cards <info@addi-data.com>
 112  */
 113 static int addidata_apci7800_setup(struct serial_private *priv,
 114                                 const struct pciserial_board *board,
 115                                 struct uart_8250_port *port, int idx)
 116 {
 117         unsigned int bar = 0, offset = board->first_offset;
 118         bar = FL_GET_BASE(board->flags);
 119
 120         if (idx < 2) {
 121                 offset += idx * board->uart_offset;
 122         } else if ((idx >= 2) && (idx < 4)) {
 123                 bar += 1;
 124                 offset += ((idx - 2) * board->uart_offset);
 125         } else if ((idx >= 4) && (idx < 6)) {
 126                 bar += 2;
 127                 offset += ((idx - 4) * board->uart_offset);
 128         } else if (idx >= 6) {
 129                 bar += 3;
 130                 offset += ((idx - 6) * board->uart_offset);
 131         }
 132
 133         return setup_port(priv, port, bar, offset, board->reg_shift);
 134 }
 135
 136 /*
 137  * AFAVLAB uses a different mixture of BARs and offsets
 138  * Not that ugly ;) -- HW
 139  */
 140 static int
 141 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
 142               struct uart_8250_port *port, int idx)
 143 {
 144         unsigned int bar, offset = board->first_offset;
 145
 146         bar = FL_GET_BASE(board->flags);
 147         if (idx < 4)
 148                 bar += idx;
 149         else {
 150                 bar = 4;
 151                 offset += (idx - 4) * board->uart_offset;
 152         }
 153
 154         return setup_port(priv, port, bar, offset, board->reg_shift);
 155 }
 156
 157 /*
 158  * HP's Remote Management Console.  The Diva chip came in several
 159  * different versions.  N-class, L2000 and A500 have two Diva chips, each
 160  * with 3 UARTs (the third UART on the second chip is unused).  Superdome
 161  * and Keystone have one Diva chip with 3 UARTs.  Some later machines have
 162  * one Diva chip, but it has been expanded to 5 UARTs.
 163  */
 164 static int pci_hp_diva_init(struct pci_dev *dev)
 165 {
 166         int rc = 0;
 167
 168         switch (dev->subsystem_device) {
 169         case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
 170         case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
 171         case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
 172         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
 173                 rc = 3;
 174                 break;
 175         case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
 176                 rc = 2;
 177                 break;
 178         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
 179                 rc = 4;
 180                 break;
 181         case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
 182         case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
 183                 rc = 1;
 184                 break;
 185         }
 186
 187         return rc;
 188 }
 189
 190 /*
 191  * HP's Diva chip puts the 4th/5th serial port further out, and
 192  * some serial ports are supposed to be hidden on certain models.
 193  */
 194 static int
 195 pci_hp_diva_setup(struct serial_private *priv,
 196                 const struct pciserial_board *board,
 197                 struct uart_8250_port *port, int idx)
 198 {
 199         unsigned int offset = board->first_offset;
 200         unsigned int bar = FL_GET_BASE(board->flags);
 201
 202         switch (priv->dev->subsystem_device) {
 203         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
 204                 if (idx == 3)
 205                         idx++;
 206                 break;
 207         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
 208                 if (idx > 0)
 209                         idx++;
 210                 if (idx > 2)
 211                         idx++;
 212                 break;
 213         }
 214         if (idx > 2)
 215                 offset = 0x18;
 216
 217         offset += idx * board->uart_offset;
 218
 219         return setup_port(priv, port, bar, offset, board->reg_shift);
 220 }
 221
 222 /*
 223  * Added for EKF Intel i960 serial boards
 224  */
 225 static int pci_inteli960ni_init(struct pci_dev *dev)
 226 {
 227         unsigned long oldval;
 228
 229         if (!(dev->subsystem_device & 0x1000))
 230                 return -ENODEV;
 231
 232         /* is firmware started? */
 233         pci_read_config_dword(dev, 0x44, (void *)&oldval);
 234         if (oldval == 0x00001000L) { /* RESET value */
 235                 dev_dbg(&dev->dev, "Local i960 firmware missing\n");
 236                 return -ENODEV;
 237         }
 238         return 0;
 239 }
 240
 241 /*
 242  * Some PCI serial cards using the PLX 9050 PCI interface chip require
 243  * that the card interrupt be explicitly enabled or disabled.  This
 244  * seems to be mainly needed on card using the PLX which also use I/O
 245  * mapped memory.
 246  */
 247 static int pci_plx9050_init(struct pci_dev *dev)
 248 {
 249         u8 irq_config;
 250         void __iomem *p;
 251
 252         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
 253                 moan_device("no memory in bar 0", dev);
 254                 return 0;
 255         }
 256
 257         irq_config = 0x41;
 258         if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
 259             dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
 260                 irq_config = 0x43;
 261
 262         if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
 263             (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
 264                 /*
 265                  * As the megawolf cards have the int pins active
 266                  * high, and have 2 UART chips, both ints must be
 267                  * enabled on the 9050. Also, the UARTS are set in
 268                  * 16450 mode by default, so we have to enable the
 269                  * 16C950 'enhanced' mode so that we can use the
 270                  * deep FIFOs
 271                  */
 272                 irq_config = 0x5b;
 273         /*
 274          * enable/disable interrupts
 275          */
 276         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
 277         if (p == NULL)
 278                 return -ENOMEM;
 279         writel(irq_config, p + 0x4c);
 280
 281         /*
 282          * Read the register back to ensure that it took effect.
 283          */
 284         readl(p + 0x4c);
 285         iounmap(p);
 286
 287         return 0;
 288 }
 289
 290 static void pci_plx9050_exit(struct pci_dev *dev)
 291 {
 292         u8 __iomem *p;
 293
 294         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
 295                 return;
 296
 297         /*
 298          * disable interrupts
 299          */
 300         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
 301         if (p != NULL) {
 302                 writel(0, p + 0x4c);
 303
 304                 /*
 305                  * Read the register back to ensure that it took effect.
 306                  */
 307                 readl(p + 0x4c);
 308                 iounmap(p);
 309         }
 310 }
 311
 312 #define NI8420_INT_ENABLE_REG   0x38
 313 #define NI8420_INT_ENABLE_BIT   0x2000
 314
 315 static void pci_ni8420_exit(struct pci_dev *dev)
 316 {
 317         void __iomem *p;
 318         unsigned long base, len;
 319         unsigned int bar = 0;
 320
 321         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 322                 moan_device("no memory in bar", dev);
 323                 return;
 324         }
 325
 326         base = pci_resource_start(dev, bar);
 327         len =  pci_resource_len(dev, bar);
 328         p = ioremap_nocache(base, len);
 329         if (p == NULL)
 330                 return;
 331
 332         /* Disable the CPU Interrupt */
 333         writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
 334                p + NI8420_INT_ENABLE_REG);
 335         iounmap(p);
 336 }
 337
 338
 339 /* MITE registers */
 340 #define MITE_IOWBSR1    0xc4
 341 #define MITE_IOWCR1     0xf4
 342 #define MITE_LCIMR1     0x08
 343 #define MITE_LCIMR2     0x10
 344
 345 #define MITE_LCIMR2_CLR_CPU_IE  (1 << 30)
 346
 347 static void pci_ni8430_exit(struct pci_dev *dev)
 348 {
 349         void __iomem *p;
 350         unsigned long base, len;
 351         unsigned int bar = 0;
 352
 353         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 354                 moan_device("no memory in bar", dev);
 355                 return;
 356         }
 357
 358         base = pci_resource_start(dev, bar);
 359         len =  pci_resource_len(dev, bar);
 360         p = ioremap_nocache(base, len);
 361         if (p == NULL)
 362                 return;
 363
 364         /* Disable the CPU Interrupt */
 365         writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
 366         iounmap(p);
 367 }
 368
 369 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
 370 static int
 371 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
 372                 struct uart_8250_port *port, int idx)
 373 {
 374         unsigned int bar, offset = board->first_offset;
 375
 376         bar = 0;
 377
 378         if (idx < 4) {
 379                 /* first four channels map to 0, 0x100, 0x200, 0x300 */
 380                 offset += idx * board->uart_offset;
 381         } else if (idx < 8) {
 382                 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
 383                 offset += idx * board->uart_offset + 0xC00;
 384         } else /* we have only 8 ports on PMC-OCTALPRO */
 385                 return 1;
 386
 387         return setup_port(priv, port, bar, offset, board->reg_shift);
 388 }
 389
 390 /*
 391 * This does initialization for PMC OCTALPRO cards:
 392 * maps the device memory, resets the UARTs (needed, bc
 393 * if the module is removed and inserted again, the card
 394 * is in the sleep mode) and enables global interrupt.
 395 */
 396
 397 /* global control register offset for SBS PMC-OctalPro */
 398 #define OCT_REG_CR_OFF          0x500
 399
 400 static int sbs_init(struct pci_dev *dev)
 401 {
 402         u8 __iomem *p;
 403
 404         p = pci_ioremap_bar(dev, 0);
 405
 406         if (p == NULL)
 407                 return -ENOMEM;
 408         /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
 409         writeb(0x10, p + OCT_REG_CR_OFF);
 410         udelay(50);
 411         writeb(0x0, p + OCT_REG_CR_OFF);
 412
 413         /* Set bit-2 (INTENABLE) of Control Register */
 414         writeb(0x4, p + OCT_REG_CR_OFF);
 415         iounmap(p);
 416
 417         return 0;
 418 }
 419
 420 /*
 421  * Disables the global interrupt of PMC-OctalPro
 422  */
 423
 424 static void sbs_exit(struct pci_dev *dev)
 425 {
 426         u8 __iomem *p;
 427
 428         p = pci_ioremap_bar(dev, 0);
 429         /* FIXME: What if resource_len < OCT_REG_CR_OFF */
 430         if (p != NULL)
 431                 writeb(0, p + OCT_REG_CR_OFF);
 432         iounmap(p);
 433 }
 434
 435 /*
 436  * SIIG serial cards have an PCI interface chip which also controls
 437  * the UART clocking frequency. Each UART can be clocked independently
 438  * (except cards equipped with 4 UARTs) and initial clocking settings
 439  * are stored in the EEPROM chip. It can cause problems because this
 440  * version of serial driver doesn't support differently clocked UART's
 441  * on single PCI card. To prevent this, initialization functions set
 442  * high frequency clocking for all UART's on given card. It is safe (I
 443  * hope) because it doesn't touch EEPROM settings to prevent conflicts
 444  * with other OSes (like M$ DOS).
 445  *
 446  *  SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
 447  *
 448  * There is two family of SIIG serial cards with different PCI
 449  * interface chip and different configuration methods:
 450  *     - 10x cards have control registers in IO and/or memory space;
 451  *     - 20x cards have control registers in standard PCI configuration space.
 452  *
 453  * Note: all 10x cards have PCI device ids 0x10..
 454  *       all 20x cards have PCI device ids 0x20..
 455  *
 456  * There are also Quartet Serial cards which use Oxford Semiconductor
 457  * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
 458  *
 459  * Note: some SIIG cards are probed by the parport_serial object.
 460  */
 461
 462 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
 463 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
 464
 465 static int pci_siig10x_init(struct pci_dev *dev)
 466 {
 467         u16 data;
 468         void __iomem *p;
 469
 470         switch (dev->device & 0xfff8) {
 471         case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
 472                 data = 0xffdf;
 473                 break;
 474         case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
 475                 data = 0xf7ff;
 476                 break;
 477         default:                        /* 1S1P, 4S */
 478                 data = 0xfffb;
 479                 break;
 480         }
 481
 482         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
 483         if (p == NULL)
 484                 return -ENOMEM;
 485
 486         writew(readw(p + 0x28) & data, p + 0x28);
 487         readw(p + 0x28);
 488         iounmap(p);
 489         return 0;
 490 }
 491
 492 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
 493 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
 494
 495 static int pci_siig20x_init(struct pci_dev *dev)
 496 {
 497         u8 data;
 498
 499         /* Change clock frequency for the first UART. */
 500         pci_read_config_byte(dev, 0x6f, &data);
 501         pci_write_config_byte(dev, 0x6f, data & 0xef);
 502
 503         /* If this card has 2 UART, we have to do the same with second UART. */
 504         if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
 505             ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
 506                 pci_read_config_byte(dev, 0x73, &data);
 507                 pci_write_config_byte(dev, 0x73, data & 0xef);
 508         }
 509         return 0;
 510 }
 511
 512 static int pci_siig_init(struct pci_dev *dev)
 513 {
 514         unsigned int type = dev->device & 0xff00;
 515
 516         if (type == 0x1000)
 517                 return pci_siig10x_init(dev);
 518         else if (type == 0x2000)
 519                 return pci_siig20x_init(dev);
 520
 521         moan_device("Unknown SIIG card", dev);
 522         return -ENODEV;
 523 }
 524
 525 static int pci_siig_setup(struct serial_private *priv,
 526                           const struct pciserial_board *board,
 527                           struct uart_8250_port *port, int idx)
 528 {
 529         unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
 530
 531         if (idx > 3) {
 532                 bar = 4;
 533                 offset = (idx - 4) * 8;
 534         }
 535
 536         return setup_port(priv, port, bar, offset, 0);
 537 }
 538
 539 /*
 540  * Timedia has an explosion of boards, and to avoid the PCI table from
 541  * growing *huge*, we use this function to collapse some 70 entries
 542  * in the PCI table into one, for sanity's and compactness's sake.
 543  */
 544 static const unsigned short timedia_single_port[] = {
 545         0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
 546 };
 547
 548 static const unsigned short timedia_dual_port[] = {
 549         0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
 550         0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
 551         0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
 552         0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
 553         0xD079, 0
 554 };
 555
 556 static const unsigned short timedia_quad_port[] = {
 557         0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
 558         0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
 559         0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
 560         0xB157, 0
 561 };
 562
 563 static const unsigned short timedia_eight_port[] = {
 564         0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
 565         0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
 566 };
 567
 568 static const struct timedia_struct {
 569         int num;
 570         const unsigned short *ids;
 571 } timedia_data[] = {
 572         { 1, timedia_single_port },
 573         { 2, timedia_dual_port },
 574         { 4, timedia_quad_port },
 575         { 8, timedia_eight_port }
 576 };
 577
 578 /*
 579  * There are nearly 70 different Timedia/SUNIX PCI serial devices.  Instead of
 580  * listing them individually, this driver merely grabs them all with
 581  * PCI_ANY_ID.  Some of these devices, however, also feature a parallel port,
 582  * and should be left free to be claimed by parport_serial instead.
 583  */
 584 static int pci_timedia_probe(struct pci_dev *dev)
 585 {
 586         /*
 587          * Check the third digit of the subdevice ID
 588          * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
 589          */
 590         if ((dev->subsystem_device & 0x00f0) >= 0x70) {
 591                 dev_info(&dev->dev,
 592                         "ignoring Timedia subdevice %04x for parport_serial\n",
 593                         dev->subsystem_device);
 594                 return -ENODEV;
 595         }
 596
 597         return 0;
 598 }
 599
 600 static int pci_timedia_init(struct pci_dev *dev)
 601 {
 602         const unsigned short *ids;
 603         int i, j;
 604
 605         for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
 606                 ids = timedia_data[i].ids;
 607                 for (j = 0; ids[j]; j++)
 608                         if (dev->subsystem_device == ids[j])
 609                                 return timedia_data[i].num;
 610         }
 611         return 0;
 612 }
 613
 614 /*
 615  * Timedia/SUNIX uses a mixture of BARs and offsets
 616  * Ugh, this is ugly as all hell --- TYT
 617  */
 618 static int
 619 pci_timedia_setup(struct serial_private *priv,
 620                   const struct pciserial_board *board,
 621                   struct uart_8250_port *port, int idx)
 622 {
 623         unsigned int bar = 0, offset = board->first_offset;
 624
 625         switch (idx) {
 626         case 0:
 627                 bar = 0;
 628                 break;
 629         case 1:
 630                 offset = board->uart_offset;
 631                 bar = 0;
 632                 break;
 633         case 2:
 634                 bar = 1;
 635                 break;
 636         case 3:
 637                 offset = board->uart_offset;
 638                 /* FALLTHROUGH */
 639         case 4: /* BAR 2 */
 640         case 5: /* BAR 3 */
 641         case 6: /* BAR 4 */
 642         case 7: /* BAR 5 */
 643                 bar = idx - 2;
 644         }
 645
 646         return setup_port(priv, port, bar, offset, board->reg_shift);
 647 }
 648
 649 /*
 650  * Some Titan cards are also a little weird
 651  */
 652 static int
 653 titan_400l_800l_setup(struct serial_private *priv,
 654                       const struct pciserial_board *board,
 655                       struct uart_8250_port *port, int idx)
 656 {
 657         unsigned int bar, offset = board->first_offset;
 658
 659         switch (idx) {
 660         case 0:
 661                 bar = 1;
 662                 break;
 663         case 1:
 664                 bar = 2;
 665                 break;
 666         default:
 667                 bar = 4;
 668                 offset = (idx - 2) * board->uart_offset;
 669         }
 670
 671         return setup_port(priv, port, bar, offset, board->reg_shift);
 672 }
 673
 674 static int pci_xircom_init(struct pci_dev *dev)
 675 {
 676         msleep(100);
 677         return 0;
 678 }
 679
 680 static int pci_ni8420_init(struct pci_dev *dev)
 681 {
 682         void __iomem *p;
 683         unsigned long base, len;
 684         unsigned int bar = 0;
 685
 686         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 687                 moan_device("no memory in bar", dev);
 688                 return 0;
 689         }
 690
 691         base = pci_resource_start(dev, bar);
 692         len =  pci_resource_len(dev, bar);
 693         p = ioremap_nocache(base, len);
 694         if (p == NULL)
 695                 return -ENOMEM;
 696
 697         /* Enable CPU Interrupt */
 698         writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
 699                p + NI8420_INT_ENABLE_REG);
 700
 701         iounmap(p);
 702         return 0;
 703 }
 704
 705 #define MITE_IOWBSR1_WSIZE      0xa
 706 #define MITE_IOWBSR1_WIN_OFFSET 0x800
 707 #define MITE_IOWBSR1_WENAB      (1 << 7)
 708 #define MITE_LCIMR1_IO_IE_0     (1 << 24)
 709 #define MITE_LCIMR2_SET_CPU_IE  (1 << 31)
 710 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
 711
 712 static int pci_ni8430_init(struct pci_dev *dev)
 713 {
 714         void __iomem *p;
 715         unsigned long base, len;
 716         u32 device_window;
 717         unsigned int bar = 0;
 718
 719         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 720                 moan_device("no memory in bar", dev);
 721                 return 0;
 722         }
 723
 724         base = pci_resource_start(dev, bar);
 725         len =  pci_resource_len(dev, bar);
 726         p = ioremap_nocache(base, len);
 727         if (p == NULL)
 728                 return -ENOMEM;
 729
 730         /* Set device window address and size in BAR0 */
 731         device_window = ((base + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
 732                         | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
 733         writel(device_window, p + MITE_IOWBSR1);
 734
 735         /* Set window access to go to RAMSEL IO address space */
 736         writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
 737                p + MITE_IOWCR1);
 738
 739         /* Enable IO Bus Interrupt 0 */
 740         writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
 741
 742         /* Enable CPU Interrupt */
 743         writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
 744
 745         iounmap(p);
 746         return 0;
 747 }
 748
 749 /* UART Port Control Register */
 750 #define NI8430_PORTCON  0x0f
 751 #define NI8430_PORTCON_TXVR_ENABLE      (1 << 3)
 752
 753 static int
 754 pci_ni8430_setup(struct serial_private *priv,
 755                  const struct pciserial_board *board,
 756                  struct uart_8250_port *port, int idx)
 757 {
 758         void __iomem *p;
 759         unsigned long base, len;
 760         unsigned int bar, offset = board->first_offset;
 761
 762         if (idx >= board->num_ports)
 763                 return 1;
 764
 765         bar = FL_GET_BASE(board->flags);
 766         offset += idx * board->uart_offset;
 767
 768         base = pci_resource_start(priv->dev, bar);
 769         len =  pci_resource_len(priv->dev, bar);
 770         p = ioremap_nocache(base, len);
 771
 772         /* enable the transceiver */
 773         writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
 774                p + offset + NI8430_PORTCON);
 775
 776         iounmap(p);
 777
 778         return setup_port(priv, port, bar, offset, board->reg_shift);
 779 }
 780
 781 static int pci_netmos_9900_setup(struct serial_private *priv,
 782                                 const struct pciserial_board *board,
 783                                 struct uart_8250_port *port, int idx)
 784 {
 785         unsigned int bar;
 786
 787         if ((priv->dev->subsystem_device & 0xff00) == 0x3000) {
 788                 /* netmos apparently orders BARs by datasheet layout, so serial
 789                  * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
 790                  */
 791                 bar = 3 * idx;
 792
 793                 return setup_port(priv, port, bar, 0, board->reg_shift);
 794         } else {
 795                 return pci_default_setup(priv, board, port, idx);
 796         }
 797 }
 798
 799 /* the 99xx series comes with a range of device IDs and a variety
 800  * of capabilities:
 801  *
 802  * 9900 has varying capabilities and can cascade to sub-controllers
 803  *   (cascading should be purely internal)
 804  * 9904 is hardwired with 4 serial ports
 805  * 9912 and 9922 are hardwired with 2 serial ports
 806  */
 807 static int pci_netmos_9900_numports(struct pci_dev *dev)
 808 {
 809         unsigned int c = dev->class;
 810         unsigned int pi;
 811         unsigned short sub_serports;
 812
 813         pi = (c & 0xff);
 814
 815         if (pi == 2) {
 816                 return 1;
 817         } else if ((pi == 0) &&
 818                            (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
 819                 /* two possibilities: 0x30ps encodes number of parallel and
 820                  * serial ports, or 0x1000 indicates *something*. This is not
 821                  * immediately obvious, since the 2s1p+4s configuration seems
 822                  * to offer all functionality on functions 0..2, while still
 823                  * advertising the same function 3 as the 4s+2s1p config.
 824                  */
 825                 sub_serports = dev->subsystem_device & 0xf;
 826                 if (sub_serports > 0) {
 827                         return sub_serports;
 828                 } else {
 829                         dev_err(&dev->dev, "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
 830                         return 0;
 831                 }
 832         }
 833
 834         moan_device("unknown NetMos/Mostech program interface", dev);
 835         return 0;
 836 }
 837
 838 static int pci_netmos_init(struct pci_dev *dev)
 839 {
 840         /* subdevice 0x00PS means <P> parallel, <S> serial */
 841         unsigned int num_serial = dev->subsystem_device & 0xf;
 842
 843         if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
 844                 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
 845                 return 0;
 846
 847         if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
 848                         dev->subsystem_device == 0x0299)
 849                 return 0;
 850
 851         switch (dev->device) { /* FALLTHROUGH on all */
 852                 case PCI_DEVICE_ID_NETMOS_9904:
 853                 case PCI_DEVICE_ID_NETMOS_9912:
 854                 case PCI_DEVICE_ID_NETMOS_9922:
 855                 case PCI_DEVICE_ID_NETMOS_9900:
 856                         num_serial = pci_netmos_9900_numports(dev);
 857                         break;
 858
 859                 default:
 860                         if (num_serial == 0 ) {
 861                                 moan_device("unknown NetMos/Mostech device", dev);
 862                         }
 863         }
 864
 865         if (num_serial == 0)
 866                 return -ENODEV;
 867
 868         return num_serial;
 869 }
 870
 871 /*
 872  * These chips are available with optionally one parallel port and up to
 873  * two serial ports. Unfortunately they all have the same product id.
 874  *
 875  * Basic configuration is done over a region of 32 I/O ports. The base
 876  * ioport is called INTA or INTC, depending on docs/other drivers.
 877  *
 878  * The region of the 32 I/O ports is configured in POSIO0R...
 879  */
 880
 881 /* registers */
 882 #define ITE_887x_MISCR          0x9c
 883 #define ITE_887x_INTCBAR        0x78
 884 #define ITE_887x_UARTBAR        0x7c
 885 #define ITE_887x_PS0BAR         0x10
 886 #define ITE_887x_POSIO0         0x60
 887
 888 /* I/O space size */
 889 #define ITE_887x_IOSIZE         32
 890 /* I/O space size (bits 26-24; 8 bytes = 011b) */
 891 #define ITE_887x_POSIO_IOSIZE_8         (3 << 24)
 892 /* I/O space size (bits 26-24; 32 bytes = 101b) */
 893 #define ITE_887x_POSIO_IOSIZE_32        (5 << 24)
 894 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
 895 #define ITE_887x_POSIO_SPEED            (3 << 29)
 896 /* enable IO_Space bit */
 897 #define ITE_887x_POSIO_ENABLE           (1 << 31)
 898
 899 static int pci_ite887x_init(struct pci_dev *dev)
 900 {
 901         /* inta_addr are the configuration addresses of the ITE */
 902         static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
 903                                                         0x200, 0x280, 0 };
 904         int ret, i, type;
 905         struct resource *iobase = NULL;
 906         u32 miscr, uartbar, ioport;
 907
 908         /* search for the base-ioport */
 909         i = 0;
 910         while (inta_addr[i] && iobase == NULL) {
 911                 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
 912                                                                 "ite887x");
 913                 if (iobase != NULL) {
 914                         /* write POSIO0R - speed | size | ioport */
 915                         pci_write_config_dword(dev, ITE_887x_POSIO0,
 916                                 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
 917                                 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
 918                         /* write INTCBAR - ioport */
 919                         pci_write_config_dword(dev, ITE_887x_INTCBAR,
 920                                                                 inta_addr[i]);
 921                         ret = inb(inta_addr[i]);
 922                         if (ret != 0xff) {
 923                                 /* ioport connected */
 924                                 break;
 925                         }
 926                         release_region(iobase->start, ITE_887x_IOSIZE);
 927                         iobase = NULL;
 928                 }
 929                 i++;
 930         }
 931
 932         if (!inta_addr[i]) {
 933                 dev_err(&dev->dev, "ite887x: could not find iobase\n");
 934                 return -ENODEV;
 935         }
 936
 937         /* start of undocumented type checking (see parport_pc.c) */
 938         type = inb(iobase->start + 0x18) & 0x0f;
 939
 940         switch (type) {
 941         case 0x2:       /* ITE8871 (1P) */
 942         case 0xa:       /* ITE8875 (1P) */
 943                 ret = 0;
 944                 break;
 945         case 0xe:       /* ITE8872 (2S1P) */
 946                 ret = 2;
 947                 break;
 948         case 0x6:       /* ITE8873 (1S) */
 949                 ret = 1;
 950                 break;
 951         case 0x8:       /* ITE8874 (2S) */
 952                 ret = 2;
 953                 break;
 954         default:
 955                 moan_device("Unknown ITE887x", dev);
 956                 ret = -ENODEV;
 957         }
 958
 959         /* configure all serial ports */
 960         for (i = 0; i < ret; i++) {
 961                 /* read the I/O port from the device */
 962                 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
 963                                                                 &ioport);
 964                 ioport &= 0x0000FF00;   /* the actual base address */
 965                 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
 966                         ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
 967                         ITE_887x_POSIO_IOSIZE_8 | ioport);
 968
 969                 /* write the ioport to the UARTBAR */
 970                 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
 971                 uartbar &= ~(0xffff << (16 * i));       /* clear half the reg */
 972                 uartbar |= (ioport << (16 * i));        /* set the ioport */
 973                 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
 974
 975                 /* get current config */
 976                 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
 977                 /* disable interrupts (UARTx_Routing[3:0]) */
 978                 miscr &= ~(0xf << (12 - 4 * i));
 979                 /* activate the UART (UARTx_En) */
 980                 miscr |= 1 << (23 - i);
 981                 /* write new config with activated UART */
 982                 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
 983         }
 984
 985         if (ret <= 0) {
 986                 /* the device has no UARTs if we get here */
 987                 release_region(iobase->start, ITE_887x_IOSIZE);
 988         }
 989
 990         return ret;
 991 }
 992
 993 static void pci_ite887x_exit(struct pci_dev *dev)
 994 {
 995         u32 ioport;
 996         /* the ioport is bit 0-15 in POSIO0R */
 997         pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
 998         ioport &= 0xffff;
 999         release_region(ioport, ITE_887x_IOSIZE);
1000 }
1001
1002 /*
1003  * Oxford Semiconductor Inc.
1004  * Check that device is part of the Tornado range of devices, then determine
1005  * the number of ports available on the device.
1006  */
1007 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1008 {
1009         u8 __iomem *p;
1010         unsigned long deviceID;
1011         unsigned int  number_uarts = 0;
1012
1013         /* OxSemi Tornado devices are all 0xCxxx */
1014         if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1015             (dev->device & 0xF000) != 0xC000)
1016                 return 0;
1017
1018         p = pci_iomap(dev, 0, 5);
1019         if (p == NULL)
1020                 return -ENOMEM;
1021
1022         deviceID = ioread32(p);
1023         /* Tornado device */
1024         if (deviceID == 0x07000200) {
1025                 number_uarts = ioread8(p + 4);
1026                 dev_dbg(&dev->dev,
1027                         "%d ports detected on Oxford PCI Express device\n",
1028                         number_uarts);
1029         }
1030         pci_iounmap(dev, p);
1031         return number_uarts;
1032 }
1033
1034 static int pci_asix_setup(struct serial_private *priv,
1035                   const struct pciserial_board *board,
1036                   struct uart_8250_port *port, int idx)
1037 {
1038         port->bugs |= UART_BUG_PARITY;
1039         return pci_default_setup(priv, board, port, idx);
1040 }
1041
1042 /* Quatech devices have their own extra interface features */
1043
1044 struct quatech_feature {
1045         u16 devid;
1046         bool amcc;
1047 };
1048
1049 #define QPCR_TEST_FOR1          0x3F
1050 #define QPCR_TEST_GET1          0x00
1051 #define QPCR_TEST_FOR2          0x40
1052 #define QPCR_TEST_GET2          0x40
1053 #define QPCR_TEST_FOR3          0x80
1054 #define QPCR_TEST_GET3          0x40
1055 #define QPCR_TEST_FOR4          0xC0
1056 #define QPCR_TEST_GET4          0x80
1057
1058 #define QOPR_CLOCK_X1           0x0000
1059 #define QOPR_CLOCK_X2           0x0001
1060 #define QOPR_CLOCK_X4           0x0002
1061 #define QOPR_CLOCK_X8           0x0003
1062 #define QOPR_CLOCK_RATE_MASK    0x0003
1063
1064
1065 static struct quatech_feature quatech_cards[] = {
1066         { PCI_DEVICE_ID_QUATECH_QSC100,   1 },
1067         { PCI_DEVICE_ID_QUATECH_DSC100,   1 },
1068         { PCI_DEVICE_ID_QUATECH_DSC100E,  0 },
1069         { PCI_DEVICE_ID_QUATECH_DSC200,   1 },
1070         { PCI_DEVICE_ID_QUATECH_DSC200E,  0 },
1071         { PCI_DEVICE_ID_QUATECH_ESC100D,  1 },
1072         { PCI_DEVICE_ID_QUATECH_ESC100M,  1 },
1073         { PCI_DEVICE_ID_QUATECH_QSCP100,  1 },
1074         { PCI_DEVICE_ID_QUATECH_DSCP100,  1 },
1075         { PCI_DEVICE_ID_QUATECH_QSCP200,  1 },
1076         { PCI_DEVICE_ID_QUATECH_DSCP200,  1 },
1077         { PCI_DEVICE_ID_QUATECH_ESCLP100, 0 },
1078         { PCI_DEVICE_ID_QUATECH_QSCLP100, 0 },
1079         { PCI_DEVICE_ID_QUATECH_DSCLP100, 0 },
1080         { PCI_DEVICE_ID_QUATECH_SSCLP100, 0 },
1081         { PCI_DEVICE_ID_QUATECH_QSCLP200, 0 },
1082         { PCI_DEVICE_ID_QUATECH_DSCLP200, 0 },
1083         { PCI_DEVICE_ID_QUATECH_SSCLP200, 0 },
1084         { PCI_DEVICE_ID_QUATECH_SPPXP_100, 0 },
1085         { 0, }
1086 };
1087
1088 static int pci_quatech_amcc(u16 devid)
1089 {
1090         struct quatech_feature *qf = &quatech_cards[0];
1091         while (qf->devid) {
1092                 if (qf->devid == devid)
1093                         return qf->amcc;
1094                 qf++;
1095         }
1096         pr_err("quatech: unknown port type '0x%04X'.\n", devid);
1097         return 0;
1098 };
1099
1100 static int pci_quatech_rqopr(struct uart_8250_port *port)
1101 {
1102         unsigned long base = port->port.iobase;
1103         u8 LCR, val;
1104
1105         LCR = inb(base + UART_LCR);
1106         outb(0xBF, base + UART_LCR);
1107         val = inb(base + UART_SCR);
1108         outb(LCR, base + UART_LCR);
1109         return val;
1110 }
1111
1112 static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr)
1113 {
1114         unsigned long base = port->port.iobase;
1115         u8 LCR, val;
1116
1117         LCR = inb(base + UART_LCR);
1118         outb(0xBF, base + UART_LCR);
1119         val = inb(base + UART_SCR);
1120         outb(qopr, base + UART_SCR);
1121         outb(LCR, base + UART_LCR);
1122 }
1123
1124 static int pci_quatech_rqmcr(struct uart_8250_port *port)
1125 {
1126         unsigned long base = port->port.iobase;
1127         u8 LCR, val, qmcr;
1128
1129         LCR = inb(base + UART_LCR);
1130         outb(0xBF, base + UART_LCR);
1131         val = inb(base + UART_SCR);
1132         outb(val | 0x10, base + UART_SCR);
1133         qmcr = inb(base + UART_MCR);
1134         outb(val, base + UART_SCR);
1135         outb(LCR, base + UART_LCR);
1136
1137         return qmcr;
1138 }
1139
1140 static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr)
1141 {
1142         unsigned long base = port->port.iobase;
1143         u8 LCR, val;
1144
1145         LCR = inb(base + UART_LCR);
1146         outb(0xBF, base + UART_LCR);
1147         val = inb(base + UART_SCR);
1148         outb(val | 0x10, base + UART_SCR);
1149         outb(qmcr, base + UART_MCR);
1150         outb(val, base + UART_SCR);
1151         outb(LCR, base + UART_LCR);
1152 }
1153
1154 static int pci_quatech_has_qmcr(struct uart_8250_port *port)
1155 {
1156         unsigned long base = port->port.iobase;
1157         u8 LCR, val;
1158
1159         LCR = inb(base + UART_LCR);
1160         outb(0xBF, base + UART_LCR);
1161         val = inb(base + UART_SCR);
1162         if (val & 0x20) {
1163                 outb(0x80, UART_LCR);
1164                 if (!(inb(UART_SCR) & 0x20)) {
1165                         outb(LCR, base + UART_LCR);
1166                         return 1;
1167                 }
1168         }
1169         return 0;
1170 }
1171
1172 static int pci_quatech_test(struct uart_8250_port *port)
1173 {
1174         u8 reg;
1175         u8 qopr = pci_quatech_rqopr(port);
1176         pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1);
1177         reg = pci_quatech_rqopr(port) & 0xC0;
1178         if (reg != QPCR_TEST_GET1)
1179                 return -EINVAL;
1180         pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2);
1181         reg = pci_quatech_rqopr(port) & 0xC0;
1182         if (reg != QPCR_TEST_GET2)
1183                 return -EINVAL;
1184         pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3);
1185         reg = pci_quatech_rqopr(port) & 0xC0;
1186         if (reg != QPCR_TEST_GET3)
1187                 return -EINVAL;
1188         pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4);
1189         reg = pci_quatech_rqopr(port) & 0xC0;
1190         if (reg != QPCR_TEST_GET4)
1191                 return -EINVAL;
1192
1193         pci_quatech_wqopr(port, qopr);
1194         return 0;
1195 }
1196
1197 static int pci_quatech_clock(struct uart_8250_port *port)
1198 {
1199         u8 qopr, reg, set;
1200         unsigned long clock;
1201
1202         if (pci_quatech_test(port) < 0)
1203                 return 1843200;
1204
1205         qopr = pci_quatech_rqopr(port);
1206
1207         pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8);
1208         reg = pci_quatech_rqopr(port);
1209         if (reg & QOPR_CLOCK_X8) {
1210                 clock = 1843200;
1211                 goto out;
1212         }
1213         pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8);
1214         reg = pci_quatech_rqopr(port);
1215         if (!(reg & QOPR_CLOCK_X8)) {
1216                 clock = 1843200;
1217                 goto out;
1218         }
1219         reg &= QOPR_CLOCK_X8;
1220         if (reg == QOPR_CLOCK_X2) {
1221                 clock =  3685400;
1222                 set = QOPR_CLOCK_X2;
1223         } else if (reg == QOPR_CLOCK_X4) {
1224                 clock = 7372800;
1225                 set = QOPR_CLOCK_X4;
1226         } else if (reg == QOPR_CLOCK_X8) {
1227                 clock = 14745600;
1228                 set = QOPR_CLOCK_X8;
1229         } else {
1230                 clock = 1843200;
1231                 set = QOPR_CLOCK_X1;
1232         }
1233         qopr &= ~QOPR_CLOCK_RATE_MASK;
1234         qopr |= set;
1235
1236 out:
1237         pci_quatech_wqopr(port, qopr);
1238         return clock;
1239 }
1240
1241 static int pci_quatech_rs422(struct uart_8250_port *port)
1242 {
1243         u8 qmcr;
1244         int rs422 = 0;
1245
1246         if (!pci_quatech_has_qmcr(port))
1247                 return 0;
1248         qmcr = pci_quatech_rqmcr(port);
1249         pci_quatech_wqmcr(port, 0xFF);
1250         if (pci_quatech_rqmcr(port))
1251                 rs422 = 1;
1252         pci_quatech_wqmcr(port, qmcr);
1253         return rs422;
1254 }
1255
1256 static int pci_quatech_init(struct pci_dev *dev)
1257 {
1258         if (pci_quatech_amcc(dev->device)) {
1259                 unsigned long base = pci_resource_start(dev, 0);
1260                 if (base) {
1261                         u32 tmp;
1262                         outl(inl(base + 0x38), base + 0x38);
1263                         tmp = inl(base + 0x3c);
1264                         outl(tmp | 0x01000000, base + 0x3c);
1265                         outl(tmp, base + 0x3c);
1266                 }
1267         }
1268         return 0;
1269 }
1270
1271 static int pci_quatech_setup(struct serial_private *priv,
1272                   const struct pciserial_board *board,
1273                   struct uart_8250_port *port, int idx)
1274 {
1275         /* Needed by pci_quatech calls below */
1276         port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags));
1277         /* Set up the clocking */
1278         port->port.uartclk = pci_quatech_clock(port);
1279         /* For now just warn about RS422 */
1280         if (pci_quatech_rs422(port))
1281                 pr_warn("quatech: software control of RS422 features not currently supported.\n");
1282         return pci_default_setup(priv, board, port, idx);
1283 }
1284
1285 static void pci_quatech_exit(struct pci_dev *dev)
1286 {
1287 }
1288
1289 static int pci_default_setup(struct serial_private *priv,
1290                   const struct pciserial_board *board,
1291                   struct uart_8250_port *port, int idx)
1292 {
1293         unsigned int bar, offset = board->first_offset, maxnr;
1294
1295         bar = FL_GET_BASE(board->flags);
1296         if (board->flags & FL_BASE_BARS)
1297                 bar += idx;
1298         else
1299                 offset += idx * board->uart_offset;
1300
1301         maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1302                 (board->reg_shift + 3);
1303
1304         if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1305                 return 1;
1306
1307         return setup_port(priv, port, bar, offset, board->reg_shift);
1308 }
1309
1310 static int pci_pericom_setup(struct serial_private *priv,
1311                   const struct pciserial_board *board,
1312                   struct uart_8250_port *port, int idx)
1313 {
1314         unsigned int bar, offset = board->first_offset, maxnr;
1315
1316         bar = FL_GET_BASE(board->flags);
1317         if (board->flags & FL_BASE_BARS)
1318                 bar += idx;
1319         else
1320                 offset += idx * board->uart_offset;
1321
1322         maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1323                 (board->reg_shift + 3);
1324
1325         if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1326                 return 1;
1327
1328         port->port.uartclk = 14745600;
1329
1330         return setup_port(priv, port, bar, offset, board->reg_shift);
1331 }
1332
1333 static int
1334 ce4100_serial_setup(struct serial_private *priv,
1335                   const struct pciserial_board *board,
1336                   struct uart_8250_port *port, int idx)
1337 {
1338         int ret;
1339
1340         ret = setup_port(priv, port, idx, 0, board->reg_shift);
1341         port->port.iotype = UPIO_MEM32;
1342         port->port.type = PORT_XSCALE;
1343         port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1344         port->port.regshift = 2;
1345
1346         return ret;
1347 }
1348
1349 #define PCI_DEVICE_ID_INTEL_BYT_UART1   0x0f0a
1350 #define PCI_DEVICE_ID_INTEL_BYT_UART2   0x0f0c
1351
1352 #define BYT_PRV_CLK                     0x800
1353 #define BYT_PRV_CLK_EN                  (1 << 0)
1354 #define BYT_PRV_CLK_M_VAL_SHIFT         1
1355 #define BYT_PRV_CLK_N_VAL_SHIFT         16
1356 #define BYT_PRV_CLK_UPDATE              (1 << 31)
1357
1358 #define BYT_GENERAL_REG                 0x808
1359 #define BYT_GENERAL_DIS_RTS_N_OVERRIDE  (1 << 3)
1360
1361 #define BYT_TX_OVF_INT                  0x820
1362 #define BYT_TX_OVF_INT_MASK             (1 << 1)
1363
1364 static void
1365 byt_set_termios(struct uart_port *p, struct ktermios *termios,
1366                 struct ktermios *old)
1367 {
1368         unsigned int baud = tty_termios_baud_rate(termios);
1369         unsigned int m = 6912;
1370         unsigned int n = 15625;
1371         u32 reg;
1372
1373         /* For baud rates 1M, 2M, 3M and 4M the dividers must be adjusted. */
1374         if (baud == 1000000 || baud == 2000000 || baud == 4000000) {
1375                 m = 64;
1376                 n = 100;
1377
1378                 p->uartclk = 64000000;
1379         } else if (baud == 3000000) {
1380                 m = 48;
1381                 n = 100;
1382
1383                 p->uartclk = 48000000;
1384         } else {
1385                 p->uartclk = 44236800;
1386         }
1387
1388         /* Reset the clock */
1389         reg = (m << BYT_PRV_CLK_M_VAL_SHIFT) | (n << BYT_PRV_CLK_N_VAL_SHIFT);
1390         writel(reg, p->membase + BYT_PRV_CLK);
1391         reg |= BYT_PRV_CLK_EN | BYT_PRV_CLK_UPDATE;
1392         writel(reg, p->membase + BYT_PRV_CLK);
1393
1394         /*
1395          * If auto-handshake mechanism is not enabled,
1396          * disable rts_n override
1397          */
1398         reg = readl(p->membase + BYT_GENERAL_REG);
1399         reg &= ~BYT_GENERAL_DIS_RTS_N_OVERRIDE;
1400         if (termios->c_cflag & CRTSCTS)
1401                 reg |= BYT_GENERAL_DIS_RTS_N_OVERRIDE;
1402         writel(reg, p->membase + BYT_GENERAL_REG);
1403
1404         serial8250_do_set_termios(p, termios, old);
1405 }
1406
1407 static bool byt_dma_filter(struct dma_chan *chan, void *param)
1408 {
1409         return chan->chan_id == *(int *)param;
1410 }
1411
1412 static int
1413 byt_serial_setup(struct serial_private *priv,
1414                  const struct pciserial_board *board,
1415                  struct uart_8250_port *port, int idx)
1416 {
1417         struct uart_8250_dma *dma;
1418         int ret;
1419
1420         dma = devm_kzalloc(port->port.dev, sizeof(*dma), GFP_KERNEL);
1421         if (!dma)
1422                 return -ENOMEM;
1423
1424         switch (priv->dev->device) {
1425         case PCI_DEVICE_ID_INTEL_BYT_UART1:
1426                 dma->rx_chan_id = 3;
1427                 dma->tx_chan_id = 2;
1428                 break;
1429         case PCI_DEVICE_ID_INTEL_BYT_UART2:
1430                 dma->rx_chan_id = 5;
1431                 dma->tx_chan_id = 4;
1432                 break;
1433         default:
1434                 return -EINVAL;
1435         }
1436
1437         dma->rxconf.slave_id = dma->rx_chan_id;
1438         dma->rxconf.src_maxburst = 16;
1439
1440         dma->txconf.slave_id = dma->tx_chan_id;
1441         dma->txconf.dst_maxburst = 16;
1442
1443         dma->fn = byt_dma_filter;
1444         dma->rx_param = &dma->rx_chan_id;
1445         dma->tx_param = &dma->tx_chan_id;
1446
1447         ret = pci_default_setup(priv, board, port, idx);
1448         port->port.iotype = UPIO_MEM;
1449         port->port.type = PORT_16550A;
1450         port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1451         port->port.set_termios = byt_set_termios;
1452         port->port.fifosize = 64;
1453         port->tx_loadsz = 64;
1454         port->dma = dma;
1455         port->capabilities = UART_CAP_FIFO | UART_CAP_AFE;
1456
1457         /* Disable Tx counter interrupts */
1458         writel(BYT_TX_OVF_INT_MASK, port->port.membase + BYT_TX_OVF_INT);
1459
1460         return ret;
1461 }
1462
1463 static int
1464 pci_omegapci_setup(struct serial_private *priv,
1465                       const struct pciserial_board *board,
1466                       struct uart_8250_port *port, int idx)
1467 {
1468         return setup_port(priv, port, 2, idx * 8, 0);
1469 }
1470
1471 static int
1472 pci_brcm_trumanage_setup(struct serial_private *priv,
1473                          const struct pciserial_board *board,
1474                          struct uart_8250_port *port, int idx)
1475 {
1476         int ret = pci_default_setup(priv, board, port, idx);
1477
1478         port->port.type = PORT_BRCM_TRUMANAGE;
1479         port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1480         return ret;
1481 }
1482
1483 static int pci_fintek_setup(struct serial_private *priv,
1484                             const struct pciserial_board *board,
1485                             struct uart_8250_port *port, int idx)
1486 {
1487         struct pci_dev *pdev = priv->dev;
1488         unsigned long base;
1489         unsigned long iobase;
1490         unsigned long ciobase = 0;
1491         u8 config_base;
1492
1493         /*
1494          * We are supposed to be able to read these from the PCI config space,
1495          * but the values there don't seem to match what we need to use, so
1496          * just use these hard-coded values for now, as they are correct.
1497          */
1498         switch (idx) {
1499         case 0: iobase = 0xe000; config_base = 0x40; break;
1500         case 1: iobase = 0xe008; config_base = 0x48; break;
1501         case 2: iobase = 0xe010; config_base = 0x50; break;
1502         case 3: iobase = 0xe018; config_base = 0x58; break;
1503         case 4: iobase = 0xe020; config_base = 0x60; break;
1504         case 5: iobase = 0xe028; config_base = 0x68; break;
1505         case 6: iobase = 0xe030; config_base = 0x70; break;
1506         case 7: iobase = 0xe038; config_base = 0x78; break;
1507         case 8: iobase = 0xe040; config_base = 0x80; break;
1508         case 9: iobase = 0xe048; config_base = 0x88; break;
1509         case 10: iobase = 0xe050; config_base = 0x90; break;
1510         case 11: iobase = 0xe058; config_base = 0x98; break;
1511         default:
1512                 /* Unknown number of ports, get out of here */
1513                 return -EINVAL;
1514         }
1515
1516         if (idx < 4) {
1517                 base = pci_resource_start(priv->dev, 3);
1518                 ciobase = (int)(base + (0x8 * idx));
1519         }
1520
1521         dev_dbg(&pdev->dev, "%s: idx=%d iobase=0x%lx ciobase=0x%lx config_base=0x%2x\n",
1522                 __func__, idx, iobase, ciobase, config_base);
1523
1524         /* Enable UART I/O port */
1525         pci_write_config_byte(pdev, config_base + 0x00, 0x01);
1526
1527         /* Select 128-byte FIFO and 8x FIFO threshold */
1528         pci_write_config_byte(pdev, config_base + 0x01, 0x33);
1529
1530         /* LSB UART */
1531         pci_write_config_byte(pdev, config_base + 0x04, (u8)(iobase & 0xff));
1532
1533         /* MSB UART */
1534         pci_write_config_byte(pdev, config_base + 0x05, (u8)((iobase & 0xff00) >> 8));
1535
1536         /* irq number, this usually fails, but the spec says to do it anyway. */
1537         pci_write_config_byte(pdev, config_base + 0x06, pdev->irq);
1538
1539         port->port.iotype = UPIO_PORT;
1540         port->port.iobase = iobase;
1541         port->port.mapbase = 0;
1542         port->port.membase = NULL;
1543         port->port.regshift = 0;
1544
1545         return 0;
1546 }
1547
1548 static int skip_tx_en_setup(struct serial_private *priv,
1549                         const struct pciserial_board *board,
1550                         struct uart_8250_port *port, int idx)
1551 {
1552         port->port.flags |= UPF_NO_TXEN_TEST;
1553         dev_dbg(&priv->dev->dev,
1554                 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n",
1555                 priv->dev->vendor, priv->dev->device,
1556                 priv->dev->subsystem_vendor, priv->dev->subsystem_device);
1557
1558         return pci_default_setup(priv, board, port, idx);
1559 }
1560
1561 static void kt_handle_break(struct uart_port *p)
1562 {
1563         struct uart_8250_port *up =
1564                 container_of(p, struct uart_8250_port, port);
1565         /*
1566          * On receipt of a BI, serial device in Intel ME (Intel
1567          * management engine) needs to have its fifos cleared for sane
1568          * SOL (Serial Over Lan) output.
1569          */
1570         serial8250_clear_and_reinit_fifos(up);
1571 }
1572
1573 static unsigned int kt_serial_in(struct uart_port *p, int offset)
1574 {
1575         struct uart_8250_port *up =
1576                 container_of(p, struct uart_8250_port, port);
1577         unsigned int val;
1578
1579         /*
1580          * When the Intel ME (management engine) gets reset its serial
1581          * port registers could return 0 momentarily.  Functions like
1582          * serial8250_console_write, read and save the IER, perform
1583          * some operation and then restore it.  In order to avoid
1584          * setting IER register inadvertently to 0, if the value read
1585          * is 0, double check with ier value in uart_8250_port and use
1586          * that instead.  up->ier should be the same value as what is
1587          * currently configured.
1588          */
1589         val = inb(p->iobase + offset);
1590         if (offset == UART_IER) {
1591                 if (val == 0)
1592                         val = up->ier;
1593         }
1594         return val;
1595 }
1596
1597 static int kt_serial_setup(struct serial_private *priv,
1598                            const struct pciserial_board *board,
1599                            struct uart_8250_port *port, int idx)
1600 {
1601         port->port.flags |= UPF_BUG_THRE;
1602         port->port.serial_in = kt_serial_in;
1603         port->port.handle_break = kt_handle_break;
1604         return skip_tx_en_setup(priv, board, port, idx);
1605 }
1606
1607 static int pci_eg20t_init(struct pci_dev *dev)
1608 {
1609 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1610         return -ENODEV;
1611 #else
1612         return 0;
1613 #endif
1614 }
1615
1616 static int
1617 pci_xr17c154_setup(struct serial_private *priv,
1618                   const struct pciserial_board *board,
1619                   struct uart_8250_port *port, int idx)
1620 {
1621         port->port.flags |= UPF_EXAR_EFR;
1622         return pci_default_setup(priv, board, port, idx);
1623 }
1624
1625 static int
1626 pci_xr17v35x_setup(struct serial_private *priv,
1627                   const struct pciserial_board *board,
1628                   struct uart_8250_port *port, int idx)
1629 {
1630         u8 __iomem *p;
1631
1632         p = pci_ioremap_bar(priv->dev, 0);
1633         if (p == NULL)
1634                 return -ENOMEM;
1635
1636         port->port.flags |= UPF_EXAR_EFR;
1637
1638         /*
1639          * Setup Multipurpose Input/Output pins.
1640          */
1641         if (idx == 0) {
1642                 writeb(0x00, p + 0x8f); /*MPIOINT[7:0]*/
1643                 writeb(0x00, p + 0x90); /*MPIOLVL[7:0]*/
1644                 writeb(0x00, p + 0x91); /*MPIO3T[7:0]*/
1645                 writeb(0x00, p + 0x92); /*MPIOINV[7:0]*/
1646                 writeb(0x00, p + 0x93); /*MPIOSEL[7:0]*/
1647                 writeb(0x00, p + 0x94); /*MPIOOD[7:0]*/
1648                 writeb(0x00, p + 0x95); /*MPIOINT[15:8]*/
1649                 writeb(0x00, p + 0x96); /*MPIOLVL[15:8]*/
1650                 writeb(0x00, p + 0x97); /*MPIO3T[15:8]*/
1651                 writeb(0x00, p + 0x98); /*MPIOINV[15:8]*/
1652                 writeb(0x00, p + 0x99); /*MPIOSEL[15:8]*/
1653                 writeb(0x00, p + 0x9a); /*MPIOOD[15:8]*/
1654         }
1655         writeb(0x00, p + UART_EXAR_8XMODE);
1656         writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1657         writeb(128, p + UART_EXAR_TXTRG);
1658         writeb(128, p + UART_EXAR_RXTRG);
1659         iounmap(p);
1660
1661         return pci_default_setup(priv, board, port, idx);
1662 }
1663
1664 #define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004
1665 #define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002
1666 #define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a
1667 #define PCI_DEVICE_ID_COMMTECH_2328PCI335 0x000b
1668
1669 static int
1670 pci_fastcom335_setup(struct serial_private *priv,
1671                   const struct pciserial_board *board,
1672                   struct uart_8250_port *port, int idx)
1673 {
1674         u8 __iomem *p;
1675
1676         p = pci_ioremap_bar(priv->dev, 0);
1677         if (p == NULL)
1678                 return -ENOMEM;
1679
1680         port->port.flags |= UPF_EXAR_EFR;
1681
1682         /*
1683          * Setup Multipurpose Input/Output pins.
1684          */
1685         if (idx == 0) {
1686                 switch (priv->dev->device) {
1687                 case PCI_DEVICE_ID_COMMTECH_4222PCI335:
1688                 case PCI_DEVICE_ID_COMMTECH_4224PCI335:
1689                         writeb(0x78, p + 0x90); /* MPIOLVL[7:0] */
1690                         writeb(0x00, p + 0x92); /* MPIOINV[7:0] */
1691                         writeb(0x00, p + 0x93); /* MPIOSEL[7:0] */
1692                         break;
1693                 case PCI_DEVICE_ID_COMMTECH_2324PCI335:
1694                 case PCI_DEVICE_ID_COMMTECH_2328PCI335:
1695                         writeb(0x00, p + 0x90); /* MPIOLVL[7:0] */
1696                         writeb(0xc0, p + 0x92); /* MPIOINV[7:0] */
1697                         writeb(0xc0, p + 0x93); /* MPIOSEL[7:0] */
1698                         break;
1699                 }
1700                 writeb(0x00, p + 0x8f); /* MPIOINT[7:0] */
1701                 writeb(0x00, p + 0x91); /* MPIO3T[7:0] */
1702                 writeb(0x00, p + 0x94); /* MPIOOD[7:0] */
1703         }
1704         writeb(0x00, p + UART_EXAR_8XMODE);
1705         writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1706         writeb(32, p + UART_EXAR_TXTRG);
1707         writeb(32, p + UART_EXAR_RXTRG);
1708         iounmap(p);
1709
1710         return pci_default_setup(priv, board, port, idx);
1711 }
1712
1713 static int
1714 pci_wch_ch353_setup(struct serial_private *priv,
1715                     const struct pciserial_board *board,
1716                     struct uart_8250_port *port, int idx)
1717 {
1718         port->port.flags |= UPF_FIXED_TYPE;
1719         port->port.type = PORT_16550A;
1720         return pci_default_setup(priv, board, port, idx);
1721 }
1722
1723 #define PCI_VENDOR_ID_SBSMODULARIO      0x124B
1724 #define PCI_SUBVENDOR_ID_SBSMODULARIO   0x124B
1725 #define PCI_DEVICE_ID_OCTPRO            0x0001
1726 #define PCI_SUBDEVICE_ID_OCTPRO232      0x0108
1727 #define PCI_SUBDEVICE_ID_OCTPRO422      0x0208
1728 #define PCI_SUBDEVICE_ID_POCTAL232      0x0308
1729 #define PCI_SUBDEVICE_ID_POCTAL422      0x0408
1730 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00   0x2500
1731 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30   0x2530
1732 #define PCI_VENDOR_ID_ADVANTECH         0x13fe
1733 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
1734 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
1735 #define PCI_DEVICE_ID_TITAN_200I        0x8028
1736 #define PCI_DEVICE_ID_TITAN_400I        0x8048
1737 #define PCI_DEVICE_ID_TITAN_800I        0x8088
1738 #define PCI_DEVICE_ID_TITAN_800EH       0xA007
1739 #define PCI_DEVICE_ID_TITAN_800EHB      0xA008
1740 #define PCI_DEVICE_ID_TITAN_400EH       0xA009
1741 #define PCI_DEVICE_ID_TITAN_100E        0xA010
1742 #define PCI_DEVICE_ID_TITAN_200E        0xA012
1743 #define PCI_DEVICE_ID_TITAN_400E        0xA013
1744 #define PCI_DEVICE_ID_TITAN_800E        0xA014
1745 #define PCI_DEVICE_ID_TITAN_200EI       0xA016
1746 #define PCI_DEVICE_ID_TITAN_200EISI     0xA017
1747 #define PCI_DEVICE_ID_TITAN_400V3       0xA310
1748 #define PCI_DEVICE_ID_TITAN_410V3       0xA312
1749 #define PCI_DEVICE_ID_TITAN_800V3       0xA314
1750 #define PCI_DEVICE_ID_TITAN_800V3B      0xA315
1751 #define PCI_DEVICE_ID_OXSEMI_16PCI958   0x9538
1752 #define PCIE_DEVICE_ID_NEO_2_OX_IBM     0x00F6
1753 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA  0xc001
1754 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
1755 #define PCI_VENDOR_ID_WCH               0x4348
1756 #define PCI_DEVICE_ID_WCH_CH352_2S      0x3253
1757 #define PCI_DEVICE_ID_WCH_CH353_4S      0x3453
1758 #define PCI_DEVICE_ID_WCH_CH353_2S1PF   0x5046
1759 #define PCI_DEVICE_ID_WCH_CH353_2S1P    0x7053
1760 #define PCI_VENDOR_ID_AGESTAR           0x5372
1761 #define PCI_DEVICE_ID_AGESTAR_9375      0x6872
1762 #define PCI_VENDOR_ID_ASIX              0x9710
1763 #define PCI_DEVICE_ID_COMMTECH_4224PCIE 0x0020
1764 #define PCI_DEVICE_ID_COMMTECH_4228PCIE 0x0021
1765 #define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022
1766 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
1767 #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e
1768
1769 #define PCI_VENDOR_ID_SUNIX             0x1fd4
1770 #define PCI_DEVICE_ID_SUNIX_1999        0x1999
1771
1772
1773 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1774 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
1775 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588
1776
1777 /*
1778  * Master list of serial port init/setup/exit quirks.
1779  * This does not describe the general nature of the port.
1780  * (ie, baud base, number and location of ports, etc)
1781  *
1782  * This list is ordered alphabetically by vendor then device.
1783  * Specific entries must come before more generic entries.
1784  */
1785 static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
1786         /*
1787         * ADDI-DATA GmbH communication cards <info@addi-data.com>
1788         */
1789         {
1790                 .vendor         = PCI_VENDOR_ID_AMCC,
1791                 .device         = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
1792                 .subvendor      = PCI_ANY_ID,
1793                 .subdevice      = PCI_ANY_ID,
1794                 .setup          = addidata_apci7800_setup,
1795         },
1796         /*
1797          * AFAVLAB cards - these may be called via parport_serial
1798          *  It is not clear whether this applies to all products.
1799          */
1800         {
1801                 .vendor         = PCI_VENDOR_ID_AFAVLAB,
1802                 .device         = PCI_ANY_ID,
1803                 .subvendor      = PCI_ANY_ID,
1804                 .subdevice      = PCI_ANY_ID,
1805                 .setup          = afavlab_setup,
1806         },
1807         /*
1808          * HP Diva
1809          */
1810         {
1811                 .vendor         = PCI_VENDOR_ID_HP,
1812                 .device         = PCI_DEVICE_ID_HP_DIVA,
1813                 .subvendor      = PCI_ANY_ID,
1814                 .subdevice      = PCI_ANY_ID,
1815                 .init           = pci_hp_diva_init,
1816                 .setup          = pci_hp_diva_setup,
1817         },
1818         /*
1819          * Intel
1820          */
1821         {
1822                 .vendor         = PCI_VENDOR_ID_INTEL,
1823                 .device         = PCI_DEVICE_ID_INTEL_80960_RP,
1824                 .subvendor      = 0xe4bf,
1825                 .subdevice      = PCI_ANY_ID,
1826                 .init           = pci_inteli960ni_init,
1827                 .setup          = pci_default_setup,
1828         },
1829         {
1830                 .vendor         = PCI_VENDOR_ID_INTEL,
1831                 .device         = PCI_DEVICE_ID_INTEL_8257X_SOL,
1832                 .subvendor      = PCI_ANY_ID,
1833                 .subdevice      = PCI_ANY_ID,
1834                 .setup          = skip_tx_en_setup,
1835         },
1836         {
1837                 .vendor         = PCI_VENDOR_ID_INTEL,
1838                 .device         = PCI_DEVICE_ID_INTEL_82573L_SOL,
1839                 .subvendor      = PCI_ANY_ID,
1840                 .subdevice      = PCI_ANY_ID,
1841                 .setup          = skip_tx_en_setup,
1842         },
1843         {
1844                 .vendor         = PCI_VENDOR_ID_INTEL,
1845                 .device         = PCI_DEVICE_ID_INTEL_82573E_SOL,
1846                 .subvendor      = PCI_ANY_ID,
1847                 .subdevice      = PCI_ANY_ID,
1848                 .setup          = skip_tx_en_setup,
1849         },
1850         {
1851                 .vendor         = PCI_VENDOR_ID_INTEL,
1852                 .device         = PCI_DEVICE_ID_INTEL_CE4100_UART,
1853                 .subvendor      = PCI_ANY_ID,
1854                 .subdevice      = PCI_ANY_ID,
1855                 .setup          = ce4100_serial_setup,
1856         },
1857         {
1858                 .vendor         = PCI_VENDOR_ID_INTEL,
1859                 .device         = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
1860                 .subvendor      = PCI_ANY_ID,
1861                 .subdevice      = PCI_ANY_ID,
1862                 .setup          = kt_serial_setup,
1863         },
1864         {
1865                 .vendor         = PCI_VENDOR_ID_INTEL,
1866                 .device         = PCI_DEVICE_ID_INTEL_BYT_UART1,
1867                 .subvendor      = PCI_ANY_ID,
1868                 .subdevice      = PCI_ANY_ID,
1869                 .setup          = byt_serial_setup,
1870         },
1871         {
1872                 .vendor         = PCI_VENDOR_ID_INTEL,
1873                 .device         = PCI_DEVICE_ID_INTEL_BYT_UART2,
1874                 .subvendor      = PCI_ANY_ID,
1875                 .subdevice      = PCI_ANY_ID,
1876                 .setup          = byt_serial_setup,
1877         },
1878         /*
1879          * ITE
1880          */
1881         {
1882                 .vendor         = PCI_VENDOR_ID_ITE,
1883                 .device         = PCI_DEVICE_ID_ITE_8872,
1884                 .subvendor      = PCI_ANY_ID,
1885                 .subdevice      = PCI_ANY_ID,
1886                 .init           = pci_ite887x_init,
1887                 .setup          = pci_default_setup,
1888                 .exit           = pci_ite887x_exit,
1889         },
1890         /*
1891          * National Instruments
1892          */
1893         {
1894                 .vendor         = PCI_VENDOR_ID_NI,
1895                 .device         = PCI_DEVICE_ID_NI_PCI23216,
1896                 .subvendor      = PCI_ANY_ID,
1897                 .subdevice      = PCI_ANY_ID,
1898                 .init           = pci_ni8420_init,
1899                 .setup          = pci_default_setup,
1900                 .exit           = pci_ni8420_exit,
1901         },
1902         {
1903                 .vendor         = PCI_VENDOR_ID_NI,
1904                 .device         = PCI_DEVICE_ID_NI_PCI2328,
1905                 .subvendor      = PCI_ANY_ID,
1906                 .subdevice      = PCI_ANY_ID,
1907                 .init           = pci_ni8420_init,
1908                 .setup          = pci_default_setup,
1909                 .exit           = pci_ni8420_exit,
1910         },
1911         {
1912                 .vendor         = PCI_VENDOR_ID_NI,
1913                 .device         = PCI_DEVICE_ID_NI_PCI2324,
1914                 .subvendor      = PCI_ANY_ID,
1915                 .subdevice      = PCI_ANY_ID,
1916                 .init           = pci_ni8420_init,
1917                 .setup          = pci_default_setup,
1918                 .exit           = pci_ni8420_exit,
1919         },
1920         {
1921                 .vendor         = PCI_VENDOR_ID_NI,
1922                 .device         = PCI_DEVICE_ID_NI_PCI2322,
1923                 .subvendor      = PCI_ANY_ID,
1924                 .subdevice      = PCI_ANY_ID,
1925                 .init           = pci_ni8420_init,
1926                 .setup          = pci_default_setup,
1927                 .exit           = pci_ni8420_exit,
1928         },
1929         {
1930                 .vendor         = PCI_VENDOR_ID_NI,
1931                 .device         = PCI_DEVICE_ID_NI_PCI2324I,
1932                 .subvendor      = PCI_ANY_ID,
1933                 .subdevice      = PCI_ANY_ID,
1934                 .init           = pci_ni8420_init,
1935                 .setup          = pci_default_setup,
1936                 .exit           = pci_ni8420_exit,
1937         },
1938         {
1939                 .vendor         = PCI_VENDOR_ID_NI,
1940                 .device         = PCI_DEVICE_ID_NI_PCI2322I,
1941                 .subvendor      = PCI_ANY_ID,
1942                 .subdevice      = PCI_ANY_ID,
1943                 .init           = pci_ni8420_init,
1944                 .setup          = pci_default_setup,
1945                 .exit           = pci_ni8420_exit,
1946         },
1947         {
1948                 .vendor         = PCI_VENDOR_ID_NI,
1949                 .device         = PCI_DEVICE_ID_NI_PXI8420_23216,
1950                 .subvendor      = PCI_ANY_ID,
1951                 .subdevice      = PCI_ANY_ID,
1952                 .init           = pci_ni8420_init,
1953                 .setup          = pci_default_setup,
1954                 .exit           = pci_ni8420_exit,
1955         },
1956         {
1957                 .vendor         = PCI_VENDOR_ID_NI,
1958                 .device         = PCI_DEVICE_ID_NI_PXI8420_2328,
1959                 .subvendor      = PCI_ANY_ID,
1960                 .subdevice      = PCI_ANY_ID,
1961                 .init           = pci_ni8420_init,
1962                 .setup          = pci_default_setup,
1963                 .exit           = pci_ni8420_exit,
1964         },
1965         {
1966                 .vendor         = PCI_VENDOR_ID_NI,
1967                 .device         = PCI_DEVICE_ID_NI_PXI8420_2324,
1968                 .subvendor      = PCI_ANY_ID,
1969                 .subdevice      = PCI_ANY_ID,
1970                 .init           = pci_ni8420_init,
1971                 .setup          = pci_default_setup,
1972                 .exit           = pci_ni8420_exit,
1973         },
1974         {
1975                 .vendor         = PCI_VENDOR_ID_NI,
1976                 .device         = PCI_DEVICE_ID_NI_PXI8420_2322,
1977                 .subvendor      = PCI_ANY_ID,
1978                 .subdevice      = PCI_ANY_ID,
1979                 .init           = pci_ni8420_init,
1980                 .setup          = pci_default_setup,
1981                 .exit           = pci_ni8420_exit,
1982         },
1983         {
1984                 .vendor         = PCI_VENDOR_ID_NI,
1985                 .device         = PCI_DEVICE_ID_NI_PXI8422_2324,
1986                 .subvendor      = PCI_ANY_ID,
1987                 .subdevice      = PCI_ANY_ID,
1988                 .init           = pci_ni8420_init,
1989                 .setup          = pci_default_setup,
1990                 .exit           = pci_ni8420_exit,
1991         },
1992         {
1993                 .vendor         = PCI_VENDOR_ID_NI,
1994                 .device         = PCI_DEVICE_ID_NI_PXI8422_2322,
1995                 .subvendor      = PCI_ANY_ID,
1996                 .subdevice      = PCI_ANY_ID,
1997                 .init           = pci_ni8420_init,
1998                 .setup          = pci_default_setup,
1999                 .exit           = pci_ni8420_exit,
2000         },
2001         {
2002                 .vendor         = PCI_VENDOR_ID_NI,
2003                 .device         = PCI_ANY_ID,
2004                 .subvendor      = PCI_ANY_ID,
2005                 .subdevice      = PCI_ANY_ID,
2006                 .init           = pci_ni8430_init,
2007                 .setup          = pci_ni8430_setup,
2008                 .exit           = pci_ni8430_exit,
2009         },
2010         /* Quatech */
2011         {
2012                 .vendor         = PCI_VENDOR_ID_QUATECH,
2013                 .device         = PCI_ANY_ID,
2014                 .subvendor      = PCI_ANY_ID,
2015                 .subdevice      = PCI_ANY_ID,
2016                 .init           = pci_quatech_init,
2017                 .setup          = pci_quatech_setup,
2018                 .exit           = pci_quatech_exit,
2019         },
2020         /*
2021          * Panacom
2022          */
2023         {
2024                 .vendor         = PCI_VENDOR_ID_PANACOM,
2025                 .device         = PCI_DEVICE_ID_PANACOM_QUADMODEM,
2026                 .subvendor      = PCI_ANY_ID,
2027                 .subdevice      = PCI_ANY_ID,
2028                 .init           = pci_plx9050_init,
2029                 .setup          = pci_default_setup,
2030                 .exit           = pci_plx9050_exit,
2031         },
2032         {
2033                 .vendor         = PCI_VENDOR_ID_PANACOM,
2034                 .device         = PCI_DEVICE_ID_PANACOM_DUALMODEM,
2035                 .subvendor      = PCI_ANY_ID,
2036                 .subdevice      = PCI_ANY_ID,
2037                 .init           = pci_plx9050_init,
2038                 .setup          = pci_default_setup,
2039                 .exit           = pci_plx9050_exit,
2040         },
2041         /*
2042          * Pericom
2043          */
2044         {
2045                 .vendor         = 0x12d8,
2046                 .device         = 0x7952,
2047                 .subvendor      = PCI_ANY_ID,
2048                 .subdevice      = PCI_ANY_ID,
2049                 .setup          = pci_pericom_setup,
2050         },
2051         {
2052                 .vendor         = 0x12d8,
2053                 .device         = 0x7954,
2054                 .subvendor      = PCI_ANY_ID,
2055                 .subdevice      = PCI_ANY_ID,
2056                 .setup          = pci_pericom_setup,
2057         },
2058         {
2059                 .vendor         = 0x12d8,
2060                 .device         = 0x7958,
2061                 .subvendor      = PCI_ANY_ID,
2062                 .subdevice      = PCI_ANY_ID,
2063                 .setup          = pci_pericom_setup,
2064         },
2065
2066         /*
2067          * PLX
2068          */
2069         {
2070                 .vendor         = PCI_VENDOR_ID_PLX,
2071                 .device         = PCI_DEVICE_ID_PLX_9030,
2072                 .subvendor      = PCI_SUBVENDOR_ID_PERLE,
2073                 .subdevice      = PCI_ANY_ID,
2074                 .setup          = pci_default_setup,
2075         },
2076         {
2077                 .vendor         = PCI_VENDOR_ID_PLX,
2078                 .device         = PCI_DEVICE_ID_PLX_9050,
2079                 .subvendor      = PCI_SUBVENDOR_ID_EXSYS,
2080                 .subdevice      = PCI_SUBDEVICE_ID_EXSYS_4055,
2081                 .init           = pci_plx9050_init,
2082                 .setup          = pci_default_setup,
2083                 .exit           = pci_plx9050_exit,
2084         },
2085         {
2086                 .vendor         = PCI_VENDOR_ID_PLX,
2087                 .device         = PCI_DEVICE_ID_PLX_9050,
2088                 .subvendor      = PCI_SUBVENDOR_ID_KEYSPAN,
2089                 .subdevice      = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
2090                 .init           = pci_plx9050_init,
2091                 .setup          = pci_default_setup,
2092                 .exit           = pci_plx9050_exit,
2093         },
2094         {
2095                 .vendor         = PCI_VENDOR_ID_PLX,
2096                 .device         = PCI_DEVICE_ID_PLX_ROMULUS,
2097                 .subvendor      = PCI_VENDOR_ID_PLX,
2098                 .subdevice      = PCI_DEVICE_ID_PLX_ROMULUS,
2099                 .init           = pci_plx9050_init,
2100                 .setup          = pci_default_setup,
2101                 .exit           = pci_plx9050_exit,
2102         },
2103         /*
2104          * SBS Technologies, Inc., PMC-OCTALPRO 232
2105          */
2106         {
2107                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
2108                 .device         = PCI_DEVICE_ID_OCTPRO,
2109                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
2110                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO232,
2111                 .init           = sbs_init,
2112                 .setup          = sbs_setup,
2113                 .exit           = sbs_exit,
2114         },
2115         /*
2116          * SBS Technologies, Inc., PMC-OCTALPRO 422
2117          */
2118         {
2119                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
2120                 .device         = PCI_DEVICE_ID_OCTPRO,
2121                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
2122                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO422,
2123                 .init           = sbs_init,
2124                 .setup          = sbs_setup,
2125                 .exit           = sbs_exit,
2126         },
2127         /*
2128          * SBS Technologies, Inc., P-Octal 232
2129          */
2130         {
2131                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
2132                 .device         = PCI_DEVICE_ID_OCTPRO,
2133                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
2134                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL232,
2135                 .init           = sbs_init,
2136                 .setup          = sbs_setup,
2137                 .exit           = sbs_exit,
2138         },
2139         /*
2140          * SBS Technologies, Inc., P-Octal 422
2141          */
2142         {
2143                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
2144                 .device         = PCI_DEVICE_ID_OCTPRO,
2145                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
2146                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL422,
2147                 .init           = sbs_init,
2148                 .setup          = sbs_setup,
2149                 .exit           = sbs_exit,
2150         },
2151         /*
2152          * SIIG cards - these may be called via parport_serial
2153          */
2154         {
2155                 .vendor         = PCI_VENDOR_ID_SIIG,
2156                 .device         = PCI_ANY_ID,
2157                 .subvendor      = PCI_ANY_ID,
2158                 .subdevice      = PCI_ANY_ID,
2159                 .init           = pci_siig_init,
2160                 .setup          = pci_siig_setup,
2161         },
2162         /*
2163          * Titan cards
2164          */
2165         {
2166                 .vendor         = PCI_VENDOR_ID_TITAN,
2167                 .device         = PCI_DEVICE_ID_TITAN_400L,
2168                 .subvendor      = PCI_ANY_ID,
2169                 .subdevice      = PCI_ANY_ID,
2170                 .setup          = titan_400l_800l_setup,
2171         },
2172         {
2173                 .vendor         = PCI_VENDOR_ID_TITAN,
2174                 .device         = PCI_DEVICE_ID_TITAN_800L,
2175                 .subvendor      = PCI_ANY_ID,
2176                 .subdevice      = PCI_ANY_ID,
2177                 .setup          = titan_400l_800l_setup,
2178         },
2179         /*
2180          * Timedia cards
2181          */
2182         {
2183                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
2184                 .device         = PCI_DEVICE_ID_TIMEDIA_1889,
2185                 .subvendor      = PCI_VENDOR_ID_TIMEDIA,
2186                 .subdevice      = PCI_ANY_ID,
2187                 .probe          = pci_timedia_probe,
2188                 .init           = pci_timedia_init,
2189                 .setup          = pci_timedia_setup,
2190         },
2191         {
2192                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
2193                 .device         = PCI_ANY_ID,
2194                 .subvendor      = PCI_ANY_ID,
2195                 .subdevice      = PCI_ANY_ID,
2196                 .setup          = pci_timedia_setup,
2197         },
2198         /*
2199          * SUNIX (Timedia) cards
2200          * Do not "probe" for these cards as there is at least one combination
2201          * card that should be handled by parport_pc that doesn't match the
2202          * rule in pci_timedia_probe.
2203          * It is part number is MIO5079A but its subdevice ID is 0x0102.
2204          * There are some boards with part number SER5037AL that report
2205          * subdevice ID 0x0002.
2206          */
2207         {
2208                 .vendor         = PCI_VENDOR_ID_SUNIX,
2209                 .device         = PCI_DEVICE_ID_SUNIX_1999,
2210                 .subvendor      = PCI_VENDOR_ID_SUNIX,
2211                 .subdevice      = PCI_ANY_ID,
2212                 .init           = pci_timedia_init,
2213                 .setup          = pci_timedia_setup,
2214         },
2215         /*
2216          * Exar cards
2217          */
2218         {
2219                 .vendor = PCI_VENDOR_ID_EXAR,
2220                 .device = PCI_DEVICE_ID_EXAR_XR17C152,
2221                 .subvendor      = PCI_ANY_ID,
2222                 .subdevice      = PCI_ANY_ID,
2223                 .setup          = pci_xr17c154_setup,
2224         },
2225         {
2226                 .vendor = PCI_VENDOR_ID_EXAR,
2227                 .device = PCI_DEVICE_ID_EXAR_XR17C154,
2228                 .subvendor      = PCI_ANY_ID,
2229                 .subdevice      = PCI_ANY_ID,
2230                 .setup          = pci_xr17c154_setup,
2231         },
2232         {
2233                 .vendor = PCI_VENDOR_ID_EXAR,
2234                 .device = PCI_DEVICE_ID_EXAR_XR17C158,
2235                 .subvendor      = PCI_ANY_ID,
2236                 .subdevice      = PCI_ANY_ID,
2237                 .setup          = pci_xr17c154_setup,
2238         },
2239         {
2240                 .vendor = PCI_VENDOR_ID_EXAR,
2241                 .device = PCI_DEVICE_ID_EXAR_XR17V352,
2242                 .subvendor      = PCI_ANY_ID,
2243                 .subdevice      = PCI_ANY_ID,
2244                 .setup          = pci_xr17v35x_setup,
2245         },
2246         {
2247                 .vendor = PCI_VENDOR_ID_EXAR,
2248                 .device = PCI_DEVICE_ID_EXAR_XR17V354,
2249                 .subvendor      = PCI_ANY_ID,
2250                 .subdevice      = PCI_ANY_ID,
2251                 .setup          = pci_xr17v35x_setup,
2252         },
2253         {
2254                 .vendor = PCI_VENDOR_ID_EXAR,
2255                 .device = PCI_DEVICE_ID_EXAR_XR17V358,
2256                 .subvendor      = PCI_ANY_ID,
2257                 .subdevice      = PCI_ANY_ID,
2258                 .setup          = pci_xr17v35x_setup,
2259         },
2260         /*
2261          * Xircom cards
2262          */
2263         {
2264                 .vendor         = PCI_VENDOR_ID_XIRCOM,
2265                 .device         = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2266                 .subvendor      = PCI_ANY_ID,
2267                 .subdevice      = PCI_ANY_ID,
2268                 .init           = pci_xircom_init,
2269                 .setup          = pci_default_setup,
2270         },
2271         /*
2272          * Netmos cards - these may be called via parport_serial
2273          */
2274         {
2275                 .vendor         = PCI_VENDOR_ID_NETMOS,
2276                 .device         = PCI_ANY_ID,
2277                 .subvendor      = PCI_ANY_ID,
2278                 .subdevice      = PCI_ANY_ID,
2279                 .init           = pci_netmos_init,
2280                 .setup          = pci_netmos_9900_setup,
2281         },
2282         /*
2283          * For Oxford Semiconductor Tornado based devices
2284          */
2285         {
2286                 .vendor         = PCI_VENDOR_ID_OXSEMI,
2287                 .device         = PCI_ANY_ID,
2288                 .subvendor      = PCI_ANY_ID,
2289                 .subdevice      = PCI_ANY_ID,
2290                 .init           = pci_oxsemi_tornado_init,
2291                 .setup          = pci_default_setup,
2292         },
2293         {
2294                 .vendor         = PCI_VENDOR_ID_MAINPINE,
2295                 .device         = PCI_ANY_ID,
2296                 .subvendor      = PCI_ANY_ID,
2297                 .subdevice      = PCI_ANY_ID,
2298                 .init           = pci_oxsemi_tornado_init,
2299                 .setup          = pci_default_setup,
2300         },
2301         {
2302                 .vendor         = PCI_VENDOR_ID_DIGI,
2303                 .device         = PCIE_DEVICE_ID_NEO_2_OX_IBM,
2304                 .subvendor              = PCI_SUBVENDOR_ID_IBM,
2305                 .subdevice              = PCI_ANY_ID,
2306                 .init                   = pci_oxsemi_tornado_init,
2307                 .setup          = pci_default_setup,
2308         },
2309         {
2310                 .vendor         = PCI_VENDOR_ID_INTEL,
2311                 .device         = 0x8811,
2312                 .subvendor      = PCI_ANY_ID,
2313                 .subdevice      = PCI_ANY_ID,
2314                 .init           = pci_eg20t_init,
2315                 .setup          = pci_default_setup,
2316         },
2317         {
2318                 .vendor         = PCI_VENDOR_ID_INTEL,
2319                 .device         = 0x8812,
2320                 .subvendor      = PCI_ANY_ID,
2321                 .subdevice      = PCI_ANY_ID,
2322                 .init           = pci_eg20t_init,
2323                 .setup          = pci_default_setup,
2324         },
2325         {
2326                 .vendor         = PCI_VENDOR_ID_INTEL,
2327                 .device         = 0x8813,
2328                 .subvendor      = PCI_ANY_ID,
2329                 .subdevice      = PCI_ANY_ID,
2330                 .init           = pci_eg20t_init,
2331                 .setup          = pci_default_setup,
2332         },
2333         {
2334                 .vendor         = PCI_VENDOR_ID_INTEL,
2335                 .device         = 0x8814,
2336                 .subvendor      = PCI_ANY_ID,
2337                 .subdevice      = PCI_ANY_ID,
2338                 .init           = pci_eg20t_init,
2339                 .setup          = pci_default_setup,
2340         },
2341         {
2342                 .vendor         = 0x10DB,
2343                 .device         = 0x8027,
2344                 .subvendor      = PCI_ANY_ID,
2345                 .subdevice      = PCI_ANY_ID,
2346                 .init           = pci_eg20t_init,
2347                 .setup          = pci_default_setup,
2348         },
2349         {
2350                 .vendor         = 0x10DB,
2351                 .device         = 0x8028,
2352                 .subvendor      = PCI_ANY_ID,
2353                 .subdevice      = PCI_ANY_ID,
2354                 .init           = pci_eg20t_init,
2355                 .setup          = pci_default_setup,
2356         },
2357         {
2358                 .vendor         = 0x10DB,
2359                 .device         = 0x8029,
2360                 .subvendor      = PCI_ANY_ID,
2361                 .subdevice      = PCI_ANY_ID,
2362                 .init           = pci_eg20t_init,
2363                 .setup          = pci_default_setup,
2364         },
2365         {
2366                 .vendor         = 0x10DB,
2367                 .device         = 0x800C,
2368                 .subvendor      = PCI_ANY_ID,
2369                 .subdevice      = PCI_ANY_ID,
2370                 .init           = pci_eg20t_init,
2371                 .setup          = pci_default_setup,
2372         },
2373         {
2374                 .vendor         = 0x10DB,
2375                 .device         = 0x800D,
2376                 .subvendor      = PCI_ANY_ID,
2377                 .subdevice      = PCI_ANY_ID,
2378                 .init           = pci_eg20t_init,
2379                 .setup          = pci_default_setup,
2380         },
2381         /*
2382          * Cronyx Omega PCI (PLX-chip based)
2383          */
2384         {
2385                 .vendor         = PCI_VENDOR_ID_PLX,
2386                 .device         = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
2387                 .subvendor      = PCI_ANY_ID,
2388                 .subdevice      = PCI_ANY_ID,
2389                 .setup          = pci_omegapci_setup,
2390         },
2391         /* WCH CH353 2S1P card (16550 clone) */
2392         {
2393                 .vendor         = PCI_VENDOR_ID_WCH,
2394                 .device         = PCI_DEVICE_ID_WCH_CH353_2S1P,
2395                 .subvendor      = PCI_ANY_ID,
2396                 .subdevice      = PCI_ANY_ID,
2397                 .setup          = pci_wch_ch353_setup,
2398         },
2399         /* WCH CH353 4S card (16550 clone) */
2400         {
2401                 .vendor         = PCI_VENDOR_ID_WCH,
2402                 .device         = PCI_DEVICE_ID_WCH_CH353_4S,
2403                 .subvendor      = PCI_ANY_ID,
2404                 .subdevice      = PCI_ANY_ID,
2405                 .setup          = pci_wch_ch353_setup,
2406         },
2407         /* WCH CH353 2S1PF card (16550 clone) */
2408         {
2409                 .vendor         = PCI_VENDOR_ID_WCH,
2410                 .device         = PCI_DEVICE_ID_WCH_CH353_2S1PF,
2411                 .subvendor      = PCI_ANY_ID,
2412                 .subdevice      = PCI_ANY_ID,
2413                 .setup          = pci_wch_ch353_setup,
2414         },
2415         /* WCH CH352 2S card (16550 clone) */
2416         {
2417                 .vendor         = PCI_VENDOR_ID_WCH,
2418                 .device         = PCI_DEVICE_ID_WCH_CH352_2S,
2419                 .subvendor      = PCI_ANY_ID,
2420                 .subdevice      = PCI_ANY_ID,
2421                 .setup          = pci_wch_ch353_setup,
2422         },
2423         /*
2424          * ASIX devices with FIFO bug
2425          */
2426         {
2427                 .vendor         = PCI_VENDOR_ID_ASIX,
2428                 .device         = PCI_ANY_ID,
2429                 .subvendor      = PCI_ANY_ID,
2430                 .subdevice      = PCI_ANY_ID,
2431                 .setup          = pci_asix_setup,
2432         },
2433         /*
2434          * Commtech, Inc. Fastcom adapters
2435          *
2436          */
2437         {
2438                 .vendor = PCI_VENDOR_ID_COMMTECH,
2439                 .device = PCI_DEVICE_ID_COMMTECH_4222PCI335,
2440                 .subvendor      = PCI_ANY_ID,
2441                 .subdevice      = PCI_ANY_ID,
2442                 .setup          = pci_fastcom335_setup,
2443         },
2444         {
2445                 .vendor = PCI_VENDOR_ID_COMMTECH,
2446                 .device = PCI_DEVICE_ID_COMMTECH_4224PCI335,
2447                 .subvendor      = PCI_ANY_ID,
2448                 .subdevice      = PCI_ANY_ID,
2449                 .setup          = pci_fastcom335_setup,
2450         },
2451         {
2452                 .vendor = PCI_VENDOR_ID_COMMTECH,
2453                 .device = PCI_DEVICE_ID_COMMTECH_2324PCI335,
2454                 .subvendor      = PCI_ANY_ID,
2455                 .subdevice      = PCI_ANY_ID,
2456                 .setup          = pci_fastcom335_setup,
2457         },
2458         {
2459                 .vendor = PCI_VENDOR_ID_COMMTECH,
2460                 .device = PCI_DEVICE_ID_COMMTECH_2328PCI335,
2461                 .subvendor      = PCI_ANY_ID,
2462                 .subdevice      = PCI_ANY_ID,
2463                 .setup          = pci_fastcom335_setup,
2464         },
2465         {
2466                 .vendor = PCI_VENDOR_ID_COMMTECH,
2467                 .device = PCI_DEVICE_ID_COMMTECH_4222PCIE,
2468                 .subvendor      = PCI_ANY_ID,
2469                 .subdevice      = PCI_ANY_ID,
2470                 .setup          = pci_xr17v35x_setup,
2471         },
2472         {
2473                 .vendor = PCI_VENDOR_ID_COMMTECH,
2474                 .device = PCI_DEVICE_ID_COMMTECH_4224PCIE,
2475                 .subvendor      = PCI_ANY_ID,
2476                 .subdevice      = PCI_ANY_ID,
2477                 .setup          = pci_xr17v35x_setup,
2478         },
2479         {
2480                 .vendor = PCI_VENDOR_ID_COMMTECH,
2481                 .device = PCI_DEVICE_ID_COMMTECH_4228PCIE,
2482                 .subvendor      = PCI_ANY_ID,
2483                 .subdevice      = PCI_ANY_ID,
2484                 .setup          = pci_xr17v35x_setup,
2485         },
2486         /*
2487          * Broadcom TruManage (NetXtreme)
2488          */
2489         {
2490                 .vendor         = PCI_VENDOR_ID_BROADCOM,
2491                 .device         = PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
2492                 .subvendor      = PCI_ANY_ID,
2493                 .subdevice      = PCI_ANY_ID,
2494                 .setup          = pci_brcm_trumanage_setup,
2495         },
2496         {
2497                 .vendor         = 0x1c29,
2498                 .device         = 0x1104,
2499                 .subvendor      = PCI_ANY_ID,
2500                 .subdevice      = PCI_ANY_ID,
2501                 .setup          = pci_fintek_setup,
2502         },
2503         {
2504                 .vendor         = 0x1c29,
2505                 .device         = 0x1108,
2506                 .subvendor      = PCI_ANY_ID,
2507                 .subdevice      = PCI_ANY_ID,
2508                 .setup          = pci_fintek_setup,
2509         },
2510         {
2511                 .vendor         = 0x1c29,
2512                 .device         = 0x1112,
2513                 .subvendor      = PCI_ANY_ID,
2514                 .subdevice      = PCI_ANY_ID,
2515                 .setup          = pci_fintek_setup,
2516         },
2517
2518         /*
2519          * Default "match everything" terminator entry
2520          */
2521         {
2522                 .vendor         = PCI_ANY_ID,
2523                 .device         = PCI_ANY_ID,
2524                 .subvendor      = PCI_ANY_ID,
2525                 .subdevice      = PCI_ANY_ID,
2526                 .setup          = pci_default_setup,
2527         }
2528 };
2529
2530 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
2531 {
2532         return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
2533 }
2534
2535 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
2536 {
2537         struct pci_serial_quirk *quirk;
2538
2539         for (quirk = pci_serial_quirks; ; quirk++)
2540                 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
2541                     quirk_id_matches(quirk->device, dev->device) &&
2542                     quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
2543                     quirk_id_matches(quirk->subdevice, dev->subsystem_device))
2544                         break;
2545         return quirk;
2546 }
2547
2548 static inline int get_pci_irq(struct pci_dev *dev,
2549                                 const struct pciserial_board *board)
2550 {
2551         if (board->flags & FL_NOIRQ)
2552                 return 0;
2553         else
2554                 return dev->irq;
2555 }
2556
2557 /*
2558  * This is the configuration table for all of the PCI serial boards
2559  * which we support.  It is directly indexed by the pci_board_num_t enum
2560  * value, which is encoded in the pci_device_id PCI probe table's
2561  * driver_data member.
2562  *
2563  * The makeup of these names are:
2564  *  pbn_bn{_bt}_n_baud{_offsetinhex}
2565  *
2566  *  bn          = PCI BAR number
2567  *  bt          = Index using PCI BARs
2568  *  n           = number of serial ports
2569  *  baud        = baud rate
2570  *  offsetinhex = offset for each sequential port (in hex)
2571  *
2572  * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
2573  *
2574  * Please note: in theory if n = 1, _bt infix should make no difference.
2575  * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
2576  */
2577 enum pci_board_num_t {
2578         pbn_default = 0,
2579
2580         pbn_b0_1_115200,
2581         pbn_b0_2_115200,
2582         pbn_b0_4_115200,
2583         pbn_b0_5_115200,
2584         pbn_b0_8_115200,
2585
2586         pbn_b0_1_921600,
2587         pbn_b0_2_921600,
2588         pbn_b0_4_921600,
2589
2590         pbn_b0_2_1130000,
2591
2592         pbn_b0_4_1152000,
2593
2594         pbn_b0_2_1152000_200,
2595         pbn_b0_4_1152000_200,
2596         pbn_b0_8_1152000_200,
2597
2598         pbn_b0_2_1843200,
2599         pbn_b0_4_1843200,
2600
2601         pbn_b0_2_1843200_200,
2602         pbn_b0_4_1843200_200,
2603         pbn_b0_8_1843200_200,
2604
2605         pbn_b0_1_4000000,
2606
2607         pbn_b0_bt_1_115200,
2608         pbn_b0_bt_2_115200,
2609         pbn_b0_bt_4_115200,
2610         pbn_b0_bt_8_115200,
2611
2612         pbn_b0_bt_1_460800,
2613         pbn_b0_bt_2_460800,
2614         pbn_b0_bt_4_460800,
2615
2616         pbn_b0_bt_1_921600,
2617         pbn_b0_bt_2_921600,
2618         pbn_b0_bt_4_921600,
2619         pbn_b0_bt_8_921600,
2620
2621         pbn_b1_1_115200,
2622         pbn_b1_2_115200,
2623         pbn_b1_4_115200,
2624         pbn_b1_8_115200,
2625         pbn_b1_16_115200,
2626
2627         pbn_b1_1_921600,
2628         pbn_b1_2_921600,
2629         pbn_b1_4_921600,
2630         pbn_b1_8_921600,
2631
2632         pbn_b1_2_1250000,
2633
2634         pbn_b1_bt_1_115200,
2635         pbn_b1_bt_2_115200,
2636         pbn_b1_bt_4_115200,
2637
2638         pbn_b1_bt_2_921600,
2639
2640         pbn_b1_1_1382400,
2641         pbn_b1_2_1382400,
2642         pbn_b1_4_1382400,
2643         pbn_b1_8_1382400,
2644
2645         pbn_b2_1_115200,
2646         pbn_b2_2_115200,
2647         pbn_b2_4_115200,
2648         pbn_b2_8_115200,
2649
2650         pbn_b2_1_460800,
2651         pbn_b2_4_460800,
2652         pbn_b2_8_460800,
2653         pbn_b2_16_460800,
2654
2655         pbn_b2_1_921600,
2656         pbn_b2_4_921600,
2657         pbn_b2_8_921600,
2658
2659         pbn_b2_8_1152000,
2660
2661         pbn_b2_bt_1_115200,
2662         pbn_b2_bt_2_115200,
2663         pbn_b2_bt_4_115200,
2664
2665         pbn_b2_bt_2_921600,
2666         pbn_b2_bt_4_921600,
2667
2668         pbn_b3_2_115200,
2669         pbn_b3_4_115200,
2670         pbn_b3_8_115200,
2671
2672         pbn_b4_bt_2_921600,
2673         pbn_b4_bt_4_921600,
2674         pbn_b4_bt_8_921600,
2675
2676         /*
2677          * Board-specific versions.
2678          */
2679         pbn_panacom,
2680         pbn_panacom2,
2681         pbn_panacom4,
2682         pbn_plx_romulus,
2683         pbn_oxsemi,
2684         pbn_oxsemi_1_4000000,
2685         pbn_oxsemi_2_4000000,
2686         pbn_oxsemi_4_4000000,
2687         pbn_oxsemi_8_4000000,
2688         pbn_intel_i960,
2689         pbn_sgi_ioc3,
2690         pbn_computone_4,
2691         pbn_computone_6,
2692         pbn_computone_8,
2693         pbn_sbsxrsio,
2694         pbn_exar_XR17C152,
2695         pbn_exar_XR17C154,
2696         pbn_exar_XR17C158,
2697         pbn_exar_XR17V352,
2698         pbn_exar_XR17V354,
2699         pbn_exar_XR17V358,
2700         pbn_exar_ibm_saturn,
2701         pbn_pasemi_1682M,
2702         pbn_ni8430_2,
2703         pbn_ni8430_4,
2704         pbn_ni8430_8,
2705         pbn_ni8430_16,
2706         pbn_ADDIDATA_PCIe_1_3906250,
2707         pbn_ADDIDATA_PCIe_2_3906250,
2708         pbn_ADDIDATA_PCIe_4_3906250,
2709         pbn_ADDIDATA_PCIe_8_3906250,
2710         pbn_ce4100_1_115200,
2711         pbn_byt,
2712         pbn_omegapci,
2713         pbn_NETMOS9900_2s_115200,
2714         pbn_brcm_trumanage,
2715         pbn_fintek_4,
2716         pbn_fintek_8,
2717         pbn_fintek_12,
2718 };
2719
2720 /*
2721  * uart_offset - the space between channels
2722  * reg_shift   - describes how the UART registers are mapped
2723  *               to PCI memory by the card.
2724  * For example IER register on SBS, Inc. PMC-OctPro is located at
2725  * offset 0x10 from the UART base, while UART_IER is defined as 1
2726  * in include/linux/serial_reg.h,
2727  * see first lines of serial_in() and serial_out() in 8250.c
2728 */
2729
2730 static struct pciserial_board pci_boards[] = {
2731         [pbn_default] = {
2732                 .flags          = FL_BASE0,
2733                 .num_ports      = 1,
2734                 .base_baud      = 115200,
2735                 .uart_offset    = 8,
2736         },
2737         [pbn_b0_1_115200] = {
2738                 .flags          = FL_BASE0,
2739                 .num_ports      = 1,
2740                 .base_baud      = 115200,
2741                 .uart_offset    = 8,
2742         },
2743         [pbn_b0_2_115200] = {
2744                 .flags          = FL_BASE0,
2745                 .num_ports      = 2,
2746                 .base_baud      = 115200,
2747                 .uart_offset    = 8,
2748         },
2749         [pbn_b0_4_115200] = {
2750                 .flags          = FL_BASE0,
2751                 .num_ports      = 4,
2752                 .base_baud      = 115200,
2753                 .uart_offset    = 8,
2754         },
2755         [pbn_b0_5_115200] = {
2756                 .flags          = FL_BASE0,
2757                 .num_ports      = 5,
2758                 .base_baud      = 115200,
2759                 .uart_offset    = 8,
2760         },
2761         [pbn_b0_8_115200] = {
2762                 .flags          = FL_BASE0,
2763                 .num_ports      = 8,
2764                 .base_baud      = 115200,
2765                 .uart_offset    = 8,
2766         },
2767         [pbn_b0_1_921600] = {
2768                 .flags          = FL_BASE0,
2769                 .num_ports      = 1,
2770                 .base_baud      = 921600,
2771                 .uart_offset    = 8,
2772         },
2773         [pbn_b0_2_921600] = {
2774                 .flags          = FL_BASE0,
2775                 .num_ports      = 2,
2776                 .base_baud      = 921600,
2777                 .uart_offset    = 8,
2778         },
2779         [pbn_b0_4_921600] = {
2780                 .flags          = FL_BASE0,
2781                 .num_ports      = 4,
2782                 .base_baud      = 921600,
2783                 .uart_offset    = 8,
2784         },
2785
2786         [pbn_b0_2_1130000] = {
2787                 .flags          = FL_BASE0,
2788                 .num_ports      = 2,
2789                 .base_baud      = 1130000,
2790                 .uart_offset    = 8,
2791         },
2792
2793         [pbn_b0_4_1152000] = {
2794                 .flags          = FL_BASE0,
2795                 .num_ports      = 4,
2796                 .base_baud      = 1152000,
2797                 .uart_offset    = 8,
2798         },
2799
2800         [pbn_b0_2_1152000_200] = {
2801                 .flags          = FL_BASE0,
2802                 .num_ports      = 2,
2803                 .base_baud      = 1152000,
2804                 .uart_offset    = 0x200,
2805         },
2806
2807         [pbn_b0_4_1152000_200] = {
2808                 .flags          = FL_BASE0,
2809                 .num_ports      = 4,
2810                 .base_baud      = 1152000,
2811                 .uart_offset    = 0x200,
2812         },
2813
2814         [pbn_b0_8_1152000_200] = {
2815                 .flags          = FL_BASE0,
2816                 .num_ports      = 8,
2817                 .base_baud      = 1152000,
2818                 .uart_offset    = 0x200,
2819         },
2820
2821         [pbn_b0_2_1843200] = {
2822                 .flags          = FL_BASE0,
2823                 .num_ports      = 2,
2824                 .base_baud      = 1843200,
2825                 .uart_offset    = 8,
2826         },
2827         [pbn_b0_4_1843200] = {
2828                 .flags          = FL_BASE0,
2829                 .num_ports      = 4,
2830                 .base_baud      = 1843200,
2831                 .uart_offset    = 8,
2832         },
2833
2834         [pbn_b0_2_1843200_200] = {
2835                 .flags          = FL_BASE0,
2836                 .num_ports      = 2,
2837                 .base_baud      = 1843200,
2838                 .uart_offset    = 0x200,
2839         },
2840         [pbn_b0_4_1843200_200] = {
2841                 .flags          = FL_BASE0,
2842                 .num_ports      = 4,
2843                 .base_baud      = 1843200,
2844                 .uart_offset    = 0x200,
2845         },
2846         [pbn_b0_8_1843200_200] = {
2847                 .flags          = FL_BASE0,
2848                 .num_ports      = 8,
2849                 .base_baud      = 1843200,
2850                 .uart_offset    = 0x200,
2851         },
2852         [pbn_b0_1_4000000] = {
2853                 .flags          = FL_BASE0,
2854                 .num_ports      = 1,
2855                 .base_baud      = 4000000,
2856                 .uart_offset    = 8,
2857         },
2858
2859         [pbn_b0_bt_1_115200] = {
2860                 .flags          = FL_BASE0|FL_BASE_BARS,
2861                 .num_ports      = 1,
2862                 .base_baud      = 115200,
2863                 .uart_offset    = 8,
2864         },
2865         [pbn_b0_bt_2_115200] = {
2866                 .flags          = FL_BASE0|FL_BASE_BARS,
2867                 .num_ports      = 2,
2868                 .base_baud      = 115200,
2869                 .uart_offset    = 8,
2870         },
2871         [pbn_b0_bt_4_115200] = {
2872                 .flags          = FL_BASE0|FL_BASE_BARS,
2873                 .num_ports      = 4,
2874                 .base_baud      = 115200,
2875                 .uart_offset    = 8,
2876         },
2877         [pbn_b0_bt_8_115200] = {
2878                 .flags          = FL_BASE0|FL_BASE_BARS,
2879                 .num_ports      = 8,
2880                 .base_baud      = 115200,
2881                 .uart_offset    = 8,
2882         },
2883
2884         [pbn_b0_bt_1_460800] = {
2885                 .flags          = FL_BASE0|FL_BASE_BARS,
2886                 .num_ports      = 1,
2887                 .base_baud      = 460800,
2888                 .uart_offset    = 8,
2889         },
2890         [pbn_b0_bt_2_460800] = {
2891                 .flags          = FL_BASE0|FL_BASE_BARS,
2892                 .num_ports      = 2,
2893                 .base_baud      = 460800,
2894                 .uart_offset    = 8,
2895         },
2896         [pbn_b0_bt_4_460800] = {
2897                 .flags          = FL_BASE0|FL_BASE_BARS,
2898                 .num_ports      = 4,
2899                 .base_baud      = 460800,
2900                 .uart_offset    = 8,
2901         },
2902
2903         [pbn_b0_bt_1_921600] = {
2904                 .flags          = FL_BASE0|FL_BASE_BARS,
2905                 .num_ports      = 1,
2906                 .base_baud      = 921600,
2907                 .uart_offset    = 8,
2908         },
2909         [pbn_b0_bt_2_921600] = {
2910                 .flags          = FL_BASE0|FL_BASE_BARS,
2911                 .num_ports      = 2,
2912                 .base_baud      = 921600,
2913                 .uart_offset    = 8,
2914         },
2915         [pbn_b0_bt_4_921600] = {
2916                 .flags          = FL_BASE0|FL_BASE_BARS,
2917                 .num_ports      = 4,
2918                 .base_baud      = 921600,
2919                 .uart_offset    = 8,
2920         },
2921         [pbn_b0_bt_8_921600] = {
2922                 .flags          = FL_BASE0|FL_BASE_BARS,
2923                 .num_ports      = 8,
2924                 .base_baud      = 921600,
2925                 .uart_offset    = 8,
2926         },
2927
2928         [pbn_b1_1_115200] = {
2929                 .flags          = FL_BASE1,
2930                 .num_ports      = 1,
2931                 .base_baud      = 115200,
2932                 .uart_offset    = 8,
2933         },
2934         [pbn_b1_2_115200] = {
2935                 .flags          = FL_BASE1,
2936                 .num_ports      = 2,
2937                 .base_baud      = 115200,
2938                 .uart_offset    = 8,
2939         },
2940         [pbn_b1_4_115200] = {
2941                 .flags          = FL_BASE1,
2942                 .num_ports      = 4,
2943                 .base_baud      = 115200,
2944                 .uart_offset    = 8,
2945         },
2946         [pbn_b1_8_115200] = {
2947                 .flags          = FL_BASE1,
2948                 .num_ports      = 8,
2949                 .base_baud      = 115200,
2950                 .uart_offset    = 8,
2951         },
2952         [pbn_b1_16_115200] = {
2953                 .flags          = FL_BASE1,
2954                 .num_ports      = 16,
2955                 .base_baud      = 115200,
2956                 .uart_offset    = 8,
2957         },
2958
2959         [pbn_b1_1_921600] = {
2960                 .flags          = FL_BASE1,
2961                 .num_ports      = 1,
2962                 .base_baud      = 921600,
2963                 .uart_offset    = 8,
2964         },
2965         [pbn_b1_2_921600] = {
2966                 .flags          = FL_BASE1,
2967                 .num_ports      = 2,
2968                 .base_baud      = 921600,
2969                 .uart_offset    = 8,
2970         },
2971         [pbn_b1_4_921600] = {
2972                 .flags          = FL_BASE1,
2973                 .num_ports      = 4,
2974                 .base_baud      = 921600,
2975                 .uart_offset    = 8,
2976         },
2977         [pbn_b1_8_921600] = {
2978                 .flags          = FL_BASE1,
2979                 .num_ports      = 8,
2980                 .base_baud      = 921600,
2981                 .uart_offset    = 8,
2982         },
2983         [pbn_b1_2_1250000] = {
2984                 .flags          = FL_BASE1,
2985                 .num_ports      = 2,
2986                 .base_baud      = 1250000,
2987                 .uart_offset    = 8,
2988         },
2989
2990         [pbn_b1_bt_1_115200] = {
2991                 .flags          = FL_BASE1|FL_BASE_BARS,
2992                 .num_ports      = 1,
2993                 .base_baud      = 115200,
2994                 .uart_offset    = 8,
2995         },
2996         [pbn_b1_bt_2_115200] = {
2997                 .flags          = FL_BASE1|FL_BASE_BARS,
2998                 .num_ports      = 2,
2999                 .base_baud      = 115200,
3000                 .uart_offset    = 8,
3001         },
3002         [pbn_b1_bt_4_115200] = {
3003                 .flags          = FL_BASE1|FL_BASE_BARS,
3004                 .num_ports      = 4,
3005                 .base_baud      = 115200,
3006                 .uart_offset    = 8,
3007         },
3008
3009         [pbn_b1_bt_2_921600] = {
3010                 .flags          = FL_BASE1|FL_BASE_BARS,
3011                 .num_ports      = 2,
3012                 .base_baud      = 921600,
3013                 .uart_offset    = 8,
3014         },
3015
3016         [pbn_b1_1_1382400] = {
3017                 .flags          = FL_BASE1,
3018                 .num_ports      = 1,
3019                 .base_baud      = 1382400,
3020                 .uart_offset    = 8,
3021         },
3022         [pbn_b1_2_1382400] = {
3023                 .flags          = FL_BASE1,
3024                 .num_ports      = 2,
3025                 .base_baud      = 1382400,
3026                 .uart_offset    = 8,
3027         },
3028         [pbn_b1_4_1382400] = {
3029                 .flags          = FL_BASE1,
3030                 .num_ports      = 4,
3031                 .base_baud      = 1382400,
3032                 .uart_offset    = 8,
3033         },
3034         [pbn_b1_8_1382400] = {
3035                 .flags          = FL_BASE1,
3036                 .num_ports      = 8,
3037                 .base_baud      = 1382400,
3038                 .uart_offset    = 8,
3039         },
3040
3041         [pbn_b2_1_115200] = {
3042                 .flags          = FL_BASE2,
3043                 .num_ports      = 1,
3044                 .base_baud      = 115200,
3045                 .uart_offset    = 8,
3046         },
3047         [pbn_b2_2_115200] = {
3048                 .flags          = FL_BASE2,
3049                 .num_ports      = 2,
3050                 .base_baud      = 115200,
3051                 .uart_offset    = 8,
3052         },
3053         [pbn_b2_4_115200] = {
3054                 .flags          = FL_BASE2,
3055                 .num_ports      = 4,
3056                 .base_baud      = 115200,
3057                 .uart_offset    = 8,
3058         },
3059         [pbn_b2_8_115200] = {
3060                 .flags          = FL_BASE2,
3061                 .num_ports      = 8,
3062                 .base_baud      = 115200,
3063                 .uart_offset    = 8,
3064         },
3065
3066         [pbn_b2_1_460800] = {
3067                 .flags          = FL_BASE2,
3068                 .num_ports      = 1,
3069                 .base_baud      = 460800,
3070                 .uart_offset    = 8,
3071         },
3072         [pbn_b2_4_460800] = {
3073                 .flags          = FL_BASE2,
3074                 .num_ports      = 4,
3075                 .base_baud      = 460800,
3076                 .uart_offset    = 8,
3077         },
3078         [pbn_b2_8_460800] = {
3079                 .flags          = FL_BASE2,
3080                 .num_ports      = 8,
3081                 .base_baud      = 460800,
3082                 .uart_offset    = 8,
3083         },
3084         [pbn_b2_16_460800] = {
3085                 .flags          = FL_BASE2,
3086                 .num_ports      = 16,
3087                 .base_baud      = 460800,
3088                 .uart_offset    = 8,
3089          },
3090
3091         [pbn_b2_1_921600] = {
3092                 .flags          = FL_BASE2,
3093                 .num_ports      = 1,
3094                 .base_baud      = 921600,
3095                 .uart_offset    = 8,
3096         },
3097         [pbn_b2_4_921600] = {
3098                 .flags          = FL_BASE2,
3099                 .num_ports      = 4,
3100                 .base_baud      = 921600,
3101                 .uart_offset    = 8,
3102         },
3103         [pbn_b2_8_921600] = {
3104                 .flags          = FL_BASE2,
3105                 .num_ports      = 8,
3106                 .base_baud      = 921600,
3107                 .uart_offset    = 8,
3108         },
3109
3110         [pbn_b2_8_1152000] = {
3111                 .flags          = FL_BASE2,
3112                 .num_ports      = 8,
3113                 .base_baud      = 1152000,
3114                 .uart_offset    = 8,
3115         },
3116
3117         [pbn_b2_bt_1_115200] = {
3118                 .flags          = FL_BASE2|FL_BASE_BARS,
3119                 .num_ports      = 1,
3120                 .base_baud      = 115200,
3121                 .uart_offset    = 8,
3122         },
3123         [pbn_b2_bt_2_115200] = {
3124                 .flags          = FL_BASE2|FL_BASE_BARS,
3125                 .num_ports      = 2,
3126                 .base_baud      = 115200,
3127                 .uart_offset    = 8,
3128         },
3129         [pbn_b2_bt_4_115200] = {
3130                 .flags          = FL_BASE2|FL_BASE_BARS,
3131                 .num_ports      = 4,
3132                 .base_baud      = 115200,
3133                 .uart_offset    = 8,
3134         },
3135
3136         [pbn_b2_bt_2_921600] = {
3137                 .flags          = FL_BASE2|FL_BASE_BARS,
3138                 .num_ports      = 2,
3139                 .base_baud      = 921600,
3140                 .uart_offset    = 8,
3141         },
3142         [pbn_b2_bt_4_921600] = {
3143                 .flags          = FL_BASE2|FL_BASE_BARS,
3144                 .num_ports      = 4,
3145                 .base_baud      = 921600,
3146                 .uart_offset    = 8,
3147         },
3148
3149         [pbn_b3_2_115200] = {
3150                 .flags          = FL_BASE3,
3151                 .num_ports      = 2,
3152                 .base_baud      = 115200,
3153                 .uart_offset    = 8,
3154         },
3155         [pbn_b3_4_115200] = {
3156                 .flags          = FL_BASE3,
3157                 .num_ports      = 4,
3158                 .base_baud      = 115200,
3159                 .uart_offset    = 8,
3160         },
3161         [pbn_b3_8_115200] = {
3162                 .flags          = FL_BASE3,
3163                 .num_ports      = 8,
3164                 .base_baud      = 115200,
3165                 .uart_offset    = 8,
3166         },
3167
3168         [pbn_b4_bt_2_921600] = {
3169                 .flags          = FL_BASE4,
3170                 .num_ports      = 2,
3171                 .base_baud      = 921600,
3172                 .uart_offset    = 8,
3173         },
3174         [pbn_b4_bt_4_921600] = {
3175                 .flags          = FL_BASE4,
3176                 .num_ports      = 4,
3177                 .base_baud      = 921600,
3178                 .uart_offset    = 8,
3179         },
3180         [pbn_b4_bt_8_921600] = {
3181                 .flags          = FL_BASE4,
3182                 .num_ports      = 8,
3183                 .base_baud      = 921600,
3184                 .uart_offset    = 8,
3185         },
3186
3187         /*
3188          * Entries following this are board-specific.
3189          */
3190
3191         /*
3192          * Panacom - IOMEM
3193          */
3194         [pbn_panacom] = {
3195                 .flags          = FL_BASE2,
3196                 .num_ports      = 2,
3197                 .base_baud      = 921600,
3198                 .uart_offset    = 0x400,
3199                 .reg_shift      = 7,
3200         },
3201         [pbn_panacom2] = {
3202                 .flags          = FL_BASE2|FL_BASE_BARS,
3203                 .num_ports      = 2,
3204                 .base_baud      = 921600,
3205                 .uart_offset    = 0x400,
3206                 .reg_shift      = 7,
3207         },
3208         [pbn_panacom4] = {
3209                 .flags          = FL_BASE2|FL_BASE_BARS,
3210                 .num_ports      = 4,
3211                 .base_baud      = 921600,
3212                 .uart_offset    = 0x400,
3213                 .reg_shift      = 7,
3214         },
3215
3216         /* I think this entry is broken - the first_offset looks wrong --rmk */
3217         [pbn_plx_romulus] = {
3218                 .flags          = FL_BASE2,
3219                 .num_ports      = 4,
3220                 .base_baud      = 921600,
3221                 .uart_offset    = 8 << 2,
3222                 .reg_shift      = 2,
3223                 .first_offset   = 0x03,
3224         },
3225
3226         /*
3227          * This board uses the size of PCI Base region 0 to
3228          * signal now many ports are available
3229          */
3230         [pbn_oxsemi] = {
3231                 .flags          = FL_BASE0|FL_REGION_SZ_CAP,
3232                 .num_ports      = 32,
3233                 .base_baud      = 115200,
3234                 .uart_offset    = 8,
3235         },
3236         [pbn_oxsemi_1_4000000] = {
3237                 .flags          = FL_BASE0,
3238                 .num_ports      = 1,
3239                 .base_baud      = 4000000,
3240                 .uart_offset    = 0x200,
3241                 .first_offset   = 0x1000,
3242         },
3243         [pbn_oxsemi_2_4000000] = {
3244                 .flags          = FL_BASE0,
3245                 .num_ports      = 2,
3246                 .base_baud      = 4000000,
3247                 .uart_offset    = 0x200,
3248                 .first_offset   = 0x1000,
3249         },
3250         [pbn_oxsemi_4_4000000] = {
3251                 .flags          = FL_BASE0,
3252                 .num_ports      = 4,
3253                 .base_baud      = 4000000,
3254                 .uart_offset    = 0x200,
3255                 .first_offset   = 0x1000,
3256         },
3257         [pbn_oxsemi_8_4000000] = {
3258                 .flags          = FL_BASE0,
3259                 .num_ports      = 8,
3260                 .base_baud      = 4000000,
3261                 .uart_offset    = 0x200,
3262                 .first_offset   = 0x1000,
3263         },
3264
3265
3266         /*
3267          * EKF addition for i960 Boards form EKF with serial port.
3268          * Max 256 ports.
3269          */
3270         [pbn_intel_i960] = {
3271                 .flags          = FL_BASE0,
3272                 .num_ports      = 32,
3273                 .base_baud      = 921600,
3274                 .uart_offset    = 8 << 2,
3275                 .reg_shift      = 2,
3276                 .first_offset   = 0x10000,
3277         },
3278         [pbn_sgi_ioc3] = {
3279                 .flags          = FL_BASE0|FL_NOIRQ,
3280                 .num_ports      = 1,
3281                 .base_baud      = 458333,
3282                 .uart_offset    = 8,
3283                 .reg_shift      = 0,
3284                 .first_offset   = 0x20178,
3285         },
3286
3287         /*
3288          * Computone - uses IOMEM.
3289          */
3290         [pbn_computone_4] = {
3291                 .flags          = FL_BASE0,
3292                 .num_ports      = 4,
3293                 .base_baud      = 921600,
3294                 .uart_offset    = 0x40,
3295                 .reg_shift      = 2,
3296                 .first_offset   = 0x200,
3297         },
3298         [pbn_computone_6] = {
3299                 .flags          = FL_BASE0,
3300                 .num_ports      = 6,
3301                 .base_baud      = 921600,
3302                 .uart_offset    = 0x40,
3303                 .reg_shift      = 2,
3304                 .first_offset   = 0x200,
3305         },
3306         [pbn_computone_8] = {
3307                 .flags          = FL_BASE0,
3308                 .num_ports      = 8,
3309                 .base_baud      = 921600,
3310                 .uart_offset    = 0x40,
3311                 .reg_shift      = 2,
3312                 .first_offset   = 0x200,
3313         },
3314         [pbn_sbsxrsio] = {
3315                 .flags          = FL_BASE0,
3316                 .num_ports      = 8,
3317                 .base_baud      = 460800,
3318                 .uart_offset    = 256,
3319                 .reg_shift      = 4,
3320         },
3321         /*
3322          * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3323          *  Only basic 16550A support.
3324          *  XR17C15[24] are not tested, but they should work.
3325          */
3326         [pbn_exar_XR17C152] = {
3327                 .flags          = FL_BASE0,
3328                 .num_ports      = 2,
3329                 .base_baud      = 921600,
3330                 .uart_offset    = 0x200,
3331         },
3332         [pbn_exar_XR17C154] = {
3333                 .flags          = FL_BASE0,
3334                 .num_ports      = 4,
3335                 .base_baud      = 921600,
3336                 .uart_offset    = 0x200,
3337         },
3338         [pbn_exar_XR17C158] = {
3339                 .flags          = FL_BASE0,
3340                 .num_ports      = 8,
3341                 .base_baud      = 921600,
3342                 .uart_offset    = 0x200,
3343         },
3344         [pbn_exar_XR17V352] = {
3345                 .flags          = FL_BASE0,
3346                 .num_ports      = 2,
3347                 .base_baud      = 7812500,
3348                 .uart_offset    = 0x400,
3349                 .reg_shift      = 0,
3350                 .first_offset   = 0,
3351         },
3352         [pbn_exar_XR17V354] = {
3353                 .flags          = FL_BASE0,
3354                 .num_ports      = 4,
3355                 .base_baud      = 7812500,
3356                 .uart_offset    = 0x400,
3357                 .reg_shift      = 0,
3358                 .first_offset   = 0,
3359         },
3360         [pbn_exar_XR17V358] = {
3361                 .flags          = FL_BASE0,
3362                 .num_ports      = 8,
3363                 .base_baud      = 7812500,
3364                 .uart_offset    = 0x400,
3365                 .reg_shift      = 0,
3366                 .first_offset   = 0,
3367         },
3368         [pbn_exar_ibm_saturn] = {
3369                 .flags          = FL_BASE0,
3370                 .num_ports      = 1,
3371                 .base_baud      = 921600,
3372                 .uart_offset    = 0x200,
3373         },
3374
3375         /*
3376          * PA Semi PWRficient PA6T-1682M on-chip UART
3377          */
3378         [pbn_pasemi_1682M] = {
3379                 .flags          = FL_BASE0,
3380                 .num_ports      = 1,
3381                 .base_baud      = 8333333,
3382         },
3383         /*
3384          * National Instruments 843x
3385          */
3386         [pbn_ni8430_16] = {
3387                 .flags          = FL_BASE0,
3388                 .num_ports      = 16,
3389                 .base_baud      = 3686400,
3390                 .uart_offset    = 0x10,
3391                 .first_offset   = 0x800,
3392         },
3393         [pbn_ni8430_8] = {
3394                 .flags          = FL_BASE0,
3395                 .num_ports      = 8,
3396                 .base_baud      = 3686400,
3397                 .uart_offset    = 0x10,
3398                 .first_offset   = 0x800,
3399         },
3400         [pbn_ni8430_4] = {
3401                 .flags          = FL_BASE0,
3402                 .num_ports      = 4,
3403                 .base_baud      = 3686400,
3404                 .uart_offset    = 0x10,
3405                 .first_offset   = 0x800,
3406         },
3407         [pbn_ni8430_2] = {
3408                 .flags          = FL_BASE0,
3409                 .num_ports      = 2,
3410                 .base_baud      = 3686400,
3411                 .uart_offset    = 0x10,
3412                 .first_offset   = 0x800,
3413         },
3414         /*
3415          * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
3416          */
3417         [pbn_ADDIDATA_PCIe_1_3906250] = {
3418                 .flags          = FL_BASE0,
3419                 .num_ports      = 1,
3420                 .base_baud      = 3906250,
3421                 .uart_offset    = 0x200,
3422                 .first_offset   = 0x1000,
3423         },
3424         [pbn_ADDIDATA_PCIe_2_3906250] = {
3425                 .flags          = FL_BASE0,
3426                 .num_ports      = 2,
3427                 .base_baud      = 3906250,
3428                 .uart_offset    = 0x200,
3429                 .first_offset   = 0x1000,
3430         },
3431         [pbn_ADDIDATA_PCIe_4_3906250] = {
3432                 .flags          = FL_BASE0,
3433                 .num_ports      = 4,
3434                 .base_baud      = 3906250,
3435                 .uart_offset    = 0x200,
3436                 .first_offset   = 0x1000,
3437         },
3438         [pbn_ADDIDATA_PCIe_8_3906250] = {
3439                 .flags          = FL_BASE0,
3440                 .num_ports      = 8,
3441                 .base_baud      = 3906250,
3442                 .uart_offset    = 0x200,
3443                 .first_offset   = 0x1000,
3444         },
3445         [pbn_ce4100_1_115200] = {
3446                 .flags          = FL_BASE_BARS,
3447                 .num_ports      = 2,
3448                 .base_baud      = 921600,
3449                 .reg_shift      = 2,
3450         },
3451         [pbn_byt] = {
3452                 .flags          = FL_BASE0,
3453                 .num_ports      = 1,
3454                 .base_baud      = 2764800,
3455                 .uart_offset    = 0x80,
3456                 .reg_shift      = 2,
3457         },
3458         [pbn_omegapci] = {
3459                 .flags          = FL_BASE0,
3460                 .num_ports      = 8,
3461                 .base_baud      = 115200,
3462                 .uart_offset    = 0x200,
3463         },
3464         [pbn_NETMOS9900_2s_115200] = {
3465                 .flags          = FL_BASE0,
3466                 .num_ports      = 2,
3467                 .base_baud      = 115200,
3468         },
3469         [pbn_brcm_trumanage] = {
3470                 .flags          = FL_BASE0,
3471                 .num_ports      = 1,
3472                 .reg_shift      = 2,
3473                 .base_baud      = 115200,
3474         },
3475         [pbn_fintek_4] = {
3476                 .num_ports      = 4,
3477                 .uart_offset    = 8,
3478                 .base_baud      = 115200,
3479                 .first_offset   = 0x40,
3480         },
3481         [pbn_fintek_8] = {
3482                 .num_ports      = 8,
3483                 .uart_offset    = 8,
3484                 .base_baud      = 115200,
3485                 .first_offset   = 0x40,
3486         },
3487         [pbn_fintek_12] = {
3488                 .num_ports      = 12,
3489                 .uart_offset    = 8,
3490                 .base_baud      = 115200,
3491                 .first_offset   = 0x40,
3492         },
3493 };
3494
3495 static const struct pci_device_id blacklist[] = {
3496         /* softmodems */
3497         { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
3498         { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
3499         { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
3500
3501         /* multi-io cards handled by parport_serial */
3502         { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */
3503 };
3504
3505 /*
3506  * Given a complete unknown PCI device, try to use some heuristics to
3507  * guess what the configuration might be, based on the pitiful PCI
3508  * serial specs.  Returns 0 on success, 1 on failure.
3509  */
3510 static int
3511 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
3512 {
3513         const struct pci_device_id *bldev;
3514         int num_iomem, num_port, first_port = -1, i;
3515
3516         /*
3517          * If it is not a communications device or the programming
3518          * interface is greater than 6, give up.
3519          *
3520          * (Should we try to make guesses for multiport serial devices
3521          * later?)
3522          */
3523         if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
3524              ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
3525             (dev->class & 0xff) > 6)
3526                 return -ENODEV;
3527
3528         /*
3529          * Do not access blacklisted devices that are known not to
3530          * feature serial ports or are handled by other modules.
3531          */
3532         for (bldev = blacklist;
3533              bldev < blacklist + ARRAY_SIZE(blacklist);
3534              bldev++) {
3535                 if (dev->vendor == bldev->vendor &&
3536                     dev->device == bldev->device)
3537                         return -ENODEV;
3538         }
3539
3540         num_iomem = num_port = 0;
3541         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3542                 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
3543                         num_port++;
3544                         if (first_port == -1)
3545                                 first_port = i;
3546                 }
3547                 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
3548                         num_iomem++;
3549         }
3550
3551         /*
3552          * If there is 1 or 0 iomem regions, and exactly one port,
3553          * use it.  We guess the number of ports based on the IO
3554          * region size.
3555          */
3556         if (num_iomem <= 1 && num_port == 1) {
3557                 board->flags = first_port;
3558                 board->num_ports = pci_resource_len(dev, first_port) / 8;
3559                 return 0;
3560         }
3561
3562         /*
3563          * Now guess if we've got a board which indexes by BARs.
3564          * Each IO BAR should be 8 bytes, and they should follow
3565          * consecutively.
3566          */
3567         first_port = -1;
3568         num_port = 0;
3569         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3570                 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
3571                     pci_resource_len(dev, i) == 8 &&
3572                     (first_port == -1 || (first_port + num_port) == i)) {
3573                         num_port++;
3574                         if (first_port == -1)
3575                                 first_port = i;
3576                 }
3577         }
3578
3579         if (num_port > 1) {
3580                 board->flags = first_port | FL_BASE_BARS;
3581                 board->num_ports = num_port;
3582                 return 0;
3583         }
3584
3585         return -ENODEV;
3586 }
3587
3588 static inline int
3589 serial_pci_matches(const struct pciserial_board *board,
3590                    const struct pciserial_board *guessed)
3591 {
3592         return
3593             board->num_ports == guessed->num_ports &&
3594             board->base_baud == guessed->base_baud &&
3595             board->uart_offset == guessed->uart_offset &&
3596             board->reg_shift == guessed->reg_shift &&
3597             board->first_offset == guessed->first_offset;
3598 }
3599
3600 struct serial_private *
3601 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
3602 {
3603         struct uart_8250_port uart;
3604         struct serial_private *priv;
3605         struct pci_serial_quirk *quirk;
3606         int rc, nr_ports, i;
3607
3608         nr_ports = board->num_ports;
3609
3610         /*
3611          * Find an init and setup quirks.
3612          */
3613         quirk = find_quirk(dev);
3614
3615         /*
3616          * Run the new-style initialization function.
3617          * The initialization function returns:
3618          *  <0  - error
3619          *   0  - use board->num_ports
3620          *  >0  - number of ports
3621          */
3622         if (quirk->init) {
3623                 rc = quirk->init(dev);
3624                 if (rc < 0) {
3625                         priv = ERR_PTR(rc);
3626                         goto err_out;
3627                 }
3628                 if (rc)
3629                         nr_ports = rc;
3630         }
3631
3632         priv = kzalloc(sizeof(struct serial_private) +
3633                        sizeof(unsigned int) * nr_ports,
3634                        GFP_KERNEL);
3635         if (!priv) {
3636                 priv = ERR_PTR(-ENOMEM);
3637                 goto err_deinit;
3638         }
3639
3640         priv->dev = dev;
3641         priv->quirk = quirk;
3642
3643         memset(&uart, 0, sizeof(uart));
3644         uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
3645         uart.port.uartclk = board->base_baud * 16;
3646         uart.port.irq = get_pci_irq(dev, board);
3647         uart.port.dev = &dev->dev;
3648
3649         for (i = 0; i < nr_ports; i++) {
3650                 if (quirk->setup(priv, board, &uart, i))
3651                         break;
3652
3653                 dev_dbg(&dev->dev, "Setup PCI port: port %lx, irq %d, type %d\n",
3654                         uart.port.iobase, uart.port.irq, uart.port.iotype);
3655
3656                 priv->line[i] = serial8250_register_8250_port(&uart);
3657                 if (priv->line[i] < 0) {
3658                         dev_err(&dev->dev,
3659                                 "Couldn't register serial port %lx, irq %d, type %d, error %d\n",
3660                                 uart.port.iobase, uart.port.irq,
3661                                 uart.port.iotype, priv->line[i]);
3662                         break;
3663                 }
3664         }
3665         priv->nr = i;
3666         return priv;
3667
3668 err_deinit:
3669         if (quirk->exit)
3670                 quirk->exit(dev);
3671 err_out:
3672         return priv;
3673 }
3674 EXPORT_SYMBOL_GPL(pciserial_init_ports);
3675
3676 void pciserial_remove_ports(struct serial_private *priv)
3677 {
3678         struct pci_serial_quirk *quirk;
3679         int i;
3680
3681         for (i = 0; i < priv->nr; i++)
3682                 serial8250_unregister_port(priv->line[i]);
3683
3684         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3685                 if (priv->remapped_bar[i])
3686                         iounmap(priv->remapped_bar[i]);
3687                 priv->remapped_bar[i] = NULL;
3688         }
3689
3690         /*
3691          * Find the exit quirks.
3692          */
3693         quirk = find_quirk(priv->dev);
3694         if (quirk->exit)
3695                 quirk->exit(priv->dev);
3696
3697         kfree(priv);
3698 }
3699 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
3700
3701 void pciserial_suspend_ports(struct serial_private *priv)
3702 {
3703         int i;
3704
3705         for (i = 0; i < priv->nr; i++)
3706                 if (priv->line[i] >= 0)
3707                         serial8250_suspend_port(priv->line[i]);
3708
3709         /*
3710          * Ensure that every init quirk is properly torn down
3711          */
3712         if (priv->quirk->exit)
3713                 priv->quirk->exit(priv->dev);
3714 }
3715 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
3716
3717 void pciserial_resume_ports(struct serial_private *priv)
3718 {
3719         int i;
3720
3721         /*
3722          * Ensure that the board is correctly configured.
3723          */
3724         if (priv->quirk->init)
3725                 priv->quirk->init(priv->dev);
3726
3727         for (i = 0; i < priv->nr; i++)
3728                 if (priv->line[i] >= 0)
3729                         serial8250_resume_port(priv->line[i]);
3730 }
3731 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
3732
3733 /*
3734  * Probe one serial board.  Unfortunately, there is no rhyme nor reason
3735  * to the arrangement of serial ports on a PCI card.
3736  */
3737 static int
3738 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
3739 {
3740         struct pci_serial_quirk *quirk;
3741         struct serial_private *priv;
3742         const struct pciserial_board *board;
3743         struct pciserial_board tmp;
3744         int rc;
3745
3746         quirk = find_quirk(dev);
3747         if (quirk->probe) {
3748                 rc = quirk->probe(dev);
3749                 if (rc)
3750                         return rc;
3751         }
3752
3753         if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
3754                 dev_err(&dev->dev, "invalid driver_data: %ld\n",
3755                         ent->driver_data);
3756                 return -EINVAL;
3757         }
3758
3759         board = &pci_boards[ent->driver_data];
3760
3761         rc = pci_enable_device(dev);
3762         pci_save_state(dev);
3763         if (rc)
3764                 return rc;
3765
3766         if (ent->driver_data == pbn_default) {
3767                 /*
3768                  * Use a copy of the pci_board entry for this;
3769                  * avoid changing entries in the table.
3770                  */
3771                 memcpy(&tmp, board, sizeof(struct pciserial_board));
3772                 board = &tmp;
3773
3774                 /*
3775                  * We matched one of our class entries.  Try to
3776                  * determine the parameters of this board.
3777                  */
3778                 rc = serial_pci_guess_board(dev, &tmp);
3779                 if (rc)
3780                         goto disable;
3781         } else {
3782                 /*
3783                  * We matched an explicit entry.  If we are able to
3784                  * detect this boards settings with our heuristic,
3785                  * then we no longer need this entry.
3786                  */
3787                 memcpy(&tmp, &pci_boards[pbn_default],
3788                        sizeof(struct pciserial_board));
3789                 rc = serial_pci_guess_board(dev, &tmp);
3790                 if (rc == 0 && serial_pci_matches(board, &tmp))
3791                         moan_device("Redundant entry in serial pci_table.",
3792                                     dev);
3793         }
3794
3795         priv = pciserial_init_ports(dev, board);
3796         if (!IS_ERR(priv)) {
3797                 pci_set_drvdata(dev, priv);
3798                 return 0;
3799         }
3800
3801         rc = PTR_ERR(priv);
3802
3803  disable:
3804         pci_disable_device(dev);
3805         return rc;
3806 }
3807
3808 static void pciserial_remove_one(struct pci_dev *dev)
3809 {
3810         struct serial_private *priv = pci_get_drvdata(dev);
3811
3812         pciserial_remove_ports(priv);
3813
3814         pci_disable_device(dev);
3815 }
3816
3817 #ifdef CONFIG_PM
3818 static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
3819 {
3820         struct serial_private *priv = pci_get_drvdata(dev);
3821
3822         if (priv)
3823                 pciserial_suspend_ports(priv);
3824
3825         pci_save_state(dev);
3826         pci_set_power_state(dev, pci_choose_state(dev, state));
3827         return 0;
3828 }
3829
3830 static int pciserial_resume_one(struct pci_dev *dev)
3831 {
3832         int err;
3833         struct serial_private *priv = pci_get_drvdata(dev);
3834
3835         pci_set_power_state(dev, PCI_D0);
3836         pci_restore_state(dev);
3837
3838         if (priv) {
3839                 /*
3840                  * The device may have been disabled.  Re-enable it.
3841                  */
3842                 err = pci_enable_device(dev);
3843                 /* FIXME: We cannot simply error out here */
3844                 if (err)
3845                         dev_err(&dev->dev, "Unable to re-enable ports, trying to continue.\n");
3846                 pciserial_resume_ports(priv);
3847         }
3848         return 0;
3849 }
3850 #endif
3851
3852 static struct pci_device_id serial_pci_tbl[] = {
3853         /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
3854         {       PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
3855                 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
3856                 pbn_b2_8_921600 },
3857         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3858                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3859                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
3860                 pbn_b1_8_1382400 },
3861         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3862                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3863                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
3864                 pbn_b1_4_1382400 },
3865         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3866                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3867                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
3868                 pbn_b1_2_1382400 },
3869         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3870                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3871                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
3872                 pbn_b1_8_1382400 },
3873         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3874                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3875                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
3876                 pbn_b1_4_1382400 },
3877         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3878                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3879                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
3880                 pbn_b1_2_1382400 },
3881         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3882                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3883                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
3884                 pbn_b1_8_921600 },
3885         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3886                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3887                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
3888                 pbn_b1_8_921600 },
3889         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3890                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3891                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
3892                 pbn_b1_4_921600 },
3893         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3894                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3895                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
3896                 pbn_b1_4_921600 },
3897         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3898                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3899                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
3900                 pbn_b1_2_921600 },
3901         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3902                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3903                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
3904                 pbn_b1_8_921600 },
3905         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3906                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3907                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
3908                 pbn_b1_8_921600 },
3909         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3910                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3911                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
3912                 pbn_b1_4_921600 },
3913         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3914                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3915                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
3916                 pbn_b1_2_1250000 },
3917         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3918                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3919                 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
3920                 pbn_b0_2_1843200 },
3921         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3922                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3923                 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
3924                 pbn_b0_4_1843200 },
3925         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3926                 PCI_VENDOR_ID_AFAVLAB,
3927                 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
3928                 pbn_b0_4_1152000 },
3929         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3930                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3931                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
3932                 pbn_b0_2_1843200_200 },
3933         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3934                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3935                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
3936                 pbn_b0_4_1843200_200 },
3937         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3938                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3939                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
3940                 pbn_b0_8_1843200_200 },
3941         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3942                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3943                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
3944                 pbn_b0_2_1843200_200 },
3945         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3946                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3947                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
3948                 pbn_b0_4_1843200_200 },
3949         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3950                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3951                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
3952                 pbn_b0_8_1843200_200 },
3953         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3954                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3955                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
3956                 pbn_b0_2_1843200_200 },
3957         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3958                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3959                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
3960                 pbn_b0_4_1843200_200 },
3961         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3962                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3963                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
3964                 pbn_b0_8_1843200_200 },
3965         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3966                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3967                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
3968                 pbn_b0_2_1843200_200 },
3969         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3970                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3971                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
3972                 pbn_b0_4_1843200_200 },
3973         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3974                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3975                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
3976                 pbn_b0_8_1843200_200 },
3977         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3978                 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT,
3979                 0, 0, pbn_exar_ibm_saturn },
3980
3981         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
3982                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3983                 pbn_b2_bt_1_115200 },
3984         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
3985                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3986                 pbn_b2_bt_2_115200 },
3987         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
3988                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3989                 pbn_b2_bt_4_115200 },
3990         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
3991                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3992                 pbn_b2_bt_2_115200 },
3993         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
3994                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3995                 pbn_b2_bt_4_115200 },
3996         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
3997                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3998                 pbn_b2_8_115200 },
3999         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
4000                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4001                 pbn_b2_8_460800 },
4002         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
4003                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4004                 pbn_b2_8_115200 },
4005
4006         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
4007                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4008                 pbn_b2_bt_2_115200 },
4009         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
4010                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4011                 pbn_b2_bt_2_921600 },
4012         /*
4013          * VScom SPCOM800, from sl@s.pl
4014          */
4015         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
4016                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4017                 pbn_b2_8_921600 },
4018         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
4019                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4020                 pbn_b2_4_921600 },
4021         /* Unknown card - subdevice 0x1584 */
4022         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4023                 PCI_VENDOR_ID_PLX,
4024                 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
4025                 pbn_b2_4_115200 },
4026         /* Unknown card - subdevice 0x1588 */
4027         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4028                 PCI_VENDOR_ID_PLX,
4029                 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0,
4030                 pbn_b2_8_115200 },
4031         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4032                 PCI_SUBVENDOR_ID_KEYSPAN,
4033                 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
4034                 pbn_panacom },
4035         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
4036                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4037                 pbn_panacom4 },
4038         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
4039                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4040                 pbn_panacom2 },
4041         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4042                 PCI_VENDOR_ID_ESDGMBH,
4043                 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
4044                 pbn_b2_4_115200 },
4045         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4046                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4047                 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
4048                 pbn_b2_4_460800 },
4049         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4050                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4051                 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
4052                 pbn_b2_8_460800 },
4053         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4054                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4055                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
4056                 pbn_b2_16_460800 },
4057         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4058                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4059                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
4060                 pbn_b2_16_460800 },
4061         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4062                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4063                 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
4064                 pbn_b2_4_460800 },
4065         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4066                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4067                 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
4068                 pbn_b2_8_460800 },
4069         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4070                 PCI_SUBVENDOR_ID_EXSYS,
4071                 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
4072                 pbn_b2_4_115200 },
4073         /*
4074          * Megawolf Romulus PCI Serial Card, from Mike Hudson
4075          * (Exoray@isys.ca)
4076          */
4077         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
4078                 0x10b5, 0x106a, 0, 0,
4079                 pbn_plx_romulus },
4080         /*
4081          * Quatech cards. These actually have configurable clocks but for
4082          * now we just use the default.
4083          *
4084          * 100 series are RS232, 200 series RS422,
4085          */
4086         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
4087                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4088                 pbn_b1_4_115200 },
4089         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
4090                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4091                 pbn_b1_2_115200 },
4092         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E,
4093                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4094                 pbn_b2_2_115200 },
4095         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200,
4096                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4097                 pbn_b1_2_115200 },
4098         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E,
4099                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4100                 pbn_b2_2_115200 },
4101         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200,
4102                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4103                 pbn_b1_4_115200 },
4104         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
4105                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4106                 pbn_b1_8_115200 },
4107         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
4108                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4109                 pbn_b1_8_115200 },
4110         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100,
4111                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4112                 pbn_b1_4_115200 },
4113         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100,
4114                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4115                 pbn_b1_2_115200 },
4116         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200,
4117                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4118                 pbn_b1_4_115200 },
4119         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200,
4120                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4121                 pbn_b1_2_115200 },
4122         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100,
4123                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4124                 pbn_b2_4_115200 },
4125         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100,
4126                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4127                 pbn_b2_2_115200 },
4128         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100,
4129                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4130                 pbn_b2_1_115200 },
4131         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200,
4132                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4133                 pbn_b2_4_115200 },
4134         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200,
4135                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4136                 pbn_b2_2_115200 },
4137         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200,
4138                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4139                 pbn_b2_1_115200 },
4140         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100,
4141                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4142                 pbn_b0_8_115200 },
4143
4144         {       PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
4145                 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
4146                 0, 0,
4147                 pbn_b0_4_921600 },
4148         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4149                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
4150                 0, 0,
4151                 pbn_b0_4_1152000 },
4152         {       PCI_VENDOR_ID_OXSEMI, 0x9505,
4153                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4154                 pbn_b0_bt_2_921600 },
4155
4156                 /*
4157                  * The below card is a little controversial since it is the
4158                  * subject of a PCI vendor/device ID clash.  (See
4159                  * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
4160                  * For now just used the hex ID 0x950a.
4161                  */
4162         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
4163                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00,
4164                 0, 0, pbn_b0_2_115200 },
4165         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
4166                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30,
4167                 0, 0, pbn_b0_2_115200 },
4168         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
4169                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4170                 pbn_b0_2_1130000 },
4171         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
4172                 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
4173                 pbn_b0_1_921600 },
4174         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4175                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4176                 pbn_b0_4_115200 },
4177         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
4178                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4179                 pbn_b0_bt_2_921600 },
4180         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
4181                 PCI_ANY_ID , PCI_ANY_ID, 0, 0,
4182                 pbn_b2_8_1152000 },
4183
4184         /*
4185          * Oxford Semiconductor Inc. Tornado PCI express device range.
4186          */
4187         {       PCI_VENDOR_ID_OXSEMI, 0xc101,    /* OXPCIe952 1 Legacy UART */
4188                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4189                 pbn_b0_1_4000000 },
4190         {       PCI_VENDOR_ID_OXSEMI, 0xc105,    /* OXPCIe952 1 Legacy UART */
4191                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4192                 pbn_b0_1_4000000 },
4193         {       PCI_VENDOR_ID_OXSEMI, 0xc11b,    /* OXPCIe952 1 Native UART */
4194                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4195                 pbn_oxsemi_1_4000000 },
4196         {       PCI_VENDOR_ID_OXSEMI, 0xc11f,    /* OXPCIe952 1 Native UART */
4197                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4198                 pbn_oxsemi_1_4000000 },
4199         {       PCI_VENDOR_ID_OXSEMI, 0xc120,    /* OXPCIe952 1 Legacy UART */
4200                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4201                 pbn_b0_1_4000000 },
4202         {       PCI_VENDOR_ID_OXSEMI, 0xc124,    /* OXPCIe952 1 Legacy UART */
4203                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4204                 pbn_b0_1_4000000 },
4205         {       PCI_VENDOR_ID_OXSEMI, 0xc138,    /* OXPCIe952 1 Native UART */
4206                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4207                 pbn_oxsemi_1_4000000 },
4208         {       PCI_VENDOR_ID_OXSEMI, 0xc13d,    /* OXPCIe952 1 Native UART */
4209                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4210                 pbn_oxsemi_1_4000000 },
4211         {       PCI_VENDOR_ID_OXSEMI, 0xc140,    /* OXPCIe952 1 Legacy UART */
4212                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4213                 pbn_b0_1_4000000 },
4214         {       PCI_VENDOR_ID_OXSEMI, 0xc141,    /* OXPCIe952 1 Legacy UART */
4215                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4216                 pbn_b0_1_4000000 },
4217         {       PCI_VENDOR_ID_OXSEMI, 0xc144,    /* OXPCIe952 1 Legacy UART */
4218                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4219                 pbn_b0_1_4000000 },
4220         {       PCI_VENDOR_ID_OXSEMI, 0xc145,    /* OXPCIe952 1 Legacy UART */
4221                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4222                 pbn_b0_1_4000000 },
4223         {       PCI_VENDOR_ID_OXSEMI, 0xc158,    /* OXPCIe952 2 Native UART */
4224                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4225                 pbn_oxsemi_2_4000000 },
4226         {       PCI_VENDOR_ID_OXSEMI, 0xc15d,    /* OXPCIe952 2 Native UART */
4227                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4228                 pbn_oxsemi_2_4000000 },
4229         {       PCI_VENDOR_ID_OXSEMI, 0xc208,    /* OXPCIe954 4 Native UART */
4230                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4231                 pbn_oxsemi_4_4000000 },
4232         {       PCI_VENDOR_ID_OXSEMI, 0xc20d,    /* OXPCIe954 4 Native UART */
4233                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4234                 pbn_oxsemi_4_4000000 },
4235         {       PCI_VENDOR_ID_OXSEMI, 0xc308,    /* OXPCIe958 8 Native UART */
4236                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4237                 pbn_oxsemi_8_4000000 },
4238         {       PCI_VENDOR_ID_OXSEMI, 0xc30d,    /* OXPCIe958 8 Native UART */
4239                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4240                 pbn_oxsemi_8_4000000 },
4241         {       PCI_VENDOR_ID_OXSEMI, 0xc40b,    /* OXPCIe200 1 Native UART */
4242                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4243                 pbn_oxsemi_1_4000000 },
4244         {       PCI_VENDOR_ID_OXSEMI, 0xc40f,    /* OXPCIe200 1 Native UART */
4245                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4246                 pbn_oxsemi_1_4000000 },
4247         {       PCI_VENDOR_ID_OXSEMI, 0xc41b,    /* OXPCIe200 1 Native UART */
4248                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4249                 pbn_oxsemi_1_4000000 },
4250         {       PCI_VENDOR_ID_OXSEMI, 0xc41f,    /* OXPCIe200 1 Native UART */
4251                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4252                 pbn_oxsemi_1_4000000 },
4253         {       PCI_VENDOR_ID_OXSEMI, 0xc42b,    /* OXPCIe200 1 Native UART */
4254                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4255                 pbn_oxsemi_1_4000000 },
4256         {       PCI_VENDOR_ID_OXSEMI, 0xc42f,    /* OXPCIe200 1 Native UART */
4257                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4258                 pbn_oxsemi_1_4000000 },
4259         {       PCI_VENDOR_ID_OXSEMI, 0xc43b,    /* OXPCIe200 1 Native UART */
4260                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4261                 pbn_oxsemi_1_4000000 },
4262         {       PCI_VENDOR_ID_OXSEMI, 0xc43f,    /* OXPCIe200 1 Native UART */
4263                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4264                 pbn_oxsemi_1_4000000 },
4265         {       PCI_VENDOR_ID_OXSEMI, 0xc44b,    /* OXPCIe200 1 Native UART */
4266                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4267                 pbn_oxsemi_1_4000000 },
4268         {       PCI_VENDOR_ID_OXSEMI, 0xc44f,    /* OXPCIe200 1 Native UART */
4269                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4270                 pbn_oxsemi_1_4000000 },
4271         {       PCI_VENDOR_ID_OXSEMI, 0xc45b,    /* OXPCIe200 1 Native UART */
4272                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4273                 pbn_oxsemi_1_4000000 },
4274         {       PCI_VENDOR_ID_OXSEMI, 0xc45f,    /* OXPCIe200 1 Native UART */
4275                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4276                 pbn_oxsemi_1_4000000 },
4277         {       PCI_VENDOR_ID_OXSEMI, 0xc46b,    /* OXPCIe200 1 Native UART */
4278                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4279                 pbn_oxsemi_1_4000000 },
4280         {       PCI_VENDOR_ID_OXSEMI, 0xc46f,    /* OXPCIe200 1 Native UART */
4281                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4282                 pbn_oxsemi_1_4000000 },
4283         {       PCI_VENDOR_ID_OXSEMI, 0xc47b,    /* OXPCIe200 1 Native UART */
4284                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4285                 pbn_oxsemi_1_4000000 },
4286         {       PCI_VENDOR_ID_OXSEMI, 0xc47f,    /* OXPCIe200 1 Native UART */
4287                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4288                 pbn_oxsemi_1_4000000 },
4289         {       PCI_VENDOR_ID_OXSEMI, 0xc48b,    /* OXPCIe200 1 Native UART */
4290                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4291                 pbn_oxsemi_1_4000000 },
4292         {       PCI_VENDOR_ID_OXSEMI, 0xc48f,    /* OXPCIe200 1 Native UART */
4293                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4294                 pbn_oxsemi_1_4000000 },
4295         {       PCI_VENDOR_ID_OXSEMI, 0xc49b,    /* OXPCIe200 1 Native UART */
4296                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4297                 pbn_oxsemi_1_4000000 },
4298         {       PCI_VENDOR_ID_OXSEMI, 0xc49f,    /* OXPCIe200 1 Native UART */
4299                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4300                 pbn_oxsemi_1_4000000 },
4301         {       PCI_VENDOR_ID_OXSEMI, 0xc4ab,    /* OXPCIe200 1 Native UART */
4302                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4303                 pbn_oxsemi_1_4000000 },
4304         {       PCI_VENDOR_ID_OXSEMI, 0xc4af,    /* OXPCIe200 1 Native UART */
4305                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4306                 pbn_oxsemi_1_4000000 },
4307         {       PCI_VENDOR_ID_OXSEMI, 0xc4bb,    /* OXPCIe200 1 Native UART */
4308                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4309                 pbn_oxsemi_1_4000000 },
4310         {       PCI_VENDOR_ID_OXSEMI, 0xc4bf,    /* OXPCIe200 1 Native UART */
4311                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4312                 pbn_oxsemi_1_4000000 },
4313         {       PCI_VENDOR_ID_OXSEMI, 0xc4cb,    /* OXPCIe200 1 Native UART */
4314                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4315                 pbn_oxsemi_1_4000000 },
4316         {       PCI_VENDOR_ID_OXSEMI, 0xc4cf,    /* OXPCIe200 1 Native UART */
4317                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4318                 pbn_oxsemi_1_4000000 },
4319         /*
4320          * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
4321          */
4322         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
4323                 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
4324                 pbn_oxsemi_1_4000000 },
4325         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
4326                 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
4327                 pbn_oxsemi_2_4000000 },
4328         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
4329                 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
4330                 pbn_oxsemi_4_4000000 },
4331         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
4332                 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
4333                 pbn_oxsemi_8_4000000 },
4334
4335         /*
4336          * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
4337          */
4338         {       PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
4339                 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
4340                 pbn_oxsemi_2_4000000 },
4341
4342         /*
4343          * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
4344          * from skokodyn@yahoo.com
4345          */
4346         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4347                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
4348                 pbn_sbsxrsio },
4349         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4350                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
4351                 pbn_sbsxrsio },
4352         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4353                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
4354                 pbn_sbsxrsio },
4355         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4356                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
4357                 pbn_sbsxrsio },
4358
4359         /*
4360          * Digitan DS560-558, from jimd@esoft.com
4361          */
4362         {       PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
4363                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4364                 pbn_b1_1_115200 },
4365
4366         /*
4367          * Titan Electronic cards
4368          *  The 400L and 800L have a custom setup quirk.
4369          */
4370         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
4371                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4372                 pbn_b0_1_921600 },
4373         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
4374                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4375                 pbn_b0_2_921600 },
4376         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
4377                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4378                 pbn_b0_4_921600 },
4379         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
4380                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4381                 pbn_b0_4_921600 },
4382         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
4383                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4384                 pbn_b1_1_921600 },
4385         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
4386                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4387                 pbn_b1_bt_2_921600 },
4388         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
4389                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4390                 pbn_b0_bt_4_921600 },
4391         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
4392                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4393                 pbn_b0_bt_8_921600 },
4394         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
4395                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4396                 pbn_b4_bt_2_921600 },
4397         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
4398                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4399                 pbn_b4_bt_4_921600 },
4400         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
4401                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4402                 pbn_b4_bt_8_921600 },
4403         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
4404                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4405                 pbn_b0_4_921600 },
4406         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
4407                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4408                 pbn_b0_4_921600 },
4409         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
4410                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4411                 pbn_b0_4_921600 },
4412         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
4413                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4414                 pbn_oxsemi_1_4000000 },
4415         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
4416                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4417                 pbn_oxsemi_2_4000000 },
4418         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
4419                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4420                 pbn_oxsemi_4_4000000 },
4421         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
4422                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4423                 pbn_oxsemi_8_4000000 },
4424         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
4425                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4426                 pbn_oxsemi_2_4000000 },
4427         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
4428                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4429                 pbn_oxsemi_2_4000000 },
4430         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
4431                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4432                 pbn_b0_4_921600 },
4433         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
4434                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4435                 pbn_b0_4_921600 },
4436         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
4437                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4438                 pbn_b0_4_921600 },
4439         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
4440                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4441                 pbn_b0_4_921600 },
4442
4443         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
4444                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4445                 pbn_b2_1_460800 },
4446         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
4447                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4448                 pbn_b2_1_460800 },
4449         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
4450                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4451                 pbn_b2_1_460800 },
4452         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
4453                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4454                 pbn_b2_bt_2_921600 },
4455         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
4456                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4457                 pbn_b2_bt_2_921600 },
4458         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
4459                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4460                 pbn_b2_bt_2_921600 },
4461         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
4462                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4463                 pbn_b2_bt_4_921600 },
4464         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
4465                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4466                 pbn_b2_bt_4_921600 },
4467         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
4468                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4469                 pbn_b2_bt_4_921600 },
4470         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
4471                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4472                 pbn_b0_1_921600 },
4473         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
4474                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4475                 pbn_b0_1_921600 },
4476         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
4477                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4478                 pbn_b0_1_921600 },
4479         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
4480                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4481                 pbn_b0_bt_2_921600 },
4482         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
4483                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4484                 pbn_b0_bt_2_921600 },
4485         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
4486                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4487                 pbn_b0_bt_2_921600 },
4488         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
4489                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4490                 pbn_b0_bt_4_921600 },
4491         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
4492                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4493                 pbn_b0_bt_4_921600 },
4494         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
4495                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4496                 pbn_b0_bt_4_921600 },
4497         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
4498                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4499                 pbn_b0_bt_8_921600 },
4500         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
4501                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4502                 pbn_b0_bt_8_921600 },
4503         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
4504                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4505                 pbn_b0_bt_8_921600 },
4506
4507         /*
4508          * Computone devices submitted by Doug McNash dmcnash@computone.com
4509          */
4510         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4511                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
4512                 0, 0, pbn_computone_4 },
4513         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4514                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
4515                 0, 0, pbn_computone_8 },
4516         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4517                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
4518                 0, 0, pbn_computone_6 },
4519
4520         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
4521                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4522                 pbn_oxsemi },
4523         {       PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
4524                 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
4525                 pbn_b0_bt_1_921600 },
4526
4527         /*
4528          * SUNIX (TIMEDIA)
4529          */
4530         {       PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4531                 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4532                 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xffff00,
4533                 pbn_b0_bt_1_921600 },
4534
4535         {       PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4536                 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4537                 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
4538                 pbn_b0_bt_1_921600 },
4539
4540         /*
4541          * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
4542          */
4543         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
4544                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4545                 pbn_b0_bt_8_115200 },
4546         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
4547                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4548                 pbn_b0_bt_8_115200 },
4549
4550         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
4551                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4552                 pbn_b0_bt_2_115200 },
4553         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
4554                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4555                 pbn_b0_bt_2_115200 },
4556         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
4557                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4558                 pbn_b0_bt_2_115200 },
4559         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
4560                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4561                 pbn_b0_bt_2_115200 },
4562         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
4563                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4564                 pbn_b0_bt_2_115200 },
4565         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
4566                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4567                 pbn_b0_bt_4_460800 },
4568         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
4569                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4570                 pbn_b0_bt_4_460800 },
4571         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
4572                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4573                 pbn_b0_bt_2_460800 },
4574         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
4575                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4576                 pbn_b0_bt_2_460800 },
4577         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
4578                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4579                 pbn_b0_bt_2_460800 },
4580         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
4581                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4582                 pbn_b0_bt_1_115200 },
4583         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
4584                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4585                 pbn_b0_bt_1_460800 },
4586
4587         /*
4588          * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
4589          * Cards are identified by their subsystem vendor IDs, which
4590          * (in hex) match the model number.
4591          *
4592          * Note that JC140x are RS422/485 cards which require ox950
4593          * ACR = 0x10, and as such are not currently fully supported.
4594          */
4595         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4596                 0x1204, 0x0004, 0, 0,
4597                 pbn_b0_4_921600 },
4598         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4599                 0x1208, 0x0004, 0, 0,
4600                 pbn_b0_4_921600 },
4601 /*      {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4602                 0x1402, 0x0002, 0, 0,
4603                 pbn_b0_2_921600 }, */
4604 /*      {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4605                 0x1404, 0x0004, 0, 0,
4606                 pbn_b0_4_921600 }, */
4607         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
4608                 0x1208, 0x0004, 0, 0,
4609                 pbn_b0_4_921600 },
4610
4611         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4612                 0x1204, 0x0004, 0, 0,
4613                 pbn_b0_4_921600 },
4614         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4615                 0x1208, 0x0004, 0, 0,
4616                 pbn_b0_4_921600 },
4617         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
4618                 0x1208, 0x0004, 0, 0,
4619                 pbn_b0_4_921600 },
4620         /*
4621          * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
4622          */
4623         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
4624                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4625                 pbn_b1_1_1382400 },
4626
4627         /*
4628          * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
4629          */
4630         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
4631                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4632                 pbn_b1_1_1382400 },
4633
4634         /*
4635          * RAStel 2 port modem, gerg@moreton.com.au
4636          */
4637         {       PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
4638                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4639                 pbn_b2_bt_2_115200 },
4640
4641         /*
4642          * EKF addition for i960 Boards form EKF with serial port
4643          */
4644         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
4645                 0xE4BF, PCI_ANY_ID, 0, 0,
4646                 pbn_intel_i960 },
4647
4648         /*
4649          * Xircom Cardbus/Ethernet combos
4650          */
4651         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
4652                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4653                 pbn_b0_1_115200 },
4654         /*
4655          * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
4656          */
4657         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
4658                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4659                 pbn_b0_1_115200 },
4660
4661         /*
4662          * Untested PCI modems, sent in from various folks...
4663          */
4664
4665         /*
4666          * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
4667          */
4668         {       PCI_VENDOR_ID_ROCKWELL, 0x1004,
4669                 0x1048, 0x1500, 0, 0,
4670                 pbn_b1_1_115200 },
4671
4672         {       PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
4673                 0xFF00, 0, 0, 0,
4674                 pbn_sgi_ioc3 },
4675
4676         /*
4677          * HP Diva card
4678          */
4679         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
4680                 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
4681                 pbn_b1_1_115200 },
4682         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
4683                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4684                 pbn_b0_5_115200 },
4685         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
4686                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4687                 pbn_b2_1_115200 },
4688
4689         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
4690                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4691                 pbn_b3_2_115200 },
4692         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
4693                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4694                 pbn_b3_4_115200 },
4695         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
4696                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4697                 pbn_b3_8_115200 },
4698
4699         /*
4700          * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
4701          */
4702         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4703                 PCI_ANY_ID, PCI_ANY_ID,
4704                 0,
4705                 0, pbn_exar_XR17C152 },
4706         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4707                 PCI_ANY_ID, PCI_ANY_ID,
4708                 0,
4709                 0, pbn_exar_XR17C154 },
4710         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4711                 PCI_ANY_ID, PCI_ANY_ID,
4712                 0,
4713                 0, pbn_exar_XR17C158 },
4714         /*
4715          * Exar Corp. XR17V35[248] Dual/Quad/Octal PCIe UARTs
4716          */
4717         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V352,
4718                 PCI_ANY_ID, PCI_ANY_ID,
4719                 0,
4720                 0, pbn_exar_XR17V352 },
4721         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V354,
4722                 PCI_ANY_ID, PCI_ANY_ID,
4723                 0,
4724                 0, pbn_exar_XR17V354 },
4725         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V358,
4726                 PCI_ANY_ID, PCI_ANY_ID,
4727                 0,
4728                 0, pbn_exar_XR17V358 },
4729
4730         /*
4731          * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
4732          */
4733         {       PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
4734                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4735                 pbn_b0_1_115200 },
4736         /*
4737          * ITE
4738          */
4739         {       PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
4740                 PCI_ANY_ID, PCI_ANY_ID,
4741                 0, 0,
4742                 pbn_b1_bt_1_115200 },
4743
4744         /*
4745          * IntaShield IS-200
4746          */
4747         {       PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
4748                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,   /* 135a.0811 */
4749                 pbn_b2_2_115200 },
4750         /*
4751          * IntaShield IS-400
4752          */
4753         {       PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
4754                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,    /* 135a.0dc0 */
4755                 pbn_b2_4_115200 },
4756         /*
4757          * Perle PCI-RAS cards
4758          */
4759         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4760                 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
4761                 0, 0, pbn_b2_4_921600 },
4762         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4763                 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
4764                 0, 0, pbn_b2_8_921600 },
4765
4766         /*
4767          * Mainpine series cards: Fairly standard layout but fools
4768          * parts of the autodetect in some cases and uses otherwise
4769          * unmatched communications subclasses in the PCI Express case
4770          */
4771
4772         {       /* RockForceDUO */
4773                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4774                 PCI_VENDOR_ID_MAINPINE, 0x0200,
4775                 0, 0, pbn_b0_2_115200 },
4776         {       /* RockForceQUATRO */
4777                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4778                 PCI_VENDOR_ID_MAINPINE, 0x0300,
4779                 0, 0, pbn_b0_4_115200 },
4780         {       /* RockForceDUO+ */
4781                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4782                 PCI_VENDOR_ID_MAINPINE, 0x0400,
4783                 0, 0, pbn_b0_2_115200 },
4784         {       /* RockForceQUATRO+ */
4785                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4786                 PCI_VENDOR_ID_MAINPINE, 0x0500,
4787                 0, 0, pbn_b0_4_115200 },
4788         {       /* RockForce+ */
4789                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4790                 PCI_VENDOR_ID_MAINPINE, 0x0600,
4791                 0, 0, pbn_b0_2_115200 },
4792         {       /* RockForce+ */
4793                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4794                 PCI_VENDOR_ID_MAINPINE, 0x0700,
4795                 0, 0, pbn_b0_4_115200 },
4796         {       /* RockForceOCTO+ */
4797                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4798                 PCI_VENDOR_ID_MAINPINE, 0x0800,
4799                 0, 0, pbn_b0_8_115200 },
4800         {       /* RockForceDUO+ */
4801                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4802                 PCI_VENDOR_ID_MAINPINE, 0x0C00,
4803                 0, 0, pbn_b0_2_115200 },
4804         {       /* RockForceQUARTRO+ */
4805                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4806                 PCI_VENDOR_ID_MAINPINE, 0x0D00,
4807                 0, 0, pbn_b0_4_115200 },
4808         {       /* RockForceOCTO+ */
4809                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4810                 PCI_VENDOR_ID_MAINPINE, 0x1D00,
4811                 0, 0, pbn_b0_8_115200 },
4812         {       /* RockForceD1 */
4813                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4814                 PCI_VENDOR_ID_MAINPINE, 0x2000,
4815                 0, 0, pbn_b0_1_115200 },
4816         {       /* RockForceF1 */
4817                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4818                 PCI_VENDOR_ID_MAINPINE, 0x2100,
4819                 0, 0, pbn_b0_1_115200 },
4820         {       /* RockForceD2 */
4821                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4822                 PCI_VENDOR_ID_MAINPINE, 0x2200,
4823                 0, 0, pbn_b0_2_115200 },
4824         {       /* RockForceF2 */
4825                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4826                 PCI_VENDOR_ID_MAINPINE, 0x2300,
4827                 0, 0, pbn_b0_2_115200 },
4828         {       /* RockForceD4 */
4829                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4830                 PCI_VENDOR_ID_MAINPINE, 0x2400,
4831                 0, 0, pbn_b0_4_115200 },
4832         {       /* RockForceF4 */
4833                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4834                 PCI_VENDOR_ID_MAINPINE, 0x2500,
4835                 0, 0, pbn_b0_4_115200 },
4836         {       /* RockForceD8 */
4837                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4838                 PCI_VENDOR_ID_MAINPINE, 0x2600,
4839                 0, 0, pbn_b0_8_115200 },
4840         {       /* RockForceF8 */
4841                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4842                 PCI_VENDOR_ID_MAINPINE, 0x2700,
4843                 0, 0, pbn_b0_8_115200 },
4844         {       /* IQ Express D1 */
4845                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4846                 PCI_VENDOR_ID_MAINPINE, 0x3000,
4847                 0, 0, pbn_b0_1_115200 },
4848         {       /* IQ Express F1 */
4849                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4850                 PCI_VENDOR_ID_MAINPINE, 0x3100,
4851                 0, 0, pbn_b0_1_115200 },
4852         {       /* IQ Express D2 */
4853                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4854                 PCI_VENDOR_ID_MAINPINE, 0x3200,
4855                 0, 0, pbn_b0_2_115200 },
4856         {       /* IQ Express F2 */
4857                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4858                 PCI_VENDOR_ID_MAINPINE, 0x3300,
4859                 0, 0, pbn_b0_2_115200 },
4860         {       /* IQ Express D4 */
4861                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4862                 PCI_VENDOR_ID_MAINPINE, 0x3400,
4863                 0, 0, pbn_b0_4_115200 },
4864         {       /* IQ Express F4 */
4865                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4866                 PCI_VENDOR_ID_MAINPINE, 0x3500,
4867                 0, 0, pbn_b0_4_115200 },
4868         {       /* IQ Express D8 */
4869                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4870                 PCI_VENDOR_ID_MAINPINE, 0x3C00,
4871                 0, 0, pbn_b0_8_115200 },
4872         {       /* IQ Express F8 */
4873                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4874                 PCI_VENDOR_ID_MAINPINE, 0x3D00,
4875                 0, 0, pbn_b0_8_115200 },
4876
4877
4878         /*
4879          * PA Semi PA6T-1682M on-chip UART
4880          */
4881         {       PCI_VENDOR_ID_PASEMI, 0xa004,
4882                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4883                 pbn_pasemi_1682M },
4884
4885         /*
4886          * National Instruments
4887          */
4888         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
4889                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4890                 pbn_b1_16_115200 },
4891         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
4892                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4893                 pbn_b1_8_115200 },
4894         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
4895                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4896                 pbn_b1_bt_4_115200 },
4897         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
4898                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4899                 pbn_b1_bt_2_115200 },
4900         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
4901                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4902                 pbn_b1_bt_4_115200 },
4903         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
4904                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4905                 pbn_b1_bt_2_115200 },
4906         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
4907                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4908                 pbn_b1_16_115200 },
4909         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
4910                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4911                 pbn_b1_8_115200 },
4912         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
4913                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4914                 pbn_b1_bt_4_115200 },
4915         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
4916                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4917                 pbn_b1_bt_2_115200 },
4918         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
4919                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4920                 pbn_b1_bt_4_115200 },
4921         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
4922                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4923                 pbn_b1_bt_2_115200 },
4924         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
4925                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4926                 pbn_ni8430_2 },
4927         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
4928                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4929                 pbn_ni8430_2 },
4930         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
4931                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4932                 pbn_ni8430_4 },
4933         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
4934                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4935                 pbn_ni8430_4 },
4936         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
4937                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4938                 pbn_ni8430_8 },
4939         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
4940                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4941                 pbn_ni8430_8 },
4942         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
4943                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4944                 pbn_ni8430_16 },
4945         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
4946                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4947                 pbn_ni8430_16 },
4948         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
4949                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4950                 pbn_ni8430_2 },
4951         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
4952                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4953                 pbn_ni8430_2 },
4954         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
4955                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4956                 pbn_ni8430_4 },
4957         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
4958                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4959                 pbn_ni8430_4 },
4960
4961         /*
4962         * ADDI-DATA GmbH communication cards <info@addi-data.com>
4963         */
4964         {       PCI_VENDOR_ID_ADDIDATA,
4965                 PCI_DEVICE_ID_ADDIDATA_APCI7500,
4966                 PCI_ANY_ID,
4967                 PCI_ANY_ID,
4968                 0,
4969                 0,
4970                 pbn_b0_4_115200 },
4971
4972         {       PCI_VENDOR_ID_ADDIDATA,
4973                 PCI_DEVICE_ID_ADDIDATA_APCI7420,
4974                 PCI_ANY_ID,
4975                 PCI_ANY_ID,
4976                 0,
4977                 0,
4978                 pbn_b0_2_115200 },
4979
4980         {       PCI_VENDOR_ID_ADDIDATA,
4981                 PCI_DEVICE_ID_ADDIDATA_APCI7300,
4982                 PCI_ANY_ID,
4983                 PCI_ANY_ID,
4984                 0,
4985                 0,
4986                 pbn_b0_1_115200 },
4987
4988         {       PCI_VENDOR_ID_AMCC,
4989                 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
4990                 PCI_ANY_ID,
4991                 PCI_ANY_ID,
4992                 0,
4993                 0,
4994                 pbn_b1_8_115200 },
4995
4996         {       PCI_VENDOR_ID_ADDIDATA,
4997                 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
4998                 PCI_ANY_ID,
4999                 PCI_ANY_ID,
5000                 0,
5001                 0,
5002                 pbn_b0_4_115200 },
5003
5004         {       PCI_VENDOR_ID_ADDIDATA,
5005                 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
5006                 PCI_ANY_ID,
5007                 PCI_ANY_ID,
5008                 0,
5009                 0,
5010                 pbn_b0_2_115200 },
5011
5012         {       PCI_VENDOR_ID_ADDIDATA,
5013                 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
5014                 PCI_ANY_ID,
5015                 PCI_ANY_ID,
5016                 0,
5017                 0,
5018                 pbn_b0_1_115200 },
5019
5020         {       PCI_VENDOR_ID_ADDIDATA,
5021                 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
5022                 PCI_ANY_ID,
5023                 PCI_ANY_ID,
5024                 0,
5025                 0,
5026                 pbn_b0_4_115200 },
5027
5028         {       PCI_VENDOR_ID_ADDIDATA,
5029                 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
5030                 PCI_ANY_ID,
5031                 PCI_ANY_ID,
5032                 0,
5033                 0,
5034                 pbn_b0_2_115200 },
5035
5036         {       PCI_VENDOR_ID_ADDIDATA,
5037                 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
5038                 PCI_ANY_ID,
5039                 PCI_ANY_ID,
5040                 0,
5041                 0,
5042                 pbn_b0_1_115200 },
5043
5044         {       PCI_VENDOR_ID_ADDIDATA,
5045                 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
5046                 PCI_ANY_ID,
5047                 PCI_ANY_ID,
5048                 0,
5049                 0,
5050                 pbn_b0_8_115200 },
5051
5052         {       PCI_VENDOR_ID_ADDIDATA,
5053                 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
5054                 PCI_ANY_ID,
5055                 PCI_ANY_ID,
5056                 0,
5057                 0,
5058                 pbn_ADDIDATA_PCIe_4_3906250 },
5059
5060         {       PCI_VENDOR_ID_ADDIDATA,
5061                 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
5062                 PCI_ANY_ID,
5063                 PCI_ANY_ID,
5064                 0,
5065                 0,
5066                 pbn_ADDIDATA_PCIe_2_3906250 },
5067
5068         {       PCI_VENDOR_ID_ADDIDATA,
5069                 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
5070                 PCI_ANY_ID,
5071                 PCI_ANY_ID,
5072                 0,
5073                 0,
5074                 pbn_ADDIDATA_PCIe_1_3906250 },
5075
5076         {       PCI_VENDOR_ID_ADDIDATA,
5077                 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
5078                 PCI_ANY_ID,
5079                 PCI_ANY_ID,
5080                 0,
5081                 0,
5082                 pbn_ADDIDATA_PCIe_8_3906250 },
5083
5084         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
5085                 PCI_VENDOR_ID_IBM, 0x0299,
5086                 0, 0, pbn_b0_bt_2_115200 },
5087
5088         /*
5089          * other NetMos 9835 devices are most likely handled by the
5090          * parport_serial driver, check drivers/parport/parport_serial.c
5091          * before adding them here.
5092          */
5093
5094         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
5095                 0xA000, 0x1000,
5096                 0, 0, pbn_b0_1_115200 },
5097
5098         /* the 9901 is a rebranded 9912 */
5099         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
5100                 0xA000, 0x1000,
5101                 0, 0, pbn_b0_1_115200 },
5102
5103         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
5104                 0xA000, 0x1000,
5105                 0, 0, pbn_b0_1_115200 },
5106
5107         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
5108                 0xA000, 0x1000,
5109                 0, 0, pbn_b0_1_115200 },
5110
5111         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5112                 0xA000, 0x1000,
5113                 0, 0, pbn_b0_1_115200 },
5114
5115         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5116                 0xA000, 0x3002,
5117                 0, 0, pbn_NETMOS9900_2s_115200 },
5118
5119         /*
5120          * Best Connectivity and Rosewill PCI Multi I/O cards
5121          */
5122
5123         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5124                 0xA000, 0x1000,
5125                 0, 0, pbn_b0_1_115200 },
5126
5127         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5128                 0xA000, 0x3002,
5129                 0, 0, pbn_b0_bt_2_115200 },
5130
5131         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5132                 0xA000, 0x3004,
5133                 0, 0, pbn_b0_bt_4_115200 },
5134         /* Intel CE4100 */
5135         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
5136                 PCI_ANY_ID,  PCI_ANY_ID, 0, 0,
5137                 pbn_ce4100_1_115200 },
5138         /* Intel BayTrail */
5139         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART1,
5140                 PCI_ANY_ID,  PCI_ANY_ID,
5141                 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5142                 pbn_byt },
5143         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART2,
5144                 PCI_ANY_ID,  PCI_ANY_ID,
5145                 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5146                 pbn_byt },
5147
5148         /*
5149          * Cronyx Omega PCI
5150          */
5151         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
5152                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5153                 pbn_omegapci },
5154
5155         /*
5156          * Broadcom TruManage
5157          */
5158         {       PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
5159                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5160                 pbn_brcm_trumanage },
5161
5162         /*
5163          * AgeStar as-prs2-009
5164          */
5165         {       PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375,
5166                 PCI_ANY_ID, PCI_ANY_ID,
5167                 0, 0, pbn_b0_bt_2_115200 },
5168
5169         /*
5170          * WCH CH353 series devices: The 2S1P is handled by parport_serial
5171          * so not listed here.
5172          */
5173         {       PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S,
5174                 PCI_ANY_ID, PCI_ANY_ID,
5175                 0, 0, pbn_b0_bt_4_115200 },
5176
5177         {       PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF,
5178                 PCI_ANY_ID, PCI_ANY_ID,
5179                 0, 0, pbn_b0_bt_2_115200 },
5180
5181         {       PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH352_2S,
5182                 PCI_ANY_ID, PCI_ANY_ID,
5183                 0, 0, pbn_b0_bt_2_115200 },
5184
5185         /*
5186          * Commtech, Inc. Fastcom adapters
5187          */
5188         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCI335,
5189                 PCI_ANY_ID, PCI_ANY_ID,
5190                 0,
5191                 0, pbn_b0_2_1152000_200 },
5192         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCI335,
5193                 PCI_ANY_ID, PCI_ANY_ID,
5194                 0,
5195                 0, pbn_b0_4_1152000_200 },
5196         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2324PCI335,
5197                 PCI_ANY_ID, PCI_ANY_ID,
5198                 0,
5199                 0, pbn_b0_4_1152000_200 },
5200         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2328PCI335,
5201                 PCI_ANY_ID, PCI_ANY_ID,
5202                 0,
5203                 0, pbn_b0_8_1152000_200 },
5204         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCIE,
5205                 PCI_ANY_ID, PCI_ANY_ID,
5206                 0,
5207                 0, pbn_exar_XR17V352 },
5208         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCIE,
5209                 PCI_ANY_ID, PCI_ANY_ID,
5210                 0,
5211                 0, pbn_exar_XR17V354 },
5212         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4228PCIE,
5213                 PCI_ANY_ID, PCI_ANY_ID,
5214                 0,
5215                 0, pbn_exar_XR17V358 },
5216
5217         /* Fintek PCI serial cards */
5218         { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 },
5219         { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 },
5220         { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 },
5221
5222         /*
5223          * These entries match devices with class COMMUNICATION_SERIAL,
5224          * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
5225          */
5226         {       PCI_ANY_ID, PCI_ANY_ID,
5227                 PCI_ANY_ID, PCI_ANY_ID,
5228                 PCI_CLASS_COMMUNICATION_SERIAL << 8,
5229                 0xffff00, pbn_default },
5230         {       PCI_ANY_ID, PCI_ANY_ID,
5231                 PCI_ANY_ID, PCI_ANY_ID,
5232                 PCI_CLASS_COMMUNICATION_MODEM << 8,
5233                 0xffff00, pbn_default },
5234         {       PCI_ANY_ID, PCI_ANY_ID,
5235                 PCI_ANY_ID, PCI_ANY_ID,
5236                 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
5237                 0xffff00, pbn_default },
5238         { 0, }
5239 };
5240
5241 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
5242                                                 pci_channel_state_t state)
5243 {
5244         struct serial_private *priv = pci_get_drvdata(dev);
5245
5246         if (state == pci_channel_io_perm_failure)
5247                 return PCI_ERS_RESULT_DISCONNECT;
5248
5249         if (priv)
5250                 pciserial_suspend_ports(priv);
5251
5252         pci_disable_device(dev);
5253
5254         return PCI_ERS_RESULT_NEED_RESET;
5255 }
5256
5257 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
5258 {
5259         int rc;
5260
5261         rc = pci_enable_device(dev);
5262
5263         if (rc)
5264                 return PCI_ERS_RESULT_DISCONNECT;
5265
5266         pci_restore_state(dev);
5267         pci_save_state(dev);
5268
5269         return PCI_ERS_RESULT_RECOVERED;
5270 }
5271
5272 static void serial8250_io_resume(struct pci_dev *dev)
5273 {
5274         struct serial_private *priv = pci_get_drvdata(dev);
5275
5276         if (priv)
5277                 pciserial_resume_ports(priv);
5278 }
5279
5280 static const struct pci_error_handlers serial8250_err_handler = {
5281         .error_detected = serial8250_io_error_detected,
5282         .slot_reset = serial8250_io_slot_reset,
5283         .resume = serial8250_io_resume,
5284 };
5285
5286 static struct pci_driver serial_pci_driver = {
5287         .name           = "serial",
5288         .probe          = pciserial_init_one,
5289         .remove         = pciserial_remove_one,
5290 #ifdef CONFIG_PM
5291         .suspend        = pciserial_suspend_one,
5292         .resume         = pciserial_resume_one,
5293 #endif
5294         .id_table       = serial_pci_tbl,
5295         .err_handler    = &serial8250_err_handler,
5296 };
5297
5298 module_pci_driver(serial_pci_driver);
5299
5300 MODULE_LICENSE("GPL");
5301 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
5302 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);