Pileus Git - ~andy/linux/blob - drivers/tty/serial/8250/8250_dw.c

   1 /*
   2  * Synopsys DesignWare 8250 driver.
   3  *
   4  * Copyright 2011 Picochip, Jamie Iles.
   5  * Copyright 2013 Intel Corporation
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * The Synopsys DesignWare 8250 has an extra feature whereby it detects if the
  13  * LCR is written whilst busy.  If it is, then a busy detect interrupt is
  14  * raised, the LCR needs to be rewritten and the uart status register read.
  15  */
  16 #include <linux/device.h>
  17 #include <linux/init.h>
  18 #include <linux/io.h>
  19 #include <linux/module.h>
  20 #include <linux/serial_8250.h>
  21 #include <linux/serial_core.h>
  22 #include <linux/serial_reg.h>
  23 #include <linux/of.h>
  24 #include <linux/of_irq.h>
  25 #include <linux/of_platform.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/slab.h>
  28 #include <linux/acpi.h>
  29 #include <linux/clk.h>
  30 #include <linux/pm_runtime.h>
  31
  32 #include <asm/byteorder.h>
  33
  34 #include "8250.h"
  35
  36 /* Offsets for the DesignWare specific registers */
  37 #define DW_UART_USR     0x1f /* UART Status Register */
  38 #define DW_UART_CPR     0xf4 /* Component Parameter Register */
  39 #define DW_UART_UCV     0xf8 /* UART Component Version */
  40
  41 /* Component Parameter Register bits */
  42 #define DW_UART_CPR_ABP_DATA_WIDTH      (3 << 0)
  43 #define DW_UART_CPR_AFCE_MODE           (1 << 4)
  44 #define DW_UART_CPR_THRE_MODE           (1 << 5)
  45 #define DW_UART_CPR_SIR_MODE            (1 << 6)
  46 #define DW_UART_CPR_SIR_LP_MODE         (1 << 7)
  47 #define DW_UART_CPR_ADDITIONAL_FEATURES (1 << 8)
  48 #define DW_UART_CPR_FIFO_ACCESS         (1 << 9)
  49 #define DW_UART_CPR_FIFO_STAT           (1 << 10)
  50 #define DW_UART_CPR_SHADOW              (1 << 11)
  51 #define DW_UART_CPR_ENCODED_PARMS       (1 << 12)
  52 #define DW_UART_CPR_DMA_EXTRA           (1 << 13)
  53 #define DW_UART_CPR_FIFO_MODE           (0xff << 16)
  54 /* Helper for fifo size calculation */
  55 #define DW_UART_CPR_FIFO_SIZE(a)        (((a >> 16) & 0xff) * 16)
  56
  57
  58 struct dw8250_data {
  59         u8                      usr_reg;
  60         int                     last_mcr;
  61         int                     line;
  62         struct clk              *clk;
  63         struct uart_8250_dma    dma;
  64 };
  65
  66 static inline int dw8250_modify_msr(struct uart_port *p, int offset, int value)
  67 {
  68         struct dw8250_data *d = p->private_data;
  69
  70         /* If reading MSR, report CTS asserted when auto-CTS/RTS enabled */
  71         if (offset == UART_MSR && d->last_mcr & UART_MCR_AFE) {
  72                 value |= UART_MSR_CTS;
  73                 value &= ~UART_MSR_DCTS;
  74         }
  75
  76         return value;
  77 }
  78
  79 static void dw8250_force_idle(struct uart_port *p)
  80 {
  81         serial8250_clear_and_reinit_fifos(container_of
  82                                           (p, struct uart_8250_port, port));
  83         (void)p->serial_in(p, UART_RX);
  84 }
  85
  86 static void dw8250_serial_out(struct uart_port *p, int offset, int value)
  87 {
  88         struct dw8250_data *d = p->private_data;
  89
  90         if (offset == UART_MCR)
  91                 d->last_mcr = value;
  92
  93         writeb(value, p->membase + (offset << p->regshift));
  94
  95         /* Make sure LCR write wasn't ignored */
  96         if (offset == UART_LCR) {
  97                 int tries = 1000;
  98                 while (tries--) {
  99                         unsigned int lcr = p->serial_in(p, UART_LCR);
 100                         if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR))
 101                                 return;
 102                         dw8250_force_idle(p);
 103                         writeb(value, p->membase + (UART_LCR << p->regshift));
 104                 }
 105                 dev_err(p->dev, "Couldn't set LCR to %d\n", value);
 106         }
 107 }
 108
 109 static unsigned int dw8250_serial_in(struct uart_port *p, int offset)
 110 {
 111         unsigned int value = readb(p->membase + (offset << p->regshift));
 112
 113         return dw8250_modify_msr(p, offset, value);
 114 }
 115
 116 /* Read Back (rb) version to ensure register access ording. */
 117 static void dw8250_serial_out_rb(struct uart_port *p, int offset, int value)
 118 {
 119         dw8250_serial_out(p, offset, value);
 120         dw8250_serial_in(p, UART_LCR);
 121 }
 122
 123 static void dw8250_serial_out32(struct uart_port *p, int offset, int value)
 124 {
 125         struct dw8250_data *d = p->private_data;
 126
 127         if (offset == UART_MCR)
 128                 d->last_mcr = value;
 129
 130         writel(value, p->membase + (offset << p->regshift));
 131
 132         /* Make sure LCR write wasn't ignored */
 133         if (offset == UART_LCR) {
 134                 int tries = 1000;
 135                 while (tries--) {
 136                         unsigned int lcr = p->serial_in(p, UART_LCR);
 137                         if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR))
 138                                 return;
 139                         dw8250_force_idle(p);
 140                         writel(value, p->membase + (UART_LCR << p->regshift));
 141                 }
 142                 dev_err(p->dev, "Couldn't set LCR to %d\n", value);
 143         }
 144 }
 145
 146 static unsigned int dw8250_serial_in32(struct uart_port *p, int offset)
 147 {
 148         unsigned int value = readl(p->membase + (offset << p->regshift));
 149
 150         return dw8250_modify_msr(p, offset, value);
 151 }
 152
 153 static int dw8250_handle_irq(struct uart_port *p)
 154 {
 155         struct dw8250_data *d = p->private_data;
 156         unsigned int iir = p->serial_in(p, UART_IIR);
 157
 158         if (serial8250_handle_irq(p, iir)) {
 159                 return 1;
 160         } else if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
 161                 /* Clear the USR */
 162                 (void)p->serial_in(p, d->usr_reg);
 163
 164                 return 1;
 165         }
 166
 167         return 0;
 168 }
 169
 170 static void
 171 dw8250_do_pm(struct uart_port *port, unsigned int state, unsigned int old)
 172 {
 173         if (!state)
 174                 pm_runtime_get_sync(port->dev);
 175
 176         serial8250_do_pm(port, state, old);
 177
 178         if (state)
 179                 pm_runtime_put_sync_suspend(port->dev);
 180 }
 181
 182 static bool dw8250_dma_filter(struct dma_chan *chan, void *param)
 183 {
 184         struct dw8250_data *data = param;
 185
 186         return chan->chan_id == data->dma.tx_chan_id ||
 187                chan->chan_id == data->dma.rx_chan_id;
 188 }
 189
 190 static void dw8250_setup_port(struct uart_8250_port *up)
 191 {
 192         struct uart_port        *p = &up->port;
 193         u32                     reg = readl(p->membase + DW_UART_UCV);
 194
 195         /*
 196          * If the Component Version Register returns zero, we know that
 197          * ADDITIONAL_FEATURES are not enabled. No need to go any further.
 198          */
 199         if (!reg)
 200                 return;
 201
 202         dev_dbg_ratelimited(p->dev, "Designware UART version %c.%c%c\n",
 203                 (reg >> 24) & 0xff, (reg >> 16) & 0xff, (reg >> 8) & 0xff);
 204
 205         reg = readl(p->membase + DW_UART_CPR);
 206         if (!reg)
 207                 return;
 208
 209         /* Select the type based on fifo */
 210         if (reg & DW_UART_CPR_FIFO_MODE) {
 211                 p->type = PORT_16550A;
 212                 p->flags |= UPF_FIXED_TYPE;
 213                 p->fifosize = DW_UART_CPR_FIFO_SIZE(reg);
 214                 up->tx_loadsz = p->fifosize;
 215                 up->capabilities = UART_CAP_FIFO;
 216         }
 217
 218         if (reg & DW_UART_CPR_AFCE_MODE)
 219                 up->capabilities |= UART_CAP_AFE;
 220 }
 221
 222 static int dw8250_probe_of(struct uart_port *p,
 223                            struct dw8250_data *data)
 224 {
 225         struct device_node      *np = p->dev->of_node;
 226         u32                     val;
 227         bool has_ucv = true;
 228
 229         if (of_device_is_compatible(np, "cavium,octeon-3860-uart")) {
 230 #ifdef __BIG_ENDIAN
 231                 /*
 232                  * Low order bits of these 64-bit registers, when
 233                  * accessed as a byte, are 7 bytes further down in the
 234                  * address space in big endian mode.
 235                  */
 236                 p->membase += 7;
 237 #endif
 238                 p->serial_out = dw8250_serial_out_rb;
 239                 p->flags = ASYNC_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE;
 240                 p->type = PORT_OCTEON;
 241                 data->usr_reg = 0x27;
 242                 has_ucv = false;
 243         } else if (!of_property_read_u32(np, "reg-io-width", &val)) {
 244                 switch (val) {
 245                 case 1:
 246                         break;
 247                 case 4:
 248                         p->iotype = UPIO_MEM32;
 249                         p->serial_in = dw8250_serial_in32;
 250                         p->serial_out = dw8250_serial_out32;
 251                         break;
 252                 default:
 253                         dev_err(p->dev, "unsupported reg-io-width (%u)\n", val);
 254                         return -EINVAL;
 255                 }
 256         }
 257         if (has_ucv)
 258                 dw8250_setup_port(container_of(p, struct uart_8250_port, port));
 259
 260         if (!of_property_read_u32(np, "reg-shift", &val))
 261                 p->regshift = val;
 262
 263         /* clock got configured through clk api, all done */
 264         if (p->uartclk)
 265                 return 0;
 266
 267         /* try to find out clock frequency from DT as fallback */
 268         if (of_property_read_u32(np, "clock-frequency", &val)) {
 269                 dev_err(p->dev, "clk or clock-frequency not defined\n");
 270                 return -EINVAL;
 271         }
 272         p->uartclk = val;
 273
 274         return 0;
 275 }
 276
 277 #ifdef CONFIG_ACPI
 278 static int dw8250_probe_acpi(struct uart_8250_port *up,
 279                              struct dw8250_data *data)
 280 {
 281         const struct acpi_device_id *id;
 282         struct uart_port *p = &up->port;
 283
 284         dw8250_setup_port(up);
 285
 286         id = acpi_match_device(p->dev->driver->acpi_match_table, p->dev);
 287         if (!id)
 288                 return -ENODEV;
 289
 290         p->iotype = UPIO_MEM32;
 291         p->serial_in = dw8250_serial_in32;
 292         p->serial_out = dw8250_serial_out32;
 293         p->regshift = 2;
 294
 295         if (!p->uartclk)
 296                 p->uartclk = (unsigned int)id->driver_data;
 297
 298         up->dma = &data->dma;
 299
 300         up->dma->rxconf.src_maxburst = p->fifosize / 4;
 301         up->dma->txconf.dst_maxburst = p->fifosize / 4;
 302
 303         return 0;
 304 }
 305 #else
 306 static inline int dw8250_probe_acpi(struct uart_8250_port *up,
 307                                     struct dw8250_data *data)
 308 {
 309         return -ENODEV;
 310 }
 311 #endif /* CONFIG_ACPI */
 312
 313 static int dw8250_probe(struct platform_device *pdev)
 314 {
 315         struct uart_8250_port uart = {};
 316         struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 317         struct resource *irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 318         struct dw8250_data *data;
 319         int err;
 320
 321         if (!regs || !irq) {
 322                 dev_err(&pdev->dev, "no registers/irq defined\n");
 323                 return -EINVAL;
 324         }
 325
 326         spin_lock_init(&uart.port.lock);
 327         uart.port.mapbase = regs->start;
 328         uart.port.irq = irq->start;
 329         uart.port.handle_irq = dw8250_handle_irq;
 330         uart.port.pm = dw8250_do_pm;
 331         uart.port.type = PORT_8250;
 332         uart.port.flags = UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF | UPF_FIXED_PORT;
 333         uart.port.dev = &pdev->dev;
 334
 335         uart.port.membase = devm_ioremap(&pdev->dev, regs->start,
 336                                          resource_size(regs));
 337         if (!uart.port.membase)
 338                 return -ENOMEM;
 339
 340         data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
 341         if (!data)
 342                 return -ENOMEM;
 343
 344         data->usr_reg = DW_UART_USR;
 345         data->clk = devm_clk_get(&pdev->dev, NULL);
 346         if (!IS_ERR(data->clk)) {
 347                 clk_prepare_enable(data->clk);
 348                 uart.port.uartclk = clk_get_rate(data->clk);
 349         }
 350
 351         data->dma.rx_chan_id = -1;
 352         data->dma.tx_chan_id = -1;
 353         data->dma.rx_param = data;
 354         data->dma.tx_param = data;
 355         data->dma.fn = dw8250_dma_filter;
 356
 357         uart.port.iotype = UPIO_MEM;
 358         uart.port.serial_in = dw8250_serial_in;
 359         uart.port.serial_out = dw8250_serial_out;
 360         uart.port.private_data = data;
 361
 362         if (pdev->dev.of_node) {
 363                 err = dw8250_probe_of(&uart.port, data);
 364                 if (err)
 365                         return err;
 366         } else if (ACPI_HANDLE(&pdev->dev)) {
 367                 err = dw8250_probe_acpi(&uart, data);
 368                 if (err)
 369                         return err;
 370         } else {
 371                 return -ENODEV;
 372         }
 373
 374         data->line = serial8250_register_8250_port(&uart);
 375         if (data->line < 0)
 376                 return data->line;
 377
 378         platform_set_drvdata(pdev, data);
 379
 380         pm_runtime_set_active(&pdev->dev);
 381         pm_runtime_enable(&pdev->dev);
 382
 383         return 0;
 384 }
 385
 386 static int dw8250_remove(struct platform_device *pdev)
 387 {
 388         struct dw8250_data *data = platform_get_drvdata(pdev);
 389
 390         pm_runtime_get_sync(&pdev->dev);
 391
 392         serial8250_unregister_port(data->line);
 393
 394         if (!IS_ERR(data->clk))
 395                 clk_disable_unprepare(data->clk);
 396
 397         pm_runtime_disable(&pdev->dev);
 398         pm_runtime_put_noidle(&pdev->dev);
 399
 400         return 0;
 401 }
 402
 403 #ifdef CONFIG_PM
 404 static int dw8250_suspend(struct device *dev)
 405 {
 406         struct dw8250_data *data = dev_get_drvdata(dev);
 407
 408         serial8250_suspend_port(data->line);
 409
 410         return 0;
 411 }
 412
 413 static int dw8250_resume(struct device *dev)
 414 {
 415         struct dw8250_data *data = dev_get_drvdata(dev);
 416
 417         serial8250_resume_port(data->line);
 418
 419         return 0;
 420 }
 421 #endif /* CONFIG_PM */
 422
 423 #ifdef CONFIG_PM_RUNTIME
 424 static int dw8250_runtime_suspend(struct device *dev)
 425 {
 426         struct dw8250_data *data = dev_get_drvdata(dev);
 427
 428         if (!IS_ERR(data->clk))
 429                 clk_disable_unprepare(data->clk);
 430
 431         return 0;
 432 }
 433
 434 static int dw8250_runtime_resume(struct device *dev)
 435 {
 436         struct dw8250_data *data = dev_get_drvdata(dev);
 437
 438         if (!IS_ERR(data->clk))
 439                 clk_prepare_enable(data->clk);
 440
 441         return 0;
 442 }
 443 #endif
 444
 445 static const struct dev_pm_ops dw8250_pm_ops = {
 446         SET_SYSTEM_SLEEP_PM_OPS(dw8250_suspend, dw8250_resume)
 447         SET_RUNTIME_PM_OPS(dw8250_runtime_suspend, dw8250_runtime_resume, NULL)
 448 };
 449
 450 static const struct of_device_id dw8250_of_match[] = {
 451         { .compatible = "snps,dw-apb-uart" },
 452         { .compatible = "cavium,octeon-3860-uart" },
 453         { /* Sentinel */ }
 454 };
 455 MODULE_DEVICE_TABLE(of, dw8250_of_match);
 456
 457 static const struct acpi_device_id dw8250_acpi_match[] = {
 458         { "INT33C4", 0 },
 459         { "INT33C5", 0 },
 460         { "INT3434", 0 },
 461         { "INT3435", 0 },
 462         { "80860F0A", 0 },
 463         { },
 464 };
 465 MODULE_DEVICE_TABLE(acpi, dw8250_acpi_match);
 466
 467 static struct platform_driver dw8250_platform_driver = {
 468         .driver = {
 469                 .name           = "dw-apb-uart",
 470                 .owner          = THIS_MODULE,
 471                 .pm             = &dw8250_pm_ops,
 472                 .of_match_table = dw8250_of_match,
 473                 .acpi_match_table = ACPI_PTR(dw8250_acpi_match),
 474         },
 475         .probe                  = dw8250_probe,
 476         .remove                 = dw8250_remove,
 477 };
 478
 479 module_platform_driver(dw8250_platform_driver);
 480
 481 MODULE_AUTHOR("Jamie Iles");
 482 MODULE_LICENSE("GPL");
 483 MODULE_DESCRIPTION("Synopsys DesignWare 8250 serial port driver");