2 * Driver for 8250/16550-type serial ports
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 * Copyright (C) 2001 Russell King.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * A note about mapbase / membase
15 * mapbase is the physical address of the IO port.
16 * membase is an 'ioremapped' cookie.
19 #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
23 #include <linux/module.h>
24 #include <linux/moduleparam.h>
25 #include <linux/ioport.h>
26 #include <linux/init.h>
27 #include <linux/console.h>
28 #include <linux/sysrq.h>
29 #include <linux/delay.h>
30 #include <linux/platform_device.h>
31 #include <linux/tty.h>
32 #include <linux/ratelimit.h>
33 #include <linux/tty_flip.h>
34 #include <linux/serial_reg.h>
35 #include <linux/serial_core.h>
36 #include <linux/serial.h>
37 #include <linux/serial_8250.h>
38 #include <linux/nmi.h>
39 #include <linux/mutex.h>
40 #include <linux/slab.h>
42 #include <linux/sunserialcore.h>
52 * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option
53 * is unsafe when used on edge-triggered interrupts.
55 static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
57 static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
59 static struct uart_driver serial8250_reg;
61 static int serial_index(struct uart_port *port)
63 return (serial8250_reg.minor - 64) + port->line;
66 static unsigned int skip_txen_test; /* force skip of txen test at init time */
72 #define DEBUG_AUTOCONF(fmt...) printk(fmt)
74 #define DEBUG_AUTOCONF(fmt...) do { } while (0)
78 #define DEBUG_INTR(fmt...) printk(fmt)
80 #define DEBUG_INTR(fmt...) do { } while (0)
83 #define PASS_LIMIT 512
85 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
88 #ifdef CONFIG_SERIAL_8250_DETECT_IRQ
89 #define CONFIG_SERIAL_DETECT_IRQ 1
91 #ifdef CONFIG_SERIAL_8250_MANY_PORTS
92 #define CONFIG_SERIAL_MANY_PORTS 1
96 * HUB6 is always on. This will be removed once the header
97 * files have been cleaned.
101 #include <asm/serial.h>
103 * SERIAL_PORT_DFNS tells us about built-in ports that have no
104 * standard enumeration mechanism. Platforms that can find all
105 * serial ports via mechanisms like ACPI or PCI need not supply it.
107 #ifndef SERIAL_PORT_DFNS
108 #define SERIAL_PORT_DFNS
111 static const struct old_serial_port old_serial_port[] = {
112 SERIAL_PORT_DFNS /* defined in asm/serial.h */
115 #define UART_NR CONFIG_SERIAL_8250_NR_UARTS
117 #ifdef CONFIG_SERIAL_8250_RSA
119 #define PORT_RSA_MAX 4
120 static unsigned long probe_rsa[PORT_RSA_MAX];
121 static unsigned int probe_rsa_count;
122 #endif /* CONFIG_SERIAL_8250_RSA */
125 struct hlist_node node;
127 spinlock_t lock; /* Protects list not the hash */
128 struct list_head *head;
131 #define NR_IRQ_HASH 32 /* Can be adjusted later */
132 static struct hlist_head irq_lists[NR_IRQ_HASH];
133 static DEFINE_MUTEX(hash_mutex); /* Used to walk the hash */
136 * Here we define the default xmit fifo size used for each type of UART.
138 static const struct serial8250_config uart_config[] = {
163 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
164 .flags = UART_CAP_FIFO,
175 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
181 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
183 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
189 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
191 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
199 .name = "16C950/954",
202 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
203 /* UART_CAP_EFR breaks billionon CF bluetooth card. */
204 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
210 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
212 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
218 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
219 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
225 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
226 .flags = UART_CAP_FIFO,
232 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
233 .flags = UART_CAP_FIFO | UART_NATSEMI,
239 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
240 .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
246 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
247 .flags = UART_CAP_FIFO,
253 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
254 .flags = UART_CAP_FIFO | UART_CAP_AFE,
260 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
261 .flags = UART_CAP_FIFO | UART_CAP_AFE,
267 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
269 .flags = UART_CAP_FIFO | UART_CAP_RTOIE,
275 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
276 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
283 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11 |
285 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
292 .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
293 UART_FCR_R_TRIG_00 | UART_FCR_T_TRIG_00,
294 .flags = UART_CAP_FIFO,
296 [PORT_BRCM_TRUMANAGE] = {
300 .flags = UART_CAP_HFIFO,
305 [PORT_ALTR_16550_F32] = {
306 .name = "Altera 16550 FIFO32",
309 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
310 .flags = UART_CAP_FIFO | UART_CAP_AFE,
312 [PORT_ALTR_16550_F64] = {
313 .name = "Altera 16550 FIFO64",
316 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
317 .flags = UART_CAP_FIFO | UART_CAP_AFE,
319 [PORT_ALTR_16550_F128] = {
320 .name = "Altera 16550 FIFO128",
323 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
324 .flags = UART_CAP_FIFO | UART_CAP_AFE,
328 /* Uart divisor latch read */
329 static int default_serial_dl_read(struct uart_8250_port *up)
331 return serial_in(up, UART_DLL) | serial_in(up, UART_DLM) << 8;
334 /* Uart divisor latch write */
335 static void default_serial_dl_write(struct uart_8250_port *up, int value)
337 serial_out(up, UART_DLL, value & 0xff);
338 serial_out(up, UART_DLM, value >> 8 & 0xff);
341 #if defined(CONFIG_MIPS_ALCHEMY) || defined(CONFIG_SERIAL_8250_RT288X)
343 /* Au1x00/RT288x UART hardware has a weird register layout */
344 static const u8 au_io_in_map[] = {
354 static const u8 au_io_out_map[] = {
362 static unsigned int au_serial_in(struct uart_port *p, int offset)
364 offset = au_io_in_map[offset] << p->regshift;
365 return __raw_readl(p->membase + offset);
368 static void au_serial_out(struct uart_port *p, int offset, int value)
370 offset = au_io_out_map[offset] << p->regshift;
371 __raw_writel(value, p->membase + offset);
374 /* Au1x00 haven't got a standard divisor latch */
375 static int au_serial_dl_read(struct uart_8250_port *up)
377 return __raw_readl(up->port.membase + 0x28);
380 static void au_serial_dl_write(struct uart_8250_port *up, int value)
382 __raw_writel(value, up->port.membase + 0x28);
387 static unsigned int hub6_serial_in(struct uart_port *p, int offset)
389 offset = offset << p->regshift;
390 outb(p->hub6 - 1 + offset, p->iobase);
391 return inb(p->iobase + 1);
394 static void hub6_serial_out(struct uart_port *p, int offset, int value)
396 offset = offset << p->regshift;
397 outb(p->hub6 - 1 + offset, p->iobase);
398 outb(value, p->iobase + 1);
401 static unsigned int mem_serial_in(struct uart_port *p, int offset)
403 offset = offset << p->regshift;
404 return readb(p->membase + offset);
407 static void mem_serial_out(struct uart_port *p, int offset, int value)
409 offset = offset << p->regshift;
410 writeb(value, p->membase + offset);
413 static void mem32_serial_out(struct uart_port *p, int offset, int value)
415 offset = offset << p->regshift;
416 writel(value, p->membase + offset);
419 static unsigned int mem32_serial_in(struct uart_port *p, int offset)
421 offset = offset << p->regshift;
422 return readl(p->membase + offset);
425 static unsigned int io_serial_in(struct uart_port *p, int offset)
427 offset = offset << p->regshift;
428 return inb(p->iobase + offset);
431 static void io_serial_out(struct uart_port *p, int offset, int value)
433 offset = offset << p->regshift;
434 outb(value, p->iobase + offset);
437 static int serial8250_default_handle_irq(struct uart_port *port);
438 static int exar_handle_irq(struct uart_port *port);
440 static void set_io_from_upio(struct uart_port *p)
442 struct uart_8250_port *up =
443 container_of(p, struct uart_8250_port, port);
445 up->dl_read = default_serial_dl_read;
446 up->dl_write = default_serial_dl_write;
450 p->serial_in = hub6_serial_in;
451 p->serial_out = hub6_serial_out;
455 p->serial_in = mem_serial_in;
456 p->serial_out = mem_serial_out;
460 p->serial_in = mem32_serial_in;
461 p->serial_out = mem32_serial_out;
464 #if defined(CONFIG_MIPS_ALCHEMY) || defined(CONFIG_SERIAL_8250_RT288X)
466 p->serial_in = au_serial_in;
467 p->serial_out = au_serial_out;
468 up->dl_read = au_serial_dl_read;
469 up->dl_write = au_serial_dl_write;
474 p->serial_in = io_serial_in;
475 p->serial_out = io_serial_out;
478 /* Remember loaded iotype */
479 up->cur_iotype = p->iotype;
480 p->handle_irq = serial8250_default_handle_irq;
484 serial_port_out_sync(struct uart_port *p, int offset, int value)
490 p->serial_out(p, offset, value);
491 p->serial_in(p, UART_LCR); /* safe, no side-effects */
494 p->serial_out(p, offset, value);
501 static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
503 serial_out(up, UART_SCR, offset);
504 serial_out(up, UART_ICR, value);
507 static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
511 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
512 serial_out(up, UART_SCR, offset);
513 value = serial_in(up, UART_ICR);
514 serial_icr_write(up, UART_ACR, up->acr);
522 static void serial8250_clear_fifos(struct uart_8250_port *p)
524 if (p->capabilities & UART_CAP_FIFO) {
525 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO);
526 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO |
527 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
528 serial_out(p, UART_FCR, 0);
532 void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p)
536 serial8250_clear_fifos(p);
537 fcr = uart_config[p->port.type].fcr;
538 serial_out(p, UART_FCR, fcr);
540 EXPORT_SYMBOL_GPL(serial8250_clear_and_reinit_fifos);
543 * IER sleep support. UARTs which have EFRs need the "extended
544 * capability" bit enabled. Note that on XR16C850s, we need to
545 * reset LCR to write to IER.
547 static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
550 * Exar UARTs have a SLEEP register that enables or disables
551 * each UART to enter sleep mode separately. On the XR17V35x the
552 * register is accessible to each UART at the UART_EXAR_SLEEP
553 * offset but the UART channel may only write to the corresponding
556 if ((p->port.type == PORT_XR17V35X) ||
557 (p->port.type == PORT_XR17D15X)) {
558 serial_out(p, UART_EXAR_SLEEP, 0xff);
562 if (p->capabilities & UART_CAP_SLEEP) {
563 if (p->capabilities & UART_CAP_EFR) {
564 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
565 serial_out(p, UART_EFR, UART_EFR_ECB);
566 serial_out(p, UART_LCR, 0);
568 serial_out(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
569 if (p->capabilities & UART_CAP_EFR) {
570 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
571 serial_out(p, UART_EFR, 0);
572 serial_out(p, UART_LCR, 0);
577 #ifdef CONFIG_SERIAL_8250_RSA
579 * Attempts to turn on the RSA FIFO. Returns zero on failure.
580 * We set the port uart clock rate if we succeed.
582 static int __enable_rsa(struct uart_8250_port *up)
587 mode = serial_in(up, UART_RSA_MSR);
588 result = mode & UART_RSA_MSR_FIFO;
591 serial_out(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
592 mode = serial_in(up, UART_RSA_MSR);
593 result = mode & UART_RSA_MSR_FIFO;
597 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
602 static void enable_rsa(struct uart_8250_port *up)
604 if (up->port.type == PORT_RSA) {
605 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
606 spin_lock_irq(&up->port.lock);
608 spin_unlock_irq(&up->port.lock);
610 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
611 serial_out(up, UART_RSA_FRR, 0);
616 * Attempts to turn off the RSA FIFO. Returns zero on failure.
617 * It is unknown why interrupts were disabled in here. However,
618 * the caller is expected to preserve this behaviour by grabbing
619 * the spinlock before calling this function.
621 static void disable_rsa(struct uart_8250_port *up)
626 if (up->port.type == PORT_RSA &&
627 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
628 spin_lock_irq(&up->port.lock);
630 mode = serial_in(up, UART_RSA_MSR);
631 result = !(mode & UART_RSA_MSR_FIFO);
634 serial_out(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
635 mode = serial_in(up, UART_RSA_MSR);
636 result = !(mode & UART_RSA_MSR_FIFO);
640 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
641 spin_unlock_irq(&up->port.lock);
644 #endif /* CONFIG_SERIAL_8250_RSA */
647 * This is a quickie test to see how big the FIFO is.
648 * It doesn't work at all the time, more's the pity.
650 static int size_fifo(struct uart_8250_port *up)
652 unsigned char old_fcr, old_mcr, old_lcr;
653 unsigned short old_dl;
656 old_lcr = serial_in(up, UART_LCR);
657 serial_out(up, UART_LCR, 0);
658 old_fcr = serial_in(up, UART_FCR);
659 old_mcr = serial_in(up, UART_MCR);
660 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
661 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
662 serial_out(up, UART_MCR, UART_MCR_LOOP);
663 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
664 old_dl = serial_dl_read(up);
665 serial_dl_write(up, 0x0001);
666 serial_out(up, UART_LCR, 0x03);
667 for (count = 0; count < 256; count++)
668 serial_out(up, UART_TX, count);
669 mdelay(20);/* FIXME - schedule_timeout */
670 for (count = 0; (serial_in(up, UART_LSR) & UART_LSR_DR) &&
671 (count < 256); count++)
672 serial_in(up, UART_RX);
673 serial_out(up, UART_FCR, old_fcr);
674 serial_out(up, UART_MCR, old_mcr);
675 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
676 serial_dl_write(up, old_dl);
677 serial_out(up, UART_LCR, old_lcr);
683 * Read UART ID using the divisor method - set DLL and DLM to zero
684 * and the revision will be in DLL and device type in DLM. We
685 * preserve the device state across this.
687 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
689 unsigned char old_dll, old_dlm, old_lcr;
692 old_lcr = serial_in(p, UART_LCR);
693 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_A);
695 old_dll = serial_in(p, UART_DLL);
696 old_dlm = serial_in(p, UART_DLM);
698 serial_out(p, UART_DLL, 0);
699 serial_out(p, UART_DLM, 0);
701 id = serial_in(p, UART_DLL) | serial_in(p, UART_DLM) << 8;
703 serial_out(p, UART_DLL, old_dll);
704 serial_out(p, UART_DLM, old_dlm);
705 serial_out(p, UART_LCR, old_lcr);
711 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
712 * When this function is called we know it is at least a StarTech
713 * 16650 V2, but it might be one of several StarTech UARTs, or one of
714 * its clones. (We treat the broken original StarTech 16650 V1 as a
715 * 16550, and why not? Startech doesn't seem to even acknowledge its
718 * What evil have men's minds wrought...
720 static void autoconfig_has_efr(struct uart_8250_port *up)
722 unsigned int id1, id2, id3, rev;
725 * Everything with an EFR has SLEEP
727 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
730 * First we check to see if it's an Oxford Semiconductor UART.
732 * If we have to do this here because some non-National
733 * Semiconductor clone chips lock up if you try writing to the
734 * LSR register (which serial_icr_read does)
738 * Check for Oxford Semiconductor 16C950.
740 * EFR [4] must be set else this test fails.
742 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
743 * claims that it's needed for 952 dual UART's (which are not
744 * recommended for new designs).
747 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
748 serial_out(up, UART_EFR, UART_EFR_ECB);
749 serial_out(up, UART_LCR, 0x00);
750 id1 = serial_icr_read(up, UART_ID1);
751 id2 = serial_icr_read(up, UART_ID2);
752 id3 = serial_icr_read(up, UART_ID3);
753 rev = serial_icr_read(up, UART_REV);
755 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
757 if (id1 == 0x16 && id2 == 0xC9 &&
758 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
759 up->port.type = PORT_16C950;
762 * Enable work around for the Oxford Semiconductor 952 rev B
763 * chip which causes it to seriously miscalculate baud rates
766 if (id3 == 0x52 && rev == 0x01)
767 up->bugs |= UART_BUG_QUOT;
772 * We check for a XR16C850 by setting DLL and DLM to 0, and then
773 * reading back DLL and DLM. The chip type depends on the DLM
775 * 0x10 - XR16C850 and the DLL contains the chip revision.
779 id1 = autoconfig_read_divisor_id(up);
780 DEBUG_AUTOCONF("850id=%04x ", id1);
783 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
784 up->port.type = PORT_16850;
789 * It wasn't an XR16C850.
791 * We distinguish between the '654 and the '650 by counting
792 * how many bytes are in the FIFO. I'm using this for now,
793 * since that's the technique that was sent to me in the
794 * serial driver update, but I'm not convinced this works.
795 * I've had problems doing this in the past. -TYT
797 if (size_fifo(up) == 64)
798 up->port.type = PORT_16654;
800 up->port.type = PORT_16650V2;
804 * We detected a chip without a FIFO. Only two fall into
805 * this category - the original 8250 and the 16450. The
806 * 16450 has a scratch register (accessible with LCR=0)
808 static void autoconfig_8250(struct uart_8250_port *up)
810 unsigned char scratch, status1, status2;
812 up->port.type = PORT_8250;
814 scratch = serial_in(up, UART_SCR);
815 serial_out(up, UART_SCR, 0xa5);
816 status1 = serial_in(up, UART_SCR);
817 serial_out(up, UART_SCR, 0x5a);
818 status2 = serial_in(up, UART_SCR);
819 serial_out(up, UART_SCR, scratch);
821 if (status1 == 0xa5 && status2 == 0x5a)
822 up->port.type = PORT_16450;
825 static int broken_efr(struct uart_8250_port *up)
828 * Exar ST16C2550 "A2" devices incorrectly detect as
829 * having an EFR, and report an ID of 0x0201. See
830 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
832 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
838 static inline int ns16550a_goto_highspeed(struct uart_8250_port *up)
840 unsigned char status;
842 status = serial_in(up, 0x04); /* EXCR2 */
843 #define PRESL(x) ((x) & 0x30)
844 if (PRESL(status) == 0x10) {
845 /* already in high speed mode */
848 status &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
849 status |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
850 serial_out(up, 0x04, status);
856 * We know that the chip has FIFOs. Does it have an EFR? The
857 * EFR is located in the same register position as the IIR and
858 * we know the top two bits of the IIR are currently set. The
859 * EFR should contain zero. Try to read the EFR.
861 static void autoconfig_16550a(struct uart_8250_port *up)
863 unsigned char status1, status2;
864 unsigned int iersave;
866 up->port.type = PORT_16550A;
867 up->capabilities |= UART_CAP_FIFO;
870 * XR17V35x UARTs have an extra divisor register, DLD
871 * that gets enabled with when DLAB is set which will
872 * cause the device to incorrectly match and assign
873 * port type to PORT_16650. The EFR for this UART is
874 * found at offset 0x09. Instead check the Deice ID (DVID)
875 * register for a 2, 4 or 8 port UART.
877 if (up->port.flags & UPF_EXAR_EFR) {
878 status1 = serial_in(up, UART_EXAR_DVID);
879 if (status1 == 0x82 || status1 == 0x84 || status1 == 0x88) {
880 DEBUG_AUTOCONF("Exar XR17V35x ");
881 up->port.type = PORT_XR17V35X;
882 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR |
891 * Check for presence of the EFR when DLAB is set.
892 * Only ST16C650V1 UARTs pass this test.
894 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
895 if (serial_in(up, UART_EFR) == 0) {
896 serial_out(up, UART_EFR, 0xA8);
897 if (serial_in(up, UART_EFR) != 0) {
898 DEBUG_AUTOCONF("EFRv1 ");
899 up->port.type = PORT_16650;
900 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
902 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
904 serial_out(up, UART_EFR, 0);
909 * Maybe it requires 0xbf to be written to the LCR.
910 * (other ST16C650V2 UARTs, TI16C752A, etc)
912 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
913 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
914 DEBUG_AUTOCONF("EFRv2 ");
915 autoconfig_has_efr(up);
920 * Check for a National Semiconductor SuperIO chip.
921 * Attempt to switch to bank 2, read the value of the LOOP bit
922 * from EXCR1. Switch back to bank 0, change it in MCR. Then
923 * switch back to bank 2, read it from EXCR1 again and check
924 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
926 serial_out(up, UART_LCR, 0);
927 status1 = serial_in(up, UART_MCR);
928 serial_out(up, UART_LCR, 0xE0);
929 status2 = serial_in(up, 0x02); /* EXCR1 */
931 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
932 serial_out(up, UART_LCR, 0);
933 serial_out(up, UART_MCR, status1 ^ UART_MCR_LOOP);
934 serial_out(up, UART_LCR, 0xE0);
935 status2 = serial_in(up, 0x02); /* EXCR1 */
936 serial_out(up, UART_LCR, 0);
937 serial_out(up, UART_MCR, status1);
939 if ((status2 ^ status1) & UART_MCR_LOOP) {
942 serial_out(up, UART_LCR, 0xE0);
944 quot = serial_dl_read(up);
947 if (ns16550a_goto_highspeed(up))
948 serial_dl_write(up, quot);
950 serial_out(up, UART_LCR, 0);
952 up->port.uartclk = 921600*16;
953 up->port.type = PORT_NS16550A;
954 up->capabilities |= UART_NATSEMI;
960 * No EFR. Try to detect a TI16750, which only sets bit 5 of
961 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
962 * Try setting it with and without DLAB set. Cheap clones
963 * set bit 5 without DLAB set.
965 serial_out(up, UART_LCR, 0);
966 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
967 status1 = serial_in(up, UART_IIR) >> 5;
968 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
969 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
970 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
971 status2 = serial_in(up, UART_IIR) >> 5;
972 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
973 serial_out(up, UART_LCR, 0);
975 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
977 if (status1 == 6 && status2 == 7) {
978 up->port.type = PORT_16750;
979 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
984 * Try writing and reading the UART_IER_UUE bit (b6).
985 * If it works, this is probably one of the Xscale platform's
987 * We're going to explicitly set the UUE bit to 0 before
988 * trying to write and read a 1 just to make sure it's not
989 * already a 1 and maybe locked there before we even start start.
991 iersave = serial_in(up, UART_IER);
992 serial_out(up, UART_IER, iersave & ~UART_IER_UUE);
993 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
995 * OK it's in a known zero state, try writing and reading
996 * without disturbing the current state of the other bits.
998 serial_out(up, UART_IER, iersave | UART_IER_UUE);
999 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1002 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1004 DEBUG_AUTOCONF("Xscale ");
1005 up->port.type = PORT_XSCALE;
1006 up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1011 * If we got here we couldn't force the IER_UUE bit to 0.
1012 * Log it and continue.
1014 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1016 serial_out(up, UART_IER, iersave);
1019 * Exar uarts have EFR in a weird location
1021 if (up->port.flags & UPF_EXAR_EFR) {
1022 DEBUG_AUTOCONF("Exar XR17D15x ");
1023 up->port.type = PORT_XR17D15X;
1024 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR |
1031 * We distinguish between 16550A and U6 16550A by counting
1032 * how many bytes are in the FIFO.
1034 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1035 up->port.type = PORT_U6_16550A;
1036 up->capabilities |= UART_CAP_AFE;
1041 * This routine is called by rs_init() to initialize a specific serial
1042 * port. It determines what type of UART chip this serial port is
1043 * using: 8250, 16450, 16550, 16550A. The important question is
1044 * whether or not this UART is a 16550A or not, since this will
1045 * determine whether or not we can use its FIFO features or not.
1047 static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
1049 unsigned char status1, scratch, scratch2, scratch3;
1050 unsigned char save_lcr, save_mcr;
1051 struct uart_port *port = &up->port;
1052 unsigned long flags;
1053 unsigned int old_capabilities;
1055 if (!port->iobase && !port->mapbase && !port->membase)
1058 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ",
1059 serial_index(port), port->iobase, port->membase);
1062 * We really do need global IRQs disabled here - we're going to
1063 * be frobbing the chips IRQ enable register to see if it exists.
1065 spin_lock_irqsave(&port->lock, flags);
1067 up->capabilities = 0;
1070 if (!(port->flags & UPF_BUGGY_UART)) {
1072 * Do a simple existence test first; if we fail this,
1073 * there's no point trying anything else.
1075 * 0x80 is used as a nonsense port to prevent against
1076 * false positives due to ISA bus float. The
1077 * assumption is that 0x80 is a non-existent port;
1078 * which should be safe since include/asm/io.h also
1079 * makes this assumption.
1081 * Note: this is safe as long as MCR bit 4 is clear
1082 * and the device is in "PC" mode.
1084 scratch = serial_in(up, UART_IER);
1085 serial_out(up, UART_IER, 0);
1090 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1091 * 16C754B) allow only to modify them if an EFR bit is set.
1093 scratch2 = serial_in(up, UART_IER) & 0x0f;
1094 serial_out(up, UART_IER, 0x0F);
1098 scratch3 = serial_in(up, UART_IER) & 0x0f;
1099 serial_out(up, UART_IER, scratch);
1100 if (scratch2 != 0 || scratch3 != 0x0F) {
1102 * We failed; there's nothing here
1104 spin_unlock_irqrestore(&port->lock, flags);
1105 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1106 scratch2, scratch3);
1111 save_mcr = serial_in(up, UART_MCR);
1112 save_lcr = serial_in(up, UART_LCR);
1115 * Check to see if a UART is really there. Certain broken
1116 * internal modems based on the Rockwell chipset fail this
1117 * test, because they apparently don't implement the loopback
1118 * test mode. So this test is skipped on the COM 1 through
1119 * COM 4 ports. This *should* be safe, since no board
1120 * manufacturer would be stupid enough to design a board
1121 * that conflicts with COM 1-4 --- we hope!
1123 if (!(port->flags & UPF_SKIP_TEST)) {
1124 serial_out(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1125 status1 = serial_in(up, UART_MSR) & 0xF0;
1126 serial_out(up, UART_MCR, save_mcr);
1127 if (status1 != 0x90) {
1128 spin_unlock_irqrestore(&port->lock, flags);
1129 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1136 * We're pretty sure there's a port here. Lets find out what
1137 * type of port it is. The IIR top two bits allows us to find
1138 * out if it's 8250 or 16450, 16550, 16550A or later. This
1139 * determines what we test for next.
1141 * We also initialise the EFR (if any) to zero for later. The
1142 * EFR occupies the same register location as the FCR and IIR.
1144 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1145 serial_out(up, UART_EFR, 0);
1146 serial_out(up, UART_LCR, 0);
1148 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1149 scratch = serial_in(up, UART_IIR) >> 6;
1153 autoconfig_8250(up);
1156 port->type = PORT_UNKNOWN;
1159 port->type = PORT_16550;
1162 autoconfig_16550a(up);
1166 #ifdef CONFIG_SERIAL_8250_RSA
1168 * Only probe for RSA ports if we got the region.
1170 if (port->type == PORT_16550A && probeflags & PROBE_RSA) {
1173 for (i = 0 ; i < probe_rsa_count; ++i) {
1174 if (probe_rsa[i] == port->iobase && __enable_rsa(up)) {
1175 port->type = PORT_RSA;
1182 serial_out(up, UART_LCR, save_lcr);
1184 port->fifosize = uart_config[up->port.type].fifo_size;
1185 old_capabilities = up->capabilities;
1186 up->capabilities = uart_config[port->type].flags;
1187 up->tx_loadsz = uart_config[port->type].tx_loadsz;
1189 if (port->type == PORT_UNKNOWN)
1195 #ifdef CONFIG_SERIAL_8250_RSA
1196 if (port->type == PORT_RSA)
1197 serial_out(up, UART_RSA_FRR, 0);
1199 serial_out(up, UART_MCR, save_mcr);
1200 serial8250_clear_fifos(up);
1201 serial_in(up, UART_RX);
1202 if (up->capabilities & UART_CAP_UUE)
1203 serial_out(up, UART_IER, UART_IER_UUE);
1205 serial_out(up, UART_IER, 0);
1208 spin_unlock_irqrestore(&port->lock, flags);
1209 if (up->capabilities != old_capabilities) {
1211 "ttyS%d: detected caps %08x should be %08x\n",
1212 serial_index(port), old_capabilities,
1216 DEBUG_AUTOCONF("iir=%d ", scratch);
1217 DEBUG_AUTOCONF("type=%s\n", uart_config[port->type].name);
1220 static void autoconfig_irq(struct uart_8250_port *up)
1222 struct uart_port *port = &up->port;
1223 unsigned char save_mcr, save_ier;
1224 unsigned char save_ICP = 0;
1225 unsigned int ICP = 0;
1229 if (port->flags & UPF_FOURPORT) {
1230 ICP = (port->iobase & 0xfe0) | 0x1f;
1231 save_ICP = inb_p(ICP);
1236 /* forget possible initially masked and pending IRQ */
1237 probe_irq_off(probe_irq_on());
1238 save_mcr = serial_in(up, UART_MCR);
1239 save_ier = serial_in(up, UART_IER);
1240 serial_out(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
1242 irqs = probe_irq_on();
1243 serial_out(up, UART_MCR, 0);
1245 if (port->flags & UPF_FOURPORT) {
1246 serial_out(up, UART_MCR,
1247 UART_MCR_DTR | UART_MCR_RTS);
1249 serial_out(up, UART_MCR,
1250 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1252 serial_out(up, UART_IER, 0x0f); /* enable all intrs */
1253 serial_in(up, UART_LSR);
1254 serial_in(up, UART_RX);
1255 serial_in(up, UART_IIR);
1256 serial_in(up, UART_MSR);
1257 serial_out(up, UART_TX, 0xFF);
1259 irq = probe_irq_off(irqs);
1261 serial_out(up, UART_MCR, save_mcr);
1262 serial_out(up, UART_IER, save_ier);
1264 if (port->flags & UPF_FOURPORT)
1265 outb_p(save_ICP, ICP);
1267 port->irq = (irq > 0) ? irq : 0;
1270 static inline void __stop_tx(struct uart_8250_port *p)
1272 if (p->ier & UART_IER_THRI) {
1273 p->ier &= ~UART_IER_THRI;
1274 serial_out(p, UART_IER, p->ier);
1278 static void serial8250_stop_tx(struct uart_port *port)
1280 struct uart_8250_port *up =
1281 container_of(port, struct uart_8250_port, port);
1286 * We really want to stop the transmitter from sending.
1288 if (port->type == PORT_16C950) {
1289 up->acr |= UART_ACR_TXDIS;
1290 serial_icr_write(up, UART_ACR, up->acr);
1294 static void serial8250_start_tx(struct uart_port *port)
1296 struct uart_8250_port *up =
1297 container_of(port, struct uart_8250_port, port);
1299 if (up->dma && !serial8250_tx_dma(up)) {
1301 } else if (!(up->ier & UART_IER_THRI)) {
1302 up->ier |= UART_IER_THRI;
1303 serial_port_out(port, UART_IER, up->ier);
1305 if (up->bugs & UART_BUG_TXEN) {
1307 lsr = serial_in(up, UART_LSR);
1308 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1309 if (lsr & UART_LSR_TEMT)
1310 serial8250_tx_chars(up);
1315 * Re-enable the transmitter if we disabled it.
1317 if (port->type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1318 up->acr &= ~UART_ACR_TXDIS;
1319 serial_icr_write(up, UART_ACR, up->acr);
1323 static void serial8250_stop_rx(struct uart_port *port)
1325 struct uart_8250_port *up =
1326 container_of(port, struct uart_8250_port, port);
1328 up->ier &= ~UART_IER_RLSI;
1329 up->port.read_status_mask &= ~UART_LSR_DR;
1330 serial_port_out(port, UART_IER, up->ier);
1333 static void serial8250_enable_ms(struct uart_port *port)
1335 struct uart_8250_port *up =
1336 container_of(port, struct uart_8250_port, port);
1338 /* no MSR capabilities */
1339 if (up->bugs & UART_BUG_NOMSR)
1342 up->ier |= UART_IER_MSI;
1343 serial_port_out(port, UART_IER, up->ier);
1347 * serial8250_rx_chars: processes according to the passed in LSR
1348 * value, and returns the remaining LSR bits not handled
1349 * by this Rx routine.
1352 serial8250_rx_chars(struct uart_8250_port *up, unsigned char lsr)
1354 struct uart_port *port = &up->port;
1356 int max_count = 256;
1360 if (likely(lsr & UART_LSR_DR))
1361 ch = serial_in(up, UART_RX);
1364 * Intel 82571 has a Serial Over Lan device that will
1365 * set UART_LSR_BI without setting UART_LSR_DR when
1366 * it receives a break. To avoid reading from the
1367 * receive buffer without UART_LSR_DR bit set, we
1368 * just force the read character to be 0
1375 lsr |= up->lsr_saved_flags;
1376 up->lsr_saved_flags = 0;
1378 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1379 if (lsr & UART_LSR_BI) {
1380 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1383 * We do the SysRQ and SAK checking
1384 * here because otherwise the break
1385 * may get masked by ignore_status_mask
1386 * or read_status_mask.
1388 if (uart_handle_break(port))
1390 } else if (lsr & UART_LSR_PE)
1391 port->icount.parity++;
1392 else if (lsr & UART_LSR_FE)
1393 port->icount.frame++;
1394 if (lsr & UART_LSR_OE)
1395 port->icount.overrun++;
1398 * Mask off conditions which should be ignored.
1400 lsr &= port->read_status_mask;
1402 if (lsr & UART_LSR_BI) {
1403 DEBUG_INTR("handling break....");
1405 } else if (lsr & UART_LSR_PE)
1407 else if (lsr & UART_LSR_FE)
1410 if (uart_handle_sysrq_char(port, ch))
1413 uart_insert_char(port, lsr, UART_LSR_OE, ch, flag);
1416 lsr = serial_in(up, UART_LSR);
1417 } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));
1418 spin_unlock(&port->lock);
1419 tty_flip_buffer_push(&port->state->port);
1420 spin_lock(&port->lock);
1423 EXPORT_SYMBOL_GPL(serial8250_rx_chars);
1425 void serial8250_tx_chars(struct uart_8250_port *up)
1427 struct uart_port *port = &up->port;
1428 struct circ_buf *xmit = &port->state->xmit;
1432 serial_out(up, UART_TX, port->x_char);
1437 if (uart_tx_stopped(port)) {
1438 serial8250_stop_tx(port);
1441 if (uart_circ_empty(xmit)) {
1446 count = up->tx_loadsz;
1448 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1449 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1451 if (uart_circ_empty(xmit))
1453 if (up->capabilities & UART_CAP_HFIFO) {
1454 if ((serial_port_in(port, UART_LSR) & BOTH_EMPTY) !=
1458 } while (--count > 0);
1460 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1461 uart_write_wakeup(port);
1463 DEBUG_INTR("THRE...");
1465 if (uart_circ_empty(xmit))
1468 EXPORT_SYMBOL_GPL(serial8250_tx_chars);
1470 unsigned int serial8250_modem_status(struct uart_8250_port *up)
1472 struct uart_port *port = &up->port;
1473 unsigned int status = serial_in(up, UART_MSR);
1475 status |= up->msr_saved_flags;
1476 up->msr_saved_flags = 0;
1477 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1478 port->state != NULL) {
1479 if (status & UART_MSR_TERI)
1481 if (status & UART_MSR_DDSR)
1483 if (status & UART_MSR_DDCD)
1484 uart_handle_dcd_change(port, status & UART_MSR_DCD);
1485 if (status & UART_MSR_DCTS)
1486 uart_handle_cts_change(port, status & UART_MSR_CTS);
1488 wake_up_interruptible(&port->state->port.delta_msr_wait);
1493 EXPORT_SYMBOL_GPL(serial8250_modem_status);
1496 * This handles the interrupt from one port.
1498 int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1500 unsigned char status;
1501 unsigned long flags;
1502 struct uart_8250_port *up =
1503 container_of(port, struct uart_8250_port, port);
1506 if (iir & UART_IIR_NO_INT)
1509 spin_lock_irqsave(&port->lock, flags);
1511 status = serial_port_in(port, UART_LSR);
1513 DEBUG_INTR("status = %x...", status);
1515 if (status & (UART_LSR_DR | UART_LSR_BI)) {
1517 dma_err = serial8250_rx_dma(up, iir);
1519 if (!up->dma || dma_err)
1520 status = serial8250_rx_chars(up, status);
1522 serial8250_modem_status(up);
1523 if (status & UART_LSR_THRE)
1524 serial8250_tx_chars(up);
1526 spin_unlock_irqrestore(&port->lock, flags);
1529 EXPORT_SYMBOL_GPL(serial8250_handle_irq);
1531 static int serial8250_default_handle_irq(struct uart_port *port)
1533 unsigned int iir = serial_port_in(port, UART_IIR);
1535 return serial8250_handle_irq(port, iir);
1539 * These Exar UARTs have an extra interrupt indicator that could
1540 * fire for a few unimplemented interrupts. One of which is a
1541 * wakeup event when coming out of sleep. Put this here just
1542 * to be on the safe side that these interrupts don't go unhandled.
1544 static int exar_handle_irq(struct uart_port *port)
1546 unsigned char int0, int1, int2, int3;
1547 unsigned int iir = serial_port_in(port, UART_IIR);
1550 ret = serial8250_handle_irq(port, iir);
1552 if ((port->type == PORT_XR17V35X) ||
1553 (port->type == PORT_XR17D15X)) {
1554 int0 = serial_port_in(port, 0x80);
1555 int1 = serial_port_in(port, 0x81);
1556 int2 = serial_port_in(port, 0x82);
1557 int3 = serial_port_in(port, 0x83);
1564 * This is the serial driver's interrupt routine.
1566 * Arjan thinks the old way was overly complex, so it got simplified.
1567 * Alan disagrees, saying that need the complexity to handle the weird
1568 * nature of ISA shared interrupts. (This is a special exception.)
1570 * In order to handle ISA shared interrupts properly, we need to check
1571 * that all ports have been serviced, and therefore the ISA interrupt
1572 * line has been de-asserted.
1574 * This means we need to loop through all ports. checking that they
1575 * don't have an interrupt pending.
1577 static irqreturn_t serial8250_interrupt(int irq, void *dev_id)
1579 struct irq_info *i = dev_id;
1580 struct list_head *l, *end = NULL;
1581 int pass_counter = 0, handled = 0;
1583 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1585 spin_lock(&i->lock);
1589 struct uart_8250_port *up;
1590 struct uart_port *port;
1592 up = list_entry(l, struct uart_8250_port, list);
1595 if (port->handle_irq(port)) {
1598 } else if (end == NULL)
1603 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1604 /* If we hit this, we're dead. */
1605 printk_ratelimited(KERN_ERR
1606 "serial8250: too much work for irq%d\n", irq);
1611 spin_unlock(&i->lock);
1613 DEBUG_INTR("end.\n");
1615 return IRQ_RETVAL(handled);
1619 * To support ISA shared interrupts, we need to have one interrupt
1620 * handler that ensures that the IRQ line has been deasserted
1621 * before returning. Failing to do this will result in the IRQ
1622 * line being stuck active, and, since ISA irqs are edge triggered,
1623 * no more IRQs will be seen.
1625 static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1627 spin_lock_irq(&i->lock);
1629 if (!list_empty(i->head)) {
1630 if (i->head == &up->list)
1631 i->head = i->head->next;
1632 list_del(&up->list);
1634 BUG_ON(i->head != &up->list);
1637 spin_unlock_irq(&i->lock);
1638 /* List empty so throw away the hash node */
1639 if (i->head == NULL) {
1640 hlist_del(&i->node);
1645 static int serial_link_irq_chain(struct uart_8250_port *up)
1647 struct hlist_head *h;
1648 struct hlist_node *n;
1650 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
1652 mutex_lock(&hash_mutex);
1654 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1656 hlist_for_each(n, h) {
1657 i = hlist_entry(n, struct irq_info, node);
1658 if (i->irq == up->port.irq)
1663 i = kzalloc(sizeof(struct irq_info), GFP_KERNEL);
1665 mutex_unlock(&hash_mutex);
1668 spin_lock_init(&i->lock);
1669 i->irq = up->port.irq;
1670 hlist_add_head(&i->node, h);
1672 mutex_unlock(&hash_mutex);
1674 spin_lock_irq(&i->lock);
1677 list_add(&up->list, i->head);
1678 spin_unlock_irq(&i->lock);
1682 INIT_LIST_HEAD(&up->list);
1683 i->head = &up->list;
1684 spin_unlock_irq(&i->lock);
1685 irq_flags |= up->port.irqflags;
1686 ret = request_irq(up->port.irq, serial8250_interrupt,
1687 irq_flags, "serial", i);
1689 serial_do_unlink(i, up);
1695 static void serial_unlink_irq_chain(struct uart_8250_port *up)
1698 struct hlist_node *n;
1699 struct hlist_head *h;
1701 mutex_lock(&hash_mutex);
1703 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1705 hlist_for_each(n, h) {
1706 i = hlist_entry(n, struct irq_info, node);
1707 if (i->irq == up->port.irq)
1712 BUG_ON(i->head == NULL);
1714 if (list_empty(i->head))
1715 free_irq(up->port.irq, i);
1717 serial_do_unlink(i, up);
1718 mutex_unlock(&hash_mutex);
1722 * This function is used to handle ports that do not have an
1723 * interrupt. This doesn't work very well for 16450's, but gives
1724 * barely passable results for a 16550A. (Although at the expense
1725 * of much CPU overhead).
1727 static void serial8250_timeout(unsigned long data)
1729 struct uart_8250_port *up = (struct uart_8250_port *)data;
1731 up->port.handle_irq(&up->port);
1732 mod_timer(&up->timer, jiffies + uart_poll_timeout(&up->port));
1735 static void serial8250_backup_timeout(unsigned long data)
1737 struct uart_8250_port *up = (struct uart_8250_port *)data;
1738 unsigned int iir, ier = 0, lsr;
1739 unsigned long flags;
1741 spin_lock_irqsave(&up->port.lock, flags);
1744 * Must disable interrupts or else we risk racing with the interrupt
1748 ier = serial_in(up, UART_IER);
1749 serial_out(up, UART_IER, 0);
1752 iir = serial_in(up, UART_IIR);
1755 * This should be a safe test for anyone who doesn't trust the
1756 * IIR bits on their UART, but it's specifically designed for
1757 * the "Diva" UART used on the management processor on many HP
1758 * ia64 and parisc boxes.
1760 lsr = serial_in(up, UART_LSR);
1761 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1762 if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) &&
1763 (!uart_circ_empty(&up->port.state->xmit) || up->port.x_char) &&
1764 (lsr & UART_LSR_THRE)) {
1765 iir &= ~(UART_IIR_ID | UART_IIR_NO_INT);
1766 iir |= UART_IIR_THRI;
1769 if (!(iir & UART_IIR_NO_INT))
1770 serial8250_tx_chars(up);
1773 serial_out(up, UART_IER, ier);
1775 spin_unlock_irqrestore(&up->port.lock, flags);
1777 /* Standard timer interval plus 0.2s to keep the port running */
1778 mod_timer(&up->timer,
1779 jiffies + uart_poll_timeout(&up->port) + HZ / 5);
1782 static unsigned int serial8250_tx_empty(struct uart_port *port)
1784 struct uart_8250_port *up =
1785 container_of(port, struct uart_8250_port, port);
1786 unsigned long flags;
1789 spin_lock_irqsave(&port->lock, flags);
1790 lsr = serial_port_in(port, UART_LSR);
1791 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1792 spin_unlock_irqrestore(&port->lock, flags);
1794 return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1797 static unsigned int serial8250_get_mctrl(struct uart_port *port)
1799 struct uart_8250_port *up =
1800 container_of(port, struct uart_8250_port, port);
1801 unsigned int status;
1804 status = serial8250_modem_status(up);
1807 if (status & UART_MSR_DCD)
1809 if (status & UART_MSR_RI)
1811 if (status & UART_MSR_DSR)
1813 if (status & UART_MSR_CTS)
1818 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1820 struct uart_8250_port *up =
1821 container_of(port, struct uart_8250_port, port);
1822 unsigned char mcr = 0;
1824 if (mctrl & TIOCM_RTS)
1825 mcr |= UART_MCR_RTS;
1826 if (mctrl & TIOCM_DTR)
1827 mcr |= UART_MCR_DTR;
1828 if (mctrl & TIOCM_OUT1)
1829 mcr |= UART_MCR_OUT1;
1830 if (mctrl & TIOCM_OUT2)
1831 mcr |= UART_MCR_OUT2;
1832 if (mctrl & TIOCM_LOOP)
1833 mcr |= UART_MCR_LOOP;
1835 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1837 serial_port_out(port, UART_MCR, mcr);
1840 static void serial8250_break_ctl(struct uart_port *port, int break_state)
1842 struct uart_8250_port *up =
1843 container_of(port, struct uart_8250_port, port);
1844 unsigned long flags;
1846 spin_lock_irqsave(&port->lock, flags);
1847 if (break_state == -1)
1848 up->lcr |= UART_LCR_SBC;
1850 up->lcr &= ~UART_LCR_SBC;
1851 serial_port_out(port, UART_LCR, up->lcr);
1852 spin_unlock_irqrestore(&port->lock, flags);
1856 * Wait for transmitter & holding register to empty
1858 static void wait_for_xmitr(struct uart_8250_port *up, int bits)
1860 unsigned int status, tmout = 10000;
1862 /* Wait up to 10ms for the character(s) to be sent. */
1864 status = serial_in(up, UART_LSR);
1866 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
1868 if ((status & bits) == bits)
1875 /* Wait up to 1s for flow control if necessary */
1876 if (up->port.flags & UPF_CONS_FLOW) {
1878 for (tmout = 1000000; tmout; tmout--) {
1879 unsigned int msr = serial_in(up, UART_MSR);
1880 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1881 if (msr & UART_MSR_CTS)
1884 touch_nmi_watchdog();
1889 #ifdef CONFIG_CONSOLE_POLL
1891 * Console polling routines for writing and reading from the uart while
1892 * in an interrupt or debug context.
1895 static int serial8250_get_poll_char(struct uart_port *port)
1897 unsigned char lsr = serial_port_in(port, UART_LSR);
1899 if (!(lsr & UART_LSR_DR))
1900 return NO_POLL_CHAR;
1902 return serial_port_in(port, UART_RX);
1906 static void serial8250_put_poll_char(struct uart_port *port,
1910 struct uart_8250_port *up =
1911 container_of(port, struct uart_8250_port, port);
1914 * First save the IER then disable the interrupts
1916 ier = serial_port_in(port, UART_IER);
1917 if (up->capabilities & UART_CAP_UUE)
1918 serial_port_out(port, UART_IER, UART_IER_UUE);
1920 serial_port_out(port, UART_IER, 0);
1922 wait_for_xmitr(up, BOTH_EMPTY);
1924 * Send the character out.
1925 * If a LF, also do CR...
1927 serial_port_out(port, UART_TX, c);
1929 wait_for_xmitr(up, BOTH_EMPTY);
1930 serial_port_out(port, UART_TX, 13);
1934 * Finally, wait for transmitter to become empty
1935 * and restore the IER
1937 wait_for_xmitr(up, BOTH_EMPTY);
1938 serial_port_out(port, UART_IER, ier);
1941 #endif /* CONFIG_CONSOLE_POLL */
1943 static int serial8250_startup(struct uart_port *port)
1945 struct uart_8250_port *up =
1946 container_of(port, struct uart_8250_port, port);
1947 unsigned long flags;
1948 unsigned char lsr, iir;
1951 if (port->type == PORT_8250_CIR)
1954 if (!port->fifosize)
1955 port->fifosize = uart_config[port->type].fifo_size;
1957 up->tx_loadsz = uart_config[port->type].tx_loadsz;
1958 if (!up->capabilities)
1959 up->capabilities = uart_config[port->type].flags;
1962 if (port->iotype != up->cur_iotype)
1963 set_io_from_upio(port);
1965 if (port->type == PORT_16C950) {
1966 /* Wake up and initialize UART */
1968 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
1969 serial_port_out(port, UART_EFR, UART_EFR_ECB);
1970 serial_port_out(port, UART_IER, 0);
1971 serial_port_out(port, UART_LCR, 0);
1972 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
1973 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
1974 serial_port_out(port, UART_EFR, UART_EFR_ECB);
1975 serial_port_out(port, UART_LCR, 0);
1978 #ifdef CONFIG_SERIAL_8250_RSA
1980 * If this is an RSA port, see if we can kick it up to the
1981 * higher speed clock.
1987 * Clear the FIFO buffers and disable them.
1988 * (they will be reenabled in set_termios())
1990 serial8250_clear_fifos(up);
1993 * Clear the interrupt registers.
1995 serial_port_in(port, UART_LSR);
1996 serial_port_in(port, UART_RX);
1997 serial_port_in(port, UART_IIR);
1998 serial_port_in(port, UART_MSR);
2001 * At this point, there's no way the LSR could still be 0xff;
2002 * if it is, then bail out, because there's likely no UART
2005 if (!(port->flags & UPF_BUGGY_UART) &&
2006 (serial_port_in(port, UART_LSR) == 0xff)) {
2007 printk_ratelimited(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
2008 serial_index(port));
2013 * For a XR16C850, we need to set the trigger levels
2015 if (port->type == PORT_16850) {
2018 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
2020 fctr = serial_in(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2021 serial_port_out(port, UART_FCTR,
2022 fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2023 serial_port_out(port, UART_TRG, UART_TRG_96);
2024 serial_port_out(port, UART_FCTR,
2025 fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2026 serial_port_out(port, UART_TRG, UART_TRG_96);
2028 serial_port_out(port, UART_LCR, 0);
2034 * Test for UARTs that do not reassert THRE when the
2035 * transmitter is idle and the interrupt has already
2036 * been cleared. Real 16550s should always reassert
2037 * this interrupt whenever the transmitter is idle and
2038 * the interrupt is enabled. Delays are necessary to
2039 * allow register changes to become visible.
2041 spin_lock_irqsave(&port->lock, flags);
2042 if (up->port.irqflags & IRQF_SHARED)
2043 disable_irq_nosync(port->irq);
2045 wait_for_xmitr(up, UART_LSR_THRE);
2046 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2047 udelay(1); /* allow THRE to set */
2048 iir1 = serial_port_in(port, UART_IIR);
2049 serial_port_out(port, UART_IER, 0);
2050 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2051 udelay(1); /* allow a working UART time to re-assert THRE */
2052 iir = serial_port_in(port, UART_IIR);
2053 serial_port_out(port, UART_IER, 0);
2055 if (port->irqflags & IRQF_SHARED)
2056 enable_irq(port->irq);
2057 spin_unlock_irqrestore(&port->lock, flags);
2060 * If the interrupt is not reasserted, or we otherwise
2061 * don't trust the iir, setup a timer to kick the UART
2062 * on a regular basis.
2064 if ((!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) ||
2065 up->port.flags & UPF_BUG_THRE) {
2066 up->bugs |= UART_BUG_THRE;
2067 pr_debug("ttyS%d - using backup timer\n",
2068 serial_index(port));
2073 * The above check will only give an accurate result the first time
2074 * the port is opened so this value needs to be preserved.
2076 if (up->bugs & UART_BUG_THRE) {
2077 up->timer.function = serial8250_backup_timeout;
2078 up->timer.data = (unsigned long)up;
2079 mod_timer(&up->timer, jiffies +
2080 uart_poll_timeout(port) + HZ / 5);
2084 * If the "interrupt" for this port doesn't correspond with any
2085 * hardware interrupt, we use a timer-based system. The original
2086 * driver used to do this with IRQ0.
2089 up->timer.data = (unsigned long)up;
2090 mod_timer(&up->timer, jiffies + uart_poll_timeout(port));
2092 retval = serial_link_irq_chain(up);
2098 * Now, initialize the UART
2100 serial_port_out(port, UART_LCR, UART_LCR_WLEN8);
2102 spin_lock_irqsave(&port->lock, flags);
2103 if (up->port.flags & UPF_FOURPORT) {
2105 up->port.mctrl |= TIOCM_OUT1;
2108 * Most PC uarts need OUT2 raised to enable interrupts.
2111 up->port.mctrl |= TIOCM_OUT2;
2113 serial8250_set_mctrl(port, port->mctrl);
2115 /* Serial over Lan (SoL) hack:
2116 Intel 8257x Gigabit ethernet chips have a
2117 16550 emulation, to be used for Serial Over Lan.
2118 Those chips take a longer time than a normal
2119 serial device to signalize that a transmission
2120 data was queued. Due to that, the above test generally
2121 fails. One solution would be to delay the reading of
2122 iir. However, this is not reliable, since the timeout
2123 is variable. So, let's just don't test if we receive
2124 TX irq. This way, we'll never enable UART_BUG_TXEN.
2126 if (skip_txen_test || up->port.flags & UPF_NO_TXEN_TEST)
2127 goto dont_test_tx_en;
2130 * Do a quick test to see if we receive an
2131 * interrupt when we enable the TX irq.
2133 serial_port_out(port, UART_IER, UART_IER_THRI);
2134 lsr = serial_port_in(port, UART_LSR);
2135 iir = serial_port_in(port, UART_IIR);
2136 serial_port_out(port, UART_IER, 0);
2138 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
2139 if (!(up->bugs & UART_BUG_TXEN)) {
2140 up->bugs |= UART_BUG_TXEN;
2141 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
2142 serial_index(port));
2145 up->bugs &= ~UART_BUG_TXEN;
2149 spin_unlock_irqrestore(&port->lock, flags);
2152 * Clear the interrupt registers again for luck, and clear the
2153 * saved flags to avoid getting false values from polling
2154 * routines or the previous session.
2156 serial_port_in(port, UART_LSR);
2157 serial_port_in(port, UART_RX);
2158 serial_port_in(port, UART_IIR);
2159 serial_port_in(port, UART_MSR);
2160 up->lsr_saved_flags = 0;
2161 up->msr_saved_flags = 0;
2164 * Request DMA channels for both RX and TX.
2167 retval = serial8250_request_dma(up);
2169 pr_warn_ratelimited("ttyS%d - failed to request DMA\n",
2170 serial_index(port));
2176 * Finally, enable interrupts. Note: Modem status interrupts
2177 * are set via set_termios(), which will be occurring imminently
2178 * anyway, so we don't enable them here.
2180 up->ier = UART_IER_RLSI | UART_IER_RDI;
2181 serial_port_out(port, UART_IER, up->ier);
2183 if (port->flags & UPF_FOURPORT) {
2186 * Enable interrupts on the AST Fourport board
2188 icp = (port->iobase & 0xfe0) | 0x01f;
2196 static void serial8250_shutdown(struct uart_port *port)
2198 struct uart_8250_port *up =
2199 container_of(port, struct uart_8250_port, port);
2200 unsigned long flags;
2203 * Disable interrupts from this port
2206 serial_port_out(port, UART_IER, 0);
2209 serial8250_release_dma(up);
2211 spin_lock_irqsave(&port->lock, flags);
2212 if (port->flags & UPF_FOURPORT) {
2213 /* reset interrupts on the AST Fourport board */
2214 inb((port->iobase & 0xfe0) | 0x1f);
2215 port->mctrl |= TIOCM_OUT1;
2217 port->mctrl &= ~TIOCM_OUT2;
2219 serial8250_set_mctrl(port, port->mctrl);
2220 spin_unlock_irqrestore(&port->lock, flags);
2223 * Disable break condition and FIFOs
2225 serial_port_out(port, UART_LCR,
2226 serial_port_in(port, UART_LCR) & ~UART_LCR_SBC);
2227 serial8250_clear_fifos(up);
2229 #ifdef CONFIG_SERIAL_8250_RSA
2231 * Reset the RSA board back to 115kbps compat mode.
2237 * Read data port to reset things, and then unlink from
2240 serial_port_in(port, UART_RX);
2242 del_timer_sync(&up->timer);
2243 up->timer.function = serial8250_timeout;
2245 serial_unlink_irq_chain(up);
2248 static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
2253 * Handle magic divisors for baud rates above baud_base on
2254 * SMSC SuperIO chips.
2256 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2257 baud == (port->uartclk/4))
2259 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2260 baud == (port->uartclk/8))
2263 quot = uart_get_divisor(port, baud);
2269 serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2270 struct ktermios *old)
2272 struct uart_8250_port *up =
2273 container_of(port, struct uart_8250_port, port);
2274 unsigned char cval, fcr = 0;
2275 unsigned long flags;
2276 unsigned int baud, quot;
2279 switch (termios->c_cflag & CSIZE) {
2281 cval = UART_LCR_WLEN5;
2284 cval = UART_LCR_WLEN6;
2287 cval = UART_LCR_WLEN7;
2291 cval = UART_LCR_WLEN8;
2295 if (termios->c_cflag & CSTOPB)
2296 cval |= UART_LCR_STOP;
2297 if (termios->c_cflag & PARENB) {
2298 cval |= UART_LCR_PARITY;
2299 if (up->bugs & UART_BUG_PARITY)
2302 if (!(termios->c_cflag & PARODD))
2303 cval |= UART_LCR_EPAR;
2305 if (termios->c_cflag & CMSPAR)
2306 cval |= UART_LCR_SPAR;
2310 * Ask the core to calculate the divisor for us.
2312 baud = uart_get_baud_rate(port, termios, old,
2313 port->uartclk / 16 / 0xffff,
2314 port->uartclk / 16);
2315 quot = serial8250_get_divisor(port, baud);
2318 * Oxford Semi 952 rev B workaround
2320 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2323 if (up->capabilities & UART_CAP_FIFO && port->fifosize > 1) {
2324 fcr = uart_config[port->type].fcr;
2325 if ((baud < 2400 && !up->dma) || fifo_bug) {
2326 fcr &= ~UART_FCR_TRIGGER_MASK;
2327 fcr |= UART_FCR_TRIGGER_1;
2332 * MCR-based auto flow control. When AFE is enabled, RTS will be
2333 * deasserted when the receive FIFO contains more characters than
2334 * the trigger, or the MCR RTS bit is cleared. In the case where
2335 * the remote UART is not using CTS auto flow control, we must
2336 * have sufficient FIFO entries for the latency of the remote
2337 * UART to respond. IOW, at least 32 bytes of FIFO.
2339 if (up->capabilities & UART_CAP_AFE && port->fifosize >= 32) {
2340 up->mcr &= ~UART_MCR_AFE;
2341 if (termios->c_cflag & CRTSCTS)
2342 up->mcr |= UART_MCR_AFE;
2346 * Ok, we're now changing the port state. Do it with
2347 * interrupts disabled.
2349 spin_lock_irqsave(&port->lock, flags);
2352 * Update the per-port timeout.
2354 uart_update_timeout(port, termios->c_cflag, baud);
2356 port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2357 if (termios->c_iflag & INPCK)
2358 port->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2359 if (termios->c_iflag & (BRKINT | PARMRK))
2360 port->read_status_mask |= UART_LSR_BI;
2363 * Characteres to ignore
2365 port->ignore_status_mask = 0;
2366 if (termios->c_iflag & IGNPAR)
2367 port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2368 if (termios->c_iflag & IGNBRK) {
2369 port->ignore_status_mask |= UART_LSR_BI;
2371 * If we're ignoring parity and break indicators,
2372 * ignore overruns too (for real raw support).
2374 if (termios->c_iflag & IGNPAR)
2375 port->ignore_status_mask |= UART_LSR_OE;
2379 * ignore all characters if CREAD is not set
2381 if ((termios->c_cflag & CREAD) == 0)
2382 port->ignore_status_mask |= UART_LSR_DR;
2385 * CTS flow control flag and modem status interrupts
2387 up->ier &= ~UART_IER_MSI;
2388 if (!(up->bugs & UART_BUG_NOMSR) &&
2389 UART_ENABLE_MS(&up->port, termios->c_cflag))
2390 up->ier |= UART_IER_MSI;
2391 if (up->capabilities & UART_CAP_UUE)
2392 up->ier |= UART_IER_UUE;
2393 if (up->capabilities & UART_CAP_RTOIE)
2394 up->ier |= UART_IER_RTOIE;
2396 serial_port_out(port, UART_IER, up->ier);
2398 if (up->capabilities & UART_CAP_EFR) {
2399 unsigned char efr = 0;
2401 * TI16C752/Startech hardware flow control. FIXME:
2402 * - TI16C752 requires control thresholds to be set.
2403 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2405 if (termios->c_cflag & CRTSCTS)
2406 efr |= UART_EFR_CTS;
2408 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2409 if (port->flags & UPF_EXAR_EFR)
2410 serial_port_out(port, UART_XR_EFR, efr);
2412 serial_port_out(port, UART_EFR, efr);
2415 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2416 if (is_omap1510_8250(up)) {
2417 if (baud == 115200) {
2419 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 1);
2421 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 0);
2425 * For NatSemi, switch to bank 2 not bank 1, to avoid resetting EXCR2,
2426 * otherwise just set DLAB
2428 if (up->capabilities & UART_NATSEMI)
2429 serial_port_out(port, UART_LCR, 0xe0);
2431 serial_port_out(port, UART_LCR, cval | UART_LCR_DLAB);
2433 serial_dl_write(up, quot);
2436 * XR17V35x UARTs have an extra fractional divisor register (DLD)
2438 * We need to recalculate all of the registers, because DLM and DLL
2439 * are already rounded to a whole integer.
2441 * When recalculating we use a 32x clock instead of a 16x clock to
2442 * allow 1-bit for rounding in the fractional part.
2444 if (up->port.type == PORT_XR17V35X) {
2445 unsigned int baud_x32 = (port->uartclk * 2) / baud;
2446 u16 quot = baud_x32 / 32;
2447 u8 quot_frac = DIV_ROUND_CLOSEST(baud_x32 % 32, 2);
2449 serial_dl_write(up, quot);
2450 serial_port_out(port, 0x2, quot_frac & 0xf);
2454 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2455 * is written without DLAB set, this mode will be disabled.
2457 if (port->type == PORT_16750)
2458 serial_port_out(port, UART_FCR, fcr);
2460 serial_port_out(port, UART_LCR, cval); /* reset DLAB */
2461 up->lcr = cval; /* Save LCR */
2462 if (port->type != PORT_16750) {
2463 /* emulated UARTs (Lucent Venus 167x) need two steps */
2464 if (fcr & UART_FCR_ENABLE_FIFO)
2465 serial_port_out(port, UART_FCR, UART_FCR_ENABLE_FIFO);
2466 serial_port_out(port, UART_FCR, fcr); /* set fcr */
2468 serial8250_set_mctrl(port, port->mctrl);
2469 spin_unlock_irqrestore(&port->lock, flags);
2470 /* Don't rewrite B0 */
2471 if (tty_termios_baud_rate(termios))
2472 tty_termios_encode_baud_rate(termios, baud, baud);
2474 EXPORT_SYMBOL(serial8250_do_set_termios);
2477 serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2478 struct ktermios *old)
2480 if (port->set_termios)
2481 port->set_termios(port, termios, old);
2483 serial8250_do_set_termios(port, termios, old);
2487 serial8250_set_ldisc(struct uart_port *port, int new)
2490 port->flags |= UPF_HARDPPS_CD;
2491 serial8250_enable_ms(port);
2493 port->flags &= ~UPF_HARDPPS_CD;
2497 void serial8250_do_pm(struct uart_port *port, unsigned int state,
2498 unsigned int oldstate)
2500 struct uart_8250_port *p =
2501 container_of(port, struct uart_8250_port, port);
2503 serial8250_set_sleep(p, state != 0);
2505 EXPORT_SYMBOL(serial8250_do_pm);
2508 serial8250_pm(struct uart_port *port, unsigned int state,
2509 unsigned int oldstate)
2512 port->pm(port, state, oldstate);
2514 serial8250_do_pm(port, state, oldstate);
2517 static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2519 if (pt->port.iotype == UPIO_AU)
2521 if (is_omap1_8250(pt))
2522 return 0x16 << pt->port.regshift;
2524 return 8 << pt->port.regshift;
2528 * Resource handling.
2530 static int serial8250_request_std_resource(struct uart_8250_port *up)
2532 unsigned int size = serial8250_port_size(up);
2533 struct uart_port *port = &up->port;
2536 switch (port->iotype) {
2544 if (!request_mem_region(port->mapbase, size, "serial")) {
2549 if (port->flags & UPF_IOREMAP) {
2550 port->membase = ioremap_nocache(port->mapbase, size);
2551 if (!port->membase) {
2552 release_mem_region(port->mapbase, size);
2560 if (!request_region(port->iobase, size, "serial"))
2567 static void serial8250_release_std_resource(struct uart_8250_port *up)
2569 unsigned int size = serial8250_port_size(up);
2570 struct uart_port *port = &up->port;
2572 switch (port->iotype) {
2580 if (port->flags & UPF_IOREMAP) {
2581 iounmap(port->membase);
2582 port->membase = NULL;
2585 release_mem_region(port->mapbase, size);
2590 release_region(port->iobase, size);
2595 static int serial8250_request_rsa_resource(struct uart_8250_port *up)
2597 unsigned long start = UART_RSA_BASE << up->port.regshift;
2598 unsigned int size = 8 << up->port.regshift;
2599 struct uart_port *port = &up->port;
2602 switch (port->iotype) {
2605 start += port->iobase;
2606 if (request_region(start, size, "serial-rsa"))
2616 static void serial8250_release_rsa_resource(struct uart_8250_port *up)
2618 unsigned long offset = UART_RSA_BASE << up->port.regshift;
2619 unsigned int size = 8 << up->port.regshift;
2620 struct uart_port *port = &up->port;
2622 switch (port->iotype) {
2625 release_region(port->iobase + offset, size);
2630 static void serial8250_release_port(struct uart_port *port)
2632 struct uart_8250_port *up =
2633 container_of(port, struct uart_8250_port, port);
2635 serial8250_release_std_resource(up);
2636 if (port->type == PORT_RSA)
2637 serial8250_release_rsa_resource(up);
2640 static int serial8250_request_port(struct uart_port *port)
2642 struct uart_8250_port *up =
2643 container_of(port, struct uart_8250_port, port);
2646 if (port->type == PORT_8250_CIR)
2649 ret = serial8250_request_std_resource(up);
2650 if (ret == 0 && port->type == PORT_RSA) {
2651 ret = serial8250_request_rsa_resource(up);
2653 serial8250_release_std_resource(up);
2659 static void serial8250_config_port(struct uart_port *port, int flags)
2661 struct uart_8250_port *up =
2662 container_of(port, struct uart_8250_port, port);
2663 int probeflags = PROBE_ANY;
2666 if (port->type == PORT_8250_CIR)
2670 * Find the region that we can probe for. This in turn
2671 * tells us whether we can probe for the type of port.
2673 ret = serial8250_request_std_resource(up);
2677 ret = serial8250_request_rsa_resource(up);
2679 probeflags &= ~PROBE_RSA;
2681 if (port->iotype != up->cur_iotype)
2682 set_io_from_upio(port);
2684 if (flags & UART_CONFIG_TYPE)
2685 autoconfig(up, probeflags);
2687 /* if access method is AU, it is a 16550 with a quirk */
2688 if (port->type == PORT_16550A && port->iotype == UPIO_AU)
2689 up->bugs |= UART_BUG_NOMSR;
2691 /* HW bugs may trigger IRQ while IIR == NO_INT */
2692 if (port->type == PORT_TEGRA)
2693 up->bugs |= UART_BUG_NOMSR;
2695 if (port->type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2698 if (port->type != PORT_RSA && probeflags & PROBE_RSA)
2699 serial8250_release_rsa_resource(up);
2700 if (port->type == PORT_UNKNOWN)
2701 serial8250_release_std_resource(up);
2703 /* Fixme: probably not the best place for this */
2704 if ((port->type == PORT_XR17V35X) ||
2705 (port->type == PORT_XR17D15X))
2706 port->handle_irq = exar_handle_irq;
2710 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2712 if (ser->irq >= nr_irqs || ser->irq < 0 ||
2713 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2714 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2715 ser->type == PORT_STARTECH)
2721 serial8250_type(struct uart_port *port)
2723 int type = port->type;
2725 if (type >= ARRAY_SIZE(uart_config))
2727 return uart_config[type].name;
2730 static struct uart_ops serial8250_pops = {
2731 .tx_empty = serial8250_tx_empty,
2732 .set_mctrl = serial8250_set_mctrl,
2733 .get_mctrl = serial8250_get_mctrl,
2734 .stop_tx = serial8250_stop_tx,
2735 .start_tx = serial8250_start_tx,
2736 .stop_rx = serial8250_stop_rx,
2737 .enable_ms = serial8250_enable_ms,
2738 .break_ctl = serial8250_break_ctl,
2739 .startup = serial8250_startup,
2740 .shutdown = serial8250_shutdown,
2741 .set_termios = serial8250_set_termios,
2742 .set_ldisc = serial8250_set_ldisc,
2743 .pm = serial8250_pm,
2744 .type = serial8250_type,
2745 .release_port = serial8250_release_port,
2746 .request_port = serial8250_request_port,
2747 .config_port = serial8250_config_port,
2748 .verify_port = serial8250_verify_port,
2749 #ifdef CONFIG_CONSOLE_POLL
2750 .poll_get_char = serial8250_get_poll_char,
2751 .poll_put_char = serial8250_put_poll_char,
2755 static struct uart_8250_port serial8250_ports[UART_NR];
2757 static void (*serial8250_isa_config)(int port, struct uart_port *up,
2758 unsigned short *capabilities);
2760 void serial8250_set_isa_configurator(
2761 void (*v)(int port, struct uart_port *up, unsigned short *capabilities))
2763 serial8250_isa_config = v;
2765 EXPORT_SYMBOL(serial8250_set_isa_configurator);
2767 static void __init serial8250_isa_init_ports(void)
2769 struct uart_8250_port *up;
2770 static int first = 1;
2777 if (nr_uarts > UART_NR)
2780 for (i = 0; i < nr_uarts; i++) {
2781 struct uart_8250_port *up = &serial8250_ports[i];
2782 struct uart_port *port = &up->port;
2785 spin_lock_init(&port->lock);
2787 init_timer(&up->timer);
2788 up->timer.function = serial8250_timeout;
2789 up->cur_iotype = 0xFF;
2792 * ALPHA_KLUDGE_MCR needs to be killed.
2794 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2795 up->mcr_force = ALPHA_KLUDGE_MCR;
2797 port->ops = &serial8250_pops;
2801 irqflag = IRQF_SHARED;
2803 for (i = 0, up = serial8250_ports;
2804 i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
2806 struct uart_port *port = &up->port;
2808 port->iobase = old_serial_port[i].port;
2809 port->irq = irq_canonicalize(old_serial_port[i].irq);
2810 port->irqflags = old_serial_port[i].irqflags;
2811 port->uartclk = old_serial_port[i].baud_base * 16;
2812 port->flags = old_serial_port[i].flags;
2813 port->hub6 = old_serial_port[i].hub6;
2814 port->membase = old_serial_port[i].iomem_base;
2815 port->iotype = old_serial_port[i].io_type;
2816 port->regshift = old_serial_port[i].iomem_reg_shift;
2817 set_io_from_upio(port);
2818 port->irqflags |= irqflag;
2819 if (serial8250_isa_config != NULL)
2820 serial8250_isa_config(i, &up->port, &up->capabilities);
2826 serial8250_init_fixed_type_port(struct uart_8250_port *up, unsigned int type)
2828 up->port.type = type;
2829 if (!up->port.fifosize)
2830 up->port.fifosize = uart_config[type].fifo_size;
2832 up->tx_loadsz = uart_config[type].tx_loadsz;
2833 if (!up->capabilities)
2834 up->capabilities = uart_config[type].flags;
2838 serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2842 for (i = 0; i < nr_uarts; i++) {
2843 struct uart_8250_port *up = &serial8250_ports[i];
2850 if (up->port.flags & UPF_FIXED_TYPE)
2851 serial8250_init_fixed_type_port(up, up->port.type);
2853 uart_add_one_port(drv, &up->port);
2857 #ifdef CONFIG_SERIAL_8250_CONSOLE
2859 static void serial8250_console_putchar(struct uart_port *port, int ch)
2861 struct uart_8250_port *up =
2862 container_of(port, struct uart_8250_port, port);
2864 wait_for_xmitr(up, UART_LSR_THRE);
2865 serial_port_out(port, UART_TX, ch);
2869 * Print a string to the serial port trying not to disturb
2870 * any possible real use of the port...
2872 * The console_lock must be held when we get here.
2875 serial8250_console_write(struct console *co, const char *s, unsigned int count)
2877 struct uart_8250_port *up = &serial8250_ports[co->index];
2878 struct uart_port *port = &up->port;
2879 unsigned long flags;
2883 touch_nmi_watchdog();
2885 local_irq_save(flags);
2887 /* serial8250_handle_irq() already took the lock */
2889 } else if (oops_in_progress) {
2890 locked = spin_trylock(&port->lock);
2892 spin_lock(&port->lock);
2895 * First save the IER then disable the interrupts
2897 ier = serial_port_in(port, UART_IER);
2899 if (up->capabilities & UART_CAP_UUE)
2900 serial_port_out(port, UART_IER, UART_IER_UUE);
2902 serial_port_out(port, UART_IER, 0);
2904 uart_console_write(port, s, count, serial8250_console_putchar);
2907 * Finally, wait for transmitter to become empty
2908 * and restore the IER
2910 wait_for_xmitr(up, BOTH_EMPTY);
2911 serial_port_out(port, UART_IER, ier);
2914 * The receive handling will happen properly because the
2915 * receive ready bit will still be set; it is not cleared
2916 * on read. However, modem control will not, we must
2917 * call it if we have saved something in the saved flags
2918 * while processing with interrupts off.
2920 if (up->msr_saved_flags)
2921 serial8250_modem_status(up);
2924 spin_unlock(&port->lock);
2925 local_irq_restore(flags);
2928 static int __init serial8250_console_setup(struct console *co, char *options)
2930 struct uart_port *port;
2937 * Check whether an invalid uart number has been specified, and
2938 * if so, search for the first available port that does have
2941 if (co->index >= nr_uarts)
2943 port = &serial8250_ports[co->index].port;
2944 if (!port->iobase && !port->membase)
2948 uart_parse_options(options, &baud, &parity, &bits, &flow);
2950 return uart_set_options(port, co, baud, parity, bits, flow);
2953 static int serial8250_console_early_setup(void)
2955 return serial8250_find_port_for_earlycon();
2958 static struct console serial8250_console = {
2960 .write = serial8250_console_write,
2961 .device = uart_console_device,
2962 .setup = serial8250_console_setup,
2963 .early_setup = serial8250_console_early_setup,
2964 .flags = CON_PRINTBUFFER | CON_ANYTIME,
2966 .data = &serial8250_reg,
2969 static int __init serial8250_console_init(void)
2971 serial8250_isa_init_ports();
2972 register_console(&serial8250_console);
2975 console_initcall(serial8250_console_init);
2977 int serial8250_find_port(struct uart_port *p)
2980 struct uart_port *port;
2982 for (line = 0; line < nr_uarts; line++) {
2983 port = &serial8250_ports[line].port;
2984 if (uart_match_port(p, port))
2990 #define SERIAL8250_CONSOLE &serial8250_console
2992 #define SERIAL8250_CONSOLE NULL
2995 static struct uart_driver serial8250_reg = {
2996 .owner = THIS_MODULE,
2997 .driver_name = "serial",
3001 .cons = SERIAL8250_CONSOLE,
3005 * early_serial_setup - early registration for 8250 ports
3007 * Setup an 8250 port structure prior to console initialisation. Use
3008 * after console initialisation will cause undefined behaviour.
3010 int __init early_serial_setup(struct uart_port *port)
3012 struct uart_port *p;
3014 if (port->line >= ARRAY_SIZE(serial8250_ports))
3017 serial8250_isa_init_ports();
3018 p = &serial8250_ports[port->line].port;
3019 p->iobase = port->iobase;
3020 p->membase = port->membase;
3022 p->irqflags = port->irqflags;
3023 p->uartclk = port->uartclk;
3024 p->fifosize = port->fifosize;
3025 p->regshift = port->regshift;
3026 p->iotype = port->iotype;
3027 p->flags = port->flags;
3028 p->mapbase = port->mapbase;
3029 p->private_data = port->private_data;
3030 p->type = port->type;
3031 p->line = port->line;
3033 set_io_from_upio(p);
3034 if (port->serial_in)
3035 p->serial_in = port->serial_in;
3036 if (port->serial_out)
3037 p->serial_out = port->serial_out;
3038 if (port->handle_irq)
3039 p->handle_irq = port->handle_irq;
3041 p->handle_irq = serial8250_default_handle_irq;
3047 * serial8250_suspend_port - suspend one serial port
3048 * @line: serial line number
3050 * Suspend one serial port.
3052 void serial8250_suspend_port(int line)
3054 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
3058 * serial8250_resume_port - resume one serial port
3059 * @line: serial line number
3061 * Resume one serial port.
3063 void serial8250_resume_port(int line)
3065 struct uart_8250_port *up = &serial8250_ports[line];
3066 struct uart_port *port = &up->port;
3068 if (up->capabilities & UART_NATSEMI) {
3069 /* Ensure it's still in high speed mode */
3070 serial_port_out(port, UART_LCR, 0xE0);
3072 ns16550a_goto_highspeed(up);
3074 serial_port_out(port, UART_LCR, 0);
3075 port->uartclk = 921600*16;
3077 uart_resume_port(&serial8250_reg, port);
3081 * Register a set of serial devices attached to a platform device. The
3082 * list is terminated with a zero flags entry, which means we expect
3083 * all entries to have at least UPF_BOOT_AUTOCONF set.
3085 static int serial8250_probe(struct platform_device *dev)
3087 struct plat_serial8250_port *p = dev_get_platdata(&dev->dev);
3088 struct uart_8250_port uart;
3089 int ret, i, irqflag = 0;
3091 memset(&uart, 0, sizeof(uart));
3094 irqflag = IRQF_SHARED;
3096 for (i = 0; p && p->flags != 0; p++, i++) {
3097 uart.port.iobase = p->iobase;
3098 uart.port.membase = p->membase;
3099 uart.port.irq = p->irq;
3100 uart.port.irqflags = p->irqflags;
3101 uart.port.uartclk = p->uartclk;
3102 uart.port.regshift = p->regshift;
3103 uart.port.iotype = p->iotype;
3104 uart.port.flags = p->flags;
3105 uart.port.mapbase = p->mapbase;
3106 uart.port.hub6 = p->hub6;
3107 uart.port.private_data = p->private_data;
3108 uart.port.type = p->type;
3109 uart.port.serial_in = p->serial_in;
3110 uart.port.serial_out = p->serial_out;
3111 uart.port.handle_irq = p->handle_irq;
3112 uart.port.handle_break = p->handle_break;
3113 uart.port.set_termios = p->set_termios;
3114 uart.port.pm = p->pm;
3115 uart.port.dev = &dev->dev;
3116 uart.port.irqflags |= irqflag;
3117 ret = serial8250_register_8250_port(&uart);
3119 dev_err(&dev->dev, "unable to register port at index %d "
3120 "(IO%lx MEM%llx IRQ%d): %d\n", i,
3121 p->iobase, (unsigned long long)p->mapbase,
3129 * Remove serial ports registered against a platform device.
3131 static int serial8250_remove(struct platform_device *dev)
3135 for (i = 0; i < nr_uarts; i++) {
3136 struct uart_8250_port *up = &serial8250_ports[i];
3138 if (up->port.dev == &dev->dev)
3139 serial8250_unregister_port(i);
3144 static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
3148 for (i = 0; i < UART_NR; i++) {
3149 struct uart_8250_port *up = &serial8250_ports[i];
3151 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
3152 uart_suspend_port(&serial8250_reg, &up->port);
3158 static int serial8250_resume(struct platform_device *dev)
3162 for (i = 0; i < UART_NR; i++) {
3163 struct uart_8250_port *up = &serial8250_ports[i];
3165 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
3166 serial8250_resume_port(i);
3172 static struct platform_driver serial8250_isa_driver = {
3173 .probe = serial8250_probe,
3174 .remove = serial8250_remove,
3175 .suspend = serial8250_suspend,
3176 .resume = serial8250_resume,
3178 .name = "serial8250",
3179 .owner = THIS_MODULE,
3184 * This "device" covers _all_ ISA 8250-compatible serial devices listed
3185 * in the table in include/asm/serial.h
3187 static struct platform_device *serial8250_isa_devs;
3190 * serial8250_register_8250_port and serial8250_unregister_port allows for
3191 * 16x50 serial ports to be configured at run-time, to support PCMCIA
3192 * modems and PCI multiport cards.
3194 static DEFINE_MUTEX(serial_mutex);
3196 static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
3201 * First, find a port entry which matches.
3203 for (i = 0; i < nr_uarts; i++)
3204 if (uart_match_port(&serial8250_ports[i].port, port))
3205 return &serial8250_ports[i];
3208 * We didn't find a matching entry, so look for the first
3209 * free entry. We look for one which hasn't been previously
3210 * used (indicated by zero iobase).
3212 for (i = 0; i < nr_uarts; i++)
3213 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
3214 serial8250_ports[i].port.iobase == 0)
3215 return &serial8250_ports[i];
3218 * That also failed. Last resort is to find any entry which
3219 * doesn't have a real port associated with it.
3221 for (i = 0; i < nr_uarts; i++)
3222 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
3223 return &serial8250_ports[i];
3229 * serial8250_register_8250_port - register a serial port
3230 * @up: serial port template
3232 * Configure the serial port specified by the request. If the
3233 * port exists and is in use, it is hung up and unregistered
3236 * The port is then probed and if necessary the IRQ is autodetected
3237 * If this fails an error is returned.
3239 * On success the port is ready to use and the line number is returned.
3241 int serial8250_register_8250_port(struct uart_8250_port *up)
3243 struct uart_8250_port *uart;
3246 if (up->port.uartclk == 0)
3249 mutex_lock(&serial_mutex);
3251 uart = serial8250_find_match_or_unused(&up->port);
3252 if (uart && uart->port.type != PORT_8250_CIR) {
3254 uart_remove_one_port(&serial8250_reg, &uart->port);
3256 uart->port.iobase = up->port.iobase;
3257 uart->port.membase = up->port.membase;
3258 uart->port.irq = up->port.irq;
3259 uart->port.irqflags = up->port.irqflags;
3260 uart->port.uartclk = up->port.uartclk;
3261 uart->port.fifosize = up->port.fifosize;
3262 uart->port.regshift = up->port.regshift;
3263 uart->port.iotype = up->port.iotype;
3264 uart->port.flags = up->port.flags | UPF_BOOT_AUTOCONF;
3265 uart->bugs = up->bugs;
3266 uart->port.mapbase = up->port.mapbase;
3267 uart->port.private_data = up->port.private_data;
3268 uart->port.fifosize = up->port.fifosize;
3269 uart->tx_loadsz = up->tx_loadsz;
3270 uart->capabilities = up->capabilities;
3272 /* Take tx_loadsz from fifosize if it wasn't set separately */
3273 if (uart->port.fifosize && !uart->tx_loadsz)
3274 uart->tx_loadsz = uart->port.fifosize;
3277 uart->port.dev = up->port.dev;
3279 if (up->port.flags & UPF_FIXED_TYPE)
3280 serial8250_init_fixed_type_port(uart, up->port.type);
3282 set_io_from_upio(&uart->port);
3283 /* Possibly override default I/O functions. */
3284 if (up->port.serial_in)
3285 uart->port.serial_in = up->port.serial_in;
3286 if (up->port.serial_out)
3287 uart->port.serial_out = up->port.serial_out;
3288 if (up->port.handle_irq)
3289 uart->port.handle_irq = up->port.handle_irq;
3290 /* Possibly override set_termios call */
3291 if (up->port.set_termios)
3292 uart->port.set_termios = up->port.set_termios;
3294 uart->port.pm = up->port.pm;
3295 if (up->port.handle_break)
3296 uart->port.handle_break = up->port.handle_break;
3298 uart->dl_read = up->dl_read;
3300 uart->dl_write = up->dl_write;
3302 uart->dma = up->dma;
3304 if (serial8250_isa_config != NULL)
3305 serial8250_isa_config(0, &uart->port,
3306 &uart->capabilities);
3308 ret = uart_add_one_port(&serial8250_reg, &uart->port);
3310 ret = uart->port.line;
3312 mutex_unlock(&serial_mutex);
3316 EXPORT_SYMBOL(serial8250_register_8250_port);
3319 * serial8250_unregister_port - remove a 16x50 serial port at runtime
3320 * @line: serial line number
3322 * Remove one serial port. This may not be called from interrupt
3323 * context. We hand the port back to the our control.
3325 void serial8250_unregister_port(int line)
3327 struct uart_8250_port *uart = &serial8250_ports[line];
3329 mutex_lock(&serial_mutex);
3330 uart_remove_one_port(&serial8250_reg, &uart->port);
3331 if (serial8250_isa_devs) {
3332 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
3333 uart->port.type = PORT_UNKNOWN;
3334 uart->port.dev = &serial8250_isa_devs->dev;
3335 uart->capabilities = uart_config[uart->port.type].flags;
3336 uart_add_one_port(&serial8250_reg, &uart->port);
3338 uart->port.dev = NULL;
3340 mutex_unlock(&serial_mutex);
3342 EXPORT_SYMBOL(serial8250_unregister_port);
3344 static int __init serial8250_init(void)
3348 serial8250_isa_init_ports();
3350 printk(KERN_INFO "Serial: 8250/16550 driver, "
3351 "%d ports, IRQ sharing %sabled\n", nr_uarts,
3352 share_irqs ? "en" : "dis");
3355 ret = sunserial_register_minors(&serial8250_reg, UART_NR);
3357 serial8250_reg.nr = UART_NR;
3358 ret = uart_register_driver(&serial8250_reg);
3363 ret = serial8250_pnp_init();
3365 goto unreg_uart_drv;
3367 serial8250_isa_devs = platform_device_alloc("serial8250",
3368 PLAT8250_DEV_LEGACY);
3369 if (!serial8250_isa_devs) {
3374 ret = platform_device_add(serial8250_isa_devs);
3378 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
3380 ret = platform_driver_register(&serial8250_isa_driver);
3384 platform_device_del(serial8250_isa_devs);
3386 platform_device_put(serial8250_isa_devs);
3388 serial8250_pnp_exit();
3391 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3393 uart_unregister_driver(&serial8250_reg);
3399 static void __exit serial8250_exit(void)
3401 struct platform_device *isa_dev = serial8250_isa_devs;
3404 * This tells serial8250_unregister_port() not to re-register
3405 * the ports (thereby making serial8250_isa_driver permanently
3408 serial8250_isa_devs = NULL;
3410 platform_driver_unregister(&serial8250_isa_driver);
3411 platform_device_unregister(isa_dev);
3413 serial8250_pnp_exit();
3416 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3418 uart_unregister_driver(&serial8250_reg);
3422 module_init(serial8250_init);
3423 module_exit(serial8250_exit);
3425 EXPORT_SYMBOL(serial8250_suspend_port);
3426 EXPORT_SYMBOL(serial8250_resume_port);
3428 MODULE_LICENSE("GPL");
3429 MODULE_DESCRIPTION("Generic 8250/16x50 serial driver");
3431 module_param(share_irqs, uint, 0644);
3432 MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
3435 module_param(nr_uarts, uint, 0644);
3436 MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
3438 module_param(skip_txen_test, uint, 0644);
3439 MODULE_PARM_DESC(skip_txen_test, "Skip checking for the TXEN bug at init time");
3441 #ifdef CONFIG_SERIAL_8250_RSA
3442 module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
3443 MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
3445 MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);
3447 #ifdef CONFIG_SERIAL_8250_DEPRECATED_OPTIONS
3449 /* This module was renamed to 8250_core in 3.7. Keep the old "8250" name
3450 * working as well for the module options so we don't break people. We
3451 * need to keep the names identical and the convenient macros will happily
3452 * refuse to let us do that by failing the build with redefinition errors
3453 * of global variables. So we stick them inside a dummy function to avoid
3454 * those conflicts. The options still get parsed, and the redefined
3455 * MODULE_PARAM_PREFIX lets us keep the "8250." syntax alive.
3457 * This is hacky. I'm sorry.
3459 static void __used s8250_options(void)
3461 #undef MODULE_PARAM_PREFIX
3462 #define MODULE_PARAM_PREFIX "8250_core."
3464 module_param_cb(share_irqs, ¶m_ops_uint, &share_irqs, 0644);
3465 module_param_cb(nr_uarts, ¶m_ops_uint, &nr_uarts, 0644);
3466 module_param_cb(skip_txen_test, ¶m_ops_uint, &skip_txen_test, 0644);
3467 #ifdef CONFIG_SERIAL_8250_RSA
3468 __module_param_call(MODULE_PARAM_PREFIX, probe_rsa,
3469 ¶m_array_ops, .arr = &__param_arr_probe_rsa,
3474 MODULE_ALIAS("8250_core");