Pileus Git - ~andy/linux/blob - drivers/staging/xgifb/vb_init.c

   1 #include <linux/delay.h>
   2 #include <linux/vmalloc.h>
   3
   4 #include "XGIfb.h"
   5 #include "vb_def.h"
   6 #include "vb_util.h"
   7 #include "vb_setmode.h"
   8 #include "vb_init.h"
   9 static const unsigned short XGINew_DDRDRAM_TYPE340[4][2] = {
  10         { 16, 0x45},
  11         {  8, 0x35},
  12         {  4, 0x31},
  13         {  2, 0x21} };
  14
  15 static const unsigned short XGINew_DDRDRAM_TYPE20[12][2] = {
  16         { 128, 0x5D},
  17         { 64, 0x59},
  18         { 64, 0x4D},
  19         { 32, 0x55},
  20         { 32, 0x49},
  21         { 32, 0x3D},
  22         { 16, 0x51},
  23         { 16, 0x45},
  24         { 16, 0x39},
  25         {  8, 0x41},
  26         {  8, 0x35},
  27         {  4, 0x31} };
  28
  29 #define XGIFB_ROM_SIZE  65536
  30
  31 static unsigned char
  32 XGINew_GetXG20DRAMType(struct xgi_hw_device_info *HwDeviceExtension,
  33                        struct vb_device_info *pVBInfo)
  34 {
  35         unsigned char data, temp;
  36
  37         if (HwDeviceExtension->jChipType < XG20) {
  38                 data = xgifb_reg_get(pVBInfo->P3c4, 0x39) & 0x02;
  39                 if (data == 0)
  40                         data = (xgifb_reg_get(pVBInfo->P3c4, 0x3A) &
  41                                    0x02) >> 1;
  42                 return data;
  43         } else if (HwDeviceExtension->jChipType == XG27) {
  44                 temp = xgifb_reg_get(pVBInfo->P3c4, 0x3B);
  45                 /* SR3B[7][3]MAA15 MAA11 (Power on Trapping) */
  46                 if (((temp & 0x88) == 0x80) || ((temp & 0x88) == 0x08))
  47                         data = 0; /* DDR */
  48                 else
  49                         data = 1; /* DDRII */
  50                 return data;
  51         } else if (HwDeviceExtension->jChipType == XG21) {
  52                 /* Independent GPIO control */
  53                 xgifb_reg_and(pVBInfo->P3d4, 0xB4, ~0x02);
  54                 udelay(800);
  55                 xgifb_reg_or(pVBInfo->P3d4, 0x4A, 0x80); /* Enable GPIOH read */
  56                 /* GPIOF 0:DVI 1:DVO */
  57                 data = xgifb_reg_get(pVBInfo->P3d4, 0x48);
  58                 /* HOTPLUG_SUPPORT */
  59                 /* for current XG20 & XG21, GPIOH is floating, driver will
  60                  * fix DDR temporarily */
  61                 /* DVI read GPIOH */
  62                 data &= 0x01; /* 1=DDRII, 0=DDR */
  63                 /* ~HOTPLUG_SUPPORT */
  64                 xgifb_reg_or(pVBInfo->P3d4, 0xB4, 0x02);
  65                 return data;
  66         } else {
  67                 data = xgifb_reg_get(pVBInfo->P3d4, 0x97) & 0x01;
  68
  69                 if (data == 1)
  70                         data++;
  71
  72                 return data;
  73         }
  74 }
  75
  76 static void XGINew_DDR1x_MRS_340(unsigned long P3c4,
  77                                  struct vb_device_info *pVBInfo)
  78 {
  79         xgifb_reg_set(P3c4, 0x18, 0x01);
  80         xgifb_reg_set(P3c4, 0x19, 0x20);
  81         xgifb_reg_set(P3c4, 0x16, 0x00);
  82         xgifb_reg_set(P3c4, 0x16, 0x80);
  83
  84         mdelay(3);
  85         xgifb_reg_set(P3c4, 0x18, 0x00);
  86         xgifb_reg_set(P3c4, 0x19, 0x20);
  87         xgifb_reg_set(P3c4, 0x16, 0x00);
  88         xgifb_reg_set(P3c4, 0x16, 0x80);
  89
  90         udelay(60);
  91         xgifb_reg_set(P3c4, 0x18, pVBInfo->SR18[pVBInfo->ram_type]); /* SR18 */
  92         xgifb_reg_set(P3c4, 0x19, 0x01);
  93         xgifb_reg_set(P3c4, 0x16, 0x03);
  94         xgifb_reg_set(P3c4, 0x16, 0x83);
  95         mdelay(1);
  96         xgifb_reg_set(P3c4, 0x1B, 0x03);
  97         udelay(500);
  98         xgifb_reg_set(P3c4, 0x18, pVBInfo->SR18[pVBInfo->ram_type]); /* SR18 */
  99         xgifb_reg_set(P3c4, 0x19, 0x00);
 100         xgifb_reg_set(P3c4, 0x16, 0x03);
 101         xgifb_reg_set(P3c4, 0x16, 0x83);
 102         xgifb_reg_set(P3c4, 0x1B, 0x00);
 103 }
 104
 105 static void XGINew_SetMemoryClock(struct vb_device_info *pVBInfo)
 106 {
 107         xgifb_reg_set(pVBInfo->P3c4,
 108                       0x28,
 109                       pVBInfo->MCLKData[pVBInfo->ram_type].SR28);
 110         xgifb_reg_set(pVBInfo->P3c4,
 111                       0x29,
 112                       pVBInfo->MCLKData[pVBInfo->ram_type].SR29);
 113         xgifb_reg_set(pVBInfo->P3c4,
 114                       0x2A,
 115                       pVBInfo->MCLKData[pVBInfo->ram_type].SR2A);
 116
 117         xgifb_reg_set(pVBInfo->P3c4,
 118                       0x2E,
 119                       XGI340_ECLKData[pVBInfo->ram_type].SR2E);
 120         xgifb_reg_set(pVBInfo->P3c4,
 121                       0x2F,
 122                       XGI340_ECLKData[pVBInfo->ram_type].SR2F);
 123         xgifb_reg_set(pVBInfo->P3c4,
 124                       0x30,
 125                       XGI340_ECLKData[pVBInfo->ram_type].SR30);
 126 }
 127
 128 static void XGINew_DDRII_Bootup_XG27(
 129                         struct xgi_hw_device_info *HwDeviceExtension,
 130                         unsigned long P3c4, struct vb_device_info *pVBInfo)
 131 {
 132         unsigned long P3d4 = P3c4 + 0x10;
 133         pVBInfo->ram_type = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
 134         XGINew_SetMemoryClock(pVBInfo);
 135
 136         /* Set Double Frequency */
 137         xgifb_reg_set(P3d4, 0x97, pVBInfo->XGINew_CR97); /* CR97 */
 138
 139         udelay(200);
 140
 141         xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS2 */
 142         xgifb_reg_set(P3c4, 0x19, 0x80); /* Set SR19 */
 143         xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
 144         udelay(15);
 145         xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
 146         udelay(15);
 147
 148         xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS3 */
 149         xgifb_reg_set(P3c4, 0x19, 0xC0); /* Set SR19 */
 150         xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
 151         udelay(15);
 152         xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
 153         udelay(15);
 154
 155         xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS1 */
 156         xgifb_reg_set(P3c4, 0x19, 0x40); /* Set SR19 */
 157         xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
 158         udelay(30);
 159         xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
 160         udelay(15);
 161
 162         xgifb_reg_set(P3c4, 0x18, 0x42); /* Set SR18 */ /* MRS, DLL Enable */
 163         xgifb_reg_set(P3c4, 0x19, 0x0A); /* Set SR19 */
 164         xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */
 165         udelay(30);
 166         xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */
 167         xgifb_reg_set(P3c4, 0x16, 0x80); /* Set SR16 */
 168
 169         xgifb_reg_set(P3c4, 0x1B, 0x04); /* Set SR1B */
 170         udelay(60);
 171         xgifb_reg_set(P3c4, 0x1B, 0x00); /* Set SR1B */
 172
 173         xgifb_reg_set(P3c4, 0x18, 0x42); /* Set SR18 */ /* MRS, DLL Reset */
 174         xgifb_reg_set(P3c4, 0x19, 0x08); /* Set SR19 */
 175         xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */
 176
 177         udelay(30);
 178         xgifb_reg_set(P3c4, 0x16, 0x83); /* Set SR16 */
 179         udelay(15);
 180
 181         xgifb_reg_set(P3c4, 0x18, 0x80); /* Set SR18 */ /* MRS, ODT */
 182         xgifb_reg_set(P3c4, 0x19, 0x46); /* Set SR19 */
 183         xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
 184         udelay(30);
 185         xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
 186         udelay(15);
 187
 188         xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS */
 189         xgifb_reg_set(P3c4, 0x19, 0x40); /* Set SR19 */
 190         xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
 191         udelay(30);
 192         xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
 193         udelay(15);
 194
 195         /* Set SR1B refresh control 000:close; 010:open */
 196         xgifb_reg_set(P3c4, 0x1B, 0x04);
 197         udelay(200);
 198
 199 }
 200
 201 static void XGINew_DDR2_MRS_XG20(struct xgi_hw_device_info *HwDeviceExtension,
 202                 unsigned long P3c4, struct vb_device_info *pVBInfo)
 203 {
 204         unsigned long P3d4 = P3c4 + 0x10;
 205
 206         pVBInfo->ram_type = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
 207         XGINew_SetMemoryClock(pVBInfo);
 208
 209         xgifb_reg_set(P3d4, 0x97, 0x11); /* CR97 */
 210
 211         udelay(200);
 212         xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS2 */
 213         xgifb_reg_set(P3c4, 0x19, 0x80);
 214         xgifb_reg_set(P3c4, 0x16, 0x05);
 215         xgifb_reg_set(P3c4, 0x16, 0x85);
 216
 217         xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS3 */
 218         xgifb_reg_set(P3c4, 0x19, 0xC0);
 219         xgifb_reg_set(P3c4, 0x16, 0x05);
 220         xgifb_reg_set(P3c4, 0x16, 0x85);
 221
 222         xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS1 */
 223         xgifb_reg_set(P3c4, 0x19, 0x40);
 224         xgifb_reg_set(P3c4, 0x16, 0x05);
 225         xgifb_reg_set(P3c4, 0x16, 0x85);
 226
 227         xgifb_reg_set(P3c4, 0x18, 0x42); /* MRS1 */
 228         xgifb_reg_set(P3c4, 0x19, 0x02);
 229         xgifb_reg_set(P3c4, 0x16, 0x05);
 230         xgifb_reg_set(P3c4, 0x16, 0x85);
 231
 232         udelay(15);
 233         xgifb_reg_set(P3c4, 0x1B, 0x04); /* SR1B */
 234         udelay(30);
 235         xgifb_reg_set(P3c4, 0x1B, 0x00); /* SR1B */
 236         udelay(100);
 237
 238         xgifb_reg_set(P3c4, 0x18, 0x42); /* MRS1 */
 239         xgifb_reg_set(P3c4, 0x19, 0x00);
 240         xgifb_reg_set(P3c4, 0x16, 0x05);
 241         xgifb_reg_set(P3c4, 0x16, 0x85);
 242
 243         udelay(200);
 244 }
 245
 246 static void XGINew_DDR1x_MRS_XG20(unsigned long P3c4,
 247                                   struct vb_device_info *pVBInfo)
 248 {
 249         xgifb_reg_set(P3c4, 0x18, 0x01);
 250         xgifb_reg_set(P3c4, 0x19, 0x40);
 251         xgifb_reg_set(P3c4, 0x16, 0x00);
 252         xgifb_reg_set(P3c4, 0x16, 0x80);
 253         udelay(60);
 254
 255         xgifb_reg_set(P3c4, 0x18, 0x00);
 256         xgifb_reg_set(P3c4, 0x19, 0x40);
 257         xgifb_reg_set(P3c4, 0x16, 0x00);
 258         xgifb_reg_set(P3c4, 0x16, 0x80);
 259         udelay(60);
 260         xgifb_reg_set(P3c4, 0x18, pVBInfo->SR18[pVBInfo->ram_type]); /* SR18 */
 261         xgifb_reg_set(P3c4, 0x19, 0x01);
 262         xgifb_reg_set(P3c4, 0x16, 0x03);
 263         xgifb_reg_set(P3c4, 0x16, 0x83);
 264         mdelay(1);
 265         xgifb_reg_set(P3c4, 0x1B, 0x03);
 266         udelay(500);
 267         xgifb_reg_set(P3c4, 0x18, pVBInfo->SR18[pVBInfo->ram_type]); /* SR18 */
 268         xgifb_reg_set(P3c4, 0x19, 0x00);
 269         xgifb_reg_set(P3c4, 0x16, 0x03);
 270         xgifb_reg_set(P3c4, 0x16, 0x83);
 271         xgifb_reg_set(P3c4, 0x1B, 0x00);
 272 }
 273
 274 static void XGINew_DDR1x_DefaultRegister(
 275                 struct xgi_hw_device_info *HwDeviceExtension,
 276                 unsigned long Port, struct vb_device_info *pVBInfo)
 277 {
 278         unsigned long P3d4 = Port, P3c4 = Port - 0x10;
 279
 280         if (HwDeviceExtension->jChipType >= XG20) {
 281                 XGINew_SetMemoryClock(pVBInfo);
 282                 xgifb_reg_set(P3d4,
 283                               0x82,
 284                               pVBInfo->CR40[11][pVBInfo->ram_type]); /* CR82 */
 285                 xgifb_reg_set(P3d4,
 286                               0x85,
 287                               pVBInfo->CR40[12][pVBInfo->ram_type]); /* CR85 */
 288                 xgifb_reg_set(P3d4,
 289                               0x86,
 290                               pVBInfo->CR40[13][pVBInfo->ram_type]); /* CR86 */
 291
 292                 xgifb_reg_set(P3d4, 0x98, 0x01);
 293                 xgifb_reg_set(P3d4, 0x9A, 0x02);
 294
 295                 XGINew_DDR1x_MRS_XG20(P3c4, pVBInfo);
 296         } else {
 297                 XGINew_SetMemoryClock(pVBInfo);
 298
 299                 switch (HwDeviceExtension->jChipType) {
 300                 case XG42:
 301                         /* CR82 */
 302                         xgifb_reg_set(P3d4,
 303                                       0x82,
 304                                       pVBInfo->CR40[11][pVBInfo->ram_type]);
 305                         /* CR85 */
 306                         xgifb_reg_set(P3d4,
 307                                       0x85,
 308                                       pVBInfo->CR40[12][pVBInfo->ram_type]);
 309                         /* CR86 */
 310                         xgifb_reg_set(P3d4,
 311                                       0x86,
 312                                       pVBInfo->CR40[13][pVBInfo->ram_type]);
 313                         break;
 314                 default:
 315                         xgifb_reg_set(P3d4, 0x82, 0x88);
 316                         xgifb_reg_set(P3d4, 0x86, 0x00);
 317                         /* Insert read command for delay */
 318                         xgifb_reg_get(P3d4, 0x86);
 319                         xgifb_reg_set(P3d4, 0x86, 0x88);
 320                         xgifb_reg_get(P3d4, 0x86);
 321                         xgifb_reg_set(P3d4,
 322                                       0x86,
 323                                       pVBInfo->CR40[13][pVBInfo->ram_type]);
 324                         xgifb_reg_set(P3d4, 0x82, 0x77);
 325                         xgifb_reg_set(P3d4, 0x85, 0x00);
 326
 327                         /* Insert read command for delay */
 328                         xgifb_reg_get(P3d4, 0x85);
 329                         xgifb_reg_set(P3d4, 0x85, 0x88);
 330
 331                         /* Insert read command for delay */
 332                         xgifb_reg_get(P3d4, 0x85);
 333                         /* CR85 */
 334                         xgifb_reg_set(P3d4,
 335                                       0x85,
 336                                       pVBInfo->CR40[12][pVBInfo->ram_type]);
 337                         /* CR82 */
 338                         xgifb_reg_set(P3d4,
 339                                       0x82,
 340                                       pVBInfo->CR40[11][pVBInfo->ram_type]);
 341                         break;
 342                 }
 343
 344                 xgifb_reg_set(P3d4, 0x97, 0x00);
 345                 xgifb_reg_set(P3d4, 0x98, 0x01);
 346                 xgifb_reg_set(P3d4, 0x9A, 0x02);
 347                 XGINew_DDR1x_MRS_340(P3c4, pVBInfo);
 348         }
 349 }
 350
 351 static void XGINew_DDR2_DefaultRegister(
 352                 struct xgi_hw_device_info *HwDeviceExtension,
 353                 unsigned long Port, struct vb_device_info *pVBInfo)
 354 {
 355         unsigned long P3d4 = Port, P3c4 = Port - 0x10;
 356
 357         /* keep following setting sequence, each setting in
 358          * the same reg insert idle */
 359         xgifb_reg_set(P3d4, 0x82, 0x77);
 360         xgifb_reg_set(P3d4, 0x86, 0x00);
 361         xgifb_reg_get(P3d4, 0x86); /* Insert read command for delay */
 362         xgifb_reg_set(P3d4, 0x86, 0x88);
 363         xgifb_reg_get(P3d4, 0x86); /* Insert read command for delay */
 364         /* CR86 */
 365         xgifb_reg_set(P3d4, 0x86, pVBInfo->CR40[13][pVBInfo->ram_type]);
 366         xgifb_reg_set(P3d4, 0x82, 0x77);
 367         xgifb_reg_set(P3d4, 0x85, 0x00);
 368         xgifb_reg_get(P3d4, 0x85); /* Insert read command for delay */
 369         xgifb_reg_set(P3d4, 0x85, 0x88);
 370         xgifb_reg_get(P3d4, 0x85); /* Insert read command for delay */
 371         xgifb_reg_set(P3d4,
 372                       0x85,
 373                       pVBInfo->CR40[12][pVBInfo->ram_type]); /* CR85 */
 374         if (HwDeviceExtension->jChipType == XG27)
 375                 /* CR82 */
 376                 xgifb_reg_set(P3d4, 0x82, pVBInfo->CR40[11][pVBInfo->ram_type]);
 377         else
 378                 xgifb_reg_set(P3d4, 0x82, 0xA8); /* CR82 */
 379
 380         xgifb_reg_set(P3d4, 0x98, 0x01);
 381         xgifb_reg_set(P3d4, 0x9A, 0x02);
 382         if (HwDeviceExtension->jChipType == XG27)
 383                 XGINew_DDRII_Bootup_XG27(HwDeviceExtension, P3c4, pVBInfo);
 384         else
 385                 XGINew_DDR2_MRS_XG20(HwDeviceExtension, P3c4, pVBInfo);
 386 }
 387
 388 static void XGI_SetDRAM_Helper(unsigned long P3d4, u8 seed, u8 temp2, u8 reg,
 389         u8 shift_factor, u8 mask1, u8 mask2)
 390 {
 391         u8 j;
 392         for (j = 0; j < 4; j++) {
 393                 temp2 |= (((seed >> (2 * j)) & 0x03) << shift_factor);
 394                 xgifb_reg_set(P3d4, reg, temp2);
 395                 xgifb_reg_get(P3d4, reg);
 396                 temp2 &= mask1;
 397                 temp2 += mask2;
 398         }
 399 }
 400
 401 static void XGINew_SetDRAMDefaultRegister340(
 402                 struct xgi_hw_device_info *HwDeviceExtension,
 403                 unsigned long Port, struct vb_device_info *pVBInfo)
 404 {
 405         unsigned char temp, temp1, temp2, temp3, j, k;
 406
 407         unsigned long P3d4 = Port, P3c4 = Port - 0x10;
 408
 409         xgifb_reg_set(P3d4, 0x6D, pVBInfo->CR40[8][pVBInfo->ram_type]);
 410         xgifb_reg_set(P3d4, 0x68, pVBInfo->CR40[5][pVBInfo->ram_type]);
 411         xgifb_reg_set(P3d4, 0x69, pVBInfo->CR40[6][pVBInfo->ram_type]);
 412         xgifb_reg_set(P3d4, 0x6A, pVBInfo->CR40[7][pVBInfo->ram_type]);
 413
 414         /* CR6B DQS fine tune delay */
 415         temp = 0xaa;
 416         XGI_SetDRAM_Helper(P3d4, temp, 0, 0x6B, 2, 0xF0, 0x10);
 417
 418         /* CR6E DQM fine tune delay */
 419         XGI_SetDRAM_Helper(P3d4, 0, 0, 0x6E, 2, 0xF0, 0x10);
 420
 421         temp3 = 0;
 422         for (k = 0; k < 4; k++) {
 423                 /* CR6E_D[1:0] select channel */
 424                 xgifb_reg_and_or(P3d4, 0x6E, 0xFC, temp3);
 425                 XGI_SetDRAM_Helper(P3d4, 0, 0, 0x6F, 0, 0xF8, 0x08);
 426                 temp3 += 0x01;
 427         }
 428
 429         xgifb_reg_set(P3d4,
 430                       0x80,
 431                       pVBInfo->CR40[9][pVBInfo->ram_type]); /* CR80 */
 432         xgifb_reg_set(P3d4,
 433                       0x81,
 434                       pVBInfo->CR40[10][pVBInfo->ram_type]); /* CR81 */
 435
 436         temp2 = 0x80;
 437         /* CR89 terminator type select */
 438         XGI_SetDRAM_Helper(P3d4, 0, temp2, 0x89, 0, 0xF0, 0x10);
 439
 440         temp = 0;
 441         temp1 = temp & 0x03;
 442         temp2 |= temp1;
 443         xgifb_reg_set(P3d4, 0x89, temp2);
 444
 445         temp = pVBInfo->CR40[3][pVBInfo->ram_type];
 446         temp1 = temp & 0x0F;
 447         temp2 = (temp >> 4) & 0x07;
 448         temp3 = temp & 0x80;
 449         xgifb_reg_set(P3d4, 0x45, temp1); /* CR45 */
 450         xgifb_reg_set(P3d4, 0x99, temp2); /* CR99 */
 451         xgifb_reg_or(P3d4, 0x40, temp3); /* CR40_D[7] */
 452         xgifb_reg_set(P3d4,
 453                       0x41,
 454                       pVBInfo->CR40[0][pVBInfo->ram_type]); /* CR41 */
 455
 456         if (HwDeviceExtension->jChipType == XG27)
 457                 xgifb_reg_set(P3d4, 0x8F, XG27_CR8F); /* CR8F */
 458
 459         for (j = 0; j <= 6; j++) /* CR90 - CR96 */
 460                 xgifb_reg_set(P3d4, (0x90 + j),
 461                                 pVBInfo->CR40[14 + j][pVBInfo->ram_type]);
 462
 463         for (j = 0; j <= 2; j++) /* CRC3 - CRC5 */
 464                 xgifb_reg_set(P3d4, (0xC3 + j),
 465                                 pVBInfo->CR40[21 + j][pVBInfo->ram_type]);
 466
 467         for (j = 0; j < 2; j++) /* CR8A - CR8B */
 468                 xgifb_reg_set(P3d4, (0x8A + j),
 469                                 pVBInfo->CR40[1 + j][pVBInfo->ram_type]);
 470
 471         if (HwDeviceExtension->jChipType == XG42)
 472                 xgifb_reg_set(P3d4, 0x8C, 0x87);
 473
 474         xgifb_reg_set(P3d4,
 475                       0x59,
 476                       pVBInfo->CR40[4][pVBInfo->ram_type]); /* CR59 */
 477
 478         xgifb_reg_set(P3d4, 0x83, 0x09); /* CR83 */
 479         xgifb_reg_set(P3d4, 0x87, 0x00); /* CR87 */
 480         xgifb_reg_set(P3d4, 0xCF, XG40_CRCF); /* CRCF */
 481         if (pVBInfo->ram_type) {
 482                 xgifb_reg_set(P3c4, 0x17, 0x80); /* SR17 DDRII */
 483                 if (HwDeviceExtension->jChipType == XG27)
 484                         xgifb_reg_set(P3c4, 0x17, 0x02); /* SR17 DDRII */
 485
 486         } else {
 487                 xgifb_reg_set(P3c4, 0x17, 0x00); /* SR17 DDR */
 488         }
 489         xgifb_reg_set(P3c4, 0x1A, 0x87); /* SR1A */
 490
 491         temp = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
 492         if (temp == 0) {
 493                 XGINew_DDR1x_DefaultRegister(HwDeviceExtension, P3d4, pVBInfo);
 494         } else {
 495                 xgifb_reg_set(P3d4, 0xB0, 0x80); /* DDRII Dual frequency mode */
 496                 XGINew_DDR2_DefaultRegister(HwDeviceExtension, P3d4, pVBInfo);
 497         }
 498         xgifb_reg_set(P3c4, 0x1B, 0x03); /* SR1B */
 499 }
 500
 501
 502 static unsigned short XGINew_SetDRAMSize20Reg(
 503                 unsigned short dram_size,
 504                 struct vb_device_info *pVBInfo)
 505 {
 506         unsigned short data = 0, memsize = 0;
 507         int RankSize;
 508         unsigned char ChannelNo;
 509
 510         RankSize = dram_size * pVBInfo->ram_bus / 8;
 511         data = xgifb_reg_get(pVBInfo->P3c4, 0x13);
 512         data &= 0x80;
 513
 514         if (data == 0x80)
 515                 RankSize *= 2;
 516
 517         data = 0;
 518
 519         if (pVBInfo->ram_channel == 3)
 520                 ChannelNo = 4;
 521         else
 522                 ChannelNo = pVBInfo->ram_channel;
 523
 524         if (ChannelNo * RankSize <= 256) {
 525                 while ((RankSize >>= 1) > 0)
 526                         data += 0x10;
 527
 528                 memsize = data >> 4;
 529
 530                 /* Fix DRAM Sizing Error */
 531                 xgifb_reg_set(pVBInfo->P3c4,
 532                               0x14,
 533                               (xgifb_reg_get(pVBInfo->P3c4, 0x14) & 0x0F) |
 534                                 (data & 0xF0));
 535                 udelay(15);
 536         }
 537         return memsize;
 538 }
 539
 540 static int XGINew_ReadWriteRest(unsigned short StopAddr,
 541                 unsigned short StartAddr, struct vb_device_info *pVBInfo)
 542 {
 543         int i;
 544         unsigned long Position = 0;
 545         void __iomem *fbaddr = pVBInfo->FBAddr;
 546
 547         writel(Position, fbaddr + Position);
 548
 549         for (i = StartAddr; i <= StopAddr; i++) {
 550                 Position = 1 << i;
 551                 writel(Position, fbaddr + Position);
 552         }
 553
 554         udelay(500); /* Fix #1759 Memory Size error in Multi-Adapter. */
 555
 556         Position = 0;
 557
 558         if (readl(fbaddr + Position) != Position)
 559                 return 0;
 560
 561         for (i = StartAddr; i <= StopAddr; i++) {
 562                 Position = 1 << i;
 563                 if (readl(fbaddr + Position) != Position)
 564                         return 0;
 565         }
 566         return 1;
 567 }
 568
 569 static unsigned char XGINew_CheckFrequence(struct vb_device_info *pVBInfo)
 570 {
 571         unsigned char data;
 572
 573         data = xgifb_reg_get(pVBInfo->P3d4, 0x97);
 574
 575         if ((data & 0x10) == 0) {
 576                 data = xgifb_reg_get(pVBInfo->P3c4, 0x39);
 577                 data = (data & 0x02) >> 1;
 578                 return data;
 579         } else {
 580                 return data & 0x01;
 581         }
 582 }
 583
 584 static void XGINew_CheckChannel(struct xgi_hw_device_info *HwDeviceExtension,
 585                 struct vb_device_info *pVBInfo)
 586 {
 587         unsigned char data;
 588
 589         switch (HwDeviceExtension->jChipType) {
 590         case XG20:
 591         case XG21:
 592                 data = xgifb_reg_get(pVBInfo->P3d4, 0x97);
 593                 data = data & 0x01;
 594                 pVBInfo->ram_channel = 1; /* XG20 "JUST" one channel */
 595
 596                 if (data == 0) { /* Single_32_16 */
 597
 598                         if ((HwDeviceExtension->ulVideoMemorySize - 1)
 599                                         > 0x1000000) {
 600
 601                                 pVBInfo->ram_bus = 32; /* 32 bits */
 602                                 /* 22bit + 2 rank + 32bit */
 603                                 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
 604                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x52);
 605                                 udelay(15);
 606
 607                                 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
 608                                         return;
 609
 610                                 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
 611                                     0x800000) {
 612                                         /* 22bit + 1 rank + 32bit */
 613                                         xgifb_reg_set(pVBInfo->P3c4,
 614                                                       0x13,
 615                                                       0x31);
 616                                         xgifb_reg_set(pVBInfo->P3c4,
 617                                                       0x14,
 618                                                       0x42);
 619                                         udelay(15);
 620
 621                                         if (XGINew_ReadWriteRest(23,
 622                                                                  23,
 623                                                                  pVBInfo) == 1)
 624                                                 return;
 625                                 }
 626                         }
 627
 628                         if ((HwDeviceExtension->ulVideoMemorySize - 1) >
 629                             0x800000) {
 630                                 pVBInfo->ram_bus = 16; /* 16 bits */
 631                                 /* 22bit + 2 rank + 16bit */
 632                                 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
 633                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x41);
 634                                 udelay(15);
 635
 636                                 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
 637                                         return;
 638                                 else
 639                                         xgifb_reg_set(pVBInfo->P3c4,
 640                                                       0x13,
 641                                                       0x31);
 642                                 udelay(15);
 643                         }
 644
 645                 } else { /* Dual_16_8 */
 646                         if ((HwDeviceExtension->ulVideoMemorySize - 1) >
 647                             0x800000) {
 648                                 pVBInfo->ram_bus = 16; /* 16 bits */
 649                                 /* (0x31:12x8x2) 22bit + 2 rank */
 650                                 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
 651                                 /* 0x41:16Mx16 bit*/
 652                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x41);
 653                                 udelay(15);
 654
 655                                 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
 656                                         return;
 657
 658                                 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
 659                                     0x400000) {
 660                                         /* (0x31:12x8x2) 22bit + 1 rank */
 661                                         xgifb_reg_set(pVBInfo->P3c4,
 662                                                       0x13,
 663                                                       0x31);
 664                                         /* 0x31:8Mx16 bit*/
 665                                         xgifb_reg_set(pVBInfo->P3c4,
 666                                                       0x14,
 667                                                       0x31);
 668                                         udelay(15);
 669
 670                                         if (XGINew_ReadWriteRest(22,
 671                                                                  22,
 672                                                                  pVBInfo) == 1)
 673                                                 return;
 674                                 }
 675                         }
 676
 677                         if ((HwDeviceExtension->ulVideoMemorySize - 1) >
 678                             0x400000) {
 679                                 pVBInfo->ram_bus = 8; /* 8 bits */
 680                                 /* (0x31:12x8x2) 22bit + 2 rank */
 681                                 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
 682                                 /* 0x30:8Mx8 bit*/
 683                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x30);
 684                                 udelay(15);
 685
 686                                 if (XGINew_ReadWriteRest(22, 21, pVBInfo) == 1)
 687                                         return;
 688                                 else /* (0x31:12x8x2) 22bit + 1 rank */
 689                                         xgifb_reg_set(pVBInfo->P3c4,
 690                                                       0x13,
 691                                                       0x31);
 692                                 udelay(15);
 693                         }
 694                 }
 695                 break;
 696
 697         case XG27:
 698                 pVBInfo->ram_bus = 16; /* 16 bits */
 699                 pVBInfo->ram_channel = 1; /* Single channel */
 700                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x51); /* 32Mx16 bit*/
 701                 break;
 702         case XG42:
 703                 /*
 704                  XG42 SR14 D[3] Reserve
 705                  D[2] = 1, Dual Channel
 706                  = 0, Single Channel
 707
 708                  It's Different from Other XG40 Series.
 709                  */
 710                 if (XGINew_CheckFrequence(pVBInfo) == 1) { /* DDRII, DDR2x */
 711                         pVBInfo->ram_bus = 32; /* 32 bits */
 712                         pVBInfo->ram_channel = 2; /* 2 Channel */
 713                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
 714                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x44);
 715
 716                         if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
 717                                 return;
 718
 719                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
 720                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x34);
 721                         if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
 722                                 return;
 723
 724                         pVBInfo->ram_channel = 1; /* Single Channel */
 725                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
 726                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x40);
 727
 728                         if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
 729                                 return;
 730                         else {
 731                                 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
 732                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x30);
 733                         }
 734                 } else { /* DDR */
 735                         pVBInfo->ram_bus = 64; /* 64 bits */
 736                         pVBInfo->ram_channel = 1; /* 1 channels */
 737                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
 738                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x52);
 739
 740                         if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
 741                                 return;
 742                         else {
 743                                 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
 744                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x42);
 745                         }
 746                 }
 747
 748                 break;
 749
 750         default: /* XG40 */
 751
 752                 if (XGINew_CheckFrequence(pVBInfo) == 1) { /* DDRII */
 753                         pVBInfo->ram_bus = 32; /* 32 bits */
 754                         pVBInfo->ram_channel = 3;
 755                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
 756                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x4C);
 757
 758                         if (XGINew_ReadWriteRest(25, 23, pVBInfo) == 1)
 759                                 return;
 760
 761                         pVBInfo->ram_channel = 2; /* 2 channels */
 762                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x48);
 763
 764                         if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
 765                                 return;
 766
 767                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
 768                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x3C);
 769
 770                         if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1) {
 771                                 pVBInfo->ram_channel = 3; /* 4 channels */
 772                         } else {
 773                                 pVBInfo->ram_channel = 2; /* 2 channels */
 774                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x38);
 775                         }
 776                 } else { /* DDR */
 777                         pVBInfo->ram_bus = 64; /* 64 bits */
 778                         pVBInfo->ram_channel = 2; /* 2 channels */
 779                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
 780                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x5A);
 781
 782                         if (XGINew_ReadWriteRest(25, 24, pVBInfo) == 1) {
 783                                 return;
 784                         } else {
 785                                 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
 786                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x4A);
 787                         }
 788                 }
 789                 break;
 790         }
 791 }
 792
 793 static int XGINew_DDRSizing340(struct xgi_hw_device_info *HwDeviceExtension,
 794                 struct vb_device_info *pVBInfo)
 795 {
 796         u8 i, size;
 797         unsigned short memsize, start_addr;
 798         const unsigned short (*dram_table)[2];
 799
 800         xgifb_reg_set(pVBInfo->P3c4, 0x15, 0x00); /* noninterleaving */
 801         xgifb_reg_set(pVBInfo->P3c4, 0x1C, 0x00); /* nontiling */
 802         XGINew_CheckChannel(HwDeviceExtension, pVBInfo);
 803
 804         if (HwDeviceExtension->jChipType >= XG20) {
 805                 dram_table = XGINew_DDRDRAM_TYPE20;
 806                 size = ARRAY_SIZE(XGINew_DDRDRAM_TYPE20);
 807                 start_addr = 5;
 808         } else {
 809                 dram_table = XGINew_DDRDRAM_TYPE340;
 810                 size = ARRAY_SIZE(XGINew_DDRDRAM_TYPE340);
 811                 start_addr = 9;
 812         }
 813
 814         for (i = 0; i < size; i++) {
 815                 /* SetDRAMSizingType */
 816                 xgifb_reg_and_or(pVBInfo->P3c4, 0x13, 0x80, dram_table[i][1]);
 817                 udelay(15); /* should delay 50 ns */
 818
 819                 memsize = XGINew_SetDRAMSize20Reg(dram_table[i][0], pVBInfo);
 820
 821                 if (memsize == 0)
 822                         continue;
 823
 824                 memsize += (pVBInfo->ram_channel - 2) + 20;
 825                 if ((HwDeviceExtension->ulVideoMemorySize - 1) <
 826                         (unsigned long) (1 << memsize))
 827                         continue;
 828
 829                 if (XGINew_ReadWriteRest(memsize, start_addr, pVBInfo) == 1)
 830                         return 1;
 831         }
 832         return 0;
 833 }
 834
 835 static void XGINew_SetDRAMSize_340(struct xgifb_video_info *xgifb_info,
 836                 struct xgi_hw_device_info *HwDeviceExtension,
 837                 struct vb_device_info *pVBInfo)
 838 {
 839         unsigned short data;
 840
 841         pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress;
 842
 843         XGISetModeNew(xgifb_info, HwDeviceExtension, 0x2e);
 844
 845         data = xgifb_reg_get(pVBInfo->P3c4, 0x21);
 846         /* disable read cache */
 847         xgifb_reg_set(pVBInfo->P3c4, 0x21, (unsigned short) (data & 0xDF));
 848         XGI_DisplayOff(xgifb_info, HwDeviceExtension, pVBInfo);
 849
 850         XGINew_DDRSizing340(HwDeviceExtension, pVBInfo);
 851         data = xgifb_reg_get(pVBInfo->P3c4, 0x21);
 852         /* enable read cache */
 853         xgifb_reg_set(pVBInfo->P3c4, 0x21, (unsigned short) (data | 0x20));
 854 }
 855
 856 static u8 *xgifb_copy_rom(struct pci_dev *dev, size_t *rom_size)
 857 {
 858         void __iomem *rom_address;
 859         u8 *rom_copy;
 860
 861         rom_address = pci_map_rom(dev, rom_size);
 862         if (rom_address == NULL)
 863                 return NULL;
 864
 865         rom_copy = vzalloc(XGIFB_ROM_SIZE);
 866         if (rom_copy == NULL)
 867                 goto done;
 868
 869         *rom_size = min_t(size_t, *rom_size, XGIFB_ROM_SIZE);
 870         memcpy_fromio(rom_copy, rom_address, *rom_size);
 871
 872 done:
 873         pci_unmap_rom(dev, rom_address);
 874         return rom_copy;
 875 }
 876
 877 static bool xgifb_read_vbios(struct pci_dev *pdev)
 878 {
 879         struct xgifb_video_info *xgifb_info = pci_get_drvdata(pdev);
 880         u8 *vbios;
 881         unsigned long i;
 882         unsigned char j;
 883         struct XGI21_LVDSCapStruct *lvds;
 884         size_t vbios_size;
 885         int entry;
 886
 887         vbios = xgifb_copy_rom(pdev, &vbios_size);
 888         if (vbios == NULL) {
 889                 dev_err(&pdev->dev, "Video BIOS not available\n");
 890                 return false;
 891         }
 892         if (vbios_size <= 0x65)
 893                 goto error;
 894         /*
 895          * The user can ignore the LVDS bit in the BIOS and force the display
 896          * type.
 897          */
 898         if (!(vbios[0x65] & 0x1) &&
 899             (!xgifb_info->display2_force ||
 900              xgifb_info->display2 != XGIFB_DISP_LCD)) {
 901                 vfree(vbios);
 902                 return false;
 903         }
 904         if (vbios_size <= 0x317)
 905                 goto error;
 906         i = vbios[0x316] | (vbios[0x317] << 8);
 907         if (vbios_size <= i - 1)
 908                 goto error;
 909         j = vbios[i - 1];
 910         if (j == 0)
 911                 goto error;
 912         if (j == 0xff)
 913                 j = 1;
 914         /*
 915          * Read the LVDS table index scratch register set by the BIOS.
 916          */
 917         entry = xgifb_reg_get(xgifb_info->dev_info.P3d4, 0x36);
 918         if (entry >= j)
 919                 entry = 0;
 920         i += entry * 25;
 921         lvds = &xgifb_info->lvds_data;
 922         if (vbios_size <= i + 24)
 923                 goto error;
 924         lvds->LVDS_Capability   = vbios[i]      | (vbios[i + 1] << 8);
 925         lvds->LVDSHT            = vbios[i + 2]  | (vbios[i + 3] << 8);
 926         lvds->LVDSVT            = vbios[i + 4]  | (vbios[i + 5] << 8);
 927         lvds->LVDSHDE           = vbios[i + 6]  | (vbios[i + 7] << 8);
 928         lvds->LVDSVDE           = vbios[i + 8]  | (vbios[i + 9] << 8);
 929         lvds->LVDSHFP           = vbios[i + 10] | (vbios[i + 11] << 8);
 930         lvds->LVDSVFP           = vbios[i + 12] | (vbios[i + 13] << 8);
 931         lvds->LVDSHSYNC         = vbios[i + 14] | (vbios[i + 15] << 8);
 932         lvds->LVDSVSYNC         = vbios[i + 16] | (vbios[i + 17] << 8);
 933         lvds->VCLKData1         = vbios[i + 18];
 934         lvds->VCLKData2         = vbios[i + 19];
 935         lvds->PSC_S1            = vbios[i + 20];
 936         lvds->PSC_S2            = vbios[i + 21];
 937         lvds->PSC_S3            = vbios[i + 22];
 938         lvds->PSC_S4            = vbios[i + 23];
 939         lvds->PSC_S5            = vbios[i + 24];
 940         vfree(vbios);
 941         return true;
 942 error:
 943         dev_err(&pdev->dev, "Video BIOS corrupted\n");
 944         vfree(vbios);
 945         return false;
 946 }
 947
 948 static void XGINew_ChkSenseStatus(struct vb_device_info *pVBInfo)
 949 {
 950         unsigned short tempbx = 0, temp, tempcx, CR3CData;
 951
 952         temp = xgifb_reg_get(pVBInfo->P3d4, 0x32);
 953
 954         if (temp & Monitor1Sense)
 955                 tempbx |= ActiveCRT1;
 956         if (temp & LCDSense)
 957                 tempbx |= ActiveLCD;
 958         if (temp & Monitor2Sense)
 959                 tempbx |= ActiveCRT2;
 960         if (temp & TVSense) {
 961                 tempbx |= ActiveTV;
 962                 if (temp & AVIDEOSense)
 963                         tempbx |= (ActiveAVideo << 8);
 964                 if (temp & SVIDEOSense)
 965                         tempbx |= (ActiveSVideo << 8);
 966                 if (temp & SCARTSense)
 967                         tempbx |= (ActiveSCART << 8);
 968                 if (temp & HiTVSense)
 969                         tempbx |= (ActiveHiTV << 8);
 970                 if (temp & YPbPrSense)
 971                         tempbx |= (ActiveYPbPr << 8);
 972         }
 973
 974         tempcx = xgifb_reg_get(pVBInfo->P3d4, 0x3d);
 975         tempcx |= (xgifb_reg_get(pVBInfo->P3d4, 0x3e) << 8);
 976
 977         if (tempbx & tempcx) {
 978                 CR3CData = xgifb_reg_get(pVBInfo->P3d4, 0x3c);
 979                 if (!(CR3CData & DisplayDeviceFromCMOS))
 980                         tempcx = 0x1FF0;
 981         } else {
 982                 tempcx = 0x1FF0;
 983         }
 984
 985         tempbx &= tempcx;
 986         xgifb_reg_set(pVBInfo->P3d4, 0x3d, (tempbx & 0x00FF));
 987         xgifb_reg_set(pVBInfo->P3d4, 0x3e, ((tempbx & 0xFF00) >> 8));
 988 }
 989
 990 static void XGINew_SetModeScratch(struct vb_device_info *pVBInfo)
 991 {
 992         unsigned short temp, tempcl = 0, tempch = 0, CR31Data, CR38Data;
 993
 994         temp = xgifb_reg_get(pVBInfo->P3d4, 0x3d);
 995         temp |= xgifb_reg_get(pVBInfo->P3d4, 0x3e) << 8;
 996         temp |= (xgifb_reg_get(pVBInfo->P3d4, 0x31) & (DriverMode >> 8)) << 8;
 997
 998         if (pVBInfo->IF_DEF_CRT2Monitor == 1) {
 999                 if (temp & ActiveCRT2)
1000                         tempcl = SetCRT2ToRAMDAC;
1001         }
1002
1003         if (temp & ActiveLCD) {
1004                 tempcl |= SetCRT2ToLCD;
1005                 if (temp & DriverMode) {
1006                         if (temp & ActiveTV) {
1007                                 tempch = SetToLCDA | EnableDualEdge;
1008                                 temp ^= SetCRT2ToLCD;
1009
1010                                 if ((temp >> 8) & ActiveAVideo)
1011                                         tempcl |= SetCRT2ToAVIDEO;
1012                                 if ((temp >> 8) & ActiveSVideo)
1013                                         tempcl |= SetCRT2ToSVIDEO;
1014                                 if ((temp >> 8) & ActiveSCART)
1015                                         tempcl |= SetCRT2ToSCART;
1016
1017                                 if (pVBInfo->IF_DEF_HiVision == 1) {
1018                                         if ((temp >> 8) & ActiveHiTV)
1019                                                 tempcl |= SetCRT2ToHiVision;
1020                                 }
1021
1022                                 if (pVBInfo->IF_DEF_YPbPr == 1) {
1023                                         if ((temp >> 8) & ActiveYPbPr)
1024                                                 tempch |= SetYPbPr;
1025                                 }
1026                         }
1027                 }
1028         } else {
1029                 if ((temp >> 8) & ActiveAVideo)
1030                         tempcl |= SetCRT2ToAVIDEO;
1031                 if ((temp >> 8) & ActiveSVideo)
1032                         tempcl |= SetCRT2ToSVIDEO;
1033                 if ((temp >> 8) & ActiveSCART)
1034                         tempcl |= SetCRT2ToSCART;
1035
1036                 if (pVBInfo->IF_DEF_HiVision == 1) {
1037                         if ((temp >> 8) & ActiveHiTV)
1038                                 tempcl |= SetCRT2ToHiVision;
1039                 }
1040
1041                 if (pVBInfo->IF_DEF_YPbPr == 1) {
1042                         if ((temp >> 8) & ActiveYPbPr)
1043                                 tempch |= SetYPbPr;
1044                 }
1045         }
1046
1047         tempcl |= SetSimuScanMode;
1048         if ((!(temp & ActiveCRT1)) && ((temp & ActiveLCD) || (temp & ActiveTV)
1049                         || (temp & ActiveCRT2)))
1050                 tempcl ^= (SetSimuScanMode | SwitchCRT2);
1051         if ((temp & ActiveLCD) && (temp & ActiveTV))
1052                 tempcl ^= (SetSimuScanMode | SwitchCRT2);
1053         xgifb_reg_set(pVBInfo->P3d4, 0x30, tempcl);
1054
1055         CR31Data = xgifb_reg_get(pVBInfo->P3d4, 0x31);
1056         CR31Data &= ~(SetNotSimuMode >> 8);
1057         if (!(temp & ActiveCRT1))
1058                 CR31Data |= (SetNotSimuMode >> 8);
1059         CR31Data &= ~(DisableCRT2Display >> 8);
1060         if (!((temp & ActiveLCD) || (temp & ActiveTV) || (temp & ActiveCRT2)))
1061                 CR31Data |= (DisableCRT2Display >> 8);
1062         xgifb_reg_set(pVBInfo->P3d4, 0x31, CR31Data);
1063
1064         CR38Data = xgifb_reg_get(pVBInfo->P3d4, 0x38);
1065         CR38Data &= ~SetYPbPr;
1066         CR38Data |= tempch;
1067         xgifb_reg_set(pVBInfo->P3d4, 0x38, CR38Data);
1068
1069 }
1070
1071 static unsigned short XGINew_SenseLCD(struct xgi_hw_device_info
1072                                                         *HwDeviceExtension,
1073                                       struct vb_device_info *pVBInfo)
1074 {
1075         unsigned short temp = HwDeviceExtension->ulCRT2LCDType;
1076
1077         switch (HwDeviceExtension->ulCRT2LCDType) {
1078         case LCD_640x480:
1079         case LCD_1024x600:
1080         case LCD_1152x864:
1081         case LCD_1280x960:
1082         case LCD_1152x768:
1083         case LCD_1920x1440:
1084         case LCD_2048x1536:
1085                 temp = 0; /* overwrite used ulCRT2LCDType */
1086                 break;
1087         case LCD_UNKNOWN: /* unknown lcd, do nothing */
1088                 return 0;
1089         }
1090         xgifb_reg_and_or(pVBInfo->P3d4, 0x36, 0xF0, temp);
1091         return 1;
1092 }
1093
1094 static void XGINew_GetXG21Sense(struct pci_dev *pdev,
1095                 struct vb_device_info *pVBInfo)
1096 {
1097         struct xgifb_video_info *xgifb_info = pci_get_drvdata(pdev);
1098         unsigned char Temp;
1099
1100         if (xgifb_read_vbios(pdev)) { /* For XG21 LVDS */
1101                 xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
1102                 /* LVDS on chip */
1103                 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xC0);
1104         } else {
1105                 /* Enable GPIOA/B read  */
1106                 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x03, 0x03);
1107                 Temp = xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0xC0;
1108                 if (Temp == 0xC0) { /* DVI & DVO GPIOA/B pull high */
1109                         XGINew_SenseLCD(&xgifb_info->hw_info, pVBInfo);
1110                         xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
1111                         /* Enable read GPIOF */
1112                         xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x20, 0x20);
1113                         if (xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0x04)
1114                                 Temp = 0xA0; /* Only DVO on chip */
1115                         else
1116                                 Temp = 0x80; /* TMDS on chip */
1117                         xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, Temp);
1118                         /* Disable read GPIOF */
1119                         xgifb_reg_and(pVBInfo->P3d4, 0x4A, ~0x20);
1120                 }
1121         }
1122 }
1123
1124 static void XGINew_GetXG27Sense(struct vb_device_info *pVBInfo)
1125 {
1126         unsigned char Temp, bCR4A;
1127
1128         bCR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
1129         /* Enable GPIOA/B/C read  */
1130         xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x07, 0x07);
1131         Temp = xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0x07;
1132         xgifb_reg_set(pVBInfo->P3d4, 0x4A, bCR4A);
1133
1134         if (Temp <= 0x02) {
1135                 /* LVDS setting */
1136                 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xC0);
1137                 xgifb_reg_set(pVBInfo->P3d4, 0x30, 0x21);
1138         } else {
1139                 /* TMDS/DVO setting */
1140                 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xA0);
1141         }
1142         xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
1143
1144 }
1145
1146 static unsigned char GetXG21FPBits(struct vb_device_info *pVBInfo)
1147 {
1148         unsigned char CR38, CR4A, temp;
1149
1150         CR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
1151         /* enable GPIOE read */
1152         xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x10, 0x10);
1153         CR38 = xgifb_reg_get(pVBInfo->P3d4, 0x38);
1154         temp = 0;
1155         if ((CR38 & 0xE0) > 0x80) {
1156                 temp = xgifb_reg_get(pVBInfo->P3d4, 0x48);
1157                 temp &= 0x08;
1158                 temp >>= 3;
1159         }
1160
1161         xgifb_reg_set(pVBInfo->P3d4, 0x4A, CR4A);
1162
1163         return temp;
1164 }
1165
1166 static unsigned char GetXG27FPBits(struct vb_device_info *pVBInfo)
1167 {
1168         unsigned char CR4A, temp;
1169
1170         CR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
1171         /* enable GPIOA/B/C read */
1172         xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x03, 0x03);
1173         temp = xgifb_reg_get(pVBInfo->P3d4, 0x48);
1174         if (temp > 2)
1175                 temp = ((temp & 0x04) >> 1) | ((~temp) & 0x01);
1176
1177         xgifb_reg_set(pVBInfo->P3d4, 0x4A, CR4A);
1178
1179         return temp;
1180 }
1181
1182 static bool xgifb_bridge_is_on(struct vb_device_info *vb_info)
1183 {
1184         u8 flag;
1185
1186         flag = xgifb_reg_get(vb_info->Part4Port, 0x00);
1187         return flag == 1 || flag == 2;
1188 }
1189
1190 unsigned char XGIInitNew(struct pci_dev *pdev)
1191 {
1192         struct xgifb_video_info *xgifb_info = pci_get_drvdata(pdev);
1193         struct xgi_hw_device_info *HwDeviceExtension = &xgifb_info->hw_info;
1194         struct vb_device_info VBINF;
1195         struct vb_device_info *pVBInfo = &VBINF;
1196         unsigned char i, temp = 0, temp1;
1197
1198         pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress;
1199
1200         if (pVBInfo->FBAddr == NULL) {
1201                 dev_dbg(&pdev->dev, "pVBInfo->FBAddr == 0\n");
1202                 return 0;
1203         }
1204
1205         XGIRegInit(pVBInfo, xgifb_info->vga_base);
1206
1207         outb(0x67, pVBInfo->P3c2);
1208
1209         InitTo330Pointer(HwDeviceExtension->jChipType, pVBInfo);
1210
1211         /* Openkey */
1212         xgifb_reg_set(pVBInfo->P3c4, 0x05, 0x86);
1213
1214         /* GetXG21Sense (GPIO) */
1215         if (HwDeviceExtension->jChipType == XG21)
1216                 XGINew_GetXG21Sense(pdev, pVBInfo);
1217
1218         if (HwDeviceExtension->jChipType == XG27)
1219                 XGINew_GetXG27Sense(pVBInfo);
1220
1221         /* Reset Extended register */
1222
1223         for (i = 0x06; i < 0x20; i++)
1224                 xgifb_reg_set(pVBInfo->P3c4, i, 0);
1225
1226         for (i = 0x21; i <= 0x27; i++)
1227                 xgifb_reg_set(pVBInfo->P3c4, i, 0);
1228
1229         for (i = 0x31; i <= 0x3B; i++)
1230                 xgifb_reg_set(pVBInfo->P3c4, i, 0);
1231
1232         /* Auto over driver for XG42 */
1233         if (HwDeviceExtension->jChipType == XG42)
1234                 xgifb_reg_set(pVBInfo->P3c4, 0x3B, 0xC0);
1235
1236         for (i = 0x79; i <= 0x7C; i++)
1237                 xgifb_reg_set(pVBInfo->P3d4, i, 0);
1238
1239         if (HwDeviceExtension->jChipType >= XG20)
1240                 xgifb_reg_set(pVBInfo->P3d4, 0x97, pVBInfo->XGINew_CR97);
1241
1242         /* SetDefExt1Regs begin */
1243         xgifb_reg_set(pVBInfo->P3c4, 0x07, XGI330_SR07);
1244         if (HwDeviceExtension->jChipType == XG27) {
1245                 xgifb_reg_set(pVBInfo->P3c4, 0x40, XG27_SR40);
1246                 xgifb_reg_set(pVBInfo->P3c4, 0x41, XG27_SR41);
1247         }
1248         xgifb_reg_set(pVBInfo->P3c4, 0x11, 0x0F);
1249         xgifb_reg_set(pVBInfo->P3c4, 0x1F, XGI330_SR1F);
1250         /* Frame buffer can read/write SR20 */
1251         xgifb_reg_set(pVBInfo->P3c4, 0x20, 0xA0);
1252         /* H/W request for slow corner chip */
1253         xgifb_reg_set(pVBInfo->P3c4, 0x36, 0x70);
1254         if (HwDeviceExtension->jChipType == XG27)
1255                 xgifb_reg_set(pVBInfo->P3c4, 0x36, XG27_SR36);
1256
1257         if (HwDeviceExtension->jChipType < XG20) {
1258                 u32 Temp;
1259
1260                 /* Set AGP customize registers (in SetDefAGPRegs) Start */
1261                 for (i = 0x47; i <= 0x4C; i++)
1262                         xgifb_reg_set(pVBInfo->P3d4,
1263                                       i,
1264                                       XGI340_AGPReg[i - 0x47]);
1265
1266                 for (i = 0x70; i <= 0x71; i++)
1267                         xgifb_reg_set(pVBInfo->P3d4,
1268                                       i,
1269                                       XGI340_AGPReg[6 + i - 0x70]);
1270
1271                 for (i = 0x74; i <= 0x77; i++)
1272                         xgifb_reg_set(pVBInfo->P3d4,
1273                                       i,
1274                                       XGI340_AGPReg[8 + i - 0x74]);
1275
1276                 pci_read_config_dword(pdev, 0x50, &Temp);
1277                 Temp >>= 20;
1278                 Temp &= 0xF;
1279
1280                 if (Temp == 1)
1281                         xgifb_reg_set(pVBInfo->P3d4, 0x48, 0x20); /* CR48 */
1282         } /* != XG20 */
1283
1284         /* Set PCI */
1285         xgifb_reg_set(pVBInfo->P3c4, 0x23, XGI330_SR23);
1286         xgifb_reg_set(pVBInfo->P3c4, 0x24, XGI330_SR24);
1287         xgifb_reg_set(pVBInfo->P3c4, 0x25, 0);
1288
1289         if (HwDeviceExtension->jChipType < XG20) {
1290                 /* Set VB */
1291                 XGI_UnLockCRT2(pVBInfo);
1292                 /* disable VideoCapture */
1293                 xgifb_reg_and_or(pVBInfo->Part0Port, 0x3F, 0xEF, 0x00);
1294                 xgifb_reg_set(pVBInfo->Part1Port, 0x00, 0x00);
1295                 /* chk if BCLK>=100MHz */
1296                 temp1 = xgifb_reg_get(pVBInfo->P3d4, 0x7B);
1297
1298                 xgifb_reg_set(pVBInfo->Part1Port,
1299                               0x02, XGI330_CRT2Data_1_2);
1300
1301                 xgifb_reg_set(pVBInfo->Part1Port, 0x2E, 0x08); /* use VB */
1302         } /* != XG20 */
1303
1304         xgifb_reg_set(pVBInfo->P3c4, 0x27, 0x1F);
1305
1306         if ((HwDeviceExtension->jChipType == XG42) &&
1307             XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo) != 0) {
1308                 /* Not DDR */
1309                 xgifb_reg_set(pVBInfo->P3c4,
1310                               0x31,
1311                               (XGI330_SR31 & 0x3F) | 0x40);
1312                 xgifb_reg_set(pVBInfo->P3c4,
1313                               0x32,
1314                               (XGI330_SR32 & 0xFC) | 0x01);
1315         } else {
1316                 xgifb_reg_set(pVBInfo->P3c4, 0x31, XGI330_SR31);
1317                 xgifb_reg_set(pVBInfo->P3c4, 0x32, XGI330_SR32);
1318         }
1319         xgifb_reg_set(pVBInfo->P3c4, 0x33, XGI330_SR33);
1320
1321         if (HwDeviceExtension->jChipType < XG20) {
1322                 if (xgifb_bridge_is_on(pVBInfo)) {
1323                         xgifb_reg_set(pVBInfo->Part2Port, 0x00, 0x1C);
1324                         xgifb_reg_set(pVBInfo->Part4Port,
1325                                       0x0D, XGI330_CRT2Data_4_D);
1326                         xgifb_reg_set(pVBInfo->Part4Port,
1327                                       0x0E, XGI330_CRT2Data_4_E);
1328                         xgifb_reg_set(pVBInfo->Part4Port,
1329                                       0x10, XGI330_CRT2Data_4_10);
1330                         xgifb_reg_set(pVBInfo->Part4Port, 0x0F, 0x3F);
1331                         XGI_LockCRT2(pVBInfo);
1332                 }
1333         } /* != XG20 */
1334
1335         XGI_SenseCRT1(pVBInfo);
1336
1337         if (HwDeviceExtension->jChipType == XG21) {
1338
1339                 xgifb_reg_and_or(pVBInfo->P3d4,
1340                                  0x32,
1341                                  ~Monitor1Sense,
1342                                  Monitor1Sense); /* Z9 default has CRT */
1343                 temp = GetXG21FPBits(pVBInfo);
1344                 xgifb_reg_and_or(pVBInfo->P3d4, 0x37, ~0x01, temp);
1345
1346         }
1347         if (HwDeviceExtension->jChipType == XG27) {
1348                 xgifb_reg_and_or(pVBInfo->P3d4,
1349                                  0x32,
1350                                  ~Monitor1Sense,
1351                                  Monitor1Sense); /* Z9 default has CRT */
1352                 temp = GetXG27FPBits(pVBInfo);
1353                 xgifb_reg_and_or(pVBInfo->P3d4, 0x37, ~0x03, temp);
1354         }
1355
1356         pVBInfo->ram_type = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
1357
1358         XGINew_SetDRAMDefaultRegister340(HwDeviceExtension,
1359                                          pVBInfo->P3d4,
1360                                          pVBInfo);
1361
1362         XGINew_SetDRAMSize_340(xgifb_info, HwDeviceExtension, pVBInfo);
1363
1364         xgifb_reg_set(pVBInfo->P3c4, 0x22, 0xfa);
1365         xgifb_reg_set(pVBInfo->P3c4, 0x21, 0xa3);
1366
1367         XGINew_ChkSenseStatus(pVBInfo);
1368         XGINew_SetModeScratch(pVBInfo);
1369
1370         xgifb_reg_set(pVBInfo->P3d4, 0x8c, 0x87);
1371
1372         return 1;
1373 } /* end of init */