2 * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
22 * Purpose: rf function code
29 * IFRFbWriteEmbedded - Embedded write RF register via MAC
42 static int msglevel =MSG_LEVEL_INFO;
43 //static int msglevel =MSG_LEVEL_DEBUG;
44 #define BY_AL2230_REG_LEN 23 //24bit
45 #define CB_AL2230_INIT_SEQ 15
46 #define AL2230_PWR_IDX_LEN 64
48 #define BY_AL7230_REG_LEN 23 //24bit
49 #define CB_AL7230_INIT_SEQ 16
50 #define AL7230_PWR_IDX_LEN 64
53 #define BY_VT3226_REG_LEN 23
54 #define CB_VT3226_INIT_SEQ 11
55 #define VT3226_PWR_IDX_LEN 64
59 #define BY_VT3342_REG_LEN 23
60 #define CB_VT3342_INIT_SEQ 13
61 #define VT3342_PWR_IDX_LEN 64
64 u8 abyAL2230InitTable[CB_AL2230_INIT_SEQ][3] = {
70 {0x0F, 0x4D, 0xC5}, //RobertYu:20060814
82 u8 abyAL2230ChannelTable0[CB_MAX_CHANNEL_24G][3] = {
83 {0x03, 0xF7, 0x90}, // channel = 1, Tf = 2412MHz
84 {0x03, 0xF7, 0x90}, // channel = 2, Tf = 2417MHz
85 {0x03, 0xE7, 0x90}, // channel = 3, Tf = 2422MHz
86 {0x03, 0xE7, 0x90}, // channel = 4, Tf = 2427MHz
87 {0x03, 0xF7, 0xA0}, // channel = 5, Tf = 2432MHz
88 {0x03, 0xF7, 0xA0}, // channel = 6, Tf = 2437MHz
89 {0x03, 0xE7, 0xA0}, // channel = 7, Tf = 2442MHz
90 {0x03, 0xE7, 0xA0}, // channel = 8, Tf = 2447MHz
91 {0x03, 0xF7, 0xB0}, // channel = 9, Tf = 2452MHz
92 {0x03, 0xF7, 0xB0}, // channel = 10, Tf = 2457MHz
93 {0x03, 0xE7, 0xB0}, // channel = 11, Tf = 2462MHz
94 {0x03, 0xE7, 0xB0}, // channel = 12, Tf = 2467MHz
95 {0x03, 0xF7, 0xC0}, // channel = 13, Tf = 2472MHz
96 {0x03, 0xE7, 0xC0} // channel = 14, Tf = 2412M
99 u8 abyAL2230ChannelTable1[CB_MAX_CHANNEL_24G][3] = {
100 {0x03, 0x33, 0x31}, // channel = 1, Tf = 2412MHz
101 {0x0B, 0x33, 0x31}, // channel = 2, Tf = 2417MHz
102 {0x03, 0x33, 0x31}, // channel = 3, Tf = 2422MHz
103 {0x0B, 0x33, 0x31}, // channel = 4, Tf = 2427MHz
104 {0x03, 0x33, 0x31}, // channel = 5, Tf = 2432MHz
105 {0x0B, 0x33, 0x31}, // channel = 6, Tf = 2437MHz
106 {0x03, 0x33, 0x31}, // channel = 7, Tf = 2442MHz
107 {0x0B, 0x33, 0x31}, // channel = 8, Tf = 2447MHz
108 {0x03, 0x33, 0x31}, // channel = 9, Tf = 2452MHz
109 {0x0B, 0x33, 0x31}, // channel = 10, Tf = 2457MHz
110 {0x03, 0x33, 0x31}, // channel = 11, Tf = 2462MHz
111 {0x0B, 0x33, 0x31}, // channel = 12, Tf = 2467MHz
112 {0x03, 0x33, 0x31}, // channel = 13, Tf = 2472MHz
113 {0x06, 0x66, 0x61} // channel = 14, Tf = 2412M
116 // 40MHz reference frequency
117 // Need to Pull PLLON(PE3) low when writing channel registers through 3-wire.
118 u8 abyAL7230InitTable[CB_AL7230_INIT_SEQ][3] = {
119 {0x20, 0x37, 0x90}, // Channel1 // Need modify for 11a
120 {0x13, 0x33, 0x31}, // Channel1 // Need modify for 11a
121 {0x84, 0x1F, 0xF2}, // Need modify for 11a: 451FE2
122 {0x3F, 0xDF, 0xA3}, // Need modify for 11a: 5FDFA3
123 {0x7F, 0xD7, 0x84}, // 11b/g // Need modify for 11a
124 //0x802B4500+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11a: 8D1B45
125 // RoberYu:20050113, Rev0.47 Regsiter Setting Guide
126 {0x80, 0x2B, 0x55}, // Need modify for 11a: 8D1B55
128 {0xCE, 0x02, 0x07}, // Need modify for 11a: 860207
131 {0xE0, 0x00, 0x0A}, // Need modify for 11a: E0600A
132 {0x08, 0x03, 0x1B}, // init 0x080B1B00 => 0x080F1B00 for 3 wire control TxGain(D10)
133 //0x00093C00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11a: 00143C
134 // RoberYu:20050113, Rev0.47 Regsiter Setting Guide
135 {0x00, 0x0A, 0x3C}, // Need modify for 11a: 00143C
138 {0x1A, 0xBA, 0x8F} // Need modify for 11a: 12BACF
141 u8 abyAL7230InitTableAMode[CB_AL7230_INIT_SEQ][3] = {
142 {0x2F, 0xF5, 0x20}, // Channel184 // Need modify for 11b/g
143 {0x00, 0x00, 0x01}, // Channel184 // Need modify for 11b/g
144 {0x45, 0x1F, 0xE2}, // Need modify for 11b/g
145 {0x5F, 0xDF, 0xA3}, // Need modify for 11b/g
146 {0x6F, 0xD7, 0x84}, // 11a // Need modify for 11b/g
147 {0x85, 0x3F, 0x55}, // Need modify for 11b/g, RoberYu:20050113
149 {0xCE, 0x02, 0x07}, // Need modify for 11b/g
152 {0xE0, 0x60, 0x0A}, // Need modify for 11b/g
153 {0x08, 0x03, 0x1B}, // init 0x080B1B00 => 0x080F1B00 for 3 wire control TxGain(D10)
154 {0x00, 0x14, 0x7C}, // Need modify for 11b/g
157 {0x12, 0xBA, 0xCF} // Need modify for 11b/g
160 u8 abyAL7230ChannelTable0[CB_MAX_CHANNEL][3] = {
161 {0x20, 0x37, 0x90}, // channel = 1, Tf = 2412MHz
162 {0x20, 0x37, 0x90}, // channel = 2, Tf = 2417MHz
163 {0x20, 0x37, 0x90}, // channel = 3, Tf = 2422MHz
164 {0x20, 0x37, 0x90}, // channel = 4, Tf = 2427MHz
165 {0x20, 0x37, 0xA0}, // channel = 5, Tf = 2432MHz
166 {0x20, 0x37, 0xA0}, // channel = 6, Tf = 2437MHz
167 {0x20, 0x37, 0xA0}, // channel = 7, Tf = 2442MHz
168 {0x20, 0x37, 0xA0}, // channel = 8, Tf = 2447MHz //RobertYu: 20050218, update for APNode 0.49
169 {0x20, 0x37, 0xB0}, // channel = 9, Tf = 2452MHz //RobertYu: 20050218, update for APNode 0.49
170 {0x20, 0x37, 0xB0}, // channel = 10, Tf = 2457MHz //RobertYu: 20050218, update for APNode 0.49
171 {0x20, 0x37, 0xB0}, // channel = 11, Tf = 2462MHz //RobertYu: 20050218, update for APNode 0.49
172 {0x20, 0x37, 0xB0}, // channel = 12, Tf = 2467MHz //RobertYu: 20050218, update for APNode 0.49
173 {0x20, 0x37, 0xC0}, // channel = 13, Tf = 2472MHz //RobertYu: 20050218, update for APNode 0.49
174 {0x20, 0x37, 0xC0}, // channel = 14, Tf = 2484MHz
176 // 4.9G => Ch 183, 184, 185, 187, 188, 189, 192, 196 (Value:15 ~ 22)
177 {0x0F, 0xF5, 0x20}, // channel = 183, Tf = 4915MHz (15)
178 {0x2F, 0xF5, 0x20}, // channel = 184, Tf = 4920MHz (16)
179 {0x0F, 0xF5, 0x20}, // channel = 185, Tf = 4925MHz (17)
180 {0x0F, 0xF5, 0x20}, // channel = 187, Tf = 4935MHz (18)
181 {0x2F, 0xF5, 0x20}, // channel = 188, Tf = 4940MHz (19)
182 {0x0F, 0xF5, 0x20}, // channel = 189, Tf = 4945MHz (20)
183 {0x2F, 0xF5, 0x30}, // channel = 192, Tf = 4960MHz (21)
184 {0x2F, 0xF5, 0x30}, // channel = 196, Tf = 4980MHz (22)
186 // 5G => Ch 7, 8, 9, 11, 12, 16, 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64,
187 // 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165 (Value 23 ~ 56)
189 {0x0F, 0xF5, 0x40}, // channel = 7, Tf = 5035MHz (23)
190 {0x2F, 0xF5, 0x40}, // channel = 8, Tf = 5040MHz (24)
191 {0x0F, 0xF5, 0x40}, // channel = 9, Tf = 5045MHz (25)
192 {0x0F, 0xF5, 0x40}, // channel = 11, Tf = 5055MHz (26)
193 {0x2F, 0xF5, 0x40}, // channel = 12, Tf = 5060MHz (27)
194 {0x2F, 0xF5, 0x50}, // channel = 16, Tf = 5080MHz (28)
195 {0x2F, 0xF5, 0x60}, // channel = 34, Tf = 5170MHz (29)
196 {0x2F, 0xF5, 0x60}, // channel = 36, Tf = 5180MHz (30)
197 {0x2F, 0xF5, 0x70}, // channel = 38, Tf = 5190MHz (31) //RobertYu: 20050218, update for APNode 0.49
198 {0x2F, 0xF5, 0x70}, // channel = 40, Tf = 5200MHz (32)
199 {0x2F, 0xF5, 0x70}, // channel = 42, Tf = 5210MHz (33)
200 {0x2F, 0xF5, 0x70}, // channel = 44, Tf = 5220MHz (34)
201 {0x2F, 0xF5, 0x70}, // channel = 46, Tf = 5230MHz (35)
202 {0x2F, 0xF5, 0x70}, // channel = 48, Tf = 5240MHz (36)
203 {0x2F, 0xF5, 0x80}, // channel = 52, Tf = 5260MHz (37)
204 {0x2F, 0xF5, 0x80}, // channel = 56, Tf = 5280MHz (38)
205 {0x2F, 0xF5, 0x80}, // channel = 60, Tf = 5300MHz (39)
206 {0x2F, 0xF5, 0x90}, // channel = 64, Tf = 5320MHz (40)
208 {0x2F, 0xF5, 0xC0}, // channel = 100, Tf = 5500MHz (41)
209 {0x2F, 0xF5, 0xC0}, // channel = 104, Tf = 5520MHz (42)
210 {0x2F, 0xF5, 0xC0}, // channel = 108, Tf = 5540MHz (43)
211 {0x2F, 0xF5, 0xD0}, // channel = 112, Tf = 5560MHz (44)
212 {0x2F, 0xF5, 0xD0}, // channel = 116, Tf = 5580MHz (45)
213 {0x2F, 0xF5, 0xD0}, // channel = 120, Tf = 5600MHz (46)
214 {0x2F, 0xF5, 0xE0}, // channel = 124, Tf = 5620MHz (47)
215 {0x2F, 0xF5, 0xE0}, // channel = 128, Tf = 5640MHz (48)
216 {0x2F, 0xF5, 0xE0}, // channel = 132, Tf = 5660MHz (49)
217 {0x2F, 0xF5, 0xF0}, // channel = 136, Tf = 5680MHz (50)
218 {0x2F, 0xF5, 0xF0}, // channel = 140, Tf = 5700MHz (51)
219 {0x2F, 0xF6, 0x00}, // channel = 149, Tf = 5745MHz (52)
220 {0x2F, 0xF6, 0x00}, // channel = 153, Tf = 5765MHz (53)
221 {0x2F, 0xF6, 0x00}, // channel = 157, Tf = 5785MHz (54)
222 {0x2F, 0xF6, 0x10}, // channel = 161, Tf = 5805MHz (55)
223 {0x2F, 0xF6, 0x10} // channel = 165, Tf = 5825MHz (56)
226 u8 abyAL7230ChannelTable1[CB_MAX_CHANNEL][3] = {
227 {0x13, 0x33, 0x31}, // channel = 1, Tf = 2412MHz
228 {0x1B, 0x33, 0x31}, // channel = 2, Tf = 2417MHz
229 {0x03, 0x33, 0x31}, // channel = 3, Tf = 2422MHz
230 {0x0B, 0x33, 0x31}, // channel = 4, Tf = 2427MHz
231 {0x13, 0x33, 0x31}, // channel = 5, Tf = 2432MHz
232 {0x1B, 0x33, 0x31}, // channel = 6, Tf = 2437MHz
233 {0x03, 0x33, 0x31}, // channel = 7, Tf = 2442MHz
234 {0x0B, 0x33, 0x31}, // channel = 8, Tf = 2447MHz
235 {0x13, 0x33, 0x31}, // channel = 9, Tf = 2452MHz
236 {0x1B, 0x33, 0x31}, // channel = 10, Tf = 2457MHz
237 {0x03, 0x33, 0x31}, // channel = 11, Tf = 2462MHz
238 {0x0B, 0x33, 0x31}, // channel = 12, Tf = 2467MHz
239 {0x13, 0x33, 0x31}, // channel = 13, Tf = 2472MHz
240 {0x06, 0x66, 0x61}, // channel = 14, Tf = 2484MHz
242 // 4.9G => Ch 183, 184, 185, 187, 188, 189, 192, 196 (Value:15 ~ 22)
243 {0x1D, 0x55, 0x51}, // channel = 183, Tf = 4915MHz (15)
244 {0x00, 0x00, 0x01}, // channel = 184, Tf = 4920MHz (16)
245 {0x02, 0xAA, 0xA1}, // channel = 185, Tf = 4925MHz (17)
246 {0x08, 0x00, 0x01}, // channel = 187, Tf = 4935MHz (18)
247 {0x0A, 0xAA, 0xA1}, // channel = 188, Tf = 4940MHz (19)
248 {0x0D, 0x55, 0x51}, // channel = 189, Tf = 4945MHz (20)
249 {0x15, 0x55, 0x51}, // channel = 192, Tf = 4960MHz (21)
250 {0x00, 0x00, 0x01}, // channel = 196, Tf = 4980MHz (22)
252 // 5G => Ch 7, 8, 9, 11, 12, 16, 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64,
253 // 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165 (Value 23 ~ 56)
254 {0x1D, 0x55, 0x51}, // channel = 7, Tf = 5035MHz (23)
255 {0x00, 0x00, 0x01}, // channel = 8, Tf = 5040MHz (24)
256 {0x02, 0xAA, 0xA1}, // channel = 9, Tf = 5045MHz (25)
257 {0x08, 0x00, 0x01}, // channel = 11, Tf = 5055MHz (26)
258 {0x0A, 0xAA, 0xA1}, // channel = 12, Tf = 5060MHz (27)
259 {0x15, 0x55, 0x51}, // channel = 16, Tf = 5080MHz (28)
260 {0x05, 0x55, 0x51}, // channel = 34, Tf = 5170MHz (29)
261 {0x0A, 0xAA, 0xA1}, // channel = 36, Tf = 5180MHz (30)
262 {0x10, 0x00, 0x01}, // channel = 38, Tf = 5190MHz (31)
263 {0x15, 0x55, 0x51}, // channel = 40, Tf = 5200MHz (32)
264 {0x1A, 0xAA, 0xA1}, // channel = 42, Tf = 5210MHz (33)
265 {0x00, 0x00, 0x01}, // channel = 44, Tf = 5220MHz (34)
266 {0x05, 0x55, 0x51}, // channel = 46, Tf = 5230MHz (35)
267 {0x0A, 0xAA, 0xA1}, // channel = 48, Tf = 5240MHz (36)
268 {0x15, 0x55, 0x51}, // channel = 52, Tf = 5260MHz (37)
269 {0x00, 0x00, 0x01}, // channel = 56, Tf = 5280MHz (38)
270 {0x0A, 0xAA, 0xA1}, // channel = 60, Tf = 5300MHz (39)
271 {0x15, 0x55, 0x51}, // channel = 64, Tf = 5320MHz (40)
272 {0x15, 0x55, 0x51}, // channel = 100, Tf = 5500MHz (41)
273 {0x00, 0x00, 0x01}, // channel = 104, Tf = 5520MHz (42)
274 {0x0A, 0xAA, 0xA1}, // channel = 108, Tf = 5540MHz (43)
275 {0x15, 0x55, 0x51}, // channel = 112, Tf = 5560MHz (44)
276 {0x00, 0x00, 0x01}, // channel = 116, Tf = 5580MHz (45)
277 {0x0A, 0xAA, 0xA1}, // channel = 120, Tf = 5600MHz (46)
278 {0x15, 0x55, 0x51}, // channel = 124, Tf = 5620MHz (47)
279 {0x00, 0x00, 0x01}, // channel = 128, Tf = 5640MHz (48)
280 {0x0A, 0xAA, 0xA1}, // channel = 132, Tf = 5660MHz (49)
281 {0x15, 0x55, 0x51}, // channel = 136, Tf = 5680MHz (50)
282 {0x00, 0x00, 0x01}, // channel = 140, Tf = 5700MHz (51)
283 {0x18, 0x00, 0x01}, // channel = 149, Tf = 5745MHz (52)
284 {0x02, 0xAA, 0xA1}, // channel = 153, Tf = 5765MHz (53)
285 {0x0D, 0x55, 0x51}, // channel = 157, Tf = 5785MHz (54)
286 {0x18, 0x00, 0x01}, // channel = 161, Tf = 5805MHz (55)
287 {0x02, 0xAA, 0xB1} // channel = 165, Tf = 5825MHz (56)
290 u8 abyAL7230ChannelTable2[CB_MAX_CHANNEL][3] = {
291 {0x7F, 0xD7, 0x84}, // channel = 1, Tf = 2412MHz
292 {0x7F, 0xD7, 0x84}, // channel = 2, Tf = 2417MHz
293 {0x7F, 0xD7, 0x84}, // channel = 3, Tf = 2422MHz
294 {0x7F, 0xD7, 0x84}, // channel = 4, Tf = 2427MHz
295 {0x7F, 0xD7, 0x84}, // channel = 5, Tf = 2432MHz
296 {0x7F, 0xD7, 0x84}, // channel = 6, Tf = 2437MHz
297 {0x7F, 0xD7, 0x84}, // channel = 7, Tf = 2442MHz
298 {0x7F, 0xD7, 0x84}, // channel = 8, Tf = 2447MHz
299 {0x7F, 0xD7, 0x84}, // channel = 9, Tf = 2452MHz
300 {0x7F, 0xD7, 0x84}, // channel = 10, Tf = 2457MHz
301 {0x7F, 0xD7, 0x84}, // channel = 11, Tf = 2462MHz
302 {0x7F, 0xD7, 0x84}, // channel = 12, Tf = 2467MHz
303 {0x7F, 0xD7, 0x84}, // channel = 13, Tf = 2472MHz
304 {0x7F, 0xD7, 0x84}, // channel = 14, Tf = 2484MHz
306 // 4.9G => Ch 183, 184, 185, 187, 188, 189, 192, 196 (Value:15 ~ 22)
307 {0x7F, 0xD7, 0x84}, // channel = 183, Tf = 4915MHz (15)
308 {0x6F, 0xD7, 0x84}, // channel = 184, Tf = 4920MHz (16)
309 {0x7F, 0xD7, 0x84}, // channel = 185, Tf = 4925MHz (17)
310 {0x7F, 0xD7, 0x84}, // channel = 187, Tf = 4935MHz (18)
311 {0x7F, 0xD7, 0x84}, // channel = 188, Tf = 4940MHz (19)
312 {0x7F, 0xD7, 0x84}, // channel = 189, Tf = 4945MHz (20)
313 {0x7F, 0xD7, 0x84}, // channel = 192, Tf = 4960MHz (21)
314 {0x6F, 0xD7, 0x84}, // channel = 196, Tf = 4980MHz (22)
316 // 5G => Ch 7, 8, 9, 11, 12, 16, 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64,
317 // 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165 (Value 23 ~ 56)
318 {0x7F, 0xD7, 0x84}, // channel = 7, Tf = 5035MHz (23)
319 {0x6F, 0xD7, 0x84}, // channel = 8, Tf = 5040MHz (24)
320 {0x7F, 0xD7, 0x84}, // channel = 9, Tf = 5045MHz (25)
321 {0x7F, 0xD7, 0x84}, // channel = 11, Tf = 5055MHz (26)
322 {0x7F, 0xD7, 0x84}, // channel = 12, Tf = 5060MHz (27)
323 {0x7F, 0xD7, 0x84}, // channel = 16, Tf = 5080MHz (28)
324 {0x7F, 0xD7, 0x84}, // channel = 34, Tf = 5170MHz (29)
325 {0x7F, 0xD7, 0x84}, // channel = 36, Tf = 5180MHz (30)
326 {0x7F, 0xD7, 0x84}, // channel = 38, Tf = 5190MHz (31)
327 {0x7F, 0xD7, 0x84}, // channel = 40, Tf = 5200MHz (32)
328 {0x7F, 0xD7, 0x84}, // channel = 42, Tf = 5210MHz (33)
329 {0x6F, 0xD7, 0x84}, // channel = 44, Tf = 5220MHz (34)
330 {0x7F, 0xD7, 0x84}, // channel = 46, Tf = 5230MHz (35)
331 {0x7F, 0xD7, 0x84}, // channel = 48, Tf = 5240MHz (36)
332 {0x7F, 0xD7, 0x84}, // channel = 52, Tf = 5260MHz (37)
333 {0x6F, 0xD7, 0x84}, // channel = 56, Tf = 5280MHz (38)
334 {0x7F, 0xD7, 0x84}, // channel = 60, Tf = 5300MHz (39)
335 {0x7F, 0xD7, 0x84}, // channel = 64, Tf = 5320MHz (40)
336 {0x7F, 0xD7, 0x84}, // channel = 100, Tf = 5500MHz (41)
337 {0x6F, 0xD7, 0x84}, // channel = 104, Tf = 5520MHz (42)
338 {0x7F, 0xD7, 0x84}, // channel = 108, Tf = 5540MHz (43)
339 {0x7F, 0xD7, 0x84}, // channel = 112, Tf = 5560MHz (44)
340 {0x6F, 0xD7, 0x84}, // channel = 116, Tf = 5580MHz (45)
341 {0x7F, 0xD7, 0x84}, // channel = 120, Tf = 5600MHz (46)
342 {0x7F, 0xD7, 0x84}, // channel = 124, Tf = 5620MHz (47)
343 {0x6F, 0xD7, 0x84}, // channel = 128, Tf = 5640MHz (48)
344 {0x7F, 0xD7, 0x84}, // channel = 132, Tf = 5660MHz (49)
345 {0x7F, 0xD7, 0x84}, // channel = 136, Tf = 5680MHz (50)
346 {0x6F, 0xD7, 0x84}, // channel = 140, Tf = 5700MHz (51)
347 {0x7F, 0xD7, 0x84}, // channel = 149, Tf = 5745MHz (52)
348 {0x7F, 0xD7, 0x84}, // channel = 153, Tf = 5765MHz (53)
349 {0x7F, 0xD7, 0x84}, // channel = 157, Tf = 5785MHz (54)
350 {0x7F, 0xD7, 0x84}, // channel = 161, Tf = 5805MHz (55)
351 {0x7F, 0xD7, 0x84} // channel = 165, Tf = 5825MHz (56)
354 ///{{RobertYu:20051111
355 u8 abyVT3226_InitTable[CB_VT3226_INIT_SEQ][3] = {
365 {0x00, 0x02, 0x39}, //RobertYu:20051116
369 u8 abyVT3226D0_InitTable[CB_VT3226_INIT_SEQ][3] = {
371 {0x03, 0x02, 0x21}, //RobertYu:20060327
375 {0x00, 0x71, 0xA5}, //RobertYu:20060103
376 {0x01, 0x15, 0xC6}, //RobertYu:20060420
377 {0x01, 0x2E, 0x07}, //RobertYu:20060420
378 {0x00, 0x58, 0x08}, //RobertYu:20060111
379 {0x00, 0x02, 0x79}, //RobertYu:20060420
380 {0x02, 0x01, 0xAA} //RobertYu:20060523
383 u8 abyVT3226_ChannelTable0[CB_MAX_CHANNEL_24G][3] = {
384 {0x01, 0x97, 0x83}, // channel = 1, Tf = 2412MHz
385 {0x01, 0x97, 0x83}, // channel = 2, Tf = 2417MHz
386 {0x01, 0x97, 0x93}, // channel = 3, Tf = 2422MHz
387 {0x01, 0x97, 0x93}, // channel = 4, Tf = 2427MHz
388 {0x01, 0x97, 0x93}, // channel = 5, Tf = 2432MHz
389 {0x01, 0x97, 0x93}, // channel = 6, Tf = 2437MHz
390 {0x01, 0x97, 0xA3}, // channel = 7, Tf = 2442MHz
391 {0x01, 0x97, 0xA3}, // channel = 8, Tf = 2447MHz
392 {0x01, 0x97, 0xA3}, // channel = 9, Tf = 2452MHz
393 {0x01, 0x97, 0xA3}, // channel = 10, Tf = 2457MHz
394 {0x01, 0x97, 0xB3}, // channel = 11, Tf = 2462MHz
395 {0x01, 0x97, 0xB3}, // channel = 12, Tf = 2467MHz
396 {0x01, 0x97, 0xB3}, // channel = 13, Tf = 2472MHz
397 {0x03, 0x37, 0xC3} // channel = 14, Tf = 2484MHz
400 u8 abyVT3226_ChannelTable1[CB_MAX_CHANNEL_24G][3] = {
401 {0x02, 0x66, 0x64}, // channel = 1, Tf = 2412MHz
402 {0x03, 0x66, 0x64}, // channel = 2, Tf = 2417MHz
403 {0x00, 0x66, 0x64}, // channel = 3, Tf = 2422MHz
404 {0x01, 0x66, 0x64}, // channel = 4, Tf = 2427MHz
405 {0x02, 0x66, 0x64}, // channel = 5, Tf = 2432MHz
406 {0x03, 0x66, 0x64}, // channel = 6, Tf = 2437MHz
407 {0x00, 0x66, 0x64}, // channel = 7, Tf = 2442MHz
408 {0x01, 0x66, 0x64}, // channel = 8, Tf = 2447MHz
409 {0x02, 0x66, 0x64}, // channel = 9, Tf = 2452MHz
410 {0x03, 0x66, 0x64}, // channel = 10, Tf = 2457MHz
411 {0x00, 0x66, 0x64}, // channel = 11, Tf = 2462MHz
412 {0x01, 0x66, 0x64}, // channel = 12, Tf = 2467MHz
413 {0x02, 0x66, 0x64}, // channel = 13, Tf = 2472MHz
414 {0x00, 0xCC, 0xC4} // channel = 14, Tf = 2484MHz
418 //{{RobertYu:20060502, TWIF 1.14, LO Current for 11b mode
419 u32 dwVT3226D0LoCurrentTable[CB_MAX_CHANNEL_24G] = {
420 0x0135C600+(BY_VT3226_REG_LEN<<3)+IFREGCTL_REGW, // channel = 1, Tf = 2412MHz
421 0x0135C600+(BY_VT3226_REG_LEN<<3)+IFREGCTL_REGW, // channel = 2, Tf = 2417MHz
422 0x0235C600+(BY_VT3226_REG_LEN<<3)+IFREGCTL_REGW, // channel = 3, Tf = 2422MHz
423 0x0235C600+(BY_VT3226_REG_LEN<<3)+IFREGCTL_REGW, // channel = 4, Tf = 2427MHz
424 0x0235C600+(BY_VT3226_REG_LEN<<3)+IFREGCTL_REGW, // channel = 5, Tf = 2432MHz
425 0x0335C600+(BY_VT3226_REG_LEN<<3)+IFREGCTL_REGW, // channel = 6, Tf = 2437MHz
426 0x0335C600+(BY_VT3226_REG_LEN<<3)+IFREGCTL_REGW, // channel = 7, Tf = 2442MHz
427 0x0335C600+(BY_VT3226_REG_LEN<<3)+IFREGCTL_REGW, // channel = 8, Tf = 2447MHz
428 0x0335C600+(BY_VT3226_REG_LEN<<3)+IFREGCTL_REGW, // channel = 9, Tf = 2452MHz
429 0x0335C600+(BY_VT3226_REG_LEN<<3)+IFREGCTL_REGW, // channel = 10, Tf = 2457MHz
430 0x0335C600+(BY_VT3226_REG_LEN<<3)+IFREGCTL_REGW, // channel = 11, Tf = 2462MHz
431 0x0335C600+(BY_VT3226_REG_LEN<<3)+IFREGCTL_REGW, // channel = 12, Tf = 2467MHz
432 0x0335C600+(BY_VT3226_REG_LEN<<3)+IFREGCTL_REGW, // channel = 13, Tf = 2472MHz
433 0x0135C600+(BY_VT3226_REG_LEN<<3)+IFREGCTL_REGW // channel = 14, Tf = 2484MHz
437 //{{RobertYu:20060609
438 u8 abyVT3342A0_InitTable[CB_VT3342_INIT_SEQ][3] = { /* 11b/g mode */
439 {0x03, 0xFF, 0x80}, //update for mode//
442 {0x03, 0xC5, 0x13}, // channel6
443 {0x00, 0xEE, 0xE4}, // channel6
454 //11b/g mode: 0x03, 0xFF, 0x80,
455 //11a mode: 0x03, 0xFF, 0xC0,
457 // channel44, 5220MHz 0x00C402
458 // channel56, 5280MHz 0x00C402 for disable Frac
459 // other channels 0x00C602
461 u8 abyVT3342_ChannelTable0[CB_MAX_CHANNEL][3] = {
462 {0x02, 0x05, 0x03}, // channel = 1, Tf = 2412MHz
463 {0x01, 0x15, 0x03}, // channel = 2, Tf = 2417MHz
464 {0x03, 0xC5, 0x03}, // channel = 3, Tf = 2422MHz
465 {0x02, 0x65, 0x03}, // channel = 4, Tf = 2427MHz
466 {0x01, 0x15, 0x13}, // channel = 5, Tf = 2432MHz
467 {0x03, 0xC5, 0x13}, // channel = 6, Tf = 2437MHz
468 {0x02, 0x05, 0x13}, // channel = 7, Tf = 2442MHz
469 {0x01, 0x15, 0x13}, // channel = 8, Tf = 2447MHz
470 {0x03, 0xC5, 0x13}, // channel = 9, Tf = 2452MHz
471 {0x02, 0x65, 0x13}, // channel = 10, Tf = 2457MHz
472 {0x01, 0x15, 0x23}, // channel = 11, Tf = 2462MHz
473 {0x03, 0xC5, 0x23}, // channel = 12, Tf = 2467MHz
474 {0x02, 0x05, 0x23}, // channel = 13, Tf = 2472MHz
475 {0x00, 0xD5, 0x23}, // channel = 14, Tf = 2484MHz
477 // 4.9G => Ch 183, 184, 185, 187, 188, 189, 192, 196 (Value:15 ~ 22)
478 {0x01, 0x15, 0x13}, // channel = 183, Tf = 4915MHz (15), TBD
479 {0x01, 0x15, 0x13}, // channel = 184, Tf = 4920MHz (16), TBD
480 {0x01, 0x15, 0x13}, // channel = 185, Tf = 4925MHz (17), TBD
481 {0x01, 0x15, 0x13}, // channel = 187, Tf = 4935MHz (18), TBD
482 {0x01, 0x15, 0x13}, // channel = 188, Tf = 4940MHz (19), TBD
483 {0x01, 0x15, 0x13}, // channel = 189, Tf = 4945MHz (20), TBD
484 {0x01, 0x15, 0x13}, // channel = 192, Tf = 4960MHz (21), TBD
485 {0x01, 0x15, 0x13}, // channel = 196, Tf = 4980MHz (22), TBD
487 // 5G => Ch 7, 8, 9, 11, 12, 16, 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64,
488 // 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165 (Value 23 ~ 56)
489 {0x01, 0x15, 0x13}, // channel = 7, Tf = 5035MHz (23), TBD
490 {0x01, 0x15, 0x13}, // channel = 8, Tf = 5040MHz (24), TBD
491 {0x01, 0x15, 0x13}, // channel = 9, Tf = 5045MHz (25), TBD
492 {0x01, 0x15, 0x13}, // channel = 11, Tf = 5055MHz (26), TBD
493 {0x01, 0x15, 0x13}, // channel = 12, Tf = 5060MHz (27), TBD
494 {0x01, 0x15, 0x13}, // channel = 16, Tf = 5080MHz (28), TBD
495 {0x01, 0x15, 0x13}, // channel = 34, Tf = 5170MHz (29), TBD
496 {0x01, 0x55, 0x63}, // channel = 36, Tf = 5180MHz (30)
497 {0x01, 0x55, 0x63}, // channel = 38, Tf = 5190MHz (31), TBD
498 {0x02, 0xA5, 0x63}, // channel = 40, Tf = 5200MHz (32)
499 {0x02, 0xA5, 0x63}, // channel = 42, Tf = 5210MHz (33), TBD
500 {0x00, 0x05, 0x73}, // channel = 44, Tf = 5220MHz (34)
501 {0x00, 0x05, 0x73}, // channel = 46, Tf = 5230MHz (35), TBD
502 {0x01, 0x55, 0x73}, // channel = 48, Tf = 5240MHz (36)
503 {0x02, 0xA5, 0x73}, // channel = 52, Tf = 5260MHz (37)
504 {0x00, 0x05, 0x83}, // channel = 56, Tf = 5280MHz (38)
505 {0x01, 0x55, 0x83}, // channel = 60, Tf = 5300MHz (39)
506 {0x02, 0xA5, 0x83}, // channel = 64, Tf = 5320MHz (40)
508 {0x02, 0xA5, 0x83}, // channel = 100, Tf = 5500MHz (41), TBD
509 {0x02, 0xA5, 0x83}, // channel = 104, Tf = 5520MHz (42), TBD
510 {0x02, 0xA5, 0x83}, // channel = 108, Tf = 5540MHz (43), TBD
511 {0x02, 0xA5, 0x83}, // channel = 112, Tf = 5560MHz (44), TBD
512 {0x02, 0xA5, 0x83}, // channel = 116, Tf = 5580MHz (45), TBD
513 {0x02, 0xA5, 0x83}, // channel = 120, Tf = 5600MHz (46), TBD
514 {0x02, 0xA5, 0x83}, // channel = 124, Tf = 5620MHz (47), TBD
515 {0x02, 0xA5, 0x83}, // channel = 128, Tf = 5640MHz (48), TBD
516 {0x02, 0xA5, 0x83}, // channel = 132, Tf = 5660MHz (49), TBD
517 {0x02, 0xA5, 0x83}, // channel = 136, Tf = 5680MHz (50), TBD
518 {0x02, 0xA5, 0x83}, // channel = 140, Tf = 5700MHz (51), TBD
520 {0x00, 0x05, 0xF3}, // channel = 149, Tf = 5745MHz (52)
521 {0x01, 0x56, 0x03}, // channel = 153, Tf = 5765MHz (53)
522 {0x02, 0xA6, 0x03}, // channel = 157, Tf = 5785MHz (54)
523 {0x00, 0x06, 0x03}, // channel = 161, Tf = 5805MHz (55)
524 {0x00, 0x06, 0x03} // channel = 165, Tf = 5825MHz (56), TBD
527 u8 abyVT3342_ChannelTable1[CB_MAX_CHANNEL][3] = {
528 {0x01, 0x99, 0x94}, // channel = 1, Tf = 2412MHz
529 {0x02, 0x44, 0x44}, // channel = 2, Tf = 2417MHz
530 {0x02, 0xEE, 0xE4}, // channel = 3, Tf = 2422MHz
531 {0x03, 0x99, 0x94}, // channel = 4, Tf = 2427MHz
532 {0x00, 0x44, 0x44}, // channel = 5, Tf = 2432MHz
533 {0x00, 0xEE, 0xE4}, // channel = 6, Tf = 2437MHz
534 {0x01, 0x99, 0x94}, // channel = 7, Tf = 2442MHz
535 {0x02, 0x44, 0x44}, // channel = 8, Tf = 2447MHz
536 {0x02, 0xEE, 0xE4}, // channel = 9, Tf = 2452MHz
537 {0x03, 0x99, 0x94}, // channel = 10, Tf = 2457MHz
538 {0x00, 0x44, 0x44}, // channel = 11, Tf = 2462MHz
539 {0x00, 0xEE, 0xE4}, // channel = 12, Tf = 2467MHz
540 {0x01, 0x99, 0x94}, // channel = 13, Tf = 2472MHz
541 {0x03, 0x33, 0x34}, // channel = 14, Tf = 2484MHz
543 // 4.9G => Ch 183, 184, 185, 187, 188, 189, 192, 196 (Value:15 ~ 22)
544 {0x00, 0x44, 0x44}, // channel = 183, Tf = 4915MHz (15), TBD
545 {0x00, 0x44, 0x44}, // channel = 184, Tf = 4920MHz (16), TBD
546 {0x00, 0x44, 0x44}, // channel = 185, Tf = 4925MHz (17), TBD
547 {0x00, 0x44, 0x44}, // channel = 187, Tf = 4935MHz (18), TBD
548 {0x00, 0x44, 0x44}, // channel = 188, Tf = 4940MHz (19), TBD
549 {0x00, 0x44, 0x44}, // channel = 189, Tf = 4945MHz (20), TBD
550 {0x00, 0x44, 0x44}, // channel = 192, Tf = 4960MHz (21), TBD
551 {0x00, 0x44, 0x44}, // channel = 196, Tf = 4980MHz (22), TBD
553 // 5G => Ch 7, 8, 9, 11, 12, 16, 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64,
554 // 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165 (Value 23 ~ 56)
555 {0x00, 0x44, 0x44}, // channel = 7, Tf = 5035MHz (23), TBD
556 {0x00, 0x44, 0x44}, // channel = 8, Tf = 5040MHz (24), TBD
557 {0x00, 0x44, 0x44}, // channel = 9, Tf = 5045MHz (25), TBD
558 {0x00, 0x44, 0x44}, // channel = 11, Tf = 5055MHz (26), TBD
559 {0x00, 0x44, 0x44}, // channel = 12, Tf = 5060MHz (27), TBD
560 {0x00, 0x44, 0x44}, // channel = 16, Tf = 5080MHz (28), TBD
561 {0x00, 0x44, 0x44}, // channel = 34, Tf = 5170MHz (29), TBD
562 {0x01, 0x55, 0x54}, // channel = 36, Tf = 5180MHz (30)
563 {0x01, 0x55, 0x54}, // channel = 38, Tf = 5190MHz (31), TBD
564 {0x02, 0xAA, 0xA4}, // channel = 40, Tf = 5200MHz (32)
565 {0x02, 0xAA, 0xA4}, // channel = 42, Tf = 5210MHz (33), TBD
566 {0x00, 0x00, 0x04}, // channel = 44, Tf = 5220MHz (34)
567 {0x00, 0x00, 0x04}, // channel = 46, Tf = 5230MHz (35), TBD
568 {0x01, 0x55, 0x54}, // channel = 48, Tf = 5240MHz (36)
569 {0x02, 0xAA, 0xA4}, // channel = 52, Tf = 5260MHz (37)
570 {0x00, 0x00, 0x04}, // channel = 56, Tf = 5280MHz (38)
571 {0x01, 0x55, 0x54}, // channel = 60, Tf = 5300MHz (39)
572 {0x02, 0xAA, 0xA4}, // channel = 64, Tf = 5320MHz (40)
573 {0x02, 0xAA, 0xA4}, // channel = 100, Tf = 5500MHz (41), TBD
574 {0x02, 0xAA, 0xA4}, // channel = 104, Tf = 5520MHz (42), TBD
575 {0x02, 0xAA, 0xA4}, // channel = 108, Tf = 5540MHz (43), TBD
576 {0x02, 0xAA, 0xA4}, // channel = 112, Tf = 5560MHz (44), TBD
577 {0x02, 0xAA, 0xA4}, // channel = 116, Tf = 5580MHz (45), TBD
578 {0x02, 0xAA, 0xA4}, // channel = 120, Tf = 5600MHz (46), TBD
579 {0x02, 0xAA, 0xA4}, // channel = 124, Tf = 5620MHz (47), TBD
580 {0x02, 0xAA, 0xA4}, // channel = 128, Tf = 5640MHz (48), TBD
581 {0x02, 0xAA, 0xA4}, // channel = 132, Tf = 5660MHz (49), TBD
582 {0x02, 0xAA, 0xA4}, // channel = 136, Tf = 5680MHz (50), TBD
583 {0x02, 0xAA, 0xA4}, // channel = 140, Tf = 5700MHz (51), TBD
584 {0x03, 0x00, 0x04}, // channel = 149, Tf = 5745MHz (52)
585 {0x00, 0x55, 0x54}, // channel = 153, Tf = 5765MHz (53)
586 {0x01, 0xAA, 0xA4}, // channel = 157, Tf = 5785MHz (54)
587 {0x03, 0x00, 0x04}, // channel = 161, Tf = 5805MHz (55)
588 {0x03, 0x00, 0x04} // channel = 165, Tf = 5825MHz (56), TBD
597 const u32 dwAL2230PowerTable[AL2230_PWR_IDX_LEN] = {
598 0x04040900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
599 0x04041900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
600 0x04042900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
601 0x04043900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
602 0x04044900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
603 0x04045900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
604 0x04046900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
605 0x04047900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
606 0x04048900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
607 0x04049900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
608 0x0404A900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
609 0x0404B900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
610 0x0404C900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
611 0x0404D900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
612 0x0404E900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
613 0x0404F900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
614 0x04050900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
615 0x04051900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
616 0x04052900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
617 0x04053900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
618 0x04054900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
619 0x04055900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
620 0x04056900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
621 0x04057900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
622 0x04058900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
623 0x04059900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
624 0x0405A900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
625 0x0405B900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
626 0x0405C900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
627 0x0405D900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
628 0x0405E900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
629 0x0405F900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
630 0x04060900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
631 0x04061900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
632 0x04062900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
633 0x04063900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
634 0x04064900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
635 0x04065900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
636 0x04066900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
637 0x04067900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
638 0x04068900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
639 0x04069900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
640 0x0406A900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
641 0x0406B900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
642 0x0406C900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
643 0x0406D900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
644 0x0406E900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
645 0x0406F900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
646 0x04070900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
647 0x04071900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
648 0x04072900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
649 0x04073900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
650 0x04074900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
651 0x04075900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
652 0x04076900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
653 0x04077900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
654 0x04078900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
655 0x04079900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
656 0x0407A900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
657 0x0407B900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
658 0x0407C900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
659 0x0407D900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
660 0x0407E900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
661 0x0407F900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW
664 //{{ RobertYu:20050103, Channel 11a Number To Index
665 // 4.9G => Ch 183, 184, 185, 187, 188, 189, 192, 196 (Value:15 ~ 22)
666 // 5G => Ch 7, 8, 9, 11, 12, 16, 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64,
667 // 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165 (Value 23 ~ 56)
669 const u8 RFaby11aChannelIndex[200] = {
670 // 1 2 3 4 5 6 7 8 9 10
671 00, 00, 00, 00, 00, 00, 23, 24, 25, 00, // 10
672 26, 27, 00, 00, 00, 28, 00, 00, 00, 00, // 20
673 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, // 30
674 00, 00, 00, 29, 00, 30, 00, 31, 00, 32, // 40
675 00, 33, 00, 34, 00, 35, 00, 36, 00, 00, // 50
676 00, 37, 00, 00, 00, 38, 00, 00, 00, 39, // 60
677 00, 00, 00, 40, 00, 00, 00, 00, 00, 00, // 70
678 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, // 80
679 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, // 90
680 00, 00, 00, 00, 00, 00, 00, 00, 00, 41, //100
682 00, 00, 00, 42, 00, 00, 00, 43, 00, 00, //110
683 00, 44, 00, 00, 00, 45, 00, 00, 00, 46, //120
684 00, 00, 00, 47, 00, 00, 00, 48, 00, 00, //130
685 00, 49, 00, 00, 00, 50, 00, 00, 00, 51, //140
686 00, 00, 00, 00, 00, 00, 00, 00, 52, 00, //150
687 00, 00, 53, 00, 00, 00, 54, 00, 00, 00, //160
688 55, 00, 00, 00, 56, 00, 00, 00, 00, 00, //170
689 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, //180
690 00, 00, 15, 16, 17, 00, 18, 19, 20, 00, //190
691 00, 21, 00, 00, 00, 22, 00, 00, 00, 00 //200
696 * Description: Write to IF/RF, by embedded programming
700 * dwData - data to write
704 * Return Value: true if succeeded; false if failed.
707 int IFRFbWriteEmbedded(struct vnt_private *pDevice, u32 dwData)
711 pbyData[0] = (u8)dwData;
712 pbyData[1] = (u8)(dwData >> 8);
713 pbyData[2] = (u8)(dwData >> 16);
714 pbyData[3] = (u8)(dwData >> 24);
716 CONTROLnsRequestOut(pDevice,
717 MESSAGE_TYPE_WRITE_IFRF, 0, 0, 4, pbyData);
723 * Description: Set Tx power
727 * dwIoBase - I/O base address
728 * dwRFPowerTable - RF Tx Power Setting
732 * Return Value: true if succeeded; false if failed.
735 int RFbSetPower(struct vnt_private *pDevice, u32 uRATE, u32 uCH)
738 u8 byPwr = pDevice->byCCKPwr;
740 if (pDevice->dwDiagRefCount)
751 byPwr = pDevice->abyCCKPwrTbl[uCH-1];
760 if (uCH > CB_MAX_CHANNEL_24G) {
761 byPwr = pDevice->abyOFDMAPwrTbl[uCH-15];
763 byPwr = pDevice->abyOFDMPwrTbl[uCH-1];
768 bResult = RFbRawSetPower(pDevice, byPwr, uRATE);
774 * Description: Set Tx power
778 * dwIoBase - I/O base address
779 * dwRFPowerTable - RF Tx Power Setting
783 * Return Value: true if succeeded; false if failed.
787 int RFbRawSetPower(struct vnt_private *pDevice, u8 byPwr, u32 uRATE)
791 if (pDevice->byCurPwr == byPwr)
794 pDevice->byCurPwr = byPwr;
796 switch (pDevice->byRFType) {
799 if (pDevice->byCurPwr >= AL2230_PWR_IDX_LEN)
801 bResult &= IFRFbWriteEmbedded(pDevice, dwAL2230PowerTable[pDevice->byCurPwr]);
802 if (uRATE <= RATE_11M)
803 bResult &= IFRFbWriteEmbedded(pDevice, 0x0001B400+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW);
805 bResult &= IFRFbWriteEmbedded(pDevice, 0x0005A400+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW);
809 if (pDevice->byCurPwr >= AL2230_PWR_IDX_LEN)
811 bResult &= IFRFbWriteEmbedded(pDevice, dwAL2230PowerTable[pDevice->byCurPwr]);
812 if (uRATE <= RATE_11M) {
813 bResult &= IFRFbWriteEmbedded(pDevice, 0x040C1400+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW);
814 bResult &= IFRFbWriteEmbedded(pDevice, 0x00299B00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW);
816 bResult &= IFRFbWriteEmbedded(pDevice, 0x0005A400+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW);
817 bResult &= IFRFbWriteEmbedded(pDevice, 0x00099B00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW);
825 if (uRATE <= RATE_11M) { //RobertYu:20060426, for better 11b mask
826 bResult &= IFRFbWriteEmbedded(pDevice, 0x111BB900+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW);
829 bResult &= IFRFbWriteEmbedded(pDevice, 0x221BB900+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW);
832 if (pDevice->byCurPwr > AL7230_PWR_IDX_LEN) return false;
834 // 0x080F1B00 for 3 wire control TxGain(D10) and 0x31 as TX Gain value
835 dwMax7230Pwr = 0x080C0B00 | ( (pDevice->byCurPwr) << 12 ) |
836 (BY_AL7230_REG_LEN << 3 ) | IFREGCTL_REGW;
838 bResult &= IFRFbWriteEmbedded(pDevice, dwMax7230Pwr);
843 case RF_VT3226: //RobertYu:20051111, VT3226C0 and before
847 if (pDevice->byCurPwr >= VT3226_PWR_IDX_LEN)
849 dwVT3226Pwr = ((0x3F-pDevice->byCurPwr) << 20 ) | ( 0x17 << 8 ) /* Reg7 */ |
850 (BY_VT3226_REG_LEN << 3 ) | IFREGCTL_REGW;
851 bResult &= IFRFbWriteEmbedded(pDevice, dwVT3226Pwr);
855 case RF_VT3226D0: //RobertYu:20051228
859 if (pDevice->byCurPwr >= VT3226_PWR_IDX_LEN)
862 if (uRATE <= RATE_11M) {
864 dwVT3226Pwr = ((0x3F-pDevice->byCurPwr) << 20 ) | ( 0xE07 << 8 ) /* Reg7 */ | //RobertYu:20060420, TWIF 1.10
865 (BY_VT3226_REG_LEN << 3 ) | IFREGCTL_REGW;
866 bResult &= IFRFbWriteEmbedded(pDevice, dwVT3226Pwr);
868 bResult &= IFRFbWriteEmbedded(pDevice, 0x03C6A200+(BY_VT3226_REG_LEN<<3)+IFREGCTL_REGW);
869 if (pDevice->vnt_mgmt.eScanState != WMAC_NO_SCANNING) {
870 /* scanning, channel number is pDevice->uScanChannel */
871 DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO
872 "RFbRawSetPower> 11B mode uCurrChannel[%d]\n",
873 pDevice->vnt_mgmt.uScanChannel);
874 bResult &= IFRFbWriteEmbedded(pDevice,
875 dwVT3226D0LoCurrentTable[pDevice->
876 vnt_mgmt.uScanChannel - 1]);
878 DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO
879 "RFbRawSetPower> 11B mode uCurrChannel[%d]\n",
880 pDevice->vnt_mgmt.uCurrChannel);
881 bResult &= IFRFbWriteEmbedded(pDevice,
882 dwVT3226D0LoCurrentTable[pDevice->
883 vnt_mgmt.uCurrChannel - 1]);
886 bResult &= IFRFbWriteEmbedded(pDevice, 0x015C0800+(BY_VT3226_REG_LEN<<3)+IFREGCTL_REGW); //RobertYu:20060420, ok now, new switching power (mini-pci can have bigger power consumption)
888 DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO"@@@@ RFbRawSetPower> 11G mode\n");
889 dwVT3226Pwr = ((0x3F-pDevice->byCurPwr) << 20 ) | ( 0x7 << 8 ) /* Reg7 */ | //RobertYu:20060420, TWIF 1.10
890 (BY_VT3226_REG_LEN << 3 ) | IFREGCTL_REGW;
891 bResult &= IFRFbWriteEmbedded(pDevice, dwVT3226Pwr);
892 bResult &= IFRFbWriteEmbedded(pDevice, 0x00C6A200+(BY_VT3226_REG_LEN<<3)+IFREGCTL_REGW); //RobertYu:20060327
893 bResult &= IFRFbWriteEmbedded(pDevice, 0x016BC600+(BY_VT3226_REG_LEN<<3)+IFREGCTL_REGW); //RobertYu:20060111
894 bResult &= IFRFbWriteEmbedded(pDevice, 0x00900800+(BY_VT3226_REG_LEN<<3)+IFREGCTL_REGW); //RobertYu:20060111
899 //{{RobertYu:20060609
904 if (pDevice->byCurPwr >= VT3342_PWR_IDX_LEN)
907 dwVT3342Pwr = ((0x3F-pDevice->byCurPwr) << 20 ) | ( 0x27 << 8 ) /* Reg7 */ |
908 (BY_VT3342_REG_LEN << 3 ) | IFREGCTL_REGW;
909 bResult &= IFRFbWriteEmbedded(pDevice, dwVT3342Pwr);
921 * Routine Description:
922 * Translate RSSI to dBm
926 * pDevice - The adapter to be translated
927 * byCurrRSSI - RSSI to be translated
929 * pdwdbm - Translated dbm number
934 void RFvRSSITodBm(struct vnt_private *pDevice, u8 byCurrRSSI, long *pldBm)
936 u8 byIdx = (((byCurrRSSI & 0xC0) >> 6) & 0x03);
937 signed long b = (byCurrRSSI & 0x3F);
939 u8 abyAIROHARF[4] = {0, 18, 0, 40};
941 switch (pDevice->byRFType) {
945 case RF_VT3226: //RobertYu:20051111
947 case RF_VT3342A0: //RobertYu:20060609
948 a = abyAIROHARF[byIdx];
954 *pldBm = -1 * (a + b * 2);
957 void RFbRFTableDownload(struct vnt_private *pDevice)
959 u16 wLength1 = 0, wLength2 = 0, wLength3 = 0;
960 u8 *pbyAddr1 = NULL, *pbyAddr2 = NULL, *pbyAddr3 = NULL;
964 switch ( pDevice->byRFType ) {
967 wLength1 = CB_AL2230_INIT_SEQ * 3;
968 wLength2 = CB_MAX_CHANNEL_24G * 3;
969 wLength3 = CB_MAX_CHANNEL_24G * 3;
970 pbyAddr1 = &(abyAL2230InitTable[0][0]);
971 pbyAddr2 = &(abyAL2230ChannelTable0[0][0]);
972 pbyAddr3 = &(abyAL2230ChannelTable1[0][0]);
975 wLength1 = CB_AL7230_INIT_SEQ * 3;
976 wLength2 = CB_MAX_CHANNEL * 3;
977 wLength3 = CB_MAX_CHANNEL * 3;
978 pbyAddr1 = &(abyAL7230InitTable[0][0]);
979 pbyAddr2 = &(abyAL7230ChannelTable0[0][0]);
980 pbyAddr3 = &(abyAL7230ChannelTable1[0][0]);
982 case RF_VT3226: //RobertYu:20051111
983 wLength1 = CB_VT3226_INIT_SEQ * 3;
984 wLength2 = CB_MAX_CHANNEL_24G * 3;
985 wLength3 = CB_MAX_CHANNEL_24G * 3;
986 pbyAddr1 = &(abyVT3226_InitTable[0][0]);
987 pbyAddr2 = &(abyVT3226_ChannelTable0[0][0]);
988 pbyAddr3 = &(abyVT3226_ChannelTable1[0][0]);
990 case RF_VT3226D0: //RobertYu:20051114
991 wLength1 = CB_VT3226_INIT_SEQ * 3;
992 wLength2 = CB_MAX_CHANNEL_24G * 3;
993 wLength3 = CB_MAX_CHANNEL_24G * 3;
994 pbyAddr1 = &(abyVT3226D0_InitTable[0][0]);
995 pbyAddr2 = &(abyVT3226_ChannelTable0[0][0]);
996 pbyAddr3 = &(abyVT3226_ChannelTable1[0][0]);
998 case RF_VT3342A0: //RobertYu:20060609
999 wLength1 = CB_VT3342_INIT_SEQ * 3;
1000 wLength2 = CB_MAX_CHANNEL * 3;
1001 wLength3 = CB_MAX_CHANNEL * 3;
1002 pbyAddr1 = &(abyVT3342A0_InitTable[0][0]);
1003 pbyAddr2 = &(abyVT3342_ChannelTable0[0][0]);
1004 pbyAddr3 = &(abyVT3342_ChannelTable1[0][0]);
1010 memcpy(abyArray, pbyAddr1, wLength1);
1011 CONTROLnsRequestOut(pDevice,
1014 MESSAGE_REQUEST_RF_INIT,
1020 while ( wLength2 > 0 ) {
1022 if ( wLength2 >= 64 ) {
1027 memcpy(abyArray, pbyAddr2, wLength);
1028 CONTROLnsRequestOut(pDevice,
1031 MESSAGE_REQUEST_RF_CH0,
1035 wLength2 -= wLength;
1037 pbyAddr2 += wLength;
1041 while ( wLength3 > 0 ) {
1043 if ( wLength3 >= 64 ) {
1048 memcpy(abyArray, pbyAddr3, wLength);
1049 CONTROLnsRequestOut(pDevice,
1052 MESSAGE_REQUEST_RF_CH1,
1056 wLength3 -= wLength;
1058 pbyAddr3 += wLength;
1061 //7230 needs 2 InitTable and 3 Channel Table
1062 if ( pDevice->byRFType == RF_AIROHA7230 ) {
1063 wLength1 = CB_AL7230_INIT_SEQ * 3;
1064 wLength2 = CB_MAX_CHANNEL * 3;
1065 pbyAddr1 = &(abyAL7230InitTableAMode[0][0]);
1066 pbyAddr2 = &(abyAL7230ChannelTable2[0][0]);
1067 memcpy(abyArray, pbyAddr1, wLength1);
1069 CONTROLnsRequestOut(pDevice,
1072 MESSAGE_REQUEST_RF_INIT2,
1078 while ( wLength2 > 0 ) {
1080 if ( wLength2 >= 64 ) {
1085 memcpy(abyArray, pbyAddr2, wLength);
1086 CONTROLnsRequestOut(pDevice,
1089 MESSAGE_REQUEST_RF_CH2,
1093 wLength2 -= wLength;
1095 pbyAddr2 += wLength;