Pileus Git - ~andy/linux/blob - drivers/staging/vt6655/mac.h

   1 /*
   2  * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program; if not, write to the Free Software Foundation, Inc.,
  17  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  *
  20  * File: mac.h
  21  *
  22  * Purpose: MAC routines
  23  *
  24  * Author: Tevin Chen
  25  *
  26  * Date: May 21, 1996
  27  *
  28  * Revision History:
  29  *      07-01-2003 Bryan YC Fan:  Re-write codes to support VT3253 spec.
  30  *      08-25-2003 Kyle Hsu:      Porting MAC functions from sim53.
  31  *      09-03-2003 Bryan YC Fan:  Add MACvDisableProtectMD & MACvEnableProtectMD
  32  */
  33
  34 #ifndef __MAC_H__
  35 #define __MAC_H__
  36
  37 #include "ttype.h"
  38 #include "tmacro.h"
  39 #include "upc.h"
  40
  41 /*---------------------  Export Definitions -------------------------*/
  42 //
  43 // Registers in the MAC
  44 //
  45 #define MAC_MAX_CONTEXT_SIZE_PAGE0  256
  46 #define MAC_MAX_CONTEXT_SIZE_PAGE1  128
  47 #define MAC_MAX_CONTEXT_SIZE        MAC_MAX_CONTEXT_SIZE_PAGE0 + MAC_MAX_CONTEXT_SIZE_PAGE1
  48
  49 // Registers not related to 802.11b
  50 #define MAC_REG_BCFG0       0x00
  51 #define MAC_REG_BCFG1       0x01
  52 #define MAC_REG_FCR0        0x02
  53 #define MAC_REG_FCR1        0x03
  54 #define MAC_REG_BISTCMD     0x04
  55 #define MAC_REG_BISTSR0     0x05
  56 #define MAC_REG_BISTSR1     0x06
  57 #define MAC_REG_BISTSR2     0x07
  58 #define MAC_REG_I2MCSR      0x08
  59 #define MAC_REG_I2MTGID     0x09
  60 #define MAC_REG_I2MTGAD     0x0A
  61 #define MAC_REG_I2MCFG      0x0B
  62 #define MAC_REG_I2MDIPT     0x0C
  63 #define MAC_REG_I2MDOPT     0x0E
  64 #define MAC_REG_PMC0        0x10
  65 #define MAC_REG_PMC1        0x11
  66 #define MAC_REG_STICKHW     0x12
  67 #define MAC_REG_LOCALID     0x14
  68 #define MAC_REG_TESTCFG     0x15
  69 #define MAC_REG_JUMPER0     0x16
  70 #define MAC_REG_JUMPER1     0x17
  71 #define MAC_REG_TMCTL0      0x18
  72 #define MAC_REG_TMCTL1      0x19
  73 #define MAC_REG_TMDATA0     0x1C
  74 // MAC Parameter related
  75 #define MAC_REG_LRT         0x20        //
  76 #define MAC_REG_SRT         0x21        //
  77 #define MAC_REG_SIFS        0x22        //
  78 #define MAC_REG_DIFS        0x23        //
  79 #define MAC_REG_EIFS        0x24        //
  80 #define MAC_REG_SLOT        0x25        //
  81 #define MAC_REG_BI          0x26        //
  82 #define MAC_REG_CWMAXMIN0   0x28        //
  83 #define MAC_REG_LINKOFFTOTM 0x2A
  84 #define MAC_REG_SWTMOT      0x2B
  85 #define MAC_REG_MIBCNTR     0x2C
  86 #define MAC_REG_RTSOKCNT    0x2C
  87 #define MAC_REG_RTSFAILCNT  0x2D
  88 #define MAC_REG_ACKFAILCNT  0x2E
  89 #define MAC_REG_FCSERRCNT   0x2F
  90 // TSF Related
  91 #define MAC_REG_TSFCNTR     0x30        //
  92 #define MAC_REG_NEXTTBTT    0x38        //
  93 #define MAC_REG_TSFOFST     0x40        //
  94 #define MAC_REG_TFTCTL      0x48        //
  95 // WMAC Control/Status Related
  96 #define MAC_REG_ENCFG       0x4C        //
  97 #define MAC_REG_PAGE1SEL    0x4F        //
  98 #define MAC_REG_CFG         0x50        //
  99 #define MAC_REG_TEST        0x52        //
 100 #define MAC_REG_HOSTCR      0x54        //
 101 #define MAC_REG_MACCR       0x55        //
 102 #define MAC_REG_RCR         0x56        //
 103 #define MAC_REG_TCR         0x57        //
 104 #define MAC_REG_IMR         0x58        //
 105 #define MAC_REG_ISR         0x5C
 106 // Power Saving Related
 107 #define MAC_REG_PSCFG       0x60        //
 108 #define MAC_REG_PSCTL       0x61        //
 109 #define MAC_REG_PSPWRSIG    0x62        //
 110 #define MAC_REG_BBCR13      0x63
 111 #define MAC_REG_AIDATIM     0x64
 112 #define MAC_REG_PWBT        0x66
 113 #define MAC_REG_WAKEOKTMR   0x68
 114 #define MAC_REG_CALTMR      0x69
 115 #define MAC_REG_SYNSPACCNT  0x6A
 116 #define MAC_REG_WAKSYNOPT   0x6B
 117 // Baseband/IF Control Group
 118 #define MAC_REG_BBREGCTL    0x6C        //
 119 #define MAC_REG_CHANNEL     0x6D
 120 #define MAC_REG_BBREGADR    0x6E
 121 #define MAC_REG_BBREGDATA   0x6F
 122 #define MAC_REG_IFREGCTL    0x70        //
 123 #define MAC_REG_IFDATA      0x71        //
 124 #define MAC_REG_ITRTMSET    0x74        //
 125 #define MAC_REG_PAPEDELAY   0x77
 126 #define MAC_REG_SOFTPWRCTL  0x78        //
 127 #define MAC_REG_GPIOCTL0    0x7A        //
 128 #define MAC_REG_GPIOCTL1    0x7B        //
 129
 130 // MAC DMA Related Group
 131 #define MAC_REG_TXDMACTL0   0x7C        //
 132 #define MAC_REG_TXDMAPTR0   0x80        //
 133 #define MAC_REG_AC0DMACTL   0x84        //
 134 #define MAC_REG_AC0DMAPTR   0x88        //
 135 #define MAC_REG_BCNDMACTL   0x8C        //
 136 #define MAC_REG_BCNDMAPTR   0x90        //
 137 #define MAC_REG_RXDMACTL0   0x94        //
 138 #define MAC_REG_RXDMAPTR0   0x98        //
 139 #define MAC_REG_RXDMACTL1   0x9C        //
 140 #define MAC_REG_RXDMAPTR1   0xA0        //
 141 #define MAC_REG_SYNCDMACTL  0xA4        //
 142 #define MAC_REG_SYNCDMAPTR  0xA8
 143 #define MAC_REG_ATIMDMACTL  0xAC
 144 #define MAC_REG_ATIMDMAPTR  0xB0
 145 // MiscFF PIO related
 146 #define MAC_REG_MISCFFNDEX  0xB4
 147 #define MAC_REG_MISCFFCTL   0xB6
 148 #define MAC_REG_MISCFFDATA  0xB8
 149 // Extend SW Timer
 150 #define MAC_REG_TMDATA1     0xBC
 151 // WOW Related Group
 152 #define MAC_REG_WAKEUPEN0   0xC0
 153 #define MAC_REG_WAKEUPEN1   0xC1
 154 #define MAC_REG_WAKEUPSR0   0xC2
 155 #define MAC_REG_WAKEUPSR1   0xC3
 156 #define MAC_REG_WAKE128_0   0xC4
 157 #define MAC_REG_WAKE128_1   0xD4
 158 #define MAC_REG_WAKE128_2   0xE4
 159 #define MAC_REG_WAKE128_3   0xF4
 160
 161 /////////////// Page 1 ///////////////////
 162 #define MAC_REG_CRC_128_0   0x04
 163 #define MAC_REG_CRC_128_1   0x06
 164 #define MAC_REG_CRC_128_2   0x08
 165 #define MAC_REG_CRC_128_3   0x0A
 166 // MAC Configuration Group
 167 #define MAC_REG_PAR0        0x0C
 168 #define MAC_REG_PAR4        0x10
 169 #define MAC_REG_BSSID0      0x14
 170 #define MAC_REG_BSSID4      0x18
 171 #define MAC_REG_MAR0        0x1C
 172 #define MAC_REG_MAR4        0x20
 173 // MAC RSPPKT INFO Group
 174 #define MAC_REG_RSPINF_B_1  0x24
 175 #define MAC_REG_RSPINF_B_2  0x28
 176 #define MAC_REG_RSPINF_B_5  0x2C
 177 #define MAC_REG_RSPINF_B_11 0x30
 178 #define MAC_REG_RSPINF_A_6  0x34
 179 #define MAC_REG_RSPINF_A_9  0x36
 180 #define MAC_REG_RSPINF_A_12 0x38
 181 #define MAC_REG_RSPINF_A_18 0x3A
 182 #define MAC_REG_RSPINF_A_24 0x3C
 183 #define MAC_REG_RSPINF_A_36 0x3E
 184 #define MAC_REG_RSPINF_A_48 0x40
 185 #define MAC_REG_RSPINF_A_54 0x42
 186 #define MAC_REG_RSPINF_A_72 0x44
 187
 188 // 802.11h relative
 189 #define MAC_REG_QUIETINIT   0x60
 190 #define MAC_REG_QUIETGAP    0x62
 191 #define MAC_REG_QUIETDUR    0x64
 192 #define MAC_REG_MSRCTL      0x66
 193 #define MAC_REG_MSRBBSTS    0x67
 194 #define MAC_REG_MSRSTART    0x68
 195 #define MAC_REG_MSRDURATION 0x70
 196 #define MAC_REG_CCAFRACTION 0x72
 197 #define MAC_REG_PWRCCK      0x73
 198 #define MAC_REG_PWROFDM     0x7C
 199
 200
 201 //
 202 // Bits in the BCFG0 register
 203 //
 204 #define BCFG0_PERROFF       0x40
 205 #define BCFG0_MRDMDIS       0x20
 206 #define BCFG0_MRDLDIS       0x10
 207 #define BCFG0_MWMEN         0x08
 208 #define BCFG0_VSERREN       0x02
 209 #define BCFG0_LATMEN        0x01
 210
 211 //
 212 // Bits in the BCFG1 register
 213 //
 214 #define BCFG1_CFUNOPT       0x80
 215 #define BCFG1_CREQOPT       0x40
 216 #define BCFG1_DMA8          0x10
 217 #define BCFG1_ARBITOPT      0x08
 218 #define BCFG1_PCIMEN        0x04
 219 #define BCFG1_MIOEN         0x02
 220 #define BCFG1_CISDLYEN      0x01
 221
 222 // Bits in RAMBIST registers
 223 #define BISTCMD_TSTPAT5     0x00        //
 224 #define BISTCMD_TSTPATA     0x80        //
 225 #define BISTCMD_TSTERR      0x20        //
 226 #define BISTCMD_TSTPATF     0x18        //
 227 #define BISTCMD_TSTPAT0     0x10        //
 228 #define BISTCMD_TSTMODE     0x04        //
 229 #define BISTCMD_TSTITTX     0x03        //
 230 #define BISTCMD_TSTATRX     0x02        //
 231 #define BISTCMD_TSTATTX     0x01        //
 232 #define BISTCMD_TSTRX       0x00        //
 233 #define BISTSR0_BISTGO      0x01        //
 234 #define BISTSR1_TSTSR       0x01        //
 235 #define BISTSR2_CMDPRTEN    0x02        //
 236 #define BISTSR2_RAMTSTEN    0x01        //
 237
 238 //
 239 // Bits in the I2MCFG EEPROM register
 240 //
 241 #define I2MCFG_BOUNDCTL     0x80
 242 #define I2MCFG_WAITCTL      0x20
 243 #define I2MCFG_SCLOECTL     0x10
 244 #define I2MCFG_WBUSYCTL     0x08
 245 #define I2MCFG_NORETRY      0x04
 246 #define I2MCFG_I2MLDSEQ     0x02
 247 #define I2MCFG_I2CMFAST     0x01
 248
 249 //
 250 // Bits in the I2MCSR EEPROM register
 251 //
 252 #define I2MCSR_EEMW         0x80
 253 #define I2MCSR_EEMR         0x40
 254 #define I2MCSR_AUTOLD       0x08
 255 #define I2MCSR_NACK         0x02
 256 #define I2MCSR_DONE         0x01
 257
 258 //
 259 // Bits in the PMC1 register
 260 //
 261 #define SPS_RST             0x80
 262 #define PCISTIKY            0x40
 263 #define PME_OVR             0x02
 264
 265 //
 266 // Bits in the STICKYHW register
 267 //
 268 #define STICKHW_DS1_SHADOW  0x02
 269 #define STICKHW_DS0_SHADOW  0x01
 270
 271 //
 272 // Bits in the TMCTL register
 273 //
 274 #define TMCTL_TSUSP         0x04
 275 #define TMCTL_TMD           0x02
 276 #define TMCTL_TE            0x01
 277
 278 //
 279 // Bits in the TFTCTL register
 280 //
 281 #define TFTCTL_HWUTSF       0x80        //
 282 #define TFTCTL_TBTTSYNC     0x40
 283 #define TFTCTL_HWUTSFEN     0x20
 284 #define TFTCTL_TSFCNTRRD    0x10        //
 285 #define TFTCTL_TBTTSYNCEN   0x08        //
 286 #define TFTCTL_TSFSYNCEN    0x04        //
 287 #define TFTCTL_TSFCNTRST    0x02        //
 288 #define TFTCTL_TSFCNTREN    0x01        //
 289
 290 //
 291 // Bits in the EnhanceCFG register
 292 //
 293 #define EnCFG_BarkerPream   0x00020000
 294 #define EnCFG_NXTBTTCFPSTR  0x00010000
 295 #define EnCFG_BcnSusClr     0x00000200
 296 #define EnCFG_BcnSusInd     0x00000100
 297 #define EnCFG_CFP_ProtectEn 0x00000040
 298 #define EnCFG_ProtectMd     0x00000020
 299 #define EnCFG_HwParCFP      0x00000010
 300 #define EnCFG_CFNULRSP      0x00000004
 301 #define EnCFG_BBType_MASK   0x00000003
 302 #define EnCFG_BBType_g      0x00000002
 303 #define EnCFG_BBType_b      0x00000001
 304 #define EnCFG_BBType_a      0x00000000
 305
 306 //
 307 // Bits in the Page1Sel register
 308 //
 309 #define PAGE1_SEL           0x01
 310
 311 //
 312 // Bits in the CFG register
 313 //
 314 #define CFG_TKIPOPT         0x80
 315 #define CFG_RXDMAOPT        0x40
 316 #define CFG_TMOT_SW         0x20
 317 #define CFG_TMOT_HWLONG     0x10
 318 #define CFG_TMOT_HW         0x00
 319 #define CFG_CFPENDOPT       0x08
 320 #define CFG_BCNSUSEN        0x04
 321 #define CFG_NOTXTIMEOUT     0x02
 322 #define CFG_NOBUFOPT        0x01
 323
 324 //
 325 // Bits in the TEST register
 326 //
 327 #define TEST_LBEXT          0x80        //
 328 #define TEST_LBINT          0x40        //
 329 #define TEST_LBNONE         0x00        //
 330 #define TEST_SOFTINT        0x20        //
 331 #define TEST_CONTTX         0x10        //
 332 #define TEST_TXPE           0x08        //
 333 #define TEST_NAVDIS         0x04        //
 334 #define TEST_NOCTS          0x02        //
 335 #define TEST_NOACK          0x01        //
 336
 337 //
 338 // Bits in the HOSTCR register
 339 //
 340 #define HOSTCR_TXONST       0x80        //
 341 #define HOSTCR_RXONST       0x40        //
 342 #define HOSTCR_ADHOC        0x20        // Network Type 1 = Ad-hoc
 343 #define HOSTCR_AP           0x10        // Port Type 1 = AP
 344 #define HOSTCR_TXON         0x08        //0000 1000
 345 #define HOSTCR_RXON         0x04        //0000 0100
 346 #define HOSTCR_MACEN        0x02        //0000 0010
 347 #define HOSTCR_SOFTRST      0x01        //0000 0001
 348
 349 //
 350 // Bits in the MACCR register
 351 //
 352 #define MACCR_SYNCFLUSHOK   0x04        //
 353 #define MACCR_SYNCFLUSH     0x02        //
 354 #define MACCR_CLRNAV        0x01        //
 355
 356 // Bits in the MAC_REG_GPIOCTL0 register
 357 //
 358 #define LED_ACTSET           0x01        //
 359 #define LED_RFOFF            0x02        //
 360 #define LED_NOCONNECT        0x04        //
 361 //
 362 // Bits in the RCR register
 363 //
 364 #define RCR_SSID            0x80
 365 #define RCR_RXALLTYPE       0x40        //
 366 #define RCR_UNICAST         0x20        //
 367 #define RCR_BROADCAST       0x10        //
 368 #define RCR_MULTICAST       0x08        //
 369 #define RCR_WPAERR          0x04        //
 370 #define RCR_ERRCRC          0x02        //
 371 #define RCR_BSSID           0x01        //
 372
 373 //
 374 // Bits in the TCR register
 375 //
 376 #define TCR_SYNCDCFOPT      0x02        //
 377 #define TCR_AUTOBCNTX       0x01        // Beacon automatically transmit enable
 378
 379 //
 380 // Bits in the IMR register
 381 //
 382 #define IMR_MEASURESTART    0x80000000      //
 383 #define IMR_QUIETSTART      0x20000000      //
 384 #define IMR_RADARDETECT     0x10000000      //
 385 #define IMR_MEASUREEND      0x08000000      //
 386 #define IMR_SOFTTIMER1      0x00200000      //
 387 #define IMR_RXDMA1          0x00001000      //0000 0000 0001 0000 0000 0000
 388 #define IMR_RXNOBUF         0x00000800      //
 389 #define IMR_MIBNEARFULL     0x00000400      //
 390 #define IMR_SOFTINT         0x00000200      //
 391 #define IMR_FETALERR        0x00000100      //
 392 #define IMR_WATCHDOG        0x00000080      //
 393 #define IMR_SOFTTIMER       0x00000040      //
 394 #define IMR_GPIO            0x00000020      //
 395 #define IMR_TBTT            0x00000010      //
 396 #define IMR_RXDMA0          0x00000008      //
 397 #define IMR_BNTX            0x00000004      //
 398 #define IMR_AC0DMA          0x00000002      //
 399 #define IMR_TXDMA0          0x00000001      //
 400
 401
 402 //
 403 // Bits in the ISR register
 404 //
 405
 406 #define ISR_MEASURESTART    0x80000000      //
 407 #define ISR_QUIETSTART      0x20000000      //
 408 #define ISR_RADARDETECT     0x10000000      //
 409 #define ISR_MEASUREEND      0x08000000      //
 410 #define ISR_SOFTTIMER1      0x00200000      //
 411 #define ISR_RXDMA1          0x00001000      //0000 0000 0001 0000 0000 0000
 412 #define ISR_RXNOBUF         0x00000800      //0000 0000 0000 1000 0000 0000
 413 #define ISR_MIBNEARFULL     0x00000400      //0000 0000 0000 0100 0000 0000
 414 #define ISR_SOFTINT         0x00000200      //
 415 #define ISR_FETALERR        0x00000100      //
 416 #define ISR_WATCHDOG        0x00000080      //
 417 #define ISR_SOFTTIMER       0x00000040      //
 418 #define ISR_GPIO            0x00000020      //
 419 #define ISR_TBTT            0x00000010      //
 420 #define ISR_RXDMA0          0x00000008      //
 421 #define ISR_BNTX            0x00000004      //
 422 #define ISR_AC0DMA          0x00000002      //
 423 #define ISR_TXDMA0          0x00000001      //
 424
 425
 426 //
 427 // Bits in the PSCFG register
 428 //
 429 #define PSCFG_PHILIPMD      0x40        //
 430 #define PSCFG_WAKECALEN     0x20        //
 431 #define PSCFG_WAKETMREN     0x10        //
 432 #define PSCFG_BBPSPROG      0x08        //
 433 #define PSCFG_WAKESYN       0x04        //
 434 #define PSCFG_SLEEPSYN      0x02        //
 435 #define PSCFG_AUTOSLEEP     0x01        //
 436
 437 //
 438 // Bits in the PSCTL register
 439 //
 440 #define PSCTL_WAKEDONE      0x20        //
 441 #define PSCTL_PS            0x10        //
 442 #define PSCTL_GO2DOZE       0x08        //
 443 #define PSCTL_LNBCN         0x04        //
 444 #define PSCTL_ALBCN         0x02        //
 445 #define PSCTL_PSEN          0x01        //
 446
 447 //
 448 // Bits in the PSPWSIG register
 449 //
 450 #define PSSIG_WPE3          0x80        //
 451 #define PSSIG_WPE2          0x40        //
 452 #define PSSIG_WPE1          0x20        //
 453 #define PSSIG_WRADIOPE      0x10        //
 454 #define PSSIG_SPE3          0x08        //
 455 #define PSSIG_SPE2          0x04        //
 456 #define PSSIG_SPE1          0x02        //
 457 #define PSSIG_SRADIOPE      0x01        //
 458
 459 //
 460 // Bits in the BBREGCTL register
 461 //
 462 #define BBREGCTL_DONE       0x04        //
 463 #define BBREGCTL_REGR       0x02        //
 464 #define BBREGCTL_REGW       0x01        //
 465
 466 //
 467 // Bits in the IFREGCTL register
 468 //
 469 #define IFREGCTL_DONE       0x04        //
 470 #define IFREGCTL_IFRF       0x02        //
 471 #define IFREGCTL_REGW       0x01        //
 472
 473 //
 474 // Bits in the SOFTPWRCTL register
 475 //
 476 #define SOFTPWRCTL_RFLEOPT      0x0800  //
 477 #define SOFTPWRCTL_TXPEINV      0x0200  //
 478 #define SOFTPWRCTL_SWPECTI      0x0100  //
 479 #define SOFTPWRCTL_SWPAPE       0x0020  //
 480 #define SOFTPWRCTL_SWCALEN      0x0010  //
 481 #define SOFTPWRCTL_SWRADIO_PE   0x0008  //
 482 #define SOFTPWRCTL_SWPE2        0x0004  //
 483 #define SOFTPWRCTL_SWPE1        0x0002  //
 484 #define SOFTPWRCTL_SWPE3        0x0001  //
 485
 486 //
 487 // Bits in the GPIOCTL1 register
 488 //
 489 #define GPIO1_DATA1             0x20    //
 490 #define GPIO1_MD1               0x10    //
 491 #define GPIO1_DATA0             0x02    //
 492 #define GPIO1_MD0               0x01    //
 493
 494 //
 495 // Bits in the DMACTL register
 496 //
 497 #define DMACTL_CLRRUN       0x00080000  //
 498 #define DMACTL_RUN          0x00000008  //
 499 #define DMACTL_WAKE         0x00000004  //
 500 #define DMACTL_DEAD         0x00000002  //
 501 #define DMACTL_ACTIVE       0x00000001  //
 502 //
 503 // Bits in the RXDMACTL0 register
 504 //
 505 #define RX_PERPKT           0x00000100  //
 506 #define RX_PERPKTCLR        0x01000000  //
 507 //
 508 // Bits in the BCNDMACTL register
 509 //
 510 #define BEACON_READY        0x01        //
 511 //
 512 // Bits in the MISCFFCTL register
 513 //
 514 #define MISCFFCTL_WRITE     0x0001      //
 515
 516
 517 //
 518 // Bits in WAKEUPEN0
 519 //
 520 #define WAKEUPEN0_DIRPKT    0x10
 521 #define WAKEUPEN0_LINKOFF   0x08
 522 #define WAKEUPEN0_ATIMEN    0x04
 523 #define WAKEUPEN0_TIMEN     0x02
 524 #define WAKEUPEN0_MAGICEN   0x01
 525
 526 //
 527 // Bits in WAKEUPEN1
 528 //
 529 #define WAKEUPEN1_128_3     0x08
 530 #define WAKEUPEN1_128_2     0x04
 531 #define WAKEUPEN1_128_1     0x02
 532 #define WAKEUPEN1_128_0     0x01
 533
 534 //
 535 // Bits in WAKEUPSR0
 536 //
 537 #define WAKEUPSR0_DIRPKT    0x10
 538 #define WAKEUPSR0_LINKOFF   0x08
 539 #define WAKEUPSR0_ATIMEN    0x04
 540 #define WAKEUPSR0_TIMEN     0x02
 541 #define WAKEUPSR0_MAGICEN   0x01
 542
 543 //
 544 // Bits in WAKEUPSR1
 545 //
 546 #define WAKEUPSR1_128_3     0x08
 547 #define WAKEUPSR1_128_2     0x04
 548 #define WAKEUPSR1_128_1     0x02
 549 #define WAKEUPSR1_128_0     0x01
 550
 551 //
 552 // Bits in the MAC_REG_GPIOCTL register
 553 //
 554 #define GPIO0_MD            0x01        //
 555 #define GPIO0_DATA          0x02        //
 556 #define GPIO0_INTMD         0x04        //
 557 #define GPIO1_MD            0x10        //
 558 #define GPIO1_DATA          0x20        //
 559
 560
 561 //
 562 // Bits in the MSRCTL register
 563 //
 564 #define MSRCTL_FINISH       0x80
 565 #define MSRCTL_READY        0x40
 566 #define MSRCTL_RADARDETECT  0x20
 567 #define MSRCTL_EN           0x10
 568 #define MSRCTL_QUIETTXCHK   0x08
 569 #define MSRCTL_QUIETRPT     0x04
 570 #define MSRCTL_QUIETINT     0x02
 571 #define MSRCTL_QUIETEN      0x01
 572 //
 573 // Bits in the MSRCTL1 register
 574 //
 575 #define MSRCTL1_TXPWR       0x08
 576 #define MSRCTL1_CSAPAREN    0x04
 577 #define MSRCTL1_TXPAUSE     0x01
 578
 579
 580 // Loopback mode
 581 #define MAC_LB_EXT          0x02        //
 582 #define MAC_LB_INTERNAL     0x01        //
 583 #define MAC_LB_NONE         0x00        //
 584
 585 // Ethernet address filter type
 586 #define PKT_TYPE_NONE           0x00    // turn off receiver
 587 #define PKT_TYPE_ALL_MULTICAST  0x80
 588 #define PKT_TYPE_PROMISCUOUS    0x40
 589 #define PKT_TYPE_DIRECTED       0x20    // obsolete, directed address is always accepted
 590 #define PKT_TYPE_BROADCAST      0x10
 591 #define PKT_TYPE_MULTICAST      0x08
 592 #define PKT_TYPE_ERROR_WPA      0x04
 593 #define PKT_TYPE_ERROR_CRC      0x02
 594 #define PKT_TYPE_BSSID          0x01
 595
 596 #define Default_BI              0x200
 597
 598
 599 // MiscFIFO Offset
 600 #define MISCFIFO_KEYETRY0       32
 601 #define MISCFIFO_KEYENTRYSIZE   22
 602 #define MISCFIFO_SYNINFO_IDX    10
 603 #define MISCFIFO_SYNDATA_IDX    11
 604 #define MISCFIFO_SYNDATASIZE    21
 605
 606 // enabled mask value of irq
 607 #define IMR_MASK_VALUE     (IMR_SOFTTIMER1 | \
 608                             IMR_RXDMA1 | \
 609                             IMR_RXNOBUF | \
 610                             IMR_MIBNEARFULL | \
 611                             IMR_SOFTINT | \
 612                             IMR_FETALERR | \
 613                             IMR_WATCHDOG | \
 614                             IMR_SOFTTIMER | \
 615                             IMR_GPIO | \
 616                             IMR_TBTT | \
 617                             IMR_RXDMA0 | \
 618                             IMR_BNTX | \
 619                             IMR_AC0DMA | \
 620                             IMR_TXDMA0)
 621
 622 // max time out delay time
 623 #define W_MAX_TIMEOUT       0xFFF0U     //
 624
 625 // wait time within loop
 626 #define CB_DELAY_LOOP_WAIT  10          // 10ms
 627
 628 //
 629 // revision id
 630 //
 631 #define REV_ID_VT3253_A0    0x00
 632 #define REV_ID_VT3253_A1    0x01
 633 #define REV_ID_VT3253_B0    0x08
 634 #define REV_ID_VT3253_B1    0x09
 635
 636 /*---------------------  Export Types  ------------------------------*/
 637
 638 /*---------------------  Export Macros ------------------------------*/
 639
 640 #define MACvRegBitsOn(dwIoBase, byRegOfs, byBits)           \
 641 {                                                           \
 642     unsigned char byData;                                   \
 643     VNSvInPortB(dwIoBase + byRegOfs, &byData);              \
 644     VNSvOutPortB(dwIoBase + byRegOfs, byData | (byBits));   \
 645 }
 646
 647 #define MACvWordRegBitsOn(dwIoBase, byRegOfs, wBits)        \
 648 {                                                           \
 649     unsigned short wData;                                   \
 650     VNSvInPortW(dwIoBase + byRegOfs, &wData);               \
 651     VNSvOutPortW(dwIoBase + byRegOfs, wData | (wBits));     \
 652 }
 653
 654 #define MACvDWordRegBitsOn(dwIoBase, byRegOfs, dwBits)      \
 655 {                                                           \
 656     unsigned long dwData;                                   \
 657     VNSvInPortD(dwIoBase + byRegOfs, &dwData);              \
 658     VNSvOutPortD(dwIoBase + byRegOfs, dwData | (dwBits));   \
 659 }
 660
 661 #define MACvRegBitsOnEx(dwIoBase, byRegOfs, byMask, byBits) \
 662 {                                                           \
 663     unsigned char byData;                                   \
 664     VNSvInPortB(dwIoBase + byRegOfs, &byData);              \
 665     byData &= byMask;                                       \
 666     VNSvOutPortB(dwIoBase + byRegOfs, byData | (byBits));   \
 667 }
 668
 669 #define MACvRegBitsOff(dwIoBase, byRegOfs, byBits)          \
 670 {                                                           \
 671     unsigned char byData;                                   \
 672     VNSvInPortB(dwIoBase + byRegOfs, &byData);              \
 673     VNSvOutPortB(dwIoBase + byRegOfs, byData & ~(byBits));  \
 674 }
 675
 676 #define MACvWordRegBitsOff(dwIoBase, byRegOfs, wBits)       \
 677 {                                                           \
 678     unsigned short wData;                                   \
 679     VNSvInPortW(dwIoBase + byRegOfs, &wData);               \
 680     VNSvOutPortW(dwIoBase + byRegOfs, wData & ~(wBits));    \
 681 }
 682
 683 #define MACvDWordRegBitsOff(dwIoBase, byRegOfs, dwBits)     \
 684 {                                                           \
 685     unsigned long dwData;                                   \
 686     VNSvInPortD(dwIoBase + byRegOfs, &dwData);              \
 687     VNSvOutPortD(dwIoBase + byRegOfs, dwData & ~(dwBits));  \
 688 }
 689
 690 #define MACvGetCurrRx0DescAddr(dwIoBase, pdwCurrDescAddr)    \
 691 {                                                           \
 692     VNSvInPortD(dwIoBase + MAC_REG_RXDMAPTR0,               \
 693                 (unsigned long *)pdwCurrDescAddr);          \
 694 }
 695
 696 #define MACvGetCurrRx1DescAddr(dwIoBase, pdwCurrDescAddr)   \
 697 {                                                           \
 698     VNSvInPortD(dwIoBase + MAC_REG_RXDMAPTR1,               \
 699                 (unsigned long *)pdwCurrDescAddr);          \
 700 }
 701
 702 #define MACvGetCurrTx0DescAddr(dwIoBase, pdwCurrDescAddr)   \
 703 {                                                           \
 704     VNSvInPortD(dwIoBase + MAC_REG_TXDMAPTR0,               \
 705                 (unsigned long *)pdwCurrDescAddr);          \
 706 }
 707
 708 #define MACvGetCurrAC0DescAddr(dwIoBase, pdwCurrDescAddr)   \
 709 {                                                           \
 710     VNSvInPortD(dwIoBase + MAC_REG_AC0DMAPTR,               \
 711                 (unsigned long *)pdwCurrDescAddr);          \
 712 }
 713
 714 #define MACvGetCurrSyncDescAddr(dwIoBase, pdwCurrDescAddr)  \
 715 {                                                           \
 716     VNSvInPortD(dwIoBase + MAC_REG_SYNCDMAPTR,              \
 717                 (unsigned long *)pdwCurrDescAddr);          \
 718 }
 719
 720 #define MACvGetCurrATIMDescAddr(dwIoBase, pdwCurrDescAddr)  \
 721 {                                                           \
 722     VNSvInPortD(dwIoBase + MAC_REG_ATIMDMAPTR,              \
 723                 (unsigned long *)pdwCurrDescAddr);          \
 724 }                                                           \
 725
 726 // set the chip with current BCN tx descriptor address
 727 #define MACvSetCurrBCNTxDescAddr(dwIoBase, dwCurrDescAddr)  \
 728 {                                                           \
 729     VNSvOutPortD(dwIoBase + MAC_REG_BCNDMAPTR,              \
 730                  dwCurrDescAddr);                           \
 731 }
 732
 733 // set the chip with current BCN length
 734 #define MACvSetCurrBCNLength(dwIoBase, wCurrBCNLength)     \
 735 {                                                          \
 736     VNSvOutPortW(dwIoBase + MAC_REG_BCNDMACTL+2,           \
 737                  wCurrBCNLength);                          \
 738 }
 739
 740 #define MACvReadBSSIDAddress(dwIoBase, pbyEtherAddr)        \
 741 {                                                           \
 742     VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 1);           \
 743     VNSvInPortB(dwIoBase + MAC_REG_BSSID0,                  \
 744                 (unsigned char *)pbyEtherAddr);             \
 745     VNSvInPortB(dwIoBase + MAC_REG_BSSID0 + 1,              \
 746                 pbyEtherAddr + 1);                          \
 747     VNSvInPortB(dwIoBase + MAC_REG_BSSID0 + 2,              \
 748                 pbyEtherAddr + 2);                          \
 749     VNSvInPortB(dwIoBase + MAC_REG_BSSID0 + 3,              \
 750                 pbyEtherAddr + 3);                          \
 751     VNSvInPortB(dwIoBase + MAC_REG_BSSID0 + 4,              \
 752                 pbyEtherAddr + 4);                          \
 753     VNSvInPortB(dwIoBase + MAC_REG_BSSID0 + 5,              \
 754                 pbyEtherAddr + 5);                          \
 755     VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 0);           \
 756 }
 757
 758 #define MACvWriteBSSIDAddress(dwIoBase, pbyEtherAddr)       \
 759 {                                                           \
 760     VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 1);           \
 761     VNSvOutPortB(dwIoBase + MAC_REG_BSSID0,                 \
 762                 *(pbyEtherAddr));                           \
 763     VNSvOutPortB(dwIoBase + MAC_REG_BSSID0 + 1,             \
 764                 *(pbyEtherAddr + 1));                       \
 765     VNSvOutPortB(dwIoBase + MAC_REG_BSSID0 + 2,             \
 766                 *(pbyEtherAddr + 2));                       \
 767     VNSvOutPortB(dwIoBase + MAC_REG_BSSID0 + 3,             \
 768                 *(pbyEtherAddr + 3));                       \
 769     VNSvOutPortB(dwIoBase + MAC_REG_BSSID0 + 4,             \
 770                 *(pbyEtherAddr + 4));                       \
 771     VNSvOutPortB(dwIoBase + MAC_REG_BSSID0 + 5,             \
 772                 *(pbyEtherAddr + 5));                       \
 773     VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 0);           \
 774 }
 775
 776 #define MACvReadEtherAddress(dwIoBase, pbyEtherAddr)        \
 777 {                                                           \
 778     VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 1);           \
 779     VNSvInPortB(dwIoBase + MAC_REG_PAR0,                    \
 780                 (unsigned char *)pbyEtherAddr);             \
 781     VNSvInPortB(dwIoBase + MAC_REG_PAR0 + 1,                \
 782                 pbyEtherAddr + 1);                          \
 783     VNSvInPortB(dwIoBase + MAC_REG_PAR0 + 2,                \
 784                 pbyEtherAddr + 2);                          \
 785     VNSvInPortB(dwIoBase + MAC_REG_PAR0 + 3,                \
 786                 pbyEtherAddr + 3);                          \
 787     VNSvInPortB(dwIoBase + MAC_REG_PAR0 + 4,                \
 788                 pbyEtherAddr + 4);                          \
 789     VNSvInPortB(dwIoBase + MAC_REG_PAR0 + 5,                \
 790                 pbyEtherAddr + 5);                          \
 791     VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 0);           \
 792 }
 793
 794
 795 #define MACvWriteEtherAddress(dwIoBase, pbyEtherAddr)       \
 796 {                                                           \
 797     VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 1);           \
 798     VNSvOutPortB(dwIoBase + MAC_REG_PAR0,                   \
 799                 *pbyEtherAddr);                             \
 800     VNSvOutPortB(dwIoBase + MAC_REG_PAR0 + 1,               \
 801                 *(pbyEtherAddr + 1));                       \
 802     VNSvOutPortB(dwIoBase + MAC_REG_PAR0 + 2,               \
 803                 *(pbyEtherAddr + 2));                       \
 804     VNSvOutPortB(dwIoBase + MAC_REG_PAR0 + 3,               \
 805                 *(pbyEtherAddr + 3));                       \
 806     VNSvOutPortB(dwIoBase + MAC_REG_PAR0 + 4,               \
 807                 *(pbyEtherAddr + 4));                       \
 808     VNSvOutPortB(dwIoBase + MAC_REG_PAR0 + 5,               \
 809                 *(pbyEtherAddr + 5));                       \
 810     VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 0);           \
 811 }
 812
 813
 814 #define MACvClearISR(dwIoBase)                              \
 815 {                                                           \
 816     VNSvOutPortD(dwIoBase + MAC_REG_ISR, IMR_MASK_VALUE);   \
 817 }
 818
 819 #define MACvStart(dwIoBase)                                      \
 820 {                                                                \
 821     VNSvOutPortB(dwIoBase + MAC_REG_HOSTCR,                      \
 822                     (HOSTCR_MACEN | HOSTCR_RXON | HOSTCR_TXON)); \
 823 }
 824
 825 #define MACvRx0PerPktMode(dwIoBase)                         \
 826 {                                                           \
 827     VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL0, RX_PERPKT);  \
 828 }
 829
 830 #define MACvRx0BufferFillMode(dwIoBase)                         \
 831 {                                                               \
 832     VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL0, RX_PERPKTCLR);   \
 833 }
 834
 835 #define MACvRx1PerPktMode(dwIoBase)                         \
 836 {                                                           \
 837     VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL1, RX_PERPKT);  \
 838 }
 839
 840 #define MACvRx1BufferFillMode(dwIoBase)                         \
 841 {                                                               \
 842     VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL1, RX_PERPKTCLR);   \
 843 }
 844
 845 #define MACvRxOn(dwIoBase)                                      \
 846 {                                                               \
 847     MACvRegBitsOn(dwIoBase, MAC_REG_HOSTCR, HOSTCR_RXON);       \
 848 }
 849
 850 #define MACvReceive0(dwIoBase)                                  \
 851 {                                                               \
 852     unsigned long dwData;                                       \
 853     VNSvInPortD(dwIoBase + MAC_REG_RXDMACTL0, &dwData);         \
 854     if (dwData & DMACTL_RUN) {                                  \
 855         VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL0, DMACTL_WAKE);\
 856     }                                                           \
 857     else {                                                      \
 858         VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL0, DMACTL_RUN); \
 859     }                                                           \
 860 }
 861
 862 #define MACvReceive1(dwIoBase)                                  \
 863 {                                                               \
 864     unsigned long dwData;                                       \
 865     VNSvInPortD(dwIoBase + MAC_REG_RXDMACTL1, &dwData);         \
 866     if (dwData & DMACTL_RUN) {                                  \
 867         VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL1, DMACTL_WAKE);\
 868     }                                                           \
 869     else {                                                      \
 870         VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL1, DMACTL_RUN); \
 871     }                                                           \
 872 }
 873
 874 #define MACvTxOn(dwIoBase)                                      \
 875 {                                                               \
 876     MACvRegBitsOn(dwIoBase, MAC_REG_HOSTCR, HOSTCR_TXON);       \
 877 }
 878
 879 #define MACvTransmit0(dwIoBase)                                 \
 880 {                                                               \
 881     unsigned long dwData;                                       \
 882     VNSvInPortD(dwIoBase + MAC_REG_TXDMACTL0, &dwData);         \
 883     if (dwData & DMACTL_RUN) {                                  \
 884         VNSvOutPortD(dwIoBase + MAC_REG_TXDMACTL0, DMACTL_WAKE);\
 885     }                                                           \
 886     else {                                                      \
 887         VNSvOutPortD(dwIoBase + MAC_REG_TXDMACTL0, DMACTL_RUN); \
 888     }                                                           \
 889 }
 890
 891 #define MACvTransmitAC0(dwIoBase)                               \
 892 {                                                               \
 893     unsigned long dwData;                                       \
 894     VNSvInPortD(dwIoBase + MAC_REG_AC0DMACTL, &dwData);         \
 895     if (dwData & DMACTL_RUN) {                                  \
 896         VNSvOutPortD(dwIoBase + MAC_REG_AC0DMACTL, DMACTL_WAKE);\
 897     }                                                           \
 898     else {                                                      \
 899         VNSvOutPortD(dwIoBase + MAC_REG_AC0DMACTL, DMACTL_RUN); \
 900     }                                                           \
 901 }
 902
 903 #define MACvTransmitSYNC(dwIoBase)                               \
 904 {                                                                \
 905     unsigned long dwData;                                        \
 906     VNSvInPortD(dwIoBase + MAC_REG_SYNCDMACTL, &dwData);         \
 907     if (dwData & DMACTL_RUN) {                                   \
 908         VNSvOutPortD(dwIoBase + MAC_REG_SYNCDMACTL, DMACTL_WAKE);\
 909     }                                                            \
 910     else {                                                       \
 911         VNSvOutPortD(dwIoBase + MAC_REG_SYNCDMACTL, DMACTL_RUN); \
 912     }                                                            \
 913 }
 914
 915 #define MACvTransmitATIM(dwIoBase)                               \
 916 {                                                                \
 917     unsigned long dwData;                                        \
 918     VNSvInPortD(dwIoBase + MAC_REG_ATIMDMACTL, &dwData);         \
 919     if (dwData & DMACTL_RUN) {                                   \
 920         VNSvOutPortD(dwIoBase + MAC_REG_ATIMDMACTL, DMACTL_WAKE);\
 921     }                                                            \
 922     else {                                                       \
 923         VNSvOutPortD(dwIoBase + MAC_REG_ATIMDMACTL, DMACTL_RUN); \
 924     }                                                            \
 925 }
 926
 927 #define MACvTransmitBCN(dwIoBase)                               \
 928 {                                                               \
 929     VNSvOutPortB(dwIoBase + MAC_REG_BCNDMACTL, BEACON_READY);   \
 930 }
 931
 932 #define MACvClearStckDS(dwIoBase)                           \
 933 {                                                           \
 934     unsigned char byOrgValue;                               \
 935     VNSvInPortB(dwIoBase + MAC_REG_STICKHW, &byOrgValue);   \
 936     byOrgValue = byOrgValue & 0xFC;                         \
 937     VNSvOutPortB(dwIoBase + MAC_REG_STICKHW, byOrgValue);   \
 938 }
 939
 940 #define MACvReadISR(dwIoBase, pdwValue)             \
 941 {                                                   \
 942     VNSvInPortD(dwIoBase + MAC_REG_ISR, pdwValue);  \
 943 }
 944
 945 #define MACvWriteISR(dwIoBase, dwValue)             \
 946 {                                                   \
 947     VNSvOutPortD(dwIoBase + MAC_REG_ISR, dwValue);  \
 948 }
 949
 950 #define MACvIntEnable(dwIoBase, dwMask)             \
 951 {                                                   \
 952     VNSvOutPortD(dwIoBase + MAC_REG_IMR, dwMask);   \
 953 }
 954
 955 #define MACvIntDisable(dwIoBase)                    \
 956 {                                                   \
 957     VNSvOutPortD(dwIoBase + MAC_REG_IMR, 0);        \
 958 }
 959
 960 #define MACvSelectPage0(dwIoBase)                   \
 961 {                                                   \
 962     VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 0);   \
 963 }
 964 #define MACvSelectPage1(dwIoBase)                   \
 965 {                                                   \
 966     VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 1);   \
 967 }
 968
 969 #define MACvReadMIBCounter(dwIoBase, pdwCounter)            \
 970 {                                                           \
 971     VNSvInPortD(dwIoBase + MAC_REG_MIBCNTR , pdwCounter);   \
 972 }
 973
 974 #define MACvPwrEvntDisable(dwIoBase)                    \
 975 {                                                       \
 976     VNSvOutPortW(dwIoBase + MAC_REG_WAKEUPEN0, 0x0000); \
 977 }
 978
 979 #define MACvEnableProtectMD(dwIoBase)                    \
 980 {                                                        \
 981     unsigned long dwOrgValue;                            \
 982     VNSvInPortD(dwIoBase + MAC_REG_ENCFG , &dwOrgValue); \
 983     dwOrgValue = dwOrgValue | EnCFG_ProtectMd;           \
 984     VNSvOutPortD(dwIoBase + MAC_REG_ENCFG, dwOrgValue);  \
 985 }
 986
 987 #define MACvDisableProtectMD(dwIoBase)                   \
 988 {                                                        \
 989     unsigned long dwOrgValue;                            \
 990     VNSvInPortD(dwIoBase + MAC_REG_ENCFG , &dwOrgValue); \
 991     dwOrgValue = dwOrgValue & ~EnCFG_ProtectMd;          \
 992     VNSvOutPortD(dwIoBase + MAC_REG_ENCFG, dwOrgValue);  \
 993 }
 994
 995 #define MACvEnableBarkerPreambleMd(dwIoBase)             \
 996 {                                                        \
 997     unsigned long dwOrgValue;                            \
 998     VNSvInPortD(dwIoBase + MAC_REG_ENCFG , &dwOrgValue); \
 999     dwOrgValue = dwOrgValue | EnCFG_BarkerPream;         \
1000     VNSvOutPortD(dwIoBase + MAC_REG_ENCFG, dwOrgValue);  \
1001 }
1002
1003 #define MACvDisableBarkerPreambleMd(dwIoBase)            \
1004 {                                                        \
1005     unsigned long dwOrgValue;                            \
1006     VNSvInPortD(dwIoBase + MAC_REG_ENCFG , &dwOrgValue); \
1007     dwOrgValue = dwOrgValue & ~EnCFG_BarkerPream;        \
1008     VNSvOutPortD(dwIoBase + MAC_REG_ENCFG, dwOrgValue);  \
1009 }
1010
1011 #define MACvSetBBType(dwIoBase, byTyp)                   \
1012 {                                                        \
1013     unsigned long dwOrgValue;                            \
1014     VNSvInPortD(dwIoBase + MAC_REG_ENCFG , &dwOrgValue); \
1015     dwOrgValue = dwOrgValue & ~EnCFG_BBType_MASK;        \
1016     dwOrgValue = dwOrgValue | (unsigned long) byTyp;     \
1017     VNSvOutPortD(dwIoBase + MAC_REG_ENCFG, dwOrgValue);  \
1018 }
1019
1020 #define MACvReadATIMW(dwIoBase, pwCounter)                 \
1021 {                                                          \
1022     VNSvInPortW(dwIoBase + MAC_REG_AIDATIM , pwCounter);   \
1023 }
1024
1025 #define MACvWriteATIMW(dwIoBase, wCounter)                 \
1026 {                                                          \
1027     VNSvOutPortW(dwIoBase + MAC_REG_AIDATIM , wCounter);   \
1028 }
1029
1030 #define MACvWriteCRC16_128(dwIoBase, byRegOfs, wCRC)       \
1031 {                                                          \
1032     VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 1);          \
1033     VNSvOutPortW(dwIoBase + byRegOfs, wCRC);               \
1034     VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 0);          \
1035 }
1036
1037 #define MACvGPIOIn(dwIoBase, pbyValue)                      \
1038 {                                                           \
1039     VNSvInPortB(dwIoBase + MAC_REG_GPIOCTL1, pbyValue);     \
1040 }
1041
1042 #define MACvSetRFLE_LatchBase(dwIoBase)                                 \
1043 {                                                                        \
1044     MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_RFLEOPT); \
1045 }
1046
1047 /*---------------------  Export Classes  ----------------------------*/
1048
1049 /*---------------------  Export Variables  --------------------------*/
1050
1051 /*---------------------  Export Functions  --------------------------*/
1052
1053 extern unsigned short TxRate_iwconfig;//2008-5-8 <add> by chester
1054 void MACvReadAllRegs(unsigned long dwIoBase, unsigned char *pbyMacRegs);
1055
1056 bool MACbIsRegBitsOn(unsigned long dwIoBase, unsigned char byRegOfs, unsigned char byTestBits);
1057 bool MACbIsRegBitsOff(unsigned long dwIoBase, unsigned char byRegOfs, unsigned char byTestBits);
1058
1059 bool MACbIsIntDisable(unsigned long dwIoBase);
1060
1061 unsigned char MACbyReadMultiAddr(unsigned long dwIoBase, unsigned int uByteIdx);
1062 void MACvWriteMultiAddr(unsigned long dwIoBase, unsigned int uByteIdx, unsigned char byData);
1063 void MACvSetMultiAddrByHash(unsigned long dwIoBase, unsigned char byHashIdx);
1064 void MACvResetMultiAddrByHash(unsigned long dwIoBase, unsigned char byHashIdx);
1065
1066 void MACvSetRxThreshold(unsigned long dwIoBase, unsigned char byThreshold);
1067 void MACvGetRxThreshold(unsigned long dwIoBase, unsigned char *pbyThreshold);
1068
1069 void MACvSetTxThreshold(unsigned long dwIoBase, unsigned char byThreshold);
1070 void MACvGetTxThreshold(unsigned long dwIoBase, unsigned char *pbyThreshold);
1071
1072 void MACvSetDmaLength(unsigned long dwIoBase, unsigned char byDmaLength);
1073 void MACvGetDmaLength(unsigned long dwIoBase, unsigned char *pbyDmaLength);
1074
1075 void MACvSetShortRetryLimit(unsigned long dwIoBase, unsigned char byRetryLimit);
1076 void MACvGetShortRetryLimit(unsigned long dwIoBase, unsigned char *pbyRetryLimit);
1077
1078 void MACvSetLongRetryLimit(unsigned long dwIoBase, unsigned char byRetryLimit);
1079 void MACvGetLongRetryLimit(unsigned long dwIoBase, unsigned char *pbyRetryLimit);
1080
1081 void MACvSetLoopbackMode(unsigned long dwIoBase, unsigned char byLoopbackMode);
1082 bool MACbIsInLoopbackMode(unsigned long dwIoBase);
1083
1084 void MACvSetPacketFilter(unsigned long dwIoBase, unsigned short wFilterType);
1085
1086 void MACvSaveContext(unsigned long dwIoBase, unsigned char *pbyCxtBuf);
1087 void MACvRestoreContext(unsigned long dwIoBase, unsigned char *pbyCxtBuf);
1088 bool MACbCompareContext(unsigned long dwIoBase, unsigned char *pbyCxtBuf);
1089
1090 bool MACbSoftwareReset(unsigned long dwIoBase);
1091 bool MACbSafeSoftwareReset(unsigned long dwIoBase);
1092 bool MACbSafeRxOff(unsigned long dwIoBase);
1093 bool MACbSafeTxOff(unsigned long dwIoBase);
1094 bool MACbSafeStop(unsigned long dwIoBase);
1095 bool MACbShutdown(unsigned long dwIoBase);
1096 void MACvInitialize(unsigned long dwIoBase);
1097 void MACvSetCurrRx0DescAddr(unsigned long dwIoBase, unsigned long dwCurrDescAddr);
1098 void MACvSetCurrRx1DescAddr(unsigned long dwIoBase, unsigned long dwCurrDescAddr);
1099 void MACvSetCurrTXDescAddr(int iTxType, unsigned long dwIoBase, unsigned long dwCurrDescAddr);
1100 void MACvSetCurrTx0DescAddrEx(unsigned long dwIoBase, unsigned long dwCurrDescAddr);
1101 void MACvSetCurrAC0DescAddrEx(unsigned long dwIoBase, unsigned long dwCurrDescAddr);
1102 void MACvSetCurrSyncDescAddrEx(unsigned long dwIoBase, unsigned long dwCurrDescAddr);
1103 void MACvSetCurrATIMDescAddrEx(unsigned long dwIoBase, unsigned long dwCurrDescAddr);
1104 void MACvTimer0MicroSDelay(unsigned long dwIoBase, unsigned int uDelay);
1105 void MACvOneShotTimer0MicroSec(unsigned long dwIoBase, unsigned int uDelayTime);
1106 void MACvOneShotTimer1MicroSec(unsigned long dwIoBase, unsigned int uDelayTime);
1107
1108 void MACvSetMISCFifo(unsigned long dwIoBase, unsigned short wOffset, unsigned long dwData);
1109
1110 bool MACbTxDMAOff (unsigned long dwIoBase, unsigned int idx);
1111
1112 void MACvClearBusSusInd(unsigned long dwIoBase);
1113 void MACvEnableBusSusEn(unsigned long dwIoBase);
1114
1115 bool MACbFlushSYNCFifo(unsigned long dwIoBase);
1116 bool MACbPSWakeup(unsigned long dwIoBase);
1117
1118 void MACvSetKeyEntry(unsigned long dwIoBase, unsigned short wKeyCtl, unsigned int uEntryIdx,
1119                 unsigned int uKeyIdx, unsigned char *pbyAddr, unsigned long *pdwKey, unsigned char byLocalID);
1120 void MACvDisableKeyEntry(unsigned long dwIoBase, unsigned int uEntryIdx);
1121 void MACvSetDefaultKeyEntry(unsigned long dwIoBase, unsigned int uKeyLen,
1122                 unsigned int uKeyIdx, unsigned long *pdwKey, unsigned char byLocalID);
1123 //void MACvEnableDefaultKey(unsigned long dwIoBase, unsigned char byLocalID);
1124 void MACvDisableDefaultKey(unsigned long dwIoBase);
1125 void MACvSetDefaultTKIPKeyEntry(unsigned long dwIoBase, unsigned int uKeyLen,
1126                 unsigned int uKeyIdx, unsigned long *pdwKey, unsigned char byLocalID);
1127 void MACvSetDefaultKeyCtl(unsigned long dwIoBase, unsigned short wKeyCtl, unsigned int uEntryIdx, unsigned char byLocalID);
1128
1129 #endif // __MAC_H__
1130