2 * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
22 * Purpose: Implement functions to access baseband
29 * BBuGetFrameTime - Calculate data frame transmitting time
30 * BBvCaculateParameter - Caculate PhyLength, PhyService and Phy Signal parameter for baseband Tx
31 * BBbReadEmbedded - Embedded read baseband register via MAC
32 * BBbWriteEmbedded - Embedded write baseband register via MAC
33 * BBbIsRegBitsOn - Test if baseband register bits on
34 * BBbIsRegBitsOff - Test if baseband register bits off
35 * BBbVT3253Init - VIA VT3253 baseband chip init code
36 * BBvReadAllRegs - Read All Baseband Registers
37 * BBvLoopbackOn - Turn on BaseBand Loopback mode
38 * BBvLoopbackOff - Turn off BaseBand Loopback mode
41 * 06-10-2003 Bryan YC Fan: Re-write codes to support VT3253 spec.
42 * 08-07-2003 Bryan YC Fan: Add MAXIM2827/2825 and RFMD2959 support.
43 * 08-26-2003 Kyle Hsu : Modify BBuGetFrameTime() and BBvCalculateParameter().
44 * cancel the setting of MAC_REG_SOFTPWRCTL on BBbVT3253Init().
46 * 09-01-2003 Bryan YC Fan: RF & BB tables updated.
47 * Modified BBvLoopbackOn & BBvLoopbackOff().
59 /*--------------------- Static Definitions -------------------------*/
60 //static int msglevel =MSG_LEVEL_DEBUG;
61 static int msglevel =MSG_LEVEL_INFO;
63 /*--------------------- Static Classes ----------------------------*/
65 /*--------------------- Static Variables --------------------------*/
67 /*--------------------- Static Functions --------------------------*/
69 /*--------------------- Export Variables --------------------------*/
71 /*--------------------- Static Definitions -------------------------*/
73 /*--------------------- Static Classes ----------------------------*/
75 /*--------------------- Static Variables --------------------------*/
79 #define CB_VT3253_INIT_FOR_RFMD 446
80 unsigned char byVT3253InitTab_RFMD[CB_VT3253_INIT_FOR_RFMD][2] = {
529 #define CB_VT3253B0_INIT_FOR_RFMD 256
530 unsigned char byVT3253B0_RFMD[CB_VT3253B0_INIT_FOR_RFMD][2] = {
789 #define CB_VT3253B0_AGC_FOR_RFMD2959 195
791 unsigned char byVT3253B0_AGC4_RFMD2959[CB_VT3253B0_AGC_FOR_RFMD2959][2] = {
989 #define CB_VT3253B0_INIT_FOR_AIROHA2230 256
991 unsigned char byVT3253B0_AIROHA2230[CB_VT3253B0_INIT_FOR_AIROHA2230][2] = {
1101 {0x6c, 0x00}, //RobertYu:20050125, request by JJSue
1253 #define CB_VT3253B0_INIT_FOR_UW2451 256
1255 unsigned char byVT3253B0_UW2451[CB_VT3253B0_INIT_FOR_UW2451][2] = {
1365 {0x6c, 0x00}, //RobertYu:20050125, request by JJSue
1515 #define CB_VT3253B0_AGC 193
1517 unsigned char byVT3253B0_AGC[CB_VT3253B0_AGC][2] = {
1713 const unsigned short awcFrameTime[MAX_RATE] =
1714 {10, 20, 55, 110, 24, 36, 48, 72, 96, 144, 192, 216};
1717 /*--------------------- Static Functions --------------------------*/
1721 s_ulGetRatio(PSDevice pDevice);
1737 //printk("Enter s_vChangeAntenna:original RxMode is %d,TxMode is %d\n",pDevice->byRxAntennaMode,pDevice->byTxAntennaMode);
1739 if ( pDevice->dwRxAntennaSel == 0) {
1740 pDevice->dwRxAntennaSel=1;
1741 if (pDevice->bTxRxAntInv == true)
1742 BBvSetRxAntennaMode(pDevice->PortOffset, ANT_A);
1744 BBvSetRxAntennaMode(pDevice->PortOffset, ANT_B);
1746 pDevice->dwRxAntennaSel=0;
1747 if (pDevice->bTxRxAntInv == true)
1748 BBvSetRxAntennaMode(pDevice->PortOffset, ANT_B);
1750 BBvSetRxAntennaMode(pDevice->PortOffset, ANT_A);
1752 if ( pDevice->dwTxAntennaSel == 0) {
1753 pDevice->dwTxAntennaSel=1;
1754 BBvSetTxAntennaMode(pDevice->PortOffset, ANT_B);
1756 pDevice->dwTxAntennaSel=0;
1757 BBvSetTxAntennaMode(pDevice->PortOffset, ANT_A);
1762 /*--------------------- Export Variables --------------------------*/
1764 * Description: Calculate data frame transmitting time
1768 * byPreambleType - Preamble Type
1769 * byPktType - PK_TYPE_11A, PK_TYPE_11B, PK_TYPE_11GB, PK_TYPE_11GA
1770 * cbFrameLength - Baseband Type
1774 * Return Value: FrameTime
1779 unsigned char byPreambleType,
1780 unsigned char byPktType,
1781 unsigned int cbFrameLength,
1782 unsigned short wRate
1785 unsigned int uFrameTime;
1786 unsigned int uPreamble;
1788 unsigned int uRateIdx = (unsigned int) wRate;
1789 unsigned int uRate = 0;
1792 if (uRateIdx > RATE_54M) {
1797 uRate = (unsigned int) awcFrameTime[uRateIdx];
1799 if (uRateIdx <= 3) { //CCK mode
1801 if (byPreambleType == 1) {//Short
1806 uFrameTime = (cbFrameLength * 80) / uRate; //?????
1807 uTmp = (uFrameTime * uRate) / 80;
1808 if (cbFrameLength != uTmp) {
1812 return (uPreamble + uFrameTime);
1815 uFrameTime = (cbFrameLength * 8 + 22) / uRate; //????????
1816 uTmp = ((uFrameTime * uRate) - 22) / 8;
1817 if(cbFrameLength != uTmp) {
1820 uFrameTime = uFrameTime * 4; //???????
1821 if(byPktType != PK_TYPE_11A) {
1822 uFrameTime += 6; //??????
1824 return (20 + uFrameTime); //??????
1829 * Description: Calculate Length, Service, and Signal fields of Phy for Tx
1833 * pDevice - Device Structure
1834 * cbFrameLength - Tx Frame Length
1837 * pwPhyLen - pointer to Phy Length field
1838 * pbyPhySrv - pointer to Phy Service field
1839 * pbyPhySgn - pointer to Phy Signal field
1841 * Return Value: none
1845 BBvCalculateParameter (
1847 unsigned int cbFrameLength,
1848 unsigned short wRate,
1849 unsigned char byPacketType,
1850 unsigned short *pwPhyLen,
1851 unsigned char *pbyPhySrv,
1852 unsigned char *pbyPhySgn
1855 unsigned int cbBitCount;
1856 unsigned int cbUsCount = 0;
1859 unsigned char byPreambleType = pDevice->byPreambleType;
1860 bool bCCK = pDevice->bCCK;
1862 cbBitCount = cbFrameLength * 8;
1867 cbUsCount = cbBitCount;
1872 cbUsCount = cbBitCount / 2;
1873 if (byPreambleType == 1)
1875 else // long preamble
1882 cbUsCount = (cbBitCount * 10) / 55;
1883 cbTmp = (cbUsCount * 55) / 10;
1884 if (cbTmp != cbBitCount)
1886 if (byPreambleType == 1)
1888 else // long preamble
1896 cbUsCount = cbBitCount / 11;
1897 cbTmp = cbUsCount * 11;
1898 if (cbTmp != cbBitCount) {
1900 if ((cbBitCount - cbTmp) <= 3)
1903 if (byPreambleType == 1)
1905 else // long preamble
1910 if(byPacketType == PK_TYPE_11A) {//11a, 5GHZ
1911 *pbyPhySgn = 0x9B; //1001 1011
1914 *pbyPhySgn = 0x8B; //1000 1011
1919 if(byPacketType == PK_TYPE_11A) {//11a, 5GHZ
1920 *pbyPhySgn = 0x9F; //1001 1111
1923 *pbyPhySgn = 0x8F; //1000 1111
1928 if(byPacketType == PK_TYPE_11A) {//11a, 5GHZ
1929 *pbyPhySgn = 0x9A; //1001 1010
1932 *pbyPhySgn = 0x8A; //1000 1010
1937 if(byPacketType == PK_TYPE_11A) {//11a, 5GHZ
1938 *pbyPhySgn = 0x9E; //1001 1110
1941 *pbyPhySgn = 0x8E; //1000 1110
1946 if(byPacketType == PK_TYPE_11A) {//11a, 5GHZ
1947 *pbyPhySgn = 0x99; //1001 1001
1950 *pbyPhySgn = 0x89; //1000 1001
1955 if(byPacketType == PK_TYPE_11A) {//11a, 5GHZ
1956 *pbyPhySgn = 0x9D; //1001 1101
1959 *pbyPhySgn = 0x8D; //1000 1101
1964 if(byPacketType == PK_TYPE_11A) {//11a, 5GHZ
1965 *pbyPhySgn = 0x98; //1001 1000
1968 *pbyPhySgn = 0x88; //1000 1000
1973 if (byPacketType == PK_TYPE_11A) {//11a, 5GHZ
1974 *pbyPhySgn = 0x9C; //1001 1100
1977 *pbyPhySgn = 0x8C; //1000 1100
1982 if (byPacketType == PK_TYPE_11A) {//11a, 5GHZ
1983 *pbyPhySgn = 0x9C; //1001 1100
1986 *pbyPhySgn = 0x8C; //1000 1100
1991 if (byPacketType == PK_TYPE_11B) {
1994 *pbyPhySrv = *pbyPhySrv | 0x80;
1995 *pwPhyLen = (unsigned short)cbUsCount;
1999 *pwPhyLen = (unsigned short)cbFrameLength;
2004 * Description: Read a byte from BASEBAND, by embedded programming
2008 * dwIoBase - I/O base address
2009 * byBBAddr - address of register in Baseband
2011 * pbyData - data read
2013 * Return Value: true if succeeded; false if failed.
2016 bool BBbReadEmbedded (unsigned long dwIoBase, unsigned char byBBAddr, unsigned char *pbyData)
2019 unsigned char byValue;
2022 VNSvOutPortB(dwIoBase + MAC_REG_BBREGADR, byBBAddr);
2025 MACvRegBitsOn(dwIoBase, MAC_REG_BBREGCTL, BBREGCTL_REGR);
2026 // W_MAX_TIMEOUT is the timeout period
2027 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
2028 VNSvInPortB(dwIoBase + MAC_REG_BBREGCTL, &byValue);
2029 if (byValue & BBREGCTL_DONE)
2034 VNSvInPortB(dwIoBase + MAC_REG_BBREGDATA, pbyData);
2036 if (ww == W_MAX_TIMEOUT) {
2038 DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO" DBG_PORT80(0x30)\n");
2046 * Description: Write a Byte to BASEBAND, by embedded programming
2050 * dwIoBase - I/O base address
2051 * byBBAddr - address of register in Baseband
2052 * byData - data to write
2056 * Return Value: true if succeeded; false if failed.
2059 bool BBbWriteEmbedded (unsigned long dwIoBase, unsigned char byBBAddr, unsigned char byData)
2062 unsigned char byValue;
2065 VNSvOutPortB(dwIoBase + MAC_REG_BBREGADR, byBBAddr);
2067 VNSvOutPortB(dwIoBase + MAC_REG_BBREGDATA, byData);
2069 // turn on BBREGCTL_REGW
2070 MACvRegBitsOn(dwIoBase, MAC_REG_BBREGCTL, BBREGCTL_REGW);
2071 // W_MAX_TIMEOUT is the timeout period
2072 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
2073 VNSvInPortB(dwIoBase + MAC_REG_BBREGCTL, &byValue);
2074 if (byValue & BBREGCTL_DONE)
2078 if (ww == W_MAX_TIMEOUT) {
2080 DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO" DBG_PORT80(0x31)\n");
2088 * Description: Test if all bits are set for the Baseband register
2092 * dwIoBase - I/O base address
2093 * byBBAddr - address of register in Baseband
2094 * byTestBits - TestBits
2098 * Return Value: true if all TestBits are set; false otherwise.
2101 bool BBbIsRegBitsOn (unsigned long dwIoBase, unsigned char byBBAddr, unsigned char byTestBits)
2103 unsigned char byOrgData;
2105 BBbReadEmbedded(dwIoBase, byBBAddr, &byOrgData);
2106 return (byOrgData & byTestBits) == byTestBits;
2111 * Description: Test if all bits are clear for the Baseband register
2115 * dwIoBase - I/O base address
2116 * byBBAddr - address of register in Baseband
2117 * byTestBits - TestBits
2121 * Return Value: true if all TestBits are clear; false otherwise.
2124 bool BBbIsRegBitsOff (unsigned long dwIoBase, unsigned char byBBAddr, unsigned char byTestBits)
2126 unsigned char byOrgData;
2128 BBbReadEmbedded(dwIoBase, byBBAddr, &byOrgData);
2129 return (byOrgData & byTestBits) == 0;
2133 * Description: VIA VT3253 Baseband chip init function
2137 * dwIoBase - I/O base address
2138 * byRevId - Revision ID
2139 * byRFType - RF type
2143 * Return Value: true if succeeded; false if failed.
2147 bool BBbVT3253Init (PSDevice pDevice)
2149 bool bResult = true;
2151 unsigned long dwIoBase = pDevice->PortOffset;
2152 unsigned char byRFType = pDevice->byRFType;
2153 unsigned char byLocalID = pDevice->byLocalID;
2155 if (byRFType == RF_RFMD2959) {
2156 if (byLocalID <= REV_ID_VT3253_A1) {
2157 for (ii = 0; ii < CB_VT3253_INIT_FOR_RFMD; ii++) {
2158 bResult &= BBbWriteEmbedded(dwIoBase,byVT3253InitTab_RFMD[ii][0],byVT3253InitTab_RFMD[ii][1]);
2161 for (ii = 0; ii < CB_VT3253B0_INIT_FOR_RFMD; ii++) {
2162 bResult &= BBbWriteEmbedded(dwIoBase,byVT3253B0_RFMD[ii][0],byVT3253B0_RFMD[ii][1]);
2164 for (ii = 0; ii < CB_VT3253B0_AGC_FOR_RFMD2959; ii++) {
2165 bResult &= BBbWriteEmbedded(dwIoBase,byVT3253B0_AGC4_RFMD2959[ii][0],byVT3253B0_AGC4_RFMD2959[ii][1]);
2167 VNSvOutPortD(dwIoBase + MAC_REG_ITRTMSET, 0x23);
2168 MACvRegBitsOn(dwIoBase, MAC_REG_PAPEDELAY, BIT0);
2170 pDevice->abyBBVGA[0] = 0x18;
2171 pDevice->abyBBVGA[1] = 0x0A;
2172 pDevice->abyBBVGA[2] = 0x0;
2173 pDevice->abyBBVGA[3] = 0x0;
2174 pDevice->ldBmThreshold[0] = -70;
2175 pDevice->ldBmThreshold[1] = -50;
2176 pDevice->ldBmThreshold[2] = 0;
2177 pDevice->ldBmThreshold[3] = 0;
2178 } else if ((byRFType == RF_AIROHA) || (byRFType == RF_AL2230S) ) {
2179 for (ii = 0; ii < CB_VT3253B0_INIT_FOR_AIROHA2230; ii++) {
2180 bResult &= BBbWriteEmbedded(dwIoBase,byVT3253B0_AIROHA2230[ii][0],byVT3253B0_AIROHA2230[ii][1]);
2182 for (ii = 0; ii < CB_VT3253B0_AGC; ii++) {
2183 bResult &= BBbWriteEmbedded(dwIoBase,byVT3253B0_AGC[ii][0],byVT3253B0_AGC[ii][1]);
2185 pDevice->abyBBVGA[0] = 0x1C;
2186 pDevice->abyBBVGA[1] = 0x10;
2187 pDevice->abyBBVGA[2] = 0x0;
2188 pDevice->abyBBVGA[3] = 0x0;
2189 pDevice->ldBmThreshold[0] = -70;
2190 pDevice->ldBmThreshold[1] = -48;
2191 pDevice->ldBmThreshold[2] = 0;
2192 pDevice->ldBmThreshold[3] = 0;
2193 } else if (byRFType == RF_UW2451) {
2194 for (ii = 0; ii < CB_VT3253B0_INIT_FOR_UW2451; ii++) {
2195 bResult &= BBbWriteEmbedded(dwIoBase,byVT3253B0_UW2451[ii][0],byVT3253B0_UW2451[ii][1]);
2197 for (ii = 0; ii < CB_VT3253B0_AGC; ii++) {
2198 bResult &= BBbWriteEmbedded(dwIoBase,byVT3253B0_AGC[ii][0],byVT3253B0_AGC[ii][1]);
2200 VNSvOutPortB(dwIoBase + MAC_REG_ITRTMSET, 0x23);
2201 MACvRegBitsOn(dwIoBase, MAC_REG_PAPEDELAY, BIT0);
2203 pDevice->abyBBVGA[0] = 0x14;
2204 pDevice->abyBBVGA[1] = 0x0A;
2205 pDevice->abyBBVGA[2] = 0x0;
2206 pDevice->abyBBVGA[3] = 0x0;
2207 pDevice->ldBmThreshold[0] = -60;
2208 pDevice->ldBmThreshold[1] = -50;
2209 pDevice->ldBmThreshold[2] = 0;
2210 pDevice->ldBmThreshold[3] = 0;
2211 } else if (byRFType == RF_UW2452) {
2212 for (ii = 0; ii < CB_VT3253B0_INIT_FOR_UW2451; ii++) {
2213 bResult &= BBbWriteEmbedded(dwIoBase,byVT3253B0_UW2451[ii][0],byVT3253B0_UW2451[ii][1]);
2215 // Init ANT B select,TX Config CR09 = 0x61->0x45, 0x45->0x41(VC1/VC2 define, make the ANT_A, ANT_B inverted)
2216 //bResult &= BBbWriteEmbedded(dwIoBase,0x09,0x41);
2217 // Init ANT B select,RX Config CR10 = 0x28->0x2A, 0x2A->0x28(VC1/VC2 define, make the ANT_A, ANT_B inverted)
2218 //bResult &= BBbWriteEmbedded(dwIoBase,0x0a,0x28);
2219 // Select VC1/VC2, CR215 = 0x02->0x06
2220 bResult &= BBbWriteEmbedded(dwIoBase,0xd7,0x06);
2222 //{{RobertYu:20050125, request by Jack
2223 bResult &= BBbWriteEmbedded(dwIoBase,0x90,0x20);
2224 bResult &= BBbWriteEmbedded(dwIoBase,0x97,0xeb);
2227 //{{RobertYu:20050221, request by Jack
2228 bResult &= BBbWriteEmbedded(dwIoBase,0xa6,0x00);
2229 bResult &= BBbWriteEmbedded(dwIoBase,0xa8,0x30);
2231 bResult &= BBbWriteEmbedded(dwIoBase,0xb0,0x58);
2233 for (ii = 0; ii < CB_VT3253B0_AGC; ii++) {
2234 bResult &= BBbWriteEmbedded(dwIoBase,byVT3253B0_AGC[ii][0],byVT3253B0_AGC[ii][1]);
2236 //VNSvOutPortB(dwIoBase + MAC_REG_ITRTMSET, 0x23); // RobertYu: 20050104, 20050131 disable PA_Delay
2237 //MACvRegBitsOn(dwIoBase, MAC_REG_PAPEDELAY, BIT0); // RobertYu: 20050104, 20050131 disable PA_Delay
2239 pDevice->abyBBVGA[0] = 0x14;
2240 pDevice->abyBBVGA[1] = 0x0A;
2241 pDevice->abyBBVGA[2] = 0x0;
2242 pDevice->abyBBVGA[3] = 0x0;
2243 pDevice->ldBmThreshold[0] = -60;
2244 pDevice->ldBmThreshold[1] = -50;
2245 pDevice->ldBmThreshold[2] = 0;
2246 pDevice->ldBmThreshold[3] = 0;
2249 } else if (byRFType == RF_VT3226) {
2250 for (ii = 0; ii < CB_VT3253B0_INIT_FOR_AIROHA2230; ii++) {
2251 bResult &= BBbWriteEmbedded(dwIoBase,byVT3253B0_AIROHA2230[ii][0],byVT3253B0_AIROHA2230[ii][1]);
2253 for (ii = 0; ii < CB_VT3253B0_AGC; ii++) {
2254 bResult &= BBbWriteEmbedded(dwIoBase,byVT3253B0_AGC[ii][0],byVT3253B0_AGC[ii][1]);
2256 pDevice->abyBBVGA[0] = 0x1C;
2257 pDevice->abyBBVGA[1] = 0x10;
2258 pDevice->abyBBVGA[2] = 0x0;
2259 pDevice->abyBBVGA[3] = 0x0;
2260 pDevice->ldBmThreshold[0] = -70;
2261 pDevice->ldBmThreshold[1] = -48;
2262 pDevice->ldBmThreshold[2] = 0;
2263 pDevice->ldBmThreshold[3] = 0;
2264 // Fix VT3226 DFC system timing issue
2265 MACvSetRFLE_LatchBase(dwIoBase);
2266 //{{ RobertYu: 20050104
2267 } else if (byRFType == RF_AIROHA7230) {
2268 for (ii = 0; ii < CB_VT3253B0_INIT_FOR_AIROHA2230; ii++) {
2269 bResult &= BBbWriteEmbedded(dwIoBase,byVT3253B0_AIROHA2230[ii][0],byVT3253B0_AIROHA2230[ii][1]);
2272 //{{ RobertYu:20050223, request by JerryChung
2273 // Init ANT B select,TX Config CR09 = 0x61->0x45, 0x45->0x41(VC1/VC2 define, make the ANT_A, ANT_B inverted)
2274 //bResult &= BBbWriteEmbedded(dwIoBase,0x09,0x41);
2275 // Init ANT B select,RX Config CR10 = 0x28->0x2A, 0x2A->0x28(VC1/VC2 define, make the ANT_A, ANT_B inverted)
2276 //bResult &= BBbWriteEmbedded(dwIoBase,0x0a,0x28);
2277 // Select VC1/VC2, CR215 = 0x02->0x06
2278 bResult &= BBbWriteEmbedded(dwIoBase,0xd7,0x06);
2281 for (ii = 0; ii < CB_VT3253B0_AGC; ii++) {
2282 bResult &= BBbWriteEmbedded(dwIoBase,byVT3253B0_AGC[ii][0],byVT3253B0_AGC[ii][1]);
2284 pDevice->abyBBVGA[0] = 0x1C;
2285 pDevice->abyBBVGA[1] = 0x10;
2286 pDevice->abyBBVGA[2] = 0x0;
2287 pDevice->abyBBVGA[3] = 0x0;
2288 pDevice->ldBmThreshold[0] = -70;
2289 pDevice->ldBmThreshold[1] = -48;
2290 pDevice->ldBmThreshold[2] = 0;
2291 pDevice->ldBmThreshold[3] = 0;
2295 pDevice->bUpdateBBVGA = false;
2296 pDevice->abyBBVGA[0] = 0x1C;
2299 if (byLocalID > REV_ID_VT3253_A1) {
2300 BBbWriteEmbedded(dwIoBase, 0x04, 0x7F);
2301 BBbWriteEmbedded(dwIoBase, 0x0D, 0x01);
2310 * Description: Read All Baseband Registers
2314 * dwIoBase - I/O base address
2315 * pbyBBRegs - Point to struct that stores Baseband Registers
2319 * Return Value: none
2322 void BBvReadAllRegs (unsigned long dwIoBase, unsigned char *pbyBBRegs)
2325 unsigned char byBase = 1;
2326 for (ii = 0; ii < BB_MAX_CONTEXT_SIZE; ii++) {
2327 BBbReadEmbedded(dwIoBase, (unsigned char)(ii*byBase), pbyBBRegs);
2328 pbyBBRegs += byBase;
2333 * Description: Turn on BaseBand Loopback mode
2337 * dwIoBase - I/O base address
2338 * bCCK - If CCK is set
2342 * Return Value: none
2347 void BBvLoopbackOn (PSDevice pDevice)
2349 unsigned char byData;
2350 unsigned long dwIoBase = pDevice->PortOffset;
2353 BBbReadEmbedded(dwIoBase, 0xC9, &pDevice->byBBCRc9);//CR201
2354 BBbWriteEmbedded(dwIoBase, 0xC9, 0);
2355 BBbReadEmbedded(dwIoBase, 0x4D, &pDevice->byBBCR4d);//CR77
2356 BBbWriteEmbedded(dwIoBase, 0x4D, 0x90);
2358 //CR 88 = 0x02(CCK), 0x03(OFDM)
2359 BBbReadEmbedded(dwIoBase, 0x88, &pDevice->byBBCR88);//CR136
2361 if (pDevice->uConnectionRate <= RATE_11M) { //CCK
2362 // Enable internal digital loopback: CR33 |= 0000 0001
2363 BBbReadEmbedded(dwIoBase, 0x21, &byData);//CR33
2364 BBbWriteEmbedded(dwIoBase, 0x21, (unsigned char)(byData | 0x01));//CR33
2366 BBbWriteEmbedded(dwIoBase, 0x9A, 0); //CR154
2368 BBbWriteEmbedded(dwIoBase, 0x88, 0x02);//CR239
2371 // Enable internal digital loopback:CR154 |= 0000 0001
2372 BBbReadEmbedded(dwIoBase, 0x9A, &byData);//CR154
2373 BBbWriteEmbedded(dwIoBase, 0x9A, (unsigned char)(byData | 0x01));//CR154
2375 BBbWriteEmbedded(dwIoBase, 0x21, 0); //CR33
2377 BBbWriteEmbedded(dwIoBase, 0x88, 0x03);//CR239
2381 BBbWriteEmbedded(dwIoBase, 0x0E, 0);//CR14
2384 BBbReadEmbedded(pDevice->PortOffset, 0x09, &pDevice->byBBCR09);
2385 BBbWriteEmbedded(pDevice->PortOffset, 0x09, (unsigned char)(pDevice->byBBCR09 & 0xDE));
2389 * Description: Turn off BaseBand Loopback mode
2393 * pDevice - Device Structure
2398 * Return Value: none
2401 void BBvLoopbackOff (PSDevice pDevice)
2403 unsigned char byData;
2404 unsigned long dwIoBase = pDevice->PortOffset;
2406 BBbWriteEmbedded(dwIoBase, 0xC9, pDevice->byBBCRc9);//CR201
2407 BBbWriteEmbedded(dwIoBase, 0x88, pDevice->byBBCR88);//CR136
2408 BBbWriteEmbedded(dwIoBase, 0x09, pDevice->byBBCR09);//CR136
2409 BBbWriteEmbedded(dwIoBase, 0x4D, pDevice->byBBCR4d);//CR77
2411 if (pDevice->uConnectionRate <= RATE_11M) { // CCK
2412 // Set the CR33 Bit2 to disable internal Loopback.
2413 BBbReadEmbedded(dwIoBase, 0x21, &byData);//CR33
2414 BBbWriteEmbedded(dwIoBase, 0x21, (unsigned char)(byData & 0xFE));//CR33
2417 BBbReadEmbedded(dwIoBase, 0x9A, &byData);//CR154
2418 BBbWriteEmbedded(dwIoBase, 0x9A, (unsigned char)(byData & 0xFE));//CR154
2420 BBbReadEmbedded(dwIoBase, 0x0E, &byData);//CR14
2421 BBbWriteEmbedded(dwIoBase, 0x0E, (unsigned char)(byData | 0x80));//CR14
2428 * Description: Set ShortSlotTime mode
2432 * pDevice - Device Structure
2436 * Return Value: none
2440 BBvSetShortSlotTime (PSDevice pDevice)
2442 unsigned char byBBRxConf=0;
2443 unsigned char byBBVGA=0;
2445 BBbReadEmbedded(pDevice->PortOffset, 0x0A, &byBBRxConf);//CR10
2447 if (pDevice->bShortSlotTime) {
2448 byBBRxConf &= 0xDF;//1101 1111
2450 byBBRxConf |= 0x20;//0010 0000
2453 // patch for 3253B0 Baseband with Cardbus module
2454 BBbReadEmbedded(pDevice->PortOffset, 0xE7, &byBBVGA);
2455 if (byBBVGA == pDevice->abyBBVGA[0]) {
2456 byBBRxConf |= 0x20;//0010 0000
2459 BBbWriteEmbedded(pDevice->PortOffset, 0x0A, byBBRxConf);//CR10
2463 void BBvSetVGAGainOffset(PSDevice pDevice, unsigned char byData)
2465 unsigned char byBBRxConf=0;
2467 BBbWriteEmbedded(pDevice->PortOffset, 0xE7, byData);
2469 BBbReadEmbedded(pDevice->PortOffset, 0x0A, &byBBRxConf);//CR10
2470 // patch for 3253B0 Baseband with Cardbus module
2471 if (byData == pDevice->abyBBVGA[0]) {
2472 byBBRxConf |= 0x20;//0010 0000
2473 } else if (pDevice->bShortSlotTime) {
2474 byBBRxConf &= 0xDF;//1101 1111
2476 byBBRxConf |= 0x20;//0010 0000
2478 pDevice->byBBVGACurrent = byData;
2479 BBbWriteEmbedded(pDevice->PortOffset, 0x0A, byBBRxConf);//CR10
2484 * Description: Baseband SoftwareReset
2488 * dwIoBase - I/O base address
2492 * Return Value: none
2496 BBvSoftwareReset (unsigned long dwIoBase)
2498 BBbWriteEmbedded(dwIoBase, 0x50, 0x40);
2499 BBbWriteEmbedded(dwIoBase, 0x50, 0);
2500 BBbWriteEmbedded(dwIoBase, 0x9C, 0x01);
2501 BBbWriteEmbedded(dwIoBase, 0x9C, 0);
2505 * Description: Baseband Power Save Mode ON
2509 * dwIoBase - I/O base address
2513 * Return Value: none
2517 BBvPowerSaveModeON (unsigned long dwIoBase)
2519 unsigned char byOrgData;
2521 BBbReadEmbedded(dwIoBase, 0x0D, &byOrgData);
2523 BBbWriteEmbedded(dwIoBase, 0x0D, byOrgData);
2527 * Description: Baseband Power Save Mode OFF
2531 * dwIoBase - I/O base address
2535 * Return Value: none
2539 BBvPowerSaveModeOFF (unsigned long dwIoBase)
2541 unsigned char byOrgData;
2543 BBbReadEmbedded(dwIoBase, 0x0D, &byOrgData);
2544 byOrgData &= ~(BIT0);
2545 BBbWriteEmbedded(dwIoBase, 0x0D, byOrgData);
2549 * Description: Set Tx Antenna mode
2553 * pDevice - Device Structure
2554 * byAntennaMode - Antenna Mode
2558 * Return Value: none
2563 BBvSetTxAntennaMode (unsigned long dwIoBase, unsigned char byAntennaMode)
2565 unsigned char byBBTxConf;
2568 //printk("Enter BBvSetTxAntennaMode\n");
2570 BBbReadEmbedded(dwIoBase, 0x09, &byBBTxConf);//CR09
2571 if (byAntennaMode == ANT_DIVERSITY) {
2572 // bit 1 is diversity
2574 } else if (byAntennaMode == ANT_A) {
2576 byBBTxConf &= 0xF9; // 1111 1001
2577 } else if (byAntennaMode == ANT_B) {
2579 //printk("BBvSetTxAntennaMode:ANT_B\n");
2581 byBBTxConf &= 0xFD; // 1111 1101
2584 BBbWriteEmbedded(dwIoBase, 0x09, byBBTxConf);//CR09
2591 * Description: Set Rx Antenna mode
2595 * pDevice - Device Structure
2596 * byAntennaMode - Antenna Mode
2600 * Return Value: none
2605 BBvSetRxAntennaMode (unsigned long dwIoBase, unsigned char byAntennaMode)
2607 unsigned char byBBRxConf;
2609 BBbReadEmbedded(dwIoBase, 0x0A, &byBBRxConf);//CR10
2610 if (byAntennaMode == ANT_DIVERSITY) {
2613 } else if (byAntennaMode == ANT_A) {
2614 byBBRxConf &= 0xFC; // 1111 1100
2615 } else if (byAntennaMode == ANT_B) {
2616 byBBRxConf &= 0xFE; // 1111 1110
2619 BBbWriteEmbedded(dwIoBase, 0x0A, byBBRxConf);//CR10
2624 * Description: BBvSetDeepSleep
2628 * pDevice - Device Structure
2632 * Return Value: none
2636 BBvSetDeepSleep (unsigned long dwIoBase, unsigned char byLocalID)
2638 BBbWriteEmbedded(dwIoBase, 0x0C, 0x17);//CR12
2639 BBbWriteEmbedded(dwIoBase, 0x0D, 0xB9);//CR13
2643 BBvExitDeepSleep (unsigned long dwIoBase, unsigned char byLocalID)
2645 BBbWriteEmbedded(dwIoBase, 0x0C, 0x00);//CR12
2646 BBbWriteEmbedded(dwIoBase, 0x0D, 0x01);//CR13
2653 s_ulGetRatio (PSDevice pDevice)
2655 unsigned long ulRatio = 0;
2656 unsigned long ulMaxPacket;
2657 unsigned long ulPacketNum;
2659 //This is a thousand-ratio
2660 ulMaxPacket = pDevice->uNumSQ3[RATE_54M];
2661 if ( pDevice->uNumSQ3[RATE_54M] != 0 ) {
2662 ulPacketNum = pDevice->uNumSQ3[RATE_54M];
2663 ulRatio = (ulPacketNum * 1000 / pDevice->uDiversityCnt);
2664 //ulRatio = (pDevice->uNumSQ3[RATE_54M] * 1000 / pDevice->uDiversityCnt);
2665 ulRatio += TOP_RATE_54M;
2667 if ( pDevice->uNumSQ3[RATE_48M] > ulMaxPacket ) {
2668 ulPacketNum = pDevice->uNumSQ3[RATE_54M] + pDevice->uNumSQ3[RATE_48M];
2669 ulRatio = (ulPacketNum * 1000 / pDevice->uDiversityCnt);
2670 //ulRatio = (pDevice->uNumSQ3[RATE_48M] * 1000 / pDevice->uDiversityCnt);
2671 ulRatio += TOP_RATE_48M;
2672 ulMaxPacket = pDevice->uNumSQ3[RATE_48M];
2674 if ( pDevice->uNumSQ3[RATE_36M] > ulMaxPacket ) {
2675 ulPacketNum = pDevice->uNumSQ3[RATE_54M] + pDevice->uNumSQ3[RATE_48M] +
2676 pDevice->uNumSQ3[RATE_36M];
2677 ulRatio = (ulPacketNum * 1000 / pDevice->uDiversityCnt);
2678 //ulRatio = (pDevice->uNumSQ3[RATE_36M] * 1000 / pDevice->uDiversityCnt);
2679 ulRatio += TOP_RATE_36M;
2680 ulMaxPacket = pDevice->uNumSQ3[RATE_36M];
2682 if ( pDevice->uNumSQ3[RATE_24M] > ulMaxPacket ) {
2683 ulPacketNum = pDevice->uNumSQ3[RATE_54M] + pDevice->uNumSQ3[RATE_48M] +
2684 pDevice->uNumSQ3[RATE_36M] + pDevice->uNumSQ3[RATE_24M];
2685 ulRatio = (ulPacketNum * 1000 / pDevice->uDiversityCnt);
2686 //ulRatio = (pDevice->uNumSQ3[RATE_24M] * 1000 / pDevice->uDiversityCnt);
2687 ulRatio += TOP_RATE_24M;
2688 ulMaxPacket = pDevice->uNumSQ3[RATE_24M];
2690 if ( pDevice->uNumSQ3[RATE_18M] > ulMaxPacket ) {
2691 ulPacketNum = pDevice->uNumSQ3[RATE_54M] + pDevice->uNumSQ3[RATE_48M] +
2692 pDevice->uNumSQ3[RATE_36M] + pDevice->uNumSQ3[RATE_24M] +
2693 pDevice->uNumSQ3[RATE_18M];
2694 ulRatio = (ulPacketNum * 1000 / pDevice->uDiversityCnt);
2695 //ulRatio = (pDevice->uNumSQ3[RATE_18M] * 1000 / pDevice->uDiversityCnt);
2696 ulRatio += TOP_RATE_18M;
2697 ulMaxPacket = pDevice->uNumSQ3[RATE_18M];
2699 if ( pDevice->uNumSQ3[RATE_12M] > ulMaxPacket ) {
2700 ulPacketNum = pDevice->uNumSQ3[RATE_54M] + pDevice->uNumSQ3[RATE_48M] +
2701 pDevice->uNumSQ3[RATE_36M] + pDevice->uNumSQ3[RATE_24M] +
2702 pDevice->uNumSQ3[RATE_18M] + pDevice->uNumSQ3[RATE_12M];
2703 ulRatio = (ulPacketNum * 1000 / pDevice->uDiversityCnt);
2704 //ulRatio = (pDevice->uNumSQ3[RATE_12M] * 1000 / pDevice->uDiversityCnt);
2705 ulRatio += TOP_RATE_12M;
2706 ulMaxPacket = pDevice->uNumSQ3[RATE_12M];
2708 if ( pDevice->uNumSQ3[RATE_11M] > ulMaxPacket ) {
2709 ulPacketNum = pDevice->uDiversityCnt - pDevice->uNumSQ3[RATE_1M] -
2710 pDevice->uNumSQ3[RATE_2M] - pDevice->uNumSQ3[RATE_5M] -
2711 pDevice->uNumSQ3[RATE_6M] - pDevice->uNumSQ3[RATE_9M];
2712 ulRatio = (ulPacketNum * 1000 / pDevice->uDiversityCnt);
2713 //ulRatio = (pDevice->uNumSQ3[RATE_11M] * 1000 / pDevice->uDiversityCnt);
2714 ulRatio += TOP_RATE_11M;
2715 ulMaxPacket = pDevice->uNumSQ3[RATE_11M];
2717 if ( pDevice->uNumSQ3[RATE_9M] > ulMaxPacket ) {
2718 ulPacketNum = pDevice->uDiversityCnt - pDevice->uNumSQ3[RATE_1M] -
2719 pDevice->uNumSQ3[RATE_2M] - pDevice->uNumSQ3[RATE_5M] -
2720 pDevice->uNumSQ3[RATE_6M];
2721 ulRatio = (ulPacketNum * 1000 / pDevice->uDiversityCnt);
2722 //ulRatio = (pDevice->uNumSQ3[RATE_9M] * 1000 / pDevice->uDiversityCnt);
2723 ulRatio += TOP_RATE_9M;
2724 ulMaxPacket = pDevice->uNumSQ3[RATE_9M];
2726 if ( pDevice->uNumSQ3[RATE_6M] > ulMaxPacket ) {
2727 ulPacketNum = pDevice->uDiversityCnt - pDevice->uNumSQ3[RATE_1M] -
2728 pDevice->uNumSQ3[RATE_2M] - pDevice->uNumSQ3[RATE_5M];
2729 ulRatio = (ulPacketNum * 1000 / pDevice->uDiversityCnt);
2730 //ulRatio = (pDevice->uNumSQ3[RATE_6M] * 1000 / pDevice->uDiversityCnt);
2731 ulRatio += TOP_RATE_6M;
2732 ulMaxPacket = pDevice->uNumSQ3[RATE_6M];
2734 if ( pDevice->uNumSQ3[RATE_5M] > ulMaxPacket ) {
2735 ulPacketNum = pDevice->uDiversityCnt - pDevice->uNumSQ3[RATE_1M] -
2736 pDevice->uNumSQ3[RATE_2M];
2737 ulRatio = (ulPacketNum * 1000 / pDevice->uDiversityCnt);
2738 //ulRatio = (pDevice->uNumSQ3[RATE_5M] * 1000 / pDevice->uDiversityCnt);
2739 ulRatio += TOP_RATE_55M;
2740 ulMaxPacket = pDevice->uNumSQ3[RATE_5M];
2742 if ( pDevice->uNumSQ3[RATE_2M] > ulMaxPacket ) {
2743 ulPacketNum = pDevice->uDiversityCnt - pDevice->uNumSQ3[RATE_1M];
2744 ulRatio = (ulPacketNum * 1000 / pDevice->uDiversityCnt);
2745 //ulRatio = (pDevice->uNumSQ3[RATE_2M] * 1000 / pDevice->uDiversityCnt);
2746 ulRatio += TOP_RATE_2M;
2747 ulMaxPacket = pDevice->uNumSQ3[RATE_2M];
2749 if ( pDevice->uNumSQ3[RATE_1M] > ulMaxPacket ) {
2750 ulPacketNum = pDevice->uDiversityCnt;
2751 ulRatio = (ulPacketNum * 1000 / pDevice->uDiversityCnt);
2752 //ulRatio = (pDevice->uNumSQ3[RATE_1M] * 1000 / pDevice->uDiversityCnt);
2753 ulRatio += TOP_RATE_1M;
2761 BBvClearAntDivSQ3Value (PSDevice pDevice)
2765 pDevice->uDiversityCnt = 0;
2766 for (ii = 0; ii < MAX_RATE; ii++) {
2767 pDevice->uNumSQ3[ii] = 0;
2773 * Description: Antenna Diversity
2777 * pDevice - Device Structure
2778 * byRSR - RSR from received packet
2779 * bySQ3 - SQ3 value from received packet
2783 * Return Value: none
2788 BBvAntennaDiversity (PSDevice pDevice, unsigned char byRxRate, unsigned char bySQ3)
2791 if ((byRxRate >= MAX_RATE) || (pDevice->wAntDiversityMaxRate >= MAX_RATE)) {
2794 pDevice->uDiversityCnt++;
2795 // DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO "pDevice->uDiversityCnt = %d\n", (int)pDevice->uDiversityCnt);
2797 pDevice->uNumSQ3[byRxRate]++;
2799 if (pDevice->byAntennaState == 0) {
2801 if (pDevice->uDiversityCnt > pDevice->ulDiversityNValue) {
2802 DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO"ulDiversityNValue=[%d],54M-[%d]\n",
2803 (int)pDevice->ulDiversityNValue, (int)pDevice->uNumSQ3[(int)pDevice->wAntDiversityMaxRate]);
2805 if (pDevice->uNumSQ3[pDevice->wAntDiversityMaxRate] < pDevice->uDiversityCnt/2) {
2807 pDevice->ulRatio_State0 = s_ulGetRatio(pDevice);
2808 DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO"SQ3_State0, rate = [%08x]\n", (int)pDevice->ulRatio_State0);
2810 if ( pDevice->byTMax == 0 )
2812 DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO"1.[%08x], uNumSQ3[%d]=%d, %d\n",
2813 (int)pDevice->ulRatio_State0, (int)pDevice->wAntDiversityMaxRate,
2814 (int)pDevice->uNumSQ3[(int)pDevice->wAntDiversityMaxRate], (int)pDevice->uDiversityCnt);
2816 //printk("BBvAntennaDiversity1:call s_vChangeAntenna\n");
2818 s_vChangeAntenna(pDevice);
2819 pDevice->byAntennaState = 1;
2820 del_timer(&pDevice->TimerSQ3Tmax3);
2821 del_timer(&pDevice->TimerSQ3Tmax2);
2822 pDevice->TimerSQ3Tmax1.expires = RUN_AT(pDevice->byTMax * HZ);
2823 add_timer(&pDevice->TimerSQ3Tmax1);
2827 pDevice->TimerSQ3Tmax3.expires = RUN_AT(pDevice->byTMax3 * HZ);
2828 add_timer(&pDevice->TimerSQ3Tmax3);
2830 BBvClearAntDivSQ3Value(pDevice);
2833 } else { //byAntennaState == 1
2835 if (pDevice->uDiversityCnt > pDevice->ulDiversityMValue) {
2837 del_timer(&pDevice->TimerSQ3Tmax1);
2839 pDevice->ulRatio_State1 = s_ulGetRatio(pDevice);
2840 DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO"RX:SQ3_State1, rate0 = %08x,rate1 = %08x\n",
2841 (int)pDevice->ulRatio_State0,(int)pDevice->ulRatio_State1);
2843 if (pDevice->ulRatio_State1 < pDevice->ulRatio_State0) {
2844 DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO"2.[%08x][%08x], uNumSQ3[%d]=%d, %d\n",
2845 (int)pDevice->ulRatio_State0, (int)pDevice->ulRatio_State1,
2846 (int)pDevice->wAntDiversityMaxRate,
2847 (int)pDevice->uNumSQ3[(int)pDevice->wAntDiversityMaxRate], (int)pDevice->uDiversityCnt);
2849 //printk("BBvAntennaDiversity2:call s_vChangeAntenna\n");
2851 s_vChangeAntenna(pDevice);
2852 pDevice->TimerSQ3Tmax3.expires = RUN_AT(pDevice->byTMax3 * HZ);
2853 pDevice->TimerSQ3Tmax2.expires = RUN_AT(pDevice->byTMax2 * HZ);
2854 add_timer(&pDevice->TimerSQ3Tmax3);
2855 add_timer(&pDevice->TimerSQ3Tmax2);
2857 pDevice->byAntennaState = 0;
2858 BBvClearAntDivSQ3Value(pDevice);
2866 * Timer for SQ3 antenna diversity
2873 * Return Value: none
2879 void *hDeviceContext
2882 PSDevice pDevice = (PSDevice)hDeviceContext;
2884 DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO"TimerSQ3CallBack...");
2885 spin_lock_irq(&pDevice->lock);
2887 DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO"3.[%08x][%08x], %d\n",(int)pDevice->ulRatio_State0, (int)pDevice->ulRatio_State1, (int)pDevice->uDiversityCnt);
2889 //printk("TimerSQ3CallBack1:call s_vChangeAntenna\n");
2892 s_vChangeAntenna(pDevice);
2893 pDevice->byAntennaState = 0;
2894 BBvClearAntDivSQ3Value(pDevice);
2896 pDevice->TimerSQ3Tmax3.expires = RUN_AT(pDevice->byTMax3 * HZ);
2897 pDevice->TimerSQ3Tmax2.expires = RUN_AT(pDevice->byTMax2 * HZ);
2898 add_timer(&pDevice->TimerSQ3Tmax3);
2899 add_timer(&pDevice->TimerSQ3Tmax2);
2902 spin_unlock_irq(&pDevice->lock);
2910 * Timer for SQ3 antenna diversity
2915 * hDeviceContext - Pointer to the adapter
2921 * Return Value: none
2926 TimerState1CallBack (
2927 void *hDeviceContext
2930 PSDevice pDevice = (PSDevice)hDeviceContext;
2932 DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO"TimerState1CallBack...");
2934 spin_lock_irq(&pDevice->lock);
2935 if (pDevice->uDiversityCnt < pDevice->ulDiversityMValue/100) {
2937 //printk("TimerSQ3CallBack2:call s_vChangeAntenna\n");
2940 s_vChangeAntenna(pDevice);
2941 pDevice->TimerSQ3Tmax3.expires = RUN_AT(pDevice->byTMax3 * HZ);
2942 pDevice->TimerSQ3Tmax2.expires = RUN_AT(pDevice->byTMax2 * HZ);
2943 add_timer(&pDevice->TimerSQ3Tmax3);
2944 add_timer(&pDevice->TimerSQ3Tmax2);
2946 pDevice->ulRatio_State1 = s_ulGetRatio(pDevice);
2947 DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO"SQ3_State1, rate0 = %08x,rate1 = %08x\n",
2948 (int)pDevice->ulRatio_State0,(int)pDevice->ulRatio_State1);
2950 if ( pDevice->ulRatio_State1 < pDevice->ulRatio_State0 ) {
2951 DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO"2.[%08x][%08x], uNumSQ3[%d]=%d, %d\n",
2952 (int)pDevice->ulRatio_State0, (int)pDevice->ulRatio_State1,
2953 (int)pDevice->wAntDiversityMaxRate,
2954 (int)pDevice->uNumSQ3[(int)pDevice->wAntDiversityMaxRate], (int)pDevice->uDiversityCnt);
2956 //printk("TimerSQ3CallBack3:call s_vChangeAntenna\n");
2959 s_vChangeAntenna(pDevice);
2961 pDevice->TimerSQ3Tmax3.expires = RUN_AT(pDevice->byTMax3 * HZ);
2962 pDevice->TimerSQ3Tmax2.expires = RUN_AT(pDevice->byTMax2 * HZ);
2963 add_timer(&pDevice->TimerSQ3Tmax3);
2964 add_timer(&pDevice->TimerSQ3Tmax2);
2967 pDevice->byAntennaState = 0;
2968 BBvClearAntDivSQ3Value(pDevice);
2969 spin_unlock_irq(&pDevice->lock);