4 * DSP-BIOS Bridge driver support functions for TI OMAP processors.
6 * IO dispatcher for a shared memory channel driver.
8 * Copyright (C) 2005-2006 Texas Instruments, Inc.
10 * This package is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
14 * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
16 * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
21 * There is an important invariant condition which must be maintained per
22 * channel outside of bridge_chnl_get_ioc() and IO_Dispatch(), violation of
23 * which may cause timeouts and/or failure of the sync_wait_on_event
26 #include <linux/types.h>
27 #include <linux/list.h>
30 #include <dspbridge/host_os.h>
31 #include <linux/workqueue.h>
33 /* ----------------------------------- DSP/BIOS Bridge */
34 #include <dspbridge/dbdefs.h>
37 #include <dspbridge/ntfy.h>
38 #include <dspbridge/sync.h>
40 /* Hardware Abstraction Layer */
45 #include <dspbridge/dspdeh.h>
46 #include <dspbridge/dspio.h>
47 #include <dspbridge/dspioctl.h>
48 #include <dspbridge/wdt.h>
50 #include <tiomap_io.h>
51 #include <_tiomap_pwr.h>
53 /* Platform Manager */
54 #include <dspbridge/cod.h>
55 #include <dspbridge/node.h>
56 #include <dspbridge/dev.h>
59 #include <dspbridge/rms_sh.h>
60 #include <dspbridge/mgr.h>
61 #include <dspbridge/drv.h>
63 #include "module_list.h"
66 #include <dspbridge/io_sm.h>
69 /* Defines, Data Structures, Typedefs */
70 #define OUTPUTNOTREADY 0xffff
71 #define NOTENABLED 0xffff /* Channel(s) not enabled */
73 #define EXTEND "_EXT_END"
75 #define SWAP_WORD(x) (x)
76 #define UL_PAGE_ALIGN_SIZE 0x10000 /* Page Align Size */
78 #define MAX_PM_REQS 32
80 #define MMU_FAULT_HEAD1 0xa5a5a5a5
81 #define MMU_FAULT_HEAD2 0x96969696
83 #define MAX_MMU_DBGBUFF 10240
85 /* IO Manager: only one created per board */
87 /* These four fields must be the first fields in a io_mgr_ struct */
88 /* Bridge device context */
89 struct bridge_dev_context *bridge_context;
90 /* Function interface to Bridge driver */
91 struct bridge_drv_interface *intf_fxns;
92 struct dev_object *dev_obj; /* Device this board represents */
94 /* These fields initialized in bridge_io_create() */
95 struct chnl_mgr *chnl_mgr;
96 struct shm *shared_mem; /* Shared Memory control */
97 u8 *input; /* Address of input channel */
98 u8 *output; /* Address of output channel */
99 struct msg_mgr *msg_mgr; /* Message manager */
100 /* Msg control for from DSP messages */
101 struct msg_ctrl *msg_input_ctrl;
102 /* Msg control for to DSP messages */
103 struct msg_ctrl *msg_output_ctrl;
104 u8 *msg_input; /* Address of input messages */
105 u8 *msg_output; /* Address of output messages */
106 u32 sm_buf_size; /* Size of a shared memory I/O channel */
107 bool shared_irq; /* Is this IRQ shared? */
108 u32 word_size; /* Size in bytes of DSP word */
109 u16 intr_val; /* Interrupt value */
110 /* Private extnd proc info; mmu setup */
111 struct mgr_processorextinfo ext_proc_info;
112 struct cmm_object *cmm_mgr; /* Shared Mem Mngr */
113 struct work_struct io_workq; /* workqueue */
114 #if defined(CONFIG_TIDSPBRIDGE_BACKTRACE)
115 u32 trace_buffer_begin; /* Trace message start address */
116 u32 trace_buffer_end; /* Trace message end address */
117 u32 trace_buffer_current; /* Trace message current address */
118 u32 gpp_read_pointer; /* GPP Read pointer to Trace buffer */
124 u32 dpc_req; /* Number of requested DPC's. */
125 u32 dpc_sched; /* Number of executed DPC's. */
126 struct tasklet_struct dpc_tasklet;
131 /* Function Prototypes */
132 static void io_dispatch_pm(struct io_mgr *pio_mgr);
133 static void notify_chnl_complete(struct chnl_object *pchnl,
134 struct chnl_irp *chnl_packet_obj);
135 static void input_chnl(struct io_mgr *pio_mgr, struct chnl_object *pchnl,
137 static void output_chnl(struct io_mgr *pio_mgr, struct chnl_object *pchnl,
139 static void input_msg(struct io_mgr *pio_mgr, struct msg_mgr *hmsg_mgr);
140 static void output_msg(struct io_mgr *pio_mgr, struct msg_mgr *hmsg_mgr);
141 static u32 find_ready_output(struct chnl_mgr *chnl_mgr_obj,
142 struct chnl_object *pchnl, u32 mask);
144 /* Bus Addr (cached kernel) */
145 static int register_shm_segs(struct io_mgr *hio_mgr,
146 struct cod_manager *cod_man,
149 static inline void set_chnl_free(struct shm *sm, u32 chnl)
151 sm->host_free_mask &= ~(1 << chnl);
154 static inline void set_chnl_busy(struct shm *sm, u32 chnl)
156 sm->host_free_mask |= 1 << chnl;
161 * ======== bridge_io_create ========
162 * Create an IO manager object.
164 int bridge_io_create(struct io_mgr **io_man,
165 struct dev_object *hdev_obj,
166 const struct io_attrs *mgr_attrts)
168 struct io_mgr *pio_mgr = NULL;
169 struct bridge_dev_context *hbridge_context = NULL;
170 struct cfg_devnode *dev_node_obj;
171 struct chnl_mgr *hchnl_mgr;
174 /* Check requirements */
175 if (!io_man || !mgr_attrts || mgr_attrts->word_size == 0)
180 dev_get_chnl_mgr(hdev_obj, &hchnl_mgr);
181 if (!hchnl_mgr || hchnl_mgr->iomgr)
185 * Message manager will be created when a file is loaded, since
186 * size of message buffer in shared memory is configurable in
189 dev_get_bridge_context(hdev_obj, &hbridge_context);
190 if (!hbridge_context)
193 dev_get_dev_type(hdev_obj, &dev_type);
195 /* Allocate IO manager object */
196 pio_mgr = kzalloc(sizeof(struct io_mgr), GFP_KERNEL);
200 /* Initialize chnl_mgr object */
201 pio_mgr->chnl_mgr = hchnl_mgr;
202 pio_mgr->word_size = mgr_attrts->word_size;
204 if (dev_type == DSP_UNIT) {
205 /* Create an IO DPC */
206 tasklet_init(&pio_mgr->dpc_tasklet, io_dpc, (u32) pio_mgr);
208 /* Initialize DPC counters */
209 pio_mgr->dpc_req = 0;
210 pio_mgr->dpc_sched = 0;
212 spin_lock_init(&pio_mgr->dpc_lock);
214 if (dev_get_dev_node(hdev_obj, &dev_node_obj)) {
215 bridge_io_destroy(pio_mgr);
220 pio_mgr->bridge_context = hbridge_context;
221 pio_mgr->shared_irq = mgr_attrts->irq_shared;
222 if (dsp_wdt_init()) {
223 bridge_io_destroy(pio_mgr);
227 /* Return IO manager object to caller... */
228 hchnl_mgr->iomgr = pio_mgr;
235 * ======== bridge_io_destroy ========
237 * Disable interrupts, destroy the IO manager.
239 int bridge_io_destroy(struct io_mgr *hio_mgr)
243 /* Free IO DPC object */
244 tasklet_kill(&hio_mgr->dpc_tasklet);
246 #if defined(CONFIG_TIDSPBRIDGE_BACKTRACE)
250 /* Free this IO manager object */
260 * ======== bridge_io_on_loaded ========
262 * Called when a new program is loaded to get shared memory buffer
263 * parameters from COFF file. ulSharedBufferBase and ulSharedBufferLimit
264 * are in DSP address units.
266 int bridge_io_on_loaded(struct io_mgr *hio_mgr)
268 struct cod_manager *cod_man;
269 struct chnl_mgr *hchnl_mgr;
270 struct msg_mgr *hmsg_mgr;
272 u32 ul_shm_base_offset;
274 u32 ul_shm_length = -1;
275 u32 ul_mem_length = -1;
278 u32 ul_msg_length = -1;
289 /* DSP MMU setup table */
290 struct bridge_ioctl_extproc ae_proc[BRDIOCTL_NUMOFMMUTLB];
291 struct cfg_hostres *host_res;
292 struct bridge_dev_context *pbridge_context;
296 u32 ul_seg1_size = 0;
302 u32 page_size[] = { HW_PAGE_SIZE16MB, HW_PAGE_SIZE1MB,
303 HW_PAGE_SIZE64KB, HW_PAGE_SIZE4KB
306 status = dev_get_bridge_context(hio_mgr->dev_obj, &pbridge_context);
307 if (!pbridge_context) {
312 host_res = pbridge_context->resources;
317 status = dev_get_cod_mgr(hio_mgr->dev_obj, &cod_man);
322 hchnl_mgr = hio_mgr->chnl_mgr;
323 /* The message manager is destroyed when the board is stopped. */
324 dev_get_msg_mgr(hio_mgr->dev_obj, &hio_mgr->msg_mgr);
325 hmsg_mgr = hio_mgr->msg_mgr;
326 if (!hchnl_mgr || !hmsg_mgr) {
330 if (hio_mgr->shared_mem)
331 hio_mgr->shared_mem = NULL;
333 /* Get start and length of channel part of shared memory */
334 status = cod_get_sym_value(cod_man, CHNL_SHARED_BUFFER_BASE_SYM,
340 status = cod_get_sym_value(cod_man, CHNL_SHARED_BUFFER_LIMIT_SYM,
346 if (ul_shm_limit <= ul_shm_base) {
350 /* Get total length in bytes */
351 ul_shm_length = (ul_shm_limit - ul_shm_base + 1) * hio_mgr->word_size;
352 /* Calculate size of a PROCCOPY shared memory region */
353 dev_dbg(bridge, "%s: (proc)proccopy shmmem size: 0x%x bytes\n",
354 __func__, (ul_shm_length - sizeof(struct shm)));
356 /* Get start and length of message part of shared memory */
357 status = cod_get_sym_value(cod_man, MSG_SHARED_BUFFER_BASE_SYM,
360 status = cod_get_sym_value(cod_man, MSG_SHARED_BUFFER_LIMIT_SYM,
363 if (ul_msg_limit <= ul_msg_base) {
367 * Length (bytes) of messaging part of shared
371 (ul_msg_limit - ul_msg_base +
372 1) * hio_mgr->word_size;
374 * Total length (bytes) of shared memory:
377 ul_mem_length = ul_shm_length + ul_msg_length;
386 #if defined(CONFIG_TIDSPBRIDGE_BACKTRACE)
388 cod_get_sym_value(cod_man, DSP_TRACESEC_END, &shm0_end);
390 status = cod_get_sym_value(cod_man, SHM0_SHARED_END_SYM,
398 cod_get_sym_value(cod_man, DYNEXTBASE, &ul_dyn_ext_base);
403 status = cod_get_sym_value(cod_man, EXTEND, &ul_ext_end);
408 /* Get memory reserved in host resources */
409 (void)mgr_enum_processor_info(0, (struct dsp_processorinfo *)
410 &hio_mgr->ext_proc_info,
412 mgr_processorextinfo),
415 /* The first MMU TLB entry(TLB_0) in DCD is ShmBase. */
417 ul_gpp_pa = host_res->mem_phys[1];
418 ul_gpp_va = host_res->mem_base[1];
419 /* This is the virtual uncached ioremapped address!!! */
420 /* Why can't we directly take the DSPVA from the symbols? */
421 ul_dsp_va = hio_mgr->ext_proc_info.ty_tlb[0].dsp_virt;
422 ul_seg_size = (shm0_end - ul_dsp_va) * hio_mgr->word_size;
424 (ul_ext_end - ul_dyn_ext_base) * hio_mgr->word_size;
426 ul_seg1_size = (ul_seg1_size + 0xFFF) & (~0xFFFUL);
428 ul_seg_size = (ul_seg_size + 0xFFFF) & (~0xFFFFUL);
429 ul_pad_size = UL_PAGE_ALIGN_SIZE - ((ul_gpp_pa + ul_seg1_size) %
431 if (ul_pad_size == UL_PAGE_ALIGN_SIZE)
434 dev_dbg(bridge, "%s: ul_gpp_pa %x, ul_gpp_va %x, ul_dsp_va %x, "
435 "shm0_end %x, ul_dyn_ext_base %x, ul_ext_end %x, "
436 "ul_seg_size %x ul_seg1_size %x \n", __func__,
437 ul_gpp_pa, ul_gpp_va, ul_dsp_va, shm0_end,
438 ul_dyn_ext_base, ul_ext_end, ul_seg_size, ul_seg1_size);
440 if ((ul_seg_size + ul_seg1_size + ul_pad_size) >
441 host_res->mem_length[1]) {
442 pr_err("%s: shm Error, reserved 0x%x required 0x%x\n",
443 __func__, host_res->mem_length[1],
444 ul_seg_size + ul_seg1_size + ul_pad_size);
452 va_curr = ul_dyn_ext_base * hio_mgr->word_size;
453 gpp_va_curr = ul_gpp_va;
454 num_bytes = ul_seg1_size;
457 * Try to fit into TLB entries. If not possible, push them to page
458 * tables. It is quite possible that if sections are not on
459 * bigger page boundary, we may end up making several small pages.
460 * So, push them onto page tables, if that is the case.
462 map_attrs = 0x00000000;
463 map_attrs = DSP_MAPLITTLEENDIAN;
464 map_attrs |= DSP_MAPPHYSICALADDR;
465 map_attrs |= DSP_MAPELEMSIZE32;
466 map_attrs |= DSP_MAPDONOTLOCK;
470 * To find the max. page size with which both PA & VA are
473 all_bits = pa_curr | va_curr;
474 dev_dbg(bridge, "all_bits %x, pa_curr %x, va_curr %x, "
475 "num_bytes %x\n", all_bits, pa_curr, va_curr,
477 for (i = 0; i < 4; i++) {
478 if ((num_bytes >= page_size[i]) && ((all_bits &
483 brd_mem_map(hio_mgr->bridge_context,
485 page_size[i], map_attrs,
489 pa_curr += page_size[i];
490 va_curr += page_size[i];
491 gpp_va_curr += page_size[i];
492 num_bytes -= page_size[i];
494 * Don't try smaller sizes. Hopefully we have
495 * reached an address aligned to a bigger page
502 pa_curr += ul_pad_size;
503 va_curr += ul_pad_size;
504 gpp_va_curr += ul_pad_size;
506 /* Configure the TLB entries for the next cacheable segment */
507 num_bytes = ul_seg_size;
508 va_curr = ul_dsp_va * hio_mgr->word_size;
511 * To find the max. page size with which both PA & VA are
514 all_bits = pa_curr | va_curr;
515 dev_dbg(bridge, "all_bits for Seg1 %x, pa_curr %x, "
516 "va_curr %x, num_bytes %x\n", all_bits, pa_curr,
518 for (i = 0; i < 4; i++) {
519 if (!(num_bytes >= page_size[i]) ||
520 !((all_bits & (page_size[i] - 1)) == 0))
522 if (ndx < MAX_LOCK_TLB_ENTRIES) {
524 * This is the physical address written to
527 ae_proc[ndx].gpp_pa = pa_curr;
529 * This is the virtual uncached ioremapped
532 ae_proc[ndx].gpp_va = gpp_va_curr;
533 ae_proc[ndx].dsp_va =
534 va_curr / hio_mgr->word_size;
535 ae_proc[ndx].size = page_size[i];
536 ae_proc[ndx].endianism = HW_LITTLE_ENDIAN;
537 ae_proc[ndx].elem_size = HW_ELEM_SIZE16BIT;
538 ae_proc[ndx].mixed_mode = HW_MMU_CPUES;
539 dev_dbg(bridge, "shm MMU TLB entry PA %x"
540 " VA %x DSP_VA %x Size %x\n",
543 ae_proc[ndx].dsp_va *
544 hio_mgr->word_size, page_size[i]);
549 brd_mem_map(hio_mgr->bridge_context,
551 page_size[i], map_attrs,
554 "shm MMU PTE entry PA %x"
555 " VA %x DSP_VA %x Size %x\n",
558 ae_proc[ndx].dsp_va *
559 hio_mgr->word_size, page_size[i]);
563 pa_curr += page_size[i];
564 va_curr += page_size[i];
565 gpp_va_curr += page_size[i];
566 num_bytes -= page_size[i];
568 * Don't try smaller sizes. Hopefully we have reached
569 * an address aligned to a bigger page size.
576 * Copy remaining entries from CDB. All entries are 1 MB and
577 * should not conflict with shm entries on MPU or DSP side.
579 for (i = 3; i < 7 && ndx < BRDIOCTL_NUMOFMMUTLB; i++) {
580 if (hio_mgr->ext_proc_info.ty_tlb[i].gpp_phys == 0)
583 if ((hio_mgr->ext_proc_info.ty_tlb[i].gpp_phys >
585 && hio_mgr->ext_proc_info.ty_tlb[i].gpp_phys <=
586 ul_gpp_pa + ul_seg_size)
587 || (hio_mgr->ext_proc_info.ty_tlb[i].dsp_virt >
588 ul_dsp_va - 0x100000 / hio_mgr->word_size
589 && hio_mgr->ext_proc_info.ty_tlb[i].dsp_virt <=
590 ul_dsp_va + ul_seg_size / hio_mgr->word_size)) {
592 "CDB MMU entry %d conflicts with "
593 "shm.\n\tCDB: GppPa %x, DspVa %x.\n\tSHM: "
594 "GppPa %x, DspVa %x, Bytes %x.\n", i,
595 hio_mgr->ext_proc_info.ty_tlb[i].gpp_phys,
596 hio_mgr->ext_proc_info.ty_tlb[i].dsp_virt,
597 ul_gpp_pa, ul_dsp_va, ul_seg_size);
600 if (ndx < MAX_LOCK_TLB_ENTRIES) {
601 ae_proc[ndx].dsp_va =
602 hio_mgr->ext_proc_info.ty_tlb[i].
604 ae_proc[ndx].gpp_pa =
605 hio_mgr->ext_proc_info.ty_tlb[i].
607 ae_proc[ndx].gpp_va = 0;
609 ae_proc[ndx].size = 0x100000;
610 dev_dbg(bridge, "shm MMU entry PA %x "
611 "DSP_VA 0x%x\n", ae_proc[ndx].gpp_pa,
612 ae_proc[ndx].dsp_va);
615 status = hio_mgr->intf_fxns->brd_mem_map
616 (hio_mgr->bridge_context,
617 hio_mgr->ext_proc_info.ty_tlb[i].
619 hio_mgr->ext_proc_info.ty_tlb[i].
620 dsp_virt, 0x100000, map_attrs,
628 map_attrs = 0x00000000;
629 map_attrs = DSP_MAPLITTLEENDIAN;
630 map_attrs |= DSP_MAPPHYSICALADDR;
631 map_attrs |= DSP_MAPELEMSIZE32;
632 map_attrs |= DSP_MAPDONOTLOCK;
634 /* Map the L4 peripherals */
636 while (l4_peripheral_table[i].phys_addr) {
637 status = hio_mgr->intf_fxns->brd_mem_map
638 (hio_mgr->bridge_context, l4_peripheral_table[i].phys_addr,
639 l4_peripheral_table[i].dsp_virt_addr, HW_PAGE_SIZE4KB,
646 for (i = ndx; i < BRDIOCTL_NUMOFMMUTLB; i++) {
647 ae_proc[i].dsp_va = 0;
648 ae_proc[i].gpp_pa = 0;
649 ae_proc[i].gpp_va = 0;
653 * Set the shm physical address entry (grayed out in CDB file)
654 * to the virtual uncached ioremapped address of shm reserved
657 hio_mgr->ext_proc_info.ty_tlb[0].gpp_phys =
658 (ul_gpp_va + ul_seg1_size + ul_pad_size);
661 * Need shm Phys addr. IO supports only one DSP for now:
664 if (!hio_mgr->ext_proc_info.ty_tlb[0].gpp_phys || num_procs != 1) {
668 if (ae_proc[0].dsp_va > ul_shm_base) {
672 /* ul_shm_base may not be at ul_dsp_va address */
673 ul_shm_base_offset = (ul_shm_base - ae_proc[0].dsp_va) *
676 * bridge_dev_ctrl() will set dev context dsp-mmu info. In
677 * bridge_brd_start() the MMU will be re-programed with MMU
678 * DSPVa-GPPPa pair info while DSP is in a known
683 hio_mgr->intf_fxns->dev_cntrl(hio_mgr->bridge_context,
684 BRDIOCTL_SETMMUCONFIG,
688 ul_shm_base = hio_mgr->ext_proc_info.ty_tlb[0].gpp_phys;
689 ul_shm_base += ul_shm_base_offset;
690 ul_shm_base = (u32) MEM_LINEAR_ADDRESS((void *)ul_shm_base,
692 if (ul_shm_base == 0) {
698 register_shm_segs(hio_mgr, cod_man, ae_proc[0].gpp_pa);
701 hio_mgr->shared_mem = (struct shm *)ul_shm_base;
702 hio_mgr->input = (u8 *) hio_mgr->shared_mem + sizeof(struct shm);
703 hio_mgr->output = hio_mgr->input + (ul_shm_length -
704 sizeof(struct shm)) / 2;
705 hio_mgr->sm_buf_size = hio_mgr->output - hio_mgr->input;
707 /* Set up Shared memory addresses for messaging. */
708 hio_mgr->msg_input_ctrl = (struct msg_ctrl *)((u8 *) hio_mgr->shared_mem
711 (u8 *) hio_mgr->msg_input_ctrl + sizeof(struct msg_ctrl);
712 hio_mgr->msg_output_ctrl =
713 (struct msg_ctrl *)((u8 *) hio_mgr->msg_input_ctrl +
715 hio_mgr->msg_output =
716 (u8 *) hio_mgr->msg_output_ctrl + sizeof(struct msg_ctrl);
718 ((u8 *) hio_mgr->msg_output_ctrl - hio_mgr->msg_input)
719 / sizeof(struct msg_dspmsg);
720 dev_dbg(bridge, "IO MGR shm details: shared_mem %p, input %p, "
721 "output %p, msg_input_ctrl %p, msg_input %p, "
722 "msg_output_ctrl %p, msg_output %p\n",
723 (u8 *) hio_mgr->shared_mem, hio_mgr->input,
724 hio_mgr->output, (u8 *) hio_mgr->msg_input_ctrl,
725 hio_mgr->msg_input, (u8 *) hio_mgr->msg_output_ctrl,
726 hio_mgr->msg_output);
727 dev_dbg(bridge, "(proc) Mas msgs in shared memory: 0x%x\n",
729 memset((void *)hio_mgr->shared_mem, 0, sizeof(struct shm));
731 #if defined(CONFIG_TIDSPBRIDGE_BACKTRACE)
732 /* Get the start address of trace buffer */
733 status = cod_get_sym_value(cod_man, SYS_PUTCBEG,
734 &hio_mgr->trace_buffer_begin);
740 hio_mgr->gpp_read_pointer = hio_mgr->trace_buffer_begin =
741 (ul_gpp_va + ul_seg1_size + ul_pad_size) +
742 (hio_mgr->trace_buffer_begin - ul_dsp_va);
743 /* Get the end address of trace buffer */
744 status = cod_get_sym_value(cod_man, SYS_PUTCEND,
745 &hio_mgr->trace_buffer_end);
750 hio_mgr->trace_buffer_end =
751 (ul_gpp_va + ul_seg1_size + ul_pad_size) +
752 (hio_mgr->trace_buffer_end - ul_dsp_va);
753 /* Get the current address of DSP write pointer */
754 status = cod_get_sym_value(cod_man, BRIDGE_SYS_PUTC_CURRENT,
755 &hio_mgr->trace_buffer_current);
760 hio_mgr->trace_buffer_current =
761 (ul_gpp_va + ul_seg1_size + ul_pad_size) +
762 (hio_mgr->trace_buffer_current - ul_dsp_va);
763 /* Calculate the size of trace buffer */
765 hio_mgr->msg = kmalloc(((hio_mgr->trace_buffer_end -
766 hio_mgr->trace_buffer_begin) *
767 hio_mgr->word_size) + 2, GFP_KERNEL);
771 hio_mgr->dsp_va = ul_dsp_va;
772 hio_mgr->gpp_va = (ul_gpp_va + ul_seg1_size + ul_pad_size);
780 * ======== io_buf_size ========
781 * Size of shared memory I/O channel.
783 u32 io_buf_size(struct io_mgr *hio_mgr)
786 return hio_mgr->sm_buf_size;
792 * ======== io_cancel_chnl ========
793 * Cancel IO on a given PCPY channel.
795 void io_cancel_chnl(struct io_mgr *hio_mgr, u32 chnl)
797 struct io_mgr *pio_mgr = (struct io_mgr *)hio_mgr;
802 sm = hio_mgr->shared_mem;
804 /* Inform DSP that we have no more buffers on this channel */
805 set_chnl_free(sm, chnl);
807 sm_interrupt_dsp(pio_mgr->bridge_context, MBX_PCPY_CLASS);
814 * ======== io_dispatch_pm ========
815 * Performs I/O dispatch on PM related messages from DSP
817 static void io_dispatch_pm(struct io_mgr *pio_mgr)
822 /* Perform Power message processing here */
823 parg[0] = pio_mgr->intr_val;
825 /* Send the command to the Bridge clk/pwr manager to handle */
826 if (parg[0] == MBX_PM_HIBERNATE_EN) {
827 dev_dbg(bridge, "PM: Hibernate command\n");
828 status = pio_mgr->intf_fxns->
829 dev_cntrl(pio_mgr->bridge_context,
830 BRDIOCTL_PWR_HIBERNATE, parg);
832 pr_err("%s: hibernate cmd failed 0x%x\n",
834 } else if (parg[0] == MBX_PM_OPP_REQ) {
835 parg[1] = pio_mgr->shared_mem->opp_request.rqst_opp_pt;
836 dev_dbg(bridge, "PM: Requested OPP = 0x%x\n", parg[1]);
837 status = pio_mgr->intf_fxns->
838 dev_cntrl(pio_mgr->bridge_context,
839 BRDIOCTL_CONSTRAINT_REQUEST, parg);
841 dev_dbg(bridge, "PM: Failed to set constraint "
842 "= 0x%x\n", parg[1]);
844 dev_dbg(bridge, "PM: clk control value of msg = 0x%x\n",
846 status = pio_mgr->intf_fxns->
847 dev_cntrl(pio_mgr->bridge_context,
848 BRDIOCTL_CLK_CTRL, parg);
850 dev_dbg(bridge, "PM: Failed to ctrl the DSP clk"
856 * ======== io_dpc ========
857 * Deferred procedure call for shared memory channel driver ISR. Carries
858 * out the dispatch of I/O as a non-preemptible event.It can only be
859 * pre-empted by an ISR.
861 void io_dpc(unsigned long ref_data)
863 struct io_mgr *pio_mgr = (struct io_mgr *)ref_data;
864 struct chnl_mgr *chnl_mgr_obj;
865 struct msg_mgr *msg_mgr_obj;
866 struct deh_mgr *hdeh_mgr;
872 chnl_mgr_obj = pio_mgr->chnl_mgr;
873 dev_get_msg_mgr(pio_mgr->dev_obj, &msg_mgr_obj);
874 dev_get_deh_mgr(pio_mgr->dev_obj, &hdeh_mgr);
878 requested = pio_mgr->dpc_req;
879 serviced = pio_mgr->dpc_sched;
881 if (serviced == requested)
884 /* Process pending DPC's */
886 /* Check value of interrupt reg to ensure it's a valid error */
887 if ((pio_mgr->intr_val > DEH_BASE) &&
888 (pio_mgr->intr_val < DEH_LIMIT)) {
889 /* Notify DSP/BIOS exception */
891 #ifdef CONFIG_TIDSPBRIDGE_BACKTRACE
892 print_dsp_debug_trace(pio_mgr);
894 bridge_deh_notify(hdeh_mgr, DSP_SYSERROR,
898 /* Proc-copy chanel dispatch */
899 input_chnl(pio_mgr, NULL, IO_SERVICE);
900 output_chnl(pio_mgr, NULL, IO_SERVICE);
904 /* Perform I/O dispatch on message queues */
905 input_msg(pio_mgr, msg_mgr_obj);
906 output_msg(pio_mgr, msg_mgr_obj);
910 #ifdef CONFIG_TIDSPBRIDGE_BACKTRACE
911 if (pio_mgr->intr_val & MBX_DBG_SYSPRINTF) {
912 /* Notify DSP Trace message */
913 print_dsp_debug_trace(pio_mgr);
917 } while (serviced != requested);
918 pio_mgr->dpc_sched = requested;
924 * ======== io_mbox_msg ========
925 * Main interrupt handler for the shared memory IO manager.
926 * Calls the Bridge's CHNL_ISR to determine if this interrupt is ours, then
927 * schedules a DPC to dispatch I/O.
929 int io_mbox_msg(struct notifier_block *self, unsigned long len, void *msg)
931 struct io_mgr *pio_mgr;
932 struct dev_object *dev_obj;
935 dev_obj = dev_get_first();
936 dev_get_io_mgr(dev_obj, &pio_mgr);
941 pio_mgr->intr_val = (u16)((u32)msg);
942 if (pio_mgr->intr_val & MBX_PM_CLASS)
943 io_dispatch_pm(pio_mgr);
945 if (pio_mgr->intr_val == MBX_DEH_RESET) {
946 pio_mgr->intr_val = 0;
948 spin_lock_irqsave(&pio_mgr->dpc_lock, flags);
950 spin_unlock_irqrestore(&pio_mgr->dpc_lock, flags);
951 tasklet_schedule(&pio_mgr->dpc_tasklet);
957 * ======== io_request_chnl ========
959 * Request chanenel I/O from the DSP. Sets flags in shared memory, then
960 * interrupts the DSP.
962 void io_request_chnl(struct io_mgr *io_manager, struct chnl_object *pchnl,
963 u8 io_mode, u16 *mbx_val)
965 struct chnl_mgr *chnl_mgr_obj;
968 if (!pchnl || !mbx_val)
970 chnl_mgr_obj = io_manager->chnl_mgr;
971 sm = io_manager->shared_mem;
972 if (io_mode == IO_INPUT) {
973 /* Indicate to the DSP we have a buffer available for input */
974 set_chnl_busy(sm, pchnl->chnl_id);
975 *mbx_val = MBX_PCPY_CLASS;
976 } else if (io_mode == IO_OUTPUT) {
978 * Record the fact that we have a buffer available for
981 chnl_mgr_obj->output_mask |= (1 << pchnl->chnl_id);
989 * ======== iosm_schedule ========
990 * Schedule DPC for IO.
992 void iosm_schedule(struct io_mgr *io_manager)
999 /* Increment count of DPC's pending. */
1000 spin_lock_irqsave(&io_manager->dpc_lock, flags);
1001 io_manager->dpc_req++;
1002 spin_unlock_irqrestore(&io_manager->dpc_lock, flags);
1005 tasklet_schedule(&io_manager->dpc_tasklet);
1009 * ======== find_ready_output ========
1010 * Search for a host output channel which is ready to send. If this is
1011 * called as a result of servicing the DPC, then implement a round
1012 * robin search; otherwise, this was called by a client thread (via
1013 * IO_Dispatch()), so just start searching from the current channel id.
1015 static u32 find_ready_output(struct chnl_mgr *chnl_mgr_obj,
1016 struct chnl_object *pchnl, u32 mask)
1018 u32 ret = OUTPUTNOTREADY;
1023 NULL ? pchnl->chnl_id : (chnl_mgr_obj->last_output + 1));
1024 id = ((id == CHNL_MAXCHANNELS) ? 0 : id);
1025 if (id >= CHNL_MAXCHANNELS)
1034 chnl_mgr_obj->last_output = id;
1038 id = ((id == CHNL_MAXCHANNELS) ? 0 : id);
1040 } while (id != start_id);
1047 * ======== input_chnl ========
1048 * Dispatch a buffer on an input channel.
1050 static void input_chnl(struct io_mgr *pio_mgr, struct chnl_object *pchnl,
1053 struct chnl_mgr *chnl_mgr_obj;
1057 struct chnl_irp *chnl_packet_obj = NULL;
1059 bool clear_chnl = false;
1060 bool notify_client = false;
1062 sm = pio_mgr->shared_mem;
1063 chnl_mgr_obj = pio_mgr->chnl_mgr;
1065 /* Attempt to perform input */
1066 if (!sm->input_full)
1069 bytes = sm->input_size * chnl_mgr_obj->word_size;
1070 chnl_id = sm->input_id;
1072 if (chnl_id >= CHNL_MAXCHANNELS) {
1073 /* Shouldn't be here: would indicate corrupted shm. */
1076 pchnl = chnl_mgr_obj->channels[chnl_id];
1077 if ((pchnl != NULL) && CHNL_IS_INPUT(pchnl->chnl_mode)) {
1078 if ((pchnl->state & ~CHNL_STATEEOS) == CHNL_STATEREADY) {
1079 /* Get the I/O request, and attempt a transfer */
1080 if (!list_empty(&pchnl->io_requests)) {
1081 if (!pchnl->cio_reqs)
1084 chnl_packet_obj = list_first_entry(
1085 &pchnl->io_requests,
1086 struct chnl_irp, link);
1087 list_del(&chnl_packet_obj->link);
1091 * Ensure we don't overflow the client's
1094 bytes = min(bytes, chnl_packet_obj->byte_size);
1095 memcpy(chnl_packet_obj->host_sys_buf,
1096 pio_mgr->input, bytes);
1097 pchnl->bytes_moved += bytes;
1098 chnl_packet_obj->byte_size = bytes;
1099 chnl_packet_obj->arg = dw_arg;
1100 chnl_packet_obj->status = CHNL_IOCSTATCOMPLETE;
1104 * This assertion fails if the DSP
1105 * sends EOS more than once on this
1108 if (pchnl->state & CHNL_STATEEOS)
1111 * Zero bytes indicates EOS. Update
1112 * IOC status for this chirp, and also
1113 * the channel state.
1115 chnl_packet_obj->status |=
1117 pchnl->state |= CHNL_STATEEOS;
1119 * Notify that end of stream has
1122 ntfy_notify(pchnl->ntfy_obj,
1125 /* Tell DSP if no more I/O buffers available */
1126 if (list_empty(&pchnl->io_requests))
1127 set_chnl_free(sm, pchnl->chnl_id);
1129 notify_client = true;
1132 * Input full for this channel, but we have no
1133 * buffers available. The channel must be
1134 * "idling". Clear out the physical input
1140 /* Input channel cancelled: clear input channel */
1144 /* DPC fired after host closed channel: clear input channel */
1148 /* Indicate to the DSP we have read the input */
1150 sm_interrupt_dsp(pio_mgr->bridge_context, MBX_PCPY_CLASS);
1152 if (notify_client) {
1153 /* Notify client with IO completion record */
1154 notify_chnl_complete(pchnl, chnl_packet_obj);
1161 * ======== input_msg ========
1162 * Copies messages from shared memory to the message queues.
1164 static void input_msg(struct io_mgr *pio_mgr, struct msg_mgr *hmsg_mgr)
1169 struct msg_queue *msg_queue_obj;
1170 struct msg_frame *pmsg;
1171 struct msg_dspmsg msg;
1172 struct msg_ctrl *msg_ctr_obj;
1176 msg_ctr_obj = pio_mgr->msg_input_ctrl;
1177 /* Get the number of input messages to be read */
1178 input_empty = msg_ctr_obj->buf_empty;
1179 num_msgs = msg_ctr_obj->size;
1183 msg_input = pio_mgr->msg_input;
1184 for (i = 0; i < num_msgs; i++) {
1185 /* Read the next message */
1186 addr = (u32) &(((struct msg_dspmsg *)msg_input)->msg.cmd);
1188 read_ext32_bit_dsp_data(pio_mgr->bridge_context, addr);
1189 addr = (u32) &(((struct msg_dspmsg *)msg_input)->msg.arg1);
1191 read_ext32_bit_dsp_data(pio_mgr->bridge_context, addr);
1192 addr = (u32) &(((struct msg_dspmsg *)msg_input)->msg.arg2);
1194 read_ext32_bit_dsp_data(pio_mgr->bridge_context, addr);
1195 addr = (u32) &(((struct msg_dspmsg *)msg_input)->msgq_id);
1197 read_ext32_bit_dsp_data(pio_mgr->bridge_context, addr);
1198 msg_input += sizeof(struct msg_dspmsg);
1200 /* Determine which queue to put the message in */
1201 dev_dbg(bridge, "input msg: cmd=0x%x arg1=0x%x "
1202 "arg2=0x%x msgq_id=0x%x\n", msg.msg.cmd,
1203 msg.msg.arg1, msg.msg.arg2, msg.msgq_id);
1205 * Interrupt may occur before shared memory and message
1206 * input locations have been set up. If all nodes were
1207 * cleaned up, hmsg_mgr->max_msgs should be 0.
1209 list_for_each_entry(msg_queue_obj, &hmsg_mgr->queue_list,
1211 if (msg.msgq_id != msg_queue_obj->msgq_id)
1214 if (msg.msg.cmd == RMS_EXITACK) {
1216 * Call the node exit notification.
1217 * The exit message does not get
1220 (*hmsg_mgr->on_exit)(msg_queue_obj->arg,
1225 * Not an exit acknowledgement, queue
1228 if (list_empty(&msg_queue_obj->msg_free_list)) {
1230 * No free frame to copy the
1233 pr_err("%s: no free msg frames,"
1234 " discarding msg\n",
1239 pmsg = list_first_entry(&msg_queue_obj->msg_free_list,
1240 struct msg_frame, list_elem);
1241 list_del(&pmsg->list_elem);
1242 pmsg->msg_data = msg;
1243 list_add_tail(&pmsg->list_elem,
1244 &msg_queue_obj->msg_used_list);
1245 ntfy_notify(msg_queue_obj->ntfy_obj,
1246 DSP_NODEMESSAGEREADY);
1247 sync_set_event(msg_queue_obj->sync_event);
1250 /* Set the post SWI flag */
1252 /* Tell the DSP we've read the messages */
1253 msg_ctr_obj->buf_empty = true;
1254 msg_ctr_obj->post_swi = true;
1255 sm_interrupt_dsp(pio_mgr->bridge_context, MBX_PCPY_CLASS);
1260 * ======== notify_chnl_complete ========
1262 * Signal the channel event, notifying the client that I/O has completed.
1264 static void notify_chnl_complete(struct chnl_object *pchnl,
1265 struct chnl_irp *chnl_packet_obj)
1269 if (!pchnl || !pchnl->sync_event || !chnl_packet_obj)
1273 * Note: we signal the channel event only if the queue of IO
1274 * completions is empty. If it is not empty, the event is sure to be
1275 * signalled by the only IO completion list consumer:
1276 * bridge_chnl_get_ioc().
1278 signal_event = list_empty(&pchnl->io_completions);
1279 /* Enqueue the IO completion info for the client */
1280 list_add_tail(&chnl_packet_obj->link, &pchnl->io_completions);
1283 if (pchnl->cio_cs > pchnl->chnl_packets)
1285 /* Signal the channel event (if not already set) that IO is complete */
1287 sync_set_event(pchnl->sync_event);
1289 /* Notify that IO is complete */
1290 ntfy_notify(pchnl->ntfy_obj, DSP_STREAMIOCOMPLETION);
1296 * ======== output_chnl ========
1298 * Dispatch a buffer on an output channel.
1300 static void output_chnl(struct io_mgr *pio_mgr, struct chnl_object *pchnl,
1303 struct chnl_mgr *chnl_mgr_obj;
1306 struct chnl_irp *chnl_packet_obj;
1309 chnl_mgr_obj = pio_mgr->chnl_mgr;
1310 sm = pio_mgr->shared_mem;
1311 /* Attempt to perform output */
1312 if (sm->output_full)
1315 if (pchnl && !((pchnl->state & ~CHNL_STATEEOS) == CHNL_STATEREADY))
1318 /* Look to see if both a PC and DSP output channel are ready */
1319 dw_dsp_f_mask = sm->dsp_free_mask;
1321 find_ready_output(chnl_mgr_obj, pchnl,
1322 (chnl_mgr_obj->output_mask & dw_dsp_f_mask));
1323 if (chnl_id == OUTPUTNOTREADY)
1326 pchnl = chnl_mgr_obj->channels[chnl_id];
1327 if (!pchnl || list_empty(&pchnl->io_requests)) {
1328 /* Shouldn't get here */
1332 if (!pchnl->cio_reqs)
1335 /* Get the I/O request, and attempt a transfer */
1336 chnl_packet_obj = list_first_entry(&pchnl->io_requests,
1337 struct chnl_irp, link);
1338 list_del(&chnl_packet_obj->link);
1342 /* Record fact that no more I/O buffers available */
1343 if (list_empty(&pchnl->io_requests))
1344 chnl_mgr_obj->output_mask &= ~(1 << chnl_id);
1346 /* Transfer buffer to DSP side */
1347 chnl_packet_obj->byte_size = min(pio_mgr->sm_buf_size,
1348 chnl_packet_obj->byte_size);
1349 memcpy(pio_mgr->output, chnl_packet_obj->host_sys_buf,
1350 chnl_packet_obj->byte_size);
1351 pchnl->bytes_moved += chnl_packet_obj->byte_size;
1352 /* Write all 32 bits of arg */
1353 sm->arg = chnl_packet_obj->arg;
1354 #if _CHNL_WORDSIZE == 2
1355 /* Access can be different SM access word size (e.g. 16/32 bit words) */
1356 sm->output_id = (u16) chnl_id;
1357 sm->output_size = (u16) (chnl_packet_obj->byte_size +
1358 chnl_mgr_obj->word_size - 1) /
1359 (u16) chnl_mgr_obj->word_size;
1361 sm->output_id = chnl_id;
1362 sm->output_size = (chnl_packet_obj->byte_size +
1363 chnl_mgr_obj->word_size - 1) / chnl_mgr_obj->word_size;
1365 sm->output_full = 1;
1366 /* Indicate to the DSP we have written the output */
1367 sm_interrupt_dsp(pio_mgr->bridge_context, MBX_PCPY_CLASS);
1368 /* Notify client with IO completion record (keep EOS) */
1369 chnl_packet_obj->status &= CHNL_IOCSTATEOS;
1370 notify_chnl_complete(pchnl, chnl_packet_obj);
1371 /* Notify if stream is done. */
1372 if (chnl_packet_obj->status & CHNL_IOCSTATEOS)
1373 ntfy_notify(pchnl->ntfy_obj, DSP_STREAMDONE);
1380 * ======== output_msg ========
1381 * Copies messages from the message queues to the shared memory.
1383 static void output_msg(struct io_mgr *pio_mgr, struct msg_mgr *hmsg_mgr)
1387 struct msg_dspmsg *msg_output;
1388 struct msg_frame *pmsg;
1389 struct msg_ctrl *msg_ctr_obj;
1393 msg_ctr_obj = pio_mgr->msg_output_ctrl;
1395 /* Check if output has been cleared */
1396 if (!msg_ctr_obj->buf_empty)
1399 num_msgs = (hmsg_mgr->msgs_pending > hmsg_mgr->max_msgs) ?
1400 hmsg_mgr->max_msgs : hmsg_mgr->msgs_pending;
1401 msg_output = (struct msg_dspmsg *) pio_mgr->msg_output;
1403 /* Copy num_msgs messages into shared memory */
1404 for (i = 0; i < num_msgs; i++) {
1405 if (list_empty(&hmsg_mgr->msg_used_list))
1408 pmsg = list_first_entry(&hmsg_mgr->msg_used_list,
1409 struct msg_frame, list_elem);
1410 list_del(&pmsg->list_elem);
1412 val = (pmsg->msg_data).msgq_id;
1413 addr = (u32) &msg_output->msgq_id;
1414 write_ext32_bit_dsp_data(pio_mgr->bridge_context, addr, val);
1416 val = (pmsg->msg_data).msg.cmd;
1417 addr = (u32) &msg_output->msg.cmd;
1418 write_ext32_bit_dsp_data(pio_mgr->bridge_context, addr, val);
1420 val = (pmsg->msg_data).msg.arg1;
1421 addr = (u32) &msg_output->msg.arg1;
1422 write_ext32_bit_dsp_data(pio_mgr->bridge_context, addr, val);
1424 val = (pmsg->msg_data).msg.arg2;
1425 addr = (u32) &msg_output->msg.arg2;
1426 write_ext32_bit_dsp_data(pio_mgr->bridge_context, addr, val);
1429 list_add_tail(&pmsg->list_elem, &hmsg_mgr->msg_free_list);
1430 sync_set_event(hmsg_mgr->sync_event);
1434 hmsg_mgr->msgs_pending -= num_msgs;
1435 #if _CHNL_WORDSIZE == 2
1437 * Access can be different SM access word size
1438 * (e.g. 16/32 bit words)
1440 msg_ctr_obj->size = (u16) num_msgs;
1442 msg_ctr_obj->size = num_msgs;
1444 msg_ctr_obj->buf_empty = false;
1445 /* Set the post SWI flag */
1446 msg_ctr_obj->post_swi = true;
1447 /* Tell the DSP we have written the output. */
1448 sm_interrupt_dsp(pio_mgr->bridge_context, MBX_PCPY_CLASS);
1453 * ======== register_shm_segs ========
1455 * Registers GPP SM segment with CMM.
1457 static int register_shm_segs(struct io_mgr *hio_mgr,
1458 struct cod_manager *cod_man,
1462 u32 ul_shm0_base = 0;
1464 u32 ul_shm0_rsrvd_start = 0;
1465 u32 ul_rsrvd_size = 0;
1468 u32 ul_shm_seg_id0 = 0;
1469 u32 dw_offset, dw_gpp_base_va, ul_dsp_size;
1472 * Read address and size info for first SM region.
1473 * Get start of 1st SM Heap region.
1476 cod_get_sym_value(cod_man, SHM0_SHARED_BASE_SYM, &ul_shm0_base);
1477 if (ul_shm0_base == 0) {
1481 /* Get end of 1st SM Heap region */
1483 /* Get start and length of message part of shared memory */
1484 status = cod_get_sym_value(cod_man, SHM0_SHARED_END_SYM,
1486 if (shm0_end == 0) {
1491 /* Start of Gpp reserved region */
1493 /* Get start and length of message part of shared memory */
1495 cod_get_sym_value(cod_man, SHM0_SHARED_RESERVED_BASE_SYM,
1496 &ul_shm0_rsrvd_start);
1497 if (ul_shm0_rsrvd_start == 0) {
1502 /* Register with CMM */
1504 status = dev_get_cmm_mgr(hio_mgr->dev_obj, &hio_mgr->cmm_mgr);
1506 status = cmm_un_register_gppsm_seg(hio_mgr->cmm_mgr,
1510 /* Register new SM region(s) */
1511 if (!status && (shm0_end - ul_shm0_base) > 0) {
1512 /* Calc size (bytes) of SM the GPP can alloc from */
1514 (shm0_end - ul_shm0_rsrvd_start + 1) * hio_mgr->word_size;
1515 if (ul_rsrvd_size <= 0) {
1519 /* Calc size of SM DSP can alloc from */
1521 (ul_shm0_rsrvd_start - ul_shm0_base) * hio_mgr->word_size;
1522 if (ul_dsp_size <= 0) {
1526 /* First TLB entry reserved for Bridge SM use. */
1527 ul_gpp_phys = hio_mgr->ext_proc_info.ty_tlb[0].gpp_phys;
1528 /* Get size in bytes */
1530 hio_mgr->ext_proc_info.ty_tlb[0].dsp_virt *
1533 * Calc byte offset used to convert GPP phys <-> DSP byte
1536 if (dw_gpp_base_pa > ul_dsp_virt)
1537 dw_offset = dw_gpp_base_pa - ul_dsp_virt;
1539 dw_offset = ul_dsp_virt - dw_gpp_base_pa;
1541 if (ul_shm0_rsrvd_start * hio_mgr->word_size < ul_dsp_virt) {
1546 * Calc Gpp phys base of SM region.
1547 * This is actually uncached kernel virtual address.
1550 ul_gpp_phys + ul_shm0_rsrvd_start * hio_mgr->word_size -
1553 * Calc Gpp phys base of SM region.
1554 * This is the physical address.
1557 dw_gpp_base_pa + ul_shm0_rsrvd_start * hio_mgr->word_size -
1559 /* Register SM Segment 0. */
1561 cmm_register_gppsm_seg(hio_mgr->cmm_mgr, dw_gpp_base_pa,
1562 ul_rsrvd_size, dw_offset,
1564 ul_dsp_virt) ? CMM_ADDTODSPPA :
1566 (u32) (ul_shm0_base *
1567 hio_mgr->word_size),
1568 ul_dsp_size, &ul_shm_seg_id0,
1570 /* First SM region is seg_id = 1 */
1571 if (ul_shm_seg_id0 != 1)
1578 /* ZCPY IO routines. */
1580 * ======== IO_SHMcontrol ========
1581 * Sets the requested shm setting.
1583 int io_sh_msetting(struct io_mgr *hio_mgr, u8 desc, void *pargs)
1585 #ifdef CONFIG_TIDSPBRIDGE_DVFS
1587 struct dspbridge_platform_data *pdata =
1588 omap_dspbridge_dev->dev.platform_data;
1592 /* Update the shared memory with requested OPP information */
1594 hio_mgr->shared_mem->opp_table_struct.curr_opp_pt =
1601 * Update the shared memory with the voltage, frequency,
1602 * min and max frequency values for an OPP.
1604 for (i = 0; i <= dsp_max_opps; i++) {
1605 hio_mgr->shared_mem->opp_table_struct.opp_point[i].
1606 voltage = vdd1_dsp_freq[i][0];
1607 dev_dbg(bridge, "OPP-shm: voltage: %d\n",
1608 vdd1_dsp_freq[i][0]);
1609 hio_mgr->shared_mem->opp_table_struct.
1610 opp_point[i].frequency = vdd1_dsp_freq[i][1];
1611 dev_dbg(bridge, "OPP-shm: frequency: %d\n",
1612 vdd1_dsp_freq[i][1]);
1613 hio_mgr->shared_mem->opp_table_struct.opp_point[i].
1614 min_freq = vdd1_dsp_freq[i][2];
1615 dev_dbg(bridge, "OPP-shm: min freq: %d\n",
1616 vdd1_dsp_freq[i][2]);
1617 hio_mgr->shared_mem->opp_table_struct.opp_point[i].
1618 max_freq = vdd1_dsp_freq[i][3];
1619 dev_dbg(bridge, "OPP-shm: max freq: %d\n",
1620 vdd1_dsp_freq[i][3]);
1622 hio_mgr->shared_mem->opp_table_struct.num_opp_pts =
1624 dev_dbg(bridge, "OPP-shm: max OPP number: %d\n", dsp_max_opps);
1625 /* Update the current OPP number */
1626 if (pdata->dsp_get_opp)
1627 i = (*pdata->dsp_get_opp) ();
1628 hio_mgr->shared_mem->opp_table_struct.curr_opp_pt = i;
1629 dev_dbg(bridge, "OPP-shm: value programmed = %d\n", i);
1632 /* Get the OPP that DSP has requested */
1633 *(u32 *) pargs = hio_mgr->shared_mem->opp_request.rqst_opp_pt;
1643 * ======== bridge_io_get_proc_load ========
1644 * Gets the Processor's Load information
1646 int bridge_io_get_proc_load(struct io_mgr *hio_mgr,
1647 struct dsp_procloadstat *proc_lstat)
1649 if (!hio_mgr->shared_mem)
1652 proc_lstat->curr_load =
1653 hio_mgr->shared_mem->load_mon_info.curr_dsp_load;
1654 proc_lstat->predicted_load =
1655 hio_mgr->shared_mem->load_mon_info.pred_dsp_load;
1656 proc_lstat->curr_dsp_freq =
1657 hio_mgr->shared_mem->load_mon_info.curr_dsp_freq;
1658 proc_lstat->predicted_freq =
1659 hio_mgr->shared_mem->load_mon_info.pred_dsp_freq;
1661 dev_dbg(bridge, "Curr Load = %d, Pred Load = %d, Curr Freq = %d, "
1662 "Pred Freq = %d\n", proc_lstat->curr_load,
1663 proc_lstat->predicted_load, proc_lstat->curr_dsp_freq,
1664 proc_lstat->predicted_freq);
1669 #if defined(CONFIG_TIDSPBRIDGE_BACKTRACE)
1670 void print_dsp_debug_trace(struct io_mgr *hio_mgr)
1672 u32 ul_new_message_length = 0, ul_gpp_cur_pointer;
1675 /* Get the DSP current pointer */
1676 ul_gpp_cur_pointer =
1677 *(u32 *) (hio_mgr->trace_buffer_current);
1678 ul_gpp_cur_pointer =
1679 hio_mgr->gpp_va + (ul_gpp_cur_pointer -
1682 /* No new debug messages available yet */
1683 if (ul_gpp_cur_pointer == hio_mgr->gpp_read_pointer) {
1685 } else if (ul_gpp_cur_pointer > hio_mgr->gpp_read_pointer) {
1686 /* Continuous data */
1687 ul_new_message_length =
1688 ul_gpp_cur_pointer - hio_mgr->gpp_read_pointer;
1690 memcpy(hio_mgr->msg,
1691 (char *)hio_mgr->gpp_read_pointer,
1692 ul_new_message_length);
1693 hio_mgr->msg[ul_new_message_length] = '\0';
1695 * Advance the GPP trace pointer to DSP current
1698 hio_mgr->gpp_read_pointer += ul_new_message_length;
1699 /* Print the trace messages */
1700 pr_info("DSPTrace: %s\n", hio_mgr->msg);
1701 } else if (ul_gpp_cur_pointer < hio_mgr->gpp_read_pointer) {
1702 /* Handle trace buffer wraparound */
1703 memcpy(hio_mgr->msg,
1704 (char *)hio_mgr->gpp_read_pointer,
1705 hio_mgr->trace_buffer_end -
1706 hio_mgr->gpp_read_pointer);
1707 ul_new_message_length =
1708 ul_gpp_cur_pointer - hio_mgr->trace_buffer_begin;
1709 memcpy(&hio_mgr->msg[hio_mgr->trace_buffer_end -
1710 hio_mgr->gpp_read_pointer],
1711 (char *)hio_mgr->trace_buffer_begin,
1712 ul_new_message_length);
1713 hio_mgr->msg[hio_mgr->trace_buffer_end -
1714 hio_mgr->gpp_read_pointer +
1715 ul_new_message_length] = '\0';
1717 * Advance the GPP trace pointer to DSP current
1720 hio_mgr->gpp_read_pointer =
1721 hio_mgr->trace_buffer_begin +
1722 ul_new_message_length;
1723 /* Print the trace messages */
1724 pr_info("DSPTrace: %s\n", hio_mgr->msg);
1730 #ifdef CONFIG_TIDSPBRIDGE_BACKTRACE
1732 * ======== print_dsp_trace_buffer ========
1733 * Prints the trace buffer returned from the DSP (if DBG_Trace is enabled).
1735 * hdeh_mgr: Handle to DEH manager object
1736 * number of extra carriage returns to generate.
1739 * -ENOMEM: Unable to allocate memory.
1741 * hdeh_mgr muse be valid. Checked in bridge_deh_notify.
1743 int print_dsp_trace_buffer(struct bridge_dev_context *hbridge_context)
1746 struct cod_manager *cod_mgr;
1750 u32 ul_num_bytes = 0;
1751 u32 ul_num_words = 0;
1752 u32 ul_word_size = 2;
1759 struct bridge_dev_context *pbridge_context = hbridge_context;
1760 struct bridge_drv_interface *intf_fxns;
1761 struct dev_object *dev_obj = (struct dev_object *)
1762 pbridge_context->dev_obj;
1764 status = dev_get_cod_mgr(dev_obj, &cod_mgr);
1767 /* Look for SYS_PUTCBEG/SYS_PUTCEND */
1769 cod_get_sym_value(cod_mgr, COD_TRACEBEG, &ul_trace_begin);
1775 cod_get_sym_value(cod_mgr, COD_TRACEEND, &ul_trace_end);
1778 /* trace_cur_pos will hold the address of a DSP pointer */
1779 status = cod_get_sym_value(cod_mgr, COD_TRACECURPOS,
1785 ul_num_bytes = (ul_trace_end - ul_trace_begin);
1787 ul_num_words = ul_num_bytes * ul_word_size;
1788 status = dev_get_intf_fxns(dev_obj, &intf_fxns);
1793 psz_buf = kzalloc(ul_num_bytes + 2, GFP_ATOMIC);
1794 if (psz_buf != NULL) {
1795 /* Read trace buffer data */
1796 status = (*intf_fxns->brd_read)(pbridge_context,
1797 (u8 *)psz_buf, (u32)ul_trace_begin,
1803 /* Pack and do newline conversion */
1804 pr_debug("PrintDspTraceBuffer: "
1805 "before pack and unpack.\n");
1806 pr_debug("%s: DSP Trace Buffer Begin:\n"
1807 "=======================\n%s\n",
1810 /* Read the value at the DSP address in trace_cur_pos. */
1811 status = (*intf_fxns->brd_read)(pbridge_context,
1812 (u8 *)&trace_cur_pos, (u32)trace_cur_pos,
1816 /* Pack and do newline conversion */
1817 pr_info("DSP Trace Buffer Begin:\n"
1818 "=======================\n%s\n",
1822 /* convert to offset */
1823 trace_cur_pos = trace_cur_pos - ul_trace_begin;
1827 * The buffer is not full, find the end of the
1828 * data -- buf_end will be >= pszBuf after
1831 buf_end = &psz_buf[ul_num_bytes+1];
1832 /* DSP print position */
1833 trace_end = &psz_buf[trace_cur_pos];
1836 * Search buffer for a new_line and replace it
1837 * with '\0', then print as string.
1838 * Continue until end of buffer is reached.
1840 str_beg = trace_end;
1841 ul_num_bytes = buf_end - str_beg;
1843 while (str_beg < buf_end) {
1844 new_line = strnchr(str_beg, ul_num_bytes,
1846 if (new_line && new_line < buf_end) {
1848 pr_debug("%s\n", str_beg);
1849 str_beg = ++new_line;
1850 ul_num_bytes = buf_end - str_beg;
1853 * Assume buffer empty if it contains
1856 if (*str_beg != '\0') {
1857 str_beg[ul_num_bytes] = 0;
1858 pr_debug("%s\n", str_beg);
1865 * Search buffer for a nNewLine and replace it
1866 * with '\0', then print as string.
1867 * Continue until buffer is exhausted.
1870 ul_num_bytes = trace_end - str_beg;
1872 while (str_beg < trace_end) {
1873 new_line = strnchr(str_beg, ul_num_bytes, '\n');
1874 if (new_line != NULL && new_line < trace_end) {
1876 pr_debug("%s\n", str_beg);
1877 str_beg = ++new_line;
1878 ul_num_bytes = trace_end - str_beg;
1881 * Assume buffer empty if it contains
1884 if (*str_beg != '\0') {
1885 str_beg[ul_num_bytes] = 0;
1886 pr_debug("%s\n", str_beg);
1888 str_beg = trace_end;
1893 pr_info("\n=======================\n"
1894 "DSP Trace Buffer End:\n");
1901 dev_dbg(bridge, "%s Failed, status 0x%x\n", __func__, status);
1906 * dump_dsp_stack() - This function dumps the data on the DSP stack.
1907 * @bridge_context: Bridge driver's device context pointer.
1910 int dump_dsp_stack(struct bridge_dev_context *bridge_context)
1913 struct cod_manager *code_mgr;
1914 struct node_mgr *node_mgr;
1920 } mmu_fault_dbg_info;
1930 const char *dsp_regs[] = {"EFR", "IERR", "ITSR", "NTSR",
1931 "IRP", "NRP", "AMR", "SSR",
1932 "ILC", "RILC", "IER", "CSR"};
1933 const char *exec_ctxt[] = {"Task", "SWI", "HWI", "Unknown"};
1934 struct bridge_drv_interface *intf_fxns;
1935 struct dev_object *dev_object = bridge_context->dev_obj;
1937 status = dev_get_cod_mgr(dev_object, &code_mgr);
1939 pr_debug("%s: Failed on dev_get_cod_mgr.\n", __func__);
1944 status = dev_get_node_manager(dev_object, &node_mgr);
1946 pr_debug("%s: Failed on dev_get_node_manager.\n",
1953 /* Look for SYS_PUTCBEG/SYS_PUTCEND: */
1955 cod_get_sym_value(code_mgr, COD_TRACEBEG, &trace_begin);
1956 pr_debug("%s: trace_begin Value 0x%x\n",
1957 __func__, trace_begin);
1959 pr_debug("%s: Failed on cod_get_sym_value.\n",
1963 status = dev_get_intf_fxns(dev_object, &intf_fxns);
1965 * Check for the "magic number" in the trace buffer. If it has
1966 * yet to appear then poll the trace buffer to wait for it. Its
1967 * appearance signals that the DSP has finished dumping its state.
1969 mmu_fault_dbg_info.head[0] = 0;
1970 mmu_fault_dbg_info.head[1] = 0;
1973 while ((mmu_fault_dbg_info.head[0] != MMU_FAULT_HEAD1 ||
1974 mmu_fault_dbg_info.head[1] != MMU_FAULT_HEAD2) &&
1975 poll_cnt < POLL_MAX) {
1977 /* Read DSP dump size from the DSP trace buffer... */
1978 status = (*intf_fxns->brd_read)(bridge_context,
1979 (u8 *)&mmu_fault_dbg_info, (u32)trace_begin,
1980 sizeof(mmu_fault_dbg_info), 0);
1988 if (mmu_fault_dbg_info.head[0] != MMU_FAULT_HEAD1 &&
1989 mmu_fault_dbg_info.head[1] != MMU_FAULT_HEAD2) {
1991 pr_err("%s:No DSP MMU-Fault information available.\n",
1997 total_size = mmu_fault_dbg_info.size;
1998 /* Limit the size in case DSP went crazy */
1999 if (total_size > MAX_MMU_DBGBUFF)
2000 total_size = MAX_MMU_DBGBUFF;
2002 buffer = kzalloc(total_size, GFP_ATOMIC);
2005 pr_debug("%s: Failed to "
2006 "allocate stack dump buffer.\n", __func__);
2010 buffer_beg = buffer;
2011 buffer_end = buffer + total_size / 4;
2013 /* Read bytes from the DSP trace buffer... */
2014 status = (*intf_fxns->brd_read)(bridge_context,
2015 (u8 *)buffer, (u32)trace_begin,
2018 pr_debug("%s: Failed to Read Trace Buffer.\n",
2023 pr_err("\nAproximate Crash Position:\n"
2024 "--------------------------\n");
2026 exc_type = buffer[3];
2028 i = buffer[79]; /* IRP */
2030 i = buffer[80]; /* NRP */
2033 cod_get_sym_value(code_mgr, DYNEXTBASE, &dyn_ext_base);
2039 if ((i > dyn_ext_base) && (node_find_addr(node_mgr, i,
2040 0x1000, &offset_output, name) == 0))
2041 pr_err("0x%-8x [\"%s\" + 0x%x]\n", i, name,
2044 pr_err("0x%-8x [Unable to match to a symbol.]\n", i);
2048 pr_err("\nExecution Info:\n"
2049 "---------------\n");
2051 if (*buffer < ARRAY_SIZE(exec_ctxt)) {
2052 pr_err("Execution context \t%s\n",
2053 exec_ctxt[*buffer++]);
2055 pr_err("Execution context corrupt\n");
2059 pr_err("Task Handle\t\t0x%x\n", *buffer++);
2060 pr_err("Stack Pointer\t\t0x%x\n", *buffer++);
2061 pr_err("Stack Top\t\t0x%x\n", *buffer++);
2062 pr_err("Stack Bottom\t\t0x%x\n", *buffer++);
2063 pr_err("Stack Size\t\t0x%x\n", *buffer++);
2064 pr_err("Stack Size In Use\t0x%x\n", *buffer++);
2066 pr_err("\nCPU Registers\n"
2067 "---------------\n");
2069 for (i = 0; i < 32; i++) {
2070 if (i == 4 || i == 6 || i == 8)
2071 pr_err("A%d 0x%-8x [Function Argument %d]\n",
2074 pr_err("A15 0x%-8x [Frame Pointer]\n",
2077 pr_err("A%d 0x%x\n", i, *buffer++);
2080 pr_err("\nB0 0x%x\n", *buffer++);
2081 pr_err("B1 0x%x\n", *buffer++);
2082 pr_err("B2 0x%x\n", *buffer++);
2084 if ((*buffer > dyn_ext_base) && (node_find_addr(node_mgr,
2085 *buffer, 0x1000, &offset_output, name) == 0))
2087 pr_err("B3 0x%-8x [Function Return Pointer:"
2088 " \"%s\" + 0x%x]\n", *buffer, name,
2089 *buffer - offset_output);
2091 pr_err("B3 0x%-8x [Function Return Pointer:"
2092 "Unable to match to a symbol.]\n", *buffer);
2096 for (i = 4; i < 32; i++) {
2097 if (i == 4 || i == 6 || i == 8)
2098 pr_err("B%d 0x%-8x [Function Argument %d]\n",
2101 pr_err("B14 0x%-8x [Data Page Pointer]\n",
2104 pr_err("B%d 0x%x\n", i, *buffer++);
2109 for (i = 0; i < ARRAY_SIZE(dsp_regs); i++)
2110 pr_err("%s 0x%x\n", dsp_regs[i], *buffer++);
2115 for (i = 0; buffer < buffer_end; i++, buffer++) {
2116 if ((*buffer > dyn_ext_base) && (
2117 node_find_addr(node_mgr, *buffer , 0x600,
2118 &offset_output, name) == 0))
2119 pr_err("[%d] 0x%-8x [\"%s\" + 0x%x]\n",
2121 *buffer - offset_output);
2123 pr_err("[%d] 0x%x\n", i, *buffer);
2132 * dump_dl_modules() - This functions dumps the _DLModules loaded in DSP side
2133 * @bridge_context: Bridge driver's device context pointer.
2136 void dump_dl_modules(struct bridge_dev_context *bridge_context)
2138 struct cod_manager *code_mgr;
2139 struct bridge_drv_interface *intf_fxns;
2140 struct bridge_dev_context *bridge_ctxt = bridge_context;
2141 struct dev_object *dev_object = bridge_ctxt->dev_obj;
2142 struct modules_header modules_hdr;
2143 struct dll_module *module_struct = NULL;
2144 u32 module_dsp_addr;
2146 u32 module_struct_size = 0;
2151 status = dev_get_intf_fxns(dev_object, &intf_fxns);
2153 pr_debug("%s: Failed on dev_get_intf_fxns.\n", __func__);
2157 status = dev_get_cod_mgr(dev_object, &code_mgr);
2159 pr_debug("%s: Failed on dev_get_cod_mgr.\n", __func__);
2164 /* Lookup the address of the modules_header structure */
2165 status = cod_get_sym_value(code_mgr, "_DLModules", &module_dsp_addr);
2167 pr_debug("%s: Failed on cod_get_sym_value for _DLModules.\n",
2172 pr_debug("%s: _DLModules at 0x%x\n", __func__, module_dsp_addr);
2174 /* Copy the modules_header structure from DSP memory. */
2175 status = (*intf_fxns->brd_read)(bridge_context, (u8 *) &modules_hdr,
2176 (u32) module_dsp_addr, sizeof(modules_hdr), 0);
2179 pr_debug("%s: Failed failed to read modules header.\n",
2184 module_dsp_addr = modules_hdr.first_module;
2185 module_size = modules_hdr.first_module_size;
2187 pr_debug("%s: dll_module_header 0x%x %d\n", __func__, module_dsp_addr,
2190 pr_err("\nDynamically Loaded Modules:\n"
2191 "---------------------------\n");
2193 /* For each dll_module structure in the list... */
2194 while (module_size) {
2196 * Allocate/re-allocate memory to hold the dll_module
2197 * structure. The memory is re-allocated only if the existing
2198 * allocation is too small.
2200 if (module_size > module_struct_size) {
2201 kfree(module_struct);
2202 module_struct = kzalloc(module_size+128, GFP_ATOMIC);
2203 module_struct_size = module_size+128;
2204 pr_debug("%s: allocated module struct %p %d\n",
2205 __func__, module_struct, module_struct_size);
2209 /* Copy the dll_module structure from DSP memory */
2210 status = (*intf_fxns->brd_read)(bridge_context,
2211 (u8 *)module_struct, module_dsp_addr, module_size, 0);
2215 "%s: Failed to read dll_module struct for 0x%x.\n",
2216 __func__, module_dsp_addr);
2220 /* Update info regarding the _next_ module in the list. */
2221 module_dsp_addr = module_struct->next_module;
2222 module_size = module_struct->next_module_size;
2224 pr_debug("%s: next module 0x%x %d, this module num sects %d\n",
2225 __func__, module_dsp_addr, module_size,
2226 module_struct->num_sects);
2229 * The section name strings start immedialty following
2230 * the array of dll_sect structures.
2232 sect_str = (char *) &module_struct->
2233 sects[module_struct->num_sects];
2234 pr_err("%s\n", sect_str);
2237 * Advance to the first section name string.
2238 * Each string follows the one before.
2240 sect_str += strlen(sect_str) + 1;
2242 /* Access each dll_sect structure and its name string. */
2244 sect_ndx < module_struct->num_sects; sect_ndx++) {
2245 pr_err(" Section: 0x%x ",
2246 module_struct->sects[sect_ndx].sect_load_adr);
2248 if (((u32) sect_str - (u32) module_struct) <
2249 module_struct_size) {
2250 pr_err("%s\n", sect_str);
2251 /* Each string follows the one before. */
2252 sect_str += strlen(sect_str)+1;
2254 pr_err("<string error>\n");
2255 pr_debug("%s: section name sting address "
2256 "is invalid %p\n", __func__, sect_str);
2261 kfree(module_struct);