Pileus Git - ~andy/linux/blob - drivers/staging/silicom/bpctl_mod.c

   1 /******************************************************************************/
   2 /*                                                                            */
   3 /* Bypass Control utility, Copyright (c) 2005-2011 Silicom                    */
   4 /*                                                                            */
   5 /* This program is free software; you can redistribute it and/or modify       */
   6 /* it under the terms of the GNU General Public License as published by       */
   7 /* the Free Software Foundation, located in the file LICENSE.                 */
   8 /* Copyright(c) 2007 - 2009, 2013 Intel Corporation. All rights reserved.     */
   9 /*                                                                            */
  10 /*                                                                            */
  11 /******************************************************************************/
  12
  13 #include <linux/kernel.h>       /* We're doing kernel work */
  14 #include <linux/module.h>       /* Specifically, a module */
  15 #include <linux/fs.h>
  16 #include <linux/pci.h>
  17 #include <linux/delay.h>
  18 #include <linux/netdevice.h>
  19 #include <linux/rtnetlink.h>
  20 #include <linux/rcupdate.h>
  21 #include <linux/etherdevice.h>
  22
  23 #include <linux/uaccess.h>      /* for get_user and put_user */
  24 #include <linux/sched.h>
  25 #include <linux/ethtool.h>
  26 #include <linux/proc_fs.h>
  27
  28 #include "bp_ioctl.h"
  29 #include "bp_mod.h"
  30 #include "bypass.h"
  31 #include "libbp_sd.h"
  32
  33 #define SUCCESS 0
  34 #define BP_MOD_VER  "9.0.4"
  35 #define BP_MOD_DESCR "Silicom Bypass-SD Control driver"
  36 #define BP_SYNC_FLAG 1
  37
  38 static int major_num;
  39
  40 MODULE_AUTHOR("Anna Lukin, annal@silicom.co.il");
  41 MODULE_LICENSE("GPL");
  42 MODULE_DESCRIPTION(BP_MOD_DESCR);
  43 MODULE_VERSION(BP_MOD_VER);
  44 spinlock_t bpvm_lock;
  45
  46 #define unlock_bpctl()                                  \
  47         up(&bpctl_sema);
  48
  49 /* Media Types */
  50 enum bp_media_type {
  51         BP_COPPER = 0,
  52         BP_FIBER,
  53         BP_CX4,
  54         BP_NONE,
  55 };
  56
  57 struct bypass_pfs_sd {
  58         char dir_name[32];
  59         struct proc_dir_entry *bypass_entry;
  60 };
  61
  62 struct bpctl_dev {
  63         char *name;
  64         char *desc;
  65         struct pci_dev *pdev;   /* PCI device */
  66         struct net_device *ndev;        /* net device */
  67         unsigned long mem_map;
  68         uint8_t bus;
  69         uint8_t slot;
  70         uint8_t func;
  71         u_int32_t device;
  72         u_int32_t vendor;
  73         u_int32_t subvendor;
  74         u_int32_t subdevice;
  75         int ifindex;
  76         uint32_t bp_caps;
  77         uint32_t bp_caps_ex;
  78         uint8_t bp_fw_ver;
  79         int bp_ext_ver;
  80         int wdt_status;
  81         unsigned long bypass_wdt_on_time;
  82         uint32_t bypass_timer_interval;
  83         struct timer_list bp_timer;
  84         uint32_t reset_time;
  85         uint8_t bp_status_un;
  86         atomic_t wdt_busy;
  87         enum bp_media_type media_type;
  88         int bp_tpl_flag;
  89         struct timer_list bp_tpl_timer;
  90         spinlock_t bypass_wr_lock;
  91         int bp_10g;
  92         int bp_10gb;
  93         int bp_fiber5;
  94         int bp_10g9;
  95         int bp_i80;
  96         int bp_540;
  97         int (*hard_start_xmit_save) (struct sk_buff *skb,
  98                                      struct net_device *dev);
  99         const struct net_device_ops *old_ops;
 100         struct net_device_ops new_ops;
 101         int bp_self_test_flag;
 102         char *bp_tx_data;
 103         struct bypass_pfs_sd bypass_pfs_set;
 104
 105 };
 106
 107 static struct bpctl_dev *bpctl_dev_arr;
 108
 109 static struct semaphore bpctl_sema;
 110 static int device_num;
 111
 112 static int get_dev_idx(int ifindex);
 113 static struct bpctl_dev *get_master_port_fn(struct bpctl_dev *pbpctl_dev);
 114 static int disc_status(struct bpctl_dev *pbpctl_dev);
 115 static int bypass_status(struct bpctl_dev *pbpctl_dev);
 116 static int wdt_timer(struct bpctl_dev *pbpctl_dev, int *time_left);
 117 static struct bpctl_dev *get_status_port_fn(struct bpctl_dev *pbpctl_dev);
 118 static void if_scan_init(void);
 119
 120 int bypass_proc_create_dev_sd(struct bpctl_dev *pbp_device_block);
 121 int bypass_proc_remove_dev_sd(struct bpctl_dev *pbp_device_block);
 122 int bp_proc_create(void);
 123
 124 int is_bypass_fn(struct bpctl_dev *pbpctl_dev);
 125 int get_dev_idx_bsf(int bus, int slot, int func);
 126
 127 static int bp_get_dev_idx_bsf(struct net_device *dev, int *index)
 128 {
 129         struct ethtool_drvinfo drvinfo = {0};
 130         char *buf;
 131         int bus, slot, func;
 132
 133         if (dev->ethtool_ops && dev->ethtool_ops->get_drvinfo)
 134                 dev->ethtool_ops->get_drvinfo(dev, &drvinfo);
 135         else
 136                 return -EOPNOTSUPP;
 137
 138         if (!drvinfo.bus_info)
 139                 return -ENODATA;
 140         if (!strcmp(drvinfo.bus_info, "N/A"))
 141                 return -ENODATA;
 142
 143         buf = strchr(drvinfo.bus_info, ':');
 144         if (!buf)
 145                 return -EINVAL;
 146         buf++;
 147         if (sscanf(buf, "%x:%x.%x", &bus, &slot, &func) != 3)
 148                 return -EINVAL;
 149
 150         *index = get_dev_idx_bsf(bus, slot, func);
 151         return 0;
 152 }
 153
 154 static int bp_device_event(struct notifier_block *unused,
 155                            unsigned long event, void *ptr)
 156 {
 157         struct net_device *dev = netdev_notifier_info_to_dev(ptr);
 158         static struct bpctl_dev *pbpctl_dev, *pbpctl_dev_m;
 159         int dev_num = 0, ret = 0, ret_d = 0, time_left = 0;
 160
 161         /* printk("BP_PROC_SUPPORT event =%d %s %d\n", event,dev->name, dev->ifindex ); */
 162         /* return NOTIFY_DONE; */
 163         if (!dev)
 164                 return NOTIFY_DONE;
 165
 166         if (event == NETDEV_REGISTER) {
 167                 int idx_dev;
 168
 169                 if (bp_get_dev_idx_bsf(dev, &idx_dev))
 170                         return NOTIFY_DONE;
 171
 172                 if (idx_dev == -1)
 173                         return NOTIFY_DONE;
 174
 175                 bpctl_dev_arr[idx_dev].ifindex = dev->ifindex;
 176                 bpctl_dev_arr[idx_dev].ndev = dev;
 177
 178                 bypass_proc_remove_dev_sd(&bpctl_dev_arr[idx_dev]);
 179                 bypass_proc_create_dev_sd(&bpctl_dev_arr[idx_dev]);
 180                 return NOTIFY_DONE;
 181         }
 182         if (event == NETDEV_UNREGISTER) {
 183                 int idx_dev = 0;
 184                 for (idx_dev = 0;
 185                      ((bpctl_dev_arr[idx_dev].pdev != NULL)
 186                       && (idx_dev < device_num)); idx_dev++) {
 187                         if (bpctl_dev_arr[idx_dev].ndev == dev) {
 188                                 bypass_proc_remove_dev_sd(&bpctl_dev_arr
 189                                                           [idx_dev]);
 190                                 bpctl_dev_arr[idx_dev].ndev = NULL;
 191
 192                                 return NOTIFY_DONE;
 193
 194                         }
 195
 196                 }
 197                 return NOTIFY_DONE;
 198         }
 199         if (event == NETDEV_CHANGENAME) {
 200                 int idx_dev = 0;
 201                 for (idx_dev = 0;
 202                      ((bpctl_dev_arr[idx_dev].pdev != NULL)
 203                       && (idx_dev < device_num)); idx_dev++) {
 204                         if (bpctl_dev_arr[idx_dev].ndev == dev) {
 205                                 bypass_proc_remove_dev_sd(&bpctl_dev_arr
 206                                                           [idx_dev]);
 207                                 bypass_proc_create_dev_sd(&bpctl_dev_arr
 208                                                           [idx_dev]);
 209
 210                                 return NOTIFY_DONE;
 211
 212                         }
 213
 214                 }
 215                 return NOTIFY_DONE;
 216
 217         }
 218
 219         switch (event) {
 220
 221         case NETDEV_CHANGE:{
 222                         if (netif_carrier_ok(dev))
 223                                 return NOTIFY_DONE;
 224
 225                         if (((dev_num = get_dev_idx(dev->ifindex)) == -1) ||
 226                             (!(pbpctl_dev = &bpctl_dev_arr[dev_num])))
 227                                 return NOTIFY_DONE;
 228
 229                         if ((is_bypass_fn(pbpctl_dev)) == 1)
 230                                 pbpctl_dev_m = pbpctl_dev;
 231                         else
 232                                 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
 233                         if (!pbpctl_dev_m)
 234                                 return NOTIFY_DONE;
 235                         ret = bypass_status(pbpctl_dev_m);
 236                         if (ret == 1)
 237                                 printk("bpmod: %s is in the Bypass mode now",
 238                                        dev->name);
 239                         ret_d = disc_status(pbpctl_dev_m);
 240                         if (ret_d == 1)
 241                                 printk
 242                                     ("bpmod: %s is in the Disconnect mode now",
 243                                      dev->name);
 244                         if (ret || ret_d) {
 245                                 wdt_timer(pbpctl_dev_m, &time_left);
 246                                 if (time_left == -1)
 247                                         printk("; WDT has expired");
 248                                 printk(".\n");
 249
 250                         }
 251                         return NOTIFY_DONE;
 252
 253                 }
 254
 255         default:
 256                 return NOTIFY_DONE;
 257
 258         }
 259         return NOTIFY_DONE;
 260
 261 }
 262
 263 static struct notifier_block bp_notifier_block = {
 264         .notifier_call = bp_device_event,
 265 };
 266
 267 int is_bypass_fn(struct bpctl_dev *pbpctl_dev);
 268 int wdt_time_left(struct bpctl_dev *pbpctl_dev);
 269
 270 static void write_pulse(struct bpctl_dev *pbpctl_dev,
 271                         unsigned int ctrl_ext,
 272                         unsigned char value, unsigned char len)
 273 {
 274         unsigned char ctrl_val = 0;
 275         unsigned int i = len;
 276         unsigned int ctrl = 0;
 277         struct bpctl_dev *pbpctl_dev_c = NULL;
 278
 279         if (pbpctl_dev->bp_i80)
 280                 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
 281         if (pbpctl_dev->bp_540)
 282                 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
 283
 284         if (pbpctl_dev->bp_10g9) {
 285                 pbpctl_dev_c = get_status_port_fn(pbpctl_dev);
 286                 if (!pbpctl_dev_c)
 287                         return;
 288                 ctrl = BP10G_READ_REG(pbpctl_dev_c, ESDP);
 289         }
 290
 291         while (i--) {
 292                 ctrl_val = (value >> i) & 0x1;
 293                 if (ctrl_val) {
 294                         if (pbpctl_dev->bp_10g9) {
 295
 296                                 /* To start management : MCLK 1, MDIO 1, output */
 297                                 /* DATA 1 CLK 1 */
 298                                 /*BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext|BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9)); */
 299                                 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
 300                                                 ctrl_ext |
 301                                                 BP10G_MDIO_DATA_OUT9);
 302                                 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
 303                                                 (ctrl | BP10G_MCLK_DATA_OUT9 |
 304                                                  BP10G_MCLK_DIR_OUT9));
 305
 306                         } else if (pbpctl_dev->bp_fiber5) {
 307                                 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, (ctrl_ext |
 308                                                                       BPCTLI_CTRL_EXT_MCLK_DIR5
 309                                                                       |
 310                                                                       BPCTLI_CTRL_EXT_MDIO_DIR5
 311                                                                       |
 312                                                                       BPCTLI_CTRL_EXT_MDIO_DATA5
 313                                                                       |
 314                                                                       BPCTLI_CTRL_EXT_MCLK_DATA5));
 315
 316                         } else if (pbpctl_dev->bp_i80) {
 317                                 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, (ctrl_ext |
 318                                                                       BPCTLI_CTRL_EXT_MDIO_DIR80
 319                                                                       |
 320                                                                       BPCTLI_CTRL_EXT_MDIO_DATA80));
 321
 322                                 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, (ctrl |
 323                                                                           BPCTLI_CTRL_EXT_MCLK_DIR80
 324                                                                           |
 325                                                                           BPCTLI_CTRL_EXT_MCLK_DATA80));
 326
 327                         } else if (pbpctl_dev->bp_540) {
 328                                 BP10G_WRITE_REG(pbpctl_dev, ESDP, (ctrl |
 329                                                                    BP540_MDIO_DIR
 330                                                                    |
 331                                                                    BP540_MDIO_DATA
 332                                                                    |
 333                                                                    BP540_MCLK_DIR
 334                                                                    |
 335                                                                    BP540_MCLK_DATA));
 336
 337                         } else if (pbpctl_dev->bp_10gb) {
 338                                 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
 339                                                  (ctrl_ext | BP10GB_MDIO_SET |
 340                                                   BP10GB_MCLK_SET) &
 341                                                  ~(BP10GB_MCLK_DIR |
 342                                                    BP10GB_MDIO_DIR |
 343                                                    BP10GB_MDIO_CLR |
 344                                                    BP10GB_MCLK_CLR));
 345
 346                         } else if (!pbpctl_dev->bp_10g)
 347                                 /* To start management : MCLK 1, MDIO 1, output */
 348                                 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
 349                                                    (ctrl_ext |
 350                                                     BPCTLI_CTRL_EXT_MCLK_DIR |
 351                                                     BPCTLI_CTRL_EXT_MDIO_DIR |
 352                                                     BPCTLI_CTRL_EXT_MDIO_DATA |
 353                                                     BPCTLI_CTRL_EXT_MCLK_DATA));
 354                         else {
 355
 356                                 /* To start management : MCLK 1, MDIO 1, output*/
 357                                 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
 358                                                 (ctrl_ext | BP10G_MCLK_DATA_OUT
 359                                                  | BP10G_MDIO_DATA_OUT));
 360
 361                         }
 362
 363                         usec_delay(PULSE_TIME);
 364                         if (pbpctl_dev->bp_10g9) {
 365
 366                                 /*BP10G_WRITE_REG(pbpctl_dev, I2CCTL, ((ctrl_ext|BP10G_MDIO_DATA_OUT9)&~(BP10G_MCLK_DATA_OUT9))); */
 367                                 /* DATA 1 CLK 0 */
 368                                 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
 369                                                 ctrl_ext |
 370                                                 BP10G_MDIO_DATA_OUT9);
 371                                 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
 372                                                 (ctrl | BP10G_MCLK_DIR_OUT9) &
 373                                                 ~BP10G_MCLK_DATA_OUT9);
 374
 375                         } else if (pbpctl_dev->bp_fiber5) {
 376                                 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
 377                                                    ((ctrl_ext |
 378                                                      BPCTLI_CTRL_EXT_MCLK_DIR5 |
 379                                                      BPCTLI_CTRL_EXT_MDIO_DIR5 |
 380                                                      BPCTLI_CTRL_EXT_MDIO_DATA5)
 381                                                     &
 382                                                     ~
 383                                                     (BPCTLI_CTRL_EXT_MCLK_DATA5)));
 384
 385                         } else if (pbpctl_dev->bp_i80) {
 386                                 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, (ctrl_ext |
 387                                                                       BPCTLI_CTRL_EXT_MDIO_DIR80
 388                                                                       |
 389                                                                       BPCTLI_CTRL_EXT_MDIO_DATA80));
 390                                 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
 391                                                    ((ctrl |
 392                                                      BPCTLI_CTRL_EXT_MCLK_DIR80)
 393                                                     &
 394                                                     ~
 395                                                     (BPCTLI_CTRL_EXT_MCLK_DATA80)));
 396
 397                         } else if (pbpctl_dev->bp_540) {
 398                                 BP10G_WRITE_REG(pbpctl_dev, ESDP,
 399                                                 (ctrl | BP540_MDIO_DIR |
 400                                                  BP540_MDIO_DATA |
 401                                                  BP540_MCLK_DIR) &
 402                                                 ~(BP540_MCLK_DATA));
 403
 404                         } else if (pbpctl_dev->bp_10gb) {
 405
 406                                 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
 407                                                  (ctrl_ext | BP10GB_MDIO_SET |
 408                                                   BP10GB_MCLK_CLR) &
 409                                                  ~(BP10GB_MCLK_DIR |
 410                                                    BP10GB_MDIO_DIR |
 411                                                    BP10GB_MDIO_CLR |
 412                                                    BP10GB_MCLK_SET));
 413
 414                         } else if (!pbpctl_dev->bp_10g)
 415
 416                                 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
 417                                                    ((ctrl_ext |
 418                                                      BPCTLI_CTRL_EXT_MCLK_DIR |
 419                                                      BPCTLI_CTRL_EXT_MDIO_DIR |
 420                                                      BPCTLI_CTRL_EXT_MDIO_DATA)
 421                                                     &
 422                                                     ~
 423                                                     (BPCTLI_CTRL_EXT_MCLK_DATA)));
 424                         else {
 425
 426                                 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
 427                                                 ((ctrl_ext |
 428                                                   BP10G_MDIO_DATA_OUT) &
 429                                                  ~(BP10G_MCLK_DATA_OUT)));
 430                         }
 431
 432                         usec_delay(PULSE_TIME);
 433
 434                 } else {
 435                         if (pbpctl_dev->bp_10g9) {
 436                                 /* DATA 0 CLK 1 */
 437                                 /*BP10G_WRITE_REG(pbpctl_dev, I2CCTL, ((ctrl_ext|BP10G_MCLK_DATA_OUT9)&~BP10G_MDIO_DATA_OUT9)); */
 438                                 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
 439                                                 (ctrl_ext &
 440                                                  ~BP10G_MDIO_DATA_OUT9));
 441                                 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
 442                                                 (ctrl | BP10G_MCLK_DATA_OUT9 |
 443                                                  BP10G_MCLK_DIR_OUT9));
 444
 445                         } else if (pbpctl_dev->bp_fiber5) {
 446                                 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
 447                                                    ((ctrl_ext |
 448                                                      BPCTLI_CTRL_EXT_MCLK_DIR5 |
 449                                                      BPCTLI_CTRL_EXT_MDIO_DIR5 |
 450                                                      BPCTLI_CTRL_EXT_MCLK_DATA5)
 451                                                     &
 452                                                     ~
 453                                                     (BPCTLI_CTRL_EXT_MDIO_DATA5)));
 454
 455                         } else if (pbpctl_dev->bp_i80) {
 456                                 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
 457                                                    ((ctrl_ext |
 458                                                      BPCTLI_CTRL_EXT_MDIO_DIR80)
 459                                                     &
 460                                                     ~
 461                                                     (BPCTLI_CTRL_EXT_MDIO_DATA80)));
 462                                 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
 463                                                    (ctrl |
 464                                                     BPCTLI_CTRL_EXT_MCLK_DIR80 |
 465                                                     BPCTLI_CTRL_EXT_MCLK_DATA80));
 466
 467                         } else if (pbpctl_dev->bp_540) {
 468                                 BP10G_WRITE_REG(pbpctl_dev, ESDP,
 469                                                 ((ctrl | BP540_MCLK_DIR |
 470                                                   BP540_MCLK_DATA |
 471                                                   BP540_MDIO_DIR) &
 472                                                  ~(BP540_MDIO_DATA)));
 473
 474                         } else if (pbpctl_dev->bp_10gb) {
 475                                 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
 476                                                  (ctrl_ext | BP10GB_MDIO_CLR |
 477                                                   BP10GB_MCLK_SET) &
 478                                                  ~(BP10GB_MCLK_DIR |
 479                                                    BP10GB_MDIO_DIR |
 480                                                    BP10GB_MDIO_SET |
 481                                                    BP10GB_MCLK_CLR));
 482
 483                         } else if (!pbpctl_dev->bp_10g)
 484
 485                                 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
 486                                                    ((ctrl_ext |
 487                                                      BPCTLI_CTRL_EXT_MCLK_DIR |
 488                                                      BPCTLI_CTRL_EXT_MDIO_DIR |
 489                                                      BPCTLI_CTRL_EXT_MCLK_DATA)
 490                                                     &
 491                                                     ~
 492                                                     (BPCTLI_CTRL_EXT_MDIO_DATA)));
 493                         else {
 494
 495                                 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
 496                                                 ((ctrl_ext |
 497                                                   BP10G_MCLK_DATA_OUT) &
 498                                                  ~BP10G_MDIO_DATA_OUT));
 499
 500                         }
 501                         usec_delay(PULSE_TIME);
 502                         if (pbpctl_dev->bp_10g9) {
 503                                 /* DATA 0 CLK 0 */
 504                                 /*BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext&~(BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9))); */
 505                                 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
 506                                                 (ctrl_ext &
 507                                                  ~BP10G_MDIO_DATA_OUT9));
 508                                 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
 509                                                 ((ctrl | BP10G_MCLK_DIR_OUT9) &
 510                                                  ~(BP10G_MCLK_DATA_OUT9)));
 511
 512                         } else if (pbpctl_dev->bp_fiber5) {
 513                                 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
 514                                                    ((ctrl_ext |
 515                                                      BPCTLI_CTRL_EXT_MCLK_DIR5 |
 516                                                      BPCTLI_CTRL_EXT_MDIO_DIR5)
 517                                                     &
 518                                                     ~(BPCTLI_CTRL_EXT_MCLK_DATA5
 519                                                       |
 520                                                       BPCTLI_CTRL_EXT_MDIO_DATA5)));
 521
 522                         } else if (pbpctl_dev->bp_i80) {
 523                                 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
 524                                                    ((ctrl_ext |
 525                                                      BPCTLI_CTRL_EXT_MDIO_DIR80)
 526                                                     &
 527                                                     ~BPCTLI_CTRL_EXT_MDIO_DATA80));
 528                                 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
 529                                                    ((ctrl |
 530                                                      BPCTLI_CTRL_EXT_MCLK_DIR80)
 531                                                     &
 532                                                     ~
 533                                                     (BPCTLI_CTRL_EXT_MCLK_DATA80)));
 534
 535                         } else if (pbpctl_dev->bp_540) {
 536                                 BP10G_WRITE_REG(pbpctl_dev, ESDP,
 537                                                 ((ctrl | BP540_MCLK_DIR |
 538                                                   BP540_MDIO_DIR) &
 539                                                  ~(BP540_MDIO_DATA |
 540                                                    BP540_MCLK_DATA)));
 541                         } else if (pbpctl_dev->bp_10gb) {
 542
 543                                 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
 544                                                  (ctrl_ext | BP10GB_MDIO_CLR |
 545                                                   BP10GB_MCLK_CLR) &
 546                                                  ~(BP10GB_MCLK_DIR |
 547                                                    BP10GB_MDIO_DIR |
 548                                                    BP10GB_MDIO_SET |
 549                                                    BP10GB_MCLK_SET));
 550
 551                         } else if (!pbpctl_dev->bp_10g)
 552                                 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
 553                                                    ((ctrl_ext |
 554                                                      BPCTLI_CTRL_EXT_MCLK_DIR |
 555                                                      BPCTLI_CTRL_EXT_MDIO_DIR) &
 556                                                     ~(BPCTLI_CTRL_EXT_MCLK_DATA
 557                                                       |
 558                                                       BPCTLI_CTRL_EXT_MDIO_DATA)));
 559                         else {
 560
 561                                 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
 562                                                 (ctrl_ext &
 563                                                  ~(BP10G_MCLK_DATA_OUT |
 564                                                    BP10G_MDIO_DATA_OUT)));
 565                         }
 566
 567                         usec_delay(PULSE_TIME);
 568                 }
 569
 570         }
 571 }
 572
 573 static int read_pulse(struct bpctl_dev *pbpctl_dev, unsigned int ctrl_ext,
 574                       unsigned char len)
 575 {
 576         unsigned char ctrl_val = 0;
 577         unsigned int i = len;
 578         unsigned int ctrl = 0;
 579         struct bpctl_dev *pbpctl_dev_c = NULL;
 580
 581         if (pbpctl_dev->bp_i80)
 582                 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
 583         if (pbpctl_dev->bp_540)
 584                 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
 585         if (pbpctl_dev->bp_10g9) {
 586                 pbpctl_dev_c = get_status_port_fn(pbpctl_dev);
 587                 if (!pbpctl_dev_c)
 588                         return -1;
 589                 ctrl = BP10G_READ_REG(pbpctl_dev_c, ESDP);
 590         }
 591
 592
 593         while (i--) {
 594                 if (pbpctl_dev->bp_10g9) {
 595                         /*BP10G_WRITE_REG(pbpctl_dev, I2CCTL, ((ctrl_ext|BP10G_MDIO_DATA_OUT9)&~BP10G_MCLK_DATA_OUT9)); */
 596                         /* DATA ? CLK 0 */
 597                         BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
 598                                         ((ctrl | BP10G_MCLK_DIR_OUT9) &
 599                                          ~(BP10G_MCLK_DATA_OUT9)));
 600
 601                 } else if (pbpctl_dev->bp_fiber5) {
 602                         BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
 603                                                                BPCTLI_CTRL_EXT_MCLK_DIR5)
 604                                                               &
 605                                                               ~
 606                                                               (BPCTLI_CTRL_EXT_MDIO_DIR5
 607                                                                |
 608                                                                BPCTLI_CTRL_EXT_MCLK_DATA5)));
 609
 610                 } else if (pbpctl_dev->bp_i80) {
 611                         BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
 612                                            (ctrl_ext &
 613                                             ~BPCTLI_CTRL_EXT_MDIO_DIR80));
 614                         BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
 615                                            ((ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80)
 616                                             & ~(BPCTLI_CTRL_EXT_MCLK_DATA80)));
 617
 618                 } else if (pbpctl_dev->bp_540) {
 619                         BP10G_WRITE_REG(pbpctl_dev, ESDP,
 620                                         ((ctrl | BP540_MCLK_DIR) &
 621                                          ~(BP540_MDIO_DIR | BP540_MCLK_DATA)));
 622
 623                 } else if (pbpctl_dev->bp_10gb) {
 624
 625                         BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
 626                                          (ctrl_ext | BP10GB_MDIO_DIR |
 627                                           BP10GB_MCLK_CLR) & ~(BP10GB_MCLK_DIR |
 628                                                                BP10GB_MDIO_CLR |
 629                                                                BP10GB_MDIO_SET |
 630                                                                BP10GB_MCLK_SET));
 631
 632                 } else if (!pbpctl_dev->bp_10g)
 633                         BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
 634                                                                    BPCTLI_CTRL_EXT_MCLK_DIR)
 635                                                                   &
 636                                                                   ~
 637                                                                   (BPCTLI_CTRL_EXT_MDIO_DIR
 638                                                                    |
 639                                                                    BPCTLI_CTRL_EXT_MCLK_DATA)));
 640                 else {
 641
 642                         BP10G_WRITE_REG(pbpctl_dev, EODSDP, ((ctrl_ext | BP10G_MDIO_DATA_OUT) & ~BP10G_MCLK_DATA_OUT)); /* ? */
 643                         /*    printk("0x28=0x%x\n",BP10G_READ_REG(pbpctl_dev,EODSDP);); */
 644
 645                 }
 646
 647                 usec_delay(PULSE_TIME);
 648                 if (pbpctl_dev->bp_10g9) {
 649                         /*BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext|BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9)); */
 650                         /* DATA ? CLK 1 */
 651                         BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
 652                                         (ctrl | BP10G_MCLK_DATA_OUT9 |
 653                                          BP10G_MCLK_DIR_OUT9));
 654
 655                 } else if (pbpctl_dev->bp_fiber5) {
 656                         BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
 657                                                                BPCTLI_CTRL_EXT_MCLK_DIR5
 658                                                                |
 659                                                                BPCTLI_CTRL_EXT_MCLK_DATA5)
 660                                                               &
 661                                                               ~
 662                                                               (BPCTLI_CTRL_EXT_MDIO_DIR5)));
 663
 664                 } else if (pbpctl_dev->bp_i80) {
 665                         BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
 666                                            (ctrl_ext &
 667                                             ~(BPCTLI_CTRL_EXT_MDIO_DIR80)));
 668                         BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
 669                                            (ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80 |
 670                                             BPCTLI_CTRL_EXT_MCLK_DATA80));
 671
 672                 } else if (pbpctl_dev->bp_540) {
 673                         BP10G_WRITE_REG(pbpctl_dev, ESDP,
 674                                         ((ctrl | BP540_MCLK_DIR |
 675                                           BP540_MCLK_DATA) &
 676                                          ~(BP540_MDIO_DIR)));
 677
 678                 } else if (pbpctl_dev->bp_10gb) {
 679                         BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
 680                                          (ctrl_ext | BP10GB_MDIO_DIR |
 681                                           BP10GB_MCLK_SET) & ~(BP10GB_MCLK_DIR |
 682                                                                BP10GB_MDIO_CLR |
 683                                                                BP10GB_MDIO_SET |
 684                                                                BP10GB_MCLK_CLR));
 685
 686                 } else if (!pbpctl_dev->bp_10g)
 687                         BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
 688                                                                    BPCTLI_CTRL_EXT_MCLK_DIR
 689                                                                    |
 690                                                                    BPCTLI_CTRL_EXT_MCLK_DATA)
 691                                                                   &
 692                                                                   ~
 693                                                                   (BPCTLI_CTRL_EXT_MDIO_DIR)));
 694                 else {
 695
 696                         BP10G_WRITE_REG(pbpctl_dev, EODSDP,
 697                                         (ctrl_ext | BP10G_MCLK_DATA_OUT |
 698                                          BP10G_MDIO_DATA_OUT));
 699
 700                 }
 701
 702                 if (pbpctl_dev->bp_10g9)
 703                         ctrl_ext = BP10G_READ_REG(pbpctl_dev, I2CCTL);
 704                 else if ((pbpctl_dev->bp_fiber5) || (pbpctl_dev->bp_i80))
 705                         ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL);
 706                 else if (pbpctl_dev->bp_540)
 707                         ctrl_ext = BP10G_READ_REG(pbpctl_dev, ESDP);
 708                 else if (pbpctl_dev->bp_10gb)
 709                         ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
 710                 else if (!pbpctl_dev->bp_10g)
 711                         ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
 712                 else
 713                         ctrl_ext = BP10G_READ_REG(pbpctl_dev, EODSDP);
 714
 715                 usec_delay(PULSE_TIME);
 716                 if (pbpctl_dev->bp_10g9) {
 717                         if (ctrl_ext & BP10G_MDIO_DATA_IN9)
 718                                 ctrl_val |= 1 << i;
 719
 720                 } else if (pbpctl_dev->bp_fiber5) {
 721                         if (ctrl_ext & BPCTLI_CTRL_EXT_MDIO_DATA5)
 722                                 ctrl_val |= 1 << i;
 723                 } else if (pbpctl_dev->bp_i80) {
 724                         if (ctrl_ext & BPCTLI_CTRL_EXT_MDIO_DATA80)
 725                                 ctrl_val |= 1 << i;
 726                 } else if (pbpctl_dev->bp_540) {
 727                         if (ctrl_ext & BP540_MDIO_DATA)
 728                                 ctrl_val |= 1 << i;
 729                 } else if (pbpctl_dev->bp_10gb) {
 730                         if (ctrl_ext & BP10GB_MDIO_DATA)
 731                                 ctrl_val |= 1 << i;
 732
 733                 } else if (!pbpctl_dev->bp_10g) {
 734
 735                         if (ctrl_ext & BPCTLI_CTRL_EXT_MDIO_DATA)
 736                                 ctrl_val |= 1 << i;
 737                 } else {
 738
 739                         if (ctrl_ext & BP10G_MDIO_DATA_IN)
 740                                 ctrl_val |= 1 << i;
 741                 }
 742
 743         }
 744
 745         return ctrl_val;
 746 }
 747
 748 static void write_reg(struct bpctl_dev *pbpctl_dev, unsigned char value,
 749                       unsigned char addr)
 750 {
 751         uint32_t ctrl_ext = 0, ctrl = 0;
 752         struct bpctl_dev *pbpctl_dev_c = NULL;
 753         unsigned long flags;
 754         if (pbpctl_dev->bp_10g9) {
 755                 pbpctl_dev_c = get_status_port_fn(pbpctl_dev);
 756                 if (!pbpctl_dev_c)
 757                         return;
 758         }
 759         if ((pbpctl_dev->wdt_status == WDT_STATUS_EN) &&
 760             (pbpctl_dev->bp_ext_ver < PXG4BPFI_VER))
 761                 wdt_time_left(pbpctl_dev);
 762
 763 #ifdef BP_SYNC_FLAG
 764         spin_lock_irqsave(&pbpctl_dev->bypass_wr_lock, flags);
 765 #else
 766         atomic_set(&pbpctl_dev->wdt_busy, 1);
 767 #endif
 768         if (pbpctl_dev->bp_10g9) {
 769
 770                 ctrl_ext = BP10G_READ_REG(pbpctl_dev, I2CCTL);
 771                 ctrl = BP10G_READ_REG(pbpctl_dev_c, ESDP);
 772                 /* DATA 0 CLK 0 */
 773                 /* BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext&~(BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9))); */
 774                 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
 775                                 (ctrl_ext & ~BP10G_MDIO_DATA_OUT9));
 776                 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
 777                                 ((ctrl | BP10G_MCLK_DIR_OUT9) &
 778                                  ~(BP10G_MCLK_DATA_OUT9)));
 779
 780         } else if (pbpctl_dev->bp_fiber5) {
 781                 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL);
 782                 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
 783                                                        BPCTLI_CTRL_EXT_MCLK_DIR5
 784                                                        |
 785                                                        BPCTLI_CTRL_EXT_MDIO_DIR5)
 786                                                       &
 787                                                       ~
 788                                                       (BPCTLI_CTRL_EXT_MDIO_DATA5
 789                                                        |
 790                                                        BPCTLI_CTRL_EXT_MCLK_DATA5)));
 791         } else if (pbpctl_dev->bp_i80) {
 792                 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL);
 793                 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
 794                 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
 795                                                        BPCTLI_CTRL_EXT_MDIO_DIR80)
 796                                                       &
 797                                                       ~BPCTLI_CTRL_EXT_MDIO_DATA80));
 798                 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
 799                                    ((ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80) &
 800                                     ~BPCTLI_CTRL_EXT_MCLK_DATA80));
 801
 802         } else if (pbpctl_dev->bp_540) {
 803                 ctrl = ctrl_ext = BP10G_READ_REG(pbpctl_dev, ESDP);
 804                 BP10G_WRITE_REG(pbpctl_dev, ESDP, ((ctrl |
 805                                                     BP540_MDIO_DIR |
 806                                                     BP540_MCLK_DIR) &
 807                                                    ~(BP540_MDIO_DATA |
 808                                                      BP540_MCLK_DATA)));
 809
 810         } else if (pbpctl_dev->bp_10gb) {
 811                 ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
 812
 813                 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
 814                                  (ctrl_ext | BP10GB_MDIO_CLR | BP10GB_MCLK_CLR)
 815                                  & ~(BP10GB_MCLK_DIR | BP10GB_MDIO_DIR |
 816                                      BP10GB_MDIO_SET | BP10GB_MCLK_SET));
 817
 818         } else if (!pbpctl_dev->bp_10g) {
 819
 820                 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
 821                 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
 822                                                            BPCTLI_CTRL_EXT_MCLK_DIR
 823                                                            |
 824                                                            BPCTLI_CTRL_EXT_MDIO_DIR)
 825                                                           &
 826                                                           ~
 827                                                           (BPCTLI_CTRL_EXT_MDIO_DATA
 828                                                            |
 829                                                            BPCTLI_CTRL_EXT_MCLK_DATA)));
 830         } else {
 831                 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
 832                 ctrl_ext = BP10G_READ_REG(pbpctl_dev, EODSDP);
 833                 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
 834                                 (ctrl_ext &
 835                                  ~(BP10G_MCLK_DATA_OUT | BP10G_MDIO_DATA_OUT)));
 836         }
 837         usec_delay(CMND_INTERVAL);
 838
 839         /*send sync cmd */
 840         write_pulse(pbpctl_dev, ctrl_ext, SYNC_CMD_VAL, SYNC_CMD_LEN);
 841         /*send wr cmd */
 842         write_pulse(pbpctl_dev, ctrl_ext, WR_CMD_VAL, WR_CMD_LEN);
 843         write_pulse(pbpctl_dev, ctrl_ext, addr, ADDR_CMD_LEN);
 844
 845         /*write data */
 846         write_pulse(pbpctl_dev, ctrl_ext, value, WR_DATA_LEN);
 847         if (pbpctl_dev->bp_10g9) {
 848                 /*BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext&~(BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9))); */
 849                 /* DATA 0 CLK 0 */
 850                 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
 851                                 (ctrl_ext & ~BP10G_MDIO_DATA_OUT9));
 852                 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
 853                                 ((ctrl | BP10G_MCLK_DIR_OUT9) &
 854                                  ~(BP10G_MCLK_DATA_OUT9)));
 855
 856         } else if (pbpctl_dev->bp_fiber5) {
 857                 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
 858                                                        BPCTLI_CTRL_EXT_MCLK_DIR5
 859                                                        |
 860                                                        BPCTLI_CTRL_EXT_MDIO_DIR5)
 861                                                       &
 862                                                       ~
 863                                                       (BPCTLI_CTRL_EXT_MDIO_DATA5
 864                                                        |
 865                                                        BPCTLI_CTRL_EXT_MCLK_DATA5)));
 866         } else if (pbpctl_dev->bp_i80) {
 867                 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
 868                                                        BPCTLI_CTRL_EXT_MDIO_DIR80)
 869                                                       &
 870                                                       ~BPCTLI_CTRL_EXT_MDIO_DATA80));
 871                 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
 872                                    ((ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80) &
 873                                     ~BPCTLI_CTRL_EXT_MCLK_DATA80));
 874         } else if (pbpctl_dev->bp_540) {
 875                 BP10G_WRITE_REG(pbpctl_dev, ESDP, ((ctrl |
 876                                                     BP540_MDIO_DIR |
 877                                                     BP540_MCLK_DIR) &
 878                                                    ~(BP540_MDIO_DATA |
 879                                                      BP540_MCLK_DATA)));
 880         } else if (pbpctl_dev->bp_10gb) {
 881                 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
 882                                  (ctrl_ext | BP10GB_MDIO_CLR | BP10GB_MCLK_CLR)
 883                                  & ~(BP10GB_MCLK_DIR | BP10GB_MDIO_DIR |
 884                                      BP10GB_MDIO_SET | BP10GB_MCLK_SET));
 885
 886         } else if (!pbpctl_dev->bp_10g)
 887
 888                 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
 889                                                            BPCTLI_CTRL_EXT_MCLK_DIR
 890                                                            |
 891                                                            BPCTLI_CTRL_EXT_MDIO_DIR)
 892                                                           &
 893                                                           ~
 894                                                           (BPCTLI_CTRL_EXT_MDIO_DATA
 895                                                            |
 896                                                            BPCTLI_CTRL_EXT_MCLK_DATA)));
 897         else {
 898                 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
 899                                 (ctrl_ext &
 900                                  ~(BP10G_MCLK_DATA_OUT | BP10G_MDIO_DATA_OUT)));
 901
 902         }
 903
 904         usec_delay(CMND_INTERVAL * 4);
 905
 906         if ((pbpctl_dev->wdt_status == WDT_STATUS_EN) &&
 907             (pbpctl_dev->bp_ext_ver < PXG4BPFI_VER) && (addr == CMND_REG_ADDR))
 908                 pbpctl_dev->bypass_wdt_on_time = jiffies;
 909 #ifdef BP_SYNC_FLAG
 910         spin_unlock_irqrestore(&pbpctl_dev->bypass_wr_lock, flags);
 911 #else
 912         atomic_set(&pbpctl_dev->wdt_busy, 0);
 913 #endif
 914
 915 }
 916
 917 static void write_data(struct bpctl_dev *pbpctl_dev, unsigned char value)
 918 {
 919         write_reg(pbpctl_dev, value, CMND_REG_ADDR);
 920 }
 921
 922 static int read_reg(struct bpctl_dev *pbpctl_dev, unsigned char addr)
 923 {
 924         uint32_t ctrl_ext = 0, ctrl = 0, ctrl_value = 0;
 925         struct bpctl_dev *pbpctl_dev_c = NULL;
 926
 927 #ifdef BP_SYNC_FLAG
 928         unsigned long flags;
 929         spin_lock_irqsave(&pbpctl_dev->bypass_wr_lock, flags);
 930 #else
 931         atomic_set(&pbpctl_dev->wdt_busy, 1);
 932 #endif
 933         if (pbpctl_dev->bp_10g9) {
 934                 pbpctl_dev_c = get_status_port_fn(pbpctl_dev);
 935                 if (!pbpctl_dev_c)
 936                         return -1;
 937         }
 938
 939         if (pbpctl_dev->bp_10g9) {
 940                 ctrl_ext = BP10G_READ_REG(pbpctl_dev, I2CCTL);
 941                 ctrl = BP10G_READ_REG(pbpctl_dev_c, ESDP);
 942
 943                 /* BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext&~(BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9))); */
 944                 /* DATA 0 CLK 0 */
 945                 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
 946                                 (ctrl_ext & ~BP10G_MDIO_DATA_OUT9));
 947                 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
 948                                 ((ctrl | BP10G_MCLK_DIR_OUT9) &
 949                                  ~(BP10G_MCLK_DATA_OUT9)));
 950
 951         } else if (pbpctl_dev->bp_fiber5) {
 952                 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL);
 953
 954                 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
 955                                                        BPCTLI_CTRL_EXT_MCLK_DIR5
 956                                                        |
 957                                                        BPCTLI_CTRL_EXT_MDIO_DIR5)
 958                                                       &
 959                                                       ~
 960                                                       (BPCTLI_CTRL_EXT_MDIO_DATA5
 961                                                        |
 962                                                        BPCTLI_CTRL_EXT_MCLK_DATA5)));
 963         } else if (pbpctl_dev->bp_i80) {
 964                 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL);
 965                 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
 966
 967                 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
 968                                                        BPCTLI_CTRL_EXT_MDIO_DIR80)
 969                                                       &
 970                                                       ~BPCTLI_CTRL_EXT_MDIO_DATA80));
 971                 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
 972                                    ((ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80) &
 973                                     ~BPCTLI_CTRL_EXT_MCLK_DATA80));
 974         } else if (pbpctl_dev->bp_540) {
 975                 ctrl_ext = BP10G_READ_REG(pbpctl_dev, ESDP);
 976                 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
 977
 978                 BP10G_WRITE_REG(pbpctl_dev, ESDP, ((ctrl | BP540_MCLK_DIR |
 979                                                     BP540_MDIO_DIR) &
 980                                                    ~(BP540_MDIO_DATA |
 981                                                      BP540_MCLK_DATA)));
 982         } else if (pbpctl_dev->bp_10gb) {
 983                 ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
 984
 985                 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
 986                                  (ctrl_ext | BP10GB_MDIO_CLR | BP10GB_MCLK_CLR)
 987                                  & ~(BP10GB_MCLK_DIR | BP10GB_MDIO_DIR |
 988                                      BP10GB_MDIO_SET | BP10GB_MCLK_SET));
 989 #if 0
 990
 991                 /*BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO, (ctrl_ext | BP10GB_MCLK_DIR | BP10GB_MDIO_DIR|
 992                    BP10GB_MCLK_CLR|BP10GB_MDIO_CLR));
 993                    ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
 994                    printk("1reg=%x\n", ctrl_ext); */
 995
 996                 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO, ((ctrl_ext |
 997                                                               BP10GB_MCLK_SET |
 998                                                               BP10GB_MDIO_CLR))
 999                                  & ~(BP10GB_MCLK_CLR | BP10GB_MDIO_SET |
1000                                      BP10GB_MCLK_DIR | BP10GB_MDIO_DIR));
1001
1002                 /*   bnx2x_set_spio(pbpctl_dev, 5, MISC_REGISTERS_SPIO_OUTPUT_LOW);
1003                    bnx2x_set_spio(pbpctl_dev, 4, MISC_REGISTERS_SPIO_OUTPUT_LOW);
1004                    bnx2x_set_spio(pbpctl_dev, 4, MISC_REGISTERS_SPIO_INPUT_HI_Z); */
1005
1006                 ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
1007
1008                 printk("2reg=%x\n", ctrl_ext);
1009
1010 #ifdef BP_SYNC_FLAG
1011                 spin_unlock_irqrestore(&pbpctl_dev->bypass_wr_lock, flags);
1012 #else
1013                 atomic_set(&pbpctl_dev->wdt_busy, 0);
1014 #endif
1015
1016                 return 0;
1017
1018 #endif
1019
1020         } else if (!pbpctl_dev->bp_10g) {
1021
1022                 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1023
1024                 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1025                                                            BPCTLI_CTRL_EXT_MCLK_DIR
1026                                                            |
1027                                                            BPCTLI_CTRL_EXT_MDIO_DIR)
1028                                                           &
1029                                                           ~
1030                                                           (BPCTLI_CTRL_EXT_MDIO_DATA
1031                                                            |
1032                                                            BPCTLI_CTRL_EXT_MCLK_DATA)));
1033         } else {
1034
1035                 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
1036                 ctrl_ext = BP10G_READ_REG(pbpctl_dev, EODSDP);
1037                 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
1038                                 (ctrl_ext &
1039                                  ~(BP10G_MCLK_DATA_OUT | BP10G_MDIO_DATA_OUT)));
1040
1041         }
1042
1043         usec_delay(CMND_INTERVAL);
1044
1045         /*send sync cmd */
1046         write_pulse(pbpctl_dev, ctrl_ext, SYNC_CMD_VAL, SYNC_CMD_LEN);
1047         /*send rd cmd */
1048         write_pulse(pbpctl_dev, ctrl_ext, RD_CMD_VAL, RD_CMD_LEN);
1049         /*send addr */
1050         write_pulse(pbpctl_dev, ctrl_ext, addr, ADDR_CMD_LEN);
1051         /*read data */
1052         /* zero */
1053         if (pbpctl_dev->bp_10g9) {
1054                 /* DATA 0 CLK 1 */
1055                 /*BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext|BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9)); */
1056                 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
1057                                 (ctrl_ext | BP10G_MDIO_DATA_OUT9));
1058                 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
1059                                 (ctrl | BP10G_MCLK_DATA_OUT9 |
1060                                  BP10G_MCLK_DIR_OUT9));
1061
1062         } else if (pbpctl_dev->bp_fiber5) {
1063                 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1064                                                        BPCTLI_CTRL_EXT_MCLK_DIR5
1065                                                        |
1066                                                        BPCTLI_CTRL_EXT_MCLK_DATA5)
1067                                                       &
1068                                                       ~
1069                                                       (BPCTLI_CTRL_EXT_MDIO_DIR5
1070                                                        |
1071                                                        BPCTLI_CTRL_EXT_MDIO_DATA5)));
1072
1073         } else if (pbpctl_dev->bp_i80) {
1074                 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
1075                                    (ctrl_ext &
1076                                     ~(BPCTLI_CTRL_EXT_MDIO_DATA80 |
1077                                       BPCTLI_CTRL_EXT_MDIO_DIR80)));
1078                 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
1079                                    (ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80 |
1080                                     BPCTLI_CTRL_EXT_MCLK_DATA80));
1081
1082         } else if (pbpctl_dev->bp_540) {
1083                 BP10G_WRITE_REG(pbpctl_dev, ESDP,
1084                                 (((ctrl | BP540_MDIO_DIR | BP540_MCLK_DIR |
1085                                    BP540_MCLK_DATA) & ~BP540_MDIO_DATA)));
1086
1087         } else if (pbpctl_dev->bp_10gb) {
1088
1089                 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
1090                                  (ctrl_ext | BP10GB_MDIO_DIR | BP10GB_MCLK_SET)
1091                                  & ~(BP10GB_MCLK_DIR | BP10GB_MDIO_SET |
1092                                      BP10GB_MDIO_CLR | BP10GB_MCLK_CLR));
1093
1094         } else if (!pbpctl_dev->bp_10g)
1095                 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1096                                                            BPCTLI_CTRL_EXT_MCLK_DIR
1097                                                            |
1098                                                            BPCTLI_CTRL_EXT_MCLK_DATA)
1099                                                           &
1100                                                           ~
1101                                                           (BPCTLI_CTRL_EXT_MDIO_DIR
1102                                                            |
1103                                                            BPCTLI_CTRL_EXT_MDIO_DATA)));
1104         else {
1105
1106                 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
1107                                 (ctrl_ext | BP10G_MCLK_DATA_OUT |
1108                                  BP10G_MDIO_DATA_OUT));
1109
1110
1111         }
1112         usec_delay(PULSE_TIME);
1113
1114         ctrl_value = read_pulse(pbpctl_dev, ctrl_ext, RD_DATA_LEN);
1115
1116         if (pbpctl_dev->bp_10g9) {
1117                 ctrl_ext = BP10G_READ_REG(pbpctl_dev, I2CCTL);
1118                 ctrl = BP10G_READ_REG(pbpctl_dev_c, ESDP);
1119
1120                 /* BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext&~(BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9))); */
1121                 /* DATA 0 CLK 0 */
1122                 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
1123                                 (ctrl_ext & ~BP10G_MDIO_DATA_OUT9));
1124                 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
1125                                 ((ctrl | BP10G_MCLK_DIR_OUT9) &
1126                                  ~(BP10G_MCLK_DATA_OUT9)));
1127
1128         } else if (pbpctl_dev->bp_fiber5) {
1129                 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1130                                                        BPCTLI_CTRL_EXT_MCLK_DIR5
1131                                                        |
1132                                                        BPCTLI_CTRL_EXT_MDIO_DIR5)
1133                                                       &
1134                                                       ~
1135                                                       (BPCTLI_CTRL_EXT_MDIO_DATA5
1136                                                        |
1137                                                        BPCTLI_CTRL_EXT_MCLK_DATA5)));
1138         } else if (pbpctl_dev->bp_i80) {
1139                 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1140                                                        BPCTLI_CTRL_EXT_MDIO_DIR80)
1141                                                       &
1142                                                       ~BPCTLI_CTRL_EXT_MDIO_DATA80));
1143                 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
1144                                    ((ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80) &
1145                                     ~BPCTLI_CTRL_EXT_MCLK_DATA80));
1146
1147         } else if (pbpctl_dev->bp_540) {
1148                 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
1149                 BP10G_WRITE_REG(pbpctl_dev, ESDP, ((ctrl | BP540_MCLK_DIR |
1150                                                     BP540_MDIO_DIR) &
1151                                                    ~(BP540_MDIO_DATA |
1152                                                      BP540_MCLK_DATA)));
1153
1154         } else if (pbpctl_dev->bp_10gb) {
1155                 ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
1156                 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
1157                                  (ctrl_ext | BP10GB_MDIO_CLR | BP10GB_MCLK_CLR)
1158                                  & ~(BP10GB_MCLK_DIR | BP10GB_MDIO_DIR |
1159                                      BP10GB_MDIO_SET | BP10GB_MCLK_SET));
1160
1161         } else if (!pbpctl_dev->bp_10g) {
1162                 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1163                                                            BPCTLI_CTRL_EXT_MCLK_DIR
1164                                                            |
1165                                                            BPCTLI_CTRL_EXT_MDIO_DIR)
1166                                                           &
1167                                                           ~
1168                                                           (BPCTLI_CTRL_EXT_MDIO_DATA
1169                                                            |
1170                                                            BPCTLI_CTRL_EXT_MCLK_DATA)));
1171         } else {
1172
1173                 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
1174                 ctrl_ext = BP10G_READ_REG(pbpctl_dev, EODSDP);
1175                 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
1176                                 (ctrl_ext &
1177                                  ~(BP10G_MCLK_DATA_OUT | BP10G_MDIO_DATA_OUT)));
1178
1179         }
1180
1181         usec_delay(CMND_INTERVAL * 4);
1182 #ifdef BP_SYNC_FLAG
1183         spin_unlock_irqrestore(&pbpctl_dev->bypass_wr_lock, flags);
1184 #else
1185         atomic_set(&pbpctl_dev->wdt_busy, 0);
1186 #endif
1187
1188         return ctrl_value;
1189 }
1190
1191 static int wdt_pulse(struct bpctl_dev *pbpctl_dev)
1192 {
1193         uint32_t ctrl_ext = 0, ctrl = 0;
1194         struct bpctl_dev *pbpctl_dev_c = NULL;
1195
1196 #ifdef BP_SYNC_FLAG
1197         unsigned long flags;
1198
1199         spin_lock_irqsave(&pbpctl_dev->bypass_wr_lock, flags);
1200 #else
1201
1202         if ((atomic_read(&pbpctl_dev->wdt_busy)) == 1)
1203                 return -1;
1204 #endif
1205         if (pbpctl_dev->bp_10g9) {
1206                 pbpctl_dev_c = get_status_port_fn(pbpctl_dev);
1207                 if (!pbpctl_dev_c)
1208                         return -1;
1209         }
1210
1211         if (pbpctl_dev->bp_10g9) {
1212                 ctrl_ext = BP10G_READ_REG(pbpctl_dev, I2CCTL);
1213                 ctrl = BP10G_READ_REG(pbpctl_dev_c, ESDP);
1214
1215                 /* BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext&~(BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9))); */
1216                 /* DATA 0 CLK 0 */
1217                 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
1218                                 (ctrl_ext & ~BP10G_MDIO_DATA_OUT9));
1219                 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
1220                                 ((ctrl | BP10G_MCLK_DIR_OUT9) &
1221                                  ~(BP10G_MCLK_DATA_OUT9)));
1222
1223         } else if (pbpctl_dev->bp_fiber5) {
1224                 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL);
1225                 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1226                                                        BPCTLI_CTRL_EXT_MCLK_DIR5
1227                                                        |
1228                                                        BPCTLI_CTRL_EXT_MDIO_DIR5)
1229                                                       &
1230                                                       ~
1231                                                       (BPCTLI_CTRL_EXT_MDIO_DATA5
1232                                                        |
1233                                                        BPCTLI_CTRL_EXT_MCLK_DATA5)));
1234         } else if (pbpctl_dev->bp_i80) {
1235                 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL);
1236                 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1237                 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1238                                                        BPCTLI_CTRL_EXT_MDIO_DIR80)
1239                                                       &
1240                                                       ~BPCTLI_CTRL_EXT_MDIO_DATA80));
1241                 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
1242                                    ((ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80) &
1243                                     ~BPCTLI_CTRL_EXT_MCLK_DATA80));
1244         } else if (pbpctl_dev->bp_540) {
1245                 ctrl_ext = ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
1246                 BP10G_WRITE_REG(pbpctl_dev, ESDP, ((ctrl | BP540_MCLK_DIR |
1247                                                     BP540_MDIO_DIR) &
1248                                                    ~(BP540_MDIO_DATA |
1249                                                      BP540_MCLK_DATA)));
1250         } else if (pbpctl_dev->bp_10gb) {
1251                 ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
1252                 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
1253                                  (ctrl_ext | BP10GB_MDIO_CLR | BP10GB_MCLK_CLR)
1254                                  & ~(BP10GB_MCLK_DIR | BP10GB_MDIO_DIR |
1255                                      BP10GB_MDIO_SET | BP10GB_MCLK_SET));
1256
1257         } else if (!pbpctl_dev->bp_10g) {
1258
1259                 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1260                 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1261                                                            BPCTLI_CTRL_EXT_MCLK_DIR
1262                                                            |
1263                                                            BPCTLI_CTRL_EXT_MDIO_DIR)
1264                                                           &
1265                                                           ~
1266                                                           (BPCTLI_CTRL_EXT_MDIO_DATA
1267                                                            |
1268                                                            BPCTLI_CTRL_EXT_MCLK_DATA)));
1269         } else {
1270
1271                 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
1272                 ctrl_ext = BP10G_READ_REG(pbpctl_dev, EODSDP);
1273                 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
1274                                 (ctrl_ext &
1275                                  ~(BP10G_MCLK_DATA_OUT | BP10G_MDIO_DATA_OUT)));
1276
1277         }
1278         if (pbpctl_dev->bp_10g9) {
1279                 /*   BP10G_WRITE_REG(pbpctl_dev, I2CCTL, ((ctrl_ext|BP10G_MCLK_DATA_OUT9)&~BP10G_MDIO_DATA_OUT9)); */
1280                 /* DATA 0 CLK 1 */
1281                 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
1282                                 (ctrl_ext & ~BP10G_MDIO_DATA_OUT9));
1283                 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
1284                                 (ctrl | BP10G_MCLK_DATA_OUT9 |
1285                                  BP10G_MCLK_DIR_OUT9));
1286
1287         } else if (pbpctl_dev->bp_fiber5) {
1288                 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1289                                                        BPCTLI_CTRL_EXT_MCLK_DIR5
1290                                                        |
1291                                                        BPCTLI_CTRL_EXT_MDIO_DIR5
1292                                                        |
1293                                                        BPCTLI_CTRL_EXT_MCLK_DATA5)
1294                                                       &
1295                                                       ~
1296                                                       (BPCTLI_CTRL_EXT_MDIO_DATA5)));
1297         } else if (pbpctl_dev->bp_i80) {
1298                 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1299                                                        BPCTLI_CTRL_EXT_MDIO_DIR80)
1300                                                       &
1301                                                       ~BPCTLI_CTRL_EXT_MDIO_DATA80));
1302                 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
1303                                    (ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80 |
1304                                     BPCTLI_CTRL_EXT_MCLK_DATA80));
1305
1306         } else if (pbpctl_dev->bp_540) {
1307                 BP10G_WRITE_REG(pbpctl_dev, ESDP, ((ctrl |
1308                                                     BP540_MDIO_DIR |
1309                                                     BP540_MCLK_DIR |
1310                                                     BP540_MCLK_DATA) &
1311                                                    ~BP540_MDIO_DATA));
1312
1313         } else if (pbpctl_dev->bp_10gb) {
1314                 ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
1315
1316                 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
1317                                  (ctrl_ext | BP10GB_MDIO_CLR | BP10GB_MCLK_SET)
1318                                  & ~(BP10GB_MCLK_DIR | BP10GB_MDIO_DIR |
1319                                      BP10GB_MDIO_SET | BP10GB_MCLK_CLR));
1320
1321         } else if (!pbpctl_dev->bp_10g)
1322                 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1323                                                            BPCTLI_CTRL_EXT_MCLK_DIR
1324                                                            |
1325                                                            BPCTLI_CTRL_EXT_MDIO_DIR
1326                                                            |
1327                                                            BPCTLI_CTRL_EXT_MCLK_DATA)
1328                                                           &
1329                                                           ~
1330                                                           (BPCTLI_CTRL_EXT_MDIO_DATA)));
1331         else {
1332
1333                 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
1334                                 ((ctrl_ext | BP10G_MCLK_DATA_OUT) &
1335                                  ~BP10G_MDIO_DATA_OUT));
1336
1337         }
1338
1339         usec_delay(WDT_INTERVAL);
1340         if (pbpctl_dev->bp_10g9) {
1341                 /* BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext&~(BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9))); */
1342                 /* DATA 0 CLK 0 */
1343                 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
1344                                 (ctrl_ext & ~BP10G_MDIO_DATA_OUT9));
1345                 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
1346                                 ((ctrl | BP10G_MCLK_DIR_OUT9) &
1347                                  ~(BP10G_MCLK_DATA_OUT9)));
1348
1349         } else if (pbpctl_dev->bp_fiber5) {
1350                 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1351                                                        BPCTLI_CTRL_EXT_MCLK_DIR5
1352                                                        |
1353                                                        BPCTLI_CTRL_EXT_MDIO_DIR5)
1354                                                       &
1355                                                       ~
1356                                                       (BPCTLI_CTRL_EXT_MCLK_DATA5
1357                                                        |
1358                                                        BPCTLI_CTRL_EXT_MDIO_DATA5)));
1359         } else if (pbpctl_dev->bp_i80) {
1360                 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1361                                                        BPCTLI_CTRL_EXT_MDIO_DIR80)
1362                                                       &
1363                                                       ~BPCTLI_CTRL_EXT_MDIO_DATA80));
1364                 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
1365                                    ((ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80) &
1366                                     ~BPCTLI_CTRL_EXT_MCLK_DATA80));
1367
1368         } else if (pbpctl_dev->bp_540) {
1369                 BP10G_WRITE_REG(pbpctl_dev, ESDP, ((ctrl | BP540_MCLK_DIR |
1370                                                     BP540_MDIO_DIR) &
1371                                                    ~(BP540_MDIO_DATA |
1372                                                      BP540_MCLK_DATA)));
1373
1374         } else if (pbpctl_dev->bp_10gb) {
1375                 ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
1376                 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
1377                                  (ctrl_ext | BP10GB_MDIO_CLR | BP10GB_MCLK_CLR)
1378                                  & ~(BP10GB_MCLK_DIR | BP10GB_MDIO_DIR |
1379                                      BP10GB_MDIO_SET | BP10GB_MCLK_SET));
1380
1381         } else if (!pbpctl_dev->bp_10g)
1382                 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1383                                                            BPCTLI_CTRL_EXT_MCLK_DIR
1384                                                            |
1385                                                            BPCTLI_CTRL_EXT_MDIO_DIR)
1386                                                           &
1387                                                           ~
1388                                                           (BPCTLI_CTRL_EXT_MCLK_DATA
1389                                                            |
1390                                                            BPCTLI_CTRL_EXT_MDIO_DATA)));
1391         else {
1392
1393                 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
1394                                 (ctrl_ext &
1395                                  ~(BP10G_MCLK_DATA_OUT | BP10G_MDIO_DATA_OUT)));
1396         }
1397         if ((pbpctl_dev->wdt_status == WDT_STATUS_EN))
1398                 /*&& (pbpctl_dev->bp_ext_ver<PXG4BPFI_VER) */
1399                 pbpctl_dev->bypass_wdt_on_time = jiffies;
1400 #ifdef BP_SYNC_FLAG
1401         spin_unlock_irqrestore(&pbpctl_dev->bypass_wr_lock, flags);
1402 #endif
1403         usec_delay(CMND_INTERVAL * 4);
1404         return 0;
1405 }
1406
1407 static void data_pulse(struct bpctl_dev *pbpctl_dev, unsigned char value)
1408 {
1409
1410         uint32_t ctrl_ext = 0;
1411 #ifdef BP_SYNC_FLAG
1412         unsigned long flags;
1413 #endif
1414         wdt_time_left(pbpctl_dev);
1415 #ifdef BP_SYNC_FLAG
1416         spin_lock_irqsave(&pbpctl_dev->bypass_wr_lock, flags);
1417 #else
1418         atomic_set(&pbpctl_dev->wdt_busy, 1);
1419 #endif
1420
1421         ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1422         BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1423                                                    BPCTLI_CTRL_EXT_SDP6_DIR |
1424                                                    BPCTLI_CTRL_EXT_SDP7_DIR) &
1425                                                   ~(BPCTLI_CTRL_EXT_SDP6_DATA |
1426                                                     BPCTLI_CTRL_EXT_SDP7_DATA)));
1427
1428         usec_delay(INIT_CMND_INTERVAL);
1429         BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1430                                                    BPCTLI_CTRL_EXT_SDP6_DIR |
1431                                                    BPCTLI_CTRL_EXT_SDP7_DIR |
1432                                                    BPCTLI_CTRL_EXT_SDP6_DATA) &
1433                                                   ~
1434                                                   (BPCTLI_CTRL_EXT_SDP7_DATA)));
1435         usec_delay(INIT_CMND_INTERVAL);
1436
1437         while (value) {
1438                 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ctrl_ext |
1439                                    BPCTLI_CTRL_EXT_SDP6_DIR |
1440                                    BPCTLI_CTRL_EXT_SDP7_DIR |
1441                                    BPCTLI_CTRL_EXT_SDP6_DATA |
1442                                    BPCTLI_CTRL_EXT_SDP7_DATA);
1443                 usec_delay(PULSE_INTERVAL);
1444                 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1445                                                            BPCTLI_CTRL_EXT_SDP6_DIR
1446                                                            |
1447                                                            BPCTLI_CTRL_EXT_SDP7_DIR
1448                                                            |
1449                                                            BPCTLI_CTRL_EXT_SDP6_DATA)
1450                                                           &
1451                                                           ~BPCTLI_CTRL_EXT_SDP7_DATA));
1452                 usec_delay(PULSE_INTERVAL);
1453                 value--;
1454
1455         }
1456         usec_delay(INIT_CMND_INTERVAL - PULSE_INTERVAL);
1457         BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1458                                                    BPCTLI_CTRL_EXT_SDP6_DIR |
1459                                                    BPCTLI_CTRL_EXT_SDP7_DIR) &
1460                                                   ~(BPCTLI_CTRL_EXT_SDP6_DATA |
1461                                                     BPCTLI_CTRL_EXT_SDP7_DATA)));
1462         usec_delay(WDT_TIME_CNT);
1463         if (pbpctl_dev->wdt_status == WDT_STATUS_EN)
1464                 pbpctl_dev->bypass_wdt_on_time = jiffies;
1465 #ifdef BP_SYNC_FLAG
1466         spin_unlock_irqrestore(&pbpctl_dev->bypass_wr_lock, flags);
1467 #else
1468         atomic_set(&pbpctl_dev->wdt_busy, 0);
1469 #endif
1470
1471 }
1472
1473 static int send_wdt_pulse(struct bpctl_dev *pbpctl_dev)
1474 {
1475         uint32_t ctrl_ext = 0;
1476
1477 #ifdef BP_SYNC_FLAG
1478         unsigned long flags;
1479
1480         spin_lock_irqsave(&pbpctl_dev->bypass_wr_lock, flags);
1481 #else
1482
1483         if ((atomic_read(&pbpctl_dev->wdt_busy)) == 1)
1484                 return -1;
1485 #endif
1486         wdt_time_left(pbpctl_dev);
1487         ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1488
1489         BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ctrl_ext |     /* 1 */
1490                            BPCTLI_CTRL_EXT_SDP7_DIR |
1491                            BPCTLI_CTRL_EXT_SDP7_DATA);
1492         usec_delay(PULSE_INTERVAL);
1493         BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |   /* 0 */
1494                                                    BPCTLI_CTRL_EXT_SDP7_DIR) &
1495                                                   ~BPCTLI_CTRL_EXT_SDP7_DATA));
1496
1497         usec_delay(PULSE_INTERVAL);
1498         if (pbpctl_dev->wdt_status == WDT_STATUS_EN)
1499                 pbpctl_dev->bypass_wdt_on_time = jiffies;
1500 #ifdef BP_SYNC_FLAG
1501         spin_unlock_irqrestore(&pbpctl_dev->bypass_wr_lock, flags);
1502 #endif
1503
1504         return 0;
1505 }
1506
1507 void send_bypass_clear_pulse(struct bpctl_dev *pbpctl_dev, unsigned int value)
1508 {
1509         uint32_t ctrl_ext = 0;
1510
1511         ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1512         BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |   /* 0 */
1513                                                    BPCTLI_CTRL_EXT_SDP6_DIR) &
1514                                                   ~BPCTLI_CTRL_EXT_SDP6_DATA));
1515
1516         usec_delay(PULSE_INTERVAL);
1517         while (value) {
1518                 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ctrl_ext |     /* 1 */
1519                                    BPCTLI_CTRL_EXT_SDP6_DIR |
1520                                    BPCTLI_CTRL_EXT_SDP6_DATA);
1521                 usec_delay(PULSE_INTERVAL);
1522                 value--;
1523         }
1524         BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |   /* 0 */
1525                                                    BPCTLI_CTRL_EXT_SDP6_DIR) &
1526                                                   ~BPCTLI_CTRL_EXT_SDP6_DATA));
1527         usec_delay(PULSE_INTERVAL);
1528 }
1529
1530 /*  #endif  OLD_FW */
1531 #ifdef BYPASS_DEBUG
1532
1533 int pulse_set_fn(struct bpctl_dev *pbpctl_dev, unsigned int counter)
1534 {
1535         uint32_t ctrl_ext = 0;
1536
1537         if (!pbpctl_dev)
1538                 return -1;
1539
1540         ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1541         write_pulse_1(pbpctl_dev, ctrl_ext, counter, counter);
1542
1543         pbpctl_dev->bypass_wdt_status = 0;
1544         if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
1545                 write_pulse_1(pbpctl_dev, ctrl_ext, counter, counter);
1546         } else {
1547                 wdt_time_left(pbpctl_dev);
1548                 if (pbpctl_dev->wdt_status == WDT_STATUS_EN) {
1549                         pbpctl_dev->wdt_status = 0;
1550                         data_pulse(pbpctl_dev, counter);
1551                         pbpctl_dev->wdt_status = WDT_STATUS_EN;
1552                         pbpctl_dev->bypass_wdt_on_time = jiffies;
1553
1554                 } else
1555                         data_pulse(pbpctl_dev, counter);
1556         }
1557
1558         return 0;
1559 }
1560
1561 int zero_set_fn(struct bpctl_dev *pbpctl_dev)
1562 {
1563         uint32_t ctrl_ext = 0, ctrl_value = 0;
1564         if (!pbpctl_dev)
1565                 return -1;
1566
1567         if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
1568                 printk("zero_set");
1569
1570                 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1571
1572                 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1573                                                            BPCTLI_CTRL_EXT_MCLK_DIR)
1574                                                           &
1575                                                           ~
1576                                                           (BPCTLI_CTRL_EXT_MCLK_DATA
1577                                                            |
1578                                                            BPCTLI_CTRL_EXT_MDIO_DIR
1579                                                            |
1580                                                            BPCTLI_CTRL_EXT_MDIO_DATA)));
1581
1582         }
1583         return ctrl_value;
1584 }
1585
1586 int pulse_get2_fn(struct bpctl_dev *pbpctl_dev)
1587 {
1588         uint32_t ctrl_ext = 0, ctrl_value = 0;
1589         if (!pbpctl_dev)
1590                 return -1;
1591
1592         if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
1593                 printk("pulse_get_fn\n");
1594                 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1595                 ctrl_value = read_pulse_2(pbpctl_dev, ctrl_ext);
1596                 printk("read:%d\n", ctrl_value);
1597         }
1598         return ctrl_value;
1599 }
1600
1601 int pulse_get1_fn(struct bpctl_dev *pbpctl_dev)
1602 {
1603         uint32_t ctrl_ext = 0, ctrl_value = 0;
1604         if (!pbpctl_dev)
1605                 return -1;
1606
1607         if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
1608
1609                 printk("pulse_get_fn\n");
1610
1611                 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1612                 ctrl_value = read_pulse_1(pbpctl_dev, ctrl_ext);
1613                 printk("read:%d\n", ctrl_value);
1614         }
1615         return ctrl_value;
1616 }
1617
1618 int gpio6_set_fn(struct bpctl_dev *pbpctl_dev)
1619 {
1620         uint32_t ctrl_ext = 0;
1621
1622         ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1623         BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ctrl_ext |
1624                            BPCTLI_CTRL_EXT_SDP6_DIR |
1625                            BPCTLI_CTRL_EXT_SDP6_DATA);
1626         return 0;
1627 }
1628
1629 int gpio7_set_fn(struct bpctl_dev *pbpctl_dev)
1630 {
1631         uint32_t ctrl_ext = 0;
1632
1633         ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1634         BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ctrl_ext |
1635                            BPCTLI_CTRL_EXT_SDP7_DIR |
1636                            BPCTLI_CTRL_EXT_SDP7_DATA);
1637         return 0;
1638 }
1639
1640 int gpio7_clear_fn(struct bpctl_dev *pbpctl_dev)
1641 {
1642         uint32_t ctrl_ext = 0;
1643
1644         ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1645         BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1646                                                    BPCTLI_CTRL_EXT_SDP7_DIR) &
1647                                                   ~BPCTLI_CTRL_EXT_SDP7_DATA));
1648         return 0;
1649 }
1650
1651 int gpio6_clear_fn(struct bpctl_dev *pbpctl_dev)
1652 {
1653         uint32_t ctrl_ext = 0;
1654
1655         ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1656         BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1657                                                    BPCTLI_CTRL_EXT_SDP6_DIR) &
1658                                                   ~BPCTLI_CTRL_EXT_SDP6_DATA));
1659         return 0;
1660 }
1661 #endif                          /*BYPASS_DEBUG */
1662
1663 static struct bpctl_dev *lookup_port(struct bpctl_dev *dev)
1664 {
1665         struct bpctl_dev *p;
1666         int n;
1667         for (n = 0, p = bpctl_dev_arr; n < device_num && p->pdev; n++) {
1668                 if (p->bus == dev->bus
1669                     && p->slot == dev->slot
1670                     && p->func == (dev->func ^ 1))
1671                         return p;
1672         }
1673         return NULL;
1674 }
1675
1676 static struct bpctl_dev *get_status_port_fn(struct bpctl_dev *pbpctl_dev)
1677 {
1678         if (pbpctl_dev) {
1679                 if (pbpctl_dev->func == 0 || pbpctl_dev->func == 2)
1680                         return lookup_port(pbpctl_dev);
1681         }
1682         return NULL;
1683 }
1684
1685 static struct bpctl_dev *get_master_port_fn(struct bpctl_dev *pbpctl_dev)
1686 {
1687         if (pbpctl_dev) {
1688                 if (pbpctl_dev->func == 1 || pbpctl_dev->func == 3)
1689                         return lookup_port(pbpctl_dev);
1690         }
1691         return NULL;
1692 }
1693
1694 /**************************************/
1695 /**************INTEL API***************/
1696 /**************************************/
1697
1698 static void write_data_port_int(struct bpctl_dev *pbpctl_dev,
1699                                 unsigned char ctrl_value)
1700 {
1701         uint32_t value;
1702
1703         value = BPCTL_READ_REG(pbpctl_dev, CTRL);
1704 /* Make SDP0 Pin Directonality to Output */
1705         value |= BPCTLI_CTRL_SDP0_DIR;
1706         BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, value);
1707
1708         value &= ~BPCTLI_CTRL_SDP0_DATA;
1709         value |= ((ctrl_value & 0x1) << BPCTLI_CTRL_SDP0_SHIFT);
1710         BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, value);
1711
1712         value = (BPCTL_READ_REG(pbpctl_dev, CTRL_EXT));
1713 /* Make SDP2 Pin Directonality to Output */
1714         value |= BPCTLI_CTRL_EXT_SDP6_DIR;
1715         BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, value);
1716
1717         value &= ~BPCTLI_CTRL_EXT_SDP6_DATA;
1718         value |= (((ctrl_value & 0x2) >> 1) << BPCTLI_CTRL_EXT_SDP6_SHIFT);
1719         BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, value);
1720
1721 }
1722
1723 static int write_data_int(struct bpctl_dev *pbpctl_dev, unsigned char value)
1724 {
1725         struct bpctl_dev *pbpctl_dev_b = NULL;
1726
1727         pbpctl_dev_b = get_status_port_fn(pbpctl_dev);
1728         if (!pbpctl_dev_b)
1729                 return -1;
1730         atomic_set(&pbpctl_dev->wdt_busy, 1);
1731         write_data_port_int(pbpctl_dev, value & 0x3);
1732         write_data_port_int(pbpctl_dev_b, ((value & 0xc) >> 2));
1733         atomic_set(&pbpctl_dev->wdt_busy, 0);
1734
1735         return 0;
1736 }
1737
1738 static int wdt_pulse_int(struct bpctl_dev *pbpctl_dev)
1739 {
1740
1741         if ((atomic_read(&pbpctl_dev->wdt_busy)) == 1)
1742                 return -1;
1743
1744         if ((write_data_int(pbpctl_dev, RESET_WDT_INT)) < 0)
1745                 return -1;
1746         msec_delay_bp(CMND_INTERVAL_INT);
1747         if ((write_data_int(pbpctl_dev, CMND_OFF_INT)) < 0)
1748                 return -1;
1749         msec_delay_bp(CMND_INTERVAL_INT);
1750
1751         if (pbpctl_dev->wdt_status == WDT_STATUS_EN)
1752                 pbpctl_dev->bypass_wdt_on_time = jiffies;
1753
1754         return 0;
1755 }
1756
1757 /*************************************/
1758 /************* COMMANDS **************/
1759 /*************************************/
1760
1761 /* CMND_ON  0x4 (100)*/
1762 int cmnd_on(struct bpctl_dev *pbpctl_dev)
1763 {
1764         int ret = BP_NOT_CAP;
1765
1766         if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
1767                 if (INTEL_IF_SERIES(pbpctl_dev->subdevice))
1768                         return 0;
1769                 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER)
1770                         write_data(pbpctl_dev, CMND_ON);
1771                 else
1772                         data_pulse(pbpctl_dev, CMND_ON);
1773                 ret = 0;
1774         }
1775         return ret;
1776 }
1777
1778 /* CMND_OFF  0x2 (10)*/
1779 int cmnd_off(struct bpctl_dev *pbpctl_dev)
1780 {
1781         int ret = BP_NOT_CAP;
1782
1783         if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
1784                 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
1785                         write_data_int(pbpctl_dev, CMND_OFF_INT);
1786                         msec_delay_bp(CMND_INTERVAL_INT);
1787                 } else if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER)
1788                         write_data(pbpctl_dev, CMND_OFF);
1789                 else
1790                         data_pulse(pbpctl_dev, CMND_OFF);
1791                 ret = 0;
1792         }
1793         return ret;
1794 }
1795
1796 /* BYPASS_ON (0xa)*/
1797 int bypass_on(struct bpctl_dev *pbpctl_dev)
1798 {
1799         int ret = BP_NOT_CAP;
1800
1801         if (pbpctl_dev->bp_caps & BP_CAP) {
1802                 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
1803                         write_data_int(pbpctl_dev, BYPASS_ON_INT);
1804                         msec_delay_bp(BYPASS_DELAY_INT);
1805                         pbpctl_dev->bp_status_un = 0;
1806                 } else if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
1807                         write_data(pbpctl_dev, BYPASS_ON);
1808                         if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER)
1809                                 msec_delay_bp(LATCH_DELAY);
1810                 } else
1811                         data_pulse(pbpctl_dev, BYPASS_ON);
1812                 ret = 0;
1813         }
1814         return ret;
1815 }
1816
1817 /* BYPASS_OFF (0x8 111)*/
1818 int bypass_off(struct bpctl_dev *pbpctl_dev)
1819 {
1820         int ret = BP_NOT_CAP;
1821
1822         if (pbpctl_dev->bp_caps & BP_CAP) {
1823                 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
1824                         write_data_int(pbpctl_dev, DIS_BYPASS_CAP_INT);
1825                         msec_delay_bp(BYPASS_DELAY_INT);
1826                         write_data_int(pbpctl_dev, PWROFF_BYPASS_ON_INT);
1827                         msec_delay_bp(BYPASS_DELAY_INT);
1828                         pbpctl_dev->bp_status_un = 0;
1829                 } else if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
1830                         write_data(pbpctl_dev, BYPASS_OFF);
1831                         if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER)
1832                                 msec_delay_bp(LATCH_DELAY);
1833                 } else
1834                         data_pulse(pbpctl_dev, BYPASS_OFF);
1835                 ret = 0;
1836         }
1837         return ret;
1838 }
1839
1840 /* TAP_OFF (0x9)*/
1841 int tap_off(struct bpctl_dev *pbpctl_dev)
1842 {
1843         int ret = BP_NOT_CAP;
1844         if ((pbpctl_dev->bp_caps & TAP_CAP)
1845             && (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER)) {
1846                 write_data(pbpctl_dev, TAP_OFF);
1847                 msec_delay_bp(LATCH_DELAY);
1848                 ret = 0;
1849         }
1850         return ret;
1851 }
1852
1853 /* TAP_ON (0xb)*/
1854 int tap_on(struct bpctl_dev *pbpctl_dev)
1855 {
1856         int ret = BP_NOT_CAP;
1857         if ((pbpctl_dev->bp_caps & TAP_CAP)
1858             && (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER)) {
1859                 write_data(pbpctl_dev, TAP_ON);
1860                 msec_delay_bp(LATCH_DELAY);
1861                 ret = 0;
1862         }
1863         return ret;
1864 }
1865
1866 /* DISC_OFF (0x9)*/
1867 int disc_off(struct bpctl_dev *pbpctl_dev)
1868 {
1869         int ret = 0;
1870         if ((pbpctl_dev->bp_caps & DISC_CAP) && (pbpctl_dev->bp_ext_ver >= 0x8)) {
1871                 write_data(pbpctl_dev, DISC_OFF);
1872                 msec_delay_bp(LATCH_DELAY);
1873         } else
1874                 ret = BP_NOT_CAP;
1875         return ret;
1876 }
1877
1878 /* DISC_ON (0xb)*/
1879 int disc_on(struct bpctl_dev *pbpctl_dev)
1880 {
1881         int ret = 0;
1882         if ((pbpctl_dev->bp_caps & DISC_CAP) && (pbpctl_dev->bp_ext_ver >= 0x8)) {
1883                 write_data(pbpctl_dev, /*DISC_ON */ 0x85);
1884                 msec_delay_bp(LATCH_DELAY);
1885         } else
1886                 ret = BP_NOT_CAP;
1887         return ret;
1888 }
1889
1890 /* DISC_PORT_ON */
1891 int disc_port_on(struct bpctl_dev *pbpctl_dev)
1892 {
1893         int ret = 0;
1894         struct bpctl_dev *pbpctl_dev_m;
1895
1896         if ((is_bypass_fn(pbpctl_dev)) == 1)
1897                 pbpctl_dev_m = pbpctl_dev;
1898         else
1899                 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
1900         if (pbpctl_dev_m == NULL)
1901                 return BP_NOT_CAP;
1902
1903         if (pbpctl_dev_m->bp_caps_ex & DISC_PORT_CAP_EX) {
1904                 if (is_bypass_fn(pbpctl_dev) == 1)
1905                         write_data(pbpctl_dev_m, TX_DISA);
1906                 else
1907                         write_data(pbpctl_dev_m, TX_DISB);
1908
1909                 msec_delay_bp(LATCH_DELAY);
1910
1911         }
1912         return ret;
1913 }
1914
1915 /* DISC_PORT_OFF */
1916 int disc_port_off(struct bpctl_dev *pbpctl_dev)
1917 {
1918         int ret = 0;
1919         struct bpctl_dev *pbpctl_dev_m;
1920
1921         if ((is_bypass_fn(pbpctl_dev)) == 1)
1922                 pbpctl_dev_m = pbpctl_dev;
1923         else
1924                 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
1925         if (pbpctl_dev_m == NULL)
1926                 return BP_NOT_CAP;
1927
1928         if (pbpctl_dev_m->bp_caps_ex & DISC_PORT_CAP_EX) {
1929                 if (is_bypass_fn(pbpctl_dev) == 1)
1930                         write_data(pbpctl_dev_m, TX_ENA);
1931                 else
1932                         write_data(pbpctl_dev_m, TX_ENB);
1933
1934                 msec_delay_bp(LATCH_DELAY);
1935
1936         }
1937         return ret;
1938 }
1939
1940 /*TWO_PORT_LINK_HW_EN (0xe)*/
1941 int tpl_hw_on(struct bpctl_dev *pbpctl_dev)
1942 {
1943         int ret = 0, ctrl = 0;
1944         struct bpctl_dev *pbpctl_dev_b = NULL;
1945
1946         pbpctl_dev_b = get_status_port_fn(pbpctl_dev);
1947         if (!pbpctl_dev_b)
1948                 return BP_NOT_CAP;
1949
1950         if (pbpctl_dev->bp_caps_ex & TPL2_CAP_EX) {
1951                 cmnd_on(pbpctl_dev);
1952                 write_data(pbpctl_dev, TPL2_ON);
1953                 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
1954                 cmnd_off(pbpctl_dev);
1955                 return ret;
1956         }
1957
1958         if (TPL_IF_SERIES(pbpctl_dev->subdevice)) {
1959                 ctrl = BPCTL_READ_REG(pbpctl_dev_b, CTRL);
1960                 BPCTL_BP_WRITE_REG(pbpctl_dev_b, CTRL,
1961                                    ((ctrl | BPCTLI_CTRL_SWDPIO0) &
1962                                     ~BPCTLI_CTRL_SWDPIN0));
1963         } else
1964                 ret = BP_NOT_CAP;
1965         return ret;
1966 }
1967
1968 /*TWO_PORT_LINK_HW_DIS (0xc)*/
1969 int tpl_hw_off(struct bpctl_dev *pbpctl_dev)
1970 {
1971         int ret = 0, ctrl = 0;
1972         struct bpctl_dev *pbpctl_dev_b = NULL;
1973
1974         pbpctl_dev_b = get_status_port_fn(pbpctl_dev);
1975         if (!pbpctl_dev_b)
1976                 return BP_NOT_CAP;
1977         if (pbpctl_dev->bp_caps_ex & TPL2_CAP_EX) {
1978                 cmnd_on(pbpctl_dev);
1979                 write_data(pbpctl_dev, TPL2_OFF);
1980                 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
1981                 cmnd_off(pbpctl_dev);
1982                 return ret;
1983         }
1984         if (TPL_IF_SERIES(pbpctl_dev->subdevice)) {
1985                 ctrl = BPCTL_READ_REG(pbpctl_dev_b, CTRL);
1986                 BPCTL_BP_WRITE_REG(pbpctl_dev_b, CTRL,
1987                                    (ctrl | BPCTLI_CTRL_SWDPIO0 |
1988                                     BPCTLI_CTRL_SWDPIN0));
1989         } else
1990                 ret = BP_NOT_CAP;
1991         return ret;
1992 }
1993
1994 /* WDT_OFF (0x6 110)*/
1995 int wdt_off(struct bpctl_dev *pbpctl_dev)
1996 {
1997         int ret = BP_NOT_CAP;
1998
1999         if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
2000                 if (INTEL_IF_SERIES(pbpctl_dev->subdevice))
2001                         bypass_off(pbpctl_dev);
2002                 else if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER)
2003                         write_data(pbpctl_dev, WDT_OFF);
2004                 else
2005                         data_pulse(pbpctl_dev, WDT_OFF);
2006                 pbpctl_dev->wdt_status = WDT_STATUS_DIS;
2007                 ret = 0;
2008         }
2009         return ret;
2010 }
2011
2012 /* WDT_ON (0x10)*/
2013
2014 /***Global***/
2015 static unsigned int
2016     wdt_val_array[] = { 1000, 1500, 2000, 3000, 4000, 8000, 16000, 32000, 0 };
2017
2018 int wdt_on(struct bpctl_dev *pbpctl_dev, unsigned int timeout)
2019 {
2020
2021         if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
2022                 unsigned int pulse = 0, temp_value = 0, temp_cnt = 0;
2023                 pbpctl_dev->wdt_status = 0;
2024
2025                 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
2026                         for (; wdt_val_array[temp_cnt]; temp_cnt++)
2027                                 if (timeout <= wdt_val_array[temp_cnt])
2028                                         break;
2029
2030                         if (!wdt_val_array[temp_cnt])
2031                                 temp_cnt--;
2032
2033                         timeout = wdt_val_array[temp_cnt];
2034                         temp_cnt += 0x7;
2035
2036                         write_data_int(pbpctl_dev, DIS_BYPASS_CAP_INT);
2037                         msec_delay_bp(BYPASS_DELAY_INT);
2038                         pbpctl_dev->bp_status_un = 0;
2039                         write_data_int(pbpctl_dev, temp_cnt);
2040                         pbpctl_dev->bypass_wdt_on_time = jiffies;
2041                         msec_delay_bp(CMND_INTERVAL_INT);
2042                         pbpctl_dev->bypass_timer_interval = timeout;
2043                 } else {
2044                         timeout =
2045                             (timeout <
2046                              TIMEOUT_UNIT ? TIMEOUT_UNIT : (timeout >
2047                                                             WDT_TIMEOUT_MAX ?
2048                                                             WDT_TIMEOUT_MAX :
2049                                                             timeout));
2050                         temp_value = timeout / 100;
2051                         while ((temp_value >>= 1))
2052                                 temp_cnt++;
2053                         if (timeout > ((1 << temp_cnt) * 100))
2054                                 temp_cnt++;
2055                         pbpctl_dev->bypass_wdt_on_time = jiffies;
2056                         pulse = (WDT_ON | temp_cnt);
2057                         if (pbpctl_dev->bp_ext_ver == OLD_IF_VER)
2058                                 data_pulse(pbpctl_dev, pulse);
2059                         else
2060                                 write_data(pbpctl_dev, pulse);
2061                         pbpctl_dev->bypass_timer_interval =
2062                             (1 << temp_cnt) * 100;
2063                 }
2064                 pbpctl_dev->wdt_status = WDT_STATUS_EN;
2065                 return 0;
2066         }
2067         return BP_NOT_CAP;
2068 }
2069
2070 void bp75_put_hw_semaphore_generic(struct bpctl_dev *pbpctl_dev)
2071 {
2072         u32 swsm;
2073
2074         swsm = BPCTL_READ_REG(pbpctl_dev, SWSM);
2075
2076         swsm &= ~(BPCTLI_SWSM_SMBI | BPCTLI_SWSM_SWESMBI);
2077
2078         BPCTL_WRITE_REG(pbpctl_dev, SWSM, swsm);
2079 }
2080
2081 s32 bp75_get_hw_semaphore_generic(struct bpctl_dev *pbpctl_dev)
2082 {
2083         u32 swsm;
2084         s32 ret_val = 0;
2085         s32 timeout = 8192 + 1;
2086         s32 i = 0;
2087
2088         /* Get the SW semaphore */
2089         while (i < timeout) {
2090                 swsm = BPCTL_READ_REG(pbpctl_dev, SWSM);
2091                 if (!(swsm & BPCTLI_SWSM_SMBI))
2092                         break;
2093
2094                 usec_delay(50);
2095                 i++;
2096         }
2097
2098         if (i == timeout) {
2099                 printk
2100                     ("bpctl_mod: Driver can't access device - SMBI bit is set.\n");
2101                 ret_val = -1;
2102                 goto out;
2103         }
2104
2105         /* Get the FW semaphore. */
2106         for (i = 0; i < timeout; i++) {
2107                 swsm = BPCTL_READ_REG(pbpctl_dev, SWSM);
2108                 BPCTL_WRITE_REG(pbpctl_dev, SWSM, swsm | BPCTLI_SWSM_SWESMBI);
2109
2110                 /* Semaphore acquired if bit latched */
2111                 if (BPCTL_READ_REG(pbpctl_dev, SWSM) & BPCTLI_SWSM_SWESMBI)
2112                         break;
2113
2114                 usec_delay(50);
2115         }
2116
2117         if (i == timeout) {
2118                 /* Release semaphores */
2119                 bp75_put_hw_semaphore_generic(pbpctl_dev);
2120                 printk("bpctl_mod: Driver can't access the NVM\n");
2121                 ret_val = -1;
2122                 goto out;
2123         }
2124
2125  out:
2126         return ret_val;
2127 }
2128
2129 static void bp75_release_phy(struct bpctl_dev *pbpctl_dev)
2130 {
2131         u16 mask = BPCTLI_SWFW_PHY0_SM;
2132         u32 swfw_sync;
2133         s32 ret_val;
2134
2135         if ((pbpctl_dev->func == 1) || (pbpctl_dev->func == 3))
2136                 mask = BPCTLI_SWFW_PHY1_SM;
2137
2138         do
2139                 ret_val = bp75_get_hw_semaphore_generic(pbpctl_dev);
2140         while (ret_val != 0);
2141
2142         swfw_sync = BPCTL_READ_REG(pbpctl_dev, SW_FW_SYNC);
2143         swfw_sync &= ~mask;
2144         BPCTL_WRITE_REG(pbpctl_dev, SW_FW_SYNC, swfw_sync);
2145
2146         bp75_put_hw_semaphore_generic(pbpctl_dev);
2147 }
2148
2149 static s32 bp75_acquire_phy(struct bpctl_dev *pbpctl_dev)
2150 {
2151         u16 mask = BPCTLI_SWFW_PHY0_SM;
2152         u32 swfw_sync;
2153         u32 swmask;
2154         u32 fwmask;
2155         s32 ret_val = 0;
2156         s32 i = 0, timeout = 200;
2157
2158         if ((pbpctl_dev->func == 1) || (pbpctl_dev->func == 3))
2159                 mask = BPCTLI_SWFW_PHY1_SM;
2160
2161         swmask = mask;
2162         fwmask = mask << 16;
2163
2164         while (i < timeout) {
2165                 if (bp75_get_hw_semaphore_generic(pbpctl_dev)) {
2166                         ret_val = -1;
2167                         goto out;
2168                 }
2169
2170                 swfw_sync = BPCTL_READ_REG(pbpctl_dev, SW_FW_SYNC);
2171                 if (!(swfw_sync & (fwmask | swmask)))
2172                         break;
2173
2174                 bp75_put_hw_semaphore_generic(pbpctl_dev);
2175                 mdelay(5);
2176                 i++;
2177         }
2178
2179         if (i == timeout) {
2180                 printk
2181                     ("bpctl_mod: Driver can't access resource, SW_FW_SYNC timeout.\n");
2182                 ret_val = -1;
2183                 goto out;
2184         }
2185
2186         swfw_sync |= swmask;
2187         BPCTL_WRITE_REG(pbpctl_dev, SW_FW_SYNC, swfw_sync);
2188
2189         bp75_put_hw_semaphore_generic(pbpctl_dev);
2190
2191  out:
2192         return ret_val;
2193 }
2194
2195 s32 bp75_read_phy_reg_mdic(struct bpctl_dev *pbpctl_dev, u32 offset, u16 *data)
2196 {
2197         u32 i, mdic = 0;
2198         s32 ret_val = 0;
2199         u32 phy_addr = 1;
2200
2201         mdic = ((offset << BPCTLI_MDIC_REG_SHIFT) |
2202                 (phy_addr << BPCTLI_MDIC_PHY_SHIFT) | (BPCTLI_MDIC_OP_READ));
2203
2204         BPCTL_WRITE_REG(pbpctl_dev, MDIC, mdic);
2205
2206         for (i = 0; i < (BPCTLI_GEN_POLL_TIMEOUT * 3); i++) {
2207                 usec_delay(50);
2208                 mdic = BPCTL_READ_REG(pbpctl_dev, MDIC);
2209                 if (mdic & BPCTLI_MDIC_READY)
2210                         break;
2211         }
2212         if (!(mdic & BPCTLI_MDIC_READY)) {
2213                 printk("bpctl_mod: MDI Read did not complete\n");
2214                 ret_val = -1;
2215                 goto out;
2216         }
2217         if (mdic & BPCTLI_MDIC_ERROR) {
2218                 printk("bpctl_mod: MDI Error\n");
2219                 ret_val = -1;
2220                 goto out;
2221         }
2222         *data = (u16) mdic;
2223
2224  out:
2225         return ret_val;
2226 }
2227
2228 s32 bp75_write_phy_reg_mdic(struct bpctl_dev *pbpctl_dev, u32 offset, u16 data)
2229 {
2230         u32 i, mdic = 0;
2231         s32 ret_val = 0;
2232         u32 phy_addr = 1;
2233
2234         mdic = (((u32) data) |
2235                 (offset << BPCTLI_MDIC_REG_SHIFT) |
2236                 (phy_addr << BPCTLI_MDIC_PHY_SHIFT) | (BPCTLI_MDIC_OP_WRITE));
2237
2238         BPCTL_WRITE_REG(pbpctl_dev, MDIC, mdic);
2239
2240         for (i = 0; i < (BPCTLI_GEN_POLL_TIMEOUT * 3); i++) {
2241                 usec_delay(50);
2242                 mdic = BPCTL_READ_REG(pbpctl_dev, MDIC);
2243                 if (mdic & BPCTLI_MDIC_READY)
2244                         break;
2245         }
2246         if (!(mdic & BPCTLI_MDIC_READY)) {
2247                 printk("bpctl_mod: MDI Write did not complete\n");
2248                 ret_val = -1;
2249                 goto out;
2250         }
2251         if (mdic & BPCTLI_MDIC_ERROR) {
2252                 printk("bpctl_mod: MDI Error\n");
2253                 ret_val = -1;
2254                 goto out;
2255         }
2256
2257  out:
2258         return ret_val;
2259 }
2260
2261 static s32 bp75_read_phy_reg(struct bpctl_dev *pbpctl_dev, u32 offset, u16 *data)
2262 {
2263         s32 ret_val = 0;
2264
2265         ret_val = bp75_acquire_phy(pbpctl_dev);
2266         if (ret_val)
2267                 goto out;
2268
2269         if (offset > BPCTLI_MAX_PHY_MULTI_PAGE_REG) {
2270                 ret_val = bp75_write_phy_reg_mdic(pbpctl_dev,
2271                                                   BPCTLI_IGP01E1000_PHY_PAGE_SELECT,
2272                                                   (u16) offset);
2273                 if (ret_val)
2274                         goto release;
2275         }
2276
2277         ret_val =
2278             bp75_read_phy_reg_mdic(pbpctl_dev,
2279                                    BPCTLI_MAX_PHY_REG_ADDRESS & offset, data);
2280
2281  release:
2282         bp75_release_phy(pbpctl_dev);
2283  out:
2284         return ret_val;
2285 }
2286
2287 static s32 bp75_write_phy_reg(struct bpctl_dev *pbpctl_dev, u32 offset, u16 data)
2288 {
2289         s32 ret_val = 0;
2290
2291         ret_val = bp75_acquire_phy(pbpctl_dev);
2292         if (ret_val)
2293                 goto out;
2294
2295         if (offset > BPCTLI_MAX_PHY_MULTI_PAGE_REG) {
2296                 ret_val = bp75_write_phy_reg_mdic(pbpctl_dev,
2297                                                   BPCTLI_IGP01E1000_PHY_PAGE_SELECT,
2298                                                   (u16) offset);
2299                 if (ret_val)
2300                         goto release;
2301         }
2302
2303         ret_val =
2304             bp75_write_phy_reg_mdic(pbpctl_dev,
2305                                     BPCTLI_MAX_PHY_REG_ADDRESS & offset, data);
2306
2307  release:
2308         bp75_release_phy(pbpctl_dev);
2309
2310  out:
2311         return ret_val;
2312 }
2313
2314 /* SET_TX  (non-Bypass command :)) */
2315 static int set_tx(struct bpctl_dev *pbpctl_dev, int tx_state)
2316 {
2317         int ret = 0, ctrl = 0;
2318         struct bpctl_dev *pbpctl_dev_m;
2319         if ((is_bypass_fn(pbpctl_dev)) == 1)
2320                 pbpctl_dev_m = pbpctl_dev;
2321         else
2322                 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
2323         if (pbpctl_dev_m == NULL)
2324                 return BP_NOT_CAP;
2325         if (pbpctl_dev_m->bp_caps_ex & DISC_PORT_CAP_EX) {
2326                 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL);
2327                 if (!tx_state) {
2328                         if (pbpctl_dev->bp_540) {
2329                                 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
2330                                 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2331                                                 (ctrl | BP10G_SDP1_DIR |
2332                                                  BP10G_SDP1_DATA));
2333
2334                         } else {
2335                                 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
2336                                                    (ctrl | BPCTLI_CTRL_SDP1_DIR
2337                                                     | BPCTLI_CTRL_SWDPIN1));
2338                         }
2339                 } else {
2340                         if (pbpctl_dev->bp_540) {
2341                                 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
2342                                 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2343                                                 ((ctrl | BP10G_SDP1_DIR) &
2344                                                  ~BP10G_SDP1_DATA));
2345                         } else {
2346                                 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
2347                                                    ((ctrl |
2348                                                      BPCTLI_CTRL_SDP1_DIR) &
2349                                                     ~BPCTLI_CTRL_SWDPIN1));
2350                         }
2351                         return ret;
2352
2353                 }
2354         } else if (pbpctl_dev->bp_caps & TX_CTL_CAP) {
2355                 if (PEG5_IF_SERIES(pbpctl_dev->subdevice)) {
2356                         if (tx_state) {
2357                                 uint16_t mii_reg;
2358                                 if (!
2359                                     (ret =
2360                                      bp75_read_phy_reg(pbpctl_dev,
2361                                                        BPCTLI_PHY_CONTROL,
2362                                                        &mii_reg))) {
2363                                         if (mii_reg & BPCTLI_MII_CR_POWER_DOWN) {
2364                                                 ret =
2365                                                     bp75_write_phy_reg
2366                                                     (pbpctl_dev,
2367                                                      BPCTLI_PHY_CONTROL,
2368                                                      mii_reg &
2369                                                      ~BPCTLI_MII_CR_POWER_DOWN);
2370                                         }
2371                                 }
2372                         } else {
2373                                 uint16_t mii_reg;
2374                                 if (!
2375                                     (ret =
2376                                      bp75_read_phy_reg(pbpctl_dev,
2377                                                        BPCTLI_PHY_CONTROL,
2378                                                        &mii_reg))) {
2379
2380                                         mii_reg |= BPCTLI_MII_CR_POWER_DOWN;
2381                                         ret =
2382                                             bp75_write_phy_reg(pbpctl_dev,
2383                                                                BPCTLI_PHY_CONTROL,
2384                                                                mii_reg);
2385                                 }
2386                         }
2387
2388                 }
2389                 if (pbpctl_dev->bp_fiber5)
2390                         ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
2391                 else if (pbpctl_dev->bp_10gb)
2392                         ctrl = BP10GB_READ_REG(pbpctl_dev, MISC_REG_GPIO);
2393                 else if (!pbpctl_dev->bp_10g)
2394                         ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL);
2395                 else
2396                         ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
2397
2398                 if (!tx_state)
2399                         if (pbpctl_dev->bp_10g9) {
2400                                 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2401                                                 (ctrl | BP10G_SDP3_DATA |
2402                                                  BP10G_SDP3_DIR));
2403
2404                         } else if (pbpctl_dev->bp_fiber5) {
2405                                 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
2406                                                    (ctrl |
2407                                                     BPCTLI_CTRL_EXT_SDP6_DIR |
2408                                                     BPCTLI_CTRL_EXT_SDP6_DATA));
2409
2410                         } else if (pbpctl_dev->bp_10gb) {
2411                                 if ((pbpctl_dev->func == 1)
2412                                     || (pbpctl_dev->func == 3))
2413                                         BP10GB_WRITE_REG(pbpctl_dev,
2414                                                          MISC_REG_GPIO,
2415                                                          (ctrl |
2416                                                           BP10GB_GPIO0_SET_P1) &
2417                                                          ~(BP10GB_GPIO0_CLR_P1 |
2418                                                            BP10GB_GPIO0_OE_P1));
2419                                 else
2420                                         BP10GB_WRITE_REG(pbpctl_dev,
2421                                                          MISC_REG_GPIO,
2422                                                          (ctrl |
2423                                                           BP10GB_GPIO0_OE_P0 |
2424                                                           BP10GB_GPIO0_SET_P0));
2425
2426                         } else if (pbpctl_dev->bp_i80) {
2427                                 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
2428                                                    (ctrl | BPCTLI_CTRL_SDP1_DIR
2429                                                     | BPCTLI_CTRL_SWDPIN1));
2430
2431                         } else if (pbpctl_dev->bp_540) {
2432                                 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
2433                                 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2434                                                 (ctrl | BP10G_SDP1_DIR |
2435                                                  BP10G_SDP1_DATA));
2436
2437                         }
2438
2439                         else if (!pbpctl_dev->bp_10g)
2440                                 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
2441                                                    (ctrl | BPCTLI_CTRL_SWDPIO0 |
2442                                                     BPCTLI_CTRL_SWDPIN0));
2443
2444                         else
2445                                 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2446                                                 (ctrl | BP10G_SDP0_DATA |
2447                                                  BP10G_SDP0_DIR));
2448
2449                 else {
2450                         if (pbpctl_dev->bp_10g9) {
2451                                 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2452                                                 ((ctrl | BP10G_SDP3_DIR) &
2453                                                  ~BP10G_SDP3_DATA));
2454
2455                         } else if (pbpctl_dev->bp_fiber5) {
2456                                 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
2457                                                    ((ctrl |
2458                                                      BPCTLI_CTRL_EXT_SDP6_DIR) &
2459                                                     ~BPCTLI_CTRL_EXT_SDP6_DATA));
2460
2461                         } else if (pbpctl_dev->bp_10gb) {
2462                                 if ((bpctl_dev_arr->func == 1)
2463                                     || (bpctl_dev_arr->func == 3))
2464                                         BP10GB_WRITE_REG(pbpctl_dev,
2465                                                          MISC_REG_GPIO,
2466                                                          (ctrl |
2467                                                           BP10GB_GPIO0_CLR_P1) &
2468                                                          ~(BP10GB_GPIO0_SET_P1 |
2469                                                            BP10GB_GPIO0_OE_P1));
2470                                 else
2471                                         BP10GB_WRITE_REG(pbpctl_dev,
2472                                                          MISC_REG_GPIO,
2473                                                          (ctrl |
2474                                                           BP10GB_GPIO0_OE_P0 |
2475                                                           BP10GB_GPIO0_CLR_P0));
2476
2477                         } else if (pbpctl_dev->bp_i80) {
2478                                 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
2479                                                    ((ctrl |
2480                                                      BPCTLI_CTRL_SDP1_DIR) &
2481                                                     ~BPCTLI_CTRL_SWDPIN1));
2482                         } else if (pbpctl_dev->bp_540) {
2483                                 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
2484                                 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2485                                                 ((ctrl | BP10G_SDP1_DIR) &
2486                                                  ~BP10G_SDP1_DATA));
2487                         }
2488
2489                         else if (!pbpctl_dev->bp_10g) {
2490                                 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
2491                                                    ((ctrl | BPCTLI_CTRL_SWDPIO0)
2492                                                     & ~BPCTLI_CTRL_SWDPIN0));
2493                                 if (!PEGF_IF_SERIES(pbpctl_dev->subdevice)) {
2494                                         BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
2495                                                            (ctrl &
2496                                                             ~
2497                                                             (BPCTLI_CTRL_SDP0_DATA
2498                                                              |
2499                                                              BPCTLI_CTRL_SDP0_DIR)));
2500                                 }
2501                         } else
2502                                 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2503                                                 ((ctrl | BP10G_SDP0_DIR) &
2504                                                  ~BP10G_SDP0_DATA));
2505
2506                 }
2507
2508         } else
2509                 ret = BP_NOT_CAP;
2510         return ret;
2511
2512 }
2513
2514 /* SET_FORCE_LINK  (non-Bypass command :)) */
2515 static int set_bp_force_link(struct bpctl_dev *pbpctl_dev, int tx_state)
2516 {
2517         int ret = 0, ctrl = 0;
2518
2519         if (DBI_IF_SERIES(pbpctl_dev->subdevice)) {
2520
2521                 if ((pbpctl_dev->bp_10g) || (pbpctl_dev->bp_10g9)) {
2522
2523                         ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL);
2524                         if (!tx_state)
2525                                 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2526                                                 ctrl & ~BP10G_SDP1_DIR);
2527                         else
2528                                 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2529                                                 ((ctrl | BP10G_SDP1_DIR) &
2530                                                  ~BP10G_SDP1_DATA));
2531                         return ret;
2532                 }
2533
2534         }
2535         return BP_NOT_CAP;
2536 }
2537
2538 /*RESET_CONT 0x20 */
2539 int reset_cont(struct bpctl_dev *pbpctl_dev)
2540 {
2541         int ret = BP_NOT_CAP;
2542
2543         if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
2544                 if (INTEL_IF_SERIES(pbpctl_dev->subdevice))
2545                         return BP_NOT_CAP;
2546                 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER)
2547                         write_data(pbpctl_dev, RESET_CONT);
2548                 else
2549                         data_pulse(pbpctl_dev, RESET_CONT);
2550                 ret = 0;
2551         }
2552         return ret;
2553 }
2554
2555 /*DIS_BYPASS_CAP 0x22 */
2556 int dis_bypass_cap(struct bpctl_dev *pbpctl_dev)
2557 {
2558
2559         if (pbpctl_dev->bp_caps & BP_DIS_CAP) {
2560                 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
2561                         write_data_int(pbpctl_dev, DIS_BYPASS_CAP_INT);
2562                         msec_delay_bp(BYPASS_DELAY_INT);
2563                 } else {
2564                         write_data(pbpctl_dev, BYPASS_OFF);
2565                         msec_delay_bp(LATCH_DELAY);
2566                         write_data(pbpctl_dev, DIS_BYPASS_CAP);
2567                         msec_delay_bp(BYPASS_CAP_DELAY);
2568                 }
2569                 return 0;
2570         }
2571         return BP_NOT_CAP;
2572 }
2573
2574 /*EN_BYPASS_CAP 0x24 */
2575 int en_bypass_cap(struct bpctl_dev *pbpctl_dev)
2576 {
2577         if (pbpctl_dev->bp_caps & BP_DIS_CAP) {
2578                 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
2579                         write_data_int(pbpctl_dev, PWROFF_BYPASS_ON_INT);
2580                         msec_delay_bp(BYPASS_DELAY_INT);
2581                 } else {
2582                         write_data(pbpctl_dev, EN_BYPASS_CAP);
2583                         msec_delay_bp(BYPASS_CAP_DELAY);
2584                 }
2585                 return 0;
2586         }
2587         return BP_NOT_CAP;
2588 }
2589
2590 /* BYPASS_STATE_PWRON 0x26*/
2591 int bypass_state_pwron(struct bpctl_dev *pbpctl_dev)
2592 {
2593         if (pbpctl_dev->bp_caps & BP_PWUP_CTL_CAP) {
2594                 write_data(pbpctl_dev, BYPASS_STATE_PWRON);
2595                 if (pbpctl_dev->bp_ext_ver == PXG2BPI_VER)
2596                         msec_delay_bp(DFLT_PWRON_DELAY);
2597                 else
2598                         msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2599                 return 0;
2600         }
2601         return BP_NOT_CAP;
2602 }
2603
2604 /* NORMAL_STATE_PWRON 0x28*/
2605 int normal_state_pwron(struct bpctl_dev *pbpctl_dev)
2606 {
2607         if ((pbpctl_dev->bp_caps & BP_PWUP_CTL_CAP)
2608             || (pbpctl_dev->bp_caps & TAP_PWUP_CTL_CAP)) {
2609                 write_data(pbpctl_dev, NORMAL_STATE_PWRON);
2610                 if (pbpctl_dev->bp_ext_ver == PXG2BPI_VER)
2611                         msec_delay_bp(DFLT_PWRON_DELAY);
2612                 else
2613                         msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2614                 return 0;
2615         }
2616         return BP_NOT_CAP;
2617 }
2618
2619 /* BYPASS_STATE_PWROFF 0x27*/
2620 int bypass_state_pwroff(struct bpctl_dev *pbpctl_dev)
2621 {
2622         if (pbpctl_dev->bp_caps & BP_PWOFF_CTL_CAP) {
2623                 write_data(pbpctl_dev, BYPASS_STATE_PWROFF);
2624                 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2625                 return 0;
2626         }
2627         return BP_NOT_CAP;
2628 }
2629
2630 /* NORMAL_STATE_PWROFF 0x29*/
2631 int normal_state_pwroff(struct bpctl_dev *pbpctl_dev)
2632 {
2633         if ((pbpctl_dev->bp_caps & BP_PWOFF_CTL_CAP)) {
2634                 write_data(pbpctl_dev, NORMAL_STATE_PWROFF);
2635                 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2636                 return 0;
2637         }
2638         return BP_NOT_CAP;
2639 }
2640
2641 /*TAP_STATE_PWRON 0x2a*/
2642 int tap_state_pwron(struct bpctl_dev *pbpctl_dev)
2643 {
2644         if (pbpctl_dev->bp_caps & TAP_PWUP_CTL_CAP) {
2645                 write_data(pbpctl_dev, TAP_STATE_PWRON);
2646                 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2647                 return 0;
2648         }
2649         return BP_NOT_CAP;
2650 }
2651
2652 /*DIS_TAP_CAP 0x2c*/
2653 int dis_tap_cap(struct bpctl_dev *pbpctl_dev)
2654 {
2655         if (pbpctl_dev->bp_caps & TAP_DIS_CAP) {
2656                 write_data(pbpctl_dev, DIS_TAP_CAP);
2657                 msec_delay_bp(BYPASS_CAP_DELAY);
2658                 return 0;
2659         }
2660         return BP_NOT_CAP;
2661 }
2662
2663 /*EN_TAP_CAP 0x2e*/
2664 int en_tap_cap(struct bpctl_dev *pbpctl_dev)
2665 {
2666         if (pbpctl_dev->bp_caps & TAP_DIS_CAP) {
2667                 write_data(pbpctl_dev, EN_TAP_CAP);
2668                 msec_delay_bp(BYPASS_CAP_DELAY);
2669                 return 0;
2670         }
2671         return BP_NOT_CAP;
2672 }
2673
2674 /*DISC_STATE_PWRON 0x2a*/
2675 int disc_state_pwron(struct bpctl_dev *pbpctl_dev)
2676 {
2677         if (pbpctl_dev->bp_caps & DISC_PWUP_CTL_CAP) {
2678                 if (pbpctl_dev->bp_ext_ver >= 0x8) {
2679                         write_data(pbpctl_dev, DISC_STATE_PWRON);
2680                         msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2681                         return BP_OK;
2682                 }
2683         }
2684         return BP_NOT_CAP;
2685 }
2686
2687 /*DIS_DISC_CAP 0x2c*/
2688 int dis_disc_cap(struct bpctl_dev *pbpctl_dev)
2689 {
2690         if (pbpctl_dev->bp_caps & DISC_DIS_CAP) {
2691                 if (pbpctl_dev->bp_ext_ver >= 0x8) {
2692                         write_data(pbpctl_dev, DIS_DISC_CAP);
2693                         msec_delay_bp(BYPASS_CAP_DELAY);
2694                         return BP_OK;
2695                 }
2696         }
2697         return BP_NOT_CAP;
2698 }
2699
2700 /*DISC_STATE_PWRON 0x2a*/
2701 int disc_port_state_pwron(struct bpctl_dev *pbpctl_dev)
2702 {
2703         int ret = 0;
2704         struct bpctl_dev *pbpctl_dev_m;
2705
2706         return BP_NOT_CAP;
2707
2708         if ((is_bypass_fn(pbpctl_dev)) == 1)
2709                 pbpctl_dev_m = pbpctl_dev;
2710         else
2711                 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
2712         if (pbpctl_dev_m == NULL)
2713                 return BP_NOT_CAP;
2714
2715         if (pbpctl_dev_m->bp_caps_ex & DISC_PORT_CAP_EX) {
2716                 if (is_bypass_fn(pbpctl_dev) == 1)
2717                         write_data(pbpctl_dev_m, TX_DISA_PWRUP);
2718                 else
2719                         write_data(pbpctl_dev_m, TX_DISB_PWRUP);
2720
2721                 msec_delay_bp(LATCH_DELAY);
2722
2723         }
2724         return ret;
2725 }
2726
2727 int normal_port_state_pwron(struct bpctl_dev *pbpctl_dev)
2728 {
2729         int ret = 0;
2730         struct bpctl_dev *pbpctl_dev_m;
2731         return BP_NOT_CAP;
2732
2733         if ((is_bypass_fn(pbpctl_dev)) == 1)
2734                 pbpctl_dev_m = pbpctl_dev;
2735         else
2736                 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
2737         if (pbpctl_dev_m == NULL)
2738                 return BP_NOT_CAP;
2739
2740         if (pbpctl_dev_m->bp_caps_ex & DISC_PORT_CAP_EX) {
2741                 if (is_bypass_fn(pbpctl_dev) == 1)
2742                         write_data(pbpctl_dev_m, TX_ENA_PWRUP);
2743                 else
2744                         write_data(pbpctl_dev_m, TX_ENB_PWRUP);
2745
2746                 msec_delay_bp(LATCH_DELAY);
2747
2748         }
2749         return ret;
2750 }
2751
2752 /*EN_TAP_CAP 0x2e*/
2753 int en_disc_cap(struct bpctl_dev *pbpctl_dev)
2754 {
2755         if (pbpctl_dev->bp_caps & DISC_DIS_CAP) {
2756                 if (pbpctl_dev->bp_ext_ver >= 0x8) {
2757                         write_data(pbpctl_dev, EN_DISC_CAP);
2758                         msec_delay_bp(BYPASS_CAP_DELAY);
2759                         return BP_OK;
2760                 }
2761         }
2762         return BP_NOT_CAP;
2763 }
2764
2765 int std_nic_on(struct bpctl_dev *pbpctl_dev)
2766 {
2767
2768         if (pbpctl_dev->bp_caps & STD_NIC_CAP) {
2769
2770                 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
2771                         write_data_int(pbpctl_dev, DIS_BYPASS_CAP_INT);
2772                         msec_delay_bp(BYPASS_DELAY_INT);
2773                         pbpctl_dev->bp_status_un = 0;
2774                         return BP_OK;
2775                 }
2776
2777                 if (pbpctl_dev->bp_ext_ver >= 0x8) {
2778                         write_data(pbpctl_dev, STD_NIC_ON);
2779                         msec_delay_bp(BYPASS_CAP_DELAY);
2780                         return BP_OK;
2781
2782                 }
2783
2784                 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
2785                         wdt_off(pbpctl_dev);
2786
2787                         if (pbpctl_dev->bp_caps & BP_CAP) {
2788                                 write_data(pbpctl_dev, BYPASS_OFF);
2789                                 msec_delay_bp(LATCH_DELAY);
2790                         }
2791
2792                         if (pbpctl_dev->bp_caps & TAP_CAP) {
2793                                 write_data(pbpctl_dev, TAP_OFF);
2794                                 msec_delay_bp(LATCH_DELAY);
2795                         }
2796
2797                         write_data(pbpctl_dev, NORMAL_STATE_PWRON);
2798                         if (pbpctl_dev->bp_ext_ver == PXG2BPI_VER)
2799                                 msec_delay_bp(DFLT_PWRON_DELAY);
2800                         else
2801                                 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2802
2803                         if (pbpctl_dev->bp_caps & BP_DIS_CAP) {
2804                                 write_data(pbpctl_dev, DIS_BYPASS_CAP);
2805                                 msec_delay_bp(BYPASS_CAP_DELAY);
2806                         }
2807
2808                         if (pbpctl_dev->bp_caps & TAP_DIS_CAP) {
2809                                 write_data(pbpctl_dev, DIS_TAP_CAP);
2810                                 msec_delay_bp(BYPASS_CAP_DELAY);
2811
2812                         }
2813                         return 0;
2814                 }
2815         }
2816         return BP_NOT_CAP;
2817 }
2818
2819 int std_nic_off(struct bpctl_dev *pbpctl_dev)
2820 {
2821
2822         if (pbpctl_dev->bp_caps & STD_NIC_CAP) {
2823                 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
2824                         write_data_int(pbpctl_dev, PWROFF_BYPASS_ON_INT);
2825                         msec_delay_bp(BYPASS_DELAY_INT);
2826                         return BP_OK;
2827                 }
2828                 if (pbpctl_dev->bp_ext_ver >= 0x8) {
2829                         write_data(pbpctl_dev, STD_NIC_OFF);
2830                         msec_delay_bp(BYPASS_CAP_DELAY);
2831                         return BP_OK;
2832
2833                 }
2834
2835                 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
2836
2837                         if (pbpctl_dev->bp_caps & TAP_PWUP_CTL_CAP) {
2838                                 write_data(pbpctl_dev, TAP_STATE_PWRON);
2839                                 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2840                         }
2841
2842                         if (pbpctl_dev->bp_caps & BP_PWUP_CTL_CAP) {
2843                                 write_data(pbpctl_dev, BYPASS_STATE_PWRON);
2844                                 if (pbpctl_dev->bp_ext_ver > PXG2BPI_VER)
2845                                         msec_delay_bp(LATCH_DELAY +
2846                                                       EEPROM_WR_DELAY);
2847                                 else
2848                                         msec_delay_bp(DFLT_PWRON_DELAY);
2849                         }
2850
2851                         if (pbpctl_dev->bp_caps & TAP_DIS_CAP) {
2852                                 write_data(pbpctl_dev, EN_TAP_CAP);
2853                                 msec_delay_bp(BYPASS_CAP_DELAY);
2854                         }
2855                         if (pbpctl_dev->bp_caps & DISC_DIS_CAP) {
2856                                 write_data(pbpctl_dev, EN_DISC_CAP);
2857                                 msec_delay_bp(BYPASS_CAP_DELAY);
2858                         }
2859
2860                         if (pbpctl_dev->bp_caps & BP_DIS_CAP) {
2861                                 write_data(pbpctl_dev, EN_BYPASS_CAP);
2862                                 msec_delay_bp(BYPASS_CAP_DELAY);
2863                         }
2864
2865                         return 0;
2866                 }
2867         }
2868         return BP_NOT_CAP;
2869 }
2870
2871 int wdt_time_left(struct bpctl_dev *pbpctl_dev)
2872 {
2873
2874         /* unsigned long curr_time=((long long)(jiffies*1000))/HZ, delta_time=0,wdt_on_time=((long long)(pbpctl_dev->bypass_wdt_on_time*1000))/HZ; */
2875         unsigned long curr_time = jiffies, delta_time = 0, wdt_on_time =
2876             pbpctl_dev->bypass_wdt_on_time, delta_time_msec = 0;
2877         int time_left = 0;
2878
2879         switch (pbpctl_dev->wdt_status) {
2880         case WDT_STATUS_DIS:
2881                 time_left = 0;
2882                 break;
2883         case WDT_STATUS_EN:
2884                 delta_time =
2885                     (curr_time >=
2886                      wdt_on_time) ? (curr_time - wdt_on_time) : (~wdt_on_time +
2887                                                                  curr_time);
2888                 delta_time_msec = jiffies_to_msecs(delta_time);
2889                 time_left = pbpctl_dev->bypass_timer_interval - delta_time_msec;
2890                 if (time_left < 0) {
2891                         time_left = -1;
2892                         pbpctl_dev->wdt_status = WDT_STATUS_EXP;
2893                 }
2894                 break;
2895         case WDT_STATUS_EXP:
2896                 time_left = -1;
2897                 break;
2898         }
2899
2900         return time_left;
2901 }
2902
2903 static int wdt_timer(struct bpctl_dev *pbpctl_dev, int *time_left)
2904 {
2905         int ret = 0;
2906         if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
2907                 {
2908                         if (pbpctl_dev->wdt_status == WDT_STATUS_UNKNOWN)
2909                                 ret = BP_NOT_CAP;
2910                         else
2911                                 *time_left = wdt_time_left(pbpctl_dev);
2912                 }
2913
2914         } else
2915                 ret = BP_NOT_CAP;
2916         return ret;
2917 }
2918
2919 static int wdt_timer_reload(struct bpctl_dev *pbpctl_dev)
2920 {
2921
2922         int ret = 0;
2923
2924         if ((pbpctl_dev->bp_caps & WD_CTL_CAP) &&
2925             (pbpctl_dev->wdt_status != WDT_STATUS_UNKNOWN)) {
2926                 if (pbpctl_dev->wdt_status == WDT_STATUS_DIS)
2927                         return 0;
2928                 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER)
2929                         ret = wdt_pulse(pbpctl_dev);
2930                 else if (INTEL_IF_SERIES(pbpctl_dev->subdevice))
2931                         ret = wdt_pulse_int(pbpctl_dev);
2932                 else
2933                         ret = send_wdt_pulse(pbpctl_dev);
2934                 /* if (ret==-1)
2935                     mod_timer(&pbpctl_dev->bp_timer, jiffies+1);*/
2936                 return 1;
2937         }
2938         return BP_NOT_CAP;
2939 }
2940
2941 static void wd_reset_timer(unsigned long param)
2942 {
2943         struct bpctl_dev *pbpctl_dev = (struct bpctl_dev *) param;
2944 #ifdef BP_SELF_TEST
2945         struct sk_buff *skb_tmp;
2946 #endif
2947
2948         if ((pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) &&
2949             ((atomic_read(&pbpctl_dev->wdt_busy)) == 1)) {
2950                 mod_timer(&pbpctl_dev->bp_timer, jiffies + 1);
2951                 return;
2952         }
2953 #ifdef BP_SELF_TEST
2954
2955         if (pbpctl_dev->bp_self_test_flag == 1) {
2956                 skb_tmp = dev_alloc_skb(BPTEST_DATA_LEN + 2);
2957                 if ((skb_tmp) && (pbpctl_dev->ndev) && (pbpctl_dev->bp_tx_data)) {
2958                         memcpy(skb_put(skb_tmp, BPTEST_DATA_LEN),
2959                                pbpctl_dev->bp_tx_data, BPTEST_DATA_LEN);
2960                         skb_tmp->dev = pbpctl_dev->ndev;
2961                         skb_tmp->protocol =
2962                             eth_type_trans(skb_tmp, pbpctl_dev->ndev);
2963                         skb_tmp->ip_summed = CHECKSUM_UNNECESSARY;
2964                         netif_receive_skb(skb_tmp);
2965                         goto bp_timer_reload;
2966                         return;
2967                 }
2968         }
2969 #endif
2970
2971         wdt_timer_reload(pbpctl_dev);
2972 #ifdef BP_SELF_TEST
2973  bp_timer_reload:
2974 #endif
2975         if (pbpctl_dev->reset_time) {
2976                 mod_timer(&pbpctl_dev->bp_timer,
2977                           jiffies + (HZ * pbpctl_dev->reset_time) / 1000);
2978         }
2979 }
2980
2981 /*WAIT_AT_PWRUP 0x80   */
2982 int bp_wait_at_pwup_en(struct bpctl_dev *pbpctl_dev)
2983 {
2984
2985         if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
2986                 if (pbpctl_dev->bp_ext_ver >= BP_FW_EXT_VER8) {
2987                         write_data(pbpctl_dev, BP_WAIT_AT_PWUP_EN);
2988                         msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2989
2990                         return BP_OK;
2991                 }
2992         }
2993         return BP_NOT_CAP;
2994 }
2995
2996 /*DIS_WAIT_AT_PWRUP       0x81 */
2997 int bp_wait_at_pwup_dis(struct bpctl_dev *pbpctl_dev)
2998 {
2999
3000         if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3001
3002                 if (pbpctl_dev->bp_ext_ver >= BP_FW_EXT_VER8) {
3003                         write_data(pbpctl_dev, BP_WAIT_AT_PWUP_DIS);
3004                         msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
3005
3006                         return BP_OK;
3007                 }
3008         }
3009         return BP_NOT_CAP;
3010 }
3011
3012 /*EN_HW_RESET  0x82   */
3013
3014 int bp_hw_reset_en(struct bpctl_dev *pbpctl_dev)
3015 {
3016
3017         if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3018                 if (pbpctl_dev->bp_ext_ver >= BP_FW_EXT_VER8) {
3019                         write_data(pbpctl_dev, BP_HW_RESET_EN);
3020                         msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
3021
3022                         return BP_OK;
3023                 }
3024         }
3025         return BP_NOT_CAP;
3026 }
3027
3028 /*DIS_HW_RESET             0x83   */
3029
3030 int bp_hw_reset_dis(struct bpctl_dev *pbpctl_dev)
3031 {
3032
3033         if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3034                 if (pbpctl_dev->bp_ext_ver >= BP_FW_EXT_VER8) {
3035                         write_data(pbpctl_dev, BP_HW_RESET_DIS);
3036                         msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
3037
3038                         return BP_OK;
3039                 }
3040         }
3041         return BP_NOT_CAP;
3042 }
3043
3044
3045 int wdt_exp_mode(struct bpctl_dev *pbpctl_dev, int mode)
3046 {
3047         uint32_t status_reg = 0, status_reg1 = 0;
3048
3049         if ((pbpctl_dev->bp_caps & (TAP_STATUS_CAP | DISC_CAP)) &&
3050             (pbpctl_dev->bp_caps & BP_CAP)) {
3051                 if (pbpctl_dev->bp_ext_ver >= PXE2TBPI_VER) {
3052
3053                         if ((pbpctl_dev->bp_ext_ver >= 0x8) &&
3054                             (mode == 2) && (pbpctl_dev->bp_caps & DISC_CAP)) {
3055                                 status_reg1 =
3056                                     read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR);
3057                                 if (!(status_reg1 & WDTE_DISC_BPN_MASK))
3058                                         write_reg(pbpctl_dev,
3059                                                   status_reg1 |
3060                                                   WDTE_DISC_BPN_MASK,
3061                                                   STATUS_DISC_REG_ADDR);
3062                                 return BP_OK;
3063                         }
3064                 }
3065                 status_reg = read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR);
3066
3067                 if ((mode == 0) && (pbpctl_dev->bp_caps & BP_CAP)) {
3068                         if (pbpctl_dev->bp_ext_ver >= 0x8) {
3069                                 status_reg1 =
3070                                     read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR);
3071                                 if (status_reg1 & WDTE_DISC_BPN_MASK)
3072                                         write_reg(pbpctl_dev,
3073                                                   status_reg1 &
3074                                                   ~WDTE_DISC_BPN_MASK,
3075                                                   STATUS_DISC_REG_ADDR);
3076                         }
3077                         if (status_reg & WDTE_TAP_BPN_MASK)
3078                                 write_reg(pbpctl_dev,
3079                                           status_reg & ~WDTE_TAP_BPN_MASK,
3080                                           STATUS_TAP_REG_ADDR);
3081                         return BP_OK;
3082
3083                 } else if ((mode == 1) && (pbpctl_dev->bp_caps & TAP_CAP)) {
3084                         if (!(status_reg & WDTE_TAP_BPN_MASK))
3085                                 write_reg(pbpctl_dev,
3086                                           status_reg | WDTE_TAP_BPN_MASK,
3087                                           STATUS_TAP_REG_ADDR);
3088                         /*else return BP_NOT_CAP; */
3089                         return BP_OK;
3090                 }
3091
3092         }
3093         return BP_NOT_CAP;
3094 }
3095
3096 int bypass_fw_ver(struct bpctl_dev *pbpctl_dev)
3097 {
3098         if (is_bypass_fn(pbpctl_dev))
3099                 return read_reg(pbpctl_dev, VER_REG_ADDR);
3100         else
3101                 return BP_NOT_CAP;
3102 }
3103
3104 int bypass_sign_check(struct bpctl_dev *pbpctl_dev)
3105 {
3106
3107         if (is_bypass_fn(pbpctl_dev))
3108                 return (((read_reg(pbpctl_dev, PIC_SIGN_REG_ADDR)) ==
3109                          PIC_SIGN_VALUE) ? 1 : 0);
3110         else
3111                 return BP_NOT_CAP;
3112 }
3113
3114 static int tx_status(struct bpctl_dev *pbpctl_dev)
3115 {
3116         uint32_t ctrl = 0;
3117         struct bpctl_dev *pbpctl_dev_m;
3118         if ((is_bypass_fn(pbpctl_dev)) == 1)
3119                 pbpctl_dev_m = pbpctl_dev;
3120         else
3121                 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
3122         if (pbpctl_dev_m == NULL)
3123                 return BP_NOT_CAP;
3124         if (pbpctl_dev_m->bp_caps_ex & DISC_PORT_CAP_EX) {
3125
3126                 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL);
3127                 if (pbpctl_dev->bp_i80)
3128                         return ((ctrl & BPCTLI_CTRL_SWDPIN1) != 0 ? 0 : 1);
3129                 if (pbpctl_dev->bp_540) {
3130                         ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
3131
3132                         return ((ctrl & BP10G_SDP1_DATA) != 0 ? 0 : 1);
3133                 }
3134
3135         }
3136
3137         if (pbpctl_dev->bp_caps & TX_CTL_CAP) {
3138                 if (PEG5_IF_SERIES(pbpctl_dev->subdevice)) {
3139                         uint16_t mii_reg;
3140                         if (!
3141                             (bp75_read_phy_reg
3142                              (pbpctl_dev, BPCTLI_PHY_CONTROL, &mii_reg))) {
3143                                 if (mii_reg & BPCTLI_MII_CR_POWER_DOWN)
3144                                         return 0;
3145
3146                                 else
3147                                         return 1;
3148                         }
3149                         return -1;
3150                 }
3151
3152                 if (pbpctl_dev->bp_10g9) {
3153                         return ((BP10G_READ_REG(pbpctl_dev, ESDP) &
3154                                  BP10G_SDP3_DATA) != 0 ? 0 : 1);
3155
3156                 } else if (pbpctl_dev->bp_fiber5) {
3157                         ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
3158                         if (ctrl & BPCTLI_CTRL_EXT_SDP6_DATA)
3159                                 return 0;
3160                         return 1;
3161                 } else if (pbpctl_dev->bp_10gb) {
3162                         ctrl = BP10GB_READ_REG(pbpctl_dev, MISC_REG_GPIO);
3163                         BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_GPIO,
3164                                          (ctrl | BP10GB_GPIO0_OE_P1) &
3165                                          ~(BP10GB_GPIO0_SET_P1 |
3166                                            BP10GB_GPIO0_CLR_P1));
3167
3168                         if ((pbpctl_dev->func == 1) || (pbpctl_dev->func == 3))
3169                                 return (((BP10GB_READ_REG
3170                                           (pbpctl_dev,
3171                                            MISC_REG_GPIO)) & BP10GB_GPIO0_P1) !=
3172                                         0 ? 0 : 1);
3173                         else
3174                                 return (((BP10GB_READ_REG
3175                                           (pbpctl_dev,
3176                                            MISC_REG_GPIO)) & BP10GB_GPIO0_P0) !=
3177                                         0 ? 0 : 1);
3178                 }
3179
3180                 if (!pbpctl_dev->bp_10g) {
3181
3182                         ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL);
3183                         if (pbpctl_dev->bp_i80)
3184                                 return ((ctrl & BPCTLI_CTRL_SWDPIN1) !=
3185                                         0 ? 0 : 1);
3186                         if (pbpctl_dev->bp_540) {
3187                                 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
3188
3189                                 return ((ctrl & BP10G_SDP1_DATA) != 0 ? 0 : 1);
3190                         }
3191
3192                         return ((ctrl & BPCTLI_CTRL_SWDPIN0) != 0 ? 0 : 1);
3193                 } else
3194                         return ((BP10G_READ_REG(pbpctl_dev, ESDP) &
3195                                  BP10G_SDP0_DATA) != 0 ? 0 : 1);
3196
3197         }
3198         return BP_NOT_CAP;
3199 }
3200
3201 static int bp_force_link_status(struct bpctl_dev *pbpctl_dev)
3202 {
3203
3204         if (DBI_IF_SERIES(pbpctl_dev->subdevice)) {
3205
3206                 if ((pbpctl_dev->bp_10g) || (pbpctl_dev->bp_10g9)) {
3207                         return ((BP10G_READ_REG(pbpctl_dev, ESDP) &
3208                                  BP10G_SDP1_DIR) != 0 ? 1 : 0);
3209
3210                 }
3211         }
3212         return BP_NOT_CAP;
3213 }
3214
3215 int bypass_from_last_read(struct bpctl_dev *pbpctl_dev)
3216 {
3217         uint32_t ctrl_ext = 0;
3218         struct bpctl_dev *pbpctl_dev_b = NULL;
3219
3220         if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3221                 pbpctl_dev_b = get_status_port_fn(pbpctl_dev);
3222                 if (!pbpctl_dev_b)
3223                         return BP_NOT_CAP;
3224                 ctrl_ext = BPCTL_READ_REG(pbpctl_dev_b, CTRL_EXT);
3225                 BPCTL_BP_WRITE_REG(pbpctl_dev_b, CTRL_EXT,
3226                                    (ctrl_ext & ~BPCTLI_CTRL_EXT_SDP7_DIR));
3227                 ctrl_ext = BPCTL_READ_REG(pbpctl_dev_b, CTRL_EXT);
3228                 if (ctrl_ext & BPCTLI_CTRL_EXT_SDP7_DATA)
3229                         return 0;
3230                 return 1;
3231         } else
3232                 return BP_NOT_CAP;
3233 }
3234
3235 int bypass_status_clear(struct bpctl_dev *pbpctl_dev)
3236 {
3237         struct bpctl_dev *pbpctl_dev_b = NULL;
3238
3239         if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3240                 pbpctl_dev_b = get_status_port_fn(pbpctl_dev);
3241                 if (!pbpctl_dev_b)
3242                         return BP_NOT_CAP;
3243                 send_bypass_clear_pulse(pbpctl_dev_b, 1);
3244                 return 0;
3245         } else
3246                 return BP_NOT_CAP;
3247 }
3248
3249 int bypass_flag_status(struct bpctl_dev *pbpctl_dev)
3250 {
3251
3252         if ((pbpctl_dev->bp_caps & BP_CAP)) {
3253                 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3254                         return ((((read_reg(pbpctl_dev, STATUS_REG_ADDR)) &
3255                                   BYPASS_FLAG_MASK) ==
3256                                  BYPASS_FLAG_MASK) ? 1 : 0);
3257                 }
3258         }
3259         return BP_NOT_CAP;
3260 }
3261
3262 int bypass_flag_status_clear(struct bpctl_dev *pbpctl_dev)
3263 {
3264
3265         if (pbpctl_dev->bp_caps & BP_CAP) {
3266                 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3267                         uint32_t status_reg = 0;
3268                         status_reg = read_reg(pbpctl_dev, STATUS_REG_ADDR);
3269                         write_reg(pbpctl_dev, status_reg & ~BYPASS_FLAG_MASK,
3270                                   STATUS_REG_ADDR);
3271                         return 0;
3272                 }
3273         }
3274         return BP_NOT_CAP;
3275 }
3276
3277 int bypass_change_status(struct bpctl_dev *pbpctl_dev)
3278 {
3279         int ret = BP_NOT_CAP;
3280
3281         if (pbpctl_dev->bp_caps & BP_STATUS_CHANGE_CAP) {
3282                 if (pbpctl_dev->bp_ext_ver >= 0x8) {
3283                         ret = bypass_flag_status(pbpctl_dev);
3284                         bypass_flag_status_clear(pbpctl_dev);
3285                 } else if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3286                         ret = bypass_flag_status(pbpctl_dev);
3287                         bypass_flag_status_clear(pbpctl_dev);
3288                 } else {
3289                         ret = bypass_from_last_read(pbpctl_dev);
3290                         bypass_status_clear(pbpctl_dev);
3291                 }
3292         }
3293         return ret;
3294 }
3295
3296 int bypass_off_status(struct bpctl_dev *pbpctl_dev)
3297 {
3298
3299         if (pbpctl_dev->bp_caps & BP_CAP) {
3300                 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3301                         return ((((read_reg(pbpctl_dev, STATUS_REG_ADDR)) &
3302                                   BYPASS_OFF_MASK) == BYPASS_OFF_MASK) ? 1 : 0);
3303                 }
3304         }
3305         return BP_NOT_CAP;
3306 }
3307
3308 static int bypass_status(struct bpctl_dev *pbpctl_dev)
3309 {
3310         u32 ctrl_ext = 0;
3311         if (pbpctl_dev->bp_caps & BP_CAP) {
3312
3313                 struct bpctl_dev *pbpctl_dev_b = NULL;
3314
3315                 pbpctl_dev_b = get_status_port_fn(pbpctl_dev);
3316                 if (!pbpctl_dev_b)
3317                         return BP_NOT_CAP;
3318
3319                 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
3320
3321                         if (!pbpctl_dev->bp_status_un)
3322                                 return (((BPCTL_READ_REG
3323                                           (pbpctl_dev_b,
3324                                            CTRL_EXT)) &
3325                                          BPCTLI_CTRL_EXT_SDP7_DATA) !=
3326                                         0 ? 1 : 0);
3327                         else
3328                                 return BP_NOT_CAP;
3329                 }
3330                 if (pbpctl_dev->bp_ext_ver >= 0x8) {
3331
3332                         if (pbpctl_dev->bp_10g9) {
3333                                 ctrl_ext = BP10G_READ_REG(pbpctl_dev_b, I2CCTL);
3334                                 BP10G_WRITE_REG(pbpctl_dev_b, I2CCTL,
3335                                                 (ctrl_ext | BP10G_I2C_CLK_OUT));
3336                                 return ((BP10G_READ_REG(pbpctl_dev_b, I2CCTL) &
3337                                          BP10G_I2C_CLK_IN) != 0 ? 0 : 1);
3338
3339                         } else if (pbpctl_dev->bp_540) {
3340                                 return (((BP10G_READ_REG(pbpctl_dev_b, ESDP)) &
3341                                          BP10G_SDP0_DATA) != 0 ? 0 : 1);
3342                         }
3343
3344                         else if ((pbpctl_dev->bp_fiber5)
3345                                  || (pbpctl_dev->bp_i80)) {
3346                                 return (((BPCTL_READ_REG(pbpctl_dev_b, CTRL)) &
3347                                          BPCTLI_CTRL_SWDPIN0) != 0 ? 0 : 1);
3348                         } else if (pbpctl_dev->bp_10gb) {
3349                                 ctrl_ext =
3350                                     BP10GB_READ_REG(pbpctl_dev, MISC_REG_GPIO);
3351                                 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_GPIO,
3352                                                  (ctrl_ext | BP10GB_GPIO3_OE_P0)
3353                                                  & ~(BP10GB_GPIO3_SET_P0 |
3354                                                      BP10GB_GPIO3_CLR_P0));
3355
3356                                 return (((BP10GB_READ_REG
3357                                           (pbpctl_dev,
3358                                            MISC_REG_GPIO)) & BP10GB_GPIO3_P0) !=
3359                                         0 ? 0 : 1);
3360                         }
3361
3362                         else if (!pbpctl_dev->bp_10g)
3363                                 return (((BPCTL_READ_REG
3364                                           (pbpctl_dev_b,
3365                                            CTRL_EXT)) &
3366                                          BPCTLI_CTRL_EXT_SDP7_DATA) !=
3367                                         0 ? 0 : 1);
3368
3369                         else {
3370                                 ctrl_ext = BP10G_READ_REG(pbpctl_dev_b, EODSDP);
3371                                 BP10G_WRITE_REG(pbpctl_dev_b, EODSDP,
3372                                                 (ctrl_ext |
3373                                                  BP10G_SDP7_DATA_OUT));
3374                                 return ((BP10G_READ_REG(pbpctl_dev_b, EODSDP) &
3375                                          BP10G_SDP7_DATA_IN) != 0 ? 0 : 1);
3376                         }
3377
3378                 } else if (pbpctl_dev->media_type == BP_COPPER) {
3379
3380                         return (((BPCTL_READ_REG(pbpctl_dev_b, CTRL)) &
3381                                  BPCTLI_CTRL_SWDPIN1) != 0 ? 1 : 0);
3382                 } else {
3383                         if ((bypass_status_clear(pbpctl_dev)) >= 0)
3384                                 return bypass_from_last_read(pbpctl_dev);
3385                 }
3386
3387         }
3388         return BP_NOT_CAP;
3389 }
3390
3391 int default_pwron_status(struct bpctl_dev *pbpctl_dev)
3392 {
3393
3394         if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3395                 if (pbpctl_dev->bp_caps & BP_PWUP_CTL_CAP) {
3396                         if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3397                                 return ((((read_reg
3398                                            (pbpctl_dev,
3399                                             STATUS_REG_ADDR)) & DFLT_PWRON_MASK)
3400                                          == DFLT_PWRON_MASK) ? 0 : 1);
3401                         }
3402                 }               /*else if ((!pbpctl_dev->bp_caps&BP_DIS_CAP)&&
3403                                    (pbpctl_dev->bp_caps&BP_PWUP_ON_CAP))
3404                                    return 1; */
3405         }
3406         return BP_NOT_CAP;
3407 }
3408
3409 static int default_pwroff_status(struct bpctl_dev *pbpctl_dev)
3410 {
3411
3412         /*if ((!pbpctl_dev->bp_caps&BP_DIS_CAP)&&
3413            (pbpctl_dev->bp_caps&BP_PWOFF_ON_CAP))
3414            return 1; */
3415         if ((pbpctl_dev->bp_caps & SW_CTL_CAP)
3416             && (pbpctl_dev->bp_caps & BP_PWOFF_CTL_CAP)) {
3417                 return ((((read_reg(pbpctl_dev, STATUS_REG_ADDR)) &
3418                           DFLT_PWROFF_MASK) == DFLT_PWROFF_MASK) ? 0 : 1);
3419         }
3420         return BP_NOT_CAP;
3421 }
3422
3423 int dis_bypass_cap_status(struct bpctl_dev *pbpctl_dev)
3424 {
3425
3426         if (pbpctl_dev->bp_caps & BP_DIS_CAP) {
3427                 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3428                         return ((((read_reg(pbpctl_dev, STATUS_REG_ADDR)) &
3429                                   DIS_BYPASS_CAP_MASK) ==
3430                                  DIS_BYPASS_CAP_MASK) ? 1 : 0);
3431                 }
3432         }
3433         return BP_NOT_CAP;
3434 }
3435
3436 int cmd_en_status(struct bpctl_dev *pbpctl_dev)
3437 {
3438
3439         if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3440                 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3441                         return ((((read_reg(pbpctl_dev, STATUS_REG_ADDR)) &
3442                                   CMND_EN_MASK) == CMND_EN_MASK) ? 1 : 0);
3443                 }
3444         }
3445         return BP_NOT_CAP;
3446 }
3447
3448 int wdt_en_status(struct bpctl_dev *pbpctl_dev)
3449 {
3450
3451         if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
3452                 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3453                         return ((((read_reg(pbpctl_dev, STATUS_REG_ADDR)) &
3454                                   WDT_EN_MASK) == WDT_EN_MASK) ? 1 : 0);
3455                 }
3456         }
3457         return BP_NOT_CAP;
3458 }
3459
3460 int wdt_programmed(struct bpctl_dev *pbpctl_dev, int *timeout)
3461 {
3462         int ret = 0;
3463         if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
3464                 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3465                         if ((read_reg(pbpctl_dev, STATUS_REG_ADDR)) &
3466                             WDT_EN_MASK) {
3467                                 u8 wdt_val;
3468                                 wdt_val = read_reg(pbpctl_dev, WDT_REG_ADDR);
3469                                 *timeout = (1 << wdt_val) * 100;
3470                         } else
3471                                 *timeout = 0;
3472                 } else {
3473                         int curr_wdt_status = pbpctl_dev->wdt_status;
3474                         if (curr_wdt_status == WDT_STATUS_UNKNOWN)
3475                                 *timeout = -1;
3476                         else
3477                                 *timeout =
3478                                     curr_wdt_status ==
3479                                     0 ? 0 : pbpctl_dev->bypass_timer_interval;
3480                 }
3481         } else
3482                 ret = BP_NOT_CAP;
3483         return ret;
3484 }
3485
3486 int bypass_support(struct bpctl_dev *pbpctl_dev)
3487 {
3488         int ret = 0;
3489
3490         if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3491                 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER) {
3492                         ret =
3493                             ((((read_reg(pbpctl_dev, PRODUCT_CAP_REG_ADDR)) &
3494                                BYPASS_SUPPORT_MASK) ==
3495                               BYPASS_SUPPORT_MASK) ? 1 : 0);
3496                 } else if (pbpctl_dev->bp_ext_ver == PXG2BPI_VER)
3497                         ret = 1;
3498         } else
3499                 ret = BP_NOT_CAP;
3500         return ret;
3501 }
3502
3503 int tap_support(struct bpctl_dev *pbpctl_dev)
3504 {
3505         int ret = 0;
3506
3507         if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3508                 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER) {
3509                         ret =
3510                             ((((read_reg(pbpctl_dev, PRODUCT_CAP_REG_ADDR)) &
3511                                TAP_SUPPORT_MASK) == TAP_SUPPORT_MASK) ? 1 : 0);
3512                 } else if (pbpctl_dev->bp_ext_ver == PXG2BPI_VER)
3513                         ret = 0;
3514         } else
3515                 ret = BP_NOT_CAP;
3516         return ret;
3517 }
3518
3519 int normal_support(struct bpctl_dev *pbpctl_dev)
3520 {
3521         int ret = BP_NOT_CAP;
3522
3523         if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3524                 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER) {
3525                         ret =
3526                             ((((read_reg(pbpctl_dev, PRODUCT_CAP_REG_ADDR)) &
3527                                NORMAL_UNSUPPORT_MASK) ==
3528                               NORMAL_UNSUPPORT_MASK) ? 0 : 1);
3529                 } else
3530                         ret = 1;
3531         }
3532         return ret;
3533 }
3534
3535 int get_bp_prod_caps(struct bpctl_dev *pbpctl_dev)
3536 {
3537         if ((pbpctl_dev->bp_caps & SW_CTL_CAP) &&
3538             (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER))
3539                 return read_reg(pbpctl_dev, PRODUCT_CAP_REG_ADDR);
3540         return BP_NOT_CAP;
3541
3542 }
3543
3544 int tap_flag_status(struct bpctl_dev *pbpctl_dev)
3545 {
3546
3547         if (pbpctl_dev->bp_caps & TAP_STATUS_CAP) {
3548                 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER)
3549                         return ((((read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR)) &
3550                                   TAP_FLAG_MASK) == TAP_FLAG_MASK) ? 1 : 0);
3551
3552         }
3553         return BP_NOT_CAP;
3554 }
3555
3556 int tap_flag_status_clear(struct bpctl_dev *pbpctl_dev)
3557 {
3558         uint32_t status_reg = 0;
3559         if (pbpctl_dev->bp_caps & TAP_STATUS_CAP) {
3560                 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER) {
3561                         status_reg = read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR);
3562                         write_reg(pbpctl_dev, status_reg & ~TAP_FLAG_MASK,
3563                                   STATUS_TAP_REG_ADDR);
3564                         return 0;
3565                 }
3566         }
3567         return BP_NOT_CAP;
3568 }
3569
3570 int tap_change_status(struct bpctl_dev *pbpctl_dev)
3571 {
3572         int ret = BP_NOT_CAP;
3573         if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER) {
3574                 if (pbpctl_dev->bp_caps & TAP_CAP) {
3575                         if (pbpctl_dev->bp_caps & BP_CAP) {
3576                                 ret = tap_flag_status(pbpctl_dev);
3577                                 tap_flag_status_clear(pbpctl_dev);
3578                         } else {
3579                                 ret = bypass_from_last_read(pbpctl_dev);
3580                                 bypass_status_clear(pbpctl_dev);
3581                         }
3582                 }
3583         }
3584         return ret;
3585 }
3586
3587 int tap_off_status(struct bpctl_dev *pbpctl_dev)
3588 {
3589         if (pbpctl_dev->bp_caps & TAP_CAP) {
3590                 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER)
3591                         return ((((read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR)) &
3592                                   TAP_OFF_MASK) == TAP_OFF_MASK) ? 1 : 0);
3593         }
3594         return BP_NOT_CAP;
3595 }
3596
3597 int tap_status(struct bpctl_dev *pbpctl_dev)
3598 {
3599         u32 ctrl_ext = 0;
3600
3601         if (pbpctl_dev->bp_caps & TAP_CAP) {
3602                 struct bpctl_dev *pbpctl_dev_b = NULL;
3603
3604                 pbpctl_dev_b = get_status_port_fn(pbpctl_dev);
3605                 if (!pbpctl_dev_b)
3606                         return BP_NOT_CAP;
3607
3608                 if (pbpctl_dev->bp_ext_ver >= 0x8) {
3609                         if (!pbpctl_dev->bp_10g)
3610                                 return (((BPCTL_READ_REG
3611                                           (pbpctl_dev_b,
3612                                            CTRL_EXT)) &
3613                                          BPCTLI_CTRL_EXT_SDP6_DATA) !=
3614                                         0 ? 0 : 1);
3615                         else {
3616                                 ctrl_ext = BP10G_READ_REG(pbpctl_dev_b, EODSDP);
3617                                 BP10G_WRITE_REG(pbpctl_dev_b, EODSDP,
3618                                                 (ctrl_ext |
3619                                                  BP10G_SDP6_DATA_OUT));
3620                                 return ((BP10G_READ_REG(pbpctl_dev_b, EODSDP) &
3621                                          BP10G_SDP6_DATA_IN) != 0 ? 0 : 1);
3622                         }
3623
3624                 } else if (pbpctl_dev->media_type == BP_COPPER)
3625                         return (((BPCTL_READ_REG(pbpctl_dev, CTRL)) &
3626                                  BPCTLI_CTRL_SWDPIN0) != 0 ? 1 : 0);
3627                 else {
3628                         if ((bypass_status_clear(pbpctl_dev)) >= 0)
3629                                 return bypass_from_last_read(pbpctl_dev);
3630                 }
3631
3632         }
3633         return BP_NOT_CAP;
3634 }
3635
3636 int default_pwron_tap_status(struct bpctl_dev *pbpctl_dev)
3637 {
3638         if (pbpctl_dev->bp_caps & TAP_PWUP_CTL_CAP) {
3639                 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER)
3640                         return ((((read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR)) &
3641                                   DFLT_PWRON_TAP_MASK) ==
3642                                  DFLT_PWRON_TAP_MASK) ? 1 : 0);
3643         }
3644         return BP_NOT_CAP;
3645 }
3646
3647 int dis_tap_cap_status(struct bpctl_dev *pbpctl_dev)
3648 {
3649         if (pbpctl_dev->bp_caps & TAP_PWUP_CTL_CAP) {
3650                 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER)
3651                         return ((((read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR)) &
3652                                   DIS_TAP_CAP_MASK) ==
3653                                  DIS_TAP_CAP_MASK) ? 1 : 0);
3654         }
3655         return BP_NOT_CAP;
3656 }
3657
3658 int disc_flag_status(struct bpctl_dev *pbpctl_dev)
3659 {
3660
3661         if (pbpctl_dev->bp_caps & DISC_CAP) {
3662                 if (pbpctl_dev->bp_ext_ver >= 0x8)
3663                         return ((((read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR)) &
3664                                   DISC_FLAG_MASK) == DISC_FLAG_MASK) ? 1 : 0);
3665
3666         }
3667         return BP_NOT_CAP;
3668 }
3669
3670 int disc_flag_status_clear(struct bpctl_dev *pbpctl_dev)
3671 {
3672         uint32_t status_reg = 0;
3673         if (pbpctl_dev->bp_caps & DISC_CAP) {
3674                 if (pbpctl_dev->bp_ext_ver >= 0x8) {
3675                         status_reg = read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR);
3676                         write_reg(pbpctl_dev, status_reg & ~DISC_FLAG_MASK,
3677                                   STATUS_DISC_REG_ADDR);
3678                         return BP_OK;
3679                 }
3680         }
3681         return BP_NOT_CAP;
3682 }
3683
3684 int disc_change_status(struct bpctl_dev *pbpctl_dev)
3685 {
3686         int ret = BP_NOT_CAP;
3687         if (pbpctl_dev->bp_caps & DISC_CAP) {
3688                 ret = disc_flag_status(pbpctl_dev);
3689                 disc_flag_status_clear(pbpctl_dev);
3690                 return ret;
3691         }
3692         return BP_NOT_CAP;
3693 }
3694
3695 int disc_off_status(struct bpctl_dev *pbpctl_dev)
3696 {
3697         struct bpctl_dev *pbpctl_dev_b = NULL;
3698         u32 ctrl_ext = 0;
3699
3700         if (pbpctl_dev->bp_caps & DISC_CAP) {
3701                 pbpctl_dev_b = get_status_port_fn(pbpctl_dev);
3702                 if (!pbpctl_dev_b)
3703                         return BP_NOT_CAP;
3704                 if (DISCF_IF_SERIES(pbpctl_dev->subdevice))
3705                         return ((((read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR)) &
3706                                   DISC_OFF_MASK) == DISC_OFF_MASK) ? 1 : 0);
3707
3708                 if (pbpctl_dev->bp_i80) {
3709                         return (((BPCTL_READ_REG(pbpctl_dev_b, CTRL_EXT)) &
3710                                  BPCTLI_CTRL_EXT_SDP6_DATA) != 0 ? 1 : 0);
3711
3712                 }
3713                 if (pbpctl_dev->bp_540) {
3714                         ctrl_ext = BP10G_READ_REG(pbpctl_dev_b, ESDP);
3715                         return ((BP10G_READ_REG(pbpctl_dev_b, ESDP) &
3716                                  BP10G_SDP2_DATA) != 0 ? 1 : 0);
3717
3718                 }
3719                 if (pbpctl_dev->media_type == BP_COPPER) {
3720
3721 #if 0
3722                         return ((((read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR)) &
3723                                   DISC_OFF_MASK) == DISC_OFF_MASK) ? 1 : 0);
3724 #endif
3725                         if (!pbpctl_dev->bp_10g)
3726                                 return (((BPCTL_READ_REG(pbpctl_dev_b, CTRL)) &
3727                                          BPCTLI_CTRL_SWDPIN1) != 0 ? 1 : 0);
3728                         else
3729                                 return ((BP10G_READ_REG(pbpctl_dev_b, ESDP) &
3730                                          BP10G_SDP1_DATA) != 0 ? 1 : 0);
3731
3732                 } else {
3733
3734                         if (pbpctl_dev->bp_10g9) {
3735                                 ctrl_ext = BP10G_READ_REG(pbpctl_dev_b, I2CCTL);
3736                                 BP10G_WRITE_REG(pbpctl_dev_b, I2CCTL,
3737                                                 (ctrl_ext |
3738                                                  BP10G_I2C_DATA_OUT));
3739                                 return ((BP10G_READ_REG(pbpctl_dev_b, I2CCTL) &
3740                                          BP10G_I2C_DATA_IN) != 0 ? 1 : 0);
3741
3742                         } else if (pbpctl_dev->bp_fiber5) {
3743                                 return (((BPCTL_READ_REG(pbpctl_dev_b, CTRL)) &
3744                                          BPCTLI_CTRL_SWDPIN1) != 0 ? 1 : 0);
3745                         } else if (pbpctl_dev->bp_10gb) {
3746                                 ctrl_ext =
3747                                     BP10GB_READ_REG(pbpctl_dev, MISC_REG_GPIO);
3748                                 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_GPIO,
3749                                                  (ctrl_ext | BP10GB_GPIO3_OE_P1)
3750                                                  & ~(BP10GB_GPIO3_SET_P1 |
3751                                                      BP10GB_GPIO3_CLR_P1));
3752
3753                                 return (((BP10GB_READ_REG
3754                                           (pbpctl_dev,
3755                                            MISC_REG_GPIO)) & BP10GB_GPIO3_P1) !=
3756                                         0 ? 1 : 0);
3757                         }
3758                         if (!pbpctl_dev->bp_10g) {
3759
3760                                 return (((BPCTL_READ_REG
3761                                           (pbpctl_dev_b,
3762                                            CTRL_EXT)) &
3763                                          BPCTLI_CTRL_EXT_SDP6_DATA) !=
3764                                         0 ? 1 : 0);
3765                         } else {
3766                                 ctrl_ext = BP10G_READ_REG(pbpctl_dev_b, EODSDP);
3767                                 BP10G_WRITE_REG(pbpctl_dev_b, EODSDP,
3768                                                 (ctrl_ext |
3769                                                  BP10G_SDP6_DATA_OUT));
3770                                 return (((BP10G_READ_REG(pbpctl_dev_b, EODSDP))
3771                                          & BP10G_SDP6_DATA_IN) != 0 ? 1 : 0);
3772                         }
3773
3774                 }
3775         }
3776         return BP_NOT_CAP;
3777 }
3778
3779 static int disc_status(struct bpctl_dev *pbpctl_dev)
3780 {
3781         int ctrl = 0;
3782         if (pbpctl_dev->bp_caps & DISC_CAP) {
3783                 ctrl = disc_off_status(pbpctl_dev);
3784                 if (ctrl < 0)
3785                         return ctrl;
3786                 return ((ctrl == 0) ? 1 : 0);
3787         }
3788         return BP_NOT_CAP;
3789 }
3790
3791 int default_pwron_disc_status(struct bpctl_dev *pbpctl_dev)
3792 {
3793         if (pbpctl_dev->bp_caps & DISC_PWUP_CTL_CAP) {
3794                 if (pbpctl_dev->bp_ext_ver >= 0x8)
3795                         return ((((read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR)) &
3796                                   DFLT_PWRON_DISC_MASK) ==
3797                                  DFLT_PWRON_DISC_MASK) ? 1 : 0);
3798         }
3799         return BP_NOT_CAP;
3800 }
3801
3802 int dis_disc_cap_status(struct bpctl_dev *pbpctl_dev)
3803 {
3804         if (pbpctl_dev->bp_caps & DIS_DISC_CAP) {
3805                 if (pbpctl_dev->bp_ext_ver >= 0x8)
3806                         return ((((read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR)) &
3807                                   DIS_DISC_CAP_MASK) ==
3808                                  DIS_DISC_CAP_MASK) ? 1 : 0);
3809         }
3810         return BP_NOT_CAP;
3811 }
3812
3813 int disc_port_status(struct bpctl_dev *pbpctl_dev)
3814 {
3815         int ret = BP_NOT_CAP;
3816         struct bpctl_dev *pbpctl_dev_m;
3817
3818         if ((is_bypass_fn(pbpctl_dev)) == 1)
3819                 pbpctl_dev_m = pbpctl_dev;
3820         else
3821                 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
3822         if (pbpctl_dev_m == NULL)
3823                 return BP_NOT_CAP;
3824
3825         if (pbpctl_dev_m->bp_caps_ex & DISC_PORT_CAP_EX) {
3826                 if (is_bypass_fn(pbpctl_dev) == 1) {
3827                         return ((((read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR)) &
3828                                   TX_DISA_MASK) == TX_DISA_MASK) ? 1 : 0);
3829                 } else
3830                         return ((((read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR)) &
3831                                   TX_DISB_MASK) == TX_DISB_MASK) ? 1 : 0);
3832
3833         }
3834         return ret;
3835 }
3836
3837 int default_pwron_disc_port_status(struct bpctl_dev *pbpctl_dev)
3838 {
3839         int ret = BP_NOT_CAP;
3840         struct bpctl_dev *pbpctl_dev_m;
3841
3842         if ((is_bypass_fn(pbpctl_dev)) == 1)
3843                 pbpctl_dev_m = pbpctl_dev;
3844         else
3845                 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
3846         if (pbpctl_dev_m == NULL)
3847                 return BP_NOT_CAP;
3848
3849         if (pbpctl_dev_m->bp_caps_ex & DISC_PORT_CAP_EX) {
3850                 if (is_bypass_fn(pbpctl_dev) == 1)
3851                         return ret;
3852                 /*  return((((read_reg(pbpctl_dev,STATUS_TAP_REG_ADDR)) & TX_DISA_MASK)==TX_DISA_MASK)?1:0); */
3853                 else
3854                         return ret;
3855                 /*   return((((read_reg(pbpctl_dev,STATUS_TAP_REG_ADDR)) & TX_DISA_MASK)==TX_DISA_MASK)?1:0); */
3856
3857         }
3858         return ret;
3859 }
3860
3861 int wdt_exp_mode_status(struct bpctl_dev *pbpctl_dev)
3862 {
3863         if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
3864                 if (pbpctl_dev->bp_ext_ver <= PXG2BPI_VER)
3865                         return 0;       /* bypass mode */
3866                 else if (pbpctl_dev->bp_ext_ver == PXG2TBPI_VER)
3867                         return 1;       /* tap mode */
3868                 else if (pbpctl_dev->bp_ext_ver >= PXE2TBPI_VER) {
3869                         if (pbpctl_dev->bp_ext_ver >= 0x8) {
3870                                 if (((read_reg
3871                                       (pbpctl_dev,
3872                                        STATUS_DISC_REG_ADDR)) &
3873                                      WDTE_DISC_BPN_MASK) == WDTE_DISC_BPN_MASK)
3874                                         return 2;
3875                         }
3876                         return ((((read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR)) &
3877                                   WDTE_TAP_BPN_MASK) ==
3878                                  WDTE_TAP_BPN_MASK) ? 1 : 0);
3879                 }
3880         }
3881         return BP_NOT_CAP;
3882 }
3883
3884 int tpl2_flag_status(struct bpctl_dev *pbpctl_dev)
3885 {
3886
3887         if (pbpctl_dev->bp_caps_ex & TPL2_CAP_EX) {
3888                 return ((((read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR)) &
3889                           TPL2_FLAG_MASK) == TPL2_FLAG_MASK) ? 1 : 0);
3890
3891         }
3892         return BP_NOT_CAP;
3893 }
3894
3895 int tpl_hw_status(struct bpctl_dev *pbpctl_dev)
3896 {
3897         struct bpctl_dev *pbpctl_dev_b = NULL;
3898
3899         pbpctl_dev_b = get_status_port_fn(pbpctl_dev);
3900         if (!pbpctl_dev_b)
3901                 return BP_NOT_CAP;
3902
3903         if (TPL_IF_SERIES(pbpctl_dev->subdevice))
3904                 return (((BPCTL_READ_REG(pbpctl_dev, CTRL)) &
3905                          BPCTLI_CTRL_SWDPIN0) != 0 ? 1 : 0);
3906         return BP_NOT_CAP;
3907 }
3908
3909
3910 int bp_wait_at_pwup_status(struct bpctl_dev *pbpctl_dev)
3911 {
3912         if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3913                 if (pbpctl_dev->bp_ext_ver >= 0x8)
3914                         return ((((read_reg(pbpctl_dev, CONT_CONFIG_REG_ADDR)) &
3915                                   WAIT_AT_PWUP_MASK) ==
3916                                  WAIT_AT_PWUP_MASK) ? 1 : 0);
3917         }
3918         return BP_NOT_CAP;
3919 }
3920
3921 int bp_hw_reset_status(struct bpctl_dev *pbpctl_dev)
3922 {
3923
3924         if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3925
3926                 if (pbpctl_dev->bp_ext_ver >= 0x8)
3927                         return ((((read_reg(pbpctl_dev, CONT_CONFIG_REG_ADDR)) &
3928                                   EN_HW_RESET_MASK) ==
3929                                  EN_HW_RESET_MASK) ? 1 : 0);
3930         }
3931         return BP_NOT_CAP;
3932 }
3933
3934
3935 int std_nic_status(struct bpctl_dev *pbpctl_dev)
3936 {
3937         int status_val = 0;
3938
3939         if (pbpctl_dev->bp_caps & STD_NIC_CAP) {
3940                 if (INTEL_IF_SERIES(pbpctl_dev->subdevice))
3941                         return BP_NOT_CAP;
3942                 if (pbpctl_dev->bp_ext_ver >= BP_FW_EXT_VER8) {
3943                         return ((((read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR)) &
3944                                   STD_NIC_ON_MASK) == STD_NIC_ON_MASK) ? 1 : 0);
3945                 }
3946
3947                 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3948                         if (pbpctl_dev->bp_caps & BP_CAP) {
3949                                 status_val =
3950                                     read_reg(pbpctl_dev, STATUS_REG_ADDR);
3951                                 if (((!(status_val & WDT_EN_MASK))
3952                                      && ((status_val & STD_NIC_MASK) ==
3953                                          STD_NIC_MASK)))
3954                                         status_val = 1;
3955                                 else
3956                                         return 0;
3957                         }
3958                         if (pbpctl_dev->bp_caps & TAP_CAP) {
3959                                 status_val =
3960                                     read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR);
3961                                 if ((status_val & STD_NIC_TAP_MASK) ==
3962                                     STD_NIC_TAP_MASK)
3963                                         status_val = 1;
3964                                 else
3965                                         return 0;
3966                         }
3967                         if (pbpctl_dev->bp_caps & TAP_CAP) {
3968                                 if ((disc_off_status(pbpctl_dev)))
3969                                         status_val = 1;
3970                                 else
3971                                         return 0;
3972                         }
3973
3974                         return status_val;
3975                 }
3976         }
3977         return BP_NOT_CAP;
3978 }
3979
3980 /******************************************************/
3981 /**************SW_INIT*********************************/
3982 /******************************************************/
3983 void bypass_caps_init(struct bpctl_dev *pbpctl_dev)
3984 {
3985         u_int32_t ctrl_ext = 0;
3986         struct bpctl_dev *pbpctl_dev_m = NULL;
3987
3988 #ifdef BYPASS_DEBUG
3989         int ret = 0;
3990         if (!(INTEL_IF_SERIES(adapter->bp_device_block.subdevice))) {
3991                 ret = read_reg(pbpctl_dev, VER_REG_ADDR);
3992                 printk("VER_REG reg1=%x\n", ret);
3993                 ret = read_reg(pbpctl_dev, PRODUCT_CAP_REG_ADDR);
3994                 printk("PRODUCT_CAP reg=%x\n", ret);
3995                 ret = read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR);
3996                 printk("STATUS_TAP reg1=%x\n", ret);
3997                 ret = read_reg(pbpctl_dev, 0x7);
3998                 printk("SIG_REG reg1=%x\n", ret);
3999                 ret = read_reg(pbpctl_dev, STATUS_REG_ADDR);
4000                 printk("STATUS_REG_ADDR=%x\n", ret);
4001                 ret = read_reg(pbpctl_dev, WDT_REG_ADDR);
4002                 printk("WDT_REG_ADDR=%x\n", ret);
4003                 ret = read_reg(pbpctl_dev, TMRL_REG_ADDR);
4004                 printk("TMRL_REG_ADDR=%x\n", ret);
4005                 ret = read_reg(pbpctl_dev, TMRH_REG_ADDR);
4006                 printk("TMRH_REG_ADDR=%x\n", ret);
4007         }
4008 #endif
4009         if ((pbpctl_dev->bp_fiber5) || (pbpctl_dev->bp_10g9)) {
4010                 pbpctl_dev->media_type = BP_FIBER;
4011         } else if (pbpctl_dev->bp_10gb) {
4012                 if (BP10GB_CX4_SERIES(pbpctl_dev->subdevice))
4013                         pbpctl_dev->media_type = BP_CX4;
4014                 else
4015                         pbpctl_dev->media_type = BP_FIBER;
4016
4017         }
4018
4019         else if (pbpctl_dev->bp_540)
4020                 pbpctl_dev->media_type = BP_NONE;
4021         else if (!pbpctl_dev->bp_10g) {
4022
4023                 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
4024                 if ((ctrl_ext & BPCTLI_CTRL_EXT_LINK_MODE_MASK) == 0x0)
4025                         pbpctl_dev->media_type = BP_COPPER;
4026                 else
4027                         pbpctl_dev->media_type = BP_FIBER;
4028
4029         } else {
4030                 if (BP10G_CX4_SERIES(pbpctl_dev->subdevice))
4031                         pbpctl_dev->media_type = BP_CX4;
4032                 else
4033                         pbpctl_dev->media_type = BP_FIBER;
4034         }
4035
4036         if (is_bypass_fn(pbpctl_dev)) {
4037
4038                 pbpctl_dev->bp_caps |= BP_PWOFF_ON_CAP;
4039                 if (pbpctl_dev->media_type == BP_FIBER)
4040                         pbpctl_dev->bp_caps |=
4041                             (TX_CTL_CAP | TX_STATUS_CAP | TPL_CAP);
4042
4043                 if (TPL_IF_SERIES(pbpctl_dev->subdevice))
4044                         pbpctl_dev->bp_caps |= TPL_CAP;
4045
4046                 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
4047                         pbpctl_dev->bp_caps |=
4048                             (BP_CAP | BP_STATUS_CAP | SW_CTL_CAP |
4049                              BP_PWUP_ON_CAP | BP_PWUP_OFF_CAP | BP_PWOFF_OFF_CAP
4050                              | WD_CTL_CAP | WD_STATUS_CAP | STD_NIC_CAP |
4051                              WD_TIMEOUT_CAP);
4052
4053                         pbpctl_dev->bp_ext_ver = OLD_IF_VER;
4054                         return;
4055                 }
4056
4057                 if ((pbpctl_dev->bp_fw_ver == 0xff) &&
4058                     OLD_IF_SERIES(pbpctl_dev->subdevice)) {
4059
4060                         pbpctl_dev->bp_caps |=
4061                             (BP_CAP | BP_STATUS_CAP | BP_STATUS_CHANGE_CAP |
4062                              SW_CTL_CAP | BP_PWUP_ON_CAP | WD_CTL_CAP |
4063                              WD_STATUS_CAP | WD_TIMEOUT_CAP);
4064
4065                         pbpctl_dev->bp_ext_ver = OLD_IF_VER;
4066                         return;
4067                 }
4068
4069                 else {
4070                         switch (pbpctl_dev->bp_fw_ver) {
4071                         case BP_FW_VER_A0:
4072                         case BP_FW_VER_A1:{
4073                                         pbpctl_dev->bp_ext_ver =
4074                                             (pbpctl_dev->
4075                                              bp_fw_ver & EXT_VER_MASK);
4076                                         break;
4077                                 }
4078                         default:{
4079                                         if ((bypass_sign_check(pbpctl_dev)) !=
4080                                             1) {
4081                                                 pbpctl_dev->bp_caps = 0;
4082                                                 return;
4083                                         }
4084                                         pbpctl_dev->bp_ext_ver =
4085                                             (pbpctl_dev->
4086                                              bp_fw_ver & EXT_VER_MASK);
4087                                 }
4088                         }
4089                 }
4090
4091                 if (pbpctl_dev->bp_ext_ver == PXG2BPI_VER)
4092                         pbpctl_dev->bp_caps |=
4093                             (BP_CAP | BP_STATUS_CAP | BP_STATUS_CHANGE_CAP |
4094                              SW_CTL_CAP | BP_DIS_CAP | BP_DIS_STATUS_CAP |
4095                              BP_PWUP_ON_CAP | BP_PWUP_OFF_CAP | BP_PWUP_CTL_CAP
4096                              | WD_CTL_CAP | STD_NIC_CAP | WD_STATUS_CAP |
4097                              WD_TIMEOUT_CAP);
4098                 else if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER) {
4099                         int cap_reg;
4100
4101                         pbpctl_dev->bp_caps |=
4102                             (SW_CTL_CAP | WD_CTL_CAP | WD_STATUS_CAP |
4103                              WD_TIMEOUT_CAP);
4104                         cap_reg = get_bp_prod_caps(pbpctl_dev);
4105
4106                         if ((cap_reg & NORMAL_UNSUPPORT_MASK) ==
4107                             NORMAL_UNSUPPORT_MASK)
4108                                 pbpctl_dev->bp_caps |= NIC_CAP_NEG;
4109                         else
4110                                 pbpctl_dev->bp_caps |= STD_NIC_CAP;
4111
4112                         if ((normal_support(pbpctl_dev)) == 1)
4113
4114                                 pbpctl_dev->bp_caps |= STD_NIC_CAP;
4115
4116                         else
4117                                 pbpctl_dev->bp_caps |= NIC_CAP_NEG;
4118                         if ((cap_reg & BYPASS_SUPPORT_MASK) ==
4119                             BYPASS_SUPPORT_MASK) {
4120                                 pbpctl_dev->bp_caps |=
4121                                     (BP_CAP | BP_STATUS_CAP |
4122                                      BP_STATUS_CHANGE_CAP | BP_DIS_CAP |
4123                                      BP_DIS_STATUS_CAP | BP_PWUP_ON_CAP |
4124                                      BP_PWUP_OFF_CAP | BP_PWUP_CTL_CAP);
4125                                 if (pbpctl_dev->bp_ext_ver >= BP_FW_EXT_VER7)
4126                                         pbpctl_dev->bp_caps |=
4127                                             BP_PWOFF_ON_CAP | BP_PWOFF_OFF_CAP |
4128                                             BP_PWOFF_CTL_CAP;
4129                         }
4130                         if ((cap_reg & TAP_SUPPORT_MASK) == TAP_SUPPORT_MASK) {
4131                                 pbpctl_dev->bp_caps |=
4132                                     (TAP_CAP | TAP_STATUS_CAP |
4133                                      TAP_STATUS_CHANGE_CAP | TAP_DIS_CAP |
4134                                      TAP_DIS_STATUS_CAP | TAP_PWUP_ON_CAP |
4135                                      TAP_PWUP_OFF_CAP | TAP_PWUP_CTL_CAP);
4136                         }
4137                         if (pbpctl_dev->bp_ext_ver >= BP_FW_EXT_VER8) {
4138                                 if ((cap_reg & DISC_SUPPORT_MASK) ==
4139                                     DISC_SUPPORT_MASK)
4140                                         pbpctl_dev->bp_caps |=
4141                                             (DISC_CAP | DISC_DIS_CAP |
4142                                              DISC_PWUP_CTL_CAP);
4143                                 if ((cap_reg & TPL2_SUPPORT_MASK) ==
4144                                     TPL2_SUPPORT_MASK) {
4145                                         pbpctl_dev->bp_caps_ex |= TPL2_CAP_EX;
4146                                         pbpctl_dev->bp_caps |= TPL_CAP;
4147                                         pbpctl_dev->bp_tpl_flag =
4148                                             tpl2_flag_status(pbpctl_dev);
4149                                 }
4150
4151                         }
4152
4153                         if (pbpctl_dev->bp_ext_ver >= BP_FW_EXT_VER9) {
4154                                 if ((cap_reg & DISC_PORT_SUPPORT_MASK) ==
4155                                     DISC_PORT_SUPPORT_MASK) {
4156                                         pbpctl_dev->bp_caps_ex |=
4157                                             DISC_PORT_CAP_EX;
4158                                         pbpctl_dev->bp_caps |=
4159                                             (TX_CTL_CAP | TX_STATUS_CAP);
4160                                 }
4161
4162                         }
4163
4164                 }
4165                 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
4166                         if ((read_reg(pbpctl_dev, STATUS_REG_ADDR)) &
4167                             WDT_EN_MASK)
4168                                 pbpctl_dev->wdt_status = WDT_STATUS_EN;
4169                         else
4170                                 pbpctl_dev->wdt_status = WDT_STATUS_DIS;
4171                 }
4172
4173         } else if ((P2BPFI_IF_SERIES(pbpctl_dev->subdevice)) ||
4174                    (PEGF5_IF_SERIES(pbpctl_dev->subdevice)) ||
4175                    (PEGF80_IF_SERIES(pbpctl_dev->subdevice)) ||
4176                    (BP10G9_IF_SERIES(pbpctl_dev->subdevice))) {
4177                 pbpctl_dev->bp_caps |= (TX_CTL_CAP | TX_STATUS_CAP);
4178         }
4179         if ((pbpctl_dev->subdevice & 0xa00) == 0xa00)
4180                 pbpctl_dev->bp_caps |= (TX_CTL_CAP | TX_STATUS_CAP);
4181         if (PEG5_IF_SERIES(pbpctl_dev->subdevice))
4182                 pbpctl_dev->bp_caps |= (TX_CTL_CAP | TX_STATUS_CAP);
4183
4184         if (BP10GB_IF_SERIES(pbpctl_dev->subdevice))
4185                 pbpctl_dev->bp_caps &= ~(TX_CTL_CAP | TX_STATUS_CAP);
4186
4187         pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
4188         if (pbpctl_dev_m != NULL) {
4189                 int cap_reg = 0;
4190                 if (pbpctl_dev_m->bp_ext_ver >= 0x9) {
4191                         cap_reg = get_bp_prod_caps(pbpctl_dev_m);
4192                         if ((cap_reg & DISC_PORT_SUPPORT_MASK) ==
4193                             DISC_PORT_SUPPORT_MASK)
4194                                 pbpctl_dev->bp_caps |=
4195                                     (TX_CTL_CAP | TX_STATUS_CAP);
4196                         pbpctl_dev->bp_caps_ex |= DISC_PORT_CAP_EX;
4197                 }
4198         }
4199 }
4200
4201 int bypass_off_init(struct bpctl_dev *pbpctl_dev)
4202 {
4203         int ret = cmnd_on(pbpctl_dev);
4204         if (ret < 0)
4205                 return ret;
4206         if (INTEL_IF_SERIES(pbpctl_dev->subdevice))
4207                 return dis_bypass_cap(pbpctl_dev);
4208         wdt_off(pbpctl_dev);
4209         if (pbpctl_dev->bp_caps & BP_CAP)
4210                 bypass_off(pbpctl_dev);
4211         if (pbpctl_dev->bp_caps & TAP_CAP)
4212                 tap_off(pbpctl_dev);
4213         cmnd_off(pbpctl_dev);
4214         return 0;
4215 }
4216
4217 void remove_bypass_wd_auto(struct bpctl_dev *pbpctl_dev)
4218 {
4219 #ifdef BP_SELF_TEST
4220         struct bpctl_dev *pbpctl_dev_sl = NULL;
4221 #endif
4222
4223         if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
4224
4225                 del_timer_sync(&pbpctl_dev->bp_timer);
4226 #ifdef BP_SELF_TEST
4227                 pbpctl_dev_sl = get_status_port_fn(pbpctl_dev);
4228                 if (pbpctl_dev_sl && (pbpctl_dev_sl->ndev)) {
4229                         if ((pbpctl_dev_sl->ndev->netdev_ops)
4230                             && (pbpctl_dev_sl->old_ops)) {
4231                                 rtnl_lock();
4232                                 pbpctl_dev_sl->ndev->netdev_ops =
4233                                     pbpctl_dev_sl->old_ops;
4234                                 pbpctl_dev_sl->old_ops = NULL;
4235
4236                                 rtnl_unlock();
4237
4238                         }
4239
4240                 }
4241 #endif
4242         }
4243
4244 }
4245
4246 int init_bypass_wd_auto(struct bpctl_dev *pbpctl_dev)
4247 {
4248         if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
4249                 init_timer(&pbpctl_dev->bp_timer);
4250                 pbpctl_dev->bp_timer.function = &wd_reset_timer;
4251                 pbpctl_dev->bp_timer.data = (unsigned long)pbpctl_dev;
4252                 return 1;
4253         }
4254         return BP_NOT_CAP;
4255 }
4256
4257 #ifdef BP_SELF_TEST
4258 int bp_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
4259 {
4260         struct bpctl_dev *pbpctl_dev = NULL, *pbpctl_dev_m = NULL;
4261         int idx_dev = 0;
4262         struct ethhdr *eth = (struct ethhdr *)skb->data;
4263
4264         for (idx_dev = 0;
4265              ((bpctl_dev_arr[idx_dev].ndev != NULL) && (idx_dev < device_num));
4266              idx_dev++) {
4267                 if (bpctl_dev_arr[idx_dev].ndev == dev) {
4268                         pbpctl_dev = &bpctl_dev_arr[idx_dev];
4269                         break;
4270                 }
4271         }
4272         if (!pbpctl_dev)
4273                 return 1;
4274         if ((htons(ETH_P_BPTEST) == eth->h_proto)) {
4275
4276                 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
4277                 if (pbpctl_dev_m) {
4278
4279                         if (bypass_status(pbpctl_dev_m)) {
4280                                 cmnd_on(pbpctl_dev_m);
4281                                 bypass_off(pbpctl_dev_m);
4282                                 cmnd_off(pbpctl_dev_m);
4283                         }
4284                         wdt_timer_reload(pbpctl_dev_m);
4285                 }
4286                 dev_kfree_skb_irq(skb);
4287                 return 0;
4288         }
4289         return pbpctl_dev->hard_start_xmit_save(skb, dev);
4290 }
4291 #endif
4292
4293 int set_bypass_wd_auto(struct bpctl_dev *pbpctl_dev, unsigned int param)
4294 {
4295         if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
4296                 if (pbpctl_dev->reset_time != param) {
4297                         if (INTEL_IF_SERIES(pbpctl_dev->subdevice))
4298                                 pbpctl_dev->reset_time =
4299                                     (param <
4300                                      WDT_AUTO_MIN_INT) ? WDT_AUTO_MIN_INT :
4301                                     param;
4302                         else
4303                                 pbpctl_dev->reset_time = param;
4304                         if (param)
4305                                 mod_timer(&pbpctl_dev->bp_timer, jiffies);
4306                 }
4307                 return 0;
4308         }
4309         return BP_NOT_CAP;
4310 }
4311
4312 int get_bypass_wd_auto(struct bpctl_dev *pbpctl_dev)
4313 {
4314         if (pbpctl_dev->bp_caps & WD_CTL_CAP)
4315                 return pbpctl_dev->reset_time;
4316
4317         return BP_NOT_CAP;
4318 }
4319
4320 #ifdef BP_SELF_TEST
4321
4322 int set_bp_self_test(struct bpctl_dev *pbpctl_dev, unsigned int param)
4323 {
4324         struct bpctl_dev *pbpctl_dev_sl = NULL;
4325
4326         if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
4327                 pbpctl_dev->bp_self_test_flag = param == 0 ? 0 : 1;
4328                 pbpctl_dev_sl = get_status_port_fn(pbpctl_dev);
4329
4330                 if ((pbpctl_dev_sl->ndev) && (pbpctl_dev_sl->ndev->netdev_ops)) {
4331                         rtnl_lock();
4332                         if (pbpctl_dev->bp_self_test_flag == 1) {
4333
4334                                 pbpctl_dev_sl->old_ops =
4335                                     pbpctl_dev_sl->ndev->netdev_ops;
4336                                 pbpctl_dev_sl->new_ops =
4337                                     *pbpctl_dev_sl->old_ops;
4338                                 pbpctl_dev_sl->new_ops.ndo_start_xmit =
4339                                     bp_hard_start_xmit;
4340                                 pbpctl_dev_sl->ndev->netdev_ops =
4341                                     &pbpctl_dev_sl->new_ops;
4342
4343                         } else if (pbpctl_dev_sl->old_ops) {
4344                                 pbpctl_dev_sl->ndev->netdev_ops =
4345                                     pbpctl_dev_sl->old_ops;
4346                                 pbpctl_dev_sl->old_ops = NULL;
4347                         }
4348                         rtnl_unlock();
4349                 }
4350
4351                 set_bypass_wd_auto(pbpctl_dev, param);
4352                 return 0;
4353         }
4354         return BP_NOT_CAP;
4355 }
4356
4357 int get_bp_self_test(struct bpctl_dev *pbpctl_dev)
4358 {
4359
4360         if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
4361                 if (pbpctl_dev->bp_self_test_flag == 1)
4362                         return pbpctl_dev->reset_time;
4363                 else
4364                         return 0;
4365         }
4366         return BP_NOT_CAP;
4367 }
4368
4369 #endif
4370
4371 /**************************************************************/
4372 /************************* API ********************************/
4373 /**************************************************************/
4374
4375 int is_bypass_fn(struct bpctl_dev *pbpctl_dev)
4376 {
4377         if (!pbpctl_dev)
4378                 return -1;
4379
4380         return (((pbpctl_dev->func == 0) || (pbpctl_dev->func == 2)) ? 1 : 0);
4381 }
4382
4383 int set_bypass_fn(struct bpctl_dev *pbpctl_dev, int bypass_mode)
4384 {
4385         int ret = 0;
4386
4387         if (!(pbpctl_dev->bp_caps & BP_CAP))
4388                 return BP_NOT_CAP;
4389         ret = cmnd_on(pbpctl_dev);
4390         if (ret < 0)
4391                 return ret;
4392         if (!bypass_mode)
4393                 ret = bypass_off(pbpctl_dev);
4394         else
4395                 ret = bypass_on(pbpctl_dev);
4396         cmnd_off(pbpctl_dev);
4397
4398         return ret;
4399 }
4400
4401 int get_bypass_fn(struct bpctl_dev *pbpctl_dev)
4402 {
4403         return bypass_status(pbpctl_dev);
4404 }
4405
4406 int get_bypass_change_fn(struct bpctl_dev *pbpctl_dev)
4407 {
4408         if (!pbpctl_dev)
4409                 return -1;
4410
4411         return bypass_change_status(pbpctl_dev);
4412 }
4413
4414 int set_dis_bypass_fn(struct bpctl_dev *pbpctl_dev, int dis_param)
4415 {
4416         int ret = 0;
4417         if (!pbpctl_dev)
4418                 return -1;
4419
4420         if (!(pbpctl_dev->bp_caps & BP_DIS_CAP))
4421                 return BP_NOT_CAP;
4422         ret = cmnd_on(pbpctl_dev);
4423         if (ret < 0)
4424                 return ret;
4425         if (dis_param)
4426                 ret = dis_bypass_cap(pbpctl_dev);
4427         else
4428                 ret = en_bypass_cap(pbpctl_dev);
4429         cmnd_off(pbpctl_dev);
4430         return ret;
4431 }
4432
4433 int get_dis_bypass_fn(struct bpctl_dev *pbpctl_dev)
4434 {
4435         if (!pbpctl_dev)
4436                 return -1;
4437
4438         return dis_bypass_cap_status(pbpctl_dev);
4439 }
4440
4441 int set_bypass_pwoff_fn(struct bpctl_dev *pbpctl_dev, int bypass_mode)
4442 {
4443         int ret = 0;
4444         if (!pbpctl_dev)
4445                 return -1;
4446
4447         if (!(pbpctl_dev->bp_caps & BP_PWOFF_CTL_CAP))
4448                 return BP_NOT_CAP;
4449         ret = cmnd_on(pbpctl_dev);
4450         if (ret < 0)
4451                 return ret;
4452         if (bypass_mode)
4453                 ret = bypass_state_pwroff(pbpctl_dev);
4454         else
4455                 ret = normal_state_pwroff(pbpctl_dev);
4456         cmnd_off(pbpctl_dev);
4457         return ret;
4458 }
4459
4460 int get_bypass_pwoff_fn(struct bpctl_dev *pbpctl_dev)
4461 {
4462         if (!pbpctl_dev)
4463                 return -1;
4464
4465         return default_pwroff_status(pbpctl_dev);
4466 }
4467
4468 int set_bypass_pwup_fn(struct bpctl_dev *pbpctl_dev, int bypass_mode)
4469 {
4470         int ret = 0;
4471         if (!pbpctl_dev)
4472                 return -1;
4473
4474         if (!(pbpctl_dev->bp_caps & BP_PWUP_CTL_CAP))
4475                 return BP_NOT_CAP;
4476         ret = cmnd_on(pbpctl_dev);
4477         if (ret < 0)
4478                 return ret;
4479         if (bypass_mode)
4480                 ret = bypass_state_pwron(pbpctl_dev);
4481         else
4482                 ret = normal_state_pwron(pbpctl_dev);
4483         cmnd_off(pbpctl_dev);
4484         return ret;
4485 }
4486
4487 int get_bypass_pwup_fn(struct bpctl_dev *pbpctl_dev)
4488 {
4489         if (!pbpctl_dev)
4490                 return -1;
4491
4492         return default_pwron_status(pbpctl_dev);
4493 }
4494
4495 int set_bypass_wd_fn(struct bpctl_dev *pbpctl_dev, int timeout)
4496 {
4497         int ret = 0;
4498         if (!pbpctl_dev)
4499                 return -1;
4500
4501         if (!(pbpctl_dev->bp_caps & WD_CTL_CAP))
4502                 return BP_NOT_CAP;
4503
4504         ret = cmnd_on(pbpctl_dev);
4505         if (ret < 0)
4506                 return ret;
4507         if (!timeout)
4508                 ret = wdt_off(pbpctl_dev);
4509         else {
4510                 wdt_on(pbpctl_dev, timeout);
4511                 ret = pbpctl_dev->bypass_timer_interval;
4512         }
4513         cmnd_off(pbpctl_dev);
4514         return ret;
4515 }
4516
4517 int get_bypass_wd_fn(struct bpctl_dev *pbpctl_dev, int *timeout)
4518 {
4519         if (!pbpctl_dev)
4520                 return -1;
4521
4522         return wdt_programmed(pbpctl_dev, timeout);
4523 }
4524
4525 int get_wd_expire_time_fn(struct bpctl_dev *pbpctl_dev, int *time_left)
4526 {
4527         if (!pbpctl_dev)
4528                 return -1;
4529
4530         return wdt_timer(pbpctl_dev, time_left);
4531 }
4532
4533 int reset_bypass_wd_timer_fn(struct bpctl_dev *pbpctl_dev)
4534 {
4535         if (!pbpctl_dev)
4536                 return -1;
4537
4538         return wdt_timer_reload(pbpctl_dev);
4539 }
4540
4541 int get_wd_set_caps_fn(struct bpctl_dev *pbpctl_dev)
4542 {
4543         int bp_status = 0;
4544
4545         unsigned int step_value = TIMEOUT_MAX_STEP + 1, bit_cnt = 0;
4546         if (!pbpctl_dev)
4547                 return -1;
4548
4549         if (INTEL_IF_SERIES(pbpctl_dev->subdevice))
4550                 return BP_NOT_CAP;
4551
4552         while ((step_value >>= 1))
4553                 bit_cnt++;
4554
4555         if (is_bypass_fn(pbpctl_dev)) {
4556                 bp_status =
4557                     WD_STEP_COUNT_MASK(bit_cnt) | WDT_STEP_TIME |
4558                     WD_MIN_TIME_MASK(TIMEOUT_UNIT / 100);
4559         } else
4560                 return -1;
4561
4562         return bp_status;
4563 }
4564
4565 int set_std_nic_fn(struct bpctl_dev *pbpctl_dev, int nic_mode)
4566 {
4567         int ret = 0;
4568         if (!pbpctl_dev)
4569                 return -1;
4570
4571         if (!(pbpctl_dev->bp_caps & STD_NIC_CAP))
4572                 return BP_NOT_CAP;
4573
4574         ret = cmnd_on(pbpctl_dev);
4575         if (ret < 0)
4576                 return ret;
4577         if (nic_mode)
4578                 ret = std_nic_on(pbpctl_dev);
4579         else
4580                 ret = std_nic_off(pbpctl_dev);
4581         cmnd_off(pbpctl_dev);
4582         return ret;
4583 }
4584
4585 int get_std_nic_fn(struct bpctl_dev *pbpctl_dev)
4586 {
4587         if (!pbpctl_dev)
4588                 return -1;
4589
4590         return std_nic_status(pbpctl_dev);
4591 }
4592
4593 int set_tap_fn(struct bpctl_dev *pbpctl_dev, int tap_mode)
4594 {
4595         if (!pbpctl_dev)
4596                 return -1;
4597
4598         if ((pbpctl_dev->bp_caps & TAP_CAP) && ((cmnd_on(pbpctl_dev)) >= 0)) {
4599                 if (!tap_mode)
4600                         tap_off(pbpctl_dev);
4601                 else
4602                         tap_on(pbpctl_dev);
4603                 cmnd_off(pbpctl_dev);
4604                 return 0;
4605         }
4606         return BP_NOT_CAP;
4607 }
4608
4609 int get_tap_fn(struct bpctl_dev *pbpctl_dev)
4610 {
4611         if (!pbpctl_dev)
4612                 return -1;
4613
4614         return tap_status(pbpctl_dev);
4615 }
4616
4617 int set_tap_pwup_fn(struct bpctl_dev *pbpctl_dev, int tap_mode)
4618 {
4619         int ret = 0;
4620         if (!pbpctl_dev)
4621                 return -1;
4622
4623         if ((pbpctl_dev->bp_caps & TAP_PWUP_CTL_CAP)
4624             && ((cmnd_on(pbpctl_dev)) >= 0)) {
4625                 if (tap_mode)
4626                         ret = tap_state_pwron(pbpctl_dev);
4627                 else
4628                         ret = normal_state_pwron(pbpctl_dev);
4629                 cmnd_off(pbpctl_dev);
4630         } else
4631                 ret = BP_NOT_CAP;
4632         return ret;
4633 }
4634
4635 int get_tap_pwup_fn(struct bpctl_dev *pbpctl_dev)
4636 {
4637         int ret = 0;
4638         if (!pbpctl_dev)
4639                 return -1;
4640
4641         ret = default_pwron_tap_status(pbpctl_dev);
4642         if (ret < 0)
4643                 return ret;
4644         return ((ret == 0) ? 1 : 0);
4645 }
4646
4647 int get_tap_change_fn(struct bpctl_dev *pbpctl_dev)
4648 {
4649         if (!pbpctl_dev)
4650                 return -1;
4651
4652         return tap_change_status(pbpctl_dev);
4653 }
4654
4655 int set_dis_tap_fn(struct bpctl_dev *pbpctl_dev, int dis_param)
4656 {
4657         int ret = 0;
4658         if (!pbpctl_dev)
4659                 return -1;
4660
4661         if ((pbpctl_dev->bp_caps & TAP_DIS_CAP) && ((cmnd_on(pbpctl_dev)) >= 0)) {
4662                 if (dis_param)
4663                         ret = dis_tap_cap(pbpctl_dev);
4664                 else
4665                         ret = en_tap_cap(pbpctl_dev);
4666                 cmnd_off(pbpctl_dev);
4667                 return ret;
4668         } else
4669                 return BP_NOT_CAP;
4670 }
4671
4672 int get_dis_tap_fn(struct bpctl_dev *pbpctl_dev)
4673 {
4674         if (!pbpctl_dev)
4675                 return -1;
4676
4677         return dis_tap_cap_status(pbpctl_dev);
4678 }
4679
4680 int set_disc_fn(struct bpctl_dev *pbpctl_dev, int disc_mode)
4681 {
4682         if (!pbpctl_dev)
4683                 return -1;
4684
4685         if ((pbpctl_dev->bp_caps & DISC_CAP) && ((cmnd_on(pbpctl_dev)) >= 0)) {
4686                 if (!disc_mode)
4687                         disc_off(pbpctl_dev);
4688                 else
4689                         disc_on(pbpctl_dev);
4690                 cmnd_off(pbpctl_dev);
4691
4692                 return BP_OK;
4693         }
4694         return BP_NOT_CAP;
4695 }
4696
4697 int get_disc_fn(struct bpctl_dev *pbpctl_dev)
4698 {
4699         int ret = 0;
4700         if (!pbpctl_dev)
4701                 return -1;
4702
4703         ret = disc_status(pbpctl_dev);
4704
4705         return ret;
4706 }
4707
4708 int set_disc_pwup_fn(struct bpctl_dev *pbpctl_dev, int disc_mode)
4709 {
4710         int ret = 0;
4711         if (!pbpctl_dev)
4712                 return -1;
4713
4714         if ((pbpctl_dev->bp_caps & DISC_PWUP_CTL_CAP)
4715             && ((cmnd_on(pbpctl_dev)) >= 0)) {
4716                 if (disc_mode)
4717                         ret = disc_state_pwron(pbpctl_dev);
4718                 else
4719                         ret = normal_state_pwron(pbpctl_dev);
4720                 cmnd_off(pbpctl_dev);
4721         } else
4722                 ret = BP_NOT_CAP;
4723         return ret;
4724 }
4725
4726 int get_disc_pwup_fn(struct bpctl_dev *pbpctl_dev)
4727 {
4728         int ret = 0;
4729         if (!pbpctl_dev)
4730                 return -1;
4731
4732         ret = default_pwron_disc_status(pbpctl_dev);
4733         return (ret == 0 ? 1 : (ret < 0 ? BP_NOT_CAP : 0));
4734 }
4735
4736 int get_disc_change_fn(struct bpctl_dev *pbpctl_dev)
4737 {
4738         int ret = 0;
4739         if (!pbpctl_dev)
4740                 return -1;
4741
4742         ret = disc_change_status(pbpctl_dev);
4743         return ret;
4744 }
4745
4746 int set_dis_disc_fn(struct bpctl_dev *pbpctl_dev, int dis_param)
4747 {
4748         int ret = 0;
4749         if (!pbpctl_dev)
4750                 return -1;
4751
4752         if ((pbpctl_dev->bp_caps & DISC_DIS_CAP)
4753             && ((cmnd_on(pbpctl_dev)) >= 0)) {
4754                 if (dis_param)
4755                         ret = dis_disc_cap(pbpctl_dev);
4756                 else
4757                         ret = en_disc_cap(pbpctl_dev);
4758                 cmnd_off(pbpctl_dev);
4759                 return ret;
4760         } else
4761                 return BP_NOT_CAP;
4762 }
4763
4764 int get_dis_disc_fn(struct bpctl_dev *pbpctl_dev)
4765 {
4766         int ret = 0;
4767         if (!pbpctl_dev)
4768                 return -1;
4769
4770         ret = dis_disc_cap_status(pbpctl_dev);
4771
4772         return ret;
4773 }
4774
4775 int set_disc_port_fn(struct bpctl_dev *pbpctl_dev, int disc_mode)
4776 {
4777         int ret = BP_NOT_CAP;
4778         if (!pbpctl_dev)
4779                 return -1;
4780
4781         if (!disc_mode)
4782                 ret = disc_port_off(pbpctl_dev);
4783         else
4784                 ret = disc_port_on(pbpctl_dev);
4785
4786         return ret;
4787 }
4788
4789 int get_disc_port_fn(struct bpctl_dev *pbpctl_dev)
4790 {
4791         if (!pbpctl_dev)
4792                 return -1;
4793
4794         return disc_port_status(pbpctl_dev);
4795 }
4796
4797 int set_disc_port_pwup_fn(struct bpctl_dev *pbpctl_dev, int disc_mode)
4798 {
4799         int ret = BP_NOT_CAP;
4800         if (!pbpctl_dev)
4801                 return -1;
4802
4803         if (!disc_mode)
4804                 ret = normal_port_state_pwron(pbpctl_dev);
4805         else
4806                 ret = disc_port_state_pwron(pbpctl_dev);
4807
4808         return ret;
4809 }
4810
4811 int get_disc_port_pwup_fn(struct bpctl_dev *pbpctl_dev)
4812 {
4813         int ret = 0;
4814         if (!pbpctl_dev)
4815                 return -1;
4816
4817         ret = default_pwron_disc_port_status(pbpctl_dev);
4818         if (ret < 0)
4819                 return ret;
4820         return ((ret == 0) ? 1 : 0);
4821 }
4822
4823 int get_wd_exp_mode_fn(struct bpctl_dev *pbpctl_dev)
4824 {
4825         if (!pbpctl_dev)
4826                 return -1;
4827
4828         return wdt_exp_mode_status(pbpctl_dev);
4829 }
4830
4831 int set_wd_exp_mode_fn(struct bpctl_dev *pbpctl_dev, int param)
4832 {
4833         if (!pbpctl_dev)
4834                 return -1;
4835
4836         return wdt_exp_mode(pbpctl_dev, param);
4837 }
4838
4839 int reset_cont_fn(struct bpctl_dev *pbpctl_dev)
4840 {
4841         int ret = 0;
4842         if (!pbpctl_dev)
4843                 return -1;
4844
4845         ret = cmnd_on(pbpctl_dev);
4846         if (ret < 0)
4847                 return ret;
4848         return reset_cont(pbpctl_dev);
4849 }
4850
4851 int set_tx_fn(struct bpctl_dev *pbpctl_dev, int tx_state)
4852 {
4853
4854         struct bpctl_dev *pbpctl_dev_b = NULL;
4855         if (!pbpctl_dev)
4856                 return -1;
4857
4858         if ((pbpctl_dev->bp_caps & TPL_CAP) &&
4859             (pbpctl_dev->bp_caps & SW_CTL_CAP)) {
4860                 if ((pbpctl_dev->bp_tpl_flag))
4861                         return BP_NOT_CAP;
4862         } else {
4863                 pbpctl_dev_b = get_master_port_fn(pbpctl_dev);
4864                 if (pbpctl_dev_b &&
4865                     (pbpctl_dev_b->bp_caps & TPL_CAP) &&
4866                     (pbpctl_dev_b->bp_tpl_flag))
4867                         return BP_NOT_CAP;
4868         }
4869         return set_tx(pbpctl_dev, tx_state);
4870 }
4871
4872 int set_bp_force_link_fn(int dev_num, int tx_state)
4873 {
4874         static struct bpctl_dev *bpctl_dev_curr;
4875
4876         if ((dev_num < 0) || (dev_num > device_num)
4877             || (bpctl_dev_arr[dev_num].pdev == NULL))
4878                 return -1;
4879         bpctl_dev_curr = &bpctl_dev_arr[dev_num];
4880
4881         return set_bp_force_link(bpctl_dev_curr, tx_state);
4882 }
4883
4884 int set_wd_autoreset_fn(struct bpctl_dev *pbpctl_dev, int param)
4885 {
4886         if (!pbpctl_dev)
4887                 return -1;
4888
4889         return set_bypass_wd_auto(pbpctl_dev, param);
4890 }
4891
4892 int get_wd_autoreset_fn(struct bpctl_dev *pbpctl_dev)
4893 {
4894         if (!pbpctl_dev)
4895                 return -1;
4896
4897         return get_bypass_wd_auto(pbpctl_dev);
4898 }
4899
4900 #ifdef BP_SELF_TEST
4901 int set_bp_self_test_fn(struct bpctl_dev *pbpctl_dev, int param)
4902 {
4903         if (!pbpctl_dev)
4904                 return -1;
4905
4906         return set_bp_self_test(pbpctl_dev, param);
4907 }
4908
4909 int get_bp_self_test_fn(struct bpctl_dev *pbpctl_dev)
4910 {
4911         if (!pbpctl_dev)
4912                 return -1;
4913
4914         return get_bp_self_test(pbpctl_dev);
4915 }
4916
4917 #endif
4918
4919 int get_bypass_caps_fn(struct bpctl_dev *pbpctl_dev)
4920 {
4921         if (!pbpctl_dev)
4922                 return -1;
4923
4924         return pbpctl_dev->bp_caps;
4925
4926 }
4927
4928 int get_bypass_slave_fn(struct bpctl_dev *pbpctl_dev, struct bpctl_dev **pbpctl_dev_out)
4929 {
4930         int idx_dev = 0;
4931         if (!pbpctl_dev)
4932                 return -1;
4933
4934         if ((pbpctl_dev->func == 0) || (pbpctl_dev->func == 2)) {
4935                 for (idx_dev = 0;
4936                      ((bpctl_dev_arr[idx_dev].pdev != NULL)
4937                       && (idx_dev < device_num)); idx_dev++) {
4938                         if ((bpctl_dev_arr[idx_dev].bus == pbpctl_dev->bus)
4939                             && (bpctl_dev_arr[idx_dev].slot ==
4940                                 pbpctl_dev->slot)) {
4941                                 if ((pbpctl_dev->func == 0)
4942                                     && (bpctl_dev_arr[idx_dev].func == 1)) {
4943                                         *pbpctl_dev_out =
4944                                             &bpctl_dev_arr[idx_dev];
4945                                         return 1;
4946                                 }
4947                                 if ((pbpctl_dev->func == 2) &&
4948                                     (bpctl_dev_arr[idx_dev].func == 3)) {
4949                                         *pbpctl_dev_out =
4950                                             &bpctl_dev_arr[idx_dev];
4951                                         return 1;
4952                                 }
4953                         }
4954                 }
4955                 return -1;
4956         } else
4957                 return 0;
4958 }
4959
4960 int is_bypass(struct bpctl_dev *pbpctl_dev)
4961 {
4962         if (!pbpctl_dev)
4963                 return -1;
4964
4965         if ((pbpctl_dev->func == 0) || (pbpctl_dev->func == 2))
4966                 return 1;
4967         else
4968                 return 0;
4969 }
4970
4971 int get_tx_fn(struct bpctl_dev *pbpctl_dev)
4972 {
4973         struct bpctl_dev *pbpctl_dev_b = NULL;
4974         if (!pbpctl_dev)
4975                 return -1;
4976
4977         if ((pbpctl_dev->bp_caps & TPL_CAP) &&
4978             (pbpctl_dev->bp_caps & SW_CTL_CAP)) {
4979                 if ((pbpctl_dev->bp_tpl_flag))
4980                         return BP_NOT_CAP;
4981         } else {
4982                 pbpctl_dev_b = get_master_port_fn(pbpctl_dev);
4983                 if (pbpctl_dev_b &&
4984                     (pbpctl_dev_b->bp_caps & TPL_CAP) &&
4985                     (pbpctl_dev_b->bp_tpl_flag))
4986                         return BP_NOT_CAP;
4987         }
4988         return tx_status(pbpctl_dev);
4989 }
4990
4991 int get_bp_force_link_fn(int dev_num)
4992 {
4993         static struct bpctl_dev *bpctl_dev_curr;
4994
4995         if ((dev_num < 0) || (dev_num > device_num)
4996             || (bpctl_dev_arr[dev_num].pdev == NULL))
4997                 return -1;
4998         bpctl_dev_curr = &bpctl_dev_arr[dev_num];
4999
5000         return bp_force_link_status(bpctl_dev_curr);
5001 }
5002
5003 static int get_bypass_link_status(struct bpctl_dev *pbpctl_dev)
5004 {
5005         if (!pbpctl_dev)
5006                 return -1;
5007
5008         if (pbpctl_dev->media_type == BP_FIBER)
5009                 return ((BPCTL_READ_REG(pbpctl_dev, CTRL) &
5010                          BPCTLI_CTRL_SWDPIN1));
5011         else
5012                 return ((BPCTL_READ_REG(pbpctl_dev, STATUS) &
5013                          BPCTLI_STATUS_LU));
5014
5015 }
5016
5017 static void bp_tpl_timer_fn(unsigned long param)
5018 {
5019         struct bpctl_dev *pbpctl_dev = (struct bpctl_dev *) param;
5020         uint32_t link1, link2;
5021         struct bpctl_dev *pbpctl_dev_b = NULL;
5022
5023         pbpctl_dev_b = get_status_port_fn(pbpctl_dev);
5024         if (!pbpctl_dev_b)
5025                 return;
5026
5027         if (!pbpctl_dev->bp_tpl_flag) {
5028                 set_tx(pbpctl_dev_b, 1);
5029                 set_tx(pbpctl_dev, 1);
5030                 return;
5031         }
5032         link1 = get_bypass_link_status(pbpctl_dev);
5033
5034         link2 = get_bypass_link_status(pbpctl_dev_b);
5035         if ((link1) && (tx_status(pbpctl_dev))) {
5036                 if ((!link2) && (tx_status(pbpctl_dev_b)))
5037                         set_tx(pbpctl_dev, 0);
5038                 else if (!tx_status(pbpctl_dev_b))
5039                         set_tx(pbpctl_dev_b, 1);
5040         } else if ((!link1) && (tx_status(pbpctl_dev))) {
5041                 if ((link2) && (tx_status(pbpctl_dev_b)))
5042                         set_tx(pbpctl_dev_b, 0);
5043         } else if ((link1) && (!tx_status(pbpctl_dev))) {
5044                 if ((link2) && (tx_status(pbpctl_dev_b)))
5045                         set_tx(pbpctl_dev, 1);
5046         } else if ((!link1) && (!tx_status(pbpctl_dev))) {
5047                 if ((link2) && (tx_status(pbpctl_dev_b)))
5048                         set_tx(pbpctl_dev, 1);
5049         }
5050
5051         mod_timer(&pbpctl_dev->bp_tpl_timer, jiffies + BP_LINK_MON_DELAY * HZ);
5052 }
5053
5054 void remove_bypass_tpl_auto(struct bpctl_dev *pbpctl_dev)
5055 {
5056         struct bpctl_dev *pbpctl_dev_b = NULL;
5057         if (!pbpctl_dev)
5058                 return;
5059         pbpctl_dev_b = get_status_port_fn(pbpctl_dev);
5060
5061         if (pbpctl_dev->bp_caps & TPL_CAP) {
5062                 del_timer_sync(&pbpctl_dev->bp_tpl_timer);
5063                 pbpctl_dev->bp_tpl_flag = 0;
5064                 pbpctl_dev_b = get_status_port_fn(pbpctl_dev);
5065                 if (pbpctl_dev_b)
5066                         set_tx(pbpctl_dev_b, 1);
5067                 set_tx(pbpctl_dev, 1);
5068         }
5069         return;
5070 }
5071
5072 int init_bypass_tpl_auto(struct bpctl_dev *pbpctl_dev)
5073 {
5074         if (!pbpctl_dev)
5075                 return -1;
5076         if (pbpctl_dev->bp_caps & TPL_CAP) {
5077                 init_timer(&pbpctl_dev->bp_tpl_timer);
5078                 pbpctl_dev->bp_tpl_timer.function = &bp_tpl_timer_fn;
5079                 pbpctl_dev->bp_tpl_timer.data = (unsigned long)pbpctl_dev;
5080                 return BP_OK;
5081         }
5082         return BP_NOT_CAP;
5083 }
5084
5085 int set_bypass_tpl_auto(struct bpctl_dev *pbpctl_dev, unsigned int param)
5086 {
5087         if (!pbpctl_dev)
5088                 return -1;
5089         if (pbpctl_dev->bp_caps & TPL_CAP) {
5090                 if ((param) && (!pbpctl_dev->bp_tpl_flag)) {
5091                         pbpctl_dev->bp_tpl_flag = param;
5092                         mod_timer(&pbpctl_dev->bp_tpl_timer, jiffies + 1);
5093                         return BP_OK;
5094                 }
5095                 if ((!param) && (pbpctl_dev->bp_tpl_flag))
5096                         remove_bypass_tpl_auto(pbpctl_dev);
5097
5098                 return BP_OK;
5099         }
5100         return BP_NOT_CAP;
5101 }
5102
5103 int get_bypass_tpl_auto(struct bpctl_dev *pbpctl_dev)
5104 {
5105         if (!pbpctl_dev)
5106                 return -1;
5107         if (pbpctl_dev->bp_caps & TPL_CAP)
5108                 return pbpctl_dev->bp_tpl_flag;
5109
5110         return BP_NOT_CAP;
5111 }
5112
5113 int set_tpl_fn(struct bpctl_dev *pbpctl_dev, int tpl_mode)
5114 {
5115
5116         struct bpctl_dev *pbpctl_dev_b = NULL;
5117         if (!pbpctl_dev)
5118                 return -1;
5119
5120         pbpctl_dev_b = get_status_port_fn(pbpctl_dev);
5121
5122         if (pbpctl_dev->bp_caps & TPL_CAP) {
5123                 if (tpl_mode) {
5124                         pbpctl_dev_b = get_status_port_fn(pbpctl_dev);
5125                         if (pbpctl_dev_b)
5126                                 set_tx(pbpctl_dev_b, 1);
5127                         set_tx(pbpctl_dev, 1);
5128                 }
5129                 if ((TPL_IF_SERIES(pbpctl_dev->subdevice)) ||
5130                     (pbpctl_dev->bp_caps_ex & TPL2_CAP_EX)) {
5131                         pbpctl_dev->bp_tpl_flag = tpl_mode;
5132                         if (!tpl_mode)
5133                                 tpl_hw_off(pbpctl_dev);
5134                         else
5135                                 tpl_hw_on(pbpctl_dev);
5136                 } else
5137                         set_bypass_tpl_auto(pbpctl_dev, tpl_mode);
5138                 return 0;
5139         }
5140         return BP_NOT_CAP;
5141 }
5142
5143 int get_tpl_fn(struct bpctl_dev *pbpctl_dev)
5144 {
5145         int ret = BP_NOT_CAP;
5146         if (!pbpctl_dev)
5147                 return -1;
5148
5149         if (pbpctl_dev->bp_caps & TPL_CAP) {
5150                 if (pbpctl_dev->bp_caps_ex & TPL2_CAP_EX)
5151                         return tpl2_flag_status(pbpctl_dev);
5152                 ret = pbpctl_dev->bp_tpl_flag;
5153         }
5154         return ret;
5155 }
5156
5157 int set_bp_wait_at_pwup_fn(struct bpctl_dev *pbpctl_dev, int tap_mode)
5158 {
5159         if (!pbpctl_dev)
5160                 return -1;
5161
5162         if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
5163                 /* bp_lock(pbp_device_block); */
5164                 cmnd_on(pbpctl_dev);
5165                 if (!tap_mode)
5166                         bp_wait_at_pwup_dis(pbpctl_dev);
5167                 else
5168                         bp_wait_at_pwup_en(pbpctl_dev);
5169                 cmnd_off(pbpctl_dev);
5170
5171                 /* bp_unlock(pbp_device_block); */
5172                 return BP_OK;
5173         }
5174         return BP_NOT_CAP;
5175 }
5176
5177 int get_bp_wait_at_pwup_fn(struct bpctl_dev *pbpctl_dev)
5178 {
5179         int ret = 0;
5180         if (!pbpctl_dev)
5181                 return -1;
5182
5183         /* bp_lock(pbp_device_block); */
5184         ret = bp_wait_at_pwup_status(pbpctl_dev);
5185         /* bp_unlock(pbp_device_block); */
5186
5187         return ret;
5188 }
5189
5190 int set_bp_hw_reset_fn(struct bpctl_dev *pbpctl_dev, int tap_mode)
5191 {
5192         if (!pbpctl_dev)
5193                 return -1;
5194
5195         if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
5196                 /*   bp_lock(pbp_device_block); */
5197                 cmnd_on(pbpctl_dev);
5198
5199                 if (!tap_mode)
5200                         bp_hw_reset_dis(pbpctl_dev);
5201                 else
5202                         bp_hw_reset_en(pbpctl_dev);
5203                 cmnd_off(pbpctl_dev);
5204                 /*    bp_unlock(pbp_device_block); */
5205                 return BP_OK;
5206         }
5207         return BP_NOT_CAP;
5208 }
5209
5210 int get_bp_hw_reset_fn(struct bpctl_dev *pbpctl_dev)
5211 {
5212         int ret = 0;
5213         if (!pbpctl_dev)
5214                 return -1;
5215
5216         /* bp_lock(pbp_device_block); */
5217         ret = bp_hw_reset_status(pbpctl_dev);
5218
5219         /* bp_unlock(pbp_device_block); */
5220
5221         return ret;
5222 }
5223
5224
5225 int get_bypass_info_fn(struct bpctl_dev *pbpctl_dev, char *dev_name,
5226                        char *add_param)
5227 {
5228         if (!pbpctl_dev)
5229                 return -1;
5230         if (!is_bypass_fn(pbpctl_dev))
5231                 return -1;
5232         strcpy(dev_name, pbpctl_dev->name);
5233         *add_param = pbpctl_dev->bp_fw_ver;
5234         return 0;
5235 }
5236
5237 int get_dev_idx_bsf(int bus, int slot, int func)
5238 {
5239         int idx_dev = 0;
5240         for (idx_dev = 0;
5241              ((bpctl_dev_arr[idx_dev].pdev != NULL) && (idx_dev < device_num));
5242              idx_dev++) {
5243                 if ((bus == bpctl_dev_arr[idx_dev].bus)
5244                     && (slot == bpctl_dev_arr[idx_dev].slot)
5245                     && (func == bpctl_dev_arr[idx_dev].func))
5246
5247                         return idx_dev;
5248         }
5249         return -1;
5250 }
5251
5252 static int get_dev_idx(int ifindex)
5253 {
5254         int idx_dev = 0;
5255
5256         for (idx_dev = 0;
5257              ((bpctl_dev_arr[idx_dev].pdev != NULL) && (idx_dev < device_num));
5258              idx_dev++) {
5259                 if (ifindex == bpctl_dev_arr[idx_dev].ifindex)
5260                         return idx_dev;
5261         }
5262
5263         return -1;
5264 }
5265
5266 static struct bpctl_dev *get_dev_idx_p(int ifindex)
5267 {
5268         int idx_dev = 0;
5269
5270         for (idx_dev = 0;
5271              ((bpctl_dev_arr[idx_dev].pdev != NULL) && (idx_dev < device_num));
5272              idx_dev++) {
5273                 if (ifindex == bpctl_dev_arr[idx_dev].ifindex)
5274                         return &bpctl_dev_arr[idx_dev];
5275         }
5276
5277         return NULL;
5278 }
5279
5280 static void if_scan_init(void)
5281 {
5282         struct net_device *dev;
5283
5284         /* rcu_read_lock(); */
5285         /* rtnl_lock();     */
5286         /* rcu_read_lock(); */
5287
5288         for_each_netdev(&init_net, dev) {
5289                 int idx_dev;
5290
5291                 if (bp_get_dev_idx_bsf(dev, &idx_dev))
5292                         continue;
5293
5294                 if (idx_dev == -1)
5295                         continue;
5296
5297                 bpctl_dev_arr[idx_dev].ifindex = dev->ifindex;
5298                 bpctl_dev_arr[idx_dev].ndev = dev;
5299         }
5300         /* rtnl_unlock();     */
5301         /* rcu_read_unlock(); */
5302 }
5303
5304 static long device_ioctl(struct file *file,     /* see include/linux/fs.h */
5305                          unsigned int ioctl_num,        /* number and param for ioctl */
5306                          unsigned long ioctl_param)
5307 {
5308         struct bpctl_cmd bpctl_cmd;
5309         int dev_idx = 0;
5310         struct bpctl_dev *pbpctl_dev_out;
5311         void __user *argp = (void __user *)ioctl_param;
5312         int ret = 0;
5313         unsigned long flags;
5314
5315         static struct bpctl_dev *pbpctl_dev;
5316
5317         /* lock_kernel(); */
5318         if (down_interruptible(&bpctl_sema))
5319                 return -ERESTARTSYS;
5320         /* local_irq_save(flags); */
5321         /* if(!spin_trylock_irqsave(&bpvm_lock)){
5322            local_irq_restore(flags);
5323            unlock_bpctl();
5324            unlock_kernel();
5325            return -1;
5326            } */
5327         /* spin_lock_irqsave(&bpvm_lock, flags); */
5328
5329 /*
5330 * Switch according to the ioctl called
5331 */
5332         if (ioctl_num == IOCTL_TX_MSG(IF_SCAN)) {
5333                 if_scan_init();
5334                 ret = SUCCESS;
5335                 goto bp_exit;
5336         }
5337         if (copy_from_user(&bpctl_cmd, argp, sizeof(struct bpctl_cmd))) {
5338
5339                 ret = -EFAULT;
5340                 goto bp_exit;
5341         }
5342
5343         if (ioctl_num == IOCTL_TX_MSG(GET_DEV_NUM)) {
5344                 bpctl_cmd.out_param[0] = device_num;
5345                 if (copy_to_user
5346                     (argp, (void *)&bpctl_cmd, sizeof(struct bpctl_cmd))) {
5347                         ret = -EFAULT;
5348                         goto bp_exit;
5349                 }
5350                 ret = SUCCESS;
5351                 goto bp_exit;
5352
5353         }
5354         /* lock_bpctl();      */
5355         /* preempt_disable(); */
5356         local_irq_save(flags);
5357         if (!spin_trylock(&bpvm_lock)) {
5358                 local_irq_restore(flags);
5359                 unlock_bpctl();
5360                 return -1;
5361         }
5362
5363 /*      preempt_disable();
5364         rcu_read_lock();
5365         spin_lock_irqsave(&bpvm_lock, flags);
5366 */
5367         if ((bpctl_cmd.in_param[5]) ||
5368             (bpctl_cmd.in_param[6]) || (bpctl_cmd.in_param[7]))
5369                 dev_idx = get_dev_idx_bsf(bpctl_cmd.in_param[5],
5370                                           bpctl_cmd.in_param[6],
5371                                           bpctl_cmd.in_param[7]);
5372         else if (bpctl_cmd.in_param[1] == 0)
5373                 dev_idx = bpctl_cmd.in_param[0];
5374         else
5375                 dev_idx = get_dev_idx(bpctl_cmd.in_param[1]);
5376
5377         if (dev_idx < 0 || dev_idx > device_num) {
5378                 /* unlock_bpctl();
5379                    preempt_enable(); */
5380                 ret = -EOPNOTSUPP;
5381                 /* preempt_enable();
5382                    rcu_read_unlock();  */
5383                 spin_unlock_irqrestore(&bpvm_lock, flags);
5384                 goto bp_exit;
5385         }
5386
5387         bpctl_cmd.out_param[0] = bpctl_dev_arr[dev_idx].bus;
5388         bpctl_cmd.out_param[1] = bpctl_dev_arr[dev_idx].slot;
5389         bpctl_cmd.out_param[2] = bpctl_dev_arr[dev_idx].func;
5390         bpctl_cmd.out_param[3] = bpctl_dev_arr[dev_idx].ifindex;
5391
5392         if ((bpctl_dev_arr[dev_idx].bp_10gb)
5393             && (!(bpctl_dev_arr[dev_idx].ifindex))) {
5394                 printk("Please load network driver for %s adapter!\n",
5395                        bpctl_dev_arr[dev_idx].name);
5396                 bpctl_cmd.status = -1;
5397                 ret = SUCCESS;
5398                 /* preempt_enable(); */
5399                 /* rcu_read_unlock(); */
5400                 spin_unlock_irqrestore(&bpvm_lock, flags);
5401                 goto bp_exit;
5402
5403         }
5404         if ((bpctl_dev_arr[dev_idx].bp_10gb) && (bpctl_dev_arr[dev_idx].ndev)) {
5405                 if (!(bpctl_dev_arr[dev_idx].ndev->flags & IFF_UP)) {
5406                         if (!(bpctl_dev_arr[dev_idx].ndev->flags & IFF_UP)) {
5407                                 printk
5408                                     ("Please bring up network interfaces for %s adapter!\n",
5409                                      bpctl_dev_arr[dev_idx].name);
5410                                 bpctl_cmd.status = -1;
5411                                 ret = SUCCESS;
5412                                 /* preempt_enable(); */
5413                                 /* rcu_read_unlock(); */
5414                                 spin_unlock_irqrestore(&bpvm_lock, flags);
5415                                 goto bp_exit;
5416                         }
5417
5418                 }
5419         }
5420
5421         if ((dev_idx < 0) || (dev_idx > device_num)
5422             || (bpctl_dev_arr[dev_idx].pdev == NULL)) {
5423                 bpctl_cmd.status = -1;
5424                 goto bpcmd_exit;
5425         }
5426
5427         pbpctl_dev = &bpctl_dev_arr[dev_idx];
5428
5429         switch (ioctl_num) {
5430         case IOCTL_TX_MSG(SET_BYPASS_PWOFF):
5431                 bpctl_cmd.status =
5432                     set_bypass_pwoff_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5433                 break;
5434
5435         case IOCTL_TX_MSG(GET_BYPASS_PWOFF):
5436                 bpctl_cmd.status = get_bypass_pwoff_fn(pbpctl_dev);
5437                 break;
5438
5439         case IOCTL_TX_MSG(SET_BYPASS_PWUP):
5440                 bpctl_cmd.status =
5441                     set_bypass_pwup_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5442                 break;
5443
5444         case IOCTL_TX_MSG(GET_BYPASS_PWUP):
5445                 bpctl_cmd.status = get_bypass_pwup_fn(pbpctl_dev);
5446                 break;
5447
5448         case IOCTL_TX_MSG(SET_BYPASS_WD):
5449                 bpctl_cmd.status =
5450                     set_bypass_wd_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5451                 break;
5452
5453         case IOCTL_TX_MSG(GET_BYPASS_WD):
5454                 bpctl_cmd.status =
5455                     get_bypass_wd_fn(pbpctl_dev, (int *)&(bpctl_cmd.data[0]));
5456                 break;
5457
5458         case IOCTL_TX_MSG(GET_WD_EXPIRE_TIME):
5459                 bpctl_cmd.status =
5460                     get_wd_expire_time_fn(pbpctl_dev,
5461                                           (int *)&(bpctl_cmd.data[0]));
5462                 break;
5463
5464         case IOCTL_TX_MSG(RESET_BYPASS_WD_TIMER):
5465                 bpctl_cmd.status = reset_bypass_wd_timer_fn(pbpctl_dev);
5466                 break;
5467
5468         case IOCTL_TX_MSG(GET_WD_SET_CAPS):
5469                 bpctl_cmd.status = get_wd_set_caps_fn(pbpctl_dev);
5470                 break;
5471
5472         case IOCTL_TX_MSG(SET_STD_NIC):
5473                 bpctl_cmd.status =
5474                     set_std_nic_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5475                 break;
5476
5477         case IOCTL_TX_MSG(GET_STD_NIC):
5478                 bpctl_cmd.status = get_std_nic_fn(pbpctl_dev);
5479                 break;
5480
5481         case IOCTL_TX_MSG(SET_TAP):
5482                 bpctl_cmd.status =
5483                     set_tap_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5484                 break;
5485
5486         case IOCTL_TX_MSG(GET_TAP):
5487                 bpctl_cmd.status = get_tap_fn(pbpctl_dev);
5488                 break;
5489
5490         case IOCTL_TX_MSG(GET_TAP_CHANGE):
5491                 bpctl_cmd.status = get_tap_change_fn(pbpctl_dev);
5492                 break;
5493
5494         case IOCTL_TX_MSG(SET_DIS_TAP):
5495                 bpctl_cmd.status =
5496                     set_dis_tap_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5497                 break;
5498
5499         case IOCTL_TX_MSG(GET_DIS_TAP):
5500                 bpctl_cmd.status = get_dis_tap_fn(pbpctl_dev);
5501                 break;
5502
5503         case IOCTL_TX_MSG(SET_TAP_PWUP):
5504                 bpctl_cmd.status =
5505                     set_tap_pwup_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5506                 break;
5507
5508         case IOCTL_TX_MSG(GET_TAP_PWUP):
5509                 bpctl_cmd.status = get_tap_pwup_fn(pbpctl_dev);
5510                 break;
5511
5512         case IOCTL_TX_MSG(SET_WD_EXP_MODE):
5513                 bpctl_cmd.status =
5514                     set_wd_exp_mode_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5515                 break;
5516
5517         case IOCTL_TX_MSG(GET_WD_EXP_MODE):
5518                 bpctl_cmd.status = get_wd_exp_mode_fn(pbpctl_dev);
5519                 break;
5520
5521         case IOCTL_TX_MSG(GET_DIS_BYPASS):
5522                 bpctl_cmd.status = get_dis_bypass_fn(pbpctl_dev);
5523                 break;
5524
5525         case IOCTL_TX_MSG(SET_DIS_BYPASS):
5526                 bpctl_cmd.status =
5527                     set_dis_bypass_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5528                 break;
5529
5530         case IOCTL_TX_MSG(GET_BYPASS_CHANGE):
5531                 bpctl_cmd.status = get_bypass_change_fn(pbpctl_dev);
5532                 break;
5533
5534         case IOCTL_TX_MSG(GET_BYPASS):
5535                 bpctl_cmd.status = get_bypass_fn(pbpctl_dev);
5536                 break;
5537
5538         case IOCTL_TX_MSG(SET_BYPASS):
5539                 bpctl_cmd.status =
5540                     set_bypass_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5541                 break;
5542
5543         case IOCTL_TX_MSG(GET_BYPASS_CAPS):
5544                 bpctl_cmd.status = get_bypass_caps_fn(pbpctl_dev);
5545                 /*preempt_enable(); */
5546                 /*rcu_read_unlock();*/
5547                 spin_unlock_irqrestore(&bpvm_lock, flags);
5548                 if (copy_to_user
5549                     (argp, (void *)&bpctl_cmd, sizeof(struct bpctl_cmd))) {
5550                         /*unlock_bpctl();   */
5551                         /*preempt_enable(); */
5552                         ret = -EFAULT;
5553                         goto bp_exit;
5554                 }
5555                 goto bp_exit;
5556
5557         case IOCTL_TX_MSG(GET_BYPASS_SLAVE):
5558                 bpctl_cmd.status =
5559                     get_bypass_slave_fn(pbpctl_dev, &pbpctl_dev_out);
5560                 if (bpctl_cmd.status == 1) {
5561                         bpctl_cmd.out_param[4] = pbpctl_dev_out->bus;
5562                         bpctl_cmd.out_param[5] = pbpctl_dev_out->slot;
5563                         bpctl_cmd.out_param[6] = pbpctl_dev_out->func;
5564                         bpctl_cmd.out_param[7] = pbpctl_dev_out->ifindex;
5565                 }
5566                 break;
5567
5568         case IOCTL_TX_MSG(IS_BYPASS):
5569                 bpctl_cmd.status = is_bypass(pbpctl_dev);
5570                 break;
5571         case IOCTL_TX_MSG(SET_TX):
5572                 bpctl_cmd.status = set_tx_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5573                 break;
5574         case IOCTL_TX_MSG(GET_TX):
5575                 bpctl_cmd.status = get_tx_fn(pbpctl_dev);
5576                 break;
5577         case IOCTL_TX_MSG(SET_WD_AUTORESET):
5578                 bpctl_cmd.status =
5579                     set_wd_autoreset_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5580
5581                 break;
5582         case IOCTL_TX_MSG(GET_WD_AUTORESET):
5583
5584                 bpctl_cmd.status = get_wd_autoreset_fn(pbpctl_dev);
5585                 break;
5586         case IOCTL_TX_MSG(SET_DISC):
5587                 bpctl_cmd.status =
5588                     set_disc_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5589                 break;
5590         case IOCTL_TX_MSG(GET_DISC):
5591                 bpctl_cmd.status = get_disc_fn(pbpctl_dev);
5592                 break;
5593         case IOCTL_TX_MSG(GET_DISC_CHANGE):
5594                 bpctl_cmd.status = get_disc_change_fn(pbpctl_dev);
5595                 break;
5596         case IOCTL_TX_MSG(SET_DIS_DISC):
5597                 bpctl_cmd.status =
5598                     set_dis_disc_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5599                 break;
5600         case IOCTL_TX_MSG(GET_DIS_DISC):
5601                 bpctl_cmd.status = get_dis_disc_fn(pbpctl_dev);
5602                 break;
5603         case IOCTL_TX_MSG(SET_DISC_PWUP):
5604                 bpctl_cmd.status =
5605                     set_disc_pwup_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5606                 break;
5607         case IOCTL_TX_MSG(GET_DISC_PWUP):
5608                 bpctl_cmd.status = get_disc_pwup_fn(pbpctl_dev);
5609                 break;
5610
5611         case IOCTL_TX_MSG(GET_BYPASS_INFO):
5612
5613                 bpctl_cmd.status =
5614                     get_bypass_info_fn(pbpctl_dev, (char *)&bpctl_cmd.data,
5615                                        (char *)&bpctl_cmd.out_param[4]);
5616                 break;
5617
5618         case IOCTL_TX_MSG(SET_TPL):
5619                 bpctl_cmd.status =
5620                     set_tpl_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5621                 break;
5622
5623         case IOCTL_TX_MSG(GET_TPL):
5624                 bpctl_cmd.status = get_tpl_fn(pbpctl_dev);
5625                 break;
5626         case IOCTL_TX_MSG(SET_BP_WAIT_AT_PWUP):
5627                 bpctl_cmd.status =
5628                     set_bp_wait_at_pwup_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5629                 break;
5630
5631         case IOCTL_TX_MSG(GET_BP_WAIT_AT_PWUP):
5632                 bpctl_cmd.status = get_bp_wait_at_pwup_fn(pbpctl_dev);
5633                 break;
5634         case IOCTL_TX_MSG(SET_BP_HW_RESET):
5635                 bpctl_cmd.status =
5636                     set_bp_hw_reset_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5637                 break;
5638
5639         case IOCTL_TX_MSG(GET_BP_HW_RESET):
5640                 bpctl_cmd.status = get_bp_hw_reset_fn(pbpctl_dev);
5641                 break;
5642 #ifdef BP_SELF_TEST
5643         case IOCTL_TX_MSG(SET_BP_SELF_TEST):
5644                 bpctl_cmd.status =
5645                     set_bp_self_test_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5646
5647                 break;
5648         case IOCTL_TX_MSG(GET_BP_SELF_TEST):
5649                 bpctl_cmd.status = get_bp_self_test_fn(pbpctl_dev);
5650                 break;
5651
5652 #endif
5653 #if 0
5654         case IOCTL_TX_MSG(SET_DISC_PORT):
5655                 bpctl_cmd.status =
5656                     set_disc_port_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5657                 break;
5658
5659         case IOCTL_TX_MSG(GET_DISC_PORT):
5660                 bpctl_cmd.status = get_disc_port_fn(pbpctl_dev);
5661                 break;
5662
5663         case IOCTL_TX_MSG(SET_DISC_PORT_PWUP):
5664                 bpctl_cmd.status =
5665                     set_disc_port_pwup_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5666                 break;
5667
5668         case IOCTL_TX_MSG(GET_DISC_PORT_PWUP):
5669                 bpctl_cmd.status = get_disc_port_pwup_fn(pbpctl_dev);
5670                 break;
5671 #endif
5672         case IOCTL_TX_MSG(SET_BP_FORCE_LINK):
5673                 bpctl_cmd.status =
5674                     set_bp_force_link_fn(dev_idx, bpctl_cmd.in_param[2]);
5675                 break;
5676
5677         case IOCTL_TX_MSG(GET_BP_FORCE_LINK):
5678                 bpctl_cmd.status = get_bp_force_link_fn(dev_idx);
5679                 break;
5680
5681         default:
5682                 /*    unlock_bpctl(); */
5683
5684                 ret = -EOPNOTSUPP;
5685                 /* preempt_enable(); */
5686                 /* rcu_read_unlock();*/
5687                 spin_unlock_irqrestore(&bpvm_lock, flags);
5688                 goto bp_exit;
5689         }
5690         /* unlock_bpctl();   */
5691         /* preempt_enable(); */
5692  bpcmd_exit:
5693         /* rcu_read_unlock(); */
5694         spin_unlock_irqrestore(&bpvm_lock, flags);
5695         if (copy_to_user(argp, (void *)&bpctl_cmd, sizeof(struct bpctl_cmd)))
5696                 ret = -EFAULT;
5697         ret = SUCCESS;
5698  bp_exit:
5699         /* unlock_kernel(); */
5700         /* spin_unlock_irqrestore(&bpvm_lock, flags); */
5701         unlock_bpctl();
5702         /* unlock_kernel(); */
5703         return ret;
5704 }
5705
5706 static const struct file_operations Fops = {
5707         .owner = THIS_MODULE,
5708         .unlocked_ioctl = device_ioctl,
5709 };
5710
5711 #ifndef PCI_DEVICE
5712 #define PCI_DEVICE(vend, dev) \
5713         .vendor = (vend), .device = (dev), \
5714         .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
5715 #endif
5716
5717 #define SILICOM_E1000BP_ETHERNET_DEVICE(device_id) {\
5718         PCI_DEVICE(SILICOM_VID, device_id)}
5719
5720 enum board_type {
5721         PXG2BPFI,
5722         PXG2BPFIL,
5723         PXG2BPFILX,
5724         PXG2BPFILLX,
5725         PXGBPI,
5726         PXGBPIG,
5727         PXG2TBFI,
5728         PXG4BPI,
5729         PXG4BPFI,
5730         PEG4BPI,
5731         PEG2BPI,
5732         PEG4BPIN,
5733         PEG2BPFI,
5734         PEG2BPFILX,
5735         PMCXG2BPFI,
5736         PMCXG2BPFIN,
5737         PEG4BPII,
5738         PEG4BPFII,
5739         PXG4BPFILX,
5740         PMCXG2BPIN,
5741         PMCXG4BPIN,
5742         PXG2BISC1,
5743         PEG2TBFI,
5744         PXG2TBI,
5745         PXG4BPFID,
5746         PEG4BPFI,
5747         PEG4BPIPT,
5748         PXG6BPI,
5749         PEG4BPIL,
5750         PMCXG2BPIN2,
5751         PMCXG4BPIN2,
5752         PMCX2BPI,
5753         PEG2BPFID,
5754         PEG2BPFIDLX,
5755         PMCX4BPI,
5756         MEG2BPFILN,
5757         MEG2BPFINX,
5758         PEG4BPFILX,
5759         PE10G2BPISR,
5760         PE10G2BPILR,
5761         MHIO8AD,
5762         PE10G2BPICX4,
5763         PEG2BPI5,
5764         PEG6BPI,
5765         PEG4BPFI5,
5766         PEG4BPFI5LX,
5767         MEG2BPFILXLN,
5768         PEG2BPIX1,
5769         MEG2BPFILXNX,
5770         XE10G2BPIT,
5771         XE10G2BPICX4,
5772         XE10G2BPISR,
5773         XE10G2BPILR,
5774         PEG4BPIIO,
5775         XE10G2BPIXR,
5776         PE10GDBISR,
5777         PE10GDBILR,
5778         PEG2BISC6,
5779         PEG6BPIFC,
5780         PE10G2BPTCX4,
5781         PE10G2BPTSR,
5782         PE10G2BPTLR,
5783         PE10G2BPTT,
5784         PEG4BPI6,
5785         PEG4BPFI6,
5786         PEG4BPFI6LX,
5787         PEG4BPFI6ZX,
5788         PEG2BPI6,
5789         PEG2BPFI6,
5790         PEG2BPFI6LX,
5791         PEG2BPFI6ZX,
5792         PEG2BPFI6FLXM,
5793         PEG4BPI6FC,
5794         PEG4BPFI6FC,
5795         PEG4BPFI6FCLX,
5796         PEG4BPFI6FCZX,
5797         PEG6BPI6,
5798         PEG2BPI6SC6,
5799         MEG2BPI6,
5800         XEG2BPI6,
5801         MEG4BPI6,
5802         PEG2BPFI5,
5803         PEG2BPFI5LX,
5804         PXEG4BPFI,
5805         M1EG2BPI6,
5806         M1EG2BPFI6,
5807         M1EG2BPFI6LX,
5808         M1EG2BPFI6ZX,
5809         M1EG4BPI6,
5810         M1EG4BPFI6,
5811         M1EG4BPFI6LX,
5812         M1EG4BPFI6ZX,
5813         M1EG6BPI6,
5814         M1E2G4BPi80,
5815         M1E2G4BPFi80,
5816         M1E2G4BPFi80LX,
5817         M1E2G4BPFi80ZX,
5818         PE210G2SPI9,
5819         M1E10G2BPI9CX4,
5820         M1E10G2BPI9SR,
5821         M1E10G2BPI9LR,
5822         M1E10G2BPI9T,
5823         PE210G2BPI9CX4,
5824         PE210G2BPI9SR,
5825         PE210G2BPI9LR,
5826         PE210G2BPI9T,
5827         M2EG2BPFI6,
5828         M2EG2BPFI6LX,
5829         M2EG2BPFI6ZX,
5830         M2EG4BPI6,
5831         M2EG4BPFI6,
5832         M2EG4BPFI6LX,
5833         M2EG4BPFI6ZX,
5834         M2EG6BPI6,
5835         PEG2DBI6,
5836         PEG2DBFI6,
5837         PEG2DBFI6LX,
5838         PEG2DBFI6ZX,
5839         PE2G4BPi80,
5840         PE2G4BPFi80,
5841         PE2G4BPFi80LX,
5842         PE2G4BPFi80ZX,
5843         PE2G4BPi80L,
5844         M6E2G8BPi80A,
5845
5846         PE2G2BPi35,
5847         PAC1200BPi35,
5848         PE2G2BPFi35,
5849         PE2G2BPFi35LX,
5850         PE2G2BPFi35ZX,
5851         PE2G4BPi35,
5852         PE2G4BPi35L,
5853         PE2G4BPFi35,
5854         PE2G4BPFi35LX,
5855         PE2G4BPFi35ZX,
5856
5857         PE2G6BPi35,
5858         PE2G6BPi35CX,
5859
5860         PE2G2BPi80,
5861         PE2G2BPFi80,
5862         PE2G2BPFi80LX,
5863         PE2G2BPFi80ZX,
5864         M2E10G2BPI9CX4,
5865         M2E10G2BPI9SR,
5866         M2E10G2BPI9LR,
5867         M2E10G2BPI9T,
5868         M6E2G8BPi80,
5869         PE210G2DBi9SR,
5870         PE210G2DBi9SRRB,
5871         PE210G2DBi9LR,
5872         PE210G2DBi9LRRB,
5873         PE310G4DBi940SR,
5874         PE310G4BPi9T,
5875         PE310G4BPi9SR,
5876         PE310G4BPi9LR,
5877         PE210G2BPi40,
5878 };
5879
5880 struct bpmod_info {
5881         unsigned int vendor;
5882         unsigned int device;
5883         unsigned int subvendor;
5884         unsigned int subdevice;
5885         unsigned int index;
5886         char *bp_name;
5887
5888 };
5889
5890 struct {
5891         char *name;
5892 } dev_desc[] = {
5893         {"Silicom Bypass PXG2BPFI-SD series adapter"},
5894         {"Silicom Bypass PXG2BPFIL-SD series adapter"},
5895         {"Silicom Bypass PXG2BPFILX-SD series adapter"},
5896         {"Silicom Bypass PXG2BPFILLX-SD series adapter"},
5897         {"Silicom Bypass PXG2BPI-SD series adapter"},
5898         {"Silicom Bypass PXG2BPIG-SD series adapter"},
5899         {"Silicom Bypass PXG2TBFI-SD series adapter"},
5900         {"Silicom Bypass PXG4BPI-SD series adapter"},
5901         {"Silicom Bypass PXG4BPFI-SD series adapter"},
5902         {"Silicom Bypass PEG4BPI-SD series adapter"},
5903         {"Silicom Bypass PEG2BPI-SD series adapter"},
5904         {"Silicom Bypass PEG4BPIN-SD series adapter"},
5905         {"Silicom Bypass PEG2BPFI-SD series adapter"},
5906         {"Silicom Bypass PEG2BPFI-LX-SD series adapter"},
5907         {"Silicom Bypass PMCX2BPFI-SD series adapter"},
5908         {"Silicom Bypass PMCX2BPFI-N series adapter"},
5909         {"Intel Bypass PEG2BPII series adapter"},
5910         {"Intel Bypass PEG2BPFII series adapter"},
5911         {"Silicom Bypass PXG4BPFILX-SD series adapter"},
5912         {"Silicom Bypass PMCX2BPI-N series adapter"},
5913         {"Silicom Bypass PMCX4BPI-N series adapter"},
5914         {"Silicom Bypass PXG2BISC1-SD series adapter"},
5915         {"Silicom Bypass PEG2TBFI-SD series adapter"},
5916         {"Silicom Bypass PXG2TBI-SD series adapter"},
5917         {"Silicom Bypass PXG4BPFID-SD series adapter"},
5918         {"Silicom Bypass PEG4BPFI-SD series adapter"},
5919         {"Silicom Bypass PEG4BPIPT-SD series adapter"},
5920         {"Silicom Bypass PXG6BPI-SD series adapter"},
5921         {"Silicom Bypass PEG4BPIL-SD series adapter"},
5922         {"Silicom Bypass PMCX2BPI-N2 series adapter"},
5923         {"Silicom Bypass PMCX4BPI-N2 series adapter"},
5924         {"Silicom Bypass PMCX2BPI-SD series adapter"},
5925         {"Silicom Bypass PEG2BPFID-SD series adapter"},
5926         {"Silicom Bypass PEG2BPFIDLX-SD series adapter"},
5927         {"Silicom Bypass PMCX4BPI-SD series adapter"},
5928         {"Silicom Bypass MEG2BPFILN-SD series adapter"},
5929         {"Silicom Bypass MEG2BPFINX-SD series adapter"},
5930         {"Silicom Bypass PEG4BPFILX-SD series adapter"},
5931         {"Silicom Bypass PE10G2BPISR-SD series adapter"},
5932         {"Silicom Bypass PE10G2BPILR-SD series adapter"},
5933         {"Silicom Bypass MHIO8AD-SD series adapter"},
5934         {"Silicom Bypass PE10G2BPICX4-SD series adapter"},
5935         {"Silicom Bypass PEG2BPI5-SD series adapter"},
5936         {"Silicom Bypass PEG6BPI5-SD series adapter"},
5937         {"Silicom Bypass PEG4BPFI5-SD series adapter"},
5938         {"Silicom Bypass PEG4BPFI5LX-SD series adapter"},
5939         {"Silicom Bypass MEG2BPFILXLN-SD series adapter"},
5940         {"Silicom Bypass PEG2BPIX1-SD series adapter"},
5941         {"Silicom Bypass MEG2BPFILXNX-SD series adapter"},
5942         {"Silicom Bypass XE10G2BPIT-SD series adapter"},
5943         {"Silicom Bypass XE10G2BPICX4-SD series adapter"},
5944         {"Silicom Bypass XE10G2BPISR-SD series adapter"},
5945         {"Silicom Bypass XE10G2BPILR-SD series adapter"},
5946         {"Intel Bypass PEG2BPFII0 series adapter"},
5947         {"Silicom Bypass XE10G2BPIXR series adapter"},
5948         {"Silicom Bypass PE10G2DBISR series adapter"},
5949         {"Silicom Bypass PEG2BI5SC6 series adapter"},
5950         {"Silicom Bypass PEG6BPI5FC series adapter"},
5951
5952         {"Silicom Bypass PE10G2BPTCX4 series adapter"},
5953         {"Silicom Bypass PE10G2BPTSR series adapter"},
5954         {"Silicom Bypass PE10G2BPTLR series adapter"},
5955         {"Silicom Bypass PE10G2BPTT series adapter"},
5956         {"Silicom Bypass PEG4BPI6 series adapter"},
5957         {"Silicom Bypass PEG4BPFI6 series adapter"},
5958         {"Silicom Bypass PEG4BPFI6LX series adapter"},
5959         {"Silicom Bypass PEG4BPFI6ZX series adapter"},
5960         {"Silicom Bypass PEG2BPI6 series adapter"},
5961         {"Silicom Bypass PEG2BPFI6 series adapter"},
5962         {"Silicom Bypass PEG2BPFI6LX series adapter"},
5963         {"Silicom Bypass PEG2BPFI6ZX series adapter"},
5964         {"Silicom Bypass PEG2BPFI6FLXM series adapter"},
5965         {"Silicom Bypass PEG4BPI6FC series adapter"},
5966         {"Silicom Bypass PEG4BPFI6FC series adapter"},
5967         {"Silicom Bypass PEG4BPFI6FCLX series adapter"},
5968         {"Silicom Bypass PEG4BPFI6FCZX series adapter"},
5969         {"Silicom Bypass PEG6BPI6 series adapter"},
5970         {"Silicom Bypass PEG2BPI6SC6 series adapter"},
5971         {"Silicom Bypass MEG2BPI6 series adapter"},
5972         {"Silicom Bypass XEG2BPI6 series adapter"},
5973         {"Silicom Bypass MEG4BPI6 series adapter"},
5974         {"Silicom Bypass PEG2BPFI5-SD series adapter"},
5975         {"Silicom Bypass PEG2BPFI5LX-SD series adapter"},
5976         {"Silicom Bypass PXEG4BPFI-SD series adapter"},
5977         {"Silicom Bypass MxEG2BPI6 series adapter"},
5978         {"Silicom Bypass MxEG2BPFI6 series adapter"},
5979         {"Silicom Bypass MxEG2BPFI6LX series adapter"},
5980         {"Silicom Bypass MxEG2BPFI6ZX series adapter"},
5981         {"Silicom Bypass MxEG4BPI6 series adapter"},
5982         {"Silicom Bypass MxEG4BPFI6 series adapter"},
5983         {"Silicom Bypass MxEG4BPFI6LX series adapter"},
5984         {"Silicom Bypass MxEG4BPFI6ZX series adapter"},
5985         {"Silicom Bypass MxEG6BPI6 series adapter"},
5986         {"Silicom Bypass MxE2G4BPi80 series adapter"},
5987         {"Silicom Bypass MxE2G4BPFi80 series adapter"},
5988         {"Silicom Bypass MxE2G4BPFi80LX series adapter"},
5989         {"Silicom Bypass MxE2G4BPFi80ZX series adapter"},
5990
5991         {"Silicom Bypass PE210G2SPI9 series adapter"},
5992
5993         {"Silicom Bypass MxE210G2BPI9CX4 series adapter"},
5994         {"Silicom Bypass MxE210G2BPI9SR series adapter"},
5995         {"Silicom Bypass MxE210G2BPI9LR series adapter"},
5996         {"Silicom Bypass MxE210G2BPI9T series adapter"},
5997
5998         {"Silicom Bypass PE210G2BPI9CX4 series adapter"},
5999         {"Silicom Bypass PE210G2BPI9SR series adapter"},
6000         {"Silicom Bypass PE210G2BPI9LR series adapter"},
6001         {"Silicom Bypass PE210G2BPI9T series adapter"},
6002
6003         {"Silicom Bypass M2EG2BPFI6 series adapter"},
6004         {"Silicom Bypass M2EG2BPFI6LX series adapter"},
6005         {"Silicom Bypass M2EG2BPFI6ZX series adapter"},
6006         {"Silicom Bypass M2EG4BPI6 series adapter"},
6007         {"Silicom Bypass M2EG4BPFI6 series adapter"},
6008         {"Silicom Bypass M2EG4BPFI6LX series adapter"},
6009         {"Silicom Bypass M2EG4BPFI6ZX series adapter"},
6010         {"Silicom Bypass M2EG6BPI6 series adapter"},
6011
6012         {"Silicom Bypass PEG2DBI6    series adapter"},
6013         {"Silicom Bypass PEG2DBFI6   series adapter"},
6014         {"Silicom Bypass PEG2DBFI6LX series adapter"},
6015         {"Silicom Bypass PEG2DBFI6ZX series adapter"},
6016
6017         {"Silicom Bypass PE2G4BPi80 series adapter"},
6018         {"Silicom Bypass PE2G4BPFi80 series adapter"},
6019         {"Silicom Bypass PE2G4BPFi80LX series adapter"},
6020         {"Silicom Bypass PE2G4BPFi80ZX series adapter"},
6021
6022         {"Silicom Bypass PE2G4BPi80L series adapter"},
6023         {"Silicom Bypass MxE2G8BPi80A series adapter"},
6024
6025         {"Silicom Bypass PE2G2BPi35 series adapter"},
6026         {"Silicom Bypass PAC1200BPi35 series adapter"},
6027         {"Silicom Bypass PE2G2BPFi35 series adapter"},
6028         {"Silicom Bypass PE2G2BPFi35LX series adapter"},
6029         {"Silicom Bypass PE2G2BPFi35ZX series adapter"},
6030
6031         {"Silicom Bypass PE2G4BPi35 series adapter"},
6032         {"Silicom Bypass PE2G4BPi35L series adapter"},
6033         {"Silicom Bypass PE2G4BPFi35 series adapter"},
6034         {"Silicom Bypass PE2G4BPFi35LX series adapter"},
6035         {"Silicom Bypass PE2G4BPFi35ZX series adapter"},
6036
6037         {"Silicom Bypass PE2G6BPi35 series adapter"},
6038         {"Silicom Bypass PE2G6BPi35CX series adapter"},
6039
6040         {"Silicom Bypass PE2G2BPi80 series adapter"},
6041         {"Silicom Bypass PE2G2BPFi80 series adapter"},
6042         {"Silicom Bypass PE2G2BPFi80LX series adapter"},
6043         {"Silicom Bypass PE2G2BPFi80ZX series adapter"},
6044
6045         {"Silicom Bypass M2E10G2BPI9CX4 series adapter"},
6046         {"Silicom Bypass M2E10G2BPI9SR series adapter"},
6047         {"Silicom Bypass M2E10G2BPI9LR series adapter"},
6048         {"Silicom Bypass M2E10G2BPI9T series adapter"},
6049         {"Silicom Bypass MxE2G8BPi80 series adapter"},
6050         {"Silicom Bypass PE210G2DBi9SR series adapter"},
6051         {"Silicom Bypass PE210G2DBi9SRRB series adapter"},
6052         {"Silicom Bypass PE210G2DBi9LR series adapter"},
6053         {"Silicom Bypass PE210G2DBi9LRRB series adapter"},
6054         {"Silicom Bypass PE310G4DBi9-SR series adapter"},
6055         {"Silicom Bypass PE310G4BPi9T series adapter"},
6056         {"Silicom Bypass PE310G4BPi9SR series adapter"},
6057         {"Silicom Bypass PE310G4BPi9LR series adapter"},
6058         {"Silicom Bypass PE210G2BPi40T series adapter"},
6059         {0},
6060 };
6061
6062 static struct bpmod_info tx_ctl_pci_tbl[] = {
6063         {0x8086, 0x107a, SILICOM_SVID, SILICOM_PXG2BPFI_SSID, PXG2BPFI,
6064          "PXG2BPFI-SD"},
6065         {0x8086, 0x107a, SILICOM_SVID, SILICOM_PXG2BPFIL_SSID, PXG2BPFIL,
6066          "PXG2BPFIL-SD"},
6067         {0x8086, 0x107a, SILICOM_SVID, SILICOM_PXG2BPFILX_SSID, PXG2BPFILX,
6068          "PXG2BPFILX-SD"},
6069         {0x8086, 0x107a, SILICOM_SVID, SILICOM_PXG2BPFILLX_SSID, PXG2BPFILLX,
6070          "PXG2BPFILLXSD"},
6071         {0x8086, 0x1010, SILICOM_SVID, SILICOM_PXGBPI_SSID, PXGBPI,
6072          "PXG2BPI-SD"},
6073         {0x8086, 0x1079, SILICOM_SVID, SILICOM_PXGBPIG_SSID, PXGBPIG,
6074          "PXG2BPIG-SD"},
6075         {0x8086, 0x107a, SILICOM_SVID, SILICOM_PXG2TBFI_SSID, PXG2TBFI,
6076          "PXG2TBFI-SD"},
6077         {0x8086, 0x1079, SILICOM_SVID, SILICOM_PXG4BPI_SSID, PXG4BPI,
6078          "PXG4BPI-SD"},
6079         {0x8086, 0x107a, SILICOM_SVID, SILICOM_PXG4BPFI_SSID, PXG4BPFI,
6080          "PXG4BPFI-SD"},
6081         {0x8086, 0x107a, SILICOM_SVID, SILICOM_PXG4BPFILX_SSID, PXG4BPFILX,
6082          "PXG4BPFILX-SD"},
6083         {0x8086, 0x1079, SILICOM_SVID, SILICOM_PEG4BPI_SSID, PEG4BPI,
6084          "PEXG4BPI-SD"},
6085         {0x8086, 0x105e, SILICOM_SVID, SILICOM_PEG2BPI_SSID, PEG2BPI,
6086          "PEG2BPI-SD"},
6087         {0x8086, 0x105e, SILICOM_SVID, SILICOM_PEG4BPIN_SSID, PEG4BPIN,
6088          "PEG4BPI-SD"},
6089         {0x8086, 0x105f, SILICOM_SVID, SILICOM_PEG2BPFI_SSID, PEG2BPFI,
6090          "PEG2BPFI-SD"},
6091         {0x8086, 0x105f, SILICOM_SVID, SILICOM_PEG2BPFILX_SSID, PEG2BPFILX,
6092          "PEG2BPFILX-SD"},
6093         {0x8086, 0x107a, SILICOM_SVID, SILICOM_PMCXG2BPFI_SSID, PMCXG2BPFI,
6094          "PMCX2BPFI-SD"},
6095         {0x8086, 0x107a, NOKIA_PMCXG2BPFIN_SVID, NOKIA_PMCXG2BPFIN_SSID,
6096          PMCXG2BPFIN, "PMCX2BPFI-N"},
6097         {0x8086, INTEL_PEG4BPII_PID, 0x8086, INTEL_PEG4BPII_SSID, PEG4BPII,
6098          "PEG4BPII"},
6099         {0x8086, INTEL_PEG4BPIIO_PID, 0x8086, INTEL_PEG4BPIIO_SSID, PEG4BPIIO,
6100          "PEG4BPII0"},
6101         {0x8086, INTEL_PEG4BPFII_PID, 0x8086, INTEL_PEG4BPFII_SSID, PEG4BPFII,
6102          "PEG4BPFII"},
6103         {0x8086, 0x1079, NOKIA_PMCXG2BPFIN_SVID, NOKIA_PMCXG2BPIN_SSID,
6104          PMCXG2BPIN, "PMCX2BPI-N"},
6105         {0x8086, 0x1079, NOKIA_PMCXG2BPFIN_SVID, NOKIA_PMCXG4BPIN_SSID,
6106          PMCXG4BPIN, "PMCX4BPI-N"},
6107         {0x8086, 0x1079, SILICOM_SVID, SILICOM_PXG2BISC1_SSID, PXG2BISC1,
6108          "PXG2BISC1-SD"},
6109         {0x8086, 0x105f, SILICOM_SVID, SILICOM_PEG2TBFI_SSID, PEG2TBFI,
6110          "PEG2TBFI-SD"},
6111         {0x8086, 0x1079, SILICOM_SVID, SILICOM_PXG2TBI_SSID, PXG2TBI,
6112          "PXG2TBI-SD"},
6113         {0x8086, 0x107a, SILICOM_SVID, SILICOM_PXG4BPFID_SSID, PXG4BPFID,
6114          "PXG4BPFID-SD"},
6115         {0x8086, 0x105f, SILICOM_SVID, SILICOM_PEG4BPFI_SSID, PEG4BPFI,
6116          "PEG4BPFI-SD"},
6117         {0x8086, 0x105e, SILICOM_SVID, SILICOM_PEG4BPIPT_SSID, PEG4BPIPT,
6118          "PEG4BPIPT-SD"},
6119         {0x8086, 0x1079, SILICOM_SVID, SILICOM_PXG6BPI_SSID, PXG6BPI,
6120          "PXG6BPI-SD"},
6121         {0x8086, 0x10a7, SILICOM_SVID /*PCI_ANY_ID */ ,
6122          SILICOM_PEG4BPIL_SSID /*PCI_ANY_ID */ , PEG4BPIL, "PEG4BPIL-SD"},
6123         {0x8086, 0x1079, NOKIA_PMCXG2BPFIN_SVID, NOKIA_PMCXG2BPIN2_SSID,
6124          PMCXG2BPIN2, "PMCX2BPI-N2"},
6125         {0x8086, 0x1079, NOKIA_PMCXG2BPFIN_SVID, NOKIA_PMCXG4BPIN2_SSID,
6126          PMCXG4BPIN2, "PMCX4BPI-N2"},
6127         {0x8086, 0x1079, SILICOM_SVID, SILICOM_PMCX2BPI_SSID, PMCX2BPI,
6128          "PMCX2BPI-SD"},
6129         {0x8086, 0x1079, SILICOM_SVID, SILICOM_PMCX4BPI_SSID, PMCX4BPI,
6130          "PMCX4BPI-SD"},
6131         {0x8086, 0x105f, SILICOM_SVID, SILICOM_PEG2BPFID_SSID, PEG2BPFID,
6132          "PEG2BPFID-SD"},
6133         {0x8086, 0x105f, SILICOM_SVID, SILICOM_PEG2BPFIDLX_SSID, PEG2BPFIDLX,
6134          "PEG2BPFIDLXSD"},
6135         {0x8086, 0x105f, SILICOM_SVID, SILICOM_MEG2BPFILN_SSID, MEG2BPFILN,
6136          "MEG2BPFILN-SD"},
6137         {0x8086, 0x105f, SILICOM_SVID, SILICOM_MEG2BPFINX_SSID, MEG2BPFINX,
6138          "MEG2BPFINX-SD"},
6139         {0x8086, 0x105f, SILICOM_SVID, SILICOM_PEG4BPFILX_SSID, PEG4BPFILX,
6140          "PEG4BPFILX-SD"},
6141         {0x8086, PCI_ANY_ID, SILICOM_SVID, SILICOM_PE10G2BPISR_SSID,
6142          PE10G2BPISR, "PE10G2BPISR"},
6143         {0x8086, PCI_ANY_ID, SILICOM_SVID, SILICOM_PE10G2BPILR_SSID,
6144          PE10G2BPILR, "PE10G2BPILR"},
6145         {0x8086, 0x10a9, SILICOM_SVID, SILICOM_MHIO8AD_SSID, MHIO8AD,
6146          "MHIO8AD-SD"},
6147         {0x8086, PCI_ANY_ID, SILICOM_SVID, SILICOM_PE10G2BPICX4_SSID,
6148          PE10G2BPISR, "PE10G2BPICX4"},
6149         {0x8086, 0x10a7, SILICOM_SVID /*PCI_ANY_ID */ ,
6150          SILICOM_PEG2BPI5_SSID /*PCI_ANY_ID */ , PEG2BPI5, "PEG2BPI5-SD"},
6151         {0x8086, 0x10a7, SILICOM_SVID /*PCI_ANY_ID */ ,
6152          SILICOM_PEG6BPI_SSID /*PCI_ANY_ID */ , PEG6BPI, "PEG6BPI5"},
6153         {0x8086, 0x10a9, SILICOM_SVID /*PCI_ANY_ID */ , SILICOM_PEG4BPFI5_SSID,
6154          PEG4BPFI5, "PEG4BPFI5"},
6155         {0x8086, 0x10a9, SILICOM_SVID /*PCI_ANY_ID */ ,
6156          SILICOM_PEG4BPFI5LX_SSID, PEG4BPFI5LX, "PEG4BPFI5LX"},
6157         {0x8086, 0x105f, SILICOM_SVID, SILICOM_MEG2BPFILXLN_SSID, MEG2BPFILXLN,
6158          "MEG2BPFILXLN"},
6159         {0x8086, 0x105e, SILICOM_SVID, SILICOM_PEG2BPIX1_SSID, PEG2BPIX1,
6160          "PEG2BPIX1-SD"},
6161         {0x8086, 0x105f, SILICOM_SVID, SILICOM_MEG2BPFILXNX_SSID, MEG2BPFILXNX,
6162          "MEG2BPFILXNX"},
6163         {0x8086, PCI_ANY_ID, SILICOM_SVID, SILICOM_XE10G2BPIT_SSID, XE10G2BPIT,
6164          "XE10G2BPIT"},
6165         {0x8086, PCI_ANY_ID, SILICOM_SVID, SILICOM_XE10G2BPICX4_SSID,
6166          XE10G2BPICX4, "XE10G2BPICX4"},
6167         {0x8086, 0x10C6, SILICOM_SVID, SILICOM_XE10G2BPISR_SSID, XE10G2BPISR,
6168          "XE10G2BPISR"},
6169         {0x8086, 0x10C6, SILICOM_SVID, SILICOM_XE10G2BPILR_SSID, XE10G2BPILR,
6170          "XE10G2BPILR"},
6171         {0x8086, 0x10C6, NOKIA_XE10G2BPIXR_SVID, NOKIA_XE10G2BPIXR_SSID,
6172          XE10G2BPIXR, "XE10G2BPIXR"},
6173         {0x8086, 0x10C6, SILICOM_SVID, SILICOM_PE10GDBISR_SSID, PE10GDBISR,
6174          "PE10G2DBISR"},
6175         {0x8086, 0x10C6, SILICOM_SVID, SILICOM_PE10GDBILR_SSID, PE10GDBILR,
6176          "PE10G2DBILR"},
6177         {0x8086, 0x10a7, SILICOM_SVID /*PCI_ANY_ID */ ,
6178          SILICOM_PEG2BISC6_SSID /*PCI_ANY_ID */ , PEG2BISC6, "PEG2BI5SC6"},
6179         {0x8086, 0x10a7, SILICOM_SVID /*PCI_ANY_ID */ ,
6180          SILICOM_PEG6BPIFC_SSID /*PCI_ANY_ID */ , PEG6BPIFC, "PEG6BPI5FC"},
6181
6182         {BROADCOM_VID, BROADCOM_PE10G2_PID, SILICOM_SVID,
6183          SILICOM_PE10G2BPTCX4_SSID, PE10G2BPTCX4, "PE10G2BPTCX4"},
6184         {BROADCOM_VID, BROADCOM_PE10G2_PID, SILICOM_SVID,
6185          SILICOM_PE10G2BPTSR_SSID, PE10G2BPTSR, "PE10G2BPTSR"},
6186         {BROADCOM_VID, BROADCOM_PE10G2_PID, SILICOM_SVID,
6187          SILICOM_PE10G2BPTLR_SSID, PE10G2BPTLR, "PE10G2BPTLR"},
6188         {BROADCOM_VID, BROADCOM_PE10G2_PID, SILICOM_SVID,
6189          SILICOM_PE10G2BPTT_SSID, PE10G2BPTT, "PE10G2BPTT"},
6190
6191         /* {BROADCOM_VID, BROADCOM_PE10G2_PID, PCI_ANY_ID, PCI_ANY_ID, PE10G2BPTCX4, "PE10G2BPTCX4"}, */
6192
6193         {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6194          SILICOM_PEG4BPI6_SSID /*PCI_ANY_ID */ , PEG4BPI6, "PEG4BPI6"},
6195         {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6196          SILICOM_PEG4BPFI6_SSID /*PCI_ANY_ID */ , PEG4BPFI6, "PEG4BPFI6"},
6197         {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6198          SILICOM_PEG4BPFI6LX_SSID /*PCI_ANY_ID */ , PEG4BPFI6LX, "PEG4BPFI6LX"},
6199         {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6200          SILICOM_PEG4BPFI6ZX_SSID /*PCI_ANY_ID */ , PEG4BPFI6ZX, "PEG4BPFI6ZX"},
6201         {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6202          SILICOM_PEG2BPI6_SSID /*PCI_ANY_ID */ , PEG2BPI6, "PEG2BPI6"},
6203         {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6204          SILICOM_PEG2BPFI6_SSID /*PCI_ANY_ID */ , PEG2BPFI6, "PEG2BPFI6"},
6205         {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6206          SILICOM_PEG2BPFI6LX_SSID /*PCI_ANY_ID */ , PEG2BPFI6LX, "PEG2BPFI6LX"},
6207         {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6208          SILICOM_PEG2BPFI6ZX_SSID /*PCI_ANY_ID */ , PEG2BPFI6ZX, "PEG2BPFI6ZX"},
6209         {0x8086, 0x10e7, SILICOM_SVID /*PCI_ANY_ID */ ,
6210          SILICOM_PEG2BPFI6FLXM_SSID /*PCI_ANY_ID */ , PEG2BPFI6FLXM,
6211          "PEG2BPFI6FLXM"},
6212         {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6213          SILICOM_PEG4BPI6FC_SSID /*PCI_ANY_ID */ , PEG4BPI6FC, "PEG4BPI6FC"},
6214         {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6215          SILICOM_PEG4BPFI6FC_SSID /*PCI_ANY_ID */ , PEG4BPFI6FC, "PEG4BPFI6FC"},
6216         {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6217          SILICOM_PEG4BPFI6FCLX_SSID /*PCI_ANY_ID */ , PEG4BPFI6FCLX,
6218          "PEG4BPFI6FCLX"},
6219         {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6220          SILICOM_PEG4BPFI6FCZX_SSID /*PCI_ANY_ID */ , PEG4BPFI6FCZX,
6221          "PEG4BPFI6FCZX"},
6222         {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6223          SILICOM_PEG6BPI6_SSID /*PCI_ANY_ID */ , PEG6BPI6, "PEG6BPI6"},
6224         {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6225          SILICOM_PEG2BPI6SC6_SSID /*PCI_ANY_ID */ , PEG2BPI6SC6,
6226          "PEG6BPI62SC6"},
6227         {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6228          SILICOM_MEG2BPI6_SSID /*PCI_ANY_ID */ , MEG2BPI6, "MEG2BPI6"},
6229         {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6230          SILICOM_XEG2BPI6_SSID /*PCI_ANY_ID */ , XEG2BPI6, "XEG2BPI6"},
6231         {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6232          SILICOM_MEG4BPI6_SSID /*PCI_ANY_ID */ , MEG4BPI6, "MEG4BPI6"},
6233
6234         {0x8086, 0x10a9, SILICOM_SVID /*PCI_ANY_ID */ , SILICOM_PEG2BPFI5_SSID,
6235          PEG2BPFI5, "PEG2BPFI5"},
6236         {0x8086, 0x10a9, SILICOM_SVID /*PCI_ANY_ID */ ,
6237          SILICOM_PEG2BPFI5LX_SSID, PEG2BPFI5LX, "PEG2BPFI5LX"},
6238
6239         {0x8086, 0x105f, SILICOM_SVID, SILICOM_PXEG4BPFI_SSID, PXEG4BPFI,
6240          "PXEG4BPFI-SD"},
6241
6242         {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6243          SILICOM_M1EG2BPI6_SSID /*PCI_ANY_ID */ , M1EG2BPI6, "MxEG2BPI6"},
6244
6245         {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6246          SILICOM_M1EG2BPFI6_SSID /*PCI_ANY_ID */ , M1EG2BPFI6, "MxEG2BPFI6"},
6247         {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6248          SILICOM_M1EG2BPFI6LX_SSID /*PCI_ANY_ID */ , M1EG2BPFI6LX,
6249          "MxEG2BPFI6LX"},
6250         {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6251          SILICOM_M1EG2BPFI6ZX_SSID /*PCI_ANY_ID */ , M1EG2BPFI6ZX,
6252          "MxEG2BPFI6ZX"},
6253
6254         {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6255          SILICOM_M1EG4BPI6_SSID /*PCI_ANY_ID */ , M1EG4BPI6, "MxEG4BPI6"},
6256
6257         {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6258          SILICOM_M1EG4BPFI6_SSID /*PCI_ANY_ID */ , M1EG4BPFI6, "MxEG4BPFI6"},
6259         {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6260          SILICOM_M1EG4BPFI6LX_SSID /*PCI_ANY_ID */ , M1EG4BPFI6LX,
6261          "MxEG4BPFI6LX"},
6262         {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6263          SILICOM_M1EG4BPFI6ZX_SSID /*PCI_ANY_ID */ , M1EG4BPFI6ZX,
6264          "MxEG4BPFI6ZX"},
6265
6266         {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6267          SILICOM_M1EG6BPI6_SSID /*PCI_ANY_ID */ , M1EG6BPI6, "MxEG6BPI6"},
6268
6269         {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6270          SILICOM_M1E2G4BPi80_SSID /*PCI_ANY_ID */ , M1E2G4BPi80, "MxE2G4BPi80"},
6271         {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6272          SILICOM_M1E2G4BPFi80_SSID /*PCI_ANY_ID */ , M1E2G4BPFi80,
6273          "MxE2G4BPFi80"},
6274         {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6275          SILICOM_M1E2G4BPFi80LX_SSID /*PCI_ANY_ID */ , M1E2G4BPFi80LX,
6276          "MxE2G4BPFi80LX"},
6277         {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6278          SILICOM_M1E2G4BPFi80ZX_SSID /*PCI_ANY_ID */ , M1E2G4BPFi80ZX,
6279          "MxE2G4BPFi80ZX"},
6280
6281         {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6282          SILICOM_M2EG2BPFI6_SSID /*PCI_ANY_ID */ , M2EG2BPFI6, "M2EG2BPFI6"},
6283         {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6284          SILICOM_M2EG2BPFI6LX_SSID /*PCI_ANY_ID */ , M2EG2BPFI6LX,
6285          "M2EG2BPFI6LX"},
6286         {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6287          SILICOM_M2EG2BPFI6ZX_SSID /*PCI_ANY_ID */ , M2EG2BPFI6ZX,
6288          "M2EG2BPFI6ZX"},
6289
6290         {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6291          SILICOM_M2EG4BPI6_SSID /*PCI_ANY_ID */ , M2EG4BPI6, "M2EG4BPI6"},
6292
6293         {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6294          SILICOM_M2EG4BPFI6_SSID /*PCI_ANY_ID */ , M2EG4BPFI6, "M2EG4BPFI6"},
6295         {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6296          SILICOM_M2EG4BPFI6LX_SSID /*PCI_ANY_ID */ , M2EG4BPFI6LX,
6297          "M2EG4BPFI6LX"},
6298         {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6299          SILICOM_M2EG4BPFI6ZX_SSID /*PCI_ANY_ID */ , M2EG4BPFI6ZX,
6300          "M2EG4BPFI6ZX"},
6301
6302         {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6303          SILICOM_M2EG6BPI6_SSID /*PCI_ANY_ID */ , M2EG6BPI6, "M2EG6BPI6"},
6304
6305         {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6306          SILICOM_PEG2DBI6_SSID /*PCI_ANY_ID */ , PEG2DBI6, "PEG2DBI6"},
6307         {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6308          SILICOM_PEG2DBFI6_SSID /*PCI_ANY_ID */ , PEG2DBFI6, "PEG2DBFI6"},
6309         {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6310          SILICOM_PEG2DBFI6LX_SSID /*PCI_ANY_ID */ , PEG2DBFI6LX, "PEG2DBFI6LX"},
6311         {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6312          SILICOM_PEG2DBFI6ZX_SSID /*PCI_ANY_ID */ , PEG2DBFI6ZX, "PEG2DBFI6ZX"},
6313
6314         {0x8086, 0x10F9, SILICOM_SVID /*PCI_ANY_ID */ ,
6315          SILICOM_PE210G2DBi9SR_SSID, PE210G2DBi9SR, "PE210G2DBi9SR"},
6316         {0x8086, 0x10F9, SILICOM_SVID /*PCI_ANY_ID */ ,
6317          SILICOM_PE210G2DBi9LR_SSID, PE210G2DBi9LR, "PE210G2DBi9LR"},
6318         {0x8086, 0x10F9, SILICOM_SVID /*PCI_ANY_ID */ ,
6319          SILICOM_PE310G4DBi940SR_SSID, PE310G4DBi940SR, "PE310G4DBi9SR"},
6320
6321         {0x8086, 0x10Fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6322          SILICOM_PE310G4BPi9T_SSID, PE310G4BPi9T, "PE310G4BPi9T"},
6323         {0x8086, 0x10Fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6324          SILICOM_PE310G4BPi9SR_SSID, PE310G4BPi9SR, "PE310G4BPi9SR"},
6325         {0x8086, 0x10Fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6326          SILICOM_PE310G4BPi9LR_SSID, PE310G4BPi9LR, "PE310G4BPi9LR"},
6327
6328         {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6329          SILICOM_PE2G4BPi80_SSID /*PCI_ANY_ID */ , PE2G4BPi80, "PE2G4BPi80"},
6330         {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6331          SILICOM_PE2G4BPFi80_SSID /*PCI_ANY_ID */ , PE2G4BPFi80, "PE2G4BPFi80"},
6332         {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6333          SILICOM_PE2G4BPFi80LX_SSID /*PCI_ANY_ID */ , PE2G4BPFi80LX,
6334          "PE2G4BPFi80LX"},
6335         {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6336          SILICOM_PE2G4BPFi80ZX_SSID /*PCI_ANY_ID */ , PE2G4BPFi80ZX,
6337          "PE2G4BPFi80ZX"},
6338
6339         {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6340          SILICOM_PE2G4BPi80L_SSID /*PCI_ANY_ID */ , PE2G4BPi80L, "PE2G4BPi80L"},
6341
6342         {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6343          SILICOM_M6E2G8BPi80A_SSID /*PCI_ANY_ID */ , M6E2G8BPi80A,
6344          "MxE2G8BPi80A"},
6345
6346         {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6347          SILICOM_PE2G2BPi35_SSID /*PCI_ANY_ID */ , PE2G2BPi35, "PE2G2BPi35"},
6348         {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6349          SILICOM_PAC1200BPi35_SSID /*PCI_ANY_ID */ , PAC1200BPi35,
6350          "PAC1200BPi35"},
6351
6352         {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6353          SILICOM_PE2G2BPFi35_SSID /*PCI_ANY_ID */ , PE2G2BPFi35, "PE2G2BPFi35"},
6354         {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6355          SILICOM_PE2G2BPFi35LX_SSID /*PCI_ANY_ID */ , PE2G2BPFi35LX,
6356          "PE2G2BPFi35LX"},
6357         {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6358          SILICOM_PE2G2BPFi35ZX_SSID /*PCI_ANY_ID */ , PE2G2BPFi35ZX,
6359          "PE2G2BPFi35ZX"},
6360
6361         {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6362          SILICOM_PE2G4BPi35_SSID /*PCI_ANY_ID */ , PE2G4BPi35, "PE2G4BPi35"},
6363
6364         {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6365          SILICOM_PE2G4BPi35L_SSID /*PCI_ANY_ID */ , PE2G4BPi35L, "PE2G4BPi35L"},
6366
6367         {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6368          SILICOM_PE2G4BPFi35_SSID /*PCI_ANY_ID */ , PE2G4BPFi35, "PE2G4BPFi35"},
6369         {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6370          SILICOM_PE2G4BPFi35LX_SSID /*PCI_ANY_ID */ , PE2G4BPFi35LX,
6371          "PE2G4BPFi35LX"},
6372         {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6373          SILICOM_PE2G4BPFi35ZX_SSID /*PCI_ANY_ID */ , PE2G4BPFi35ZX,
6374          "PE2G4BPFi35ZX"},
6375
6376         {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6377          SILICOM_PE2G6BPi35_SSID /*PCI_ANY_ID */ , PE2G6BPi35, "PE2G6BPi35"},
6378
6379
6380         {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa0, PE2G6BPi35CX,
6381          "PE2G6BPi35CX"},
6382         {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa1, PE2G6BPi35CX,
6383          "PE2G6BPi35CX"},
6384         {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa2, PE2G6BPi35CX,
6385          "PE2G6BPi35CX"},
6386         {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa3, PE2G6BPi35CX,
6387          "PE2G6BPi35CX"},
6388         {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa4, PE2G6BPi35CX,
6389          "PE2G6BPi35CX"},
6390         {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa5, PE2G6BPi35CX,
6391          "PE2G6BPi35CX"},
6392         {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa6, PE2G6BPi35CX,
6393          "PE2G6BPi35CX"},
6394         {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa7, PE2G6BPi35CX,
6395          "PE2G6BPi35CX"},
6396         {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa8, PE2G6BPi35CX,
6397          "PE2G6BPi35CX"},
6398         {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa9, PE2G6BPi35CX,
6399          "PE2G6BPi35CX"},
6400         {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaaa, PE2G6BPi35CX,
6401          "PE2G6BPi35CX"},
6402         {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaab, PE2G6BPi35CX,
6403          "PE2G6BPi35CX"},
6404         {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaac, PE2G6BPi35CX,
6405          "PE2G6BPi35CX"},
6406         {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaad, PE2G6BPi35CX,
6407          "PE2G6BPi35CX"},
6408         {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaae, PE2G6BPi35CX,
6409          "PE2G6BPi35CX"},
6410         {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaaf, PE2G6BPi35CX,
6411          "PE2G6BPi35CX"},
6412         {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab0, PE2G6BPi35CX,
6413          "PE2G6BPi35CX"},
6414         {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab1, PE2G6BPi35CX,
6415          "PE2G6BPi35CX"},
6416         {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab2, PE2G6BPi35CX,
6417          "PE2G6BPi35CX"},
6418         {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab3, PE2G6BPi35CX,
6419          "PE2G6BPi35CX"},
6420         {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab4, PE2G6BPi35CX,
6421          "PE2G6BPi35CX"},
6422         {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab5, PE2G6BPi35CX,
6423          "PE2G6BPi35CX"},
6424         {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab6, PE2G6BPi35CX,
6425          "PE2G6BPi35CX"},
6426         {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab7, PE2G6BPi35CX,
6427          "PE2G6BPi35CX"},
6428         {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab8, PE2G6BPi35CX,
6429          "PE2G6BPi35CX"},
6430         {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab9, PE2G6BPi35CX,
6431          "PE2G6BPi35CX"},
6432         {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaba, PE2G6BPi35CX,
6433          "PE2G6BPi35CX"},
6434         {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xabb, PE2G6BPi35CX,
6435          "PE2G6BPi35CX"},
6436         {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xabc, PE2G6BPi35CX,
6437          "PE2G6BPi35CX"},
6438         {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xabd, PE2G6BPi35CX,
6439          "PE2G6BPi35CX"},
6440         {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xabe, PE2G6BPi35CX,
6441          "PE2G6BPi35CX"},
6442         {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xabf, PE2G6BPi35CX,
6443          "PE2G6BPi35CX"},
6444
6445         {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6446          SILICOM_PE2G2BPi80_SSID /*PCI_ANY_ID */ , PE2G2BPi80, "PE2G2BPi80"},
6447         {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6448          SILICOM_PE2G2BPFi80_SSID /*PCI_ANY_ID */ , PE2G2BPFi80, "PE2G2BPFi80"},
6449         {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6450          SILICOM_PE2G2BPFi80LX_SSID /*PCI_ANY_ID */ , PE2G2BPFi80LX,
6451          "PE2G2BPFi80LX"},
6452         {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6453          SILICOM_PE2G2BPFi80ZX_SSID /*PCI_ANY_ID */ , PE2G2BPFi80ZX,
6454          "PE2G2BPFi80ZX"},
6455
6456         {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6457          SILICOM_MEG2BPI6_SSID /*PCI_ANY_ID */ , MEG2BPI6, "MEG2BPI6"},
6458         {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6459          SILICOM_XEG2BPI6_SSID /*PCI_ANY_ID */ , XEG2BPI6, "XEG2BPI6"},
6460
6461 #if 0
6462         {0x8086, 0x10fb, 0x8086, INTEL_PE210G2SPI9_SSID, PE210G2SPI9,
6463          "PE210G2SPI9"},
6464 #endif
6465         {0x8086, 0x10fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6466          SILICOM_M1E10G2BPI9CX4_SSID /*PCI_ANY_ID */ , M1E10G2BPI9CX4,
6467          "MxE210G2BPI9CX4"},
6468         {0x8086, 0x10fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6469          SILICOM_M1E10G2BPI9SR_SSID /*PCI_ANY_ID */ , M1E10G2BPI9SR,
6470          "MxE210G2BPI9SR"},
6471         {0x8086, 0x10fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6472          SILICOM_M1E10G2BPI9LR_SSID /*PCI_ANY_ID */ , M1E10G2BPI9LR,
6473          "MxE210G2BPI9LR"},
6474         {0x8086, 0x10fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6475          SILICOM_M1E10G2BPI9T_SSID /*PCI_ANY_ID */ , M1E10G2BPI9T,
6476          "MxE210G2BPI9T"},
6477
6478         {0x8086, 0x10fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6479          SILICOM_M2E10G2BPI9CX4_SSID /*PCI_ANY_ID */ , M2E10G2BPI9CX4,
6480          "M2E10G2BPI9CX4"},
6481         {0x8086, 0x10fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6482          SILICOM_M2E10G2BPI9SR_SSID /*PCI_ANY_ID */ , M2E10G2BPI9SR,
6483          "M2E10G2BPI9SR"},
6484         {0x8086, 0x10fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6485          SILICOM_M2E10G2BPI9LR_SSID /*PCI_ANY_ID */ , M2E10G2BPI9LR,
6486          "M2E10G2BPI9LR"},
6487         {0x8086, 0x10fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6488          SILICOM_M2E10G2BPI9T_SSID /*PCI_ANY_ID */ , M2E10G2BPI9T,
6489          "M2E10G2BPI9T"},
6490
6491         {0x8086, 0x10fb, SILICOM_SVID, SILICOM_PE210G2BPI9CX4_SSID,
6492          PE210G2BPI9CX4, "PE210G2BPI9CX4"},
6493         {0x8086, 0x10fb, SILICOM_SVID, SILICOM_PE210G2BPI9SR_SSID,
6494          PE210G2BPI9SR, "PE210G2BPI9SR"},
6495         {0x8086, 0x10fb, SILICOM_SVID, SILICOM_PE210G2BPI9LR_SSID,
6496          PE210G2BPI9LR, "PE210G2BPI9LR"},
6497         {0x8086, 0x10fb, SILICOM_SVID, SILICOM_PE210G2BPI9T_SSID, PE210G2BPI9T,
6498          "PE210G2BPI9T"},
6499
6500 #if 0
6501         {0x1374, 0x2c, SILICOM_SVID, SILICOM_PXG4BPI_SSID, PXG4BPI,
6502          "PXG4BPI-SD"},
6503
6504         {0x1374, 0x2d, SILICOM_SVID, SILICOM_PXG4BPFI_SSID, PXG4BPFI,
6505          "PXG4BPFI-SD"},
6506
6507         {0x1374, 0x3f, SILICOM_SVID, SILICOM_PXG2TBI_SSID, PXG2TBI,
6508          "PXG2TBI-SD"},
6509
6510         {0x1374, 0x3d, SILICOM_SVID, SILICOM_PXG2BISC1_SSID, PXG2BISC1,
6511          "PXG2BISC1-SD"},
6512
6513         {0x1374, 0x40, SILICOM_SVID, SILICOM_PEG4BPFI_SSID, PEG4BPFI,
6514          "PEG4BPFI-SD"},
6515
6516 #ifdef BP_SELF_TEST
6517         {0x1374, 0x28, SILICOM_SVID, 0x28, PXGBPI, "PXG2BPI-SD"},
6518 #endif
6519 #endif
6520         {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6521          SILICOM_M6E2G8BPi80_SSID /*PCI_ANY_ID */ , M6E2G8BPi80, "MxE2G8BPi80"},
6522         {0x8086, 0x1528, SILICOM_SVID /*PCI_ANY_ID */ ,
6523          SILICOM_PE210G2BPi40_SSID /*PCI_ANY_ID */ , PE210G2BPi40,
6524          "PE210G2BPi40T"},
6525
6526         /* required last entry */
6527         {0,}
6528 };
6529
6530 static void find_fw(struct bpctl_dev *dev)
6531 {
6532         unsigned long mmio_start, mmio_len;
6533         struct pci_dev *pdev1 = dev->pdev;
6534
6535         if ((OLD_IF_SERIES(dev->subdevice)) ||
6536             (INTEL_IF_SERIES(dev->subdevice)))
6537                 dev->bp_fw_ver = 0xff;
6538         else
6539                 dev->bp_fw_ver = bypass_fw_ver(dev);
6540
6541         if (dev->bp_10gb == 1 && dev->bp_fw_ver == 0xff) {
6542                 int cnt = 100;
6543                 while (cnt--) {
6544                         iounmap((void *)dev->mem_map);
6545                         mmio_start = pci_resource_start(pdev1, 0);
6546                         mmio_len = pci_resource_len(pdev1, 0);
6547
6548                         dev->mem_map = (unsigned long)
6549                             ioremap(mmio_start, mmio_len);
6550
6551                         dev->bp_fw_ver = bypass_fw_ver(dev);
6552                         if (dev->bp_fw_ver == 0xa8)
6553                                 break;
6554                 }
6555         }
6556         /* dev->bp_fw_ver=0xa8; */
6557         printk("firmware version: 0x%x\n", dev->bp_fw_ver);
6558 }
6559
6560 static int init_one(struct bpctl_dev *dev, struct bpmod_info *info, struct pci_dev *pdev1)
6561 {
6562         unsigned long mmio_start, mmio_len;
6563
6564         dev->pdev = pdev1;
6565         mmio_start = pci_resource_start(pdev1, 0);
6566         mmio_len = pci_resource_len(pdev1, 0);
6567
6568         dev->desc = dev_desc[info->index].name;
6569         dev->name = info->bp_name;
6570         dev->device = info->device;
6571         dev->vendor = info->vendor;
6572         dev->subdevice = info->subdevice;
6573         dev->subvendor = info->subvendor;
6574         dev->func = PCI_FUNC(pdev1->devfn);
6575         dev->slot = PCI_SLOT(pdev1->devfn);
6576         dev->bus = pdev1->bus->number;
6577         dev->mem_map = (unsigned long)ioremap(mmio_start, mmio_len);
6578 #ifdef BP_SYNC_FLAG
6579         spin_lock_init(&dev->bypass_wr_lock);
6580 #endif
6581         if (BP10G9_IF_SERIES(dev->subdevice))
6582                 dev->bp_10g9 = 1;
6583         if (BP10G_IF_SERIES(dev->subdevice))
6584                 dev->bp_10g = 1;
6585         if (PEG540_IF_SERIES(dev->subdevice))
6586                 dev->bp_540 = 1;
6587         if (PEGF5_IF_SERIES(dev->subdevice))
6588                 dev->bp_fiber5 = 1;
6589         if (PEG80_IF_SERIES(dev->subdevice))
6590                 dev->bp_i80 = 1;
6591         if (PEGF80_IF_SERIES(dev->subdevice))
6592                 dev->bp_i80 = 1;
6593         if ((dev->subdevice & 0xa00) == 0xa00)
6594                 dev->bp_i80 = 1;
6595         if (BP10GB_IF_SERIES(dev->subdevice)) {
6596                 if (dev->ifindex == 0) {
6597                         unregister_chrdev(major_num, DEVICE_NAME);
6598                         printk("Please load network driver for %s adapter!\n",
6599                              dev->name);
6600                         return -1;
6601                 }
6602
6603                 if (dev->ndev && !(dev->ndev->flags & IFF_UP)) {
6604                         unregister_chrdev(major_num, DEVICE_NAME);
6605                         printk("Please bring up network interfaces for %s adapter!\n",
6606                              dev->name);
6607                         return -1;
6608                 }
6609                 dev->bp_10gb = 1;
6610         }
6611
6612         if (!dev->bp_10g9) {
6613                 if (is_bypass_fn(dev)) {
6614                         printk(KERN_INFO "%s found, ",
6615                                dev->name);
6616                         find_fw(dev);
6617                 }
6618                 dev->wdt_status = WDT_STATUS_UNKNOWN;
6619                 dev->reset_time = 0;
6620                 atomic_set(&dev->wdt_busy, 0);
6621                 dev->bp_status_un = 1;
6622
6623                 bypass_caps_init(dev);
6624
6625                 init_bypass_wd_auto(dev);
6626                 init_bypass_tpl_auto(dev);
6627                 if (NOKIA_SERIES(dev->subdevice))
6628                         reset_cont(dev);
6629         }
6630 #ifdef BP_SELF_TEST
6631         dev->bp_tx_data = kzalloc(BPTEST_DATA_LEN, GFP_KERNEL);
6632         if (dev->bp_tx_data) {
6633                 memset(dev->bp_tx_data, 0xff, 6);
6634                 memset(dev->bp_tx_data + 6, 0x0, 1);
6635                 memset(dev->bp_tx_data + 7, 0xaa, 5);
6636                 *(__be16 *)(dev->bp_tx_data + 12) = htons(ETH_P_BPTEST);
6637         } else
6638                 printk("bp_ctl: Memory allocation error!\n");
6639 #endif
6640         return 0;
6641 }
6642
6643 /*
6644 * Initialize the module - Register the character device
6645 */
6646
6647 static int __init bypass_init_module(void)
6648 {
6649         int ret_val, idx, idx_dev = 0;
6650         struct pci_dev *pdev1 = NULL;
6651         struct bpctl_dev *dev;
6652
6653         printk(BP_MOD_DESCR " v" BP_MOD_VER "\n");
6654         ret_val = register_chrdev(major_num, DEVICE_NAME, &Fops);
6655         if (ret_val < 0) {
6656                 printk("%s failed with %d\n", DEVICE_NAME, ret_val);
6657                 return ret_val;
6658         }
6659         major_num = ret_val;    /* dynamic */
6660         for (idx = 0; tx_ctl_pci_tbl[idx].vendor; idx++) {
6661                 while ((pdev1 = pci_get_subsys(tx_ctl_pci_tbl[idx].vendor,
6662                                                tx_ctl_pci_tbl[idx].device,
6663                                                tx_ctl_pci_tbl[idx].subvendor,
6664                                                tx_ctl_pci_tbl[idx].subdevice,
6665                                                pdev1))) {
6666
6667                         device_num++;
6668                 }
6669         }
6670         if (!device_num) {
6671                 printk("No such device\n");
6672                 unregister_chrdev(major_num, DEVICE_NAME);
6673                 return -1;
6674         }
6675
6676         bpctl_dev_arr = kmalloc((device_num) * sizeof(struct bpctl_dev), GFP_KERNEL);
6677
6678         if (!bpctl_dev_arr) {
6679                 printk("Allocation error\n");
6680                 unregister_chrdev(major_num, DEVICE_NAME);
6681                 return -1;
6682         }
6683         memset(bpctl_dev_arr, 0, ((device_num) * sizeof(struct bpctl_dev)));
6684
6685         pdev1 = NULL;
6686         dev = bpctl_dev_arr;
6687         for (idx = 0; tx_ctl_pci_tbl[idx].vendor; idx++) {
6688                 while ((pdev1 = pci_get_subsys(tx_ctl_pci_tbl[idx].vendor,
6689                                                tx_ctl_pci_tbl[idx].device,
6690                                                tx_ctl_pci_tbl[idx].subvendor,
6691                                                tx_ctl_pci_tbl[idx].subdevice,
6692                                                pdev1))) {
6693                         if (init_one(dev, &tx_ctl_pci_tbl[idx], pdev1) < 0)
6694                                 return -1;
6695                         dev++;
6696                 }
6697         }
6698         if_scan_init();
6699
6700         sema_init(&bpctl_sema, 1);
6701         spin_lock_init(&bpvm_lock);
6702         {
6703
6704                 struct bpctl_dev *pbpctl_dev_c = NULL;
6705                 for (idx_dev = 0, dev = bpctl_dev_arr;
6706                      idx_dev < device_num && dev->pdev;
6707                      idx_dev++, dev++) {
6708                         if (dev->bp_10g9) {
6709                                 pbpctl_dev_c = get_status_port_fn(dev);
6710                                 if (is_bypass_fn(dev)) {
6711                                         printk(KERN_INFO "%s found, ",
6712                                                dev->name);
6713                                         dev->bp_fw_ver = bypass_fw_ver(dev);
6714                                         printk("firmware version: 0x%x\n",
6715                                                dev->bp_fw_ver);
6716                                 }
6717                                 dev->wdt_status = WDT_STATUS_UNKNOWN;
6718                                 dev->reset_time = 0;
6719                                 atomic_set(&dev->wdt_busy, 0);
6720                                 dev->bp_status_un = 1;
6721
6722                                 bypass_caps_init(dev);
6723
6724                                 init_bypass_wd_auto(dev);
6725                                 init_bypass_tpl_auto(dev);
6726
6727                         }
6728
6729                 }
6730         }
6731
6732         register_netdevice_notifier(&bp_notifier_block);
6733 #ifdef BP_PROC_SUPPORT
6734         {
6735                 int i = 0;
6736                 /* unsigned long flags; */
6737                 /* rcu_read_lock(); */
6738                 bp_proc_create();
6739                 for (i = 0; i < device_num; i++) {
6740                         if (bpctl_dev_arr[i].ifindex) {
6741                                 /* spin_lock_irqsave(&bpvm_lock, flags); */
6742                                 bypass_proc_remove_dev_sd(&bpctl_dev_arr[i]);
6743                                 bypass_proc_create_dev_sd(&bpctl_dev_arr[i]);
6744                                 /* spin_unlock_irqrestore(&bpvm_lock, flags); */
6745                         }
6746
6747                 }
6748                 /* rcu_read_unlock(); */
6749         }
6750 #endif
6751
6752         return 0;
6753 }
6754
6755 /*
6756 * Cleanup - unregister the appropriate file from /proc
6757 */
6758 static void __exit bypass_cleanup_module(void)
6759 {
6760         int i;
6761         unregister_netdevice_notifier(&bp_notifier_block);
6762
6763         for (i = 0; i < device_num; i++) {
6764                 /* unsigned long flags; */
6765 #ifdef BP_PROC_SUPPORT
6766 /*      spin_lock_irqsave(&bpvm_lock, flags);
6767         rcu_read_lock(); */
6768                 bypass_proc_remove_dev_sd(&bpctl_dev_arr[i]);
6769 /*      spin_unlock_irqrestore(&bpvm_lock, flags);
6770         rcu_read_unlock(); */
6771 #endif
6772                 remove_bypass_wd_auto(&bpctl_dev_arr[i]);
6773                 bpctl_dev_arr[i].reset_time = 0;
6774
6775                 remove_bypass_tpl_auto(&bpctl_dev_arr[i]);
6776         }
6777
6778         /* unmap all devices */
6779         for (i = 0; i < device_num; i++) {
6780 #ifdef BP_SELF_TEST
6781                 kfree(bpctl_dev_arr[i].bp_tx_data);
6782 #endif
6783                 iounmap((void *)(bpctl_dev_arr[i].mem_map));
6784         }
6785
6786         /* free all devices space */
6787         kfree(bpctl_dev_arr);
6788
6789 /*
6790 * Unregister the device
6791 */
6792         unregister_chrdev(major_num, DEVICE_NAME);
6793 }
6794
6795 module_init(bypass_init_module);
6796 module_exit(bypass_cleanup_module);
6797
6798 int is_bypass_sd(int ifindex)
6799 {
6800         return is_bypass(get_dev_idx_p(ifindex));
6801 }
6802 EXPORT_SYMBOL(is_bypass_sd);
6803
6804 int set_bypass_sd(int ifindex, int bypass_mode)
6805 {
6806
6807         return set_bypass_fn(get_dev_idx_p(ifindex), bypass_mode);
6808 }
6809 EXPORT_SYMBOL(set_bypass_sd);
6810
6811 int get_bypass_sd(int ifindex)
6812 {
6813
6814         return get_bypass_fn(get_dev_idx_p(ifindex));
6815 }
6816 EXPORT_SYMBOL(get_bypass_sd);
6817
6818 int get_bypass_change_sd(int ifindex)
6819 {
6820
6821         return get_bypass_change_fn(get_dev_idx_p(ifindex));
6822 }
6823 EXPORT_SYMBOL(get_bypass_change_sd);
6824
6825 int set_dis_bypass_sd(int ifindex, int dis_param)
6826 {
6827         return set_dis_bypass_fn(get_dev_idx_p(ifindex), dis_param);
6828 }
6829 EXPORT_SYMBOL(set_dis_bypass_sd);
6830
6831 int get_dis_bypass_sd(int ifindex)
6832 {
6833
6834         return get_dis_bypass_fn(get_dev_idx_p(ifindex));
6835 }
6836 EXPORT_SYMBOL(get_dis_bypass_sd);
6837
6838 int set_bypass_pwoff_sd(int ifindex, int bypass_mode)
6839 {
6840         return set_bypass_pwoff_fn(get_dev_idx_p(ifindex), bypass_mode);
6841
6842 }
6843 EXPORT_SYMBOL(set_bypass_pwoff_sd);
6844
6845 int get_bypass_pwoff_sd(int ifindex)
6846 {
6847         return get_bypass_pwoff_fn(get_dev_idx_p(ifindex));
6848
6849 }
6850 EXPORT_SYMBOL(get_bypass_pwoff_sd);
6851
6852 int set_bypass_pwup_sd(int ifindex, int bypass_mode)
6853 {
6854         return set_bypass_pwup_fn(get_dev_idx_p(ifindex), bypass_mode);
6855
6856 }
6857 EXPORT_SYMBOL(set_bypass_pwup_sd);
6858
6859 int get_bypass_pwup_sd(int ifindex)
6860 {
6861         return get_bypass_pwup_fn(get_dev_idx_p(ifindex));
6862
6863 }
6864 EXPORT_SYMBOL(get_bypass_pwup_sd);
6865
6866 int set_bypass_wd_sd(int if_index, int ms_timeout, int *ms_timeout_set)
6867 {
6868         if ((is_bypass(get_dev_idx_p(if_index))) <= 0)
6869                 return BP_NOT_CAP;
6870         *ms_timeout_set = set_bypass_wd_fn(get_dev_idx_p(if_index), ms_timeout);
6871         return 0;
6872 }
6873 EXPORT_SYMBOL(set_bypass_wd_sd);
6874
6875 int get_bypass_wd_sd(int ifindex, int *timeout)
6876 {
6877         return get_bypass_wd_fn(get_dev_idx_p(ifindex), timeout);
6878
6879 }
6880 EXPORT_SYMBOL(get_bypass_wd_sd);
6881
6882 int get_wd_expire_time_sd(int ifindex, int *time_left)
6883 {
6884         return get_wd_expire_time_fn(get_dev_idx_p(ifindex), time_left);
6885 }
6886 EXPORT_SYMBOL(get_wd_expire_time_sd);
6887
6888 int reset_bypass_wd_timer_sd(int ifindex)
6889 {
6890         return reset_bypass_wd_timer_fn(get_dev_idx_p(ifindex));
6891
6892 }
6893 EXPORT_SYMBOL(reset_bypass_wd_timer_sd);
6894
6895 int get_wd_set_caps_sd(int ifindex)
6896 {
6897         return get_wd_set_caps_fn(get_dev_idx_p(ifindex));
6898
6899 }
6900 EXPORT_SYMBOL(get_wd_set_caps_sd);
6901
6902 int set_std_nic_sd(int ifindex, int nic_mode)
6903 {
6904         return set_std_nic_fn(get_dev_idx_p(ifindex), nic_mode);
6905
6906 }
6907 EXPORT_SYMBOL(set_std_nic_sd);
6908
6909 int get_std_nic_sd(int ifindex)
6910 {
6911         return get_std_nic_fn(get_dev_idx_p(ifindex));
6912
6913 }
6914 EXPORT_SYMBOL(get_std_nic_sd);
6915
6916 int set_tap_sd(int ifindex, int tap_mode)
6917 {
6918         return set_tap_fn(get_dev_idx_p(ifindex), tap_mode);
6919
6920 }
6921 EXPORT_SYMBOL(set_tap_sd);
6922
6923 int get_tap_sd(int ifindex)
6924 {
6925         return get_tap_fn(get_dev_idx_p(ifindex));
6926
6927 }
6928 EXPORT_SYMBOL(get_tap_sd);
6929
6930 int set_tap_pwup_sd(int ifindex, int tap_mode)
6931 {
6932         return set_tap_pwup_fn(get_dev_idx_p(ifindex), tap_mode);
6933
6934 }
6935 EXPORT_SYMBOL(set_tap_pwup_sd);
6936
6937 int get_tap_pwup_sd(int ifindex)
6938 {
6939         return get_tap_pwup_fn(get_dev_idx_p(ifindex));
6940
6941 }
6942 EXPORT_SYMBOL(get_tap_pwup_sd);
6943
6944 int get_tap_change_sd(int ifindex)
6945 {
6946         return get_tap_change_fn(get_dev_idx_p(ifindex));
6947
6948 }
6949 EXPORT_SYMBOL(get_tap_change_sd);
6950
6951 int set_dis_tap_sd(int ifindex, int dis_param)
6952 {
6953         return set_dis_tap_fn(get_dev_idx_p(ifindex), dis_param);
6954
6955 }
6956 EXPORT_SYMBOL(set_dis_tap_sd);
6957
6958 int get_dis_tap_sd(int ifindex)
6959 {
6960         return get_dis_tap_fn(get_dev_idx_p(ifindex));
6961
6962 }
6963 EXPORT_SYMBOL(get_dis_tap_sd);
6964
6965 int set_bp_disc_sd(int ifindex, int disc_mode)
6966 {
6967         return set_disc_fn(get_dev_idx_p(ifindex), disc_mode);
6968
6969 }
6970 EXPORT_SYMBOL(set_bp_disc_sd);
6971
6972 int get_bp_disc_sd(int ifindex)
6973 {
6974         return get_disc_fn(get_dev_idx_p(ifindex));
6975
6976 }
6977 EXPORT_SYMBOL(get_bp_disc_sd);
6978
6979 int set_bp_disc_pwup_sd(int ifindex, int disc_mode)
6980 {
6981         return set_disc_pwup_fn(get_dev_idx_p(ifindex), disc_mode);
6982
6983 }
6984 EXPORT_SYMBOL(set_bp_disc_pwup_sd);
6985
6986 int get_bp_disc_pwup_sd(int ifindex)
6987 {
6988         return get_disc_pwup_fn(get_dev_idx_p(ifindex));
6989
6990 }
6991 EXPORT_SYMBOL(get_bp_disc_pwup_sd);
6992
6993 int get_bp_disc_change_sd(int ifindex)
6994 {
6995         return get_disc_change_fn(get_dev_idx_p(ifindex));
6996
6997 }
6998 EXPORT_SYMBOL(get_bp_disc_change_sd);
6999
7000 int set_bp_dis_disc_sd(int ifindex, int dis_param)
7001 {
7002         return set_dis_disc_fn(get_dev_idx_p(ifindex), dis_param);
7003
7004 }
7005 EXPORT_SYMBOL(set_bp_dis_disc_sd);
7006
7007 int get_bp_dis_disc_sd(int ifindex)
7008 {
7009         return get_dis_disc_fn(get_dev_idx_p(ifindex));
7010
7011 }
7012 EXPORT_SYMBOL(get_bp_dis_disc_sd);
7013
7014 int get_wd_exp_mode_sd(int ifindex)
7015 {
7016         return get_wd_exp_mode_fn(get_dev_idx_p(ifindex));
7017 }
7018 EXPORT_SYMBOL(get_wd_exp_mode_sd);
7019
7020 int set_wd_exp_mode_sd(int ifindex, int param)
7021 {
7022         return set_wd_exp_mode_fn(get_dev_idx_p(ifindex), param);
7023
7024 }
7025 EXPORT_SYMBOL(set_wd_exp_mode_sd);
7026
7027 int reset_cont_sd(int ifindex)
7028 {
7029         return reset_cont_fn(get_dev_idx_p(ifindex));
7030
7031 }
7032
7033 int set_tx_sd(int ifindex, int tx_state)
7034 {
7035         return set_tx_fn(get_dev_idx_p(ifindex), tx_state);
7036
7037 }
7038 EXPORT_SYMBOL(set_tx_sd);
7039
7040 int set_tpl_sd(int ifindex, int tpl_state)
7041 {
7042         return set_tpl_fn(get_dev_idx_p(ifindex), tpl_state);
7043
7044 }
7045 EXPORT_SYMBOL(set_tpl_sd);
7046
7047 int set_bp_hw_reset_sd(int ifindex, int status)
7048 {
7049         return set_bp_hw_reset_fn(get_dev_idx_p(ifindex), status);
7050
7051 }
7052 EXPORT_SYMBOL(set_bp_hw_reset_sd);
7053
7054 int set_wd_autoreset_sd(int ifindex, int param)
7055 {
7056         return set_wd_autoreset_fn(get_dev_idx_p(ifindex), param);
7057
7058 }
7059 EXPORT_SYMBOL(set_wd_autoreset_sd);
7060
7061 int get_wd_autoreset_sd(int ifindex)
7062 {
7063         return get_wd_autoreset_fn(get_dev_idx_p(ifindex));
7064
7065 }
7066 EXPORT_SYMBOL(get_wd_autoreset_sd);
7067
7068 int get_bypass_caps_sd(int ifindex)
7069 {
7070         return get_bypass_caps_fn(get_dev_idx_p(ifindex));
7071 }
7072 EXPORT_SYMBOL(get_bypass_caps_sd);
7073
7074 int get_bypass_slave_sd(int ifindex)
7075 {
7076         struct bpctl_dev *pbpctl_dev_out;
7077         int ret = get_bypass_slave_fn(get_dev_idx_p(ifindex), &pbpctl_dev_out);
7078         if (ret == 1)
7079                 return pbpctl_dev_out->ifindex;
7080         return -1;
7081
7082 }
7083 EXPORT_SYMBOL(get_bypass_slave_sd);
7084
7085 int get_tx_sd(int ifindex)
7086 {
7087         return get_tx_fn(get_dev_idx_p(ifindex));
7088
7089 }
7090 EXPORT_SYMBOL(get_tx_sd);
7091
7092 int get_tpl_sd(int ifindex)
7093 {
7094         return get_tpl_fn(get_dev_idx_p(ifindex));
7095
7096 }
7097 EXPORT_SYMBOL(get_tpl_sd);
7098
7099 int get_bp_hw_reset_sd(int ifindex)
7100 {
7101         return get_bp_hw_reset_fn(get_dev_idx_p(ifindex));
7102
7103 }
7104 EXPORT_SYMBOL(get_bp_hw_reset_sd);
7105
7106 int get_bypass_info_sd(int ifindex, struct bp_info *bp_info)
7107 {
7108         return get_bypass_info_fn(get_dev_idx_p(ifindex), bp_info->prod_name, &bp_info->fw_ver);
7109 }
7110 EXPORT_SYMBOL(get_bypass_info_sd);
7111
7112 int bp_if_scan_sd(void)
7113 {
7114         if_scan_init();
7115         return 0;
7116 }
7117 EXPORT_SYMBOL(bp_if_scan_sd);
7118
7119 #define BP_PROC_DIR "bypass"
7120
7121 static struct proc_dir_entry *bp_procfs_dir;
7122
7123 int bp_proc_create(void)
7124 {
7125         bp_procfs_dir = proc_mkdir(BP_PROC_DIR, init_net.proc_net);
7126         if (bp_procfs_dir == (struct proc_dir_entry *)0) {
7127                 printk(KERN_DEBUG
7128                        "Could not create procfs nicinfo directory %s\n",
7129                        BP_PROC_DIR);
7130                 return -1;
7131         }
7132         return 0;
7133 }
7134
7135 static int procfs_add(char *proc_name, const struct file_operations *fops,
7136                       struct bpctl_dev *dev)
7137 {
7138         struct bypass_pfs_sd *pfs = &dev->bypass_pfs_set;
7139         if (!proc_create_data(proc_name, 0644, pfs->bypass_entry, fops, dev))
7140                 return -1;
7141         return 0;
7142 }
7143
7144 #define RO_FOPS(name)   \
7145 static int name##_open(struct inode *inode, struct file *file)  \
7146 {                                                               \
7147         return single_open(file, show_##name, PDE_DATA(inode));\
7148 }                                                               \
7149 static const struct file_operations name##_ops = {              \
7150         .open = name##_open,                                    \
7151         .read = seq_read,                                       \
7152         .llseek = seq_lseek,                                    \
7153         .release = single_release,                              \
7154 };
7155
7156 #define RW_FOPS(name)   \
7157 static int name##_open(struct inode *inode, struct file *file)  \
7158 {                                                               \
7159         return single_open(file, show_##name, PDE_DATA(inode));\
7160 }                                                               \
7161 static const struct file_operations name##_ops = {              \
7162         .open = name##_open,                                    \
7163         .read = seq_read,                                       \
7164         .write = name##_write,                                  \
7165         .llseek = seq_lseek,                                    \
7166         .release = single_release,                              \
7167 };
7168
7169 static int show_bypass_info(struct seq_file *m, void *v)
7170 {
7171         struct bpctl_dev *dev = m->private;
7172
7173         seq_printf(m, "Name\t\t\t%s\n", dev->name);
7174         seq_printf(m, "Firmware version\t0x%x\n", dev->bp_fw_ver);
7175         return 0;
7176 }
7177 RO_FOPS(bypass_info)
7178
7179 static int show_bypass_slave(struct seq_file *m, void *v)
7180 {
7181         struct bpctl_dev *dev = m->private;
7182         struct bpctl_dev *slave = get_status_port_fn(dev);
7183         if (!slave)
7184                 slave = dev;
7185         if (!slave)
7186                 seq_puts(m, "fail\n");
7187         else if (slave->ndev)
7188                 seq_printf(m, "%s\n", slave->ndev->name);
7189         return 0;
7190 }
7191 RO_FOPS(bypass_slave)
7192
7193 static int show_bypass_caps(struct seq_file *m, void *v)
7194 {
7195         struct bpctl_dev *dev = m->private;
7196         int ret = get_bypass_caps_fn(dev);
7197         if (ret == BP_NOT_CAP)
7198                 seq_puts(m, "-1\n");
7199         else
7200                 seq_printf(m, "0x%x\n", ret);
7201         return 0;
7202 }
7203 RO_FOPS(bypass_caps)
7204
7205 static int show_wd_set_caps(struct seq_file *m, void *v)
7206 {
7207         struct bpctl_dev *dev = m->private;
7208         int ret = get_wd_set_caps_fn(dev);
7209         if (ret == BP_NOT_CAP)
7210                 seq_puts(m, "-1\n");
7211         else
7212                 seq_printf(m, "0x%x\n", ret);
7213         return 0;
7214 }
7215 RO_FOPS(wd_set_caps)
7216
7217 static int user_on_off(const void __user *buffer, size_t count)
7218 {
7219
7220         char kbuf[256];
7221         int length = 0;
7222
7223         if (count > (sizeof(kbuf) - 1))
7224                 return -1;
7225
7226         if (copy_from_user(&kbuf, buffer, count))
7227                 return -1;
7228
7229         kbuf[count] = '\0';
7230         length = strlen(kbuf);
7231         if (kbuf[length - 1] == '\n')
7232                 kbuf[--length] = '\0';
7233
7234         if (strcmp(kbuf, "on") == 0)
7235                 return 1;
7236         if (strcmp(kbuf, "off") == 0)
7237                 return 0;
7238         return 0;
7239 }
7240
7241 static ssize_t bypass_write(struct file *file, const char __user *buffer,
7242                                   size_t count, loff_t *pos)
7243 {
7244         int bypass_param = user_on_off(buffer, count);
7245         if (bypass_param < 0)
7246                 return -1;
7247
7248         set_bypass_fn(PDE_DATA(file_inode(file)), bypass_param);
7249         return count;
7250 }
7251 static int show_bypass(struct seq_file *m, void *v)
7252 {
7253         struct bpctl_dev *dev = m->private;
7254         int ret = get_bypass_fn(dev);
7255         if (ret == BP_NOT_CAP)
7256                 seq_puts(m, "fail\n");
7257         else if (ret == 1)
7258                 seq_puts(m, "on\n");
7259         else if (ret == 0)
7260                 seq_puts(m, "off\n");
7261         return 0;
7262 }
7263 RW_FOPS(bypass)
7264
7265 static ssize_t tap_write(struct file *file, const char __user *buffer,
7266                                   size_t count, loff_t *pos)
7267 {
7268         int tap_param = user_on_off(buffer, count);
7269         if (tap_param < 0)
7270                 return -1;
7271
7272         set_tap_fn(PDE_DATA(file_inode(file)), tap_param);
7273         return count;
7274 }
7275 static int show_tap(struct seq_file *m, void *v)
7276 {
7277         struct bpctl_dev *dev = m->private;
7278         int ret = get_tap_fn(dev);
7279         if (ret == BP_NOT_CAP)
7280                 seq_puts(m, "fail\n");
7281         else if (ret == 1)
7282                 seq_puts(m, "on\n");
7283         else if (ret == 0)
7284                 seq_puts(m, "off\n");
7285         return 0;
7286 }
7287 RW_FOPS(tap)
7288
7289 static ssize_t disc_write(struct file *file, const char __user *buffer,
7290                                   size_t count, loff_t *pos)
7291 {
7292         int tap_param = user_on_off(buffer, count);
7293         if (tap_param < 0)
7294                 return -1;
7295
7296         set_disc_fn(PDE_DATA(file_inode(file)), tap_param);
7297         return count;
7298 }
7299 static int show_disc(struct seq_file *m, void *v)
7300 {
7301         struct bpctl_dev *dev = m->private;
7302         int ret = get_disc_fn(dev);
7303         if (ret == BP_NOT_CAP)
7304                 seq_puts(m, "fail\n");
7305         else if (ret == 1)
7306                 seq_puts(m, "on\n");
7307         else if (ret == 0)
7308                 seq_puts(m, "off\n");
7309         return 0;
7310 }
7311 RW_FOPS(disc)
7312
7313 static int show_bypass_change(struct seq_file *m, void *v)
7314 {
7315         struct bpctl_dev *dev = m->private;
7316         int ret = get_bypass_change_fn(dev);
7317         if (ret == 1)
7318                 seq_puts(m, "on\n");
7319         else if (ret == 0)
7320                 seq_puts(m, "off\n");
7321         else
7322                 seq_puts(m, "fail\n");
7323         return 0;
7324 }
7325 RO_FOPS(bypass_change)
7326
7327 static int show_tap_change(struct seq_file *m, void *v)
7328 {
7329         struct bpctl_dev *dev = m->private;
7330         int ret = get_tap_change_fn(dev);
7331         if (ret == 1)
7332                 seq_puts(m, "on\n");
7333         else if (ret == 0)
7334                 seq_puts(m, "off\n");
7335         else
7336                 seq_puts(m, "fail\n");
7337         return 0;
7338 }
7339 RO_FOPS(tap_change)
7340
7341 static int show_disc_change(struct seq_file *m, void *v)
7342 {
7343         struct bpctl_dev *dev = m->private;
7344         int ret = get_disc_change_fn(dev);
7345         if (ret == 1)
7346                 seq_puts(m, "on\n");
7347         else if (ret == 0)
7348                 seq_puts(m, "off\n");
7349         else
7350                 seq_puts(m, "fail\n");
7351         return 0;
7352 }
7353 RO_FOPS(disc_change)
7354
7355 static ssize_t bypass_wd_write(struct file *file, const char __user *buffer,
7356                                   size_t count, loff_t *pos)
7357 {
7358         struct bpctl_dev *dev = PDE_DATA(file_inode(file));
7359         int timeout;
7360         int ret = kstrtoint_from_user(buffer, count, 10, &timeout);
7361         if (ret)
7362                 return ret;
7363         set_bypass_wd_fn(dev, timeout);
7364         return count;
7365 }
7366 static int show_bypass_wd(struct seq_file *m, void *v)
7367 {
7368         struct bpctl_dev *dev = m->private;
7369         int ret = 0, timeout = 0;
7370
7371         ret = get_bypass_wd_fn(dev, &timeout);
7372         if (ret == BP_NOT_CAP)
7373                 seq_puts(m,  "fail\n");
7374         else if (timeout == -1)
7375                 seq_puts(m,  "unknown\n");
7376         else if (timeout == 0)
7377                 seq_puts(m,  "disable\n");
7378         else
7379                 seq_printf(m, "%d\n", timeout);
7380         return 0;
7381 }
7382 RW_FOPS(bypass_wd)
7383
7384 static int show_wd_expire_time(struct seq_file *m, void *v)
7385 {
7386         struct bpctl_dev *dev = m->private;
7387         int ret = 0, timeout = 0;
7388         ret = get_wd_expire_time_fn(dev, &timeout);
7389         if (ret == BP_NOT_CAP)
7390                 seq_puts(m, "fail\n");
7391         else if (timeout == -1)
7392                 seq_puts(m, "expire\n");
7393         else if (timeout == 0)
7394                 seq_puts(m, "disable\n");
7395         else
7396                 seq_printf(m, "%d\n", timeout);
7397         return 0;
7398 }
7399 RO_FOPS(wd_expire_time)
7400
7401 static ssize_t tpl_write(struct file *file, const char __user *buffer,
7402                                   size_t count, loff_t *pos)
7403 {
7404         struct bpctl_dev *dev = PDE_DATA(file_inode(file));
7405         int tpl_param = user_on_off(buffer, count);
7406         if (tpl_param < 0)
7407                 return -1;
7408
7409         set_tpl_fn(dev, tpl_param);
7410         return count;
7411 }
7412 static int show_tpl(struct seq_file *m, void *v)
7413 {
7414         struct bpctl_dev *dev = m->private;
7415         int ret = get_tpl_fn(dev);
7416         if (ret == BP_NOT_CAP)
7417                 seq_puts(m, "fail\n");
7418         else if (ret == 1)
7419                 seq_puts(m, "on\n");
7420         else if (ret == 0)
7421                 seq_puts(m, "off\n");
7422         return 0;
7423 }
7424 RW_FOPS(tpl)
7425
7426 #ifdef PMC_FIX_FLAG
7427 static ssize_t wait_at_pwup_write(struct file *file, const char __user *buffer,
7428                                   size_t count, loff_t *pos)
7429 {
7430         struct bpctl_dev *dev = PDE_DATA(file_inode(file));
7431         int tpl_param = user_on_off(buffer, count);
7432         if (tpl_param < 0)
7433                 return -1;
7434
7435         set_bp_wait_at_pwup_fn(dev, tpl_param);
7436         return count;
7437 }
7438 static int show_wait_at_pwup(struct seq_file *m, void *v)
7439 {
7440         struct bpctl_dev *dev = m->private;
7441         int ret = get_bp_wait_at_pwup_fn(dev);
7442         if (ret == BP_NOT_CAP)
7443                 seq_puts(m, "fail\n");
7444         else if (ret == 1)
7445                 seq_puts(m, "on\n");
7446         else if (ret == 0)
7447                 seq_puts(m, "off\n");
7448         return 0;
7449 }
7450 RW_FOPS(wait_at_pwup)
7451
7452 static ssize_t hw_reset_write(struct file *file, const char __user *buffer,
7453                                   size_t count, loff_t *pos)
7454 {
7455         struct bpctl_dev *dev = PDE_DATA(file_inode(file));
7456         int tpl_param = user_on_off(buffer, count);
7457         if (tpl_param < 0)
7458                 return -1;
7459
7460         set_bp_hw_reset_fn(dev, tpl_param);
7461         return count;
7462 }
7463 static int show_hw_reset(struct seq_file *m, void *v)
7464 {
7465         struct bpctl_dev *dev = m->private;
7466         int ret = get_bp_hw_reset_fn(dev);
7467         if (ret == BP_NOT_CAP)
7468                 seq_puts(m, "fail\n");
7469         else if (ret == 1)
7470                 seq_puts(m, "on\n");
7471         else if (ret == 0)
7472                 seq_puts(m, "off\n");
7473         return 0;
7474 }
7475 RW_FOPS(hw_reset)
7476
7477 #endif                          /*PMC_WAIT_FLAG */
7478
7479 static int show_reset_bypass_wd(struct seq_file *m, void *v)
7480 {
7481         struct bpctl_dev *dev = m->private;
7482         int ret = reset_bypass_wd_timer_fn(dev);
7483         if (ret == BP_NOT_CAP)
7484                 seq_puts(m, "fail\n");
7485         else if (ret == 0)
7486                 seq_puts(m, "disable\n");
7487         else if (ret == 1)
7488                 seq_puts(m, "success\n");
7489         return 0;
7490 }
7491 RO_FOPS(reset_bypass_wd)
7492
7493 static ssize_t dis_bypass_write(struct file *file, const char __user *buffer,
7494                                   size_t count, loff_t *pos)
7495 {
7496         int bypass_param = user_on_off(buffer, count);
7497         if (bypass_param < 0)
7498                 return -EINVAL;
7499
7500         set_dis_bypass_fn(PDE_DATA(file_inode(file)), bypass_param);
7501         return count;
7502 }
7503 static int show_dis_bypass(struct seq_file *m, void *v)
7504 {
7505         struct bpctl_dev *dev = m->private;
7506         int ret = get_dis_bypass_fn(dev);
7507         if (ret == BP_NOT_CAP)
7508                 seq_puts(m, "fail\n");
7509         else if (ret == 0)
7510                 seq_puts(m, "off\n");
7511         else
7512                 seq_puts(m, "on\n");
7513         return 0;
7514 }
7515 RW_FOPS(dis_bypass)
7516
7517 static ssize_t dis_tap_write(struct file *file, const char __user *buffer,
7518                                   size_t count, loff_t *pos)
7519 {
7520         int tap_param = user_on_off(buffer, count);
7521         if (tap_param < 0)
7522                 return -EINVAL;
7523
7524         set_dis_tap_fn(PDE_DATA(file_inode(file)), tap_param);
7525         return count;
7526 }
7527 static int show_dis_tap(struct seq_file *m, void *v)
7528 {
7529         struct bpctl_dev *dev = m->private;
7530         int ret = get_dis_tap_fn(dev);
7531         if (ret == BP_NOT_CAP)
7532                 seq_puts(m, "fail\n");
7533         else if (ret == 0)
7534                 seq_puts(m, "off\n");
7535         else
7536                 seq_puts(m, "on\n");
7537         return 0;
7538 }
7539 RW_FOPS(dis_tap)
7540
7541 static ssize_t dis_disc_write(struct file *file, const char __user *buffer,
7542                                   size_t count, loff_t *pos)
7543 {
7544         int tap_param = user_on_off(buffer, count);
7545         if (tap_param < 0)
7546                 return -EINVAL;
7547
7548         set_dis_disc_fn(PDE_DATA(file_inode(file)), tap_param);
7549         return count;
7550 }
7551 static int show_dis_disc(struct seq_file *m, void *v)
7552 {
7553         struct bpctl_dev *dev = m->private;
7554         int ret = get_dis_disc_fn(dev);
7555         if (ret == BP_NOT_CAP)
7556                 seq_puts(m, "fail\n");
7557         else if (ret == 0)
7558                 seq_puts(m, "off\n");
7559         else
7560                 seq_puts(m, "on\n");
7561         return 0;
7562 }
7563 RW_FOPS(dis_disc)
7564
7565 static ssize_t bypass_pwup_write(struct file *file, const char __user *buffer,
7566                                   size_t count, loff_t *pos)
7567 {
7568         int bypass_param = user_on_off(buffer, count);
7569         if (bypass_param < 0)
7570                 return -EINVAL;
7571
7572         set_bypass_pwup_fn(PDE_DATA(file_inode(file)), bypass_param);
7573         return count;
7574 }
7575 static int show_bypass_pwup(struct seq_file *m, void *v)
7576 {
7577         struct bpctl_dev *dev = m->private;
7578         int ret = get_bypass_pwup_fn(dev);
7579         if (ret == BP_NOT_CAP)
7580                 seq_puts(m, "fail\n");
7581         else if (ret == 0)
7582                 seq_puts(m, "off\n");
7583         else
7584                 seq_puts(m, "on\n");
7585         return 0;
7586 }
7587 RW_FOPS(bypass_pwup)
7588
7589 static ssize_t bypass_pwoff_write(struct file *file, const char __user *buffer,
7590                                   size_t count, loff_t *pos)
7591 {
7592         int bypass_param = user_on_off(buffer, count);
7593         if (bypass_param < 0)
7594                 return -EINVAL;
7595
7596         set_bypass_pwoff_fn(PDE_DATA(file_inode(file)), bypass_param);
7597         return count;
7598 }
7599 static int show_bypass_pwoff(struct seq_file *m, void *v)
7600 {
7601         struct bpctl_dev *dev = m->private;
7602         int ret = get_bypass_pwoff_fn(dev);
7603         if (ret == BP_NOT_CAP)
7604                 seq_puts(m, "fail\n");
7605         else if (ret == 0)
7606                 seq_puts(m, "off\n");
7607         else
7608                 seq_puts(m, "on\n");
7609         return 0;
7610 }
7611 RW_FOPS(bypass_pwoff)
7612
7613 static ssize_t tap_pwup_write(struct file *file, const char __user *buffer,
7614                                   size_t count, loff_t *pos)
7615 {
7616         int tap_param = user_on_off(buffer, count);
7617         if (tap_param < 0)
7618                 return -EINVAL;
7619
7620         set_tap_pwup_fn(PDE_DATA(file_inode(file)), tap_param);
7621         return count;
7622 }
7623 static int show_tap_pwup(struct seq_file *m, void *v)
7624 {
7625         struct bpctl_dev *dev = m->private;
7626         int ret = get_tap_pwup_fn(dev);
7627         if (ret == BP_NOT_CAP)
7628                 seq_puts(m, "fail\n");
7629         else if (ret == 0)
7630                 seq_puts(m, "off\n");
7631         else
7632                 seq_puts(m, "on\n");
7633         return 0;
7634 }
7635 RW_FOPS(tap_pwup)
7636
7637 static ssize_t disc_pwup_write(struct file *file, const char __user *buffer,
7638                                   size_t count, loff_t *pos)
7639 {
7640         int tap_param = user_on_off(buffer, count);
7641         if (tap_param < 0)
7642                 return -EINVAL;
7643
7644         set_disc_pwup_fn(PDE_DATA(file_inode(file)), tap_param);
7645         return count;
7646 }
7647 static int show_disc_pwup(struct seq_file *m, void *v)
7648 {
7649         struct bpctl_dev *dev = m->private;
7650         int ret = get_disc_pwup_fn(dev);
7651         if (ret == BP_NOT_CAP)
7652                 seq_puts(m, "fail\n");
7653         else if (ret == 0)
7654                 seq_puts(m, "off\n");
7655         else
7656                 seq_puts(m, "on\n");
7657         return 0;
7658 }
7659 RW_FOPS(disc_pwup)
7660
7661 static ssize_t std_nic_write(struct file *file, const char __user *buffer,
7662                                   size_t count, loff_t *pos)
7663 {
7664         int bypass_param = user_on_off(buffer, count);
7665         if (bypass_param < 0)
7666                 return -EINVAL;
7667
7668         set_std_nic_fn(PDE_DATA(file_inode(file)), bypass_param);
7669         return count;
7670 }
7671 static int show_std_nic(struct seq_file *m, void *v)
7672 {
7673         struct bpctl_dev *dev = m->private;
7674         int ret = get_std_nic_fn(dev);
7675         if (ret == BP_NOT_CAP)
7676                 seq_puts(m, "fail\n");
7677         else if (ret == 0)
7678                 seq_puts(m, "off\n");
7679         else
7680                 seq_puts(m, "on\n");
7681         return 0;
7682 }
7683 RW_FOPS(std_nic)
7684
7685 static ssize_t wd_exp_mode_write(struct file *file, const char __user *buffer,
7686                                   size_t count, loff_t *pos)
7687 {
7688         char kbuf[256];
7689         int bypass_param = 0, length = 0;
7690
7691         if (count > (sizeof(kbuf) - 1))
7692                 return -1;
7693
7694         if (copy_from_user(&kbuf, buffer, count))
7695                 return -1;
7696
7697         kbuf[count] = '\0';
7698         length = strlen(kbuf);
7699         if (kbuf[length - 1] == '\n')
7700                 kbuf[--length] = '\0';
7701
7702         if (strcmp(kbuf, "tap") == 0)
7703                 bypass_param = 1;
7704         else if (strcmp(kbuf, "bypass") == 0)
7705                 bypass_param = 0;
7706         else if (strcmp(kbuf, "disc") == 0)
7707                 bypass_param = 2;
7708
7709         set_wd_exp_mode_fn(PDE_DATA(file_inode(file)), bypass_param);
7710
7711         return count;
7712 }
7713 static int show_wd_exp_mode(struct seq_file *m, void *v)
7714 {
7715         struct bpctl_dev *dev = m->private;
7716         int ret = get_wd_exp_mode_fn(dev);
7717         if (ret == 1)
7718                 seq_puts(m, "tap\n");
7719         else if (ret == 0)
7720                 seq_puts(m, "bypass\n");
7721         else if (ret == 2)
7722                 seq_puts(m, "disc\n");
7723         else
7724                 seq_puts(m, "fail\n");
7725         return 0;
7726 }
7727 RW_FOPS(wd_exp_mode)
7728
7729 static ssize_t wd_autoreset_write(struct file *file, const char __user *buffer,
7730                                   size_t count, loff_t *pos)
7731 {
7732         int timeout;
7733         int ret = kstrtoint_from_user(buffer, count, 10, &timeout);
7734         if (ret)
7735                 return ret;
7736         set_wd_autoreset_fn(PDE_DATA(file_inode(file)), timeout);
7737         return count;
7738 }
7739 static int show_wd_autoreset(struct seq_file *m, void *v)
7740 {
7741         struct bpctl_dev *dev = m->private;
7742         int ret = get_wd_autoreset_fn(dev);
7743         if (ret >= 0)
7744                 seq_printf(m, "%d\n", ret);
7745         else
7746                 seq_puts(m, "fail\n");
7747         return 0;
7748 }
7749 RW_FOPS(wd_autoreset)
7750
7751 int bypass_proc_create_dev_sd(struct bpctl_dev *pbp_device_block)
7752 {
7753         struct bypass_pfs_sd *current_pfs = &(pbp_device_block->bypass_pfs_set);
7754         static struct proc_dir_entry *procfs_dir;
7755         int ret = 0;
7756
7757         if (!pbp_device_block->ndev)
7758                 return -1;
7759         sprintf(current_pfs->dir_name, "bypass_%s",
7760                 pbp_device_block->ndev->name);
7761
7762         if (!bp_procfs_dir)
7763                 return -1;
7764
7765         /* create device proc dir */
7766         procfs_dir = proc_mkdir(current_pfs->dir_name, bp_procfs_dir);
7767         if (!procfs_dir) {
7768                 printk(KERN_DEBUG "Could not create procfs directory %s\n",
7769                        current_pfs->dir_name);
7770                 return -1;
7771         }
7772         current_pfs->bypass_entry = procfs_dir;
7773
7774 #define ENTRY(x) (ret |= procfs_add(#x, &x##_ops, pbp_device_block))
7775
7776         ENTRY(bypass_info);
7777         if (pbp_device_block->bp_caps & SW_CTL_CAP) {
7778                 /* Create set param proc's */
7779                 ENTRY(bypass_slave);
7780                 ENTRY(bypass_caps);
7781                 ENTRY(wd_set_caps);
7782                 ENTRY(bypass_wd);
7783                 ENTRY(wd_expire_time);
7784                 ENTRY(reset_bypass_wd);
7785                 ENTRY(std_nic);
7786                 if (pbp_device_block->bp_caps & BP_CAP) {
7787                         ENTRY(bypass);
7788                         ENTRY(dis_bypass);
7789                         ENTRY(bypass_pwup);
7790                         ENTRY(bypass_pwoff);
7791                         ENTRY(bypass_change);
7792                 }
7793                 if (pbp_device_block->bp_caps & TAP_CAP) {
7794                         ENTRY(tap);
7795                         ENTRY(dis_tap);
7796                         ENTRY(tap_pwup);
7797                         ENTRY(tap_change);
7798                 }
7799                 if (pbp_device_block->bp_caps & DISC_CAP) {
7800                         ENTRY(disc);
7801                         ENTRY(dis_disc);
7802                         ENTRY(disc_pwup);
7803                         ENTRY(disc_change);
7804                 }
7805
7806                 ENTRY(wd_exp_mode);
7807                 ENTRY(wd_autoreset);
7808                 ENTRY(tpl);
7809 #ifdef PMC_FIX_FLAG
7810                 ENTRY(wait_at_pwup);
7811                 ENTRY(hw_reset);
7812 #endif
7813         }
7814 #undef ENTRY
7815         if (ret < 0)
7816                 printk(KERN_DEBUG "Create proc entry failed\n");
7817
7818         return ret;
7819 }
7820
7821 int bypass_proc_remove_dev_sd(struct bpctl_dev *pbp_device_block)
7822 {
7823
7824         struct bypass_pfs_sd *current_pfs = &pbp_device_block->bypass_pfs_set;
7825         remove_proc_subtree(current_pfs->dir_name, bp_procfs_dir);
7826         current_pfs->bypass_entry = NULL;
7827         return 0;
7828 }