1 /******************************************************************************/
3 /* Bypass Control utility, Copyright (c) 2005-20011 Silicom */
5 /* This program is free software; you can redistribute it and/or modify */
6 /* it under the terms of the GNU General Public License as published by */
7 /* the Free Software Foundation, located in the file LICENSE. */
8 /* Copyright(c) 2007 - 2009 Intel Corporation. All rights reserved. */
11 /******************************************************************************/
13 #include <linux/kernel.h> /* We're doing kernel work */
14 #include <linux/module.h> /* Specifically, a module */
16 #include <linux/pci.h>
17 #include <linux/delay.h>
18 #include <linux/netdevice.h>
19 #include <linux/rtnetlink.h>
20 #include <linux/rcupdate.h>
21 #include <linux/etherdevice.h>
23 #include <linux/uaccess.h> /* for get_user and put_user */
24 #include <linux/sched.h>
25 #include <linux/ethtool.h>
26 #include <linux/proc_fs.h>
34 #define BP_MOD_VER "9.0.4"
35 #define BP_MOD_DESCR "Silicom Bypass-SD Control driver"
36 #define BP_SYNC_FLAG 1
38 static int Device_Open = 0;
39 static int major_num = 0;
41 MODULE_AUTHOR("Anna Lukin, annal@silicom.co.il");
42 MODULE_LICENSE("GPL");
43 MODULE_DESCRIPTION(BP_MOD_DESCR);
44 MODULE_VERSION(BP_MOD_VER);
47 #define lock_bpctl() \
48 if (down_interruptible(&bpctl_sema)) { \
49 return -ERESTARTSYS; \
52 #define unlock_bpctl() \
64 struct proc_dir_entry *proc_entry;
68 struct bypass_pfs_sd {
70 struct proc_dir_entry *bypass_entry;
71 struct pfs_unit_sd bypass_info;
72 struct pfs_unit_sd bypass_slave;
73 struct pfs_unit_sd bypass_caps;
74 struct pfs_unit_sd wd_set_caps;
75 struct pfs_unit_sd bypass;
76 struct pfs_unit_sd bypass_change;
77 struct pfs_unit_sd bypass_wd;
78 struct pfs_unit_sd wd_expire_time;
79 struct pfs_unit_sd reset_bypass_wd;
80 struct pfs_unit_sd dis_bypass;
81 struct pfs_unit_sd bypass_pwup;
82 struct pfs_unit_sd bypass_pwoff;
83 struct pfs_unit_sd std_nic;
84 struct pfs_unit_sd tap;
85 struct pfs_unit_sd dis_tap;
86 struct pfs_unit_sd tap_pwup;
87 struct pfs_unit_sd tap_change;
88 struct pfs_unit_sd wd_exp_mode;
89 struct pfs_unit_sd wd_autoreset;
90 struct pfs_unit_sd tpl;
94 typedef struct _bpctl_dev {
97 struct pci_dev *pdev; /* PCI device */
98 struct net_device *ndev; /* net device */
99 unsigned long mem_map;
113 unsigned long bypass_wdt_on_time;
114 uint32_t bypass_timer_interval;
115 struct timer_list bp_timer;
117 uint8_t bp_status_un;
119 bp_media_type media_type;
121 struct timer_list bp_tpl_timer;
122 spinlock_t bypass_wr_lock;
129 int (*hard_start_xmit_save) (struct sk_buff *skb,
130 struct net_device *dev);
131 const struct net_device_ops *old_ops;
132 struct net_device_ops new_ops;
133 int bp_self_test_flag;
135 struct bypass_pfs_sd bypass_pfs_set;
139 static bpctl_dev_t *bpctl_dev_arr;
141 static struct semaphore bpctl_sema;
142 static int device_num = 0;
144 static int get_dev_idx(int ifindex);
145 static bpctl_dev_t *get_master_port_fn(bpctl_dev_t *pbpctl_dev);
146 static int disc_status(bpctl_dev_t *pbpctl_dev);
147 static int bypass_status(bpctl_dev_t *pbpctl_dev);
148 static int wdt_timer(bpctl_dev_t *pbpctl_dev, int *time_left);
149 static bpctl_dev_t *get_status_port_fn(bpctl_dev_t *pbpctl_dev);
150 static void if_scan_init(void);
152 int bypass_proc_create_dev_sd(bpctl_dev_t *pbp_device_block);
153 int bypass_proc_remove_dev_sd(bpctl_dev_t *pbp_device_block);
154 int bp_proc_create(void);
156 int is_bypass_fn(bpctl_dev_t *pbpctl_dev);
157 int get_dev_idx_bsf(int bus, int slot, int func);
159 static unsigned long str_to_hex(char *p);
160 static int bp_device_event(struct notifier_block *unused,
161 unsigned long event, void *ptr)
163 struct net_device *dev = ptr;
164 static bpctl_dev_t *pbpctl_dev = NULL, *pbpctl_dev_m = NULL;
165 int dev_num = 0, ret = 0, ret_d = 0, time_left = 0;
166 /* printk("BP_PROC_SUPPORT event =%d %s %d\n", event,dev->name, dev->ifindex ); */
167 /* return NOTIFY_DONE; */
170 if (event == NETDEV_REGISTER) {
172 struct ethtool_drvinfo drvinfo;
176 int i = 0, ifindex, idx_dev = 0;
177 int bus = 0, slot = 0, func = 0;
178 ifindex = dev->ifindex;
181 memset(&drvinfo, 0, sizeof(struct ethtool_drvinfo));
183 if (dev->ethtool_ops && dev->ethtool_ops->get_drvinfo) {
184 memset(&drvinfo, 0, sizeof(drvinfo));
185 dev->ethtool_ops->get_drvinfo(dev, &drvinfo);
188 if (!drvinfo.bus_info)
190 if (!strcmp(drvinfo.bus_info, "N/A"))
192 memcpy(&cbuf, drvinfo.bus_info, 32);
195 while (*buf++ != ':') ;
196 for (i = 0; i < 10; i++, buf++) {
203 bus = str_to_hex(res);
206 for (i = 0; i < 10; i++, buf++) {
213 slot = str_to_hex(res);
214 func = str_to_hex(buf);
215 idx_dev = get_dev_idx_bsf(bus, slot, func);
219 bpctl_dev_arr[idx_dev].ifindex = ifindex;
220 bpctl_dev_arr[idx_dev].ndev = dev;
222 bypass_proc_remove_dev_sd(&bpctl_dev_arr
224 bypass_proc_create_dev_sd(&bpctl_dev_arr
233 if (event == NETDEV_UNREGISTER) {
236 ((bpctl_dev_arr[idx_dev].pdev != NULL)
237 && (idx_dev < device_num)); idx_dev++) {
238 if (bpctl_dev_arr[idx_dev].ndev == dev) {
239 bypass_proc_remove_dev_sd(&bpctl_dev_arr
241 bpctl_dev_arr[idx_dev].ndev = NULL;
250 if (event == NETDEV_CHANGENAME) {
253 ((bpctl_dev_arr[idx_dev].pdev != NULL)
254 && (idx_dev < device_num)); idx_dev++) {
255 if (bpctl_dev_arr[idx_dev].ndev == dev) {
256 bypass_proc_remove_dev_sd(&bpctl_dev_arr
258 bypass_proc_create_dev_sd(&bpctl_dev_arr
273 if (netif_carrier_ok(dev))
276 if (((dev_num = get_dev_idx(dev->ifindex)) == -1) ||
277 (!(pbpctl_dev = &bpctl_dev_arr[dev_num])))
280 if ((is_bypass_fn(pbpctl_dev)) == 1)
281 pbpctl_dev_m = pbpctl_dev;
283 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
286 ret = bypass_status(pbpctl_dev_m);
288 printk("bpmod: %s is in the Bypass mode now",
290 ret_d = disc_status(pbpctl_dev_m);
293 ("bpmod: %s is in the Disconnect mode now",
296 wdt_timer(pbpctl_dev_m, &time_left);
298 printk("; WDT has expired");
314 static struct notifier_block bp_notifier_block = {
315 .notifier_call = bp_device_event,
318 static int device_open(struct inode *inode, struct file *file)
321 printk("device_open(%p)\n", file);
325 * Initialize the message
330 static int device_release(struct inode *inode, struct file *file)
333 printk("device_release(%p,%p)\n", inode, file);
339 int is_bypass_fn(bpctl_dev_t *pbpctl_dev);
340 int wdt_time_left(bpctl_dev_t *pbpctl_dev);
342 static void write_pulse(bpctl_dev_t *pbpctl_dev,
343 unsigned int ctrl_ext,
344 unsigned char value, unsigned char len)
346 unsigned char ctrl_val = 0;
347 unsigned int i = len;
348 unsigned int ctrl = 0;
349 bpctl_dev_t *pbpctl_dev_c = NULL;
351 if (pbpctl_dev->bp_i80)
352 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
353 if (pbpctl_dev->bp_540)
354 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
356 if (pbpctl_dev->bp_10g9) {
357 if (!(pbpctl_dev_c = get_status_port_fn(pbpctl_dev)))
359 ctrl = BP10G_READ_REG(pbpctl_dev_c, ESDP);
363 ctrl_val = (value >> i) & 0x1;
365 if (pbpctl_dev->bp_10g9) {
367 /* To start management : MCLK 1, MDIO 1, output */
369 /*BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext|BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9)); */
370 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
372 BP10G_MDIO_DATA_OUT9);
373 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
374 (ctrl | BP10G_MCLK_DATA_OUT9 |
375 BP10G_MCLK_DIR_OUT9));
377 } else if (pbpctl_dev->bp_fiber5) {
378 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, (ctrl_ext |
379 BPCTLI_CTRL_EXT_MCLK_DIR5
381 BPCTLI_CTRL_EXT_MDIO_DIR5
383 BPCTLI_CTRL_EXT_MDIO_DATA5
385 BPCTLI_CTRL_EXT_MCLK_DATA5));
387 } else if (pbpctl_dev->bp_i80) {
388 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, (ctrl_ext |
389 BPCTLI_CTRL_EXT_MDIO_DIR80
391 BPCTLI_CTRL_EXT_MDIO_DATA80));
393 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, (ctrl |
394 BPCTLI_CTRL_EXT_MCLK_DIR80
396 BPCTLI_CTRL_EXT_MCLK_DATA80));
398 } else if (pbpctl_dev->bp_540) {
399 BP10G_WRITE_REG(pbpctl_dev, ESDP, (ctrl |
408 } else if (pbpctl_dev->bp_10gb) {
409 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
410 (ctrl_ext | BP10GB_MDIO_SET |
417 } else if (!pbpctl_dev->bp_10g)
418 /* To start management : MCLK 1, MDIO 1, output */
419 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
421 BPCTLI_CTRL_EXT_MCLK_DIR |
422 BPCTLI_CTRL_EXT_MDIO_DIR |
423 BPCTLI_CTRL_EXT_MDIO_DATA |
424 BPCTLI_CTRL_EXT_MCLK_DATA));
427 /* To start management : MCLK 1, MDIO 1, output*/
428 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
429 (ctrl_ext | BP10G_MCLK_DATA_OUT
430 | BP10G_MDIO_DATA_OUT));
434 usec_delay(PULSE_TIME);
435 if (pbpctl_dev->bp_10g9) {
437 /*BP10G_WRITE_REG(pbpctl_dev, I2CCTL, ((ctrl_ext|BP10G_MDIO_DATA_OUT9)&~(BP10G_MCLK_DATA_OUT9))); */
439 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
441 BP10G_MDIO_DATA_OUT9);
442 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
443 (ctrl | BP10G_MCLK_DIR_OUT9) &
444 ~BP10G_MCLK_DATA_OUT9);
446 } else if (pbpctl_dev->bp_fiber5) {
447 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
449 BPCTLI_CTRL_EXT_MCLK_DIR5 |
450 BPCTLI_CTRL_EXT_MDIO_DIR5 |
451 BPCTLI_CTRL_EXT_MDIO_DATA5)
454 (BPCTLI_CTRL_EXT_MCLK_DATA5)));
456 } else if (pbpctl_dev->bp_i80) {
457 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, (ctrl_ext |
458 BPCTLI_CTRL_EXT_MDIO_DIR80
460 BPCTLI_CTRL_EXT_MDIO_DATA80));
461 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
463 BPCTLI_CTRL_EXT_MCLK_DIR80)
466 (BPCTLI_CTRL_EXT_MCLK_DATA80)));
468 } else if (pbpctl_dev->bp_540) {
469 BP10G_WRITE_REG(pbpctl_dev, ESDP,
470 (ctrl | BP540_MDIO_DIR |
475 } else if (pbpctl_dev->bp_10gb) {
477 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
478 (ctrl_ext | BP10GB_MDIO_SET |
485 } else if (!pbpctl_dev->bp_10g)
487 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
489 BPCTLI_CTRL_EXT_MCLK_DIR |
490 BPCTLI_CTRL_EXT_MDIO_DIR |
491 BPCTLI_CTRL_EXT_MDIO_DATA)
494 (BPCTLI_CTRL_EXT_MCLK_DATA)));
497 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
499 BP10G_MDIO_DATA_OUT) &
500 ~(BP10G_MCLK_DATA_OUT)));
503 usec_delay(PULSE_TIME);
506 if (pbpctl_dev->bp_10g9) {
508 /*BP10G_WRITE_REG(pbpctl_dev, I2CCTL, ((ctrl_ext|BP10G_MCLK_DATA_OUT9)&~BP10G_MDIO_DATA_OUT9)); */
509 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
511 ~BP10G_MDIO_DATA_OUT9));
512 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
513 (ctrl | BP10G_MCLK_DATA_OUT9 |
514 BP10G_MCLK_DIR_OUT9));
516 } else if (pbpctl_dev->bp_fiber5) {
517 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
519 BPCTLI_CTRL_EXT_MCLK_DIR5 |
520 BPCTLI_CTRL_EXT_MDIO_DIR5 |
521 BPCTLI_CTRL_EXT_MCLK_DATA5)
524 (BPCTLI_CTRL_EXT_MDIO_DATA5)));
526 } else if (pbpctl_dev->bp_i80) {
527 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
529 BPCTLI_CTRL_EXT_MDIO_DIR80)
532 (BPCTLI_CTRL_EXT_MDIO_DATA80)));
533 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
535 BPCTLI_CTRL_EXT_MCLK_DIR80 |
536 BPCTLI_CTRL_EXT_MCLK_DATA80));
538 } else if (pbpctl_dev->bp_540) {
539 BP10G_WRITE_REG(pbpctl_dev, ESDP,
540 ((ctrl | BP540_MCLK_DIR |
543 ~(BP540_MDIO_DATA)));
545 } else if (pbpctl_dev->bp_10gb) {
546 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
547 (ctrl_ext | BP10GB_MDIO_CLR |
554 } else if (!pbpctl_dev->bp_10g)
556 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
558 BPCTLI_CTRL_EXT_MCLK_DIR |
559 BPCTLI_CTRL_EXT_MDIO_DIR |
560 BPCTLI_CTRL_EXT_MCLK_DATA)
563 (BPCTLI_CTRL_EXT_MDIO_DATA)));
566 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
568 BP10G_MCLK_DATA_OUT) &
569 ~BP10G_MDIO_DATA_OUT));
572 usec_delay(PULSE_TIME);
573 if (pbpctl_dev->bp_10g9) {
575 /*BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext&~(BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9))); */
576 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
578 ~BP10G_MDIO_DATA_OUT9));
579 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
580 ((ctrl | BP10G_MCLK_DIR_OUT9) &
581 ~(BP10G_MCLK_DATA_OUT9)));
583 } else if (pbpctl_dev->bp_fiber5) {
584 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
586 BPCTLI_CTRL_EXT_MCLK_DIR5 |
587 BPCTLI_CTRL_EXT_MDIO_DIR5)
589 ~(BPCTLI_CTRL_EXT_MCLK_DATA5
591 BPCTLI_CTRL_EXT_MDIO_DATA5)));
593 } else if (pbpctl_dev->bp_i80) {
594 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
596 BPCTLI_CTRL_EXT_MDIO_DIR80)
598 ~BPCTLI_CTRL_EXT_MDIO_DATA80));
599 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
601 BPCTLI_CTRL_EXT_MCLK_DIR80)
604 (BPCTLI_CTRL_EXT_MCLK_DATA80)));
606 } else if (pbpctl_dev->bp_540) {
607 BP10G_WRITE_REG(pbpctl_dev, ESDP,
608 ((ctrl | BP540_MCLK_DIR |
612 } else if (pbpctl_dev->bp_10gb) {
614 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
615 (ctrl_ext | BP10GB_MDIO_CLR |
622 } else if (!pbpctl_dev->bp_10g)
623 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
625 BPCTLI_CTRL_EXT_MCLK_DIR |
626 BPCTLI_CTRL_EXT_MDIO_DIR) &
627 ~(BPCTLI_CTRL_EXT_MCLK_DATA
629 BPCTLI_CTRL_EXT_MDIO_DATA)));
632 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
634 ~(BP10G_MCLK_DATA_OUT |
635 BP10G_MDIO_DATA_OUT)));
638 usec_delay(PULSE_TIME);
644 static int read_pulse(bpctl_dev_t *pbpctl_dev, unsigned int ctrl_ext,
647 unsigned char ctrl_val = 0;
648 unsigned int i = len;
649 unsigned int ctrl = 0;
650 bpctl_dev_t *pbpctl_dev_c = NULL;
652 if (pbpctl_dev->bp_i80)
653 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
654 if (pbpctl_dev->bp_540)
655 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
656 if (pbpctl_dev->bp_10g9) {
657 if (!(pbpctl_dev_c = get_status_port_fn(pbpctl_dev)))
659 ctrl = BP10G_READ_REG(pbpctl_dev_c, ESDP);
664 if (pbpctl_dev->bp_10g9) {
665 /*BP10G_WRITE_REG(pbpctl_dev, I2CCTL, ((ctrl_ext|BP10G_MDIO_DATA_OUT9)&~BP10G_MCLK_DATA_OUT9)); */
667 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
668 ((ctrl | BP10G_MCLK_DIR_OUT9) &
669 ~(BP10G_MCLK_DATA_OUT9)));
671 } else if (pbpctl_dev->bp_fiber5) {
672 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
673 BPCTLI_CTRL_EXT_MCLK_DIR5)
676 (BPCTLI_CTRL_EXT_MDIO_DIR5
678 BPCTLI_CTRL_EXT_MCLK_DATA5)));
680 } else if (pbpctl_dev->bp_i80) {
681 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
683 ~BPCTLI_CTRL_EXT_MDIO_DIR80));
684 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
685 ((ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80)
686 & ~(BPCTLI_CTRL_EXT_MCLK_DATA80)));
688 } else if (pbpctl_dev->bp_540) {
689 BP10G_WRITE_REG(pbpctl_dev, ESDP,
690 ((ctrl | BP540_MCLK_DIR) &
691 ~(BP540_MDIO_DIR | BP540_MCLK_DATA)));
693 } else if (pbpctl_dev->bp_10gb) {
695 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
696 (ctrl_ext | BP10GB_MDIO_DIR |
697 BP10GB_MCLK_CLR) & ~(BP10GB_MCLK_DIR |
702 } else if (!pbpctl_dev->bp_10g)
703 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
704 BPCTLI_CTRL_EXT_MCLK_DIR)
707 (BPCTLI_CTRL_EXT_MDIO_DIR
709 BPCTLI_CTRL_EXT_MCLK_DATA)));
712 BP10G_WRITE_REG(pbpctl_dev, EODSDP, ((ctrl_ext | BP10G_MDIO_DATA_OUT) & ~BP10G_MCLK_DATA_OUT)); /* ? */
713 /* printk("0x28=0x%x\n",BP10G_READ_REG(pbpctl_dev,EODSDP);); */
717 usec_delay(PULSE_TIME);
718 if (pbpctl_dev->bp_10g9) {
719 /*BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext|BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9)); */
721 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
722 (ctrl | BP10G_MCLK_DATA_OUT9 |
723 BP10G_MCLK_DIR_OUT9));
725 } else if (pbpctl_dev->bp_fiber5) {
726 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
727 BPCTLI_CTRL_EXT_MCLK_DIR5
729 BPCTLI_CTRL_EXT_MCLK_DATA5)
732 (BPCTLI_CTRL_EXT_MDIO_DIR5)));
734 } else if (pbpctl_dev->bp_i80) {
735 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
737 ~(BPCTLI_CTRL_EXT_MDIO_DIR80)));
738 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
739 (ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80 |
740 BPCTLI_CTRL_EXT_MCLK_DATA80));
742 } else if (pbpctl_dev->bp_540) {
743 BP10G_WRITE_REG(pbpctl_dev, ESDP,
744 ((ctrl | BP540_MCLK_DIR |
748 } else if (pbpctl_dev->bp_10gb) {
749 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
750 (ctrl_ext | BP10GB_MDIO_DIR |
751 BP10GB_MCLK_SET) & ~(BP10GB_MCLK_DIR |
756 } else if (!pbpctl_dev->bp_10g)
757 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
758 BPCTLI_CTRL_EXT_MCLK_DIR
760 BPCTLI_CTRL_EXT_MCLK_DATA)
763 (BPCTLI_CTRL_EXT_MDIO_DIR)));
766 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
767 (ctrl_ext | BP10G_MCLK_DATA_OUT |
768 BP10G_MDIO_DATA_OUT));
771 if (pbpctl_dev->bp_10g9) {
772 ctrl_ext = BP10G_READ_REG(pbpctl_dev, I2CCTL);
774 } else if ((pbpctl_dev->bp_fiber5) || (pbpctl_dev->bp_i80)) {
775 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL);
776 } else if (pbpctl_dev->bp_540) {
777 ctrl_ext = BP10G_READ_REG(pbpctl_dev, ESDP);
778 } else if (pbpctl_dev->bp_10gb)
779 ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
781 else if (!pbpctl_dev->bp_10g)
782 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
784 ctrl_ext = BP10G_READ_REG(pbpctl_dev, EODSDP);
786 usec_delay(PULSE_TIME);
787 if (pbpctl_dev->bp_10g9) {
788 if (ctrl_ext & BP10G_MDIO_DATA_IN9)
791 } else if (pbpctl_dev->bp_fiber5) {
792 if (ctrl_ext & BPCTLI_CTRL_EXT_MDIO_DATA5)
794 } else if (pbpctl_dev->bp_i80) {
795 if (ctrl_ext & BPCTLI_CTRL_EXT_MDIO_DATA80)
797 } else if (pbpctl_dev->bp_540) {
798 if (ctrl_ext & BP540_MDIO_DATA)
800 } else if (pbpctl_dev->bp_10gb) {
801 if (ctrl_ext & BP10GB_MDIO_DATA)
804 } else if (!pbpctl_dev->bp_10g) {
806 if (ctrl_ext & BPCTLI_CTRL_EXT_MDIO_DATA)
810 if (ctrl_ext & BP10G_MDIO_DATA_IN)
819 static void write_reg(bpctl_dev_t *pbpctl_dev, unsigned char value,
822 uint32_t ctrl_ext = 0, ctrl = 0;
823 bpctl_dev_t *pbpctl_dev_c = NULL;
825 if (pbpctl_dev->bp_10g9) {
826 if (!(pbpctl_dev_c = get_status_port_fn(pbpctl_dev)))
829 if ((pbpctl_dev->wdt_status == WDT_STATUS_EN) &&
830 (pbpctl_dev->bp_ext_ver < PXG4BPFI_VER))
831 wdt_time_left(pbpctl_dev);
834 spin_lock_irqsave(&pbpctl_dev->bypass_wr_lock, flags);
836 atomic_set(&pbpctl_dev->wdt_busy, 1);
838 if (pbpctl_dev->bp_10g9) {
840 ctrl_ext = BP10G_READ_REG(pbpctl_dev, I2CCTL);
841 ctrl = BP10G_READ_REG(pbpctl_dev_c, ESDP);
843 /* BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext&~(BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9))); */
844 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
845 (ctrl_ext & ~BP10G_MDIO_DATA_OUT9));
846 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
847 ((ctrl | BP10G_MCLK_DIR_OUT9) &
848 ~(BP10G_MCLK_DATA_OUT9)));
850 } else if (pbpctl_dev->bp_fiber5) {
851 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL);
852 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
853 BPCTLI_CTRL_EXT_MCLK_DIR5
855 BPCTLI_CTRL_EXT_MDIO_DIR5)
858 (BPCTLI_CTRL_EXT_MDIO_DATA5
860 BPCTLI_CTRL_EXT_MCLK_DATA5)));
861 } else if (pbpctl_dev->bp_i80) {
862 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL);
863 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
864 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
865 BPCTLI_CTRL_EXT_MDIO_DIR80)
867 ~BPCTLI_CTRL_EXT_MDIO_DATA80));
868 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
869 ((ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80) &
870 ~BPCTLI_CTRL_EXT_MCLK_DATA80));
872 } else if (pbpctl_dev->bp_540) {
873 ctrl = ctrl_ext = BP10G_READ_REG(pbpctl_dev, ESDP);
874 BP10G_WRITE_REG(pbpctl_dev, ESDP, ((ctrl |
880 } else if (pbpctl_dev->bp_10gb) {
881 ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
883 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
884 (ctrl_ext | BP10GB_MDIO_CLR | BP10GB_MCLK_CLR)
885 & ~(BP10GB_MCLK_DIR | BP10GB_MDIO_DIR |
886 BP10GB_MDIO_SET | BP10GB_MCLK_SET));
888 } else if (!pbpctl_dev->bp_10g) {
890 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
891 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
892 BPCTLI_CTRL_EXT_MCLK_DIR
894 BPCTLI_CTRL_EXT_MDIO_DIR)
897 (BPCTLI_CTRL_EXT_MDIO_DATA
899 BPCTLI_CTRL_EXT_MCLK_DATA)));
901 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
902 ctrl_ext = BP10G_READ_REG(pbpctl_dev, EODSDP);
903 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
905 ~(BP10G_MCLK_DATA_OUT | BP10G_MDIO_DATA_OUT)));
907 usec_delay(CMND_INTERVAL);
910 write_pulse(pbpctl_dev, ctrl_ext, SYNC_CMD_VAL, SYNC_CMD_LEN);
912 write_pulse(pbpctl_dev, ctrl_ext, WR_CMD_VAL, WR_CMD_LEN);
913 write_pulse(pbpctl_dev, ctrl_ext, addr, ADDR_CMD_LEN);
916 write_pulse(pbpctl_dev, ctrl_ext, value, WR_DATA_LEN);
917 if (pbpctl_dev->bp_10g9) {
918 /*BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext&~(BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9))); */
920 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
921 (ctrl_ext & ~BP10G_MDIO_DATA_OUT9));
922 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
923 ((ctrl | BP10G_MCLK_DIR_OUT9) &
924 ~(BP10G_MCLK_DATA_OUT9)));
926 } else if (pbpctl_dev->bp_fiber5) {
927 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
928 BPCTLI_CTRL_EXT_MCLK_DIR5
930 BPCTLI_CTRL_EXT_MDIO_DIR5)
933 (BPCTLI_CTRL_EXT_MDIO_DATA5
935 BPCTLI_CTRL_EXT_MCLK_DATA5)));
936 } else if (pbpctl_dev->bp_i80) {
937 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
938 BPCTLI_CTRL_EXT_MDIO_DIR80)
940 ~BPCTLI_CTRL_EXT_MDIO_DATA80));
941 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
942 ((ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80) &
943 ~BPCTLI_CTRL_EXT_MCLK_DATA80));
944 } else if (pbpctl_dev->bp_540) {
945 BP10G_WRITE_REG(pbpctl_dev, ESDP, ((ctrl |
950 } else if (pbpctl_dev->bp_10gb) {
951 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
952 (ctrl_ext | BP10GB_MDIO_CLR | BP10GB_MCLK_CLR)
953 & ~(BP10GB_MCLK_DIR | BP10GB_MDIO_DIR |
954 BP10GB_MDIO_SET | BP10GB_MCLK_SET));
956 } else if (!pbpctl_dev->bp_10g)
958 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
959 BPCTLI_CTRL_EXT_MCLK_DIR
961 BPCTLI_CTRL_EXT_MDIO_DIR)
964 (BPCTLI_CTRL_EXT_MDIO_DATA
966 BPCTLI_CTRL_EXT_MCLK_DATA)));
968 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
970 ~(BP10G_MCLK_DATA_OUT | BP10G_MDIO_DATA_OUT)));
974 usec_delay(CMND_INTERVAL * 4);
976 if ((pbpctl_dev->wdt_status == WDT_STATUS_EN) &&
977 (pbpctl_dev->bp_ext_ver < PXG4BPFI_VER) && (addr == CMND_REG_ADDR))
978 pbpctl_dev->bypass_wdt_on_time = jiffies;
980 spin_unlock_irqrestore(&pbpctl_dev->bypass_wr_lock, flags);
982 atomic_set(&pbpctl_dev->wdt_busy, 0);
987 static void write_data(bpctl_dev_t *pbpctl_dev, unsigned char value)
989 write_reg(pbpctl_dev, value, CMND_REG_ADDR);
992 static int read_reg(bpctl_dev_t *pbpctl_dev, unsigned char addr)
994 uint32_t ctrl_ext = 0, ctrl = 0, ctrl_value = 0;
995 bpctl_dev_t *pbpctl_dev_c = NULL;
999 spin_lock_irqsave(&pbpctl_dev->bypass_wr_lock, flags);
1001 atomic_set(&pbpctl_dev->wdt_busy, 1);
1003 if (pbpctl_dev->bp_10g9) {
1004 if (!(pbpctl_dev_c = get_status_port_fn(pbpctl_dev)))
1008 if (pbpctl_dev->bp_10g9) {
1009 ctrl_ext = BP10G_READ_REG(pbpctl_dev, I2CCTL);
1010 ctrl = BP10G_READ_REG(pbpctl_dev_c, ESDP);
1012 /* BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext&~(BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9))); */
1014 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
1015 (ctrl_ext & ~BP10G_MDIO_DATA_OUT9));
1016 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
1017 ((ctrl | BP10G_MCLK_DIR_OUT9) &
1018 ~(BP10G_MCLK_DATA_OUT9)));
1020 } else if (pbpctl_dev->bp_fiber5) {
1021 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL);
1023 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1024 BPCTLI_CTRL_EXT_MCLK_DIR5
1026 BPCTLI_CTRL_EXT_MDIO_DIR5)
1029 (BPCTLI_CTRL_EXT_MDIO_DATA5
1031 BPCTLI_CTRL_EXT_MCLK_DATA5)));
1032 } else if (pbpctl_dev->bp_i80) {
1033 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL);
1034 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1036 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1037 BPCTLI_CTRL_EXT_MDIO_DIR80)
1039 ~BPCTLI_CTRL_EXT_MDIO_DATA80));
1040 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
1041 ((ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80) &
1042 ~BPCTLI_CTRL_EXT_MCLK_DATA80));
1043 } else if (pbpctl_dev->bp_540) {
1044 ctrl_ext = BP10G_READ_REG(pbpctl_dev, ESDP);
1045 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
1047 BP10G_WRITE_REG(pbpctl_dev, ESDP, ((ctrl | BP540_MCLK_DIR |
1051 } else if (pbpctl_dev->bp_10gb) {
1052 ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
1054 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
1055 (ctrl_ext | BP10GB_MDIO_CLR | BP10GB_MCLK_CLR)
1056 & ~(BP10GB_MCLK_DIR | BP10GB_MDIO_DIR |
1057 BP10GB_MDIO_SET | BP10GB_MCLK_SET));
1060 /*BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO, (ctrl_ext | BP10GB_MCLK_DIR | BP10GB_MDIO_DIR|
1061 BP10GB_MCLK_CLR|BP10GB_MDIO_CLR));
1062 ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
1063 printk("1reg=%x\n", ctrl_ext); */
1065 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO, ((ctrl_ext |
1068 & ~(BP10GB_MCLK_CLR | BP10GB_MDIO_SET |
1069 BP10GB_MCLK_DIR | BP10GB_MDIO_DIR));
1071 /* bnx2x_set_spio(pbpctl_dev, 5, MISC_REGISTERS_SPIO_OUTPUT_LOW);
1072 bnx2x_set_spio(pbpctl_dev, 4, MISC_REGISTERS_SPIO_OUTPUT_LOW);
1073 bnx2x_set_spio(pbpctl_dev, 4, MISC_REGISTERS_SPIO_INPUT_HI_Z); */
1075 ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
1077 printk("2reg=%x\n", ctrl_ext);
1080 spin_unlock_irqrestore(&pbpctl_dev->bypass_wr_lock, flags);
1082 atomic_set(&pbpctl_dev->wdt_busy, 0);
1089 } else if (!pbpctl_dev->bp_10g) {
1091 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1093 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1094 BPCTLI_CTRL_EXT_MCLK_DIR
1096 BPCTLI_CTRL_EXT_MDIO_DIR)
1099 (BPCTLI_CTRL_EXT_MDIO_DATA
1101 BPCTLI_CTRL_EXT_MCLK_DATA)));
1104 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
1105 ctrl_ext = BP10G_READ_REG(pbpctl_dev, EODSDP);
1106 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
1108 ~(BP10G_MCLK_DATA_OUT | BP10G_MDIO_DATA_OUT)));
1112 usec_delay(CMND_INTERVAL);
1115 write_pulse(pbpctl_dev, ctrl_ext, SYNC_CMD_VAL, SYNC_CMD_LEN);
1117 write_pulse(pbpctl_dev, ctrl_ext, RD_CMD_VAL, RD_CMD_LEN);
1119 write_pulse(pbpctl_dev, ctrl_ext, addr, ADDR_CMD_LEN);
1122 if (pbpctl_dev->bp_10g9) {
1124 /*BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext|BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9)); */
1125 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
1126 (ctrl_ext | BP10G_MDIO_DATA_OUT9));
1127 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
1128 (ctrl | BP10G_MCLK_DATA_OUT9 |
1129 BP10G_MCLK_DIR_OUT9));
1131 } else if (pbpctl_dev->bp_fiber5) {
1132 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1133 BPCTLI_CTRL_EXT_MCLK_DIR5
1135 BPCTLI_CTRL_EXT_MCLK_DATA5)
1138 (BPCTLI_CTRL_EXT_MDIO_DIR5
1140 BPCTLI_CTRL_EXT_MDIO_DATA5)));
1142 } else if (pbpctl_dev->bp_i80) {
1143 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
1145 ~(BPCTLI_CTRL_EXT_MDIO_DATA80 |
1146 BPCTLI_CTRL_EXT_MDIO_DIR80)));
1147 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
1148 (ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80 |
1149 BPCTLI_CTRL_EXT_MCLK_DATA80));
1151 } else if (pbpctl_dev->bp_540) {
1152 BP10G_WRITE_REG(pbpctl_dev, ESDP,
1153 (((ctrl | BP540_MDIO_DIR | BP540_MCLK_DIR |
1154 BP540_MCLK_DATA) & ~BP540_MDIO_DATA)));
1156 } else if (pbpctl_dev->bp_10gb) {
1158 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
1159 (ctrl_ext | BP10GB_MDIO_DIR | BP10GB_MCLK_SET)
1160 & ~(BP10GB_MCLK_DIR | BP10GB_MDIO_SET |
1161 BP10GB_MDIO_CLR | BP10GB_MCLK_CLR));
1163 } else if (!pbpctl_dev->bp_10g)
1164 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1165 BPCTLI_CTRL_EXT_MCLK_DIR
1167 BPCTLI_CTRL_EXT_MCLK_DATA)
1170 (BPCTLI_CTRL_EXT_MDIO_DIR
1172 BPCTLI_CTRL_EXT_MDIO_DATA)));
1175 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
1176 (ctrl_ext | BP10G_MCLK_DATA_OUT |
1177 BP10G_MDIO_DATA_OUT));
1181 usec_delay(PULSE_TIME);
1183 ctrl_value = read_pulse(pbpctl_dev, ctrl_ext, RD_DATA_LEN);
1185 if (pbpctl_dev->bp_10g9) {
1186 ctrl_ext = BP10G_READ_REG(pbpctl_dev, I2CCTL);
1187 ctrl = BP10G_READ_REG(pbpctl_dev_c, ESDP);
1189 /* BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext&~(BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9))); */
1191 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
1192 (ctrl_ext & ~BP10G_MDIO_DATA_OUT9));
1193 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
1194 ((ctrl | BP10G_MCLK_DIR_OUT9) &
1195 ~(BP10G_MCLK_DATA_OUT9)));
1197 } else if (pbpctl_dev->bp_fiber5) {
1198 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1199 BPCTLI_CTRL_EXT_MCLK_DIR5
1201 BPCTLI_CTRL_EXT_MDIO_DIR5)
1204 (BPCTLI_CTRL_EXT_MDIO_DATA5
1206 BPCTLI_CTRL_EXT_MCLK_DATA5)));
1207 } else if (pbpctl_dev->bp_i80) {
1208 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1209 BPCTLI_CTRL_EXT_MDIO_DIR80)
1211 ~BPCTLI_CTRL_EXT_MDIO_DATA80));
1212 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
1213 ((ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80) &
1214 ~BPCTLI_CTRL_EXT_MCLK_DATA80));
1216 } else if (pbpctl_dev->bp_540) {
1217 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
1218 BP10G_WRITE_REG(pbpctl_dev, ESDP, ((ctrl | BP540_MCLK_DIR |
1223 } else if (pbpctl_dev->bp_10gb) {
1224 ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
1225 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
1226 (ctrl_ext | BP10GB_MDIO_CLR | BP10GB_MCLK_CLR)
1227 & ~(BP10GB_MCLK_DIR | BP10GB_MDIO_DIR |
1228 BP10GB_MDIO_SET | BP10GB_MCLK_SET));
1230 } else if (!pbpctl_dev->bp_10g) {
1231 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1232 BPCTLI_CTRL_EXT_MCLK_DIR
1234 BPCTLI_CTRL_EXT_MDIO_DIR)
1237 (BPCTLI_CTRL_EXT_MDIO_DATA
1239 BPCTLI_CTRL_EXT_MCLK_DATA)));
1242 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
1243 ctrl_ext = BP10G_READ_REG(pbpctl_dev, EODSDP);
1244 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
1246 ~(BP10G_MCLK_DATA_OUT | BP10G_MDIO_DATA_OUT)));
1250 usec_delay(CMND_INTERVAL * 4);
1252 spin_unlock_irqrestore(&pbpctl_dev->bypass_wr_lock, flags);
1254 atomic_set(&pbpctl_dev->wdt_busy, 0);
1260 static int wdt_pulse(bpctl_dev_t *pbpctl_dev)
1262 uint32_t ctrl_ext = 0, ctrl = 0;
1263 bpctl_dev_t *pbpctl_dev_c = NULL;
1266 unsigned long flags;
1268 spin_lock_irqsave(&pbpctl_dev->bypass_wr_lock, flags);
1271 if ((atomic_read(&pbpctl_dev->wdt_busy)) == 1)
1274 if (pbpctl_dev->bp_10g9) {
1275 if (!(pbpctl_dev_c = get_status_port_fn(pbpctl_dev)))
1279 if (pbpctl_dev->bp_10g9) {
1280 ctrl_ext = BP10G_READ_REG(pbpctl_dev, I2CCTL);
1281 ctrl = BP10G_READ_REG(pbpctl_dev_c, ESDP);
1283 /* BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext&~(BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9))); */
1285 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
1286 (ctrl_ext & ~BP10G_MDIO_DATA_OUT9));
1287 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
1288 ((ctrl | BP10G_MCLK_DIR_OUT9) &
1289 ~(BP10G_MCLK_DATA_OUT9)));
1291 } else if (pbpctl_dev->bp_fiber5) {
1292 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL);
1293 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1294 BPCTLI_CTRL_EXT_MCLK_DIR5
1296 BPCTLI_CTRL_EXT_MDIO_DIR5)
1299 (BPCTLI_CTRL_EXT_MDIO_DATA5
1301 BPCTLI_CTRL_EXT_MCLK_DATA5)));
1302 } else if (pbpctl_dev->bp_i80) {
1303 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL);
1304 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1305 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1306 BPCTLI_CTRL_EXT_MDIO_DIR80)
1308 ~BPCTLI_CTRL_EXT_MDIO_DATA80));
1309 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
1310 ((ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80) &
1311 ~BPCTLI_CTRL_EXT_MCLK_DATA80));
1312 } else if (pbpctl_dev->bp_540) {
1313 ctrl_ext = ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
1314 BP10G_WRITE_REG(pbpctl_dev, ESDP, ((ctrl | BP540_MCLK_DIR |
1318 } else if (pbpctl_dev->bp_10gb) {
1319 ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
1320 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
1321 (ctrl_ext | BP10GB_MDIO_CLR | BP10GB_MCLK_CLR)
1322 & ~(BP10GB_MCLK_DIR | BP10GB_MDIO_DIR |
1323 BP10GB_MDIO_SET | BP10GB_MCLK_SET));
1325 } else if (!pbpctl_dev->bp_10g) {
1327 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1328 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1329 BPCTLI_CTRL_EXT_MCLK_DIR
1331 BPCTLI_CTRL_EXT_MDIO_DIR)
1334 (BPCTLI_CTRL_EXT_MDIO_DATA
1336 BPCTLI_CTRL_EXT_MCLK_DATA)));
1339 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
1340 ctrl_ext = BP10G_READ_REG(pbpctl_dev, EODSDP);
1341 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
1343 ~(BP10G_MCLK_DATA_OUT | BP10G_MDIO_DATA_OUT)));
1346 if (pbpctl_dev->bp_10g9) {
1347 /* BP10G_WRITE_REG(pbpctl_dev, I2CCTL, ((ctrl_ext|BP10G_MCLK_DATA_OUT9)&~BP10G_MDIO_DATA_OUT9)); */
1349 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
1350 (ctrl_ext & ~BP10G_MDIO_DATA_OUT9));
1351 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
1352 (ctrl | BP10G_MCLK_DATA_OUT9 |
1353 BP10G_MCLK_DIR_OUT9));
1355 } else if (pbpctl_dev->bp_fiber5) {
1356 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1357 BPCTLI_CTRL_EXT_MCLK_DIR5
1359 BPCTLI_CTRL_EXT_MDIO_DIR5
1361 BPCTLI_CTRL_EXT_MCLK_DATA5)
1364 (BPCTLI_CTRL_EXT_MDIO_DATA5)));
1365 } else if (pbpctl_dev->bp_i80) {
1366 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1367 BPCTLI_CTRL_EXT_MDIO_DIR80)
1369 ~BPCTLI_CTRL_EXT_MDIO_DATA80));
1370 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
1371 (ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80 |
1372 BPCTLI_CTRL_EXT_MCLK_DATA80));
1374 } else if (pbpctl_dev->bp_540) {
1375 BP10G_WRITE_REG(pbpctl_dev, ESDP, ((ctrl |
1381 } else if (pbpctl_dev->bp_10gb) {
1382 ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
1384 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
1385 (ctrl_ext | BP10GB_MDIO_CLR | BP10GB_MCLK_SET)
1386 & ~(BP10GB_MCLK_DIR | BP10GB_MDIO_DIR |
1387 BP10GB_MDIO_SET | BP10GB_MCLK_CLR));
1389 } else if (!pbpctl_dev->bp_10g)
1390 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1391 BPCTLI_CTRL_EXT_MCLK_DIR
1393 BPCTLI_CTRL_EXT_MDIO_DIR
1395 BPCTLI_CTRL_EXT_MCLK_DATA)
1398 (BPCTLI_CTRL_EXT_MDIO_DATA)));
1401 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
1402 ((ctrl_ext | BP10G_MCLK_DATA_OUT) &
1403 ~BP10G_MDIO_DATA_OUT));
1407 usec_delay(WDT_INTERVAL);
1408 if (pbpctl_dev->bp_10g9) {
1409 /* BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext&~(BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9))); */
1411 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
1412 (ctrl_ext & ~BP10G_MDIO_DATA_OUT9));
1413 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
1414 ((ctrl | BP10G_MCLK_DIR_OUT9) &
1415 ~(BP10G_MCLK_DATA_OUT9)));
1417 } else if (pbpctl_dev->bp_fiber5) {
1418 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1419 BPCTLI_CTRL_EXT_MCLK_DIR5
1421 BPCTLI_CTRL_EXT_MDIO_DIR5)
1424 (BPCTLI_CTRL_EXT_MCLK_DATA5
1426 BPCTLI_CTRL_EXT_MDIO_DATA5)));
1427 } else if (pbpctl_dev->bp_i80) {
1428 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1429 BPCTLI_CTRL_EXT_MDIO_DIR80)
1431 ~BPCTLI_CTRL_EXT_MDIO_DATA80));
1432 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
1433 ((ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80) &
1434 ~BPCTLI_CTRL_EXT_MCLK_DATA80));
1436 } else if (pbpctl_dev->bp_540) {
1437 BP10G_WRITE_REG(pbpctl_dev, ESDP, ((ctrl | BP540_MCLK_DIR |
1442 } else if (pbpctl_dev->bp_10gb) {
1443 ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
1444 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
1445 (ctrl_ext | BP10GB_MDIO_CLR | BP10GB_MCLK_CLR)
1446 & ~(BP10GB_MCLK_DIR | BP10GB_MDIO_DIR |
1447 BP10GB_MDIO_SET | BP10GB_MCLK_SET));
1449 } else if (!pbpctl_dev->bp_10g)
1450 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1451 BPCTLI_CTRL_EXT_MCLK_DIR
1453 BPCTLI_CTRL_EXT_MDIO_DIR)
1456 (BPCTLI_CTRL_EXT_MCLK_DATA
1458 BPCTLI_CTRL_EXT_MDIO_DATA)));
1461 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
1463 ~(BP10G_MCLK_DATA_OUT | BP10G_MDIO_DATA_OUT)));
1465 if ((pbpctl_dev->wdt_status == WDT_STATUS_EN) /*&&
1466 (pbpctl_dev->bp_ext_ver<PXG4BPFI_VER) */ )
1467 pbpctl_dev->bypass_wdt_on_time = jiffies;
1469 spin_unlock_irqrestore(&pbpctl_dev->bypass_wr_lock, flags);
1471 usec_delay(CMND_INTERVAL * 4);
1475 static void data_pulse(bpctl_dev_t *pbpctl_dev, unsigned char value)
1478 uint32_t ctrl_ext = 0;
1480 unsigned long flags;
1482 wdt_time_left(pbpctl_dev);
1484 spin_lock_irqsave(&pbpctl_dev->bypass_wr_lock, flags);
1486 atomic_set(&pbpctl_dev->wdt_busy, 1);
1489 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1490 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1491 BPCTLI_CTRL_EXT_SDP6_DIR |
1492 BPCTLI_CTRL_EXT_SDP7_DIR) &
1493 ~(BPCTLI_CTRL_EXT_SDP6_DATA |
1494 BPCTLI_CTRL_EXT_SDP7_DATA)));
1496 usec_delay(INIT_CMND_INTERVAL);
1497 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1498 BPCTLI_CTRL_EXT_SDP6_DIR |
1499 BPCTLI_CTRL_EXT_SDP7_DIR |
1500 BPCTLI_CTRL_EXT_SDP6_DATA) &
1502 (BPCTLI_CTRL_EXT_SDP7_DATA)));
1503 usec_delay(INIT_CMND_INTERVAL);
1506 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ctrl_ext |
1507 BPCTLI_CTRL_EXT_SDP6_DIR |
1508 BPCTLI_CTRL_EXT_SDP7_DIR |
1509 BPCTLI_CTRL_EXT_SDP6_DATA |
1510 BPCTLI_CTRL_EXT_SDP7_DATA);
1511 usec_delay(PULSE_INTERVAL);
1512 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1513 BPCTLI_CTRL_EXT_SDP6_DIR
1515 BPCTLI_CTRL_EXT_SDP7_DIR
1517 BPCTLI_CTRL_EXT_SDP6_DATA)
1519 ~BPCTLI_CTRL_EXT_SDP7_DATA));
1520 usec_delay(PULSE_INTERVAL);
1524 usec_delay(INIT_CMND_INTERVAL - PULSE_INTERVAL);
1525 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1526 BPCTLI_CTRL_EXT_SDP6_DIR |
1527 BPCTLI_CTRL_EXT_SDP7_DIR) &
1528 ~(BPCTLI_CTRL_EXT_SDP6_DATA |
1529 BPCTLI_CTRL_EXT_SDP7_DATA)));
1530 usec_delay(WDT_TIME_CNT);
1531 if (pbpctl_dev->wdt_status == WDT_STATUS_EN)
1532 pbpctl_dev->bypass_wdt_on_time = jiffies;
1534 spin_unlock_irqrestore(&pbpctl_dev->bypass_wr_lock, flags);
1536 atomic_set(&pbpctl_dev->wdt_busy, 0);
1541 static int send_wdt_pulse(bpctl_dev_t *pbpctl_dev)
1543 uint32_t ctrl_ext = 0;
1546 unsigned long flags;
1548 spin_lock_irqsave(&pbpctl_dev->bypass_wr_lock, flags);
1551 if ((atomic_read(&pbpctl_dev->wdt_busy)) == 1)
1554 wdt_time_left(pbpctl_dev);
1555 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1557 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ctrl_ext | /* 1 */
1558 BPCTLI_CTRL_EXT_SDP7_DIR |
1559 BPCTLI_CTRL_EXT_SDP7_DATA);
1560 usec_delay(PULSE_INTERVAL);
1561 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext | /* 0 */
1562 BPCTLI_CTRL_EXT_SDP7_DIR) &
1563 ~BPCTLI_CTRL_EXT_SDP7_DATA));
1565 usec_delay(PULSE_INTERVAL);
1566 if (pbpctl_dev->wdt_status == WDT_STATUS_EN)
1567 pbpctl_dev->bypass_wdt_on_time = jiffies;
1569 spin_unlock_irqrestore(&pbpctl_dev->bypass_wr_lock, flags);
1575 void send_bypass_clear_pulse(bpctl_dev_t *pbpctl_dev, unsigned int value)
1577 uint32_t ctrl_ext = 0;
1579 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1580 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext | /* 0 */
1581 BPCTLI_CTRL_EXT_SDP6_DIR) &
1582 ~BPCTLI_CTRL_EXT_SDP6_DATA));
1584 usec_delay(PULSE_INTERVAL);
1586 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ctrl_ext | /* 1 */
1587 BPCTLI_CTRL_EXT_SDP6_DIR |
1588 BPCTLI_CTRL_EXT_SDP6_DATA);
1589 usec_delay(PULSE_INTERVAL);
1592 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext | /* 0 */
1593 BPCTLI_CTRL_EXT_SDP6_DIR) &
1594 ~BPCTLI_CTRL_EXT_SDP6_DATA));
1595 usec_delay(PULSE_INTERVAL);
1601 int pulse_set_fn(bpctl_dev_t *pbpctl_dev, unsigned int counter)
1603 uint32_t ctrl_ext = 0;
1608 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1609 write_pulse_1(pbpctl_dev, ctrl_ext, counter, counter);
1611 pbpctl_dev->bypass_wdt_status = 0;
1612 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
1613 write_pulse_1(pbpctl_dev, ctrl_ext, counter, counter);
1615 wdt_time_left(pbpctl_dev);
1616 if (pbpctl_dev->wdt_status == WDT_STATUS_EN) {
1617 pbpctl_dev->wdt_status = 0;
1618 data_pulse(pbpctl_dev, counter);
1619 pbpctl_dev->wdt_status = WDT_STATUS_EN;
1620 pbpctl_dev->bypass_wdt_on_time = jiffies;
1623 data_pulse(pbpctl_dev, counter);
1629 int zero_set_fn(bpctl_dev_t *pbpctl_dev)
1631 uint32_t ctrl_ext = 0, ctrl_value = 0;
1635 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
1638 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1640 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1641 BPCTLI_CTRL_EXT_MCLK_DIR)
1644 (BPCTLI_CTRL_EXT_MCLK_DATA
1646 BPCTLI_CTRL_EXT_MDIO_DIR
1648 BPCTLI_CTRL_EXT_MDIO_DATA)));
1654 int pulse_get2_fn(bpctl_dev_t *pbpctl_dev)
1656 uint32_t ctrl_ext = 0, ctrl_value = 0;
1660 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
1661 printk("pulse_get_fn\n");
1662 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1663 ctrl_value = read_pulse_2(pbpctl_dev, ctrl_ext);
1664 printk("read:%d\n", ctrl_value);
1669 int pulse_get1_fn(bpctl_dev_t *pbpctl_dev)
1671 uint32_t ctrl_ext = 0, ctrl_value = 0;
1675 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
1677 printk("pulse_get_fn\n");
1679 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1680 ctrl_value = read_pulse_1(pbpctl_dev, ctrl_ext);
1681 printk("read:%d\n", ctrl_value);
1686 int gpio6_set_fn(bpctl_dev_t *pbpctl_dev)
1688 uint32_t ctrl_ext = 0;
1690 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1691 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ctrl_ext |
1692 BPCTLI_CTRL_EXT_SDP6_DIR |
1693 BPCTLI_CTRL_EXT_SDP6_DATA);
1697 int gpio7_set_fn(bpctl_dev_t *pbpctl_dev)
1699 uint32_t ctrl_ext = 0;
1701 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1702 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ctrl_ext |
1703 BPCTLI_CTRL_EXT_SDP7_DIR |
1704 BPCTLI_CTRL_EXT_SDP7_DATA);
1708 int gpio7_clear_fn(bpctl_dev_t *pbpctl_dev)
1710 uint32_t ctrl_ext = 0;
1712 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1713 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1714 BPCTLI_CTRL_EXT_SDP7_DIR) &
1715 ~BPCTLI_CTRL_EXT_SDP7_DATA));
1719 int gpio6_clear_fn(bpctl_dev_t *pbpctl_dev)
1721 uint32_t ctrl_ext = 0;
1723 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1724 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1725 BPCTLI_CTRL_EXT_SDP6_DIR) &
1726 ~BPCTLI_CTRL_EXT_SDP6_DATA));
1729 #endif /*BYPASS_DEBUG */
1731 static bpctl_dev_t *get_status_port_fn(bpctl_dev_t *pbpctl_dev)
1735 if (pbpctl_dev == NULL)
1738 if ((pbpctl_dev->func == 0) || (pbpctl_dev->func == 2)) {
1740 ((bpctl_dev_arr[idx_dev].pdev != NULL)
1741 && (idx_dev < device_num)); idx_dev++) {
1742 if ((bpctl_dev_arr[idx_dev].bus == pbpctl_dev->bus)
1743 && (bpctl_dev_arr[idx_dev].slot == pbpctl_dev->slot)
1744 && ((bpctl_dev_arr[idx_dev].func == 1)
1745 && (pbpctl_dev->func == 0))) {
1747 return &(bpctl_dev_arr[idx_dev]);
1749 if ((bpctl_dev_arr[idx_dev].bus == pbpctl_dev->bus) &&
1750 (bpctl_dev_arr[idx_dev].slot == pbpctl_dev->slot) &&
1751 ((bpctl_dev_arr[idx_dev].func == 3)
1752 && (pbpctl_dev->func == 2))) {
1754 return &(bpctl_dev_arr[idx_dev]);
1761 static bpctl_dev_t *get_master_port_fn(bpctl_dev_t *pbpctl_dev)
1765 if (pbpctl_dev == NULL)
1768 if ((pbpctl_dev->func == 1) || (pbpctl_dev->func == 3)) {
1770 ((bpctl_dev_arr[idx_dev].pdev != NULL)
1771 && (idx_dev < device_num)); idx_dev++) {
1772 if ((bpctl_dev_arr[idx_dev].bus == pbpctl_dev->bus)
1773 && (bpctl_dev_arr[idx_dev].slot == pbpctl_dev->slot)
1774 && ((bpctl_dev_arr[idx_dev].func == 0)
1775 && (pbpctl_dev->func == 1))) {
1777 return &(bpctl_dev_arr[idx_dev]);
1779 if ((bpctl_dev_arr[idx_dev].bus == pbpctl_dev->bus) &&
1780 (bpctl_dev_arr[idx_dev].slot == pbpctl_dev->slot) &&
1781 ((bpctl_dev_arr[idx_dev].func == 2)
1782 && (pbpctl_dev->func == 3))) {
1784 return &(bpctl_dev_arr[idx_dev]);
1791 /**************************************/
1792 /**************INTEL API***************/
1793 /**************************************/
1795 static void write_data_port_int(bpctl_dev_t *pbpctl_dev,
1796 unsigned char ctrl_value)
1800 value = BPCTL_READ_REG(pbpctl_dev, CTRL);
1801 /* Make SDP0 Pin Directonality to Output */
1802 value |= BPCTLI_CTRL_SDP0_DIR;
1803 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, value);
1805 value &= ~BPCTLI_CTRL_SDP0_DATA;
1806 value |= ((ctrl_value & 0x1) << BPCTLI_CTRL_SDP0_SHIFT);
1807 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, value);
1809 value = (BPCTL_READ_REG(pbpctl_dev, CTRL_EXT));
1810 /* Make SDP2 Pin Directonality to Output */
1811 value |= BPCTLI_CTRL_EXT_SDP6_DIR;
1812 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, value);
1814 value &= ~BPCTLI_CTRL_EXT_SDP6_DATA;
1815 value |= (((ctrl_value & 0x2) >> 1) << BPCTLI_CTRL_EXT_SDP6_SHIFT);
1816 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, value);
1820 static int write_data_int(bpctl_dev_t *pbpctl_dev, unsigned char value)
1822 bpctl_dev_t *pbpctl_dev_b = NULL;
1824 if (!(pbpctl_dev_b = get_status_port_fn(pbpctl_dev)))
1826 atomic_set(&pbpctl_dev->wdt_busy, 1);
1827 write_data_port_int(pbpctl_dev, value & 0x3);
1828 write_data_port_int(pbpctl_dev_b, ((value & 0xc) >> 2));
1829 atomic_set(&pbpctl_dev->wdt_busy, 0);
1834 static int wdt_pulse_int(bpctl_dev_t *pbpctl_dev)
1837 if ((atomic_read(&pbpctl_dev->wdt_busy)) == 1)
1840 if ((write_data_int(pbpctl_dev, RESET_WDT_INT)) < 0)
1842 msec_delay_bp(CMND_INTERVAL_INT);
1843 if ((write_data_int(pbpctl_dev, CMND_OFF_INT)) < 0)
1845 msec_delay_bp(CMND_INTERVAL_INT);
1847 if (pbpctl_dev->wdt_status == WDT_STATUS_EN)
1848 pbpctl_dev->bypass_wdt_on_time = jiffies;
1853 /*************************************/
1854 /************* COMMANDS **************/
1855 /*************************************/
1857 /* CMND_ON 0x4 (100)*/
1858 int cmnd_on(bpctl_dev_t *pbpctl_dev)
1860 int ret = BP_NOT_CAP;
1862 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
1863 if (INTEL_IF_SERIES(pbpctl_dev->subdevice))
1865 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER)
1866 write_data(pbpctl_dev, CMND_ON);
1868 data_pulse(pbpctl_dev, CMND_ON);
1874 /* CMND_OFF 0x2 (10)*/
1875 int cmnd_off(bpctl_dev_t *pbpctl_dev)
1877 int ret = BP_NOT_CAP;
1879 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
1880 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
1881 write_data_int(pbpctl_dev, CMND_OFF_INT);
1882 msec_delay_bp(CMND_INTERVAL_INT);
1883 } else if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER)
1884 write_data(pbpctl_dev, CMND_OFF);
1886 data_pulse(pbpctl_dev, CMND_OFF);
1892 /* BYPASS_ON (0xa)*/
1893 int bypass_on(bpctl_dev_t *pbpctl_dev)
1895 int ret = BP_NOT_CAP;
1897 if (pbpctl_dev->bp_caps & BP_CAP) {
1898 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
1899 write_data_int(pbpctl_dev, BYPASS_ON_INT);
1900 msec_delay_bp(BYPASS_DELAY_INT);
1901 pbpctl_dev->bp_status_un = 0;
1902 } else if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
1903 write_data(pbpctl_dev, BYPASS_ON);
1904 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER)
1905 msec_delay_bp(LATCH_DELAY);
1907 data_pulse(pbpctl_dev, BYPASS_ON);
1913 /* BYPASS_OFF (0x8 111)*/
1914 int bypass_off(bpctl_dev_t *pbpctl_dev)
1916 int ret = BP_NOT_CAP;
1918 if (pbpctl_dev->bp_caps & BP_CAP) {
1919 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
1920 write_data_int(pbpctl_dev, DIS_BYPASS_CAP_INT);
1921 msec_delay_bp(BYPASS_DELAY_INT);
1922 write_data_int(pbpctl_dev, PWROFF_BYPASS_ON_INT);
1923 msec_delay_bp(BYPASS_DELAY_INT);
1924 pbpctl_dev->bp_status_un = 0;
1925 } else if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
1926 write_data(pbpctl_dev, BYPASS_OFF);
1927 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER)
1928 msec_delay_bp(LATCH_DELAY);
1930 data_pulse(pbpctl_dev, BYPASS_OFF);
1937 int tap_off(bpctl_dev_t *pbpctl_dev)
1939 int ret = BP_NOT_CAP;
1940 if ((pbpctl_dev->bp_caps & TAP_CAP)
1941 && (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER)) {
1942 write_data(pbpctl_dev, TAP_OFF);
1943 msec_delay_bp(LATCH_DELAY);
1950 int tap_on(bpctl_dev_t *pbpctl_dev)
1952 int ret = BP_NOT_CAP;
1953 if ((pbpctl_dev->bp_caps & TAP_CAP)
1954 && (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER)) {
1955 write_data(pbpctl_dev, TAP_ON);
1956 msec_delay_bp(LATCH_DELAY);
1963 int disc_off(bpctl_dev_t *pbpctl_dev)
1966 if ((pbpctl_dev->bp_caps & DISC_CAP) && (pbpctl_dev->bp_ext_ver >= 0x8)) {
1967 write_data(pbpctl_dev, DISC_OFF);
1968 msec_delay_bp(LATCH_DELAY);
1975 int disc_on(bpctl_dev_t *pbpctl_dev)
1978 if ((pbpctl_dev->bp_caps & DISC_CAP) && (pbpctl_dev->bp_ext_ver >= 0x8)) {
1979 write_data(pbpctl_dev, /*DISC_ON */ 0x85);
1980 msec_delay_bp(LATCH_DELAY);
1987 int disc_port_on(bpctl_dev_t *pbpctl_dev)
1990 bpctl_dev_t *pbpctl_dev_m;
1992 if ((is_bypass_fn(pbpctl_dev)) == 1)
1993 pbpctl_dev_m = pbpctl_dev;
1995 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
1996 if (pbpctl_dev_m == NULL)
1999 if (pbpctl_dev_m->bp_caps_ex & DISC_PORT_CAP_EX) {
2000 if (is_bypass_fn(pbpctl_dev) == 1) {
2002 write_data(pbpctl_dev_m, TX_DISA);
2005 write_data(pbpctl_dev_m, TX_DISB);
2008 msec_delay_bp(LATCH_DELAY);
2015 int disc_port_off(bpctl_dev_t *pbpctl_dev)
2018 bpctl_dev_t *pbpctl_dev_m;
2020 if ((is_bypass_fn(pbpctl_dev)) == 1)
2021 pbpctl_dev_m = pbpctl_dev;
2023 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
2024 if (pbpctl_dev_m == NULL)
2027 if (pbpctl_dev_m->bp_caps_ex & DISC_PORT_CAP_EX) {
2028 if (is_bypass_fn(pbpctl_dev) == 1)
2029 write_data(pbpctl_dev_m, TX_ENA);
2031 write_data(pbpctl_dev_m, TX_ENB);
2033 msec_delay_bp(LATCH_DELAY);
2039 /*TWO_PORT_LINK_HW_EN (0xe)*/
2040 int tpl_hw_on(bpctl_dev_t *pbpctl_dev)
2042 int ret = 0, ctrl = 0;
2043 bpctl_dev_t *pbpctl_dev_b = NULL;
2045 if (!(pbpctl_dev_b = get_status_port_fn(pbpctl_dev)))
2048 if (pbpctl_dev->bp_caps_ex & TPL2_CAP_EX) {
2049 cmnd_on(pbpctl_dev);
2050 write_data(pbpctl_dev, TPL2_ON);
2051 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2052 cmnd_off(pbpctl_dev);
2056 if (TPL_IF_SERIES(pbpctl_dev->subdevice)) {
2057 ctrl = BPCTL_READ_REG(pbpctl_dev_b, CTRL);
2058 BPCTL_BP_WRITE_REG(pbpctl_dev_b, CTRL,
2059 ((ctrl | BPCTLI_CTRL_SWDPIO0) &
2060 ~BPCTLI_CTRL_SWDPIN0));
2066 /*TWO_PORT_LINK_HW_DIS (0xc)*/
2067 int tpl_hw_off(bpctl_dev_t *pbpctl_dev)
2069 int ret = 0, ctrl = 0;
2070 bpctl_dev_t *pbpctl_dev_b = NULL;
2072 if (!(pbpctl_dev_b = get_status_port_fn(pbpctl_dev)))
2074 if (pbpctl_dev->bp_caps_ex & TPL2_CAP_EX) {
2075 cmnd_on(pbpctl_dev);
2076 write_data(pbpctl_dev, TPL2_OFF);
2077 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2078 cmnd_off(pbpctl_dev);
2081 if (TPL_IF_SERIES(pbpctl_dev->subdevice)) {
2082 ctrl = BPCTL_READ_REG(pbpctl_dev_b, CTRL);
2083 BPCTL_BP_WRITE_REG(pbpctl_dev_b, CTRL,
2084 (ctrl | BPCTLI_CTRL_SWDPIO0 |
2085 BPCTLI_CTRL_SWDPIN0));
2091 /* WDT_OFF (0x6 110)*/
2092 int wdt_off(bpctl_dev_t *pbpctl_dev)
2094 int ret = BP_NOT_CAP;
2096 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
2097 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
2098 bypass_off(pbpctl_dev);
2099 } else if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER)
2100 write_data(pbpctl_dev, WDT_OFF);
2102 data_pulse(pbpctl_dev, WDT_OFF);
2103 pbpctl_dev->wdt_status = WDT_STATUS_DIS;
2113 wdt_val_array[] = { 1000, 1500, 2000, 3000, 4000, 8000, 16000, 32000, 0 };
2115 int wdt_on(bpctl_dev_t *pbpctl_dev, unsigned int timeout)
2118 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
2119 unsigned int pulse = 0, temp_value = 0, temp_cnt = 0;
2120 pbpctl_dev->wdt_status = 0;
2122 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
2123 for (; wdt_val_array[temp_cnt]; temp_cnt++)
2124 if (timeout <= wdt_val_array[temp_cnt])
2127 if (!wdt_val_array[temp_cnt])
2130 timeout = wdt_val_array[temp_cnt];
2133 write_data_int(pbpctl_dev, DIS_BYPASS_CAP_INT);
2134 msec_delay_bp(BYPASS_DELAY_INT);
2135 pbpctl_dev->bp_status_un = 0;
2136 write_data_int(pbpctl_dev, temp_cnt);
2137 pbpctl_dev->bypass_wdt_on_time = jiffies;
2138 msec_delay_bp(CMND_INTERVAL_INT);
2139 pbpctl_dev->bypass_timer_interval = timeout;
2143 TIMEOUT_UNIT ? TIMEOUT_UNIT : (timeout >
2147 temp_value = timeout / 100;
2148 while ((temp_value >>= 1))
2150 if (timeout > ((1 << temp_cnt) * 100))
2152 pbpctl_dev->bypass_wdt_on_time = jiffies;
2153 pulse = (WDT_ON | temp_cnt);
2154 if (pbpctl_dev->bp_ext_ver == OLD_IF_VER)
2155 data_pulse(pbpctl_dev, pulse);
2157 write_data(pbpctl_dev, pulse);
2158 pbpctl_dev->bypass_timer_interval =
2159 (1 << temp_cnt) * 100;
2161 pbpctl_dev->wdt_status = WDT_STATUS_EN;
2167 void bp75_put_hw_semaphore_generic(bpctl_dev_t *pbpctl_dev)
2171 swsm = BPCTL_READ_REG(pbpctl_dev, SWSM);
2173 swsm &= ~(BPCTLI_SWSM_SMBI | BPCTLI_SWSM_SWESMBI);
2175 BPCTL_WRITE_REG(pbpctl_dev, SWSM, swsm);
2178 s32 bp75_get_hw_semaphore_generic(bpctl_dev_t *pbpctl_dev)
2182 s32 timeout = 8192 + 1;
2185 /* Get the SW semaphore */
2186 while (i < timeout) {
2187 swsm = BPCTL_READ_REG(pbpctl_dev, SWSM);
2188 if (!(swsm & BPCTLI_SWSM_SMBI))
2197 ("bpctl_mod: Driver can't access device - SMBI bit is set.\n");
2202 /* Get the FW semaphore. */
2203 for (i = 0; i < timeout; i++) {
2204 swsm = BPCTL_READ_REG(pbpctl_dev, SWSM);
2205 BPCTL_WRITE_REG(pbpctl_dev, SWSM, swsm | BPCTLI_SWSM_SWESMBI);
2207 /* Semaphore acquired if bit latched */
2208 if (BPCTL_READ_REG(pbpctl_dev, SWSM) & BPCTLI_SWSM_SWESMBI)
2215 /* Release semaphores */
2216 bp75_put_hw_semaphore_generic(pbpctl_dev);
2217 printk("bpctl_mod: Driver can't access the NVM\n");
2226 static void bp75_release_phy(bpctl_dev_t *pbpctl_dev)
2228 u16 mask = BPCTLI_SWFW_PHY0_SM;
2231 if ((pbpctl_dev->func == 1) || (pbpctl_dev->func == 3))
2232 mask = BPCTLI_SWFW_PHY1_SM;
2234 while (bp75_get_hw_semaphore_generic(pbpctl_dev) != 0) ;
2237 swfw_sync = BPCTL_READ_REG(pbpctl_dev, SW_FW_SYNC);
2239 BPCTL_WRITE_REG(pbpctl_dev, SW_FW_SYNC, swfw_sync);
2241 bp75_put_hw_semaphore_generic(pbpctl_dev);
2244 static s32 bp75_acquire_phy(bpctl_dev_t *pbpctl_dev)
2246 u16 mask = BPCTLI_SWFW_PHY0_SM;
2251 s32 i = 0, timeout = 200;
2253 if ((pbpctl_dev->func == 1) || (pbpctl_dev->func == 3))
2254 mask = BPCTLI_SWFW_PHY1_SM;
2257 fwmask = mask << 16;
2259 while (i < timeout) {
2260 if (bp75_get_hw_semaphore_generic(pbpctl_dev)) {
2265 swfw_sync = BPCTL_READ_REG(pbpctl_dev, SW_FW_SYNC);
2266 if (!(swfw_sync & (fwmask | swmask)))
2269 bp75_put_hw_semaphore_generic(pbpctl_dev);
2276 ("bpctl_mod: Driver can't access resource, SW_FW_SYNC timeout.\n");
2281 swfw_sync |= swmask;
2282 BPCTL_WRITE_REG(pbpctl_dev, SW_FW_SYNC, swfw_sync);
2284 bp75_put_hw_semaphore_generic(pbpctl_dev);
2290 s32 bp75_read_phy_reg_mdic(bpctl_dev_t *pbpctl_dev, u32 offset, u16 *data)
2296 mdic = ((offset << BPCTLI_MDIC_REG_SHIFT) |
2297 (phy_addr << BPCTLI_MDIC_PHY_SHIFT) | (BPCTLI_MDIC_OP_READ));
2299 BPCTL_WRITE_REG(pbpctl_dev, MDIC, mdic);
2301 for (i = 0; i < (BPCTLI_GEN_POLL_TIMEOUT * 3); i++) {
2303 mdic = BPCTL_READ_REG(pbpctl_dev, MDIC);
2304 if (mdic & BPCTLI_MDIC_READY)
2307 if (!(mdic & BPCTLI_MDIC_READY)) {
2308 printk("bpctl_mod: MDI Read did not complete\n");
2312 if (mdic & BPCTLI_MDIC_ERROR) {
2313 printk("bpctl_mod: MDI Error\n");
2323 s32 bp75_write_phy_reg_mdic(bpctl_dev_t *pbpctl_dev, u32 offset, u16 data)
2329 mdic = (((u32) data) |
2330 (offset << BPCTLI_MDIC_REG_SHIFT) |
2331 (phy_addr << BPCTLI_MDIC_PHY_SHIFT) | (BPCTLI_MDIC_OP_WRITE));
2333 BPCTL_WRITE_REG(pbpctl_dev, MDIC, mdic);
2335 for (i = 0; i < (BPCTLI_GEN_POLL_TIMEOUT * 3); i++) {
2337 mdic = BPCTL_READ_REG(pbpctl_dev, MDIC);
2338 if (mdic & BPCTLI_MDIC_READY)
2341 if (!(mdic & BPCTLI_MDIC_READY)) {
2342 printk("bpctl_mod: MDI Write did not complete\n");
2346 if (mdic & BPCTLI_MDIC_ERROR) {
2347 printk("bpctl_mod: MDI Error\n");
2356 static s32 bp75_read_phy_reg(bpctl_dev_t *pbpctl_dev, u32 offset, u16 *data)
2360 ret_val = bp75_acquire_phy(pbpctl_dev);
2364 if (offset > BPCTLI_MAX_PHY_MULTI_PAGE_REG) {
2365 ret_val = bp75_write_phy_reg_mdic(pbpctl_dev,
2366 BPCTLI_IGP01E1000_PHY_PAGE_SELECT,
2373 bp75_read_phy_reg_mdic(pbpctl_dev,
2374 BPCTLI_MAX_PHY_REG_ADDRESS & offset, data);
2377 bp75_release_phy(pbpctl_dev);
2382 static s32 bp75_write_phy_reg(bpctl_dev_t *pbpctl_dev, u32 offset, u16 data)
2386 ret_val = bp75_acquire_phy(pbpctl_dev);
2390 if (offset > BPCTLI_MAX_PHY_MULTI_PAGE_REG) {
2391 ret_val = bp75_write_phy_reg_mdic(pbpctl_dev,
2392 BPCTLI_IGP01E1000_PHY_PAGE_SELECT,
2399 bp75_write_phy_reg_mdic(pbpctl_dev,
2400 BPCTLI_MAX_PHY_REG_ADDRESS & offset, data);
2403 bp75_release_phy(pbpctl_dev);
2409 /* SET_TX (non-Bypass command :)) */
2410 static int set_tx(bpctl_dev_t *pbpctl_dev, int tx_state)
2412 int ret = 0, ctrl = 0;
2413 bpctl_dev_t *pbpctl_dev_m;
2414 if ((is_bypass_fn(pbpctl_dev)) == 1)
2415 pbpctl_dev_m = pbpctl_dev;
2417 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
2418 if (pbpctl_dev_m == NULL)
2420 if (pbpctl_dev_m->bp_caps_ex & DISC_PORT_CAP_EX) {
2421 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL);
2423 if (pbpctl_dev->bp_540) {
2424 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
2425 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2426 (ctrl | BP10G_SDP1_DIR |
2430 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
2431 (ctrl | BPCTLI_CTRL_SDP1_DIR
2432 | BPCTLI_CTRL_SWDPIN1));
2435 if (pbpctl_dev->bp_540) {
2436 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
2437 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2438 ((ctrl | BP10G_SDP1_DIR) &
2441 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
2443 BPCTLI_CTRL_SDP1_DIR) &
2444 ~BPCTLI_CTRL_SWDPIN1));
2449 } else if (pbpctl_dev->bp_caps & TX_CTL_CAP) {
2450 if (PEG5_IF_SERIES(pbpctl_dev->subdevice)) {
2455 bp75_read_phy_reg(pbpctl_dev,
2458 if (mii_reg & BPCTLI_MII_CR_POWER_DOWN) {
2464 ~BPCTLI_MII_CR_POWER_DOWN);
2471 bp75_read_phy_reg(pbpctl_dev,
2475 mii_reg |= BPCTLI_MII_CR_POWER_DOWN;
2477 bp75_write_phy_reg(pbpctl_dev,
2484 if (pbpctl_dev->bp_fiber5) {
2485 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
2487 } else if (pbpctl_dev->bp_10gb)
2488 ctrl = BP10GB_READ_REG(pbpctl_dev, MISC_REG_GPIO);
2490 else if (!pbpctl_dev->bp_10g)
2491 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL);
2493 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
2496 if (pbpctl_dev->bp_10g9) {
2497 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2498 (ctrl | BP10G_SDP3_DATA |
2501 } else if (pbpctl_dev->bp_fiber5) {
2502 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
2504 BPCTLI_CTRL_EXT_SDP6_DIR |
2505 BPCTLI_CTRL_EXT_SDP6_DATA));
2507 } else if (pbpctl_dev->bp_10gb) {
2508 if ((pbpctl_dev->func == 1)
2509 || (pbpctl_dev->func == 3))
2510 BP10GB_WRITE_REG(pbpctl_dev,
2513 BP10GB_GPIO0_SET_P1) &
2514 ~(BP10GB_GPIO0_CLR_P1 |
2515 BP10GB_GPIO0_OE_P1));
2517 BP10GB_WRITE_REG(pbpctl_dev,
2520 BP10GB_GPIO0_OE_P0 |
2521 BP10GB_GPIO0_SET_P0));
2523 } else if (pbpctl_dev->bp_i80) {
2524 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
2525 (ctrl | BPCTLI_CTRL_SDP1_DIR
2526 | BPCTLI_CTRL_SWDPIN1));
2528 } else if (pbpctl_dev->bp_540) {
2529 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
2530 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2531 (ctrl | BP10G_SDP1_DIR |
2536 else if (!pbpctl_dev->bp_10g)
2537 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
2538 (ctrl | BPCTLI_CTRL_SWDPIO0 |
2539 BPCTLI_CTRL_SWDPIN0));
2542 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2543 (ctrl | BP10G_SDP0_DATA |
2547 if (pbpctl_dev->bp_10g9) {
2548 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2549 ((ctrl | BP10G_SDP3_DIR) &
2552 } else if (pbpctl_dev->bp_fiber5) {
2553 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
2555 BPCTLI_CTRL_EXT_SDP6_DIR) &
2556 ~BPCTLI_CTRL_EXT_SDP6_DATA));
2558 } else if (pbpctl_dev->bp_10gb) {
2559 if ((bpctl_dev_arr->func == 1)
2560 || (bpctl_dev_arr->func == 3))
2561 BP10GB_WRITE_REG(pbpctl_dev,
2564 BP10GB_GPIO0_CLR_P1) &
2565 ~(BP10GB_GPIO0_SET_P1 |
2566 BP10GB_GPIO0_OE_P1));
2568 BP10GB_WRITE_REG(pbpctl_dev,
2571 BP10GB_GPIO0_OE_P0 |
2572 BP10GB_GPIO0_CLR_P0));
2574 } else if (pbpctl_dev->bp_i80) {
2575 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
2577 BPCTLI_CTRL_SDP1_DIR) &
2578 ~BPCTLI_CTRL_SWDPIN1));
2579 } else if (pbpctl_dev->bp_540) {
2580 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
2581 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2582 ((ctrl | BP10G_SDP1_DIR) &
2586 else if (!pbpctl_dev->bp_10g) {
2587 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
2588 ((ctrl | BPCTLI_CTRL_SWDPIO0)
2589 & ~BPCTLI_CTRL_SWDPIN0));
2590 if (!PEGF_IF_SERIES(pbpctl_dev->subdevice)) {
2591 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
2594 (BPCTLI_CTRL_SDP0_DATA
2596 BPCTLI_CTRL_SDP0_DIR)));
2599 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2600 ((ctrl | BP10G_SDP0_DIR) &
2611 /* SET_FORCE_LINK (non-Bypass command :)) */
2612 static int set_bp_force_link(bpctl_dev_t *pbpctl_dev, int tx_state)
2614 int ret = 0, ctrl = 0;
2616 if (DBI_IF_SERIES(pbpctl_dev->subdevice)) {
2618 if ((pbpctl_dev->bp_10g) || (pbpctl_dev->bp_10g9)) {
2620 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL);
2622 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2623 ctrl & ~BP10G_SDP1_DIR);
2625 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2626 ((ctrl | BP10G_SDP1_DIR) &
2635 /*RESET_CONT 0x20 */
2636 int reset_cont(bpctl_dev_t *pbpctl_dev)
2638 int ret = BP_NOT_CAP;
2640 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
2641 if (INTEL_IF_SERIES(pbpctl_dev->subdevice))
2643 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER)
2644 write_data(pbpctl_dev, RESET_CONT);
2646 data_pulse(pbpctl_dev, RESET_CONT);
2652 /*DIS_BYPASS_CAP 0x22 */
2653 int dis_bypass_cap(bpctl_dev_t *pbpctl_dev)
2656 if (pbpctl_dev->bp_caps & BP_DIS_CAP) {
2657 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
2658 write_data_int(pbpctl_dev, DIS_BYPASS_CAP_INT);
2659 msec_delay_bp(BYPASS_DELAY_INT);
2661 write_data(pbpctl_dev, BYPASS_OFF);
2662 msec_delay_bp(LATCH_DELAY);
2663 write_data(pbpctl_dev, DIS_BYPASS_CAP);
2664 msec_delay_bp(BYPASS_CAP_DELAY);
2671 /*EN_BYPASS_CAP 0x24 */
2672 int en_bypass_cap(bpctl_dev_t *pbpctl_dev)
2674 if (pbpctl_dev->bp_caps & BP_DIS_CAP) {
2675 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
2676 write_data_int(pbpctl_dev, PWROFF_BYPASS_ON_INT);
2677 msec_delay_bp(BYPASS_DELAY_INT);
2679 write_data(pbpctl_dev, EN_BYPASS_CAP);
2680 msec_delay_bp(BYPASS_CAP_DELAY);
2687 /* BYPASS_STATE_PWRON 0x26*/
2688 int bypass_state_pwron(bpctl_dev_t *pbpctl_dev)
2690 if (pbpctl_dev->bp_caps & BP_PWUP_CTL_CAP) {
2691 write_data(pbpctl_dev, BYPASS_STATE_PWRON);
2692 if (pbpctl_dev->bp_ext_ver == PXG2BPI_VER)
2693 msec_delay_bp(DFLT_PWRON_DELAY);
2695 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2701 /* NORMAL_STATE_PWRON 0x28*/
2702 int normal_state_pwron(bpctl_dev_t *pbpctl_dev)
2704 if ((pbpctl_dev->bp_caps & BP_PWUP_CTL_CAP)
2705 || (pbpctl_dev->bp_caps & TAP_PWUP_CTL_CAP)) {
2706 write_data(pbpctl_dev, NORMAL_STATE_PWRON);
2707 if (pbpctl_dev->bp_ext_ver == PXG2BPI_VER)
2708 msec_delay_bp(DFLT_PWRON_DELAY);
2710 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2716 /* BYPASS_STATE_PWROFF 0x27*/
2717 int bypass_state_pwroff(bpctl_dev_t *pbpctl_dev)
2719 if (pbpctl_dev->bp_caps & BP_PWOFF_CTL_CAP) {
2720 write_data(pbpctl_dev, BYPASS_STATE_PWROFF);
2721 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2727 /* NORMAL_STATE_PWROFF 0x29*/
2728 int normal_state_pwroff(bpctl_dev_t *pbpctl_dev)
2730 if ((pbpctl_dev->bp_caps & BP_PWOFF_CTL_CAP)) {
2731 write_data(pbpctl_dev, NORMAL_STATE_PWROFF);
2732 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2738 /*TAP_STATE_PWRON 0x2a*/
2739 int tap_state_pwron(bpctl_dev_t *pbpctl_dev)
2741 if (pbpctl_dev->bp_caps & TAP_PWUP_CTL_CAP) {
2742 write_data(pbpctl_dev, TAP_STATE_PWRON);
2743 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2749 /*DIS_TAP_CAP 0x2c*/
2750 int dis_tap_cap(bpctl_dev_t *pbpctl_dev)
2752 if (pbpctl_dev->bp_caps & TAP_DIS_CAP) {
2753 write_data(pbpctl_dev, DIS_TAP_CAP);
2754 msec_delay_bp(BYPASS_CAP_DELAY);
2761 int en_tap_cap(bpctl_dev_t *pbpctl_dev)
2763 if (pbpctl_dev->bp_caps & TAP_DIS_CAP) {
2764 write_data(pbpctl_dev, EN_TAP_CAP);
2765 msec_delay_bp(BYPASS_CAP_DELAY);
2771 /*DISC_STATE_PWRON 0x2a*/
2772 int disc_state_pwron(bpctl_dev_t *pbpctl_dev)
2774 if (pbpctl_dev->bp_caps & DISC_PWUP_CTL_CAP) {
2775 if (pbpctl_dev->bp_ext_ver >= 0x8) {
2776 write_data(pbpctl_dev, DISC_STATE_PWRON);
2777 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2784 /*DIS_DISC_CAP 0x2c*/
2785 int dis_disc_cap(bpctl_dev_t *pbpctl_dev)
2787 if (pbpctl_dev->bp_caps & DISC_DIS_CAP) {
2788 if (pbpctl_dev->bp_ext_ver >= 0x8) {
2789 write_data(pbpctl_dev, DIS_DISC_CAP);
2790 msec_delay_bp(BYPASS_CAP_DELAY);
2797 /*DISC_STATE_PWRON 0x2a*/
2798 int disc_port_state_pwron(bpctl_dev_t *pbpctl_dev)
2801 bpctl_dev_t *pbpctl_dev_m;
2805 if ((is_bypass_fn(pbpctl_dev)) == 1)
2806 pbpctl_dev_m = pbpctl_dev;
2808 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
2809 if (pbpctl_dev_m == NULL)
2812 if (pbpctl_dev_m->bp_caps_ex & DISC_PORT_CAP_EX) {
2813 if (is_bypass_fn(pbpctl_dev) == 1)
2814 write_data(pbpctl_dev_m, TX_DISA_PWRUP);
2816 write_data(pbpctl_dev_m, TX_DISB_PWRUP);
2818 msec_delay_bp(LATCH_DELAY);
2824 int normal_port_state_pwron(bpctl_dev_t *pbpctl_dev)
2827 bpctl_dev_t *pbpctl_dev_m;
2830 if ((is_bypass_fn(pbpctl_dev)) == 1)
2831 pbpctl_dev_m = pbpctl_dev;
2833 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
2834 if (pbpctl_dev_m == NULL)
2837 if (pbpctl_dev_m->bp_caps_ex & DISC_PORT_CAP_EX) {
2838 if (is_bypass_fn(pbpctl_dev) == 1)
2839 write_data(pbpctl_dev_m, TX_ENA_PWRUP);
2841 write_data(pbpctl_dev_m, TX_ENB_PWRUP);
2843 msec_delay_bp(LATCH_DELAY);
2850 int en_disc_cap(bpctl_dev_t *pbpctl_dev)
2852 if (pbpctl_dev->bp_caps & DISC_DIS_CAP) {
2853 if (pbpctl_dev->bp_ext_ver >= 0x8) {
2854 write_data(pbpctl_dev, EN_DISC_CAP);
2855 msec_delay_bp(BYPASS_CAP_DELAY);
2862 int std_nic_on(bpctl_dev_t *pbpctl_dev)
2865 if (pbpctl_dev->bp_caps & STD_NIC_CAP) {
2867 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
2868 write_data_int(pbpctl_dev, DIS_BYPASS_CAP_INT);
2869 msec_delay_bp(BYPASS_DELAY_INT);
2870 pbpctl_dev->bp_status_un = 0;
2874 if (pbpctl_dev->bp_ext_ver >= 0x8) {
2875 write_data(pbpctl_dev, STD_NIC_ON);
2876 msec_delay_bp(BYPASS_CAP_DELAY);
2881 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
2882 wdt_off(pbpctl_dev);
2884 if (pbpctl_dev->bp_caps & BP_CAP) {
2885 write_data(pbpctl_dev, BYPASS_OFF);
2886 msec_delay_bp(LATCH_DELAY);
2889 if (pbpctl_dev->bp_caps & TAP_CAP) {
2890 write_data(pbpctl_dev, TAP_OFF);
2891 msec_delay_bp(LATCH_DELAY);
2894 write_data(pbpctl_dev, NORMAL_STATE_PWRON);
2895 if (pbpctl_dev->bp_ext_ver == PXG2BPI_VER)
2896 msec_delay_bp(DFLT_PWRON_DELAY);
2898 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2900 if (pbpctl_dev->bp_caps & BP_DIS_CAP) {
2901 write_data(pbpctl_dev, DIS_BYPASS_CAP);
2902 msec_delay_bp(BYPASS_CAP_DELAY);
2905 if (pbpctl_dev->bp_caps & TAP_DIS_CAP) {
2906 write_data(pbpctl_dev, DIS_TAP_CAP);
2907 msec_delay_bp(BYPASS_CAP_DELAY);
2916 int std_nic_off(bpctl_dev_t *pbpctl_dev)
2919 if (pbpctl_dev->bp_caps & STD_NIC_CAP) {
2920 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
2921 write_data_int(pbpctl_dev, PWROFF_BYPASS_ON_INT);
2922 msec_delay_bp(BYPASS_DELAY_INT);
2925 if (pbpctl_dev->bp_ext_ver >= 0x8) {
2926 write_data(pbpctl_dev, STD_NIC_OFF);
2927 msec_delay_bp(BYPASS_CAP_DELAY);
2932 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
2934 if (pbpctl_dev->bp_caps & TAP_PWUP_CTL_CAP) {
2935 write_data(pbpctl_dev, TAP_STATE_PWRON);
2936 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2939 if (pbpctl_dev->bp_caps & BP_PWUP_CTL_CAP) {
2940 write_data(pbpctl_dev, BYPASS_STATE_PWRON);
2941 if (pbpctl_dev->bp_ext_ver > PXG2BPI_VER)
2942 msec_delay_bp(LATCH_DELAY +
2945 msec_delay_bp(DFLT_PWRON_DELAY);
2948 if (pbpctl_dev->bp_caps & TAP_DIS_CAP) {
2949 write_data(pbpctl_dev, EN_TAP_CAP);
2950 msec_delay_bp(BYPASS_CAP_DELAY);
2952 if (pbpctl_dev->bp_caps & DISC_DIS_CAP) {
2953 write_data(pbpctl_dev, EN_DISC_CAP);
2954 msec_delay_bp(BYPASS_CAP_DELAY);
2957 if (pbpctl_dev->bp_caps & BP_DIS_CAP) {
2958 write_data(pbpctl_dev, EN_BYPASS_CAP);
2959 msec_delay_bp(BYPASS_CAP_DELAY);
2968 int wdt_time_left(bpctl_dev_t *pbpctl_dev)
2971 /* unsigned long curr_time=((long long)(jiffies*1000))/HZ, delta_time=0,wdt_on_time=((long long)(pbpctl_dev->bypass_wdt_on_time*1000))/HZ; */
2972 unsigned long curr_time = jiffies, delta_time = 0, wdt_on_time =
2973 pbpctl_dev->bypass_wdt_on_time, delta_time_msec = 0;
2976 switch (pbpctl_dev->wdt_status) {
2977 case WDT_STATUS_DIS:
2983 wdt_on_time) ? (curr_time - wdt_on_time) : (~wdt_on_time +
2985 delta_time_msec = jiffies_to_msecs(delta_time);
2986 time_left = pbpctl_dev->bypass_timer_interval - delta_time_msec;
2987 if (time_left < 0) {
2989 pbpctl_dev->wdt_status = WDT_STATUS_EXP;
2992 case WDT_STATUS_EXP:
3000 static int wdt_timer(bpctl_dev_t *pbpctl_dev, int *time_left)
3003 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
3005 if (pbpctl_dev->wdt_status == WDT_STATUS_UNKNOWN)
3008 *time_left = wdt_time_left(pbpctl_dev);
3016 static int wdt_timer_reload(bpctl_dev_t *pbpctl_dev)
3021 if ((pbpctl_dev->bp_caps & WD_CTL_CAP) &&
3022 (pbpctl_dev->wdt_status != WDT_STATUS_UNKNOWN)) {
3023 if (pbpctl_dev->wdt_status == WDT_STATUS_DIS)
3025 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER)
3026 ret = wdt_pulse(pbpctl_dev);
3027 else if (INTEL_IF_SERIES(pbpctl_dev->subdevice))
3028 ret = wdt_pulse_int(pbpctl_dev);
3030 ret = send_wdt_pulse(pbpctl_dev);
3032 mod_timer(&pbpctl_dev->bp_timer, jiffies+1);*/
3038 static void wd_reset_timer(unsigned long param)
3040 bpctl_dev_t *pbpctl_dev = (bpctl_dev_t *) param;
3042 struct sk_buff *skb_tmp;
3045 if ((pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) &&
3046 ((atomic_read(&pbpctl_dev->wdt_busy)) == 1)) {
3047 mod_timer(&pbpctl_dev->bp_timer, jiffies + 1);
3052 if (pbpctl_dev->bp_self_test_flag == 1) {
3053 skb_tmp = dev_alloc_skb(BPTEST_DATA_LEN + 2);
3054 if ((skb_tmp) && (pbpctl_dev->ndev) && (pbpctl_dev->bp_tx_data)) {
3055 memcpy(skb_put(skb_tmp, BPTEST_DATA_LEN),
3056 pbpctl_dev->bp_tx_data, BPTEST_DATA_LEN);
3057 skb_tmp->dev = pbpctl_dev->ndev;
3059 eth_type_trans(skb_tmp, pbpctl_dev->ndev);
3060 skb_tmp->ip_summed = CHECKSUM_UNNECESSARY;
3061 netif_receive_skb(skb_tmp);
3062 goto bp_timer_reload;
3068 wdt_timer_reload(pbpctl_dev);
3072 if (pbpctl_dev->reset_time) {
3073 mod_timer(&pbpctl_dev->bp_timer,
3074 jiffies + (HZ * pbpctl_dev->reset_time) / 1000);
3078 /*WAIT_AT_PWRUP 0x80 */
3079 int bp_wait_at_pwup_en(bpctl_dev_t *pbpctl_dev)
3082 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3083 if (pbpctl_dev->bp_ext_ver >= BP_FW_EXT_VER8) {
3084 write_data(pbpctl_dev, BP_WAIT_AT_PWUP_EN);
3085 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
3093 /*DIS_WAIT_AT_PWRUP 0x81 */
3094 int bp_wait_at_pwup_dis(bpctl_dev_t *pbpctl_dev)
3097 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3099 if (pbpctl_dev->bp_ext_ver >= BP_FW_EXT_VER8) {
3100 write_data(pbpctl_dev, BP_WAIT_AT_PWUP_DIS);
3101 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
3109 /*EN_HW_RESET 0x82 */
3111 int bp_hw_reset_en(bpctl_dev_t *pbpctl_dev)
3114 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3115 if (pbpctl_dev->bp_ext_ver >= BP_FW_EXT_VER8) {
3116 write_data(pbpctl_dev, BP_HW_RESET_EN);
3117 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
3125 /*DIS_HW_RESET 0x83 */
3127 int bp_hw_reset_dis(bpctl_dev_t *pbpctl_dev)
3130 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3131 if (pbpctl_dev->bp_ext_ver >= BP_FW_EXT_VER8) {
3132 write_data(pbpctl_dev, BP_HW_RESET_DIS);
3133 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
3142 int wdt_exp_mode(bpctl_dev_t *pbpctl_dev, int mode)
3144 uint32_t status_reg = 0, status_reg1 = 0;
3146 if ((pbpctl_dev->bp_caps & (TAP_STATUS_CAP | DISC_CAP)) &&
3147 (pbpctl_dev->bp_caps & BP_CAP)) {
3148 if (pbpctl_dev->bp_ext_ver >= PXE2TBPI_VER) {
3150 if ((pbpctl_dev->bp_ext_ver >= 0x8) &&
3151 (mode == 2) && (pbpctl_dev->bp_caps & DISC_CAP)) {
3153 read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR);
3154 if (!(status_reg1 & WDTE_DISC_BPN_MASK))
3155 write_reg(pbpctl_dev,
3158 STATUS_DISC_REG_ADDR);
3162 status_reg = read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR);
3164 if ((mode == 0) && (pbpctl_dev->bp_caps & BP_CAP)) {
3165 if (pbpctl_dev->bp_ext_ver >= 0x8) {
3167 read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR);
3168 if (status_reg1 & WDTE_DISC_BPN_MASK)
3169 write_reg(pbpctl_dev,
3171 ~WDTE_DISC_BPN_MASK,
3172 STATUS_DISC_REG_ADDR);
3174 if (status_reg & WDTE_TAP_BPN_MASK)
3175 write_reg(pbpctl_dev,
3176 status_reg & ~WDTE_TAP_BPN_MASK,
3177 STATUS_TAP_REG_ADDR);
3180 } else if ((mode == 1) && (pbpctl_dev->bp_caps & TAP_CAP)) {
3181 if (!(status_reg & WDTE_TAP_BPN_MASK))
3182 write_reg(pbpctl_dev,
3183 status_reg | WDTE_TAP_BPN_MASK,
3184 STATUS_TAP_REG_ADDR);
3185 /*else return BP_NOT_CAP; */
3193 int bypass_fw_ver(bpctl_dev_t *pbpctl_dev)
3195 if (is_bypass_fn(pbpctl_dev))
3196 return read_reg(pbpctl_dev, VER_REG_ADDR);
3201 int bypass_sign_check(bpctl_dev_t *pbpctl_dev)
3204 if (is_bypass_fn(pbpctl_dev))
3205 return (((read_reg(pbpctl_dev, PIC_SIGN_REG_ADDR)) ==
3206 PIC_SIGN_VALUE) ? 1 : 0);
3211 static int tx_status(bpctl_dev_t *pbpctl_dev)
3214 bpctl_dev_t *pbpctl_dev_m;
3215 if ((is_bypass_fn(pbpctl_dev)) == 1)
3216 pbpctl_dev_m = pbpctl_dev;
3218 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
3219 if (pbpctl_dev_m == NULL)
3221 if (pbpctl_dev_m->bp_caps_ex & DISC_PORT_CAP_EX) {
3223 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL);
3224 if (pbpctl_dev->bp_i80)
3225 return ((ctrl & BPCTLI_CTRL_SWDPIN1) != 0 ? 0 : 1);
3226 if (pbpctl_dev->bp_540) {
3227 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
3229 return ((ctrl & BP10G_SDP1_DATA) != 0 ? 0 : 1);
3234 if (pbpctl_dev->bp_caps & TX_CTL_CAP) {
3235 if (PEG5_IF_SERIES(pbpctl_dev->subdevice)) {
3239 (pbpctl_dev, BPCTLI_PHY_CONTROL, &mii_reg))) {
3240 if (mii_reg & BPCTLI_MII_CR_POWER_DOWN)
3249 if (pbpctl_dev->bp_10g9) {
3250 return ((BP10G_READ_REG(pbpctl_dev, ESDP) &
3251 BP10G_SDP3_DATA) != 0 ? 0 : 1);
3253 } else if (pbpctl_dev->bp_fiber5) {
3254 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
3255 if (ctrl & BPCTLI_CTRL_EXT_SDP6_DATA)
3258 } else if (pbpctl_dev->bp_10gb) {
3259 ctrl = BP10GB_READ_REG(pbpctl_dev, MISC_REG_GPIO);
3260 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_GPIO,
3261 (ctrl | BP10GB_GPIO0_OE_P1) &
3262 ~(BP10GB_GPIO0_SET_P1 |
3263 BP10GB_GPIO0_CLR_P1));
3265 if ((pbpctl_dev->func == 1) || (pbpctl_dev->func == 3))
3266 return (((BP10GB_READ_REG
3268 MISC_REG_GPIO)) & BP10GB_GPIO0_P1) !=
3271 return (((BP10GB_READ_REG
3273 MISC_REG_GPIO)) & BP10GB_GPIO0_P0) !=
3277 if (!pbpctl_dev->bp_10g) {
3279 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL);
3280 if (pbpctl_dev->bp_i80)
3281 return ((ctrl & BPCTLI_CTRL_SWDPIN1) !=
3283 if (pbpctl_dev->bp_540) {
3284 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
3286 return ((ctrl & BP10G_SDP1_DATA) != 0 ? 0 : 1);
3289 return ((ctrl & BPCTLI_CTRL_SWDPIN0) != 0 ? 0 : 1);
3291 return ((BP10G_READ_REG(pbpctl_dev, ESDP) &
3292 BP10G_SDP0_DATA) != 0 ? 0 : 1);
3298 static int bp_force_link_status(bpctl_dev_t *pbpctl_dev)
3301 if (DBI_IF_SERIES(pbpctl_dev->subdevice)) {
3303 if ((pbpctl_dev->bp_10g) || (pbpctl_dev->bp_10g9)) {
3304 return ((BP10G_READ_REG(pbpctl_dev, ESDP) &
3305 BP10G_SDP1_DIR) != 0 ? 1 : 0);
3312 int bypass_from_last_read(bpctl_dev_t *pbpctl_dev)
3314 uint32_t ctrl_ext = 0;
3315 bpctl_dev_t *pbpctl_dev_b = NULL;
3317 if ((pbpctl_dev->bp_caps & SW_CTL_CAP)
3318 && (pbpctl_dev_b = get_status_port_fn(pbpctl_dev))) {
3319 ctrl_ext = BPCTL_READ_REG(pbpctl_dev_b, CTRL_EXT);
3320 BPCTL_BP_WRITE_REG(pbpctl_dev_b, CTRL_EXT,
3321 (ctrl_ext & ~BPCTLI_CTRL_EXT_SDP7_DIR));
3322 ctrl_ext = BPCTL_READ_REG(pbpctl_dev_b, CTRL_EXT);
3323 if (ctrl_ext & BPCTLI_CTRL_EXT_SDP7_DATA)
3330 int bypass_status_clear(bpctl_dev_t *pbpctl_dev)
3332 bpctl_dev_t *pbpctl_dev_b = NULL;
3334 if ((pbpctl_dev->bp_caps & SW_CTL_CAP)
3335 && (pbpctl_dev_b = get_status_port_fn(pbpctl_dev))) {
3337 send_bypass_clear_pulse(pbpctl_dev_b, 1);
3343 int bypass_flag_status(bpctl_dev_t *pbpctl_dev)
3346 if ((pbpctl_dev->bp_caps & BP_CAP)) {
3347 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3348 return ((((read_reg(pbpctl_dev, STATUS_REG_ADDR)) &
3349 BYPASS_FLAG_MASK) ==
3350 BYPASS_FLAG_MASK) ? 1 : 0);
3356 int bypass_flag_status_clear(bpctl_dev_t *pbpctl_dev)
3359 if (pbpctl_dev->bp_caps & BP_CAP) {
3360 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3361 uint32_t status_reg = 0;
3362 status_reg = read_reg(pbpctl_dev, STATUS_REG_ADDR);
3363 write_reg(pbpctl_dev, status_reg & ~BYPASS_FLAG_MASK,
3371 int bypass_change_status(bpctl_dev_t *pbpctl_dev)
3373 int ret = BP_NOT_CAP;
3375 if (pbpctl_dev->bp_caps & BP_STATUS_CHANGE_CAP) {
3376 if (pbpctl_dev->bp_ext_ver >= 0x8) {
3377 ret = bypass_flag_status(pbpctl_dev);
3378 bypass_flag_status_clear(pbpctl_dev);
3379 } else if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3380 ret = bypass_flag_status(pbpctl_dev);
3381 bypass_flag_status_clear(pbpctl_dev);
3383 ret = bypass_from_last_read(pbpctl_dev);
3384 bypass_status_clear(pbpctl_dev);
3390 int bypass_off_status(bpctl_dev_t *pbpctl_dev)
3393 if (pbpctl_dev->bp_caps & BP_CAP) {
3394 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3395 return ((((read_reg(pbpctl_dev, STATUS_REG_ADDR)) &
3396 BYPASS_OFF_MASK) == BYPASS_OFF_MASK) ? 1 : 0);
3402 static int bypass_status(bpctl_dev_t *pbpctl_dev)
3405 if (pbpctl_dev->bp_caps & BP_CAP) {
3407 bpctl_dev_t *pbpctl_dev_b = NULL;
3409 if (!(pbpctl_dev_b = get_status_port_fn(pbpctl_dev)))
3412 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
3414 if (!pbpctl_dev->bp_status_un)
3415 return (((BPCTL_READ_REG
3418 BPCTLI_CTRL_EXT_SDP7_DATA) !=
3423 if (pbpctl_dev->bp_ext_ver >= 0x8) {
3425 if (pbpctl_dev->bp_10g9) {
3426 ctrl_ext = BP10G_READ_REG(pbpctl_dev_b, I2CCTL);
3427 BP10G_WRITE_REG(pbpctl_dev_b, I2CCTL,
3428 (ctrl_ext | BP10G_I2C_CLK_OUT));
3429 return ((BP10G_READ_REG(pbpctl_dev_b, I2CCTL) &
3430 BP10G_I2C_CLK_IN) != 0 ? 0 : 1);
3432 } else if (pbpctl_dev->bp_540) {
3433 return (((BP10G_READ_REG(pbpctl_dev_b, ESDP)) &
3434 BP10G_SDP0_DATA) != 0 ? 0 : 1);
3437 else if ((pbpctl_dev->bp_fiber5)
3438 || (pbpctl_dev->bp_i80)) {
3439 return (((BPCTL_READ_REG(pbpctl_dev_b, CTRL)) &
3440 BPCTLI_CTRL_SWDPIN0) != 0 ? 0 : 1);
3441 } else if (pbpctl_dev->bp_10gb) {
3443 BP10GB_READ_REG(pbpctl_dev, MISC_REG_GPIO);
3444 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_GPIO,
3445 (ctrl_ext | BP10GB_GPIO3_OE_P0)
3446 & ~(BP10GB_GPIO3_SET_P0 |
3447 BP10GB_GPIO3_CLR_P0));
3449 return (((BP10GB_READ_REG
3451 MISC_REG_GPIO)) & BP10GB_GPIO3_P0) !=
3455 else if (!pbpctl_dev->bp_10g)
3456 return (((BPCTL_READ_REG
3459 BPCTLI_CTRL_EXT_SDP7_DATA) !=
3463 ctrl_ext = BP10G_READ_REG(pbpctl_dev_b, EODSDP);
3464 BP10G_WRITE_REG(pbpctl_dev_b, EODSDP,
3466 BP10G_SDP7_DATA_OUT));
3467 return ((BP10G_READ_REG(pbpctl_dev_b, EODSDP) &
3468 BP10G_SDP7_DATA_IN) != 0 ? 0 : 1);
3471 } else if (pbpctl_dev->media_type == bp_copper) {
3473 return (((BPCTL_READ_REG(pbpctl_dev_b, CTRL)) &
3474 BPCTLI_CTRL_SWDPIN1) != 0 ? 1 : 0);
3476 if ((bypass_status_clear(pbpctl_dev)) >= 0)
3477 return bypass_from_last_read(pbpctl_dev);
3484 int default_pwron_status(bpctl_dev_t *pbpctl_dev)
3487 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3488 if (pbpctl_dev->bp_caps & BP_PWUP_CTL_CAP) {
3489 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3492 STATUS_REG_ADDR)) & DFLT_PWRON_MASK)
3493 == DFLT_PWRON_MASK) ? 0 : 1);
3495 } /*else if ((!pbpctl_dev->bp_caps&BP_DIS_CAP)&&
3496 (pbpctl_dev->bp_caps&BP_PWUP_ON_CAP))
3502 static int default_pwroff_status(bpctl_dev_t *pbpctl_dev)
3505 /*if ((!pbpctl_dev->bp_caps&BP_DIS_CAP)&&
3506 (pbpctl_dev->bp_caps&BP_PWOFF_ON_CAP))
3508 if ((pbpctl_dev->bp_caps & SW_CTL_CAP)
3509 && (pbpctl_dev->bp_caps & BP_PWOFF_CTL_CAP)) {
3510 return ((((read_reg(pbpctl_dev, STATUS_REG_ADDR)) &
3511 DFLT_PWROFF_MASK) == DFLT_PWROFF_MASK) ? 0 : 1);
3516 int dis_bypass_cap_status(bpctl_dev_t *pbpctl_dev)
3519 if (pbpctl_dev->bp_caps & BP_DIS_CAP) {
3520 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3521 return ((((read_reg(pbpctl_dev, STATUS_REG_ADDR)) &
3522 DIS_BYPASS_CAP_MASK) ==
3523 DIS_BYPASS_CAP_MASK) ? 1 : 0);
3529 int cmd_en_status(bpctl_dev_t *pbpctl_dev)
3532 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3533 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3534 return ((((read_reg(pbpctl_dev, STATUS_REG_ADDR)) &
3535 CMND_EN_MASK) == CMND_EN_MASK) ? 1 : 0);
3541 int wdt_en_status(bpctl_dev_t *pbpctl_dev)
3544 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
3545 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3546 return ((((read_reg(pbpctl_dev, STATUS_REG_ADDR)) &
3547 WDT_EN_MASK) == WDT_EN_MASK) ? 1 : 0);
3553 int wdt_programmed(bpctl_dev_t *pbpctl_dev, int *timeout)
3556 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
3557 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3558 if ((read_reg(pbpctl_dev, STATUS_REG_ADDR)) &
3561 wdt_val = read_reg(pbpctl_dev, WDT_REG_ADDR);
3562 *timeout = (1 << wdt_val) * 100;
3566 int curr_wdt_status = pbpctl_dev->wdt_status;
3567 if (curr_wdt_status == WDT_STATUS_UNKNOWN)
3572 0 ? 0 : pbpctl_dev->bypass_timer_interval;
3579 int bypass_support(bpctl_dev_t *pbpctl_dev)
3583 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3584 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER) {
3586 ((((read_reg(pbpctl_dev, PRODUCT_CAP_REG_ADDR)) &
3587 BYPASS_SUPPORT_MASK) ==
3588 BYPASS_SUPPORT_MASK) ? 1 : 0);
3589 } else if (pbpctl_dev->bp_ext_ver == PXG2BPI_VER)
3596 int tap_support(bpctl_dev_t *pbpctl_dev)
3600 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3601 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER) {
3603 ((((read_reg(pbpctl_dev, PRODUCT_CAP_REG_ADDR)) &
3604 TAP_SUPPORT_MASK) == TAP_SUPPORT_MASK) ? 1 : 0);
3605 } else if (pbpctl_dev->bp_ext_ver == PXG2BPI_VER)
3612 int normal_support(bpctl_dev_t *pbpctl_dev)
3614 int ret = BP_NOT_CAP;
3616 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3617 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER) {
3619 ((((read_reg(pbpctl_dev, PRODUCT_CAP_REG_ADDR)) &
3620 NORMAL_UNSUPPORT_MASK) ==
3621 NORMAL_UNSUPPORT_MASK) ? 0 : 1);
3628 int get_bp_prod_caps(bpctl_dev_t *pbpctl_dev)
3630 if ((pbpctl_dev->bp_caps & SW_CTL_CAP) &&
3631 (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER))
3632 return read_reg(pbpctl_dev, PRODUCT_CAP_REG_ADDR);
3637 int tap_flag_status(bpctl_dev_t *pbpctl_dev)
3640 if (pbpctl_dev->bp_caps & TAP_STATUS_CAP) {
3641 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER)
3642 return ((((read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR)) &
3643 TAP_FLAG_MASK) == TAP_FLAG_MASK) ? 1 : 0);
3649 int tap_flag_status_clear(bpctl_dev_t *pbpctl_dev)
3651 uint32_t status_reg = 0;
3652 if (pbpctl_dev->bp_caps & TAP_STATUS_CAP) {
3653 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER) {
3654 status_reg = read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR);
3655 write_reg(pbpctl_dev, status_reg & ~TAP_FLAG_MASK,
3656 STATUS_TAP_REG_ADDR);
3663 int tap_change_status(bpctl_dev_t *pbpctl_dev)
3665 int ret = BP_NOT_CAP;
3666 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER) {
3667 if (pbpctl_dev->bp_caps & TAP_CAP) {
3668 if (pbpctl_dev->bp_caps & BP_CAP) {
3669 ret = tap_flag_status(pbpctl_dev);
3670 tap_flag_status_clear(pbpctl_dev);
3672 ret = bypass_from_last_read(pbpctl_dev);
3673 bypass_status_clear(pbpctl_dev);
3680 int tap_off_status(bpctl_dev_t *pbpctl_dev)
3682 if (pbpctl_dev->bp_caps & TAP_CAP) {
3683 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER)
3684 return ((((read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR)) &
3685 TAP_OFF_MASK) == TAP_OFF_MASK) ? 1 : 0);
3690 int tap_status(bpctl_dev_t *pbpctl_dev)
3694 if (pbpctl_dev->bp_caps & TAP_CAP) {
3695 bpctl_dev_t *pbpctl_dev_b = NULL;
3697 if (!(pbpctl_dev_b = get_status_port_fn(pbpctl_dev)))
3700 if (pbpctl_dev->bp_ext_ver >= 0x8) {
3701 if (!pbpctl_dev->bp_10g)
3702 return (((BPCTL_READ_REG
3705 BPCTLI_CTRL_EXT_SDP6_DATA) !=
3708 ctrl_ext = BP10G_READ_REG(pbpctl_dev_b, EODSDP);
3709 BP10G_WRITE_REG(pbpctl_dev_b, EODSDP,
3711 BP10G_SDP6_DATA_OUT));
3712 return ((BP10G_READ_REG(pbpctl_dev_b, EODSDP) &
3713 BP10G_SDP6_DATA_IN) != 0 ? 0 : 1);
3716 } else if (pbpctl_dev->media_type == bp_copper)
3717 return (((BPCTL_READ_REG(pbpctl_dev, CTRL)) &
3718 BPCTLI_CTRL_SWDPIN0) != 0 ? 1 : 0);
3720 if ((bypass_status_clear(pbpctl_dev)) >= 0)
3721 return bypass_from_last_read(pbpctl_dev);
3728 int default_pwron_tap_status(bpctl_dev_t *pbpctl_dev)
3730 if (pbpctl_dev->bp_caps & TAP_PWUP_CTL_CAP) {
3731 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER)
3732 return ((((read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR)) &
3733 DFLT_PWRON_TAP_MASK) ==
3734 DFLT_PWRON_TAP_MASK) ? 1 : 0);
3739 int dis_tap_cap_status(bpctl_dev_t *pbpctl_dev)
3741 if (pbpctl_dev->bp_caps & TAP_PWUP_CTL_CAP) {
3742 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER)
3743 return ((((read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR)) &
3744 DIS_TAP_CAP_MASK) ==
3745 DIS_TAP_CAP_MASK) ? 1 : 0);
3750 int disc_flag_status(bpctl_dev_t *pbpctl_dev)
3753 if (pbpctl_dev->bp_caps & DISC_CAP) {
3754 if (pbpctl_dev->bp_ext_ver >= 0x8)
3755 return ((((read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR)) &
3756 DISC_FLAG_MASK) == DISC_FLAG_MASK) ? 1 : 0);
3762 int disc_flag_status_clear(bpctl_dev_t *pbpctl_dev)
3764 uint32_t status_reg = 0;
3765 if (pbpctl_dev->bp_caps & DISC_CAP) {
3766 if (pbpctl_dev->bp_ext_ver >= 0x8) {
3767 status_reg = read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR);
3768 write_reg(pbpctl_dev, status_reg & ~DISC_FLAG_MASK,
3769 STATUS_DISC_REG_ADDR);
3776 int disc_change_status(bpctl_dev_t *pbpctl_dev)
3778 int ret = BP_NOT_CAP;
3779 if (pbpctl_dev->bp_caps & DISC_CAP) {
3780 ret = disc_flag_status(pbpctl_dev);
3781 disc_flag_status_clear(pbpctl_dev);
3787 int disc_off_status(bpctl_dev_t *pbpctl_dev)
3789 bpctl_dev_t *pbpctl_dev_b = NULL;
3792 if (pbpctl_dev->bp_caps & DISC_CAP) {
3793 if (!(pbpctl_dev_b = get_status_port_fn(pbpctl_dev)))
3795 if (DISCF_IF_SERIES(pbpctl_dev->subdevice))
3796 return ((((read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR)) &
3797 DISC_OFF_MASK) == DISC_OFF_MASK) ? 1 : 0);
3799 if (pbpctl_dev->bp_i80) {
3800 return (((BPCTL_READ_REG(pbpctl_dev_b, CTRL_EXT)) &
3801 BPCTLI_CTRL_EXT_SDP6_DATA) != 0 ? 1 : 0);
3804 if (pbpctl_dev->bp_540) {
3805 ctrl_ext = BP10G_READ_REG(pbpctl_dev_b, ESDP);
3806 return ((BP10G_READ_REG(pbpctl_dev_b, ESDP) &
3807 BP10G_SDP2_DATA) != 0 ? 1 : 0);
3810 if (pbpctl_dev->media_type == bp_copper) {
3813 return ((((read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR)) &
3814 DISC_OFF_MASK) == DISC_OFF_MASK) ? 1 : 0);
3816 if (!pbpctl_dev->bp_10g)
3817 return (((BPCTL_READ_REG(pbpctl_dev_b, CTRL)) &
3818 BPCTLI_CTRL_SWDPIN1) != 0 ? 1 : 0);
3820 return ((BP10G_READ_REG(pbpctl_dev_b, ESDP) &
3821 BP10G_SDP1_DATA) != 0 ? 1 : 0);
3825 if (pbpctl_dev->bp_10g9) {
3826 ctrl_ext = BP10G_READ_REG(pbpctl_dev_b, I2CCTL);
3827 BP10G_WRITE_REG(pbpctl_dev_b, I2CCTL,
3829 BP10G_I2C_DATA_OUT));
3830 return ((BP10G_READ_REG(pbpctl_dev_b, I2CCTL) &
3831 BP10G_I2C_DATA_IN) != 0 ? 1 : 0);
3833 } else if (pbpctl_dev->bp_fiber5) {
3834 return (((BPCTL_READ_REG(pbpctl_dev_b, CTRL)) &
3835 BPCTLI_CTRL_SWDPIN1) != 0 ? 1 : 0);
3836 } else if (pbpctl_dev->bp_10gb) {
3838 BP10GB_READ_REG(pbpctl_dev, MISC_REG_GPIO);
3839 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_GPIO,
3840 (ctrl_ext | BP10GB_GPIO3_OE_P1)
3841 & ~(BP10GB_GPIO3_SET_P1 |
3842 BP10GB_GPIO3_CLR_P1));
3844 return (((BP10GB_READ_REG
3846 MISC_REG_GPIO)) & BP10GB_GPIO3_P1) !=
3849 if (!pbpctl_dev->bp_10g) {
3851 return (((BPCTL_READ_REG
3854 BPCTLI_CTRL_EXT_SDP6_DATA) !=
3857 ctrl_ext = BP10G_READ_REG(pbpctl_dev_b, EODSDP);
3858 BP10G_WRITE_REG(pbpctl_dev_b, EODSDP,
3860 BP10G_SDP6_DATA_OUT));
3861 return (((BP10G_READ_REG(pbpctl_dev_b, EODSDP))
3862 & BP10G_SDP6_DATA_IN) != 0 ? 1 : 0);
3870 static int disc_status(bpctl_dev_t *pbpctl_dev)
3873 if (pbpctl_dev->bp_caps & DISC_CAP) {
3875 if ((ctrl = disc_off_status(pbpctl_dev)) < 0)
3877 return ((ctrl == 0) ? 1 : 0);
3883 int default_pwron_disc_status(bpctl_dev_t *pbpctl_dev)
3885 if (pbpctl_dev->bp_caps & DISC_PWUP_CTL_CAP) {
3886 if (pbpctl_dev->bp_ext_ver >= 0x8)
3887 return ((((read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR)) &
3888 DFLT_PWRON_DISC_MASK) ==
3889 DFLT_PWRON_DISC_MASK) ? 1 : 0);
3894 int dis_disc_cap_status(bpctl_dev_t *pbpctl_dev)
3896 if (pbpctl_dev->bp_caps & DIS_DISC_CAP) {
3897 if (pbpctl_dev->bp_ext_ver >= 0x8)
3898 return ((((read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR)) &
3899 DIS_DISC_CAP_MASK) ==
3900 DIS_DISC_CAP_MASK) ? 1 : 0);
3905 int disc_port_status(bpctl_dev_t *pbpctl_dev)
3907 int ret = BP_NOT_CAP;
3908 bpctl_dev_t *pbpctl_dev_m;
3910 if ((is_bypass_fn(pbpctl_dev)) == 1)
3911 pbpctl_dev_m = pbpctl_dev;
3913 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
3914 if (pbpctl_dev_m == NULL)
3917 if (pbpctl_dev_m->bp_caps_ex & DISC_PORT_CAP_EX) {
3918 if (is_bypass_fn(pbpctl_dev) == 1) {
3919 return ((((read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR)) &
3920 TX_DISA_MASK) == TX_DISA_MASK) ? 1 : 0);
3922 return ((((read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR)) &
3923 TX_DISB_MASK) == TX_DISB_MASK) ? 1 : 0);
3929 int default_pwron_disc_port_status(bpctl_dev_t *pbpctl_dev)
3931 int ret = BP_NOT_CAP;
3932 bpctl_dev_t *pbpctl_dev_m;
3934 if ((is_bypass_fn(pbpctl_dev)) == 1)
3935 pbpctl_dev_m = pbpctl_dev;
3937 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
3938 if (pbpctl_dev_m == NULL)
3941 if (pbpctl_dev_m->bp_caps_ex & DISC_PORT_CAP_EX) {
3942 if (is_bypass_fn(pbpctl_dev) == 1)
3944 /* return((((read_reg(pbpctl_dev,STATUS_TAP_REG_ADDR)) & TX_DISA_MASK)==TX_DISA_MASK)?1:0); */
3947 /* return((((read_reg(pbpctl_dev,STATUS_TAP_REG_ADDR)) & TX_DISA_MASK)==TX_DISA_MASK)?1:0); */
3953 int wdt_exp_mode_status(bpctl_dev_t *pbpctl_dev)
3955 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
3956 if (pbpctl_dev->bp_ext_ver <= PXG2BPI_VER)
3957 return 0; /* bypass mode */
3958 else if (pbpctl_dev->bp_ext_ver == PXG2TBPI_VER)
3959 return 1; /* tap mode */
3960 else if (pbpctl_dev->bp_ext_ver >= PXE2TBPI_VER) {
3961 if (pbpctl_dev->bp_ext_ver >= 0x8) {
3964 STATUS_DISC_REG_ADDR)) &
3965 WDTE_DISC_BPN_MASK) == WDTE_DISC_BPN_MASK)
3968 return ((((read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR)) &
3969 WDTE_TAP_BPN_MASK) ==
3970 WDTE_TAP_BPN_MASK) ? 1 : 0);
3976 int tpl2_flag_status(bpctl_dev_t *pbpctl_dev)
3979 if (pbpctl_dev->bp_caps_ex & TPL2_CAP_EX) {
3980 return ((((read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR)) &
3981 TPL2_FLAG_MASK) == TPL2_FLAG_MASK) ? 1 : 0);
3987 int tpl_hw_status(bpctl_dev_t *pbpctl_dev)
3989 bpctl_dev_t *pbpctl_dev_b = NULL;
3991 if (!(pbpctl_dev_b = get_status_port_fn(pbpctl_dev)))
3994 if (TPL_IF_SERIES(pbpctl_dev->subdevice))
3995 return (((BPCTL_READ_REG(pbpctl_dev, CTRL)) &
3996 BPCTLI_CTRL_SWDPIN0) != 0 ? 1 : 0);
4001 int bp_wait_at_pwup_status(bpctl_dev_t *pbpctl_dev)
4003 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
4004 if (pbpctl_dev->bp_ext_ver >= 0x8)
4005 return ((((read_reg(pbpctl_dev, CONT_CONFIG_REG_ADDR)) &
4006 WAIT_AT_PWUP_MASK) ==
4007 WAIT_AT_PWUP_MASK) ? 1 : 0);
4012 int bp_hw_reset_status(bpctl_dev_t *pbpctl_dev)
4015 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
4017 if (pbpctl_dev->bp_ext_ver >= 0x8)
4018 return ((((read_reg(pbpctl_dev, CONT_CONFIG_REG_ADDR)) &
4019 EN_HW_RESET_MASK) ==
4020 EN_HW_RESET_MASK) ? 1 : 0);
4026 int std_nic_status(bpctl_dev_t *pbpctl_dev)
4030 if (pbpctl_dev->bp_caps & STD_NIC_CAP) {
4031 if (INTEL_IF_SERIES(pbpctl_dev->subdevice))
4033 if (pbpctl_dev->bp_ext_ver >= BP_FW_EXT_VER8) {
4034 return ((((read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR)) &
4035 STD_NIC_ON_MASK) == STD_NIC_ON_MASK) ? 1 : 0);
4038 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
4039 if (pbpctl_dev->bp_caps & BP_CAP) {
4041 read_reg(pbpctl_dev, STATUS_REG_ADDR);
4042 if (((!(status_val & WDT_EN_MASK))
4043 && ((status_val & STD_NIC_MASK) ==
4049 if (pbpctl_dev->bp_caps & TAP_CAP) {
4051 read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR);
4052 if ((status_val & STD_NIC_TAP_MASK) ==
4058 if (pbpctl_dev->bp_caps & TAP_CAP) {
4059 if ((disc_off_status(pbpctl_dev)))
4071 /******************************************************/
4072 /**************SW_INIT*********************************/
4073 /******************************************************/
4074 void bypass_caps_init(bpctl_dev_t *pbpctl_dev)
4076 u_int32_t ctrl_ext = 0;
4077 bpctl_dev_t *pbpctl_dev_m = NULL;
4081 if (!(INTEL_IF_SERIES(adapter->bp_device_block.subdevice))) {
4082 ret = read_reg(pbpctl_dev, VER_REG_ADDR);
4083 printk("VER_REG reg1=%x\n", ret);
4084 ret = read_reg(pbpctl_dev, PRODUCT_CAP_REG_ADDR);
4085 printk("PRODUCT_CAP reg=%x\n", ret);
4086 ret = read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR);
4087 printk("STATUS_TAP reg1=%x\n", ret);
4088 ret = read_reg(pbpctl_dev, 0x7);
4089 printk("SIG_REG reg1=%x\n", ret);
4090 ret = read_reg(pbpctl_dev, STATUS_REG_ADDR);
4091 printk("STATUS_REG_ADDR=%x\n", ret);
4092 ret = read_reg(pbpctl_dev, WDT_REG_ADDR);
4093 printk("WDT_REG_ADDR=%x\n", ret);
4094 ret = read_reg(pbpctl_dev, TMRL_REG_ADDR);
4095 printk("TMRL_REG_ADDR=%x\n", ret);
4096 ret = read_reg(pbpctl_dev, TMRH_REG_ADDR);
4097 printk("TMRH_REG_ADDR=%x\n", ret);
4100 if ((pbpctl_dev->bp_fiber5) || (pbpctl_dev->bp_10g9)) {
4101 pbpctl_dev->media_type = bp_fiber;
4102 } else if (pbpctl_dev->bp_10gb) {
4103 if (BP10GB_CX4_SERIES(pbpctl_dev->subdevice))
4104 pbpctl_dev->media_type = bp_cx4;
4106 pbpctl_dev->media_type = bp_fiber;
4110 else if (pbpctl_dev->bp_540)
4111 pbpctl_dev->media_type = bp_none;
4112 else if (!pbpctl_dev->bp_10g) {
4114 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
4115 if ((ctrl_ext & BPCTLI_CTRL_EXT_LINK_MODE_MASK) == 0x0)
4116 pbpctl_dev->media_type = bp_copper;
4118 pbpctl_dev->media_type = bp_fiber;
4121 if (BP10G_CX4_SERIES(pbpctl_dev->subdevice))
4122 pbpctl_dev->media_type = bp_cx4;
4124 pbpctl_dev->media_type = bp_fiber;
4127 if (is_bypass_fn(pbpctl_dev)) {
4129 pbpctl_dev->bp_caps |= BP_PWOFF_ON_CAP;
4130 if (pbpctl_dev->media_type == bp_fiber)
4131 pbpctl_dev->bp_caps |=
4132 (TX_CTL_CAP | TX_STATUS_CAP | TPL_CAP);
4134 if (TPL_IF_SERIES(pbpctl_dev->subdevice)) {
4135 pbpctl_dev->bp_caps |= TPL_CAP;
4138 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
4139 pbpctl_dev->bp_caps |=
4140 (BP_CAP | BP_STATUS_CAP | SW_CTL_CAP |
4141 BP_PWUP_ON_CAP | BP_PWUP_OFF_CAP | BP_PWOFF_OFF_CAP
4142 | WD_CTL_CAP | WD_STATUS_CAP | STD_NIC_CAP |
4145 pbpctl_dev->bp_ext_ver = OLD_IF_VER;
4149 if ((pbpctl_dev->bp_fw_ver == 0xff) &&
4150 OLD_IF_SERIES(pbpctl_dev->subdevice)) {
4152 pbpctl_dev->bp_caps |=
4153 (BP_CAP | BP_STATUS_CAP | BP_STATUS_CHANGE_CAP |
4154 SW_CTL_CAP | BP_PWUP_ON_CAP | WD_CTL_CAP |
4155 WD_STATUS_CAP | WD_TIMEOUT_CAP);
4157 pbpctl_dev->bp_ext_ver = OLD_IF_VER;
4162 switch (pbpctl_dev->bp_fw_ver) {
4165 pbpctl_dev->bp_ext_ver =
4167 bp_fw_ver & EXT_VER_MASK);
4171 if ((bypass_sign_check(pbpctl_dev)) !=
4173 pbpctl_dev->bp_caps = 0;
4176 pbpctl_dev->bp_ext_ver =
4178 bp_fw_ver & EXT_VER_MASK);
4183 if (pbpctl_dev->bp_ext_ver == PXG2BPI_VER)
4184 pbpctl_dev->bp_caps |=
4185 (BP_CAP | BP_STATUS_CAP | BP_STATUS_CHANGE_CAP |
4186 SW_CTL_CAP | BP_DIS_CAP | BP_DIS_STATUS_CAP |
4187 BP_PWUP_ON_CAP | BP_PWUP_OFF_CAP | BP_PWUP_CTL_CAP
4188 | WD_CTL_CAP | STD_NIC_CAP | WD_STATUS_CAP |
4190 else if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER) {
4193 pbpctl_dev->bp_caps |=
4194 (SW_CTL_CAP | WD_CTL_CAP | WD_STATUS_CAP |
4196 cap_reg = get_bp_prod_caps(pbpctl_dev);
4198 if ((cap_reg & NORMAL_UNSUPPORT_MASK) ==
4199 NORMAL_UNSUPPORT_MASK)
4200 pbpctl_dev->bp_caps |= NIC_CAP_NEG;
4202 pbpctl_dev->bp_caps |= STD_NIC_CAP;
4204 if ((normal_support(pbpctl_dev)) == 1)
4206 pbpctl_dev->bp_caps |= STD_NIC_CAP;
4209 pbpctl_dev->bp_caps |= NIC_CAP_NEG;
4210 if ((cap_reg & BYPASS_SUPPORT_MASK) ==
4211 BYPASS_SUPPORT_MASK) {
4212 pbpctl_dev->bp_caps |=
4213 (BP_CAP | BP_STATUS_CAP |
4214 BP_STATUS_CHANGE_CAP | BP_DIS_CAP |
4215 BP_DIS_STATUS_CAP | BP_PWUP_ON_CAP |
4216 BP_PWUP_OFF_CAP | BP_PWUP_CTL_CAP);
4217 if (pbpctl_dev->bp_ext_ver >= BP_FW_EXT_VER7)
4218 pbpctl_dev->bp_caps |=
4219 BP_PWOFF_ON_CAP | BP_PWOFF_OFF_CAP |
4222 if ((cap_reg & TAP_SUPPORT_MASK) == TAP_SUPPORT_MASK) {
4223 pbpctl_dev->bp_caps |=
4224 (TAP_CAP | TAP_STATUS_CAP |
4225 TAP_STATUS_CHANGE_CAP | TAP_DIS_CAP |
4226 TAP_DIS_STATUS_CAP | TAP_PWUP_ON_CAP |
4227 TAP_PWUP_OFF_CAP | TAP_PWUP_CTL_CAP);
4229 if (pbpctl_dev->bp_ext_ver >= BP_FW_EXT_VER8) {
4230 if ((cap_reg & DISC_SUPPORT_MASK) ==
4232 pbpctl_dev->bp_caps |=
4233 (DISC_CAP | DISC_DIS_CAP |
4235 if ((cap_reg & TPL2_SUPPORT_MASK) ==
4236 TPL2_SUPPORT_MASK) {
4237 pbpctl_dev->bp_caps_ex |= TPL2_CAP_EX;
4238 pbpctl_dev->bp_caps |= TPL_CAP;
4239 pbpctl_dev->bp_tpl_flag =
4240 tpl2_flag_status(pbpctl_dev);
4245 if (pbpctl_dev->bp_ext_ver >= BP_FW_EXT_VER9) {
4246 if ((cap_reg & DISC_PORT_SUPPORT_MASK) ==
4247 DISC_PORT_SUPPORT_MASK) {
4248 pbpctl_dev->bp_caps_ex |=
4250 pbpctl_dev->bp_caps |=
4251 (TX_CTL_CAP | TX_STATUS_CAP);
4257 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
4258 if ((read_reg(pbpctl_dev, STATUS_REG_ADDR)) &
4260 pbpctl_dev->wdt_status = WDT_STATUS_EN;
4262 pbpctl_dev->wdt_status = WDT_STATUS_DIS;
4265 } else if ((P2BPFI_IF_SERIES(pbpctl_dev->subdevice)) ||
4266 (PEGF5_IF_SERIES(pbpctl_dev->subdevice)) ||
4267 (PEGF80_IF_SERIES(pbpctl_dev->subdevice)) ||
4268 (BP10G9_IF_SERIES(pbpctl_dev->subdevice))) {
4269 pbpctl_dev->bp_caps |= (TX_CTL_CAP | TX_STATUS_CAP);
4271 if ((pbpctl_dev->subdevice & 0xa00) == 0xa00)
4272 pbpctl_dev->bp_caps |= (TX_CTL_CAP | TX_STATUS_CAP);
4273 if (PEG5_IF_SERIES(pbpctl_dev->subdevice))
4274 pbpctl_dev->bp_caps |= (TX_CTL_CAP | TX_STATUS_CAP);
4276 if (BP10GB_IF_SERIES(pbpctl_dev->subdevice)) {
4277 pbpctl_dev->bp_caps &= ~(TX_CTL_CAP | TX_STATUS_CAP);
4279 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
4280 if (pbpctl_dev_m != NULL) {
4282 if (pbpctl_dev_m->bp_ext_ver >= 0x9) {
4283 cap_reg = get_bp_prod_caps(pbpctl_dev_m);
4284 if ((cap_reg & DISC_PORT_SUPPORT_MASK) ==
4285 DISC_PORT_SUPPORT_MASK)
4286 pbpctl_dev->bp_caps |=
4287 (TX_CTL_CAP | TX_STATUS_CAP);
4288 pbpctl_dev->bp_caps_ex |= DISC_PORT_CAP_EX;
4293 int bypass_off_init(bpctl_dev_t *pbpctl_dev)
4297 if ((ret = cmnd_on(pbpctl_dev)) < 0)
4299 if (INTEL_IF_SERIES(pbpctl_dev->subdevice))
4300 return dis_bypass_cap(pbpctl_dev);
4301 wdt_off(pbpctl_dev);
4302 if (pbpctl_dev->bp_caps & BP_CAP)
4303 bypass_off(pbpctl_dev);
4304 if (pbpctl_dev->bp_caps & TAP_CAP)
4305 tap_off(pbpctl_dev);
4306 cmnd_off(pbpctl_dev);
4310 void remove_bypass_wd_auto(bpctl_dev_t *pbpctl_dev)
4313 bpctl_dev_t *pbpctl_dev_sl = NULL;
4316 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
4318 del_timer_sync(&pbpctl_dev->bp_timer);
4320 pbpctl_dev_sl = get_status_port_fn(pbpctl_dev);
4321 if (pbpctl_dev_sl && (pbpctl_dev_sl->ndev)) {
4322 if ((pbpctl_dev_sl->ndev->netdev_ops)
4323 && (pbpctl_dev_sl->old_ops)) {
4325 pbpctl_dev_sl->ndev->netdev_ops =
4326 pbpctl_dev_sl->old_ops;
4327 pbpctl_dev_sl->old_ops = NULL;
4339 int init_bypass_wd_auto(bpctl_dev_t *pbpctl_dev)
4341 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
4342 init_timer(&pbpctl_dev->bp_timer);
4343 pbpctl_dev->bp_timer.function = &wd_reset_timer;
4344 pbpctl_dev->bp_timer.data = (unsigned long)pbpctl_dev;
4351 int bp_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
4353 bpctl_dev_t *pbpctl_dev = NULL, *pbpctl_dev_m = NULL;
4355 struct ethhdr *eth = (struct ethhdr *)skb->data;
4358 ((bpctl_dev_arr[idx_dev].ndev != NULL) && (idx_dev < device_num));
4360 if (bpctl_dev_arr[idx_dev].ndev == dev) {
4361 pbpctl_dev = &bpctl_dev_arr[idx_dev];
4367 if ((htons(ETH_P_BPTEST) == eth->h_proto)) {
4369 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
4372 if (bypass_status(pbpctl_dev_m)) {
4373 cmnd_on(pbpctl_dev_m);
4374 bypass_off(pbpctl_dev_m);
4375 cmnd_off(pbpctl_dev_m);
4377 wdt_timer_reload(pbpctl_dev_m);
4379 dev_kfree_skb_irq(skb);
4382 return pbpctl_dev->hard_start_xmit_save(skb, dev);
4386 int set_bypass_wd_auto(bpctl_dev_t *pbpctl_dev, unsigned int param)
4388 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
4389 if (pbpctl_dev->reset_time != param) {
4390 if (INTEL_IF_SERIES(pbpctl_dev->subdevice))
4391 pbpctl_dev->reset_time =
4393 WDT_AUTO_MIN_INT) ? WDT_AUTO_MIN_INT :
4396 pbpctl_dev->reset_time = param;
4398 mod_timer(&pbpctl_dev->bp_timer, jiffies);
4405 int get_bypass_wd_auto(bpctl_dev_t *pbpctl_dev)
4408 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
4409 return pbpctl_dev->reset_time;
4416 int set_bp_self_test(bpctl_dev_t *pbpctl_dev, unsigned int param)
4418 bpctl_dev_t *pbpctl_dev_sl = NULL;
4420 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
4421 pbpctl_dev->bp_self_test_flag = param == 0 ? 0 : 1;
4422 pbpctl_dev_sl = get_status_port_fn(pbpctl_dev);
4424 if ((pbpctl_dev_sl->ndev) && (pbpctl_dev_sl->ndev->netdev_ops)) {
4426 if (pbpctl_dev->bp_self_test_flag == 1) {
4428 pbpctl_dev_sl->old_ops =
4429 pbpctl_dev_sl->ndev->netdev_ops;
4430 pbpctl_dev_sl->new_ops =
4431 *pbpctl_dev_sl->old_ops;
4432 pbpctl_dev_sl->new_ops.ndo_start_xmit =
4434 pbpctl_dev_sl->ndev->netdev_ops =
4435 &pbpctl_dev_sl->new_ops;
4437 } else if (pbpctl_dev_sl->old_ops) {
4438 pbpctl_dev_sl->ndev->netdev_ops =
4439 pbpctl_dev_sl->old_ops;
4440 pbpctl_dev_sl->old_ops = NULL;
4445 set_bypass_wd_auto(pbpctl_dev, param);
4451 int get_bp_self_test(bpctl_dev_t *pbpctl_dev)
4454 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
4455 if (pbpctl_dev->bp_self_test_flag == 1)
4456 return pbpctl_dev->reset_time;
4465 /**************************************************************/
4466 /************************* API ********************************/
4467 /**************************************************************/
4469 int is_bypass_fn(bpctl_dev_t *pbpctl_dev)
4474 return (((pbpctl_dev->func == 0) || (pbpctl_dev->func == 2)) ? 1 : 0);
4477 int set_bypass_fn(bpctl_dev_t *pbpctl_dev, int bypass_mode)
4481 if (!(pbpctl_dev->bp_caps & BP_CAP))
4483 if ((ret = cmnd_on(pbpctl_dev)) < 0)
4486 ret = bypass_off(pbpctl_dev);
4488 ret = bypass_on(pbpctl_dev);
4489 cmnd_off(pbpctl_dev);
4494 int get_bypass_fn(bpctl_dev_t *pbpctl_dev)
4496 return bypass_status(pbpctl_dev);
4499 int get_bypass_change_fn(bpctl_dev_t *pbpctl_dev)
4504 return bypass_change_status(pbpctl_dev);
4507 int set_dis_bypass_fn(bpctl_dev_t *pbpctl_dev, int dis_param)
4513 if (!(pbpctl_dev->bp_caps & BP_DIS_CAP))
4515 if ((ret = cmnd_on(pbpctl_dev)) < 0)
4518 ret = dis_bypass_cap(pbpctl_dev);
4520 ret = en_bypass_cap(pbpctl_dev);
4521 cmnd_off(pbpctl_dev);
4525 int get_dis_bypass_fn(bpctl_dev_t *pbpctl_dev)
4530 return dis_bypass_cap_status(pbpctl_dev);
4533 int set_bypass_pwoff_fn(bpctl_dev_t *pbpctl_dev, int bypass_mode)
4539 if (!(pbpctl_dev->bp_caps & BP_PWOFF_CTL_CAP))
4541 if ((ret = cmnd_on(pbpctl_dev)) < 0)
4544 ret = bypass_state_pwroff(pbpctl_dev);
4546 ret = normal_state_pwroff(pbpctl_dev);
4547 cmnd_off(pbpctl_dev);
4551 int get_bypass_pwoff_fn(bpctl_dev_t *pbpctl_dev)
4556 return default_pwroff_status(pbpctl_dev);
4559 int set_bypass_pwup_fn(bpctl_dev_t *pbpctl_dev, int bypass_mode)
4565 if (!(pbpctl_dev->bp_caps & BP_PWUP_CTL_CAP))
4567 if ((ret = cmnd_on(pbpctl_dev)) < 0)
4570 ret = bypass_state_pwron(pbpctl_dev);
4572 ret = normal_state_pwron(pbpctl_dev);
4573 cmnd_off(pbpctl_dev);
4577 int get_bypass_pwup_fn(bpctl_dev_t *pbpctl_dev)
4582 return default_pwron_status(pbpctl_dev);
4585 int set_bypass_wd_fn(bpctl_dev_t *pbpctl_dev, int timeout)
4591 if (!(pbpctl_dev->bp_caps & WD_CTL_CAP))
4594 if ((ret = cmnd_on(pbpctl_dev)) < 0)
4597 ret = wdt_off(pbpctl_dev);
4599 wdt_on(pbpctl_dev, timeout);
4600 ret = pbpctl_dev->bypass_timer_interval;
4602 cmnd_off(pbpctl_dev);
4606 int get_bypass_wd_fn(bpctl_dev_t *pbpctl_dev, int *timeout)
4611 return wdt_programmed(pbpctl_dev, timeout);
4614 int get_wd_expire_time_fn(bpctl_dev_t *pbpctl_dev, int *time_left)
4619 return wdt_timer(pbpctl_dev, time_left);
4622 int reset_bypass_wd_timer_fn(bpctl_dev_t *pbpctl_dev)
4627 return wdt_timer_reload(pbpctl_dev);
4630 int get_wd_set_caps_fn(bpctl_dev_t *pbpctl_dev)
4634 unsigned int step_value = TIMEOUT_MAX_STEP + 1, bit_cnt = 0;
4638 if (INTEL_IF_SERIES(pbpctl_dev->subdevice))
4641 while ((step_value >>= 1))
4644 if (is_bypass_fn(pbpctl_dev)) {
4646 WD_STEP_COUNT_MASK(bit_cnt) | WDT_STEP_TIME |
4647 WD_MIN_TIME_MASK(TIMEOUT_UNIT / 100);
4654 int set_std_nic_fn(bpctl_dev_t *pbpctl_dev, int nic_mode)
4660 if (!(pbpctl_dev->bp_caps & STD_NIC_CAP))
4663 if ((ret = cmnd_on(pbpctl_dev)) < 0)
4666 ret = std_nic_on(pbpctl_dev);
4668 ret = std_nic_off(pbpctl_dev);
4669 cmnd_off(pbpctl_dev);
4673 int get_std_nic_fn(bpctl_dev_t *pbpctl_dev)
4678 return std_nic_status(pbpctl_dev);
4681 int set_tap_fn(bpctl_dev_t *pbpctl_dev, int tap_mode)
4686 if ((pbpctl_dev->bp_caps & TAP_CAP) && ((cmnd_on(pbpctl_dev)) >= 0)) {
4688 tap_off(pbpctl_dev);
4691 cmnd_off(pbpctl_dev);
4697 int get_tap_fn(bpctl_dev_t *pbpctl_dev)
4702 return tap_status(pbpctl_dev);
4705 int set_tap_pwup_fn(bpctl_dev_t *pbpctl_dev, int tap_mode)
4711 if ((pbpctl_dev->bp_caps & TAP_PWUP_CTL_CAP)
4712 && ((cmnd_on(pbpctl_dev)) >= 0)) {
4714 ret = tap_state_pwron(pbpctl_dev);
4716 ret = normal_state_pwron(pbpctl_dev);
4717 cmnd_off(pbpctl_dev);
4723 int get_tap_pwup_fn(bpctl_dev_t *pbpctl_dev)
4729 if ((ret = default_pwron_tap_status(pbpctl_dev)) < 0)
4731 return ((ret == 0) ? 1 : 0);
4734 int get_tap_change_fn(bpctl_dev_t *pbpctl_dev)
4739 return tap_change_status(pbpctl_dev);
4742 int set_dis_tap_fn(bpctl_dev_t *pbpctl_dev, int dis_param)
4748 if ((pbpctl_dev->bp_caps & TAP_DIS_CAP) && ((cmnd_on(pbpctl_dev)) >= 0)) {
4750 ret = dis_tap_cap(pbpctl_dev);
4752 ret = en_tap_cap(pbpctl_dev);
4753 cmnd_off(pbpctl_dev);
4759 int get_dis_tap_fn(bpctl_dev_t *pbpctl_dev)
4764 return dis_tap_cap_status(pbpctl_dev);
4767 int set_disc_fn(bpctl_dev_t *pbpctl_dev, int disc_mode)
4772 if ((pbpctl_dev->bp_caps & DISC_CAP) && ((cmnd_on(pbpctl_dev)) >= 0)) {
4774 disc_off(pbpctl_dev);
4776 disc_on(pbpctl_dev);
4777 cmnd_off(pbpctl_dev);
4784 int get_disc_fn(bpctl_dev_t *pbpctl_dev)
4790 ret = disc_status(pbpctl_dev);
4795 int set_disc_pwup_fn(bpctl_dev_t *pbpctl_dev, int disc_mode)
4801 if ((pbpctl_dev->bp_caps & DISC_PWUP_CTL_CAP)
4802 && ((cmnd_on(pbpctl_dev)) >= 0)) {
4804 ret = disc_state_pwron(pbpctl_dev);
4806 ret = normal_state_pwron(pbpctl_dev);
4807 cmnd_off(pbpctl_dev);
4813 int get_disc_pwup_fn(bpctl_dev_t *pbpctl_dev)
4819 ret = default_pwron_disc_status(pbpctl_dev);
4820 return (ret == 0 ? 1 : (ret < 0 ? BP_NOT_CAP : 0));
4823 int get_disc_change_fn(bpctl_dev_t *pbpctl_dev)
4829 ret = disc_change_status(pbpctl_dev);
4833 int set_dis_disc_fn(bpctl_dev_t *pbpctl_dev, int dis_param)
4839 if ((pbpctl_dev->bp_caps & DISC_DIS_CAP)
4840 && ((cmnd_on(pbpctl_dev)) >= 0)) {
4842 ret = dis_disc_cap(pbpctl_dev);
4844 ret = en_disc_cap(pbpctl_dev);
4845 cmnd_off(pbpctl_dev);
4851 int get_dis_disc_fn(bpctl_dev_t *pbpctl_dev)
4857 ret = dis_disc_cap_status(pbpctl_dev);
4862 int set_disc_port_fn(bpctl_dev_t *pbpctl_dev, int disc_mode)
4864 int ret = BP_NOT_CAP;
4869 ret = disc_port_off(pbpctl_dev);
4871 ret = disc_port_on(pbpctl_dev);
4876 int get_disc_port_fn(bpctl_dev_t *pbpctl_dev)
4881 return disc_port_status(pbpctl_dev);
4884 int set_disc_port_pwup_fn(bpctl_dev_t *pbpctl_dev, int disc_mode)
4886 int ret = BP_NOT_CAP;
4891 ret = normal_port_state_pwron(pbpctl_dev);
4893 ret = disc_port_state_pwron(pbpctl_dev);
4898 int get_disc_port_pwup_fn(bpctl_dev_t *pbpctl_dev)
4904 if ((ret = default_pwron_disc_port_status(pbpctl_dev)) < 0)
4906 return ((ret == 0) ? 1 : 0);
4909 int get_wd_exp_mode_fn(bpctl_dev_t *pbpctl_dev)
4914 return wdt_exp_mode_status(pbpctl_dev);
4917 int set_wd_exp_mode_fn(bpctl_dev_t *pbpctl_dev, int param)
4922 return wdt_exp_mode(pbpctl_dev, param);
4925 int reset_cont_fn(bpctl_dev_t *pbpctl_dev)
4931 if ((ret = cmnd_on(pbpctl_dev)) < 0)
4933 return reset_cont(pbpctl_dev);
4936 int set_tx_fn(bpctl_dev_t *pbpctl_dev, int tx_state)
4939 bpctl_dev_t *pbpctl_dev_b = NULL;
4943 if ((pbpctl_dev->bp_caps & TPL_CAP) &&
4944 (pbpctl_dev->bp_caps & SW_CTL_CAP)) {
4945 if ((pbpctl_dev->bp_tpl_flag))
4947 } else if ((pbpctl_dev_b = get_master_port_fn(pbpctl_dev))) {
4948 if ((pbpctl_dev_b->bp_caps & TPL_CAP) &&
4949 (pbpctl_dev_b->bp_tpl_flag))
4952 return set_tx(pbpctl_dev, tx_state);
4955 int set_bp_force_link_fn(int dev_num, int tx_state)
4957 static bpctl_dev_t *bpctl_dev_curr;
4959 if ((dev_num < 0) || (dev_num > device_num)
4960 || (bpctl_dev_arr[dev_num].pdev == NULL))
4962 bpctl_dev_curr = &bpctl_dev_arr[dev_num];
4964 return set_bp_force_link(bpctl_dev_curr, tx_state);
4967 int set_wd_autoreset_fn(bpctl_dev_t *pbpctl_dev, int param)
4972 return set_bypass_wd_auto(pbpctl_dev, param);
4975 int get_wd_autoreset_fn(bpctl_dev_t *pbpctl_dev)
4980 return get_bypass_wd_auto(pbpctl_dev);
4984 int set_bp_self_test_fn(bpctl_dev_t *pbpctl_dev, int param)
4989 return set_bp_self_test(pbpctl_dev, param);
4992 int get_bp_self_test_fn(bpctl_dev_t *pbpctl_dev)
4997 return get_bp_self_test(pbpctl_dev);
5002 int get_bypass_caps_fn(bpctl_dev_t *pbpctl_dev)
5007 return pbpctl_dev->bp_caps;
5011 int get_bypass_slave_fn(bpctl_dev_t *pbpctl_dev, bpctl_dev_t **pbpctl_dev_out)
5017 if ((pbpctl_dev->func == 0) || (pbpctl_dev->func == 2)) {
5019 ((bpctl_dev_arr[idx_dev].pdev != NULL)
5020 && (idx_dev < device_num)); idx_dev++) {
5021 if ((bpctl_dev_arr[idx_dev].bus == pbpctl_dev->bus)
5022 && (bpctl_dev_arr[idx_dev].slot ==
5023 pbpctl_dev->slot)) {
5024 if ((pbpctl_dev->func == 0)
5025 && (bpctl_dev_arr[idx_dev].func == 1)) {
5027 &bpctl_dev_arr[idx_dev];
5030 if ((pbpctl_dev->func == 2) &&
5031 (bpctl_dev_arr[idx_dev].func == 3)) {
5033 &bpctl_dev_arr[idx_dev];
5043 int is_bypass(bpctl_dev_t *pbpctl_dev)
5048 if ((pbpctl_dev->func == 0) || (pbpctl_dev->func == 2))
5054 int get_tx_fn(bpctl_dev_t *pbpctl_dev)
5056 bpctl_dev_t *pbpctl_dev_b = NULL;
5060 if ((pbpctl_dev->bp_caps & TPL_CAP) &&
5061 (pbpctl_dev->bp_caps & SW_CTL_CAP)) {
5062 if ((pbpctl_dev->bp_tpl_flag))
5064 } else if ((pbpctl_dev_b = get_master_port_fn(pbpctl_dev))) {
5065 if ((pbpctl_dev_b->bp_caps & TPL_CAP) &&
5066 (pbpctl_dev_b->bp_tpl_flag))
5069 return tx_status(pbpctl_dev);
5072 int get_bp_force_link_fn(int dev_num)
5074 static bpctl_dev_t *bpctl_dev_curr;
5076 if ((dev_num < 0) || (dev_num > device_num)
5077 || (bpctl_dev_arr[dev_num].pdev == NULL))
5079 bpctl_dev_curr = &bpctl_dev_arr[dev_num];
5081 return bp_force_link_status(bpctl_dev_curr);
5084 static int get_bypass_link_status(bpctl_dev_t *pbpctl_dev)
5089 if (pbpctl_dev->media_type == bp_fiber)
5090 return ((BPCTL_READ_REG(pbpctl_dev, CTRL) &
5091 BPCTLI_CTRL_SWDPIN1));
5093 return ((BPCTL_READ_REG(pbpctl_dev, STATUS) &
5098 static void bp_tpl_timer_fn(unsigned long param)
5100 bpctl_dev_t *pbpctl_dev = (bpctl_dev_t *) param;
5101 uint32_t link1, link2;
5102 bpctl_dev_t *pbpctl_dev_b = NULL;
5104 if (!(pbpctl_dev_b = get_status_port_fn(pbpctl_dev)))
5107 if (!pbpctl_dev->bp_tpl_flag) {
5108 set_tx(pbpctl_dev_b, 1);
5109 set_tx(pbpctl_dev, 1);
5112 link1 = get_bypass_link_status(pbpctl_dev);
5114 link2 = get_bypass_link_status(pbpctl_dev_b);
5115 if ((link1) && (tx_status(pbpctl_dev))) {
5116 if ((!link2) && (tx_status(pbpctl_dev_b))) {
5117 set_tx(pbpctl_dev, 0);
5118 } else if (!tx_status(pbpctl_dev_b)) {
5119 set_tx(pbpctl_dev_b, 1);
5121 } else if ((!link1) && (tx_status(pbpctl_dev))) {
5122 if ((link2) && (tx_status(pbpctl_dev_b))) {
5123 set_tx(pbpctl_dev_b, 0);
5125 } else if ((link1) && (!tx_status(pbpctl_dev))) {
5126 if ((link2) && (tx_status(pbpctl_dev_b))) {
5127 set_tx(pbpctl_dev, 1);
5129 } else if ((!link1) && (!tx_status(pbpctl_dev))) {
5130 if ((link2) && (tx_status(pbpctl_dev_b))) {
5131 set_tx(pbpctl_dev, 1);
5135 mod_timer(&pbpctl_dev->bp_tpl_timer, jiffies + BP_LINK_MON_DELAY * HZ);
5138 void remove_bypass_tpl_auto(bpctl_dev_t *pbpctl_dev)
5140 bpctl_dev_t *pbpctl_dev_b = NULL;
5143 pbpctl_dev_b = get_status_port_fn(pbpctl_dev);
5145 if (pbpctl_dev->bp_caps & TPL_CAP) {
5146 del_timer_sync(&pbpctl_dev->bp_tpl_timer);
5147 pbpctl_dev->bp_tpl_flag = 0;
5148 pbpctl_dev_b = get_status_port_fn(pbpctl_dev);
5150 set_tx(pbpctl_dev_b, 1);
5151 set_tx(pbpctl_dev, 1);
5156 int init_bypass_tpl_auto(bpctl_dev_t *pbpctl_dev)
5160 if (pbpctl_dev->bp_caps & TPL_CAP) {
5161 init_timer(&pbpctl_dev->bp_tpl_timer);
5162 pbpctl_dev->bp_tpl_timer.function = &bp_tpl_timer_fn;
5163 pbpctl_dev->bp_tpl_timer.data = (unsigned long)pbpctl_dev;
5169 int set_bypass_tpl_auto(bpctl_dev_t *pbpctl_dev, unsigned int param)
5173 if (pbpctl_dev->bp_caps & TPL_CAP) {
5174 if ((param) && (!pbpctl_dev->bp_tpl_flag)) {
5175 pbpctl_dev->bp_tpl_flag = param;
5176 mod_timer(&pbpctl_dev->bp_tpl_timer, jiffies + 1);
5179 if ((!param) && (pbpctl_dev->bp_tpl_flag))
5180 remove_bypass_tpl_auto(pbpctl_dev);
5187 int get_bypass_tpl_auto(bpctl_dev_t *pbpctl_dev)
5191 if (pbpctl_dev->bp_caps & TPL_CAP) {
5192 return pbpctl_dev->bp_tpl_flag;
5197 int set_tpl_fn(bpctl_dev_t *pbpctl_dev, int tpl_mode)
5200 bpctl_dev_t *pbpctl_dev_b = NULL;
5204 pbpctl_dev_b = get_status_port_fn(pbpctl_dev);
5206 if (pbpctl_dev->bp_caps & TPL_CAP) {
5208 if ((pbpctl_dev_b = get_status_port_fn(pbpctl_dev)))
5209 set_tx(pbpctl_dev_b, 1);
5210 set_tx(pbpctl_dev, 1);
5212 if ((TPL_IF_SERIES(pbpctl_dev->subdevice)) ||
5213 (pbpctl_dev->bp_caps_ex & TPL2_CAP_EX)) {
5214 pbpctl_dev->bp_tpl_flag = tpl_mode;
5216 tpl_hw_off(pbpctl_dev);
5218 tpl_hw_on(pbpctl_dev);
5220 set_bypass_tpl_auto(pbpctl_dev, tpl_mode);
5226 int get_tpl_fn(bpctl_dev_t *pbpctl_dev)
5228 int ret = BP_NOT_CAP;
5232 if (pbpctl_dev->bp_caps & TPL_CAP) {
5233 if (pbpctl_dev->bp_caps_ex & TPL2_CAP_EX)
5234 return tpl2_flag_status(pbpctl_dev);
5235 ret = pbpctl_dev->bp_tpl_flag;
5240 int set_bp_wait_at_pwup_fn(bpctl_dev_t *pbpctl_dev, int tap_mode)
5245 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
5246 /* bp_lock(pbp_device_block); */
5247 cmnd_on(pbpctl_dev);
5249 bp_wait_at_pwup_dis(pbpctl_dev);
5251 bp_wait_at_pwup_en(pbpctl_dev);
5252 cmnd_off(pbpctl_dev);
5254 /* bp_unlock(pbp_device_block); */
5260 int get_bp_wait_at_pwup_fn(bpctl_dev_t *pbpctl_dev)
5266 /* bp_lock(pbp_device_block); */
5267 ret = bp_wait_at_pwup_status(pbpctl_dev);
5268 /* bp_unlock(pbp_device_block); */
5273 int set_bp_hw_reset_fn(bpctl_dev_t *pbpctl_dev, int tap_mode)
5278 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
5279 /* bp_lock(pbp_device_block); */
5280 cmnd_on(pbpctl_dev);
5283 bp_hw_reset_dis(pbpctl_dev);
5285 bp_hw_reset_en(pbpctl_dev);
5286 cmnd_off(pbpctl_dev);
5287 /* bp_unlock(pbp_device_block); */
5293 int get_bp_hw_reset_fn(bpctl_dev_t *pbpctl_dev)
5299 /* bp_lock(pbp_device_block); */
5300 ret = bp_hw_reset_status(pbpctl_dev);
5302 /* bp_unlock(pbp_device_block); */
5308 int get_bypass_info_fn(bpctl_dev_t *pbpctl_dev, char *dev_name,
5313 if (!is_bypass_fn(pbpctl_dev))
5315 strcpy(dev_name, pbpctl_dev->name);
5316 *add_param = pbpctl_dev->bp_fw_ver;
5320 int get_dev_idx_bsf(int bus, int slot, int func)
5324 ((bpctl_dev_arr[idx_dev].pdev != NULL) && (idx_dev < device_num));
5326 if ((bus == bpctl_dev_arr[idx_dev].bus)
5327 && (slot == bpctl_dev_arr[idx_dev].slot)
5328 && (func == bpctl_dev_arr[idx_dev].func))
5335 static void str_low(char *str)
5339 for (i = 0; i < strlen(str); i++)
5340 if ((str[i] >= 65) && (str[i] <= 90))
5344 static unsigned long str_to_hex(char *p)
5346 unsigned long hex = 0;
5347 unsigned long length = strlen(p), shift = 0;
5348 unsigned char dig = 0;
5358 dig = dig < 'a' ? (dig - '0') : (dig - 'a' + 0xa);
5359 hex |= (dig << shift);
5365 static int get_dev_idx(int ifindex)
5370 ((bpctl_dev_arr[idx_dev].pdev != NULL) && (idx_dev < device_num));
5372 if (ifindex == bpctl_dev_arr[idx_dev].ifindex)
5379 static bpctl_dev_t *get_dev_idx_p(int ifindex)
5384 ((bpctl_dev_arr[idx_dev].pdev != NULL) && (idx_dev < device_num));
5386 if (ifindex == bpctl_dev_arr[idx_dev].ifindex)
5387 return &bpctl_dev_arr[idx_dev];
5393 static void if_scan_init(void)
5396 struct net_device *dev;
5398 /* rcu_read_lock(); */
5400 /* rcu_read_lock(); */
5402 for_each_netdev(&init_net, dev) {
5404 struct ethtool_drvinfo drvinfo;
5409 int bus = 0, slot = 0, func = 0;
5410 ifindex = dev->ifindex;
5413 memset(&drvinfo, 0, sizeof(struct ethtool_drvinfo));
5415 if (dev->ethtool_ops && dev->ethtool_ops->get_drvinfo) {
5416 memset(&drvinfo, 0, sizeof(drvinfo));
5417 dev->ethtool_ops->get_drvinfo(dev, &drvinfo);
5420 if (!strcmp(drvinfo.bus_info, "N/A"))
5422 memcpy(&cbuf, drvinfo.bus_info, 32);
5425 while (*buf++ != ':') ;
5426 for (i = 0; i < 10; i++, buf++) {
5433 bus = str_to_hex(res);
5436 for (i = 0; i < 10; i++, buf++) {
5443 slot = str_to_hex(res);
5444 func = str_to_hex(buf);
5445 idx_dev = get_dev_idx_bsf(bus, slot, func);
5447 if (idx_dev != -1) {
5449 bpctl_dev_arr[idx_dev].ifindex = ifindex;
5450 bpctl_dev_arr[idx_dev].ndev = dev;
5455 /* rtnl_unlock(); */
5456 /* rcu_read_unlock(); */
5460 static long device_ioctl(struct file *file, /* see include/linux/fs.h */
5461 unsigned int ioctl_num, /* number and param for ioctl */
5462 unsigned long ioctl_param)
5464 struct bpctl_cmd bpctl_cmd;
5466 bpctl_dev_t *pbpctl_dev_out;
5467 void __user *argp = (void __user *)ioctl_param;
5469 unsigned long flags;
5471 static bpctl_dev_t *pbpctl_dev;
5473 /* lock_kernel(); */
5475 /* local_irq_save(flags); */
5476 /* if(!spin_trylock_irqsave(&bpvm_lock)){
5477 local_irq_restore(flags);
5482 /* spin_lock_irqsave(&bpvm_lock, flags); */
5485 * Switch according to the ioctl called
5487 if (ioctl_num == IOCTL_TX_MSG(IF_SCAN)) {
5492 if (copy_from_user(&bpctl_cmd, argp, sizeof(struct bpctl_cmd))) {
5498 if (ioctl_num == IOCTL_TX_MSG(GET_DEV_NUM)) {
5499 bpctl_cmd.out_param[0] = device_num;
5501 (argp, (void *)&bpctl_cmd, sizeof(struct bpctl_cmd))) {
5510 /* preempt_disable(); */
5511 local_irq_save(flags);
5512 if (!spin_trylock(&bpvm_lock)) {
5513 local_irq_restore(flags);
5518 /* preempt_disable();
5520 spin_lock_irqsave(&bpvm_lock, flags);
5522 if ((bpctl_cmd.in_param[5]) ||
5523 (bpctl_cmd.in_param[6]) || (bpctl_cmd.in_param[7]))
5524 dev_idx = get_dev_idx_bsf(bpctl_cmd.in_param[5],
5525 bpctl_cmd.in_param[6],
5526 bpctl_cmd.in_param[7]);
5527 else if (bpctl_cmd.in_param[1] == 0)
5528 dev_idx = bpctl_cmd.in_param[0];
5530 dev_idx = get_dev_idx(bpctl_cmd.in_param[1]);
5532 if (dev_idx < 0 || dev_idx > device_num) {
5534 preempt_enable(); */
5536 /* preempt_enable();
5537 rcu_read_unlock(); */
5538 spin_unlock_irqrestore(&bpvm_lock, flags);
5542 bpctl_cmd.out_param[0] = bpctl_dev_arr[dev_idx].bus;
5543 bpctl_cmd.out_param[1] = bpctl_dev_arr[dev_idx].slot;
5544 bpctl_cmd.out_param[2] = bpctl_dev_arr[dev_idx].func;
5545 bpctl_cmd.out_param[3] = bpctl_dev_arr[dev_idx].ifindex;
5547 if ((bpctl_dev_arr[dev_idx].bp_10gb)
5548 && (!(bpctl_dev_arr[dev_idx].ifindex))) {
5549 printk("Please load network driver for %s adapter!\n",
5550 bpctl_dev_arr[dev_idx].name);
5551 bpctl_cmd.status = -1;
5553 /* preempt_enable(); */
5554 /* rcu_read_unlock(); */
5555 spin_unlock_irqrestore(&bpvm_lock, flags);
5559 if ((bpctl_dev_arr[dev_idx].bp_10gb) && (bpctl_dev_arr[dev_idx].ndev)) {
5560 if (!(bpctl_dev_arr[dev_idx].ndev->flags & IFF_UP)) {
5561 if (!(bpctl_dev_arr[dev_idx].ndev->flags & IFF_UP)) {
5563 ("Please bring up network interfaces for %s adapter!\n",
5564 bpctl_dev_arr[dev_idx].name);
5565 bpctl_cmd.status = -1;
5567 /* preempt_enable(); */
5568 /* rcu_read_unlock(); */
5569 spin_unlock_irqrestore(&bpvm_lock, flags);
5576 if ((dev_idx < 0) || (dev_idx > device_num)
5577 || (bpctl_dev_arr[dev_idx].pdev == NULL)) {
5578 bpctl_cmd.status = -1;
5582 pbpctl_dev = &bpctl_dev_arr[dev_idx];
5584 switch (ioctl_num) {
5585 case IOCTL_TX_MSG(SET_BYPASS_PWOFF):
5587 set_bypass_pwoff_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5590 case IOCTL_TX_MSG(GET_BYPASS_PWOFF):
5591 bpctl_cmd.status = get_bypass_pwoff_fn(pbpctl_dev);
5594 case IOCTL_TX_MSG(SET_BYPASS_PWUP):
5596 set_bypass_pwup_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5599 case IOCTL_TX_MSG(GET_BYPASS_PWUP):
5600 bpctl_cmd.status = get_bypass_pwup_fn(pbpctl_dev);
5603 case IOCTL_TX_MSG(SET_BYPASS_WD):
5605 set_bypass_wd_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5608 case IOCTL_TX_MSG(GET_BYPASS_WD):
5610 get_bypass_wd_fn(pbpctl_dev, (int *)&(bpctl_cmd.data[0]));
5613 case IOCTL_TX_MSG(GET_WD_EXPIRE_TIME):
5615 get_wd_expire_time_fn(pbpctl_dev,
5616 (int *)&(bpctl_cmd.data[0]));
5619 case IOCTL_TX_MSG(RESET_BYPASS_WD_TIMER):
5620 bpctl_cmd.status = reset_bypass_wd_timer_fn(pbpctl_dev);
5623 case IOCTL_TX_MSG(GET_WD_SET_CAPS):
5624 bpctl_cmd.status = get_wd_set_caps_fn(pbpctl_dev);
5627 case IOCTL_TX_MSG(SET_STD_NIC):
5629 set_std_nic_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5632 case IOCTL_TX_MSG(GET_STD_NIC):
5633 bpctl_cmd.status = get_std_nic_fn(pbpctl_dev);
5636 case IOCTL_TX_MSG(SET_TAP):
5638 set_tap_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5641 case IOCTL_TX_MSG(GET_TAP):
5642 bpctl_cmd.status = get_tap_fn(pbpctl_dev);
5645 case IOCTL_TX_MSG(GET_TAP_CHANGE):
5646 bpctl_cmd.status = get_tap_change_fn(pbpctl_dev);
5649 case IOCTL_TX_MSG(SET_DIS_TAP):
5651 set_dis_tap_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5654 case IOCTL_TX_MSG(GET_DIS_TAP):
5655 bpctl_cmd.status = get_dis_tap_fn(pbpctl_dev);
5658 case IOCTL_TX_MSG(SET_TAP_PWUP):
5660 set_tap_pwup_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5663 case IOCTL_TX_MSG(GET_TAP_PWUP):
5664 bpctl_cmd.status = get_tap_pwup_fn(pbpctl_dev);
5667 case IOCTL_TX_MSG(SET_WD_EXP_MODE):
5669 set_wd_exp_mode_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5672 case IOCTL_TX_MSG(GET_WD_EXP_MODE):
5673 bpctl_cmd.status = get_wd_exp_mode_fn(pbpctl_dev);
5676 case IOCTL_TX_MSG(GET_DIS_BYPASS):
5677 bpctl_cmd.status = get_dis_bypass_fn(pbpctl_dev);
5680 case IOCTL_TX_MSG(SET_DIS_BYPASS):
5682 set_dis_bypass_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5685 case IOCTL_TX_MSG(GET_BYPASS_CHANGE):
5686 bpctl_cmd.status = get_bypass_change_fn(pbpctl_dev);
5689 case IOCTL_TX_MSG(GET_BYPASS):
5690 bpctl_cmd.status = get_bypass_fn(pbpctl_dev);
5693 case IOCTL_TX_MSG(SET_BYPASS):
5695 set_bypass_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5698 case IOCTL_TX_MSG(GET_BYPASS_CAPS):
5699 bpctl_cmd.status = get_bypass_caps_fn(pbpctl_dev);
5700 /*preempt_enable(); */
5701 /*rcu_read_unlock();*/
5702 spin_unlock_irqrestore(&bpvm_lock, flags);
5704 (argp, (void *)&bpctl_cmd, sizeof(struct bpctl_cmd))) {
5705 /*unlock_bpctl(); */
5706 /*preempt_enable(); */
5712 case IOCTL_TX_MSG(GET_BYPASS_SLAVE):
5714 get_bypass_slave_fn(pbpctl_dev, &pbpctl_dev_out);
5715 if (bpctl_cmd.status == 1) {
5716 bpctl_cmd.out_param[4] = pbpctl_dev_out->bus;
5717 bpctl_cmd.out_param[5] = pbpctl_dev_out->slot;
5718 bpctl_cmd.out_param[6] = pbpctl_dev_out->func;
5719 bpctl_cmd.out_param[7] = pbpctl_dev_out->ifindex;
5723 case IOCTL_TX_MSG(IS_BYPASS):
5724 bpctl_cmd.status = is_bypass(pbpctl_dev);
5726 case IOCTL_TX_MSG(SET_TX):
5727 bpctl_cmd.status = set_tx_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5729 case IOCTL_TX_MSG(GET_TX):
5730 bpctl_cmd.status = get_tx_fn(pbpctl_dev);
5732 case IOCTL_TX_MSG(SET_WD_AUTORESET):
5734 set_wd_autoreset_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5737 case IOCTL_TX_MSG(GET_WD_AUTORESET):
5739 bpctl_cmd.status = get_wd_autoreset_fn(pbpctl_dev);
5741 case IOCTL_TX_MSG(SET_DISC):
5743 set_disc_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5745 case IOCTL_TX_MSG(GET_DISC):
5746 bpctl_cmd.status = get_disc_fn(pbpctl_dev);
5748 case IOCTL_TX_MSG(GET_DISC_CHANGE):
5749 bpctl_cmd.status = get_disc_change_fn(pbpctl_dev);
5751 case IOCTL_TX_MSG(SET_DIS_DISC):
5753 set_dis_disc_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5755 case IOCTL_TX_MSG(GET_DIS_DISC):
5756 bpctl_cmd.status = get_dis_disc_fn(pbpctl_dev);
5758 case IOCTL_TX_MSG(SET_DISC_PWUP):
5760 set_disc_pwup_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5762 case IOCTL_TX_MSG(GET_DISC_PWUP):
5763 bpctl_cmd.status = get_disc_pwup_fn(pbpctl_dev);
5766 case IOCTL_TX_MSG(GET_BYPASS_INFO):
5769 get_bypass_info_fn(pbpctl_dev, (char *)&bpctl_cmd.data,
5770 (char *)&bpctl_cmd.out_param[4]);
5773 case IOCTL_TX_MSG(SET_TPL):
5775 set_tpl_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5778 case IOCTL_TX_MSG(GET_TPL):
5779 bpctl_cmd.status = get_tpl_fn(pbpctl_dev);
5781 case IOCTL_TX_MSG(SET_BP_WAIT_AT_PWUP):
5783 set_bp_wait_at_pwup_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5786 case IOCTL_TX_MSG(GET_BP_WAIT_AT_PWUP):
5787 bpctl_cmd.status = get_bp_wait_at_pwup_fn(pbpctl_dev);
5789 case IOCTL_TX_MSG(SET_BP_HW_RESET):
5791 set_bp_hw_reset_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5794 case IOCTL_TX_MSG(GET_BP_HW_RESET):
5795 bpctl_cmd.status = get_bp_hw_reset_fn(pbpctl_dev);
5798 case IOCTL_TX_MSG(SET_BP_SELF_TEST):
5800 set_bp_self_test_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5803 case IOCTL_TX_MSG(GET_BP_SELF_TEST):
5804 bpctl_cmd.status = get_bp_self_test_fn(pbpctl_dev);
5809 case IOCTL_TX_MSG(SET_DISC_PORT):
5811 set_disc_port_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5814 case IOCTL_TX_MSG(GET_DISC_PORT):
5815 bpctl_cmd.status = get_disc_port_fn(pbpctl_dev);
5818 case IOCTL_TX_MSG(SET_DISC_PORT_PWUP):
5820 set_disc_port_pwup_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5823 case IOCTL_TX_MSG(GET_DISC_PORT_PWUP):
5824 bpctl_cmd.status = get_disc_port_pwup_fn(pbpctl_dev);
5827 case IOCTL_TX_MSG(SET_BP_FORCE_LINK):
5829 set_bp_force_link_fn(dev_idx, bpctl_cmd.in_param[2]);
5832 case IOCTL_TX_MSG(GET_BP_FORCE_LINK):
5833 bpctl_cmd.status = get_bp_force_link_fn(dev_idx);
5837 /* unlock_bpctl(); */
5840 /* preempt_enable(); */
5841 /* rcu_read_unlock();*/
5842 spin_unlock_irqrestore(&bpvm_lock, flags);
5845 /* unlock_bpctl(); */
5846 /* preempt_enable(); */
5848 /* rcu_read_unlock(); */
5849 spin_unlock_irqrestore(&bpvm_lock, flags);
5850 if (copy_to_user(argp, (void *)&bpctl_cmd, sizeof(struct bpctl_cmd)))
5854 /* unlock_kernel(); */
5855 /* spin_unlock_irqrestore(&bpvm_lock, flags); */
5857 /* unlock_kernel(); */
5861 struct file_operations Fops = {
5862 .owner = THIS_MODULE,
5863 .unlocked_ioctl = device_ioctl,
5864 .open = device_open,
5865 .release = device_release, /* a.k.a. close */
5869 #define PCI_DEVICE(vend,dev) \
5870 .vendor = (vend), .device = (dev), \
5871 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
5874 #define SILICOM_E1000BP_ETHERNET_DEVICE(device_id) {\
5875 PCI_DEVICE(SILICOM_VID, device_id)}
6037 typedef struct _bpmod_info_t {
6038 unsigned int vendor;
6039 unsigned int device;
6040 unsigned int subvendor;
6041 unsigned int subdevice;
6047 typedef struct _dev_desc {
6051 dev_desc_t dev_desc[] = {
6052 {"Silicom Bypass PXG2BPFI-SD series adapter"},
6053 {"Silicom Bypass PXG2BPFIL-SD series adapter"},
6054 {"Silicom Bypass PXG2BPFILX-SD series adapter"},
6055 {"Silicom Bypass PXG2BPFILLX-SD series adapter"},
6056 {"Silicom Bypass PXG2BPI-SD series adapter"},
6057 {"Silicom Bypass PXG2BPIG-SD series adapter"},
6058 {"Silicom Bypass PXG2TBFI-SD series adapter"},
6059 {"Silicom Bypass PXG4BPI-SD series adapter"},
6060 {"Silicom Bypass PXG4BPFI-SD series adapter"},
6061 {"Silicom Bypass PEG4BPI-SD series adapter"},
6062 {"Silicom Bypass PEG2BPI-SD series adapter"},
6063 {"Silicom Bypass PEG4BPIN-SD series adapter"},
6064 {"Silicom Bypass PEG2BPFI-SD series adapter"},
6065 {"Silicom Bypass PEG2BPFI-LX-SD series adapter"},
6066 {"Silicom Bypass PMCX2BPFI-SD series adapter"},
6067 {"Silicom Bypass PMCX2BPFI-N series adapter"},
6068 {"Intel Bypass PEG2BPII series adapter"},
6069 {"Intel Bypass PEG2BPFII series adapter"},
6070 {"Silicom Bypass PXG4BPFILX-SD series adapter"},
6071 {"Silicom Bypass PMCX2BPI-N series adapter"},
6072 {"Silicom Bypass PMCX4BPI-N series adapter"},
6073 {"Silicom Bypass PXG2BISC1-SD series adapter"},
6074 {"Silicom Bypass PEG2TBFI-SD series adapter"},
6075 {"Silicom Bypass PXG2TBI-SD series adapter"},
6076 {"Silicom Bypass PXG4BPFID-SD series adapter"},
6077 {"Silicom Bypass PEG4BPFI-SD series adapter"},
6078 {"Silicom Bypass PEG4BPIPT-SD series adapter"},
6079 {"Silicom Bypass PXG6BPI-SD series adapter"},
6080 {"Silicom Bypass PEG4BPIL-SD series adapter"},
6081 {"Silicom Bypass PMCX2BPI-N2 series adapter"},
6082 {"Silicom Bypass PMCX4BPI-N2 series adapter"},
6083 {"Silicom Bypass PMCX2BPI-SD series adapter"},
6084 {"Silicom Bypass PEG2BPFID-SD series adapter"},
6085 {"Silicom Bypass PEG2BPFIDLX-SD series adapter"},
6086 {"Silicom Bypass PMCX4BPI-SD series adapter"},
6087 {"Silicom Bypass MEG2BPFILN-SD series adapter"},
6088 {"Silicom Bypass MEG2BPFINX-SD series adapter"},
6089 {"Silicom Bypass PEG4BPFILX-SD series adapter"},
6090 {"Silicom Bypass PE10G2BPISR-SD series adapter"},
6091 {"Silicom Bypass PE10G2BPILR-SD series adapter"},
6092 {"Silicom Bypass MHIO8AD-SD series adapter"},
6093 {"Silicom Bypass PE10G2BPICX4-SD series adapter"},
6094 {"Silicom Bypass PEG2BPI5-SD series adapter"},
6095 {"Silicom Bypass PEG6BPI5-SD series adapter"},
6096 {"Silicom Bypass PEG4BPFI5-SD series adapter"},
6097 {"Silicom Bypass PEG4BPFI5LX-SD series adapter"},
6098 {"Silicom Bypass MEG2BPFILXLN-SD series adapter"},
6099 {"Silicom Bypass PEG2BPIX1-SD series adapter"},
6100 {"Silicom Bypass MEG2BPFILXNX-SD series adapter"},
6101 {"Silicom Bypass XE10G2BPIT-SD series adapter"},
6102 {"Silicom Bypass XE10G2BPICX4-SD series adapter"},
6103 {"Silicom Bypass XE10G2BPISR-SD series adapter"},
6104 {"Silicom Bypass XE10G2BPILR-SD series adapter"},
6105 {"Intel Bypass PEG2BPFII0 series adapter"},
6106 {"Silicom Bypass XE10G2BPIXR series adapter"},
6107 {"Silicom Bypass PE10G2DBISR series adapter"},
6108 {"Silicom Bypass PEG2BI5SC6 series adapter"},
6109 {"Silicom Bypass PEG6BPI5FC series adapter"},
6111 {"Silicom Bypass PE10G2BPTCX4 series adapter"},
6112 {"Silicom Bypass PE10G2BPTSR series adapter"},
6113 {"Silicom Bypass PE10G2BPTLR series adapter"},
6114 {"Silicom Bypass PE10G2BPTT series adapter"},
6115 {"Silicom Bypass PEG4BPI6 series adapter"},
6116 {"Silicom Bypass PEG4BPFI6 series adapter"},
6117 {"Silicom Bypass PEG4BPFI6LX series adapter"},
6118 {"Silicom Bypass PEG4BPFI6ZX series adapter"},
6119 {"Silicom Bypass PEG2BPI6 series adapter"},
6120 {"Silicom Bypass PEG2BPFI6 series adapter"},
6121 {"Silicom Bypass PEG2BPFI6LX series adapter"},
6122 {"Silicom Bypass PEG2BPFI6ZX series adapter"},
6123 {"Silicom Bypass PEG2BPFI6FLXM series adapter"},
6124 {"Silicom Bypass PEG4BPI6FC series adapter"},
6125 {"Silicom Bypass PEG4BPFI6FC series adapter"},
6126 {"Silicom Bypass PEG4BPFI6FCLX series adapter"},
6127 {"Silicom Bypass PEG4BPFI6FCZX series adapter"},
6128 {"Silicom Bypass PEG6BPI6 series adapter"},
6129 {"Silicom Bypass PEG2BPI6SC6 series adapter"},
6130 {"Silicom Bypass MEG2BPI6 series adapter"},
6131 {"Silicom Bypass XEG2BPI6 series adapter"},
6132 {"Silicom Bypass MEG4BPI6 series adapter"},
6133 {"Silicom Bypass PEG2BPFI5-SD series adapter"},
6134 {"Silicom Bypass PEG2BPFI5LX-SD series adapter"},
6135 {"Silicom Bypass PXEG4BPFI-SD series adapter"},
6136 {"Silicom Bypass MxEG2BPI6 series adapter"},
6137 {"Silicom Bypass MxEG2BPFI6 series adapter"},
6138 {"Silicom Bypass MxEG2BPFI6LX series adapter"},
6139 {"Silicom Bypass MxEG2BPFI6ZX series adapter"},
6140 {"Silicom Bypass MxEG4BPI6 series adapter"},
6141 {"Silicom Bypass MxEG4BPFI6 series adapter"},
6142 {"Silicom Bypass MxEG4BPFI6LX series adapter"},
6143 {"Silicom Bypass MxEG4BPFI6ZX series adapter"},
6144 {"Silicom Bypass MxEG6BPI6 series adapter"},
6145 {"Silicom Bypass MxE2G4BPi80 series adapter"},
6146 {"Silicom Bypass MxE2G4BPFi80 series adapter"},
6147 {"Silicom Bypass MxE2G4BPFi80LX series adapter"},
6148 {"Silicom Bypass MxE2G4BPFi80ZX series adapter"},
6150 {"Silicom Bypass PE210G2SPI9 series adapter"},
6152 {"Silicom Bypass MxE210G2BPI9CX4 series adapter"},
6153 {"Silicom Bypass MxE210G2BPI9SR series adapter"},
6154 {"Silicom Bypass MxE210G2BPI9LR series adapter"},
6155 {"Silicom Bypass MxE210G2BPI9T series adapter"},
6157 {"Silicom Bypass PE210G2BPI9CX4 series adapter"},
6158 {"Silicom Bypass PE210G2BPI9SR series adapter"},
6159 {"Silicom Bypass PE210G2BPI9LR series adapter"},
6160 {"Silicom Bypass PE210G2BPI9T series adapter"},
6162 {"Silicom Bypass M2EG2BPFI6 series adapter"},
6163 {"Silicom Bypass M2EG2BPFI6LX series adapter"},
6164 {"Silicom Bypass M2EG2BPFI6ZX series adapter"},
6165 {"Silicom Bypass M2EG4BPI6 series adapter"},
6166 {"Silicom Bypass M2EG4BPFI6 series adapter"},
6167 {"Silicom Bypass M2EG4BPFI6LX series adapter"},
6168 {"Silicom Bypass M2EG4BPFI6ZX series adapter"},
6169 {"Silicom Bypass M2EG6BPI6 series adapter"},
6171 {"Silicom Bypass PEG2DBI6 series adapter"},
6172 {"Silicom Bypass PEG2DBFI6 series adapter"},
6173 {"Silicom Bypass PEG2DBFI6LX series adapter"},
6174 {"Silicom Bypass PEG2DBFI6ZX series adapter"},
6176 {"Silicom Bypass PE2G4BPi80 series adapter"},
6177 {"Silicom Bypass PE2G4BPFi80 series adapter"},
6178 {"Silicom Bypass PE2G4BPFi80LX series adapter"},
6179 {"Silicom Bypass PE2G4BPFi80ZX series adapter"},
6181 {"Silicom Bypass PE2G4BPi80L series adapter"},
6182 {"Silicom Bypass MxE2G8BPi80A series adapter"},
6184 {"Silicom Bypass PE2G2BPi35 series adapter"},
6185 {"Silicom Bypass PAC1200BPi35 series adapter"},
6186 {"Silicom Bypass PE2G2BPFi35 series adapter"},
6187 {"Silicom Bypass PE2G2BPFi35LX series adapter"},
6188 {"Silicom Bypass PE2G2BPFi35ZX series adapter"},
6190 {"Silicom Bypass PE2G4BPi35 series adapter"},
6191 {"Silicom Bypass PE2G4BPi35L series adapter"},
6192 {"Silicom Bypass PE2G4BPFi35 series adapter"},
6193 {"Silicom Bypass PE2G4BPFi35LX series adapter"},
6194 {"Silicom Bypass PE2G4BPFi35ZX series adapter"},
6196 {"Silicom Bypass PE2G6BPi35 series adapter"},
6197 {"Silicom Bypass PE2G6BPi35CX series adapter"},
6199 {"Silicom Bypass PE2G2BPi80 series adapter"},
6200 {"Silicom Bypass PE2G2BPFi80 series adapter"},
6201 {"Silicom Bypass PE2G2BPFi80LX series adapter"},
6202 {"Silicom Bypass PE2G2BPFi80ZX series adapter"},
6204 {"Silicom Bypass M2E10G2BPI9CX4 series adapter"},
6205 {"Silicom Bypass M2E10G2BPI9SR series adapter"},
6206 {"Silicom Bypass M2E10G2BPI9LR series adapter"},
6207 {"Silicom Bypass M2E10G2BPI9T series adapter"},
6208 {"Silicom Bypass MxE2G8BPi80 series adapter"},
6209 {"Silicom Bypass PE210G2DBi9SR series adapter"},
6210 {"Silicom Bypass PE210G2DBi9SRRB series adapter"},
6211 {"Silicom Bypass PE210G2DBi9LR series adapter"},
6212 {"Silicom Bypass PE210G2DBi9LRRB series adapter"},
6213 {"Silicom Bypass PE310G4DBi9-SR series adapter"},
6214 {"Silicom Bypass PE310G4BPi9T series adapter"},
6215 {"Silicom Bypass PE310G4BPi9SR series adapter"},
6216 {"Silicom Bypass PE310G4BPi9LR series adapter"},
6217 {"Silicom Bypass PE210G2BPi40T series adapter"},
6221 static bpmod_info_t tx_ctl_pci_tbl[] = {
6222 {0x8086, 0x107a, SILICOM_SVID, SILICOM_PXG2BPFI_SSID, PXG2BPFI,
6224 {0x8086, 0x107a, SILICOM_SVID, SILICOM_PXG2BPFIL_SSID, PXG2BPFIL,
6226 {0x8086, 0x107a, SILICOM_SVID, SILICOM_PXG2BPFILX_SSID, PXG2BPFILX,
6228 {0x8086, 0x107a, SILICOM_SVID, SILICOM_PXG2BPFILLX_SSID, PXG2BPFILLX,
6230 {0x8086, 0x1010, SILICOM_SVID, SILICOM_PXGBPI_SSID, PXGBPI,
6232 {0x8086, 0x1079, SILICOM_SVID, SILICOM_PXGBPIG_SSID, PXGBPIG,
6234 {0x8086, 0x107a, SILICOM_SVID, SILICOM_PXG2TBFI_SSID, PXG2TBFI,
6236 {0x8086, 0x1079, SILICOM_SVID, SILICOM_PXG4BPI_SSID, PXG4BPI,
6238 {0x8086, 0x107a, SILICOM_SVID, SILICOM_PXG4BPFI_SSID, PXG4BPFI,
6240 {0x8086, 0x107a, SILICOM_SVID, SILICOM_PXG4BPFILX_SSID, PXG4BPFILX,
6242 {0x8086, 0x1079, SILICOM_SVID, SILICOM_PEG4BPI_SSID, PEG4BPI,
6244 {0x8086, 0x105e, SILICOM_SVID, SILICOM_PEG2BPI_SSID, PEG2BPI,
6246 {0x8086, 0x105e, SILICOM_SVID, SILICOM_PEG4BPIN_SSID, PEG4BPIN,
6248 {0x8086, 0x105f, SILICOM_SVID, SILICOM_PEG2BPFI_SSID, PEG2BPFI,
6250 {0x8086, 0x105f, SILICOM_SVID, SILICOM_PEG2BPFILX_SSID, PEG2BPFILX,
6252 {0x8086, 0x107a, SILICOM_SVID, SILICOM_PMCXG2BPFI_SSID, PMCXG2BPFI,
6254 {0x8086, 0x107a, NOKIA_PMCXG2BPFIN_SVID, NOKIA_PMCXG2BPFIN_SSID,
6255 PMCXG2BPFIN, "PMCX2BPFI-N"},
6256 {0x8086, INTEL_PEG4BPII_PID, 0x8086, INTEL_PEG4BPII_SSID, PEG4BPII,
6258 {0x8086, INTEL_PEG4BPIIO_PID, 0x8086, INTEL_PEG4BPIIO_SSID, PEG4BPIIO,
6260 {0x8086, INTEL_PEG4BPFII_PID, 0x8086, INTEL_PEG4BPFII_SSID, PEG4BPFII,
6262 {0x8086, 0x1079, NOKIA_PMCXG2BPFIN_SVID, NOKIA_PMCXG2BPIN_SSID,
6263 PMCXG2BPIN, "PMCX2BPI-N"},
6264 {0x8086, 0x1079, NOKIA_PMCXG2BPFIN_SVID, NOKIA_PMCXG4BPIN_SSID,
6265 PMCXG4BPIN, "PMCX4BPI-N"},
6266 {0x8086, 0x1079, SILICOM_SVID, SILICOM_PXG2BISC1_SSID, PXG2BISC1,
6268 {0x8086, 0x105f, SILICOM_SVID, SILICOM_PEG2TBFI_SSID, PEG2TBFI,
6270 {0x8086, 0x1079, SILICOM_SVID, SILICOM_PXG2TBI_SSID, PXG2TBI,
6272 {0x8086, 0x107a, SILICOM_SVID, SILICOM_PXG4BPFID_SSID, PXG4BPFID,
6274 {0x8086, 0x105f, SILICOM_SVID, SILICOM_PEG4BPFI_SSID, PEG4BPFI,
6276 {0x8086, 0x105e, SILICOM_SVID, SILICOM_PEG4BPIPT_SSID, PEG4BPIPT,
6278 {0x8086, 0x1079, SILICOM_SVID, SILICOM_PXG6BPI_SSID, PXG6BPI,
6280 {0x8086, 0x10a7, SILICOM_SVID /*PCI_ANY_ID */ ,
6281 SILICOM_PEG4BPIL_SSID /*PCI_ANY_ID */ , PEG4BPIL, "PEG4BPIL-SD"},
6282 {0x8086, 0x1079, NOKIA_PMCXG2BPFIN_SVID, NOKIA_PMCXG2BPIN2_SSID,
6283 PMCXG2BPIN2, "PMCX2BPI-N2"},
6284 {0x8086, 0x1079, NOKIA_PMCXG2BPFIN_SVID, NOKIA_PMCXG4BPIN2_SSID,
6285 PMCXG4BPIN2, "PMCX4BPI-N2"},
6286 {0x8086, 0x1079, SILICOM_SVID, SILICOM_PMCX2BPI_SSID, PMCX2BPI,
6288 {0x8086, 0x1079, SILICOM_SVID, SILICOM_PMCX4BPI_SSID, PMCX4BPI,
6290 {0x8086, 0x105f, SILICOM_SVID, SILICOM_PEG2BPFID_SSID, PEG2BPFID,
6292 {0x8086, 0x105f, SILICOM_SVID, SILICOM_PEG2BPFIDLX_SSID, PEG2BPFIDLX,
6294 {0x8086, 0x105f, SILICOM_SVID, SILICOM_MEG2BPFILN_SSID, MEG2BPFILN,
6296 {0x8086, 0x105f, SILICOM_SVID, SILICOM_MEG2BPFINX_SSID, MEG2BPFINX,
6298 {0x8086, 0x105f, SILICOM_SVID, SILICOM_PEG4BPFILX_SSID, PEG4BPFILX,
6300 {0x8086, PCI_ANY_ID, SILICOM_SVID, SILICOM_PE10G2BPISR_SSID,
6301 PE10G2BPISR, "PE10G2BPISR"},
6302 {0x8086, PCI_ANY_ID, SILICOM_SVID, SILICOM_PE10G2BPILR_SSID,
6303 PE10G2BPILR, "PE10G2BPILR"},
6304 {0x8086, 0x10a9, SILICOM_SVID, SILICOM_MHIO8AD_SSID, MHIO8AD,
6306 {0x8086, PCI_ANY_ID, SILICOM_SVID, SILICOM_PE10G2BPICX4_SSID,
6307 PE10G2BPISR, "PE10G2BPICX4"},
6308 {0x8086, 0x10a7, SILICOM_SVID /*PCI_ANY_ID */ ,
6309 SILICOM_PEG2BPI5_SSID /*PCI_ANY_ID */ , PEG2BPI5, "PEG2BPI5-SD"},
6310 {0x8086, 0x10a7, SILICOM_SVID /*PCI_ANY_ID */ ,
6311 SILICOM_PEG6BPI_SSID /*PCI_ANY_ID */ , PEG6BPI, "PEG6BPI5"},
6312 {0x8086, 0x10a9, SILICOM_SVID /*PCI_ANY_ID */ , SILICOM_PEG4BPFI5_SSID,
6313 PEG4BPFI5, "PEG4BPFI5"},
6314 {0x8086, 0x10a9, SILICOM_SVID /*PCI_ANY_ID */ ,
6315 SILICOM_PEG4BPFI5LX_SSID, PEG4BPFI5LX, "PEG4BPFI5LX"},
6316 {0x8086, 0x105f, SILICOM_SVID, SILICOM_MEG2BPFILXLN_SSID, MEG2BPFILXLN,
6318 {0x8086, 0x105e, SILICOM_SVID, SILICOM_PEG2BPIX1_SSID, PEG2BPIX1,
6320 {0x8086, 0x105f, SILICOM_SVID, SILICOM_MEG2BPFILXNX_SSID, MEG2BPFILXNX,
6322 {0x8086, PCI_ANY_ID, SILICOM_SVID, SILICOM_XE10G2BPIT_SSID, XE10G2BPIT,
6324 {0x8086, PCI_ANY_ID, SILICOM_SVID, SILICOM_XE10G2BPICX4_SSID,
6325 XE10G2BPICX4, "XE10G2BPICX4"},
6326 {0x8086, 0x10C6, SILICOM_SVID, SILICOM_XE10G2BPISR_SSID, XE10G2BPISR,
6328 {0x8086, 0x10C6, SILICOM_SVID, SILICOM_XE10G2BPILR_SSID, XE10G2BPILR,
6330 {0x8086, 0x10C6, NOKIA_XE10G2BPIXR_SVID, NOKIA_XE10G2BPIXR_SSID,
6331 XE10G2BPIXR, "XE10G2BPIXR"},
6332 {0x8086, 0x10C6, SILICOM_SVID, SILICOM_PE10GDBISR_SSID, PE10GDBISR,
6334 {0x8086, 0x10C6, SILICOM_SVID, SILICOM_PE10GDBILR_SSID, PE10GDBILR,
6336 {0x8086, 0x10a7, SILICOM_SVID /*PCI_ANY_ID */ ,
6337 SILICOM_PEG2BISC6_SSID /*PCI_ANY_ID */ , PEG2BISC6, "PEG2BI5SC6"},
6338 {0x8086, 0x10a7, SILICOM_SVID /*PCI_ANY_ID */ ,
6339 SILICOM_PEG6BPIFC_SSID /*PCI_ANY_ID */ , PEG6BPIFC, "PEG6BPI5FC"},
6341 {BROADCOM_VID, BROADCOM_PE10G2_PID, SILICOM_SVID,
6342 SILICOM_PE10G2BPTCX4_SSID, PE10G2BPTCX4, "PE10G2BPTCX4"},
6343 {BROADCOM_VID, BROADCOM_PE10G2_PID, SILICOM_SVID,
6344 SILICOM_PE10G2BPTSR_SSID, PE10G2BPTSR, "PE10G2BPTSR"},
6345 {BROADCOM_VID, BROADCOM_PE10G2_PID, SILICOM_SVID,
6346 SILICOM_PE10G2BPTLR_SSID, PE10G2BPTLR, "PE10G2BPTLR"},
6347 {BROADCOM_VID, BROADCOM_PE10G2_PID, SILICOM_SVID,
6348 SILICOM_PE10G2BPTT_SSID, PE10G2BPTT, "PE10G2BPTT"},
6350 /* {BROADCOM_VID, BROADCOM_PE10G2_PID, PCI_ANY_ID, PCI_ANY_ID, PE10G2BPTCX4, "PE10G2BPTCX4"}, */
6352 {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6353 SILICOM_PEG4BPI6_SSID /*PCI_ANY_ID */ , PEG4BPI6, "PEG4BPI6"},
6354 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6355 SILICOM_PEG4BPFI6_SSID /*PCI_ANY_ID */ , PEG4BPFI6, "PEG4BPFI6"},
6356 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6357 SILICOM_PEG4BPFI6LX_SSID /*PCI_ANY_ID */ , PEG4BPFI6LX, "PEG4BPFI6LX"},
6358 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6359 SILICOM_PEG4BPFI6ZX_SSID /*PCI_ANY_ID */ , PEG4BPFI6ZX, "PEG4BPFI6ZX"},
6360 {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6361 SILICOM_PEG2BPI6_SSID /*PCI_ANY_ID */ , PEG2BPI6, "PEG2BPI6"},
6362 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6363 SILICOM_PEG2BPFI6_SSID /*PCI_ANY_ID */ , PEG2BPFI6, "PEG2BPFI6"},
6364 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6365 SILICOM_PEG2BPFI6LX_SSID /*PCI_ANY_ID */ , PEG2BPFI6LX, "PEG2BPFI6LX"},
6366 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6367 SILICOM_PEG2BPFI6ZX_SSID /*PCI_ANY_ID */ , PEG2BPFI6ZX, "PEG2BPFI6ZX"},
6368 {0x8086, 0x10e7, SILICOM_SVID /*PCI_ANY_ID */ ,
6369 SILICOM_PEG2BPFI6FLXM_SSID /*PCI_ANY_ID */ , PEG2BPFI6FLXM,
6371 {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6372 SILICOM_PEG4BPI6FC_SSID /*PCI_ANY_ID */ , PEG4BPI6FC, "PEG4BPI6FC"},
6373 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6374 SILICOM_PEG4BPFI6FC_SSID /*PCI_ANY_ID */ , PEG4BPFI6FC, "PEG4BPFI6FC"},
6375 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6376 SILICOM_PEG4BPFI6FCLX_SSID /*PCI_ANY_ID */ , PEG4BPFI6FCLX,
6378 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6379 SILICOM_PEG4BPFI6FCZX_SSID /*PCI_ANY_ID */ , PEG4BPFI6FCZX,
6381 {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6382 SILICOM_PEG6BPI6_SSID /*PCI_ANY_ID */ , PEG6BPI6, "PEG6BPI6"},
6383 {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6384 SILICOM_PEG2BPI6SC6_SSID /*PCI_ANY_ID */ , PEG2BPI6SC6,
6386 {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6387 SILICOM_MEG2BPI6_SSID /*PCI_ANY_ID */ , MEG2BPI6, "MEG2BPI6"},
6388 {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6389 SILICOM_XEG2BPI6_SSID /*PCI_ANY_ID */ , XEG2BPI6, "XEG2BPI6"},
6390 {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6391 SILICOM_MEG4BPI6_SSID /*PCI_ANY_ID */ , MEG4BPI6, "MEG4BPI6"},
6393 {0x8086, 0x10a9, SILICOM_SVID /*PCI_ANY_ID */ , SILICOM_PEG2BPFI5_SSID,
6394 PEG2BPFI5, "PEG2BPFI5"},
6395 {0x8086, 0x10a9, SILICOM_SVID /*PCI_ANY_ID */ ,
6396 SILICOM_PEG2BPFI5LX_SSID, PEG2BPFI5LX, "PEG2BPFI5LX"},
6398 {0x8086, 0x105f, SILICOM_SVID, SILICOM_PXEG4BPFI_SSID, PXEG4BPFI,
6401 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6402 SILICOM_M1EG2BPI6_SSID /*PCI_ANY_ID */ , M1EG2BPI6, "MxEG2BPI6"},
6404 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6405 SILICOM_M1EG2BPFI6_SSID /*PCI_ANY_ID */ , M1EG2BPFI6, "MxEG2BPFI6"},
6406 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6407 SILICOM_M1EG2BPFI6LX_SSID /*PCI_ANY_ID */ , M1EG2BPFI6LX,
6409 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6410 SILICOM_M1EG2BPFI6ZX_SSID /*PCI_ANY_ID */ , M1EG2BPFI6ZX,
6413 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6414 SILICOM_M1EG4BPI6_SSID /*PCI_ANY_ID */ , M1EG4BPI6, "MxEG4BPI6"},
6416 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6417 SILICOM_M1EG4BPFI6_SSID /*PCI_ANY_ID */ , M1EG4BPFI6, "MxEG4BPFI6"},
6418 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6419 SILICOM_M1EG4BPFI6LX_SSID /*PCI_ANY_ID */ , M1EG4BPFI6LX,
6421 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6422 SILICOM_M1EG4BPFI6ZX_SSID /*PCI_ANY_ID */ , M1EG4BPFI6ZX,
6425 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6426 SILICOM_M1EG6BPI6_SSID /*PCI_ANY_ID */ , M1EG6BPI6, "MxEG6BPI6"},
6428 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6429 SILICOM_M1E2G4BPi80_SSID /*PCI_ANY_ID */ , M1E2G4BPi80, "MxE2G4BPi80"},
6430 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6431 SILICOM_M1E2G4BPFi80_SSID /*PCI_ANY_ID */ , M1E2G4BPFi80,
6433 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6434 SILICOM_M1E2G4BPFi80LX_SSID /*PCI_ANY_ID */ , M1E2G4BPFi80LX,
6436 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6437 SILICOM_M1E2G4BPFi80ZX_SSID /*PCI_ANY_ID */ , M1E2G4BPFi80ZX,
6440 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6441 SILICOM_M2EG2BPFI6_SSID /*PCI_ANY_ID */ , M2EG2BPFI6, "M2EG2BPFI6"},
6442 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6443 SILICOM_M2EG2BPFI6LX_SSID /*PCI_ANY_ID */ , M2EG2BPFI6LX,
6445 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6446 SILICOM_M2EG2BPFI6ZX_SSID /*PCI_ANY_ID */ , M2EG2BPFI6ZX,
6449 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6450 SILICOM_M2EG4BPI6_SSID /*PCI_ANY_ID */ , M2EG4BPI6, "M2EG4BPI6"},
6452 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6453 SILICOM_M2EG4BPFI6_SSID /*PCI_ANY_ID */ , M2EG4BPFI6, "M2EG4BPFI6"},
6454 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6455 SILICOM_M2EG4BPFI6LX_SSID /*PCI_ANY_ID */ , M2EG4BPFI6LX,
6457 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6458 SILICOM_M2EG4BPFI6ZX_SSID /*PCI_ANY_ID */ , M2EG4BPFI6ZX,
6461 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6462 SILICOM_M2EG6BPI6_SSID /*PCI_ANY_ID */ , M2EG6BPI6, "M2EG6BPI6"},
6464 {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6465 SILICOM_PEG2DBI6_SSID /*PCI_ANY_ID */ , PEG2DBI6, "PEG2DBI6"},
6466 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6467 SILICOM_PEG2DBFI6_SSID /*PCI_ANY_ID */ , PEG2DBFI6, "PEG2DBFI6"},
6468 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6469 SILICOM_PEG2DBFI6LX_SSID /*PCI_ANY_ID */ , PEG2DBFI6LX, "PEG2DBFI6LX"},
6470 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6471 SILICOM_PEG2DBFI6ZX_SSID /*PCI_ANY_ID */ , PEG2DBFI6ZX, "PEG2DBFI6ZX"},
6473 {0x8086, 0x10F9, SILICOM_SVID /*PCI_ANY_ID */ ,
6474 SILICOM_PE210G2DBi9SR_SSID, PE210G2DBi9SR, "PE210G2DBi9SR"},
6475 {0x8086, 0x10F9, SILICOM_SVID /*PCI_ANY_ID */ ,
6476 SILICOM_PE210G2DBi9LR_SSID, PE210G2DBi9LR, "PE210G2DBi9LR"},
6477 {0x8086, 0x10F9, SILICOM_SVID /*PCI_ANY_ID */ ,
6478 SILICOM_PE310G4DBi940SR_SSID, PE310G4DBi940SR, "PE310G4DBi9SR"},
6480 {0x8086, 0x10Fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6481 SILICOM_PE310G4BPi9T_SSID, PE310G4BPi9T, "PE310G4BPi9T"},
6482 {0x8086, 0x10Fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6483 SILICOM_PE310G4BPi9SR_SSID, PE310G4BPi9SR, "PE310G4BPi9SR"},
6484 {0x8086, 0x10Fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6485 SILICOM_PE310G4BPi9LR_SSID, PE310G4BPi9LR, "PE310G4BPi9LR"},
6487 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6488 SILICOM_PE2G4BPi80_SSID /*PCI_ANY_ID */ , PE2G4BPi80, "PE2G4BPi80"},
6489 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6490 SILICOM_PE2G4BPFi80_SSID /*PCI_ANY_ID */ , PE2G4BPFi80, "PE2G4BPFi80"},
6491 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6492 SILICOM_PE2G4BPFi80LX_SSID /*PCI_ANY_ID */ , PE2G4BPFi80LX,
6494 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6495 SILICOM_PE2G4BPFi80ZX_SSID /*PCI_ANY_ID */ , PE2G4BPFi80ZX,
6498 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6499 SILICOM_PE2G4BPi80L_SSID /*PCI_ANY_ID */ , PE2G4BPi80L, "PE2G4BPi80L"},
6501 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6502 SILICOM_M6E2G8BPi80A_SSID /*PCI_ANY_ID */ , M6E2G8BPi80A,
6505 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6506 SILICOM_PE2G2BPi35_SSID /*PCI_ANY_ID */ , PE2G2BPi35, "PE2G2BPi35"},
6507 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6508 SILICOM_PAC1200BPi35_SSID /*PCI_ANY_ID */ , PAC1200BPi35,
6511 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6512 SILICOM_PE2G2BPFi35_SSID /*PCI_ANY_ID */ , PE2G2BPFi35, "PE2G2BPFi35"},
6513 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6514 SILICOM_PE2G2BPFi35LX_SSID /*PCI_ANY_ID */ , PE2G2BPFi35LX,
6516 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6517 SILICOM_PE2G2BPFi35ZX_SSID /*PCI_ANY_ID */ , PE2G2BPFi35ZX,
6520 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6521 SILICOM_PE2G4BPi35_SSID /*PCI_ANY_ID */ , PE2G4BPi35, "PE2G4BPi35"},
6523 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6524 SILICOM_PE2G4BPi35L_SSID /*PCI_ANY_ID */ , PE2G4BPi35L, "PE2G4BPi35L"},
6526 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6527 SILICOM_PE2G4BPFi35_SSID /*PCI_ANY_ID */ , PE2G4BPFi35, "PE2G4BPFi35"},
6528 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6529 SILICOM_PE2G4BPFi35LX_SSID /*PCI_ANY_ID */ , PE2G4BPFi35LX,
6531 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6532 SILICOM_PE2G4BPFi35ZX_SSID /*PCI_ANY_ID */ , PE2G4BPFi35ZX,
6535 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6536 SILICOM_PE2G6BPi35_SSID /*PCI_ANY_ID */ , PE2G6BPi35, "PE2G6BPi35"},
6539 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa0, PE2G6BPi35CX,
6541 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa1, PE2G6BPi35CX,
6543 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa2, PE2G6BPi35CX,
6545 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa3, PE2G6BPi35CX,
6547 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa4, PE2G6BPi35CX,
6549 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa5, PE2G6BPi35CX,
6551 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa6, PE2G6BPi35CX,
6553 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa7, PE2G6BPi35CX,
6555 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa8, PE2G6BPi35CX,
6557 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa9, PE2G6BPi35CX,
6559 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaaa, PE2G6BPi35CX,
6561 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaab, PE2G6BPi35CX,
6563 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaac, PE2G6BPi35CX,
6565 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaad, PE2G6BPi35CX,
6567 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaae, PE2G6BPi35CX,
6569 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaaf, PE2G6BPi35CX,
6571 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab0, PE2G6BPi35CX,
6573 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab1, PE2G6BPi35CX,
6575 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab2, PE2G6BPi35CX,
6577 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab3, PE2G6BPi35CX,
6579 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab4, PE2G6BPi35CX,
6581 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab5, PE2G6BPi35CX,
6583 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab6, PE2G6BPi35CX,
6585 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab7, PE2G6BPi35CX,
6587 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab8, PE2G6BPi35CX,
6589 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab9, PE2G6BPi35CX,
6591 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaba, PE2G6BPi35CX,
6593 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xabb, PE2G6BPi35CX,
6595 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xabc, PE2G6BPi35CX,
6597 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xabd, PE2G6BPi35CX,
6599 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xabe, PE2G6BPi35CX,
6601 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xabf, PE2G6BPi35CX,
6604 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6605 SILICOM_PE2G2BPi80_SSID /*PCI_ANY_ID */ , PE2G2BPi80, "PE2G2BPi80"},
6606 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6607 SILICOM_PE2G2BPFi80_SSID /*PCI_ANY_ID */ , PE2G2BPFi80, "PE2G2BPFi80"},
6608 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6609 SILICOM_PE2G2BPFi80LX_SSID /*PCI_ANY_ID */ , PE2G2BPFi80LX,
6611 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6612 SILICOM_PE2G2BPFi80ZX_SSID /*PCI_ANY_ID */ , PE2G2BPFi80ZX,
6615 {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6616 SILICOM_MEG2BPI6_SSID /*PCI_ANY_ID */ , MEG2BPI6, "MEG2BPI6"},
6617 {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6618 SILICOM_XEG2BPI6_SSID /*PCI_ANY_ID */ , XEG2BPI6, "XEG2BPI6"},
6621 {0x8086, 0x10fb, 0x8086, INTEL_PE210G2SPI9_SSID, PE210G2SPI9,
6624 {0x8086, 0x10fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6625 SILICOM_M1E10G2BPI9CX4_SSID /*PCI_ANY_ID */ , M1E10G2BPI9CX4,
6627 {0x8086, 0x10fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6628 SILICOM_M1E10G2BPI9SR_SSID /*PCI_ANY_ID */ , M1E10G2BPI9SR,
6630 {0x8086, 0x10fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6631 SILICOM_M1E10G2BPI9LR_SSID /*PCI_ANY_ID */ , M1E10G2BPI9LR,
6633 {0x8086, 0x10fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6634 SILICOM_M1E10G2BPI9T_SSID /*PCI_ANY_ID */ , M1E10G2BPI9T,
6637 {0x8086, 0x10fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6638 SILICOM_M2E10G2BPI9CX4_SSID /*PCI_ANY_ID */ , M2E10G2BPI9CX4,
6640 {0x8086, 0x10fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6641 SILICOM_M2E10G2BPI9SR_SSID /*PCI_ANY_ID */ , M2E10G2BPI9SR,
6643 {0x8086, 0x10fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6644 SILICOM_M2E10G2BPI9LR_SSID /*PCI_ANY_ID */ , M2E10G2BPI9LR,
6646 {0x8086, 0x10fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6647 SILICOM_M2E10G2BPI9T_SSID /*PCI_ANY_ID */ , M2E10G2BPI9T,
6650 {0x8086, 0x10fb, SILICOM_SVID, SILICOM_PE210G2BPI9CX4_SSID,
6651 PE210G2BPI9CX4, "PE210G2BPI9CX4"},
6652 {0x8086, 0x10fb, SILICOM_SVID, SILICOM_PE210G2BPI9SR_SSID,
6653 PE210G2BPI9SR, "PE210G2BPI9SR"},
6654 {0x8086, 0x10fb, SILICOM_SVID, SILICOM_PE210G2BPI9LR_SSID,
6655 PE210G2BPI9LR, "PE210G2BPI9LR"},
6656 {0x8086, 0x10fb, SILICOM_SVID, SILICOM_PE210G2BPI9T_SSID, PE210G2BPI9T,
6660 {0x1374, 0x2c, SILICOM_SVID, SILICOM_PXG4BPI_SSID, PXG4BPI,
6663 {0x1374, 0x2d, SILICOM_SVID, SILICOM_PXG4BPFI_SSID, PXG4BPFI,
6666 {0x1374, 0x3f, SILICOM_SVID, SILICOM_PXG2TBI_SSID, PXG2TBI,
6669 {0x1374, 0x3d, SILICOM_SVID, SILICOM_PXG2BISC1_SSID, PXG2BISC1,
6672 {0x1374, 0x40, SILICOM_SVID, SILICOM_PEG4BPFI_SSID, PEG4BPFI,
6676 {0x1374, 0x28, SILICOM_SVID, 0x28, PXGBPI, "PXG2BPI-SD"},
6679 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6680 SILICOM_M6E2G8BPi80_SSID /*PCI_ANY_ID */ , M6E2G8BPi80, "MxE2G8BPi80"},
6681 {0x8086, 0x1528, SILICOM_SVID /*PCI_ANY_ID */ ,
6682 SILICOM_PE210G2BPi40_SSID /*PCI_ANY_ID */ , PE210G2BPi40,
6685 /* required last entry */
6690 * Initialize the module - Register the character device
6693 static int __init bypass_init_module(void)
6695 int ret_val, idx, idx_dev = 0;
6696 struct pci_dev *pdev1 = NULL;
6697 unsigned long mmio_start, mmio_len;
6699 printk(BP_MOD_DESCR " v" BP_MOD_VER "\n");
6700 ret_val = register_chrdev(major_num, DEVICE_NAME, &Fops);
6702 printk("%s failed with %d\n", DEVICE_NAME, ret_val);
6705 major_num = ret_val; /* dynamic */
6706 for (idx = 0; tx_ctl_pci_tbl[idx].vendor; idx++) {
6707 while ((pdev1 = pci_get_subsys(tx_ctl_pci_tbl[idx].vendor,
6708 tx_ctl_pci_tbl[idx].device,
6709 tx_ctl_pci_tbl[idx].subvendor,
6710 tx_ctl_pci_tbl[idx].subdevice,
6717 printk("No such device\n");
6718 unregister_chrdev(major_num, DEVICE_NAME);
6722 bpctl_dev_arr = kmalloc((device_num) * sizeof(bpctl_dev_t), GFP_KERNEL);
6724 if (!bpctl_dev_arr) {
6725 printk("Allocation error\n");
6726 unregister_chrdev(major_num, DEVICE_NAME);
6729 memset(bpctl_dev_arr, 0, ((device_num) * sizeof(bpctl_dev_t)));
6732 for (idx = 0; tx_ctl_pci_tbl[idx].vendor; idx++) {
6733 while ((pdev1 = pci_get_subsys(tx_ctl_pci_tbl[idx].vendor,
6734 tx_ctl_pci_tbl[idx].device,
6735 tx_ctl_pci_tbl[idx].subvendor,
6736 tx_ctl_pci_tbl[idx].subdevice,
6738 bpctl_dev_arr[idx_dev].pdev = pdev1;
6740 mmio_start = pci_resource_start(pdev1, 0);
6741 mmio_len = pci_resource_len(pdev1, 0);
6743 bpctl_dev_arr[idx_dev].desc =
6744 dev_desc[tx_ctl_pci_tbl[idx].index].name;
6745 bpctl_dev_arr[idx_dev].name =
6746 tx_ctl_pci_tbl[idx].bp_name;
6747 bpctl_dev_arr[idx_dev].device =
6748 tx_ctl_pci_tbl[idx].device;
6749 bpctl_dev_arr[idx_dev].vendor =
6750 tx_ctl_pci_tbl[idx].vendor;
6751 bpctl_dev_arr[idx_dev].subdevice =
6752 tx_ctl_pci_tbl[idx].subdevice;
6753 bpctl_dev_arr[idx_dev].subvendor =
6754 tx_ctl_pci_tbl[idx].subvendor;
6755 /* bpctl_dev_arr[idx_dev].pdev=pdev1; */
6756 bpctl_dev_arr[idx_dev].func = PCI_FUNC(pdev1->devfn);
6757 bpctl_dev_arr[idx_dev].slot = PCI_SLOT(pdev1->devfn);
6758 bpctl_dev_arr[idx_dev].bus = pdev1->bus->number;
6759 bpctl_dev_arr[idx_dev].mem_map =
6760 (unsigned long)ioremap(mmio_start, mmio_len);
6762 spin_lock_init(&bpctl_dev_arr[idx_dev].bypass_wr_lock);
6764 if (BP10G9_IF_SERIES(bpctl_dev_arr[idx_dev].subdevice))
6765 bpctl_dev_arr[idx_dev].bp_10g9 = 1;
6766 if (BP10G_IF_SERIES(bpctl_dev_arr[idx_dev].subdevice))
6767 bpctl_dev_arr[idx_dev].bp_10g = 1;
6768 if (PEG540_IF_SERIES(bpctl_dev_arr[idx_dev].subdevice)) {
6770 bpctl_dev_arr[idx_dev].bp_540 = 1;
6772 if (PEGF5_IF_SERIES(bpctl_dev_arr[idx_dev].subdevice))
6773 bpctl_dev_arr[idx_dev].bp_fiber5 = 1;
6774 if (PEG80_IF_SERIES(bpctl_dev_arr[idx_dev].subdevice))
6775 bpctl_dev_arr[idx_dev].bp_i80 = 1;
6776 if (PEGF80_IF_SERIES(bpctl_dev_arr[idx_dev].subdevice))
6777 bpctl_dev_arr[idx_dev].bp_i80 = 1;
6778 if ((bpctl_dev_arr[idx_dev].subdevice & 0xa00) == 0xa00)
6779 bpctl_dev_arr[idx_dev].bp_i80 = 1;
6780 if (BP10GB_IF_SERIES(bpctl_dev_arr[idx_dev].subdevice)) {
6781 if (bpctl_dev_arr[idx_dev].ifindex == 0) {
6782 unregister_chrdev(major_num,
6785 ("Please load network driver for %s adapter!\n",
6786 bpctl_dev_arr[idx_dev].name);
6790 if (bpctl_dev_arr[idx_dev].ndev) {
6792 (bpctl_dev_arr[idx_dev].ndev->
6795 (bpctl_dev_arr[idx_dev].
6796 ndev->flags & IFF_UP)) {
6801 ("Please bring up network interfaces for %s adapter!\n",
6809 bpctl_dev_arr[idx_dev].bp_10gb = 1;
6812 if (!bpctl_dev_arr[idx_dev].bp_10g9) {
6814 if (is_bypass_fn(&bpctl_dev_arr[idx_dev])) {
6815 printk(KERN_INFO "%s found, ",
6816 bpctl_dev_arr[idx_dev].name);
6818 (bpctl_dev_arr[idx_dev].subdevice))
6821 (bpctl_dev_arr[idx_dev].
6823 bpctl_dev_arr[idx_dev].
6826 bpctl_dev_arr[idx_dev].
6828 bypass_fw_ver(&bpctl_dev_arr
6830 if ((bpctl_dev_arr[idx_dev].bp_10gb ==
6832 && (bpctl_dev_arr[idx_dev].
6833 bp_fw_ver == 0xff)) {
6848 bpctl_dev_arr[idx_dev].
6854 bpctl_dev_arr[idx_dev].
6866 /* bpctl_dev_arr[idx_dev].bp_fw_ver=0xa8; */
6867 printk("firmware version: 0x%x\n",
6868 bpctl_dev_arr[idx_dev].
6871 bpctl_dev_arr[idx_dev].wdt_status =
6873 bpctl_dev_arr[idx_dev].reset_time = 0;
6874 atomic_set(&bpctl_dev_arr[idx_dev].wdt_busy, 0);
6875 bpctl_dev_arr[idx_dev].bp_status_un = 1;
6877 bypass_caps_init(&bpctl_dev_arr[idx_dev]);
6879 init_bypass_wd_auto(&bpctl_dev_arr[idx_dev]);
6880 init_bypass_tpl_auto(&bpctl_dev_arr[idx_dev]);
6882 (bpctl_dev_arr[idx_dev].subdevice))
6883 reset_cont(&bpctl_dev_arr[idx_dev]);
6886 if ((bpctl_dev_arr[idx_dev].bp_tx_data =
6887 kmalloc(BPTEST_DATA_LEN, GFP_KERNEL))) {
6889 memset(bpctl_dev_arr[idx_dev].bp_tx_data, 0x0,
6892 memset(bpctl_dev_arr[idx_dev].bp_tx_data, 0xff,
6894 memset(bpctl_dev_arr[idx_dev].bp_tx_data + 6,
6896 memset(bpctl_dev_arr[idx_dev].bp_tx_data + 7,
6899 *(__be16 *) (bpctl_dev_arr[idx_dev].bp_tx_data +
6900 12) = htons(ETH_P_BPTEST);
6903 printk("bp_ctl: Memory allocation error!\n");
6911 sema_init(&bpctl_sema, 1);
6912 spin_lock_init(&bpvm_lock);
6915 bpctl_dev_t *pbpctl_dev_c = NULL;
6917 ((bpctl_dev_arr[idx_dev].pdev != NULL)
6918 && (idx_dev < device_num)); idx_dev++) {
6919 if (bpctl_dev_arr[idx_dev].bp_10g9) {
6921 get_status_port_fn(&bpctl_dev_arr[idx_dev]);
6922 if (is_bypass_fn(&bpctl_dev_arr[idx_dev])) {
6923 printk(KERN_INFO "%s found, ",
6924 bpctl_dev_arr[idx_dev].name);
6925 bpctl_dev_arr[idx_dev].bp_fw_ver =
6926 bypass_fw_ver(&bpctl_dev_arr
6928 printk("firmware version: 0x%x\n",
6929 bpctl_dev_arr[idx_dev].
6933 bpctl_dev_arr[idx_dev].wdt_status =
6935 bpctl_dev_arr[idx_dev].reset_time = 0;
6936 atomic_set(&bpctl_dev_arr[idx_dev].wdt_busy, 0);
6937 bpctl_dev_arr[idx_dev].bp_status_un = 1;
6939 bypass_caps_init(&bpctl_dev_arr[idx_dev]);
6941 init_bypass_wd_auto(&bpctl_dev_arr[idx_dev]);
6942 init_bypass_tpl_auto(&bpctl_dev_arr[idx_dev]);
6949 register_netdevice_notifier(&bp_notifier_block);
6950 #ifdef BP_PROC_SUPPORT
6953 /* unsigned long flags; */
6954 /* rcu_read_lock(); */
6956 for (i = 0; i < device_num; i++) {
6957 if (bpctl_dev_arr[i].ifindex) {
6958 /* spin_lock_irqsave(&bpvm_lock, flags); */
6959 bypass_proc_remove_dev_sd(&bpctl_dev_arr[i]);
6960 bypass_proc_create_dev_sd(&bpctl_dev_arr[i]);
6961 /* spin_unlock_irqrestore(&bpvm_lock, flags); */
6965 /* rcu_read_unlock(); */
6973 * Cleanup - unregister the appropriate file from /proc
6975 static void __exit bypass_cleanup_module(void)
6978 unregister_netdevice_notifier(&bp_notifier_block);
6980 for (i = 0; i < device_num; i++) {
6981 /* unsigned long flags; */
6982 #ifdef BP_PROC_SUPPORT
6983 /* spin_lock_irqsave(&bpvm_lock, flags);
6985 bypass_proc_remove_dev_sd(&bpctl_dev_arr[i]);
6986 /* spin_unlock_irqrestore(&bpvm_lock, flags);
6987 rcu_read_unlock(); */
6989 remove_bypass_wd_auto(&bpctl_dev_arr[i]);
6990 bpctl_dev_arr[i].reset_time = 0;
6992 remove_bypass_tpl_auto(&bpctl_dev_arr[i]);
6995 /* unmap all devices */
6996 for (i = 0; i < device_num; i++) {
6998 if (bpctl_dev_arr[i].bp_tx_data)
6999 kfree(bpctl_dev_arr[i].bp_tx_data);
7001 iounmap((void *)(bpctl_dev_arr[i].mem_map));
7004 /* free all devices space */
7006 kfree(bpctl_dev_arr);
7009 * Unregister the device
7011 unregister_chrdev(major_num, DEVICE_NAME);
7014 module_init(bypass_init_module);
7015 module_exit(bypass_cleanup_module);
7017 int is_bypass_sd(int ifindex)
7019 return is_bypass(get_dev_idx_p(ifindex));
7022 int set_bypass_sd(int ifindex, int bypass_mode)
7025 return set_bypass_fn(get_dev_idx_p(ifindex), bypass_mode);
7028 int get_bypass_sd(int ifindex)
7031 return get_bypass_fn(get_dev_idx_p(ifindex));
7034 int get_bypass_change_sd(int ifindex)
7037 return get_bypass_change_fn(get_dev_idx_p(ifindex));
7040 int set_dis_bypass_sd(int ifindex, int dis_param)
7042 return set_dis_bypass_fn(get_dev_idx_p(ifindex), dis_param);
7045 int get_dis_bypass_sd(int ifindex)
7048 return get_dis_bypass_fn(get_dev_idx_p(ifindex));
7051 int set_bypass_pwoff_sd(int ifindex, int bypass_mode)
7053 return set_bypass_pwoff_fn(get_dev_idx_p(ifindex), bypass_mode);
7057 int get_bypass_pwoff_sd(int ifindex)
7059 return get_bypass_pwoff_fn(get_dev_idx_p(ifindex));
7063 int set_bypass_pwup_sd(int ifindex, int bypass_mode)
7065 return set_bypass_pwup_fn(get_dev_idx_p(ifindex), bypass_mode);
7069 int get_bypass_pwup_sd(int ifindex)
7071 return get_bypass_pwup_fn(get_dev_idx_p(ifindex));
7075 int set_bypass_wd_sd(int if_index, int ms_timeout, int *ms_timeout_set)
7077 if ((is_bypass(get_dev_idx_p(if_index))) <= 0)
7079 *ms_timeout_set = set_bypass_wd_fn(get_dev_idx_p(if_index), ms_timeout);
7083 int get_bypass_wd_sd(int ifindex, int *timeout)
7085 return get_bypass_wd_fn(get_dev_idx_p(ifindex), timeout);
7089 int get_wd_expire_time_sd(int ifindex, int *time_left)
7091 return get_wd_expire_time_fn(get_dev_idx_p(ifindex), time_left);
7094 int reset_bypass_wd_timer_sd(int ifindex)
7096 return reset_bypass_wd_timer_fn(get_dev_idx_p(ifindex));
7100 int get_wd_set_caps_sd(int ifindex)
7102 return get_wd_set_caps_fn(get_dev_idx_p(ifindex));
7106 int set_std_nic_sd(int ifindex, int nic_mode)
7108 return set_std_nic_fn(get_dev_idx_p(ifindex), nic_mode);
7112 int get_std_nic_sd(int ifindex)
7114 return get_std_nic_fn(get_dev_idx_p(ifindex));
7118 int set_tap_sd(int ifindex, int tap_mode)
7120 return set_tap_fn(get_dev_idx_p(ifindex), tap_mode);
7124 int get_tap_sd(int ifindex)
7126 return get_tap_fn(get_dev_idx_p(ifindex));
7130 int set_tap_pwup_sd(int ifindex, int tap_mode)
7132 return set_tap_pwup_fn(get_dev_idx_p(ifindex), tap_mode);
7136 int get_tap_pwup_sd(int ifindex)
7138 return get_tap_pwup_fn(get_dev_idx_p(ifindex));
7142 int get_tap_change_sd(int ifindex)
7144 return get_tap_change_fn(get_dev_idx_p(ifindex));
7148 int set_dis_tap_sd(int ifindex, int dis_param)
7150 return set_dis_tap_fn(get_dev_idx_p(ifindex), dis_param);
7154 int get_dis_tap_sd(int ifindex)
7156 return get_dis_tap_fn(get_dev_idx_p(ifindex));
7160 int set_bp_disc_sd(int ifindex, int disc_mode)
7162 return set_disc_fn(get_dev_idx_p(ifindex), disc_mode);
7166 int get_bp_disc_sd(int ifindex)
7168 return get_disc_fn(get_dev_idx_p(ifindex));
7172 int set_bp_disc_pwup_sd(int ifindex, int disc_mode)
7174 return set_disc_pwup_fn(get_dev_idx_p(ifindex), disc_mode);
7178 int get_bp_disc_pwup_sd(int ifindex)
7180 return get_disc_pwup_fn(get_dev_idx_p(ifindex));
7184 int get_bp_disc_change_sd(int ifindex)
7186 return get_disc_change_fn(get_dev_idx_p(ifindex));
7190 int set_bp_dis_disc_sd(int ifindex, int dis_param)
7192 return set_dis_disc_fn(get_dev_idx_p(ifindex), dis_param);
7196 int get_bp_dis_disc_sd(int ifindex)
7198 return get_dis_disc_fn(get_dev_idx_p(ifindex));
7202 int get_wd_exp_mode_sd(int ifindex)
7204 return get_wd_exp_mode_fn(get_dev_idx_p(ifindex));
7207 int set_wd_exp_mode_sd(int ifindex, int param)
7209 return set_wd_exp_mode_fn(get_dev_idx_p(ifindex), param);
7213 int reset_cont_sd(int ifindex)
7215 return reset_cont_fn(get_dev_idx_p(ifindex));
7219 int set_tx_sd(int ifindex, int tx_state)
7221 return set_tx_fn(get_dev_idx_p(ifindex), tx_state);
7225 int set_tpl_sd(int ifindex, int tpl_state)
7227 return set_tpl_fn(get_dev_idx_p(ifindex), tpl_state);
7231 int set_bp_hw_reset_sd(int ifindex, int status)
7233 return set_bp_hw_reset_fn(get_dev_idx_p(ifindex), status);
7237 int set_wd_autoreset_sd(int ifindex, int param)
7239 return set_wd_autoreset_fn(get_dev_idx_p(ifindex), param);
7243 int get_wd_autoreset_sd(int ifindex)
7245 return get_wd_autoreset_fn(get_dev_idx_p(ifindex));
7249 int get_bypass_caps_sd(int ifindex)
7251 return get_bypass_caps_fn(get_dev_idx_p(ifindex));
7254 int get_bypass_slave_sd(int ifindex)
7256 bpctl_dev_t *pbpctl_dev_out;
7257 int ret = get_bypass_slave_fn(get_dev_idx_p(ifindex), &pbpctl_dev_out);
7259 return pbpctl_dev_out->ifindex;
7264 int get_tx_sd(int ifindex)
7266 return get_tx_fn(get_dev_idx_p(ifindex));
7270 int get_tpl_sd(int ifindex)
7272 return get_tpl_fn(get_dev_idx_p(ifindex));
7276 int get_bp_hw_reset_sd(int ifindex)
7278 return get_bp_hw_reset_fn(get_dev_idx_p(ifindex));
7282 int get_bypass_info_sd(int ifindex, struct bp_info *bp_info)
7284 return get_bypass_info_fn(get_dev_idx_p(ifindex), bp_info->prod_name, &bp_info->fw_ver);
7287 int bp_if_scan_sd(void)
7293 EXPORT_SYMBOL_NOVERS(is_bypass_sd);
7294 EXPORT_SYMBOL_NOVERS(get_bypass_slave_sd);
7295 EXPORT_SYMBOL_NOVERS(get_bypass_caps_sd);
7296 EXPORT_SYMBOL_NOVERS(get_wd_set_caps_sd);
7297 EXPORT_SYMBOL_NOVERS(set_bypass_sd);
7298 EXPORT_SYMBOL_NOVERS(get_bypass_sd);
7299 EXPORT_SYMBOL_NOVERS(get_bypass_change_sd);
7300 EXPORT_SYMBOL_NOVERS(set_dis_bypass_sd);
7301 EXPORT_SYMBOL_NOVERS(get_dis_bypass_sd);
7302 EXPORT_SYMBOL_NOVERS(set_bypass_pwoff_sd);
7303 EXPORT_SYMBOL_NOVERS(get_bypass_pwoff_sd);
7304 EXPORT_SYMBOL_NOVERS(set_bypass_pwup_sd);
7305 EXPORT_SYMBOL_NOVERS(get_bypass_pwup_sd);
7306 EXPORT_SYMBOL_NOVERS(set_bypass_wd_sd);
7307 EXPORT_SYMBOL_NOVERS(get_bypass_wd_sd);
7308 EXPORT_SYMBOL_NOVERS(get_wd_expire_time_sd);
7309 EXPORT_SYMBOL_NOVERS(reset_bypass_wd_timer_sd);
7310 EXPORT_SYMBOL_NOVERS(set_std_nic_sd);
7311 EXPORT_SYMBOL_NOVERS(get_std_nic_sd);
7312 EXPORT_SYMBOL_NOVERS(set_tx_sd);
7313 EXPORT_SYMBOL_NOVERS(get_tx_sd);
7314 EXPORT_SYMBOL_NOVERS(set_tpl_sd);
7315 EXPORT_SYMBOL_NOVERS(get_tpl_sd);
7316 EXPORT_SYMBOL_NOVERS(set_bp_hw_reset_sd);
7317 EXPORT_SYMBOL_NOVERS(get_bp_hw_reset_sd);
7318 EXPORT_SYMBOL_NOVERS(set_tap_sd);
7319 EXPORT_SYMBOL_NOVERS(get_tap_sd);
7320 EXPORT_SYMBOL_NOVERS(get_tap_change_sd);
7321 EXPORT_SYMBOL_NOVERS(set_dis_tap_sd);
7322 EXPORT_SYMBOL_NOVERS(get_dis_tap_sd);
7323 EXPORT_SYMBOL_NOVERS(set_tap_pwup_sd);
7324 EXPORT_SYMBOL_NOVERS(get_tap_pwup_sd);
7325 EXPORT_SYMBOL_NOVERS(set_wd_exp_mode_sd);
7326 EXPORT_SYMBOL_NOVERS(get_wd_exp_mode_sd);
7327 EXPORT_SYMBOL_NOVERS(set_wd_autoreset_sd);
7328 EXPORT_SYMBOL_NOVERS(get_wd_autoreset_sd);
7329 EXPORT_SYMBOL_NOVERS(set_bp_disc_sd);
7330 EXPORT_SYMBOL_NOVERS(get_bp_disc_sd);
7331 EXPORT_SYMBOL_NOVERS(get_bp_disc_change_sd);
7332 EXPORT_SYMBOL_NOVERS(set_bp_dis_disc_sd);
7333 EXPORT_SYMBOL_NOVERS(get_bp_dis_disc_sd);
7334 EXPORT_SYMBOL_NOVERS(set_bp_disc_pwup_sd);
7335 EXPORT_SYMBOL_NOVERS(get_bp_disc_pwup_sd);
7336 EXPORT_SYMBOL_NOVERS(get_bypass_info_sd);
7337 EXPORT_SYMBOL_NOVERS(bp_if_scan_sd);
7339 #define BP_PROC_DIR "bypass"
7341 #define GPIO6_SET_ENTRY_SD "gpio6_set"
7342 #define GPIO6_CLEAR_ENTRY_SD "gpio6_clear"
7344 #define GPIO7_SET_ENTRY_SD "gpio7_set"
7345 #define GPIO7_CLEAR_ENTRY_SD "gpio7_clear"
7347 #define PULSE_SET_ENTRY_SD "pulse_set"
7348 #define ZERO_SET_ENTRY_SD "zero_set"
7349 #define PULSE_GET1_ENTRY_SD "pulse_get1"
7350 #define PULSE_GET2_ENTRY_SD "pulse_get2"
7352 #define CMND_ON_ENTRY_SD "cmnd_on"
7353 #define CMND_OFF_ENTRY_SD "cmnd_off"
7354 #define RESET_CONT_ENTRY_SD "reset_cont"
7357 #define BYPASS_INFO_ENTRY_SD "bypass_info"
7358 #define BYPASS_SLAVE_ENTRY_SD "bypass_slave"
7359 #define BYPASS_CAPS_ENTRY_SD "bypass_caps"
7360 #define WD_SET_CAPS_ENTRY_SD "wd_set_caps"
7361 #define BYPASS_ENTRY_SD "bypass"
7362 #define BYPASS_CHANGE_ENTRY_SD "bypass_change"
7363 #define BYPASS_WD_ENTRY_SD "bypass_wd"
7364 #define WD_EXPIRE_TIME_ENTRY_SD "wd_expire_time"
7365 #define RESET_BYPASS_WD_ENTRY_SD "reset_bypass_wd"
7366 #define DIS_BYPASS_ENTRY_SD "dis_bypass"
7367 #define BYPASS_PWUP_ENTRY_SD "bypass_pwup"
7368 #define BYPASS_PWOFF_ENTRY_SD "bypass_pwoff"
7369 #define STD_NIC_ENTRY_SD "std_nic"
7370 #define STD_NIC_ENTRY_SD "std_nic"
7371 #define TAP_ENTRY_SD "tap"
7372 #define TAP_CHANGE_ENTRY_SD "tap_change"
7373 #define DIS_TAP_ENTRY_SD "dis_tap"
7374 #define TAP_PWUP_ENTRY_SD "tap_pwup"
7375 #define TWO_PORT_LINK_ENTRY_SD "two_port_link"
7376 #define WD_EXP_MODE_ENTRY_SD "wd_exp_mode"
7377 #define WD_AUTORESET_ENTRY_SD "wd_autoreset"
7378 #define TPL_ENTRY_SD "tpl"
7379 #define WAIT_AT_PWUP_ENTRY_SD "wait_at_pwup"
7380 #define HW_RESET_ENTRY_SD "hw_reset"
7381 #define DISC_ENTRY_SD "disc"
7382 #define DISC_CHANGE_ENTRY_SD "disc_change"
7383 #define DIS_DISC_ENTRY_SD "dis_disc"
7384 #define DISC_PWUP_ENTRY_SD "disc_pwup"
7385 static struct proc_dir_entry *bp_procfs_dir;
7387 static struct proc_dir_entry *proc_getdir(char *name,
7388 struct proc_dir_entry *proc_dir)
7390 struct proc_dir_entry *pde = proc_dir;
7392 for (pde = pde->subdir; pde; pde = pde->next) {
7393 if (pde->namelen && (strcmp(name, pde->name) == 0)) {
7394 /* directory exists */
7398 if (pde == (struct proc_dir_entry *)0) {
7399 /* create the directory */
7400 pde = proc_mkdir(name, proc_dir);
7401 if (pde == (struct proc_dir_entry *)0) {
7410 int bp_proc_create(void)
7412 bp_procfs_dir = proc_getdir(BP_PROC_DIR, init_net.proc_net);
7413 if (bp_procfs_dir == (struct proc_dir_entry *)0) {
7415 "Could not create procfs nicinfo directory %s\n",
7423 bypass_proc_create_entry_sd(struct pfs_unit_sd *pfs_unit_curr,
7425 write_proc_t *write_proc,
7426 read_proc_t *read_proc,
7427 struct proc_dir_entry *parent_pfs, void *data)
7429 strcpy(pfs_unit_curr->proc_name, proc_name);
7430 pfs_unit_curr->proc_entry = create_proc_entry(pfs_unit_curr->proc_name,
7433 S_IROTH, parent_pfs);
7434 if (pfs_unit_curr->proc_entry == NULL)
7437 pfs_unit_curr->proc_entry->read_proc = read_proc;
7438 pfs_unit_curr->proc_entry->write_proc = write_proc;
7439 pfs_unit_curr->proc_entry->data = data;
7446 get_bypass_info_pfs(char *page, char **start, off_t off, int count,
7447 int *eof, void *data)
7449 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7452 len += sprintf(page, "Name\t\t\t%s\n", pbp_device_block->name);
7454 sprintf(page + len, "Firmware version\t0x%x\n",
7455 pbp_device_block->bp_fw_ver);
7462 get_bypass_slave_pfs(char *page, char **start, off_t off, int count,
7463 int *eof, void *data)
7465 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7468 bpctl_dev_t *pbp_device_block_slave = NULL;
7470 struct net_device *net_slave_dev = NULL;
7472 if ((pbp_device_block->func == 0) || (pbp_device_block->func == 2)) {
7474 ((bpctl_dev_arr[idx_dev].pdev != NULL)
7475 && (idx_dev < device_num)); idx_dev++) {
7476 if ((bpctl_dev_arr[idx_dev].bus ==
7477 pbp_device_block->bus)
7478 && (bpctl_dev_arr[idx_dev].slot ==
7479 pbp_device_block->slot)) {
7480 if ((pbp_device_block->func == 0)
7481 && (bpctl_dev_arr[idx_dev].func == 1)) {
7482 pbp_device_block_slave =
7483 &bpctl_dev_arr[idx_dev];
7486 if ((pbp_device_block->func == 2) &&
7487 (bpctl_dev_arr[idx_dev].func == 3)) {
7488 pbp_device_block_slave =
7489 &bpctl_dev_arr[idx_dev];
7495 pbp_device_block_slave = pbp_device_block;
7496 if (!pbp_device_block_slave) {
7497 len = sprintf(page, "fail\n");
7501 net_slave_dev = pbp_device_block_slave->ndev;
7503 len = sprintf(page, "%s\n", net_slave_dev->name);
7510 get_bypass_caps_pfs(char *page, char **start, off_t off, int count,
7511 int *eof, void *data)
7513 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7515 int len = 0, ret = 0;
7517 ret = get_bypass_caps_fn(pbp_device_block);
7518 if (ret == BP_NOT_CAP)
7519 len = sprintf(page, "-1\n");
7521 len = sprintf(page, "0x%x\n", ret);
7528 get_wd_set_caps_pfs(char *page, char **start, off_t off, int count,
7529 int *eof, void *data)
7531 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7533 int len = 0, ret = 0;
7535 ret = get_wd_set_caps_fn(pbp_device_block);
7536 if (ret == BP_NOT_CAP)
7537 len = sprintf(page, "-1\n");
7539 len = sprintf(page, "0x%x\n", ret);
7545 set_bypass_pfs(struct file *file, const char *buffer,
7546 unsigned long count, void *data)
7550 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7552 int bypass_param = 0, length = 0;
7554 if (count > (sizeof(kbuf) - 1))
7557 if (copy_from_user(&kbuf, buffer, count)) {
7562 length = strlen(kbuf);
7563 if (kbuf[length - 1] == '\n')
7564 kbuf[--length] = '\0';
7566 if (strcmp(kbuf, "on") == 0)
7568 else if (strcmp(kbuf, "off") == 0)
7571 set_bypass_fn(pbp_device_block, bypass_param);
7577 set_tap_pfs(struct file *file, const char *buffer,
7578 unsigned long count, void *data)
7582 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7584 int tap_param = 0, length = 0;
7586 if (count > (sizeof(kbuf) - 1))
7589 if (copy_from_user(&kbuf, buffer, count)) {
7594 length = strlen(kbuf);
7595 if (kbuf[length - 1] == '\n')
7596 kbuf[--length] = '\0';
7598 if (strcmp(kbuf, "on") == 0)
7600 else if (strcmp(kbuf, "off") == 0)
7603 set_tap_fn(pbp_device_block, tap_param);
7609 set_disc_pfs(struct file *file, const char *buffer,
7610 unsigned long count, void *data)
7614 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7616 int tap_param = 0, length = 0;
7618 if (count > (sizeof(kbuf) - 1))
7621 if (copy_from_user(&kbuf, buffer, count)) {
7626 length = strlen(kbuf);
7627 if (kbuf[length - 1] == '\n')
7628 kbuf[--length] = '\0';
7630 if (strcmp(kbuf, "on") == 0)
7632 else if (strcmp(kbuf, "off") == 0)
7635 set_disc_fn(pbp_device_block, tap_param);
7641 get_bypass_pfs(char *page, char **start, off_t off, int count,
7642 int *eof, void *data)
7644 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7646 int len = 0, ret = 0;
7648 ret = get_bypass_fn(pbp_device_block);
7649 if (ret == BP_NOT_CAP)
7650 len = sprintf(page, "fail\n");
7652 len = sprintf(page, "on\n");
7654 len = sprintf(page, "off\n");
7661 get_tap_pfs(char *page, char **start, off_t off, int count,
7662 int *eof, void *data)
7664 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7666 int len = 0, ret = 0;
7668 ret = get_tap_fn(pbp_device_block);
7669 if (ret == BP_NOT_CAP)
7670 len = sprintf(page, "fail\n");
7672 len = sprintf(page, "on\n");
7674 len = sprintf(page, "off\n");
7681 get_disc_pfs(char *page, char **start, off_t off, int count,
7682 int *eof, void *data)
7684 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7686 int len = 0, ret = 0;
7688 ret = get_disc_fn(pbp_device_block);
7689 if (ret == BP_NOT_CAP)
7690 len = sprintf(page, "fail\n");
7692 len = sprintf(page, "on\n");
7694 len = sprintf(page, "off\n");
7701 get_bypass_change_pfs(char *page, char **start, off_t off, int count,
7702 int *eof, void *data)
7704 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7706 int len = 0, ret = 0;
7708 ret = get_bypass_change_fn(pbp_device_block);
7710 len = sprintf(page, "on\n");
7712 len = sprintf(page, "off\n");
7714 len = sprintf(page, "fail\n");
7721 get_tap_change_pfs(char *page, char **start, off_t off, int count,
7722 int *eof, void *data)
7724 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7726 int len = 0, ret = 0;
7728 ret = get_tap_change_fn(pbp_device_block);
7730 len = sprintf(page, "on\n");
7732 len = sprintf(page, "off\n");
7734 len = sprintf(page, "fail\n");
7741 get_disc_change_pfs(char *page, char **start, off_t off, int count,
7742 int *eof, void *data)
7744 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7746 int len = 0, ret = 0;
7748 ret = get_disc_change_fn(pbp_device_block);
7750 len = sprintf(page, "on\n");
7752 len = sprintf(page, "off\n");
7754 len = sprintf(page, "fail\n");
7760 #define isdigit(c) (c >= '0' && c <= '9')
7761 __inline static int atoi(char **s)
7764 while (isdigit(**s))
7765 i = i * 10 + *((*s)++) - '0';
7770 set_bypass_wd_pfs(struct file *file, const char *buffer,
7771 unsigned long count, void *data)
7773 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7777 ret = kstrtoint_from_user(buffer, count, 10, &timeout);
7780 set_bypass_wd_fn(pbp_device_block, timeout);
7786 get_bypass_wd_pfs(char *page, char **start, off_t off, int count,
7787 int *eof, void *data)
7789 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7791 int len = 0, ret = 0, timeout = 0;
7793 ret = get_bypass_wd_fn(pbp_device_block, &timeout);
7794 if (ret == BP_NOT_CAP)
7795 len = sprintf(page, "fail\n");
7796 else if (timeout == -1)
7797 len = sprintf(page, "unknown\n");
7798 else if (timeout == 0)
7799 len = sprintf(page, "disable\n");
7801 len = sprintf(page, "%d\n", timeout);
7808 get_wd_expire_time_pfs(char *page, char **start, off_t off, int count,
7809 int *eof, void *data)
7811 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7813 int len = 0, ret = 0, timeout = 0;
7815 ret = get_wd_expire_time_fn(pbp_device_block, &timeout);
7816 if (ret == BP_NOT_CAP)
7817 len = sprintf(page, "fail\n");
7818 else if (timeout == -1)
7819 len = sprintf(page, "expire\n");
7820 else if (timeout == 0)
7821 len = sprintf(page, "disable\n");
7824 len = sprintf(page, "%d\n", timeout);
7830 get_tpl_pfs(char *page, char **start, off_t off, int count,
7831 int *eof, void *data)
7833 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7835 int len = 0, ret = 0;
7837 ret = get_tpl_fn(pbp_device_block);
7838 if (ret == BP_NOT_CAP)
7839 len = sprintf(page, "fail\n");
7841 len = sprintf(page, "on\n");
7843 len = sprintf(page, "off\n");
7851 get_wait_at_pwup_pfs(char *page, char **start, off_t off, int count,
7852 int *eof, void *data)
7854 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7856 int len = 0, ret = 0;
7858 ret = get_bp_wait_at_pwup_fn(pbp_device_block);
7859 if (ret == BP_NOT_CAP)
7860 len = sprintf(page, "fail\n");
7862 len = sprintf(page, "on\n");
7864 len = sprintf(page, "off\n");
7871 get_hw_reset_pfs(char *page, char **start, off_t off, int count,
7872 int *eof, void *data)
7874 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7876 int len = 0, ret = 0;
7878 ret = get_bp_hw_reset_fn(pbp_device_block);
7879 if (ret == BP_NOT_CAP)
7880 len = sprintf(page, "fail\n");
7882 len = sprintf(page, "on\n");
7884 len = sprintf(page, "off\n");
7890 #endif /*PMC_WAIT_FLAG */
7893 reset_bypass_wd_pfs(char *page, char **start, off_t off, int count,
7894 int *eof, void *data)
7896 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7898 int len = 0, ret = 0;
7900 ret = reset_bypass_wd_timer_fn(pbp_device_block);
7901 if (ret == BP_NOT_CAP)
7902 len = sprintf(page, "fail\n");
7904 len = sprintf(page, "disable\n");
7906 len = sprintf(page, "success\n");
7913 set_dis_bypass_pfs(struct file *file, const char *buffer,
7914 unsigned long count, void *data)
7918 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7920 int bypass_param = 0, length = 0;
7922 if (count >= sizeof(kbuf))
7925 if (copy_from_user(&kbuf, buffer, count)) {
7930 length = strlen(kbuf);
7931 if (kbuf[length - 1] == '\n')
7932 kbuf[--length] = '\0';
7934 if (strcmp(kbuf, "on") == 0)
7936 else if (strcmp(kbuf, "off") == 0)
7939 set_dis_bypass_fn(pbp_device_block, bypass_param);
7945 set_dis_tap_pfs(struct file *file, const char *buffer,
7946 unsigned long count, void *data)
7950 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7952 int tap_param = 0, length = 0;
7954 if (count >= sizeof(kbuf))
7957 if (copy_from_user(&kbuf, buffer, count)) {
7962 length = strlen(kbuf);
7963 if (kbuf[length - 1] == '\n')
7964 kbuf[--length] = '\0';
7966 if (strcmp(kbuf, "on") == 0)
7968 else if (strcmp(kbuf, "off") == 0)
7971 set_dis_tap_fn(pbp_device_block, tap_param);
7977 set_dis_disc_pfs(struct file *file, const char *buffer,
7978 unsigned long count, void *data)
7982 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7984 int tap_param = 0, length = 0;
7986 if (count >= sizeof(kbuf))
7989 if (copy_from_user(&kbuf, buffer, count)) {
7994 length = strlen(kbuf);
7995 if (kbuf[length - 1] == '\n')
7996 kbuf[--length] = '\0';
7998 if (strcmp(kbuf, "on") == 0)
8000 else if (strcmp(kbuf, "off") == 0)
8003 set_dis_disc_fn(pbp_device_block, tap_param);
8009 get_dis_bypass_pfs(char *page, char **start, off_t off, int count,
8010 int *eof, void *data)
8012 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8014 int len = 0, ret = 0;
8016 ret = get_dis_bypass_fn(pbp_device_block);
8017 if (ret == BP_NOT_CAP)
8018 len = sprintf(page, "fail\n");
8020 len = sprintf(page, "off\n");
8022 len = sprintf(page, "on\n");
8029 get_dis_tap_pfs(char *page, char **start, off_t off, int count,
8030 int *eof, void *data)
8032 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8034 int len = 0, ret = 0;
8036 ret = get_dis_tap_fn(pbp_device_block);
8037 if (ret == BP_NOT_CAP)
8038 len = sprintf(page, "fail\n");
8040 len = sprintf(page, "off\n");
8042 len = sprintf(page, "on\n");
8049 get_dis_disc_pfs(char *page, char **start, off_t off, int count,
8050 int *eof, void *data)
8052 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8054 int len = 0, ret = 0;
8056 ret = get_dis_disc_fn(pbp_device_block);
8057 if (ret == BP_NOT_CAP)
8058 len = sprintf(page, "fail\n");
8060 len = sprintf(page, "off\n");
8062 len = sprintf(page, "on\n");
8069 set_bypass_pwup_pfs(struct file *file, const char *buffer,
8070 unsigned long count, void *data)
8074 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8076 int bypass_param = 0, length = 0;
8078 if (count >= sizeof(kbuf))
8081 if (copy_from_user(&kbuf, buffer, count)) {
8086 length = strlen(kbuf);
8087 if (kbuf[length - 1] == '\n')
8088 kbuf[--length] = '\0';
8090 if (strcmp(kbuf, "on") == 0)
8092 else if (strcmp(kbuf, "off") == 0)
8095 set_bypass_pwup_fn(pbp_device_block, bypass_param);
8101 set_bypass_pwoff_pfs(struct file *file, const char *buffer,
8102 unsigned long count, void *data)
8106 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8108 int bypass_param = 0, length = 0;
8110 if (count >= sizeof(kbuf))
8113 if (copy_from_user(&kbuf, buffer, count)) {
8118 length = strlen(kbuf);
8119 if (kbuf[length - 1] == '\n')
8120 kbuf[--length] = '\0';
8122 if (strcmp(kbuf, "on") == 0)
8124 else if (strcmp(kbuf, "off") == 0)
8127 set_bypass_pwoff_fn(pbp_device_block, bypass_param);
8133 set_tap_pwup_pfs(struct file *file, const char *buffer,
8134 unsigned long count, void *data)
8138 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8140 int tap_param = 0, length = 0;
8142 if (count >= sizeof(kbuf))
8145 if (copy_from_user(&kbuf, buffer, count)) {
8150 length = strlen(kbuf);
8151 if (kbuf[length - 1] == '\n')
8152 kbuf[--length] = '\0';
8154 if (strcmp(kbuf, "on") == 0)
8156 else if (strcmp(kbuf, "off") == 0)
8159 set_tap_pwup_fn(pbp_device_block, tap_param);
8165 set_disc_pwup_pfs(struct file *file, const char *buffer,
8166 unsigned long count, void *data)
8170 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8172 int tap_param = 0, length = 0;
8174 if (count >= sizeof(kbuf))
8177 if (copy_from_user(&kbuf, buffer, count)) {
8182 length = strlen(kbuf);
8183 if (kbuf[length - 1] == '\n')
8184 kbuf[--length] = '\0';
8186 if (strcmp(kbuf, "on") == 0)
8188 else if (strcmp(kbuf, "off") == 0)
8191 set_disc_pwup_fn(pbp_device_block, tap_param);
8197 get_bypass_pwup_pfs(char *page, char **start, off_t off, int count,
8198 int *eof, void *data)
8200 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8202 int len = 0, ret = 0;
8204 ret = get_bypass_pwup_fn(pbp_device_block);
8205 if (ret == BP_NOT_CAP)
8206 len = sprintf(page, "fail\n");
8208 len = sprintf(page, "off\n");
8210 len = sprintf(page, "on\n");
8217 get_bypass_pwoff_pfs(char *page, char **start, off_t off, int count,
8218 int *eof, void *data)
8220 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8222 int len = 0, ret = 0;
8224 ret = get_bypass_pwoff_fn(pbp_device_block);
8225 if (ret == BP_NOT_CAP)
8226 len = sprintf(page, "fail\n");
8228 len = sprintf(page, "off\n");
8230 len = sprintf(page, "on\n");
8237 get_tap_pwup_pfs(char *page, char **start, off_t off, int count,
8238 int *eof, void *data)
8240 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8242 int len = 0, ret = 0;
8244 ret = get_tap_pwup_fn(pbp_device_block);
8245 if (ret == BP_NOT_CAP)
8246 len = sprintf(page, "fail\n");
8248 len = sprintf(page, "off\n");
8250 len = sprintf(page, "on\n");
8257 get_disc_pwup_pfs(char *page, char **start, off_t off, int count,
8258 int *eof, void *data)
8260 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8262 int len = 0, ret = 0;
8264 ret = get_disc_pwup_fn(pbp_device_block);
8265 if (ret == BP_NOT_CAP)
8266 len = sprintf(page, "fail\n");
8268 len = sprintf(page, "off\n");
8270 len = sprintf(page, "on\n");
8277 set_std_nic_pfs(struct file *file, const char *buffer,
8278 unsigned long count, void *data)
8282 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8284 int bypass_param = 0, length = 0;
8286 if (count >= sizeof(kbuf))
8289 if (copy_from_user(&kbuf, buffer, count)) {
8294 length = strlen(kbuf);
8295 if (kbuf[length - 1] == '\n')
8296 kbuf[--length] = '\0';
8298 if (strcmp(kbuf, "on") == 0)
8300 else if (strcmp(kbuf, "off") == 0)
8303 set_std_nic_fn(pbp_device_block, bypass_param);
8309 get_std_nic_pfs(char *page, char **start, off_t off, int count,
8310 int *eof, void *data)
8312 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8314 int len = 0, ret = 0;
8316 ret = get_std_nic_fn(pbp_device_block);
8317 if (ret == BP_NOT_CAP)
8318 len = sprintf(page, "fail\n");
8320 len = sprintf(page, "off\n");
8322 len = sprintf(page, "on\n");
8329 get_wd_exp_mode_pfs(char *page, char **start, off_t off, int count,
8330 int *eof, void *data)
8332 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8334 int len = 0, ret = 0;
8336 ret = get_wd_exp_mode_fn(pbp_device_block);
8338 len = sprintf(page, "tap\n");
8340 len = sprintf(page, "bypass\n");
8342 len = sprintf(page, "disc\n");
8345 len = sprintf(page, "fail\n");
8352 set_wd_exp_mode_pfs(struct file *file, const char *buffer,
8353 unsigned long count, void *data)
8357 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8359 int bypass_param = 0, length = 0;
8361 if (count > (sizeof(kbuf) - 1))
8364 if (copy_from_user(&kbuf, buffer, count)) {
8369 length = strlen(kbuf);
8370 if (kbuf[length - 1] == '\n')
8371 kbuf[--length] = '\0';
8373 if (strcmp(kbuf, "tap") == 0)
8375 else if (strcmp(kbuf, "bypass") == 0)
8377 else if (strcmp(kbuf, "disc") == 0)
8380 set_wd_exp_mode_fn(pbp_device_block, bypass_param);
8386 get_wd_autoreset_pfs(char *page, char **start, off_t off, int count,
8387 int *eof, void *data)
8389 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8391 int len = 0, ret = 0;
8393 ret = get_wd_autoreset_fn(pbp_device_block);
8395 len = sprintf(page, "%d\n", ret);
8397 len = sprintf(page, "fail\n");
8404 set_wd_autoreset_pfs(struct file *file, const char *buffer,
8405 unsigned long count, void *data)
8407 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8411 ret = kstrtoint_from_user(buffer, count, 10, &timeout);
8414 set_wd_autoreset_fn(pbp_device_block, timeout);
8420 set_tpl_pfs(struct file *file, const char *buffer,
8421 unsigned long count, void *data)
8425 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8427 int tpl_param = 0, length = 0;
8429 if (count > (sizeof(kbuf) - 1))
8432 if (copy_from_user(&kbuf, buffer, count)) {
8437 length = strlen(kbuf);
8438 if (kbuf[length - 1] == '\n')
8439 kbuf[--length] = '\0';
8441 if (strcmp(kbuf, "on") == 0)
8443 else if (strcmp(kbuf, "off") == 0)
8446 set_tpl_fn(pbp_device_block, tpl_param);
8453 set_wait_at_pwup_pfs(struct file *file, const char *buffer,
8454 unsigned long count, void *data)
8458 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8460 int tpl_param = 0, length = 0;
8462 if (count > (sizeof(kbuf) - 1))
8465 if (copy_from_user(&kbuf, buffer, count)) {
8470 length = strlen(kbuf);
8471 if (kbuf[length - 1] == '\n')
8472 kbuf[--length] = '\0';
8474 if (strcmp(kbuf, "on") == 0)
8476 else if (strcmp(kbuf, "off") == 0)
8479 set_bp_wait_at_pwup_fn(pbp_device_block, tpl_param);
8485 set_hw_reset_pfs(struct file *file, const char *buffer,
8486 unsigned long count, void *data)
8490 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8492 int tpl_param = 0, length = 0;
8494 if (count > (sizeof(kbuf) - 1))
8497 if (copy_from_user(&kbuf, buffer, count)) {
8502 length = strlen(kbuf);
8503 if (kbuf[length - 1] == '\n')
8504 kbuf[--length] = '\0';
8506 if (strcmp(kbuf, "on") == 0)
8508 else if (strcmp(kbuf, "off") == 0)
8511 set_bp_hw_reset_fn(pbp_device_block, tpl_param);
8516 #endif /*PMC_FIX_FLAG */
8518 int bypass_proc_create_dev_sd(bpctl_dev_t *pbp_device_block)
8520 struct bypass_pfs_sd *current_pfs = &(pbp_device_block->bypass_pfs_set);
8521 static struct proc_dir_entry *procfs_dir = NULL;
8524 if (!pbp_device_block->ndev)
8526 sprintf(current_pfs->dir_name, "bypass_%s",
8527 pbp_device_block->ndev->name);
8532 /* create device proc dir */
8533 procfs_dir = proc_getdir(current_pfs->dir_name, bp_procfs_dir);
8534 if (procfs_dir == 0) {
8535 printk(KERN_DEBUG "Could not create procfs directory %s\n",
8536 current_pfs->dir_name);
8539 current_pfs->bypass_entry = procfs_dir;
8541 if (bypass_proc_create_entry_sd(&(current_pfs->bypass_info), BYPASS_INFO_ENTRY_SD, NULL, /* write */
8542 get_bypass_info_pfs, /* read */
8543 procfs_dir, pbp_device_block))
8546 if (pbp_device_block->bp_caps & SW_CTL_CAP) {
8548 /* Create set param proc's */
8549 if (bypass_proc_create_entry_sd(&(current_pfs->bypass_slave), BYPASS_SLAVE_ENTRY_SD, NULL, /* write */
8550 get_bypass_slave_pfs, /* read */
8551 procfs_dir, pbp_device_block))
8554 if (bypass_proc_create_entry_sd(&(current_pfs->bypass_caps), BYPASS_CAPS_ENTRY_SD, NULL, /* write */
8555 get_bypass_caps_pfs, /* read */
8556 procfs_dir, pbp_device_block))
8559 if (bypass_proc_create_entry_sd(&(current_pfs->wd_set_caps), WD_SET_CAPS_ENTRY_SD, NULL, /* write */
8560 get_wd_set_caps_pfs, /* read */
8561 procfs_dir, pbp_device_block))
8563 if (bypass_proc_create_entry_sd(&(current_pfs->bypass_wd), BYPASS_WD_ENTRY_SD, set_bypass_wd_pfs, /* write */
8564 get_bypass_wd_pfs, /* read */
8565 procfs_dir, pbp_device_block))
8568 if (bypass_proc_create_entry_sd(&(current_pfs->wd_expire_time), WD_EXPIRE_TIME_ENTRY_SD, NULL, /* write */
8569 get_wd_expire_time_pfs, /* read */
8570 procfs_dir, pbp_device_block))
8573 if (bypass_proc_create_entry_sd(&(current_pfs->reset_bypass_wd), RESET_BYPASS_WD_ENTRY_SD, NULL, /* write */
8574 reset_bypass_wd_pfs, /* read */
8575 procfs_dir, pbp_device_block))
8578 if (bypass_proc_create_entry_sd(&(current_pfs->std_nic), STD_NIC_ENTRY_SD, set_std_nic_pfs, /* write */
8579 get_std_nic_pfs, /* read */
8580 procfs_dir, pbp_device_block))
8583 if (pbp_device_block->bp_caps & BP_CAP) {
8584 if (bypass_proc_create_entry_sd(&(current_pfs->bypass), BYPASS_ENTRY_SD, set_bypass_pfs, /* write */
8585 get_bypass_pfs, /* read */
8590 if (bypass_proc_create_entry_sd(&(current_pfs->dis_bypass), DIS_BYPASS_ENTRY_SD, set_dis_bypass_pfs, /* write */
8591 get_dis_bypass_pfs, /* read */
8596 if (bypass_proc_create_entry_sd(&(current_pfs->bypass_pwup), BYPASS_PWUP_ENTRY_SD, set_bypass_pwup_pfs, /* write */
8597 get_bypass_pwup_pfs, /* read */
8601 if (bypass_proc_create_entry_sd(&(current_pfs->bypass_pwoff), BYPASS_PWOFF_ENTRY_SD, set_bypass_pwoff_pfs, /* write */
8602 get_bypass_pwoff_pfs, /* read */
8607 if (bypass_proc_create_entry_sd(&(current_pfs->bypass_change), BYPASS_CHANGE_ENTRY_SD, NULL, /* write */
8608 get_bypass_change_pfs, /* read */
8614 if (pbp_device_block->bp_caps & TAP_CAP) {
8616 if (bypass_proc_create_entry_sd(&(current_pfs->tap), TAP_ENTRY_SD, set_tap_pfs, /* write */
8617 get_tap_pfs, /* read */
8622 if (bypass_proc_create_entry_sd(&(current_pfs->dis_tap), DIS_TAP_ENTRY_SD, set_dis_tap_pfs, /* write */
8623 get_dis_tap_pfs, /* read */
8628 if (bypass_proc_create_entry_sd(&(current_pfs->tap_pwup), TAP_PWUP_ENTRY_SD, set_tap_pwup_pfs, /* write */
8629 get_tap_pwup_pfs, /* read */
8634 if (bypass_proc_create_entry_sd(&(current_pfs->tap_change), TAP_CHANGE_ENTRY_SD, NULL, /* write */
8635 get_tap_change_pfs, /* read */
8640 if (pbp_device_block->bp_caps & DISC_CAP) {
8642 if (bypass_proc_create_entry_sd(&(current_pfs->tap), DISC_ENTRY_SD, set_disc_pfs, /* write */
8643 get_disc_pfs, /* read */
8649 if (bypass_proc_create_entry_sd(&(current_pfs->dis_tap), DIS_DISC_ENTRY_SD, set_dis_disc_pfs, /* write */
8650 get_dis_disc_pfs, /* read */
8656 if (bypass_proc_create_entry_sd(&(current_pfs->tap_pwup), DISC_PWUP_ENTRY_SD, set_disc_pwup_pfs, /* write */
8657 get_disc_pwup_pfs, /* read */
8662 if (bypass_proc_create_entry_sd(&(current_pfs->tap_change), DISC_CHANGE_ENTRY_SD, NULL, /* write */
8663 get_disc_change_pfs, /* read */
8669 if (bypass_proc_create_entry_sd(&(current_pfs->wd_exp_mode), WD_EXP_MODE_ENTRY_SD, set_wd_exp_mode_pfs, /* write */
8670 get_wd_exp_mode_pfs, /* read */
8671 procfs_dir, pbp_device_block))
8674 if (bypass_proc_create_entry_sd(&(current_pfs->wd_autoreset), WD_AUTORESET_ENTRY_SD, set_wd_autoreset_pfs, /* write */
8675 get_wd_autoreset_pfs, /* read */
8676 procfs_dir, pbp_device_block))
8678 if (bypass_proc_create_entry_sd(&(current_pfs->tpl), TPL_ENTRY_SD, set_tpl_pfs, /* write */
8679 get_tpl_pfs, /* read */
8680 procfs_dir, pbp_device_block))
8683 if (bypass_proc_create_entry_sd(&(current_pfs->tpl), WAIT_AT_PWUP_ENTRY_SD, set_wait_at_pwup_pfs, /* write */
8684 get_wait_at_pwup_pfs, /* read */
8685 procfs_dir, pbp_device_block))
8687 if (bypass_proc_create_entry_sd(&(current_pfs->tpl), HW_RESET_ENTRY_SD, set_hw_reset_pfs, /* write */
8688 get_hw_reset_pfs, /* read */
8689 procfs_dir, pbp_device_block))
8696 printk(KERN_DEBUG "Create proc entry failed\n");
8701 int bypass_proc_remove_dev_sd(bpctl_dev_t *pbp_device_block)
8704 struct bypass_pfs_sd *current_pfs = &pbp_device_block->bypass_pfs_set;
8705 struct proc_dir_entry *pde = current_pfs->bypass_entry, *pde_curr =
8711 for (pde = pde->subdir; pde;) {
8712 strcpy(name, pde->name);
8715 remove_proc_entry(name, current_pfs->bypass_entry);
8718 remove_proc_entry(current_pfs->dir_name, bp_procfs_dir);
8719 current_pfs->bypass_entry = NULL;