1 /******************************************************************************/
3 /* Bypass Control utility, Copyright (c) 2005-20011 Silicom */
5 /* This program is free software; you can redistribute it and/or modify */
6 /* it under the terms of the GNU General Public License as published by */
7 /* the Free Software Foundation, located in the file LICENSE. */
8 /* Copyright(c) 2007 - 2009 Intel Corporation. All rights reserved. */
11 /******************************************************************************/
12 #include <linux/version.h>
14 #include <linux/kernel.h> /* We're doing kernel work */
15 #include <linux/module.h> /* Specifically, a module */
17 #include <linux/pci.h>
18 #include <linux/delay.h>
19 #include <linux/netdevice.h>
20 #include <linux/rtnetlink.h>
21 #include <linux/rcupdate.h>
22 #include <linux/etherdevice.h>
24 #include <linux/uaccess.h> /* for get_user and put_user */
25 #include <linux/sched.h>
26 #include <linux/ethtool.h>
27 #include <linux/proc_fs.h>
35 #define BP_MOD_VER "9.0.4"
36 #define BP_MOD_DESCR "Silicom Bypass-SD Control driver"
37 #define BP_SYNC_FLAG 1
39 static int Device_Open = 0;
40 static int major_num = 0;
42 MODULE_AUTHOR("Anna Lukin, annal@silicom.co.il");
43 MODULE_LICENSE("GPL");
44 MODULE_DESCRIPTION(BP_MOD_DESCR);
45 MODULE_VERSION(BP_MOD_VER);
48 #define lock_bpctl() \
49 if (down_interruptible(&bpctl_sema)) { \
50 return -ERESTARTSYS; \
53 #define unlock_bpctl() \
65 struct proc_dir_entry *proc_entry;
69 struct bypass_pfs_sd {
71 struct proc_dir_entry *bypass_entry;
72 struct pfs_unit_sd bypass_info;
73 struct pfs_unit_sd bypass_slave;
74 struct pfs_unit_sd bypass_caps;
75 struct pfs_unit_sd wd_set_caps;
76 struct pfs_unit_sd bypass;
77 struct pfs_unit_sd bypass_change;
78 struct pfs_unit_sd bypass_wd;
79 struct pfs_unit_sd wd_expire_time;
80 struct pfs_unit_sd reset_bypass_wd;
81 struct pfs_unit_sd dis_bypass;
82 struct pfs_unit_sd bypass_pwup;
83 struct pfs_unit_sd bypass_pwoff;
84 struct pfs_unit_sd std_nic;
85 struct pfs_unit_sd tap;
86 struct pfs_unit_sd dis_tap;
87 struct pfs_unit_sd tap_pwup;
88 struct pfs_unit_sd tap_change;
89 struct pfs_unit_sd wd_exp_mode;
90 struct pfs_unit_sd wd_autoreset;
91 struct pfs_unit_sd tpl;
95 typedef struct _bpctl_dev {
98 struct pci_dev *pdev; /* PCI device */
99 struct net_device *ndev; /* net device */
100 unsigned long mem_map;
114 unsigned long bypass_wdt_on_time;
115 uint32_t bypass_timer_interval;
116 struct timer_list bp_timer;
118 uint8_t bp_status_un;
120 bp_media_type media_type;
122 struct timer_list bp_tpl_timer;
123 spinlock_t bypass_wr_lock;
130 int (*hard_start_xmit_save) (struct sk_buff *skb,
131 struct net_device *dev);
132 const struct net_device_ops *old_ops;
133 struct net_device_ops new_ops;
134 int bp_self_test_flag;
136 struct bypass_pfs_sd bypass_pfs_set;
140 static bpctl_dev_t *bpctl_dev_arr;
142 static struct semaphore bpctl_sema;
143 static int device_num = 0;
145 static int get_dev_idx(int ifindex);
146 static bpctl_dev_t *get_master_port_fn(bpctl_dev_t *pbpctl_dev);
147 static int disc_status(bpctl_dev_t *pbpctl_dev);
148 static int bypass_status(bpctl_dev_t *pbpctl_dev);
149 static int wdt_timer(bpctl_dev_t *pbpctl_dev, int *time_left);
150 static bpctl_dev_t *get_status_port_fn(bpctl_dev_t *pbpctl_dev);
151 static void if_scan_init(void);
153 int bypass_proc_create_dev_sd(bpctl_dev_t *pbp_device_block);
154 int bypass_proc_remove_dev_sd(bpctl_dev_t *pbp_device_block);
155 int bp_proc_create(void);
157 int is_bypass_fn(bpctl_dev_t *pbpctl_dev);
158 int get_dev_idx_bsf(int bus, int slot, int func);
160 static unsigned long str_to_hex(char *p);
161 static int bp_device_event(struct notifier_block *unused,
162 unsigned long event, void *ptr)
164 struct net_device *dev = ptr;
165 static bpctl_dev_t *pbpctl_dev = NULL, *pbpctl_dev_m = NULL;
166 int dev_num = 0, ret = 0, ret_d = 0, time_left = 0;
167 /* printk("BP_PROC_SUPPORT event =%d %s %d\n", event,dev->name, dev->ifindex ); */
168 /* return NOTIFY_DONE; */
171 if (event == NETDEV_REGISTER) {
173 struct ethtool_drvinfo drvinfo;
177 int i = 0, ifindex, idx_dev = 0;
178 int bus = 0, slot = 0, func = 0;
179 ifindex = dev->ifindex;
182 memset(&drvinfo, 0, sizeof(struct ethtool_drvinfo));
184 if (dev->ethtool_ops && dev->ethtool_ops->get_drvinfo) {
185 memset(&drvinfo, 0, sizeof(drvinfo));
186 dev->ethtool_ops->get_drvinfo(dev, &drvinfo);
189 if (!drvinfo.bus_info)
191 if (!strcmp(drvinfo.bus_info, "N/A"))
193 memcpy(&cbuf, drvinfo.bus_info, 32);
196 while (*buf++ != ':') ;
197 for (i = 0; i < 10; i++, buf++) {
204 bus = str_to_hex(res);
207 for (i = 0; i < 10; i++, buf++) {
214 slot = str_to_hex(res);
215 func = str_to_hex(buf);
216 idx_dev = get_dev_idx_bsf(bus, slot, func);
220 bpctl_dev_arr[idx_dev].ifindex = ifindex;
221 bpctl_dev_arr[idx_dev].ndev = dev;
223 bypass_proc_remove_dev_sd(&bpctl_dev_arr
225 bypass_proc_create_dev_sd(&bpctl_dev_arr
234 if (event == NETDEV_UNREGISTER) {
237 ((bpctl_dev_arr[idx_dev].pdev != NULL)
238 && (idx_dev < device_num)); idx_dev++) {
239 if (bpctl_dev_arr[idx_dev].ndev == dev) {
240 bypass_proc_remove_dev_sd(&bpctl_dev_arr
242 bpctl_dev_arr[idx_dev].ndev = NULL;
251 if (event == NETDEV_CHANGENAME) {
254 ((bpctl_dev_arr[idx_dev].pdev != NULL)
255 && (idx_dev < device_num)); idx_dev++) {
256 if (bpctl_dev_arr[idx_dev].ndev == dev) {
257 bypass_proc_remove_dev_sd(&bpctl_dev_arr
259 bypass_proc_create_dev_sd(&bpctl_dev_arr
274 if (netif_carrier_ok(dev))
277 if (((dev_num = get_dev_idx(dev->ifindex)) == -1) ||
278 (!(pbpctl_dev = &bpctl_dev_arr[dev_num])))
281 if ((is_bypass_fn(pbpctl_dev)) == 1)
282 pbpctl_dev_m = pbpctl_dev;
284 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
287 ret = bypass_status(pbpctl_dev_m);
289 printk("bpmod: %s is in the Bypass mode now",
291 ret_d = disc_status(pbpctl_dev_m);
294 ("bpmod: %s is in the Disconnect mode now",
297 wdt_timer(pbpctl_dev_m, &time_left);
299 printk("; WDT has expired");
315 static struct notifier_block bp_notifier_block = {
316 .notifier_call = bp_device_event,
319 static int device_open(struct inode *inode, struct file *file)
322 printk("device_open(%p)\n", file);
326 * Initialize the message
331 static int device_release(struct inode *inode, struct file *file)
334 printk("device_release(%p,%p)\n", inode, file);
340 int is_bypass_fn(bpctl_dev_t *pbpctl_dev);
341 int wdt_time_left(bpctl_dev_t *pbpctl_dev);
343 static void write_pulse(bpctl_dev_t *pbpctl_dev,
344 unsigned int ctrl_ext,
345 unsigned char value, unsigned char len)
347 unsigned char ctrl_val = 0;
348 unsigned int i = len;
349 unsigned int ctrl = 0;
350 bpctl_dev_t *pbpctl_dev_c = NULL;
352 if (pbpctl_dev->bp_i80)
353 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
354 if (pbpctl_dev->bp_540)
355 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
357 if (pbpctl_dev->bp_10g9) {
358 if (!(pbpctl_dev_c = get_status_port_fn(pbpctl_dev)))
360 ctrl = BP10G_READ_REG(pbpctl_dev_c, ESDP);
364 ctrl_val = (value >> i) & 0x1;
366 if (pbpctl_dev->bp_10g9) {
368 /* To start management : MCLK 1, MDIO 1, output */
370 /*BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext|BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9)); */
371 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
373 BP10G_MDIO_DATA_OUT9);
374 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
375 (ctrl | BP10G_MCLK_DATA_OUT9 |
376 BP10G_MCLK_DIR_OUT9));
378 } else if (pbpctl_dev->bp_fiber5) {
379 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, (ctrl_ext |
380 BPCTLI_CTRL_EXT_MCLK_DIR5
382 BPCTLI_CTRL_EXT_MDIO_DIR5
384 BPCTLI_CTRL_EXT_MDIO_DATA5
386 BPCTLI_CTRL_EXT_MCLK_DATA5));
388 } else if (pbpctl_dev->bp_i80) {
389 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, (ctrl_ext |
390 BPCTLI_CTRL_EXT_MDIO_DIR80
392 BPCTLI_CTRL_EXT_MDIO_DATA80));
394 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, (ctrl |
395 BPCTLI_CTRL_EXT_MCLK_DIR80
397 BPCTLI_CTRL_EXT_MCLK_DATA80));
399 } else if (pbpctl_dev->bp_540) {
400 BP10G_WRITE_REG(pbpctl_dev, ESDP, (ctrl |
409 } else if (pbpctl_dev->bp_10gb) {
410 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
411 (ctrl_ext | BP10GB_MDIO_SET |
418 } else if (!pbpctl_dev->bp_10g)
419 /* To start management : MCLK 1, MDIO 1, output */
420 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
422 BPCTLI_CTRL_EXT_MCLK_DIR |
423 BPCTLI_CTRL_EXT_MDIO_DIR |
424 BPCTLI_CTRL_EXT_MDIO_DATA |
425 BPCTLI_CTRL_EXT_MCLK_DATA));
428 /* To start management : MCLK 1, MDIO 1, output*/
429 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
430 (ctrl_ext | BP10G_MCLK_DATA_OUT
431 | BP10G_MDIO_DATA_OUT));
435 usec_delay(PULSE_TIME);
436 if (pbpctl_dev->bp_10g9) {
438 /*BP10G_WRITE_REG(pbpctl_dev, I2CCTL, ((ctrl_ext|BP10G_MDIO_DATA_OUT9)&~(BP10G_MCLK_DATA_OUT9))); */
440 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
442 BP10G_MDIO_DATA_OUT9);
443 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
444 (ctrl | BP10G_MCLK_DIR_OUT9) &
445 ~BP10G_MCLK_DATA_OUT9);
447 } else if (pbpctl_dev->bp_fiber5) {
448 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
450 BPCTLI_CTRL_EXT_MCLK_DIR5 |
451 BPCTLI_CTRL_EXT_MDIO_DIR5 |
452 BPCTLI_CTRL_EXT_MDIO_DATA5)
455 (BPCTLI_CTRL_EXT_MCLK_DATA5)));
457 } else if (pbpctl_dev->bp_i80) {
458 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, (ctrl_ext |
459 BPCTLI_CTRL_EXT_MDIO_DIR80
461 BPCTLI_CTRL_EXT_MDIO_DATA80));
462 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
464 BPCTLI_CTRL_EXT_MCLK_DIR80)
467 (BPCTLI_CTRL_EXT_MCLK_DATA80)));
469 } else if (pbpctl_dev->bp_540) {
470 BP10G_WRITE_REG(pbpctl_dev, ESDP,
471 (ctrl | BP540_MDIO_DIR |
476 } else if (pbpctl_dev->bp_10gb) {
478 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
479 (ctrl_ext | BP10GB_MDIO_SET |
486 } else if (!pbpctl_dev->bp_10g)
488 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
490 BPCTLI_CTRL_EXT_MCLK_DIR |
491 BPCTLI_CTRL_EXT_MDIO_DIR |
492 BPCTLI_CTRL_EXT_MDIO_DATA)
495 (BPCTLI_CTRL_EXT_MCLK_DATA)));
498 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
500 BP10G_MDIO_DATA_OUT) &
501 ~(BP10G_MCLK_DATA_OUT)));
504 usec_delay(PULSE_TIME);
507 if (pbpctl_dev->bp_10g9) {
509 /*BP10G_WRITE_REG(pbpctl_dev, I2CCTL, ((ctrl_ext|BP10G_MCLK_DATA_OUT9)&~BP10G_MDIO_DATA_OUT9)); */
510 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
512 ~BP10G_MDIO_DATA_OUT9));
513 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
514 (ctrl | BP10G_MCLK_DATA_OUT9 |
515 BP10G_MCLK_DIR_OUT9));
517 } else if (pbpctl_dev->bp_fiber5) {
518 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
520 BPCTLI_CTRL_EXT_MCLK_DIR5 |
521 BPCTLI_CTRL_EXT_MDIO_DIR5 |
522 BPCTLI_CTRL_EXT_MCLK_DATA5)
525 (BPCTLI_CTRL_EXT_MDIO_DATA5)));
527 } else if (pbpctl_dev->bp_i80) {
528 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
530 BPCTLI_CTRL_EXT_MDIO_DIR80)
533 (BPCTLI_CTRL_EXT_MDIO_DATA80)));
534 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
536 BPCTLI_CTRL_EXT_MCLK_DIR80 |
537 BPCTLI_CTRL_EXT_MCLK_DATA80));
539 } else if (pbpctl_dev->bp_540) {
540 BP10G_WRITE_REG(pbpctl_dev, ESDP,
541 ((ctrl | BP540_MCLK_DIR |
544 ~(BP540_MDIO_DATA)));
546 } else if (pbpctl_dev->bp_10gb) {
547 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
548 (ctrl_ext | BP10GB_MDIO_CLR |
555 } else if (!pbpctl_dev->bp_10g)
557 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
559 BPCTLI_CTRL_EXT_MCLK_DIR |
560 BPCTLI_CTRL_EXT_MDIO_DIR |
561 BPCTLI_CTRL_EXT_MCLK_DATA)
564 (BPCTLI_CTRL_EXT_MDIO_DATA)));
567 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
569 BP10G_MCLK_DATA_OUT) &
570 ~BP10G_MDIO_DATA_OUT));
573 usec_delay(PULSE_TIME);
574 if (pbpctl_dev->bp_10g9) {
576 /*BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext&~(BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9))); */
577 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
579 ~BP10G_MDIO_DATA_OUT9));
580 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
581 ((ctrl | BP10G_MCLK_DIR_OUT9) &
582 ~(BP10G_MCLK_DATA_OUT9)));
584 } else if (pbpctl_dev->bp_fiber5) {
585 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
587 BPCTLI_CTRL_EXT_MCLK_DIR5 |
588 BPCTLI_CTRL_EXT_MDIO_DIR5)
590 ~(BPCTLI_CTRL_EXT_MCLK_DATA5
592 BPCTLI_CTRL_EXT_MDIO_DATA5)));
594 } else if (pbpctl_dev->bp_i80) {
595 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
597 BPCTLI_CTRL_EXT_MDIO_DIR80)
599 ~BPCTLI_CTRL_EXT_MDIO_DATA80));
600 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
602 BPCTLI_CTRL_EXT_MCLK_DIR80)
605 (BPCTLI_CTRL_EXT_MCLK_DATA80)));
607 } else if (pbpctl_dev->bp_540) {
608 BP10G_WRITE_REG(pbpctl_dev, ESDP,
609 ((ctrl | BP540_MCLK_DIR |
613 } else if (pbpctl_dev->bp_10gb) {
615 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
616 (ctrl_ext | BP10GB_MDIO_CLR |
623 } else if (!pbpctl_dev->bp_10g)
624 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
626 BPCTLI_CTRL_EXT_MCLK_DIR |
627 BPCTLI_CTRL_EXT_MDIO_DIR) &
628 ~(BPCTLI_CTRL_EXT_MCLK_DATA
630 BPCTLI_CTRL_EXT_MDIO_DATA)));
633 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
635 ~(BP10G_MCLK_DATA_OUT |
636 BP10G_MDIO_DATA_OUT)));
639 usec_delay(PULSE_TIME);
645 static int read_pulse(bpctl_dev_t *pbpctl_dev, unsigned int ctrl_ext,
648 unsigned char ctrl_val = 0;
649 unsigned int i = len;
650 unsigned int ctrl = 0;
651 bpctl_dev_t *pbpctl_dev_c = NULL;
653 if (pbpctl_dev->bp_i80)
654 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
655 if (pbpctl_dev->bp_540)
656 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
657 if (pbpctl_dev->bp_10g9) {
658 if (!(pbpctl_dev_c = get_status_port_fn(pbpctl_dev)))
660 ctrl = BP10G_READ_REG(pbpctl_dev_c, ESDP);
665 if (pbpctl_dev->bp_10g9) {
666 /*BP10G_WRITE_REG(pbpctl_dev, I2CCTL, ((ctrl_ext|BP10G_MDIO_DATA_OUT9)&~BP10G_MCLK_DATA_OUT9)); */
668 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
669 ((ctrl | BP10G_MCLK_DIR_OUT9) &
670 ~(BP10G_MCLK_DATA_OUT9)));
672 } else if (pbpctl_dev->bp_fiber5) {
673 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
674 BPCTLI_CTRL_EXT_MCLK_DIR5)
677 (BPCTLI_CTRL_EXT_MDIO_DIR5
679 BPCTLI_CTRL_EXT_MCLK_DATA5)));
681 } else if (pbpctl_dev->bp_i80) {
682 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
684 ~BPCTLI_CTRL_EXT_MDIO_DIR80));
685 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
686 ((ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80)
687 & ~(BPCTLI_CTRL_EXT_MCLK_DATA80)));
689 } else if (pbpctl_dev->bp_540) {
690 BP10G_WRITE_REG(pbpctl_dev, ESDP,
691 ((ctrl | BP540_MCLK_DIR) &
692 ~(BP540_MDIO_DIR | BP540_MCLK_DATA)));
694 } else if (pbpctl_dev->bp_10gb) {
696 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
697 (ctrl_ext | BP10GB_MDIO_DIR |
698 BP10GB_MCLK_CLR) & ~(BP10GB_MCLK_DIR |
703 } else if (!pbpctl_dev->bp_10g)
704 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
705 BPCTLI_CTRL_EXT_MCLK_DIR)
708 (BPCTLI_CTRL_EXT_MDIO_DIR
710 BPCTLI_CTRL_EXT_MCLK_DATA)));
713 BP10G_WRITE_REG(pbpctl_dev, EODSDP, ((ctrl_ext | BP10G_MDIO_DATA_OUT) & ~BP10G_MCLK_DATA_OUT)); /* ? */
714 /* printk("0x28=0x%x\n",BP10G_READ_REG(pbpctl_dev,EODSDP);); */
718 usec_delay(PULSE_TIME);
719 if (pbpctl_dev->bp_10g9) {
720 /*BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext|BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9)); */
722 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
723 (ctrl | BP10G_MCLK_DATA_OUT9 |
724 BP10G_MCLK_DIR_OUT9));
726 } else if (pbpctl_dev->bp_fiber5) {
727 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
728 BPCTLI_CTRL_EXT_MCLK_DIR5
730 BPCTLI_CTRL_EXT_MCLK_DATA5)
733 (BPCTLI_CTRL_EXT_MDIO_DIR5)));
735 } else if (pbpctl_dev->bp_i80) {
736 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
738 ~(BPCTLI_CTRL_EXT_MDIO_DIR80)));
739 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
740 (ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80 |
741 BPCTLI_CTRL_EXT_MCLK_DATA80));
743 } else if (pbpctl_dev->bp_540) {
744 BP10G_WRITE_REG(pbpctl_dev, ESDP,
745 ((ctrl | BP540_MCLK_DIR |
749 } else if (pbpctl_dev->bp_10gb) {
750 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
751 (ctrl_ext | BP10GB_MDIO_DIR |
752 BP10GB_MCLK_SET) & ~(BP10GB_MCLK_DIR |
757 } else if (!pbpctl_dev->bp_10g)
758 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
759 BPCTLI_CTRL_EXT_MCLK_DIR
761 BPCTLI_CTRL_EXT_MCLK_DATA)
764 (BPCTLI_CTRL_EXT_MDIO_DIR)));
767 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
768 (ctrl_ext | BP10G_MCLK_DATA_OUT |
769 BP10G_MDIO_DATA_OUT));
772 if (pbpctl_dev->bp_10g9) {
773 ctrl_ext = BP10G_READ_REG(pbpctl_dev, I2CCTL);
775 } else if ((pbpctl_dev->bp_fiber5) || (pbpctl_dev->bp_i80)) {
776 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL);
777 } else if (pbpctl_dev->bp_540) {
778 ctrl_ext = BP10G_READ_REG(pbpctl_dev, ESDP);
779 } else if (pbpctl_dev->bp_10gb)
780 ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
782 else if (!pbpctl_dev->bp_10g)
783 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
785 ctrl_ext = BP10G_READ_REG(pbpctl_dev, EODSDP);
787 usec_delay(PULSE_TIME);
788 if (pbpctl_dev->bp_10g9) {
789 if (ctrl_ext & BP10G_MDIO_DATA_IN9)
792 } else if (pbpctl_dev->bp_fiber5) {
793 if (ctrl_ext & BPCTLI_CTRL_EXT_MDIO_DATA5)
795 } else if (pbpctl_dev->bp_i80) {
796 if (ctrl_ext & BPCTLI_CTRL_EXT_MDIO_DATA80)
798 } else if (pbpctl_dev->bp_540) {
799 if (ctrl_ext & BP540_MDIO_DATA)
801 } else if (pbpctl_dev->bp_10gb) {
802 if (ctrl_ext & BP10GB_MDIO_DATA)
805 } else if (!pbpctl_dev->bp_10g) {
807 if (ctrl_ext & BPCTLI_CTRL_EXT_MDIO_DATA)
811 if (ctrl_ext & BP10G_MDIO_DATA_IN)
820 static void write_reg(bpctl_dev_t *pbpctl_dev, unsigned char value,
823 uint32_t ctrl_ext = 0, ctrl = 0;
824 bpctl_dev_t *pbpctl_dev_c = NULL;
826 if (pbpctl_dev->bp_10g9) {
827 if (!(pbpctl_dev_c = get_status_port_fn(pbpctl_dev)))
830 if ((pbpctl_dev->wdt_status == WDT_STATUS_EN) &&
831 (pbpctl_dev->bp_ext_ver < PXG4BPFI_VER))
832 wdt_time_left(pbpctl_dev);
835 spin_lock_irqsave(&pbpctl_dev->bypass_wr_lock, flags);
837 atomic_set(&pbpctl_dev->wdt_busy, 1);
839 if (pbpctl_dev->bp_10g9) {
841 ctrl_ext = BP10G_READ_REG(pbpctl_dev, I2CCTL);
842 ctrl = BP10G_READ_REG(pbpctl_dev_c, ESDP);
844 /* BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext&~(BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9))); */
845 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
846 (ctrl_ext & ~BP10G_MDIO_DATA_OUT9));
847 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
848 ((ctrl | BP10G_MCLK_DIR_OUT9) &
849 ~(BP10G_MCLK_DATA_OUT9)));
851 } else if (pbpctl_dev->bp_fiber5) {
852 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL);
853 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
854 BPCTLI_CTRL_EXT_MCLK_DIR5
856 BPCTLI_CTRL_EXT_MDIO_DIR5)
859 (BPCTLI_CTRL_EXT_MDIO_DATA5
861 BPCTLI_CTRL_EXT_MCLK_DATA5)));
862 } else if (pbpctl_dev->bp_i80) {
863 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL);
864 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
865 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
866 BPCTLI_CTRL_EXT_MDIO_DIR80)
868 ~BPCTLI_CTRL_EXT_MDIO_DATA80));
869 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
870 ((ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80) &
871 ~BPCTLI_CTRL_EXT_MCLK_DATA80));
873 } else if (pbpctl_dev->bp_540) {
874 ctrl = ctrl_ext = BP10G_READ_REG(pbpctl_dev, ESDP);
875 BP10G_WRITE_REG(pbpctl_dev, ESDP, ((ctrl |
881 } else if (pbpctl_dev->bp_10gb) {
882 ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
884 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
885 (ctrl_ext | BP10GB_MDIO_CLR | BP10GB_MCLK_CLR)
886 & ~(BP10GB_MCLK_DIR | BP10GB_MDIO_DIR |
887 BP10GB_MDIO_SET | BP10GB_MCLK_SET));
889 } else if (!pbpctl_dev->bp_10g) {
891 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
892 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
893 BPCTLI_CTRL_EXT_MCLK_DIR
895 BPCTLI_CTRL_EXT_MDIO_DIR)
898 (BPCTLI_CTRL_EXT_MDIO_DATA
900 BPCTLI_CTRL_EXT_MCLK_DATA)));
902 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
903 ctrl_ext = BP10G_READ_REG(pbpctl_dev, EODSDP);
904 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
906 ~(BP10G_MCLK_DATA_OUT | BP10G_MDIO_DATA_OUT)));
908 usec_delay(CMND_INTERVAL);
911 write_pulse(pbpctl_dev, ctrl_ext, SYNC_CMD_VAL, SYNC_CMD_LEN);
913 write_pulse(pbpctl_dev, ctrl_ext, WR_CMD_VAL, WR_CMD_LEN);
914 write_pulse(pbpctl_dev, ctrl_ext, addr, ADDR_CMD_LEN);
917 write_pulse(pbpctl_dev, ctrl_ext, value, WR_DATA_LEN);
918 if (pbpctl_dev->bp_10g9) {
919 /*BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext&~(BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9))); */
921 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
922 (ctrl_ext & ~BP10G_MDIO_DATA_OUT9));
923 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
924 ((ctrl | BP10G_MCLK_DIR_OUT9) &
925 ~(BP10G_MCLK_DATA_OUT9)));
927 } else if (pbpctl_dev->bp_fiber5) {
928 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
929 BPCTLI_CTRL_EXT_MCLK_DIR5
931 BPCTLI_CTRL_EXT_MDIO_DIR5)
934 (BPCTLI_CTRL_EXT_MDIO_DATA5
936 BPCTLI_CTRL_EXT_MCLK_DATA5)));
937 } else if (pbpctl_dev->bp_i80) {
938 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
939 BPCTLI_CTRL_EXT_MDIO_DIR80)
941 ~BPCTLI_CTRL_EXT_MDIO_DATA80));
942 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
943 ((ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80) &
944 ~BPCTLI_CTRL_EXT_MCLK_DATA80));
945 } else if (pbpctl_dev->bp_540) {
946 BP10G_WRITE_REG(pbpctl_dev, ESDP, ((ctrl |
951 } else if (pbpctl_dev->bp_10gb) {
952 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
953 (ctrl_ext | BP10GB_MDIO_CLR | BP10GB_MCLK_CLR)
954 & ~(BP10GB_MCLK_DIR | BP10GB_MDIO_DIR |
955 BP10GB_MDIO_SET | BP10GB_MCLK_SET));
957 } else if (!pbpctl_dev->bp_10g)
959 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
960 BPCTLI_CTRL_EXT_MCLK_DIR
962 BPCTLI_CTRL_EXT_MDIO_DIR)
965 (BPCTLI_CTRL_EXT_MDIO_DATA
967 BPCTLI_CTRL_EXT_MCLK_DATA)));
969 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
971 ~(BP10G_MCLK_DATA_OUT | BP10G_MDIO_DATA_OUT)));
975 usec_delay(CMND_INTERVAL * 4);
977 if ((pbpctl_dev->wdt_status == WDT_STATUS_EN) &&
978 (pbpctl_dev->bp_ext_ver < PXG4BPFI_VER) && (addr == CMND_REG_ADDR))
979 pbpctl_dev->bypass_wdt_on_time = jiffies;
981 spin_unlock_irqrestore(&pbpctl_dev->bypass_wr_lock, flags);
983 atomic_set(&pbpctl_dev->wdt_busy, 0);
988 static void write_data(bpctl_dev_t *pbpctl_dev, unsigned char value)
990 write_reg(pbpctl_dev, value, CMND_REG_ADDR);
993 static int read_reg(bpctl_dev_t *pbpctl_dev, unsigned char addr)
995 uint32_t ctrl_ext = 0, ctrl = 0, ctrl_value = 0;
996 bpctl_dev_t *pbpctl_dev_c = NULL;
1000 spin_lock_irqsave(&pbpctl_dev->bypass_wr_lock, flags);
1002 atomic_set(&pbpctl_dev->wdt_busy, 1);
1004 if (pbpctl_dev->bp_10g9) {
1005 if (!(pbpctl_dev_c = get_status_port_fn(pbpctl_dev)))
1009 if (pbpctl_dev->bp_10g9) {
1010 ctrl_ext = BP10G_READ_REG(pbpctl_dev, I2CCTL);
1011 ctrl = BP10G_READ_REG(pbpctl_dev_c, ESDP);
1013 /* BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext&~(BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9))); */
1015 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
1016 (ctrl_ext & ~BP10G_MDIO_DATA_OUT9));
1017 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
1018 ((ctrl | BP10G_MCLK_DIR_OUT9) &
1019 ~(BP10G_MCLK_DATA_OUT9)));
1021 } else if (pbpctl_dev->bp_fiber5) {
1022 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL);
1024 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1025 BPCTLI_CTRL_EXT_MCLK_DIR5
1027 BPCTLI_CTRL_EXT_MDIO_DIR5)
1030 (BPCTLI_CTRL_EXT_MDIO_DATA5
1032 BPCTLI_CTRL_EXT_MCLK_DATA5)));
1033 } else if (pbpctl_dev->bp_i80) {
1034 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL);
1035 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1037 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1038 BPCTLI_CTRL_EXT_MDIO_DIR80)
1040 ~BPCTLI_CTRL_EXT_MDIO_DATA80));
1041 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
1042 ((ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80) &
1043 ~BPCTLI_CTRL_EXT_MCLK_DATA80));
1044 } else if (pbpctl_dev->bp_540) {
1045 ctrl_ext = BP10G_READ_REG(pbpctl_dev, ESDP);
1046 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
1048 BP10G_WRITE_REG(pbpctl_dev, ESDP, ((ctrl | BP540_MCLK_DIR |
1052 } else if (pbpctl_dev->bp_10gb) {
1053 ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
1055 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
1056 (ctrl_ext | BP10GB_MDIO_CLR | BP10GB_MCLK_CLR)
1057 & ~(BP10GB_MCLK_DIR | BP10GB_MDIO_DIR |
1058 BP10GB_MDIO_SET | BP10GB_MCLK_SET));
1061 /*BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO, (ctrl_ext | BP10GB_MCLK_DIR | BP10GB_MDIO_DIR|
1062 BP10GB_MCLK_CLR|BP10GB_MDIO_CLR));
1063 ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
1064 printk("1reg=%x\n", ctrl_ext); */
1066 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO, ((ctrl_ext |
1069 & ~(BP10GB_MCLK_CLR | BP10GB_MDIO_SET |
1070 BP10GB_MCLK_DIR | BP10GB_MDIO_DIR));
1072 /* bnx2x_set_spio(pbpctl_dev, 5, MISC_REGISTERS_SPIO_OUTPUT_LOW);
1073 bnx2x_set_spio(pbpctl_dev, 4, MISC_REGISTERS_SPIO_OUTPUT_LOW);
1074 bnx2x_set_spio(pbpctl_dev, 4, MISC_REGISTERS_SPIO_INPUT_HI_Z); */
1076 ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
1078 printk("2reg=%x\n", ctrl_ext);
1081 spin_unlock_irqrestore(&pbpctl_dev->bypass_wr_lock, flags);
1083 atomic_set(&pbpctl_dev->wdt_busy, 0);
1090 } else if (!pbpctl_dev->bp_10g) {
1092 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1094 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1095 BPCTLI_CTRL_EXT_MCLK_DIR
1097 BPCTLI_CTRL_EXT_MDIO_DIR)
1100 (BPCTLI_CTRL_EXT_MDIO_DATA
1102 BPCTLI_CTRL_EXT_MCLK_DATA)));
1105 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
1106 ctrl_ext = BP10G_READ_REG(pbpctl_dev, EODSDP);
1107 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
1109 ~(BP10G_MCLK_DATA_OUT | BP10G_MDIO_DATA_OUT)));
1113 usec_delay(CMND_INTERVAL);
1116 write_pulse(pbpctl_dev, ctrl_ext, SYNC_CMD_VAL, SYNC_CMD_LEN);
1118 write_pulse(pbpctl_dev, ctrl_ext, RD_CMD_VAL, RD_CMD_LEN);
1120 write_pulse(pbpctl_dev, ctrl_ext, addr, ADDR_CMD_LEN);
1123 if (pbpctl_dev->bp_10g9) {
1125 /*BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext|BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9)); */
1126 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
1127 (ctrl_ext | BP10G_MDIO_DATA_OUT9));
1128 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
1129 (ctrl | BP10G_MCLK_DATA_OUT9 |
1130 BP10G_MCLK_DIR_OUT9));
1132 } else if (pbpctl_dev->bp_fiber5) {
1133 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1134 BPCTLI_CTRL_EXT_MCLK_DIR5
1136 BPCTLI_CTRL_EXT_MCLK_DATA5)
1139 (BPCTLI_CTRL_EXT_MDIO_DIR5
1141 BPCTLI_CTRL_EXT_MDIO_DATA5)));
1143 } else if (pbpctl_dev->bp_i80) {
1144 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
1146 ~(BPCTLI_CTRL_EXT_MDIO_DATA80 |
1147 BPCTLI_CTRL_EXT_MDIO_DIR80)));
1148 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
1149 (ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80 |
1150 BPCTLI_CTRL_EXT_MCLK_DATA80));
1152 } else if (pbpctl_dev->bp_540) {
1153 BP10G_WRITE_REG(pbpctl_dev, ESDP,
1154 (((ctrl | BP540_MDIO_DIR | BP540_MCLK_DIR |
1155 BP540_MCLK_DATA) & ~BP540_MDIO_DATA)));
1157 } else if (pbpctl_dev->bp_10gb) {
1159 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
1160 (ctrl_ext | BP10GB_MDIO_DIR | BP10GB_MCLK_SET)
1161 & ~(BP10GB_MCLK_DIR | BP10GB_MDIO_SET |
1162 BP10GB_MDIO_CLR | BP10GB_MCLK_CLR));
1164 } else if (!pbpctl_dev->bp_10g)
1165 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1166 BPCTLI_CTRL_EXT_MCLK_DIR
1168 BPCTLI_CTRL_EXT_MCLK_DATA)
1171 (BPCTLI_CTRL_EXT_MDIO_DIR
1173 BPCTLI_CTRL_EXT_MDIO_DATA)));
1176 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
1177 (ctrl_ext | BP10G_MCLK_DATA_OUT |
1178 BP10G_MDIO_DATA_OUT));
1182 usec_delay(PULSE_TIME);
1184 ctrl_value = read_pulse(pbpctl_dev, ctrl_ext, RD_DATA_LEN);
1186 if (pbpctl_dev->bp_10g9) {
1187 ctrl_ext = BP10G_READ_REG(pbpctl_dev, I2CCTL);
1188 ctrl = BP10G_READ_REG(pbpctl_dev_c, ESDP);
1190 /* BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext&~(BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9))); */
1192 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
1193 (ctrl_ext & ~BP10G_MDIO_DATA_OUT9));
1194 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
1195 ((ctrl | BP10G_MCLK_DIR_OUT9) &
1196 ~(BP10G_MCLK_DATA_OUT9)));
1198 } else if (pbpctl_dev->bp_fiber5) {
1199 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1200 BPCTLI_CTRL_EXT_MCLK_DIR5
1202 BPCTLI_CTRL_EXT_MDIO_DIR5)
1205 (BPCTLI_CTRL_EXT_MDIO_DATA5
1207 BPCTLI_CTRL_EXT_MCLK_DATA5)));
1208 } else if (pbpctl_dev->bp_i80) {
1209 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1210 BPCTLI_CTRL_EXT_MDIO_DIR80)
1212 ~BPCTLI_CTRL_EXT_MDIO_DATA80));
1213 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
1214 ((ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80) &
1215 ~BPCTLI_CTRL_EXT_MCLK_DATA80));
1217 } else if (pbpctl_dev->bp_540) {
1218 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
1219 BP10G_WRITE_REG(pbpctl_dev, ESDP, ((ctrl | BP540_MCLK_DIR |
1224 } else if (pbpctl_dev->bp_10gb) {
1225 ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
1226 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
1227 (ctrl_ext | BP10GB_MDIO_CLR | BP10GB_MCLK_CLR)
1228 & ~(BP10GB_MCLK_DIR | BP10GB_MDIO_DIR |
1229 BP10GB_MDIO_SET | BP10GB_MCLK_SET));
1231 } else if (!pbpctl_dev->bp_10g) {
1232 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1233 BPCTLI_CTRL_EXT_MCLK_DIR
1235 BPCTLI_CTRL_EXT_MDIO_DIR)
1238 (BPCTLI_CTRL_EXT_MDIO_DATA
1240 BPCTLI_CTRL_EXT_MCLK_DATA)));
1243 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
1244 ctrl_ext = BP10G_READ_REG(pbpctl_dev, EODSDP);
1245 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
1247 ~(BP10G_MCLK_DATA_OUT | BP10G_MDIO_DATA_OUT)));
1251 usec_delay(CMND_INTERVAL * 4);
1253 spin_unlock_irqrestore(&pbpctl_dev->bypass_wr_lock, flags);
1255 atomic_set(&pbpctl_dev->wdt_busy, 0);
1261 static int wdt_pulse(bpctl_dev_t *pbpctl_dev)
1263 uint32_t ctrl_ext = 0, ctrl = 0;
1264 bpctl_dev_t *pbpctl_dev_c = NULL;
1267 unsigned long flags;
1269 spin_lock_irqsave(&pbpctl_dev->bypass_wr_lock, flags);
1272 if ((atomic_read(&pbpctl_dev->wdt_busy)) == 1)
1275 if (pbpctl_dev->bp_10g9) {
1276 if (!(pbpctl_dev_c = get_status_port_fn(pbpctl_dev)))
1280 if (pbpctl_dev->bp_10g9) {
1281 ctrl_ext = BP10G_READ_REG(pbpctl_dev, I2CCTL);
1282 ctrl = BP10G_READ_REG(pbpctl_dev_c, ESDP);
1284 /* BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext&~(BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9))); */
1286 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
1287 (ctrl_ext & ~BP10G_MDIO_DATA_OUT9));
1288 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
1289 ((ctrl | BP10G_MCLK_DIR_OUT9) &
1290 ~(BP10G_MCLK_DATA_OUT9)));
1292 } else if (pbpctl_dev->bp_fiber5) {
1293 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL);
1294 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1295 BPCTLI_CTRL_EXT_MCLK_DIR5
1297 BPCTLI_CTRL_EXT_MDIO_DIR5)
1300 (BPCTLI_CTRL_EXT_MDIO_DATA5
1302 BPCTLI_CTRL_EXT_MCLK_DATA5)));
1303 } else if (pbpctl_dev->bp_i80) {
1304 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL);
1305 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1306 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1307 BPCTLI_CTRL_EXT_MDIO_DIR80)
1309 ~BPCTLI_CTRL_EXT_MDIO_DATA80));
1310 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
1311 ((ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80) &
1312 ~BPCTLI_CTRL_EXT_MCLK_DATA80));
1313 } else if (pbpctl_dev->bp_540) {
1314 ctrl_ext = ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
1315 BP10G_WRITE_REG(pbpctl_dev, ESDP, ((ctrl | BP540_MCLK_DIR |
1319 } else if (pbpctl_dev->bp_10gb) {
1320 ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
1321 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
1322 (ctrl_ext | BP10GB_MDIO_CLR | BP10GB_MCLK_CLR)
1323 & ~(BP10GB_MCLK_DIR | BP10GB_MDIO_DIR |
1324 BP10GB_MDIO_SET | BP10GB_MCLK_SET));
1326 } else if (!pbpctl_dev->bp_10g) {
1328 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1329 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1330 BPCTLI_CTRL_EXT_MCLK_DIR
1332 BPCTLI_CTRL_EXT_MDIO_DIR)
1335 (BPCTLI_CTRL_EXT_MDIO_DATA
1337 BPCTLI_CTRL_EXT_MCLK_DATA)));
1340 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
1341 ctrl_ext = BP10G_READ_REG(pbpctl_dev, EODSDP);
1342 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
1344 ~(BP10G_MCLK_DATA_OUT | BP10G_MDIO_DATA_OUT)));
1347 if (pbpctl_dev->bp_10g9) {
1348 /* BP10G_WRITE_REG(pbpctl_dev, I2CCTL, ((ctrl_ext|BP10G_MCLK_DATA_OUT9)&~BP10G_MDIO_DATA_OUT9)); */
1350 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
1351 (ctrl_ext & ~BP10G_MDIO_DATA_OUT9));
1352 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
1353 (ctrl | BP10G_MCLK_DATA_OUT9 |
1354 BP10G_MCLK_DIR_OUT9));
1356 } else if (pbpctl_dev->bp_fiber5) {
1357 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1358 BPCTLI_CTRL_EXT_MCLK_DIR5
1360 BPCTLI_CTRL_EXT_MDIO_DIR5
1362 BPCTLI_CTRL_EXT_MCLK_DATA5)
1365 (BPCTLI_CTRL_EXT_MDIO_DATA5)));
1366 } else if (pbpctl_dev->bp_i80) {
1367 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1368 BPCTLI_CTRL_EXT_MDIO_DIR80)
1370 ~BPCTLI_CTRL_EXT_MDIO_DATA80));
1371 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
1372 (ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80 |
1373 BPCTLI_CTRL_EXT_MCLK_DATA80));
1375 } else if (pbpctl_dev->bp_540) {
1376 BP10G_WRITE_REG(pbpctl_dev, ESDP, ((ctrl |
1382 } else if (pbpctl_dev->bp_10gb) {
1383 ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
1385 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
1386 (ctrl_ext | BP10GB_MDIO_CLR | BP10GB_MCLK_SET)
1387 & ~(BP10GB_MCLK_DIR | BP10GB_MDIO_DIR |
1388 BP10GB_MDIO_SET | BP10GB_MCLK_CLR));
1390 } else if (!pbpctl_dev->bp_10g)
1391 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1392 BPCTLI_CTRL_EXT_MCLK_DIR
1394 BPCTLI_CTRL_EXT_MDIO_DIR
1396 BPCTLI_CTRL_EXT_MCLK_DATA)
1399 (BPCTLI_CTRL_EXT_MDIO_DATA)));
1402 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
1403 ((ctrl_ext | BP10G_MCLK_DATA_OUT) &
1404 ~BP10G_MDIO_DATA_OUT));
1408 usec_delay(WDT_INTERVAL);
1409 if (pbpctl_dev->bp_10g9) {
1410 /* BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext&~(BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9))); */
1412 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
1413 (ctrl_ext & ~BP10G_MDIO_DATA_OUT9));
1414 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
1415 ((ctrl | BP10G_MCLK_DIR_OUT9) &
1416 ~(BP10G_MCLK_DATA_OUT9)));
1418 } else if (pbpctl_dev->bp_fiber5) {
1419 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1420 BPCTLI_CTRL_EXT_MCLK_DIR5
1422 BPCTLI_CTRL_EXT_MDIO_DIR5)
1425 (BPCTLI_CTRL_EXT_MCLK_DATA5
1427 BPCTLI_CTRL_EXT_MDIO_DATA5)));
1428 } else if (pbpctl_dev->bp_i80) {
1429 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1430 BPCTLI_CTRL_EXT_MDIO_DIR80)
1432 ~BPCTLI_CTRL_EXT_MDIO_DATA80));
1433 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
1434 ((ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80) &
1435 ~BPCTLI_CTRL_EXT_MCLK_DATA80));
1437 } else if (pbpctl_dev->bp_540) {
1438 BP10G_WRITE_REG(pbpctl_dev, ESDP, ((ctrl | BP540_MCLK_DIR |
1443 } else if (pbpctl_dev->bp_10gb) {
1444 ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
1445 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
1446 (ctrl_ext | BP10GB_MDIO_CLR | BP10GB_MCLK_CLR)
1447 & ~(BP10GB_MCLK_DIR | BP10GB_MDIO_DIR |
1448 BP10GB_MDIO_SET | BP10GB_MCLK_SET));
1450 } else if (!pbpctl_dev->bp_10g)
1451 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1452 BPCTLI_CTRL_EXT_MCLK_DIR
1454 BPCTLI_CTRL_EXT_MDIO_DIR)
1457 (BPCTLI_CTRL_EXT_MCLK_DATA
1459 BPCTLI_CTRL_EXT_MDIO_DATA)));
1462 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
1464 ~(BP10G_MCLK_DATA_OUT | BP10G_MDIO_DATA_OUT)));
1466 if ((pbpctl_dev->wdt_status == WDT_STATUS_EN) /*&&
1467 (pbpctl_dev->bp_ext_ver<PXG4BPFI_VER) */ )
1468 pbpctl_dev->bypass_wdt_on_time = jiffies;
1470 spin_unlock_irqrestore(&pbpctl_dev->bypass_wr_lock, flags);
1472 usec_delay(CMND_INTERVAL * 4);
1476 static void data_pulse(bpctl_dev_t *pbpctl_dev, unsigned char value)
1479 uint32_t ctrl_ext = 0;
1481 unsigned long flags;
1483 wdt_time_left(pbpctl_dev);
1485 spin_lock_irqsave(&pbpctl_dev->bypass_wr_lock, flags);
1487 atomic_set(&pbpctl_dev->wdt_busy, 1);
1490 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1491 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1492 BPCTLI_CTRL_EXT_SDP6_DIR |
1493 BPCTLI_CTRL_EXT_SDP7_DIR) &
1494 ~(BPCTLI_CTRL_EXT_SDP6_DATA |
1495 BPCTLI_CTRL_EXT_SDP7_DATA)));
1497 usec_delay(INIT_CMND_INTERVAL);
1498 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1499 BPCTLI_CTRL_EXT_SDP6_DIR |
1500 BPCTLI_CTRL_EXT_SDP7_DIR |
1501 BPCTLI_CTRL_EXT_SDP6_DATA) &
1503 (BPCTLI_CTRL_EXT_SDP7_DATA)));
1504 usec_delay(INIT_CMND_INTERVAL);
1507 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ctrl_ext |
1508 BPCTLI_CTRL_EXT_SDP6_DIR |
1509 BPCTLI_CTRL_EXT_SDP7_DIR |
1510 BPCTLI_CTRL_EXT_SDP6_DATA |
1511 BPCTLI_CTRL_EXT_SDP7_DATA);
1512 usec_delay(PULSE_INTERVAL);
1513 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1514 BPCTLI_CTRL_EXT_SDP6_DIR
1516 BPCTLI_CTRL_EXT_SDP7_DIR
1518 BPCTLI_CTRL_EXT_SDP6_DATA)
1520 ~BPCTLI_CTRL_EXT_SDP7_DATA));
1521 usec_delay(PULSE_INTERVAL);
1525 usec_delay(INIT_CMND_INTERVAL - PULSE_INTERVAL);
1526 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1527 BPCTLI_CTRL_EXT_SDP6_DIR |
1528 BPCTLI_CTRL_EXT_SDP7_DIR) &
1529 ~(BPCTLI_CTRL_EXT_SDP6_DATA |
1530 BPCTLI_CTRL_EXT_SDP7_DATA)));
1531 usec_delay(WDT_TIME_CNT);
1532 if (pbpctl_dev->wdt_status == WDT_STATUS_EN)
1533 pbpctl_dev->bypass_wdt_on_time = jiffies;
1535 spin_unlock_irqrestore(&pbpctl_dev->bypass_wr_lock, flags);
1537 atomic_set(&pbpctl_dev->wdt_busy, 0);
1542 static int send_wdt_pulse(bpctl_dev_t *pbpctl_dev)
1544 uint32_t ctrl_ext = 0;
1547 unsigned long flags;
1549 spin_lock_irqsave(&pbpctl_dev->bypass_wr_lock, flags);
1552 if ((atomic_read(&pbpctl_dev->wdt_busy)) == 1)
1555 wdt_time_left(pbpctl_dev);
1556 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1558 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ctrl_ext | /* 1 */
1559 BPCTLI_CTRL_EXT_SDP7_DIR |
1560 BPCTLI_CTRL_EXT_SDP7_DATA);
1561 usec_delay(PULSE_INTERVAL);
1562 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext | /* 0 */
1563 BPCTLI_CTRL_EXT_SDP7_DIR) &
1564 ~BPCTLI_CTRL_EXT_SDP7_DATA));
1566 usec_delay(PULSE_INTERVAL);
1567 if (pbpctl_dev->wdt_status == WDT_STATUS_EN)
1568 pbpctl_dev->bypass_wdt_on_time = jiffies;
1570 spin_unlock_irqrestore(&pbpctl_dev->bypass_wr_lock, flags);
1576 void send_bypass_clear_pulse(bpctl_dev_t *pbpctl_dev, unsigned int value)
1578 uint32_t ctrl_ext = 0;
1580 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1581 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext | /* 0 */
1582 BPCTLI_CTRL_EXT_SDP6_DIR) &
1583 ~BPCTLI_CTRL_EXT_SDP6_DATA));
1585 usec_delay(PULSE_INTERVAL);
1587 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ctrl_ext | /* 1 */
1588 BPCTLI_CTRL_EXT_SDP6_DIR |
1589 BPCTLI_CTRL_EXT_SDP6_DATA);
1590 usec_delay(PULSE_INTERVAL);
1593 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext | /* 0 */
1594 BPCTLI_CTRL_EXT_SDP6_DIR) &
1595 ~BPCTLI_CTRL_EXT_SDP6_DATA));
1596 usec_delay(PULSE_INTERVAL);
1602 int pulse_set_fn(bpctl_dev_t *pbpctl_dev, unsigned int counter)
1604 uint32_t ctrl_ext = 0;
1609 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1610 write_pulse_1(pbpctl_dev, ctrl_ext, counter, counter);
1612 pbpctl_dev->bypass_wdt_status = 0;
1613 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
1614 write_pulse_1(pbpctl_dev, ctrl_ext, counter, counter);
1616 wdt_time_left(pbpctl_dev);
1617 if (pbpctl_dev->wdt_status == WDT_STATUS_EN) {
1618 pbpctl_dev->wdt_status = 0;
1619 data_pulse(pbpctl_dev, counter);
1620 pbpctl_dev->wdt_status = WDT_STATUS_EN;
1621 pbpctl_dev->bypass_wdt_on_time = jiffies;
1624 data_pulse(pbpctl_dev, counter);
1630 int zero_set_fn(bpctl_dev_t *pbpctl_dev)
1632 uint32_t ctrl_ext = 0, ctrl_value = 0;
1636 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
1639 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1641 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1642 BPCTLI_CTRL_EXT_MCLK_DIR)
1645 (BPCTLI_CTRL_EXT_MCLK_DATA
1647 BPCTLI_CTRL_EXT_MDIO_DIR
1649 BPCTLI_CTRL_EXT_MDIO_DATA)));
1655 int pulse_get2_fn(bpctl_dev_t *pbpctl_dev)
1657 uint32_t ctrl_ext = 0, ctrl_value = 0;
1661 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
1662 printk("pulse_get_fn\n");
1663 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1664 ctrl_value = read_pulse_2(pbpctl_dev, ctrl_ext);
1665 printk("read:%d\n", ctrl_value);
1670 int pulse_get1_fn(bpctl_dev_t *pbpctl_dev)
1672 uint32_t ctrl_ext = 0, ctrl_value = 0;
1676 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
1678 printk("pulse_get_fn\n");
1680 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1681 ctrl_value = read_pulse_1(pbpctl_dev, ctrl_ext);
1682 printk("read:%d\n", ctrl_value);
1687 int gpio6_set_fn(bpctl_dev_t *pbpctl_dev)
1689 uint32_t ctrl_ext = 0;
1691 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1692 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ctrl_ext |
1693 BPCTLI_CTRL_EXT_SDP6_DIR |
1694 BPCTLI_CTRL_EXT_SDP6_DATA);
1698 int gpio7_set_fn(bpctl_dev_t *pbpctl_dev)
1700 uint32_t ctrl_ext = 0;
1702 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1703 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ctrl_ext |
1704 BPCTLI_CTRL_EXT_SDP7_DIR |
1705 BPCTLI_CTRL_EXT_SDP7_DATA);
1709 int gpio7_clear_fn(bpctl_dev_t *pbpctl_dev)
1711 uint32_t ctrl_ext = 0;
1713 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1714 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1715 BPCTLI_CTRL_EXT_SDP7_DIR) &
1716 ~BPCTLI_CTRL_EXT_SDP7_DATA));
1720 int gpio6_clear_fn(bpctl_dev_t *pbpctl_dev)
1722 uint32_t ctrl_ext = 0;
1724 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1725 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1726 BPCTLI_CTRL_EXT_SDP6_DIR) &
1727 ~BPCTLI_CTRL_EXT_SDP6_DATA));
1730 #endif /*BYPASS_DEBUG */
1732 static bpctl_dev_t *get_status_port_fn(bpctl_dev_t *pbpctl_dev)
1736 if (pbpctl_dev == NULL)
1739 if ((pbpctl_dev->func == 0) || (pbpctl_dev->func == 2)) {
1741 ((bpctl_dev_arr[idx_dev].pdev != NULL)
1742 && (idx_dev < device_num)); idx_dev++) {
1743 if ((bpctl_dev_arr[idx_dev].bus == pbpctl_dev->bus)
1744 && (bpctl_dev_arr[idx_dev].slot == pbpctl_dev->slot)
1745 && ((bpctl_dev_arr[idx_dev].func == 1)
1746 && (pbpctl_dev->func == 0))) {
1748 return &(bpctl_dev_arr[idx_dev]);
1750 if ((bpctl_dev_arr[idx_dev].bus == pbpctl_dev->bus) &&
1751 (bpctl_dev_arr[idx_dev].slot == pbpctl_dev->slot) &&
1752 ((bpctl_dev_arr[idx_dev].func == 3)
1753 && (pbpctl_dev->func == 2))) {
1755 return &(bpctl_dev_arr[idx_dev]);
1762 static bpctl_dev_t *get_master_port_fn(bpctl_dev_t *pbpctl_dev)
1766 if (pbpctl_dev == NULL)
1769 if ((pbpctl_dev->func == 1) || (pbpctl_dev->func == 3)) {
1771 ((bpctl_dev_arr[idx_dev].pdev != NULL)
1772 && (idx_dev < device_num)); idx_dev++) {
1773 if ((bpctl_dev_arr[idx_dev].bus == pbpctl_dev->bus)
1774 && (bpctl_dev_arr[idx_dev].slot == pbpctl_dev->slot)
1775 && ((bpctl_dev_arr[idx_dev].func == 0)
1776 && (pbpctl_dev->func == 1))) {
1778 return &(bpctl_dev_arr[idx_dev]);
1780 if ((bpctl_dev_arr[idx_dev].bus == pbpctl_dev->bus) &&
1781 (bpctl_dev_arr[idx_dev].slot == pbpctl_dev->slot) &&
1782 ((bpctl_dev_arr[idx_dev].func == 2)
1783 && (pbpctl_dev->func == 3))) {
1785 return &(bpctl_dev_arr[idx_dev]);
1792 /**************************************/
1793 /**************INTEL API***************/
1794 /**************************************/
1796 static void write_data_port_int(bpctl_dev_t *pbpctl_dev,
1797 unsigned char ctrl_value)
1801 value = BPCTL_READ_REG(pbpctl_dev, CTRL);
1802 /* Make SDP0 Pin Directonality to Output */
1803 value |= BPCTLI_CTRL_SDP0_DIR;
1804 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, value);
1806 value &= ~BPCTLI_CTRL_SDP0_DATA;
1807 value |= ((ctrl_value & 0x1) << BPCTLI_CTRL_SDP0_SHIFT);
1808 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, value);
1810 value = (BPCTL_READ_REG(pbpctl_dev, CTRL_EXT));
1811 /* Make SDP2 Pin Directonality to Output */
1812 value |= BPCTLI_CTRL_EXT_SDP6_DIR;
1813 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, value);
1815 value &= ~BPCTLI_CTRL_EXT_SDP6_DATA;
1816 value |= (((ctrl_value & 0x2) >> 1) << BPCTLI_CTRL_EXT_SDP6_SHIFT);
1817 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, value);
1821 static int write_data_int(bpctl_dev_t *pbpctl_dev, unsigned char value)
1823 bpctl_dev_t *pbpctl_dev_b = NULL;
1825 if (!(pbpctl_dev_b = get_status_port_fn(pbpctl_dev)))
1827 atomic_set(&pbpctl_dev->wdt_busy, 1);
1828 write_data_port_int(pbpctl_dev, value & 0x3);
1829 write_data_port_int(pbpctl_dev_b, ((value & 0xc) >> 2));
1830 atomic_set(&pbpctl_dev->wdt_busy, 0);
1835 static int wdt_pulse_int(bpctl_dev_t *pbpctl_dev)
1838 if ((atomic_read(&pbpctl_dev->wdt_busy)) == 1)
1841 if ((write_data_int(pbpctl_dev, RESET_WDT_INT)) < 0)
1843 msec_delay_bp(CMND_INTERVAL_INT);
1844 if ((write_data_int(pbpctl_dev, CMND_OFF_INT)) < 0)
1846 msec_delay_bp(CMND_INTERVAL_INT);
1848 if (pbpctl_dev->wdt_status == WDT_STATUS_EN)
1849 pbpctl_dev->bypass_wdt_on_time = jiffies;
1854 /*************************************/
1855 /************* COMMANDS **************/
1856 /*************************************/
1858 /* CMND_ON 0x4 (100)*/
1859 int cmnd_on(bpctl_dev_t *pbpctl_dev)
1861 int ret = BP_NOT_CAP;
1863 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
1864 if (INTEL_IF_SERIES(pbpctl_dev->subdevice))
1866 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER)
1867 write_data(pbpctl_dev, CMND_ON);
1869 data_pulse(pbpctl_dev, CMND_ON);
1875 /* CMND_OFF 0x2 (10)*/
1876 int cmnd_off(bpctl_dev_t *pbpctl_dev)
1878 int ret = BP_NOT_CAP;
1880 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
1881 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
1882 write_data_int(pbpctl_dev, CMND_OFF_INT);
1883 msec_delay_bp(CMND_INTERVAL_INT);
1884 } else if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER)
1885 write_data(pbpctl_dev, CMND_OFF);
1887 data_pulse(pbpctl_dev, CMND_OFF);
1893 /* BYPASS_ON (0xa)*/
1894 int bypass_on(bpctl_dev_t *pbpctl_dev)
1896 int ret = BP_NOT_CAP;
1898 if (pbpctl_dev->bp_caps & BP_CAP) {
1899 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
1900 write_data_int(pbpctl_dev, BYPASS_ON_INT);
1901 msec_delay_bp(BYPASS_DELAY_INT);
1902 pbpctl_dev->bp_status_un = 0;
1903 } else if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
1904 write_data(pbpctl_dev, BYPASS_ON);
1905 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER)
1906 msec_delay_bp(LATCH_DELAY);
1908 data_pulse(pbpctl_dev, BYPASS_ON);
1914 /* BYPASS_OFF (0x8 111)*/
1915 int bypass_off(bpctl_dev_t *pbpctl_dev)
1917 int ret = BP_NOT_CAP;
1919 if (pbpctl_dev->bp_caps & BP_CAP) {
1920 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
1921 write_data_int(pbpctl_dev, DIS_BYPASS_CAP_INT);
1922 msec_delay_bp(BYPASS_DELAY_INT);
1923 write_data_int(pbpctl_dev, PWROFF_BYPASS_ON_INT);
1924 msec_delay_bp(BYPASS_DELAY_INT);
1925 pbpctl_dev->bp_status_un = 0;
1926 } else if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
1927 write_data(pbpctl_dev, BYPASS_OFF);
1928 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER)
1929 msec_delay_bp(LATCH_DELAY);
1931 data_pulse(pbpctl_dev, BYPASS_OFF);
1938 int tap_off(bpctl_dev_t *pbpctl_dev)
1940 int ret = BP_NOT_CAP;
1941 if ((pbpctl_dev->bp_caps & TAP_CAP)
1942 && (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER)) {
1943 write_data(pbpctl_dev, TAP_OFF);
1944 msec_delay_bp(LATCH_DELAY);
1951 int tap_on(bpctl_dev_t *pbpctl_dev)
1953 int ret = BP_NOT_CAP;
1954 if ((pbpctl_dev->bp_caps & TAP_CAP)
1955 && (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER)) {
1956 write_data(pbpctl_dev, TAP_ON);
1957 msec_delay_bp(LATCH_DELAY);
1964 int disc_off(bpctl_dev_t *pbpctl_dev)
1967 if ((pbpctl_dev->bp_caps & DISC_CAP) && (pbpctl_dev->bp_ext_ver >= 0x8)) {
1968 write_data(pbpctl_dev, DISC_OFF);
1969 msec_delay_bp(LATCH_DELAY);
1976 int disc_on(bpctl_dev_t *pbpctl_dev)
1979 if ((pbpctl_dev->bp_caps & DISC_CAP) && (pbpctl_dev->bp_ext_ver >= 0x8)) {
1980 write_data(pbpctl_dev, /*DISC_ON */ 0x85);
1981 msec_delay_bp(LATCH_DELAY);
1988 int disc_port_on(bpctl_dev_t *pbpctl_dev)
1991 bpctl_dev_t *pbpctl_dev_m;
1993 if ((is_bypass_fn(pbpctl_dev)) == 1)
1994 pbpctl_dev_m = pbpctl_dev;
1996 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
1997 if (pbpctl_dev_m == NULL)
2000 if (pbpctl_dev_m->bp_caps_ex & DISC_PORT_CAP_EX) {
2001 if (is_bypass_fn(pbpctl_dev) == 1) {
2003 write_data(pbpctl_dev_m, TX_DISA);
2006 write_data(pbpctl_dev_m, TX_DISB);
2009 msec_delay_bp(LATCH_DELAY);
2016 int disc_port_off(bpctl_dev_t *pbpctl_dev)
2019 bpctl_dev_t *pbpctl_dev_m;
2021 if ((is_bypass_fn(pbpctl_dev)) == 1)
2022 pbpctl_dev_m = pbpctl_dev;
2024 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
2025 if (pbpctl_dev_m == NULL)
2028 if (pbpctl_dev_m->bp_caps_ex & DISC_PORT_CAP_EX) {
2029 if (is_bypass_fn(pbpctl_dev) == 1)
2030 write_data(pbpctl_dev_m, TX_ENA);
2032 write_data(pbpctl_dev_m, TX_ENB);
2034 msec_delay_bp(LATCH_DELAY);
2040 /*TWO_PORT_LINK_HW_EN (0xe)*/
2041 int tpl_hw_on(bpctl_dev_t *pbpctl_dev)
2043 int ret = 0, ctrl = 0;
2044 bpctl_dev_t *pbpctl_dev_b = NULL;
2046 if (!(pbpctl_dev_b = get_status_port_fn(pbpctl_dev)))
2049 if (pbpctl_dev->bp_caps_ex & TPL2_CAP_EX) {
2050 cmnd_on(pbpctl_dev);
2051 write_data(pbpctl_dev, TPL2_ON);
2052 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2053 cmnd_off(pbpctl_dev);
2057 if (TPL_IF_SERIES(pbpctl_dev->subdevice)) {
2058 ctrl = BPCTL_READ_REG(pbpctl_dev_b, CTRL);
2059 BPCTL_BP_WRITE_REG(pbpctl_dev_b, CTRL,
2060 ((ctrl | BPCTLI_CTRL_SWDPIO0) &
2061 ~BPCTLI_CTRL_SWDPIN0));
2067 /*TWO_PORT_LINK_HW_DIS (0xc)*/
2068 int tpl_hw_off(bpctl_dev_t *pbpctl_dev)
2070 int ret = 0, ctrl = 0;
2071 bpctl_dev_t *pbpctl_dev_b = NULL;
2073 if (!(pbpctl_dev_b = get_status_port_fn(pbpctl_dev)))
2075 if (pbpctl_dev->bp_caps_ex & TPL2_CAP_EX) {
2076 cmnd_on(pbpctl_dev);
2077 write_data(pbpctl_dev, TPL2_OFF);
2078 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2079 cmnd_off(pbpctl_dev);
2082 if (TPL_IF_SERIES(pbpctl_dev->subdevice)) {
2083 ctrl = BPCTL_READ_REG(pbpctl_dev_b, CTRL);
2084 BPCTL_BP_WRITE_REG(pbpctl_dev_b, CTRL,
2085 (ctrl | BPCTLI_CTRL_SWDPIO0 |
2086 BPCTLI_CTRL_SWDPIN0));
2092 /* WDT_OFF (0x6 110)*/
2093 int wdt_off(bpctl_dev_t *pbpctl_dev)
2095 int ret = BP_NOT_CAP;
2097 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
2098 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
2099 bypass_off(pbpctl_dev);
2100 } else if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER)
2101 write_data(pbpctl_dev, WDT_OFF);
2103 data_pulse(pbpctl_dev, WDT_OFF);
2104 pbpctl_dev->wdt_status = WDT_STATUS_DIS;
2114 wdt_val_array[] = { 1000, 1500, 2000, 3000, 4000, 8000, 16000, 32000, 0 };
2116 int wdt_on(bpctl_dev_t *pbpctl_dev, unsigned int timeout)
2119 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
2120 unsigned int pulse = 0, temp_value = 0, temp_cnt = 0;
2121 pbpctl_dev->wdt_status = 0;
2123 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
2124 for (; wdt_val_array[temp_cnt]; temp_cnt++)
2125 if (timeout <= wdt_val_array[temp_cnt])
2128 if (!wdt_val_array[temp_cnt])
2131 timeout = wdt_val_array[temp_cnt];
2134 write_data_int(pbpctl_dev, DIS_BYPASS_CAP_INT);
2135 msec_delay_bp(BYPASS_DELAY_INT);
2136 pbpctl_dev->bp_status_un = 0;
2137 write_data_int(pbpctl_dev, temp_cnt);
2138 pbpctl_dev->bypass_wdt_on_time = jiffies;
2139 msec_delay_bp(CMND_INTERVAL_INT);
2140 pbpctl_dev->bypass_timer_interval = timeout;
2144 TIMEOUT_UNIT ? TIMEOUT_UNIT : (timeout >
2148 temp_value = timeout / 100;
2149 while ((temp_value >>= 1))
2151 if (timeout > ((1 << temp_cnt) * 100))
2153 pbpctl_dev->bypass_wdt_on_time = jiffies;
2154 pulse = (WDT_ON | temp_cnt);
2155 if (pbpctl_dev->bp_ext_ver == OLD_IF_VER)
2156 data_pulse(pbpctl_dev, pulse);
2158 write_data(pbpctl_dev, pulse);
2159 pbpctl_dev->bypass_timer_interval =
2160 (1 << temp_cnt) * 100;
2162 pbpctl_dev->wdt_status = WDT_STATUS_EN;
2168 void bp75_put_hw_semaphore_generic(bpctl_dev_t *pbpctl_dev)
2172 swsm = BPCTL_READ_REG(pbpctl_dev, SWSM);
2174 swsm &= ~(BPCTLI_SWSM_SMBI | BPCTLI_SWSM_SWESMBI);
2176 BPCTL_WRITE_REG(pbpctl_dev, SWSM, swsm);
2179 s32 bp75_get_hw_semaphore_generic(bpctl_dev_t *pbpctl_dev)
2183 s32 timeout = 8192 + 1;
2186 /* Get the SW semaphore */
2187 while (i < timeout) {
2188 swsm = BPCTL_READ_REG(pbpctl_dev, SWSM);
2189 if (!(swsm & BPCTLI_SWSM_SMBI))
2198 ("bpctl_mod: Driver can't access device - SMBI bit is set.\n");
2203 /* Get the FW semaphore. */
2204 for (i = 0; i < timeout; i++) {
2205 swsm = BPCTL_READ_REG(pbpctl_dev, SWSM);
2206 BPCTL_WRITE_REG(pbpctl_dev, SWSM, swsm | BPCTLI_SWSM_SWESMBI);
2208 /* Semaphore acquired if bit latched */
2209 if (BPCTL_READ_REG(pbpctl_dev, SWSM) & BPCTLI_SWSM_SWESMBI)
2216 /* Release semaphores */
2217 bp75_put_hw_semaphore_generic(pbpctl_dev);
2218 printk("bpctl_mod: Driver can't access the NVM\n");
2227 static void bp75_release_phy(bpctl_dev_t *pbpctl_dev)
2229 u16 mask = BPCTLI_SWFW_PHY0_SM;
2232 if ((pbpctl_dev->func == 1) || (pbpctl_dev->func == 3))
2233 mask = BPCTLI_SWFW_PHY1_SM;
2235 while (bp75_get_hw_semaphore_generic(pbpctl_dev) != 0) ;
2238 swfw_sync = BPCTL_READ_REG(pbpctl_dev, SW_FW_SYNC);
2240 BPCTL_WRITE_REG(pbpctl_dev, SW_FW_SYNC, swfw_sync);
2242 bp75_put_hw_semaphore_generic(pbpctl_dev);
2245 static s32 bp75_acquire_phy(bpctl_dev_t *pbpctl_dev)
2247 u16 mask = BPCTLI_SWFW_PHY0_SM;
2252 s32 i = 0, timeout = 200;
2254 if ((pbpctl_dev->func == 1) || (pbpctl_dev->func == 3))
2255 mask = BPCTLI_SWFW_PHY1_SM;
2258 fwmask = mask << 16;
2260 while (i < timeout) {
2261 if (bp75_get_hw_semaphore_generic(pbpctl_dev)) {
2266 swfw_sync = BPCTL_READ_REG(pbpctl_dev, SW_FW_SYNC);
2267 if (!(swfw_sync & (fwmask | swmask)))
2270 bp75_put_hw_semaphore_generic(pbpctl_dev);
2277 ("bpctl_mod: Driver can't access resource, SW_FW_SYNC timeout.\n");
2282 swfw_sync |= swmask;
2283 BPCTL_WRITE_REG(pbpctl_dev, SW_FW_SYNC, swfw_sync);
2285 bp75_put_hw_semaphore_generic(pbpctl_dev);
2291 s32 bp75_read_phy_reg_mdic(bpctl_dev_t *pbpctl_dev, u32 offset, u16 *data)
2297 mdic = ((offset << BPCTLI_MDIC_REG_SHIFT) |
2298 (phy_addr << BPCTLI_MDIC_PHY_SHIFT) | (BPCTLI_MDIC_OP_READ));
2300 BPCTL_WRITE_REG(pbpctl_dev, MDIC, mdic);
2302 for (i = 0; i < (BPCTLI_GEN_POLL_TIMEOUT * 3); i++) {
2304 mdic = BPCTL_READ_REG(pbpctl_dev, MDIC);
2305 if (mdic & BPCTLI_MDIC_READY)
2308 if (!(mdic & BPCTLI_MDIC_READY)) {
2309 printk("bpctl_mod: MDI Read did not complete\n");
2313 if (mdic & BPCTLI_MDIC_ERROR) {
2314 printk("bpctl_mod: MDI Error\n");
2324 s32 bp75_write_phy_reg_mdic(bpctl_dev_t *pbpctl_dev, u32 offset, u16 data)
2330 mdic = (((u32) data) |
2331 (offset << BPCTLI_MDIC_REG_SHIFT) |
2332 (phy_addr << BPCTLI_MDIC_PHY_SHIFT) | (BPCTLI_MDIC_OP_WRITE));
2334 BPCTL_WRITE_REG(pbpctl_dev, MDIC, mdic);
2336 for (i = 0; i < (BPCTLI_GEN_POLL_TIMEOUT * 3); i++) {
2338 mdic = BPCTL_READ_REG(pbpctl_dev, MDIC);
2339 if (mdic & BPCTLI_MDIC_READY)
2342 if (!(mdic & BPCTLI_MDIC_READY)) {
2343 printk("bpctl_mod: MDI Write did not complete\n");
2347 if (mdic & BPCTLI_MDIC_ERROR) {
2348 printk("bpctl_mod: MDI Error\n");
2357 static s32 bp75_read_phy_reg(bpctl_dev_t *pbpctl_dev, u32 offset, u16 *data)
2361 ret_val = bp75_acquire_phy(pbpctl_dev);
2365 if (offset > BPCTLI_MAX_PHY_MULTI_PAGE_REG) {
2366 ret_val = bp75_write_phy_reg_mdic(pbpctl_dev,
2367 BPCTLI_IGP01E1000_PHY_PAGE_SELECT,
2374 bp75_read_phy_reg_mdic(pbpctl_dev,
2375 BPCTLI_MAX_PHY_REG_ADDRESS & offset, data);
2378 bp75_release_phy(pbpctl_dev);
2383 static s32 bp75_write_phy_reg(bpctl_dev_t *pbpctl_dev, u32 offset, u16 data)
2387 ret_val = bp75_acquire_phy(pbpctl_dev);
2391 if (offset > BPCTLI_MAX_PHY_MULTI_PAGE_REG) {
2392 ret_val = bp75_write_phy_reg_mdic(pbpctl_dev,
2393 BPCTLI_IGP01E1000_PHY_PAGE_SELECT,
2400 bp75_write_phy_reg_mdic(pbpctl_dev,
2401 BPCTLI_MAX_PHY_REG_ADDRESS & offset, data);
2404 bp75_release_phy(pbpctl_dev);
2410 /* SET_TX (non-Bypass command :)) */
2411 static int set_tx(bpctl_dev_t *pbpctl_dev, int tx_state)
2413 int ret = 0, ctrl = 0;
2414 bpctl_dev_t *pbpctl_dev_m;
2415 if ((is_bypass_fn(pbpctl_dev)) == 1)
2416 pbpctl_dev_m = pbpctl_dev;
2418 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
2419 if (pbpctl_dev_m == NULL)
2421 if (pbpctl_dev_m->bp_caps_ex & DISC_PORT_CAP_EX) {
2422 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL);
2424 if (pbpctl_dev->bp_540) {
2425 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
2426 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2427 (ctrl | BP10G_SDP1_DIR |
2431 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
2432 (ctrl | BPCTLI_CTRL_SDP1_DIR
2433 | BPCTLI_CTRL_SWDPIN1));
2436 if (pbpctl_dev->bp_540) {
2437 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
2438 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2439 ((ctrl | BP10G_SDP1_DIR) &
2442 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
2444 BPCTLI_CTRL_SDP1_DIR) &
2445 ~BPCTLI_CTRL_SWDPIN1));
2450 } else if (pbpctl_dev->bp_caps & TX_CTL_CAP) {
2451 if (PEG5_IF_SERIES(pbpctl_dev->subdevice)) {
2456 bp75_read_phy_reg(pbpctl_dev,
2459 if (mii_reg & BPCTLI_MII_CR_POWER_DOWN) {
2465 ~BPCTLI_MII_CR_POWER_DOWN);
2472 bp75_read_phy_reg(pbpctl_dev,
2476 mii_reg |= BPCTLI_MII_CR_POWER_DOWN;
2478 bp75_write_phy_reg(pbpctl_dev,
2485 if (pbpctl_dev->bp_fiber5) {
2486 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
2488 } else if (pbpctl_dev->bp_10gb)
2489 ctrl = BP10GB_READ_REG(pbpctl_dev, MISC_REG_GPIO);
2491 else if (!pbpctl_dev->bp_10g)
2492 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL);
2494 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
2497 if (pbpctl_dev->bp_10g9) {
2498 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2499 (ctrl | BP10G_SDP3_DATA |
2502 } else if (pbpctl_dev->bp_fiber5) {
2503 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
2505 BPCTLI_CTRL_EXT_SDP6_DIR |
2506 BPCTLI_CTRL_EXT_SDP6_DATA));
2508 } else if (pbpctl_dev->bp_10gb) {
2509 if ((pbpctl_dev->func == 1)
2510 || (pbpctl_dev->func == 3))
2511 BP10GB_WRITE_REG(pbpctl_dev,
2514 BP10GB_GPIO0_SET_P1) &
2515 ~(BP10GB_GPIO0_CLR_P1 |
2516 BP10GB_GPIO0_OE_P1));
2518 BP10GB_WRITE_REG(pbpctl_dev,
2521 BP10GB_GPIO0_OE_P0 |
2522 BP10GB_GPIO0_SET_P0));
2524 } else if (pbpctl_dev->bp_i80) {
2525 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
2526 (ctrl | BPCTLI_CTRL_SDP1_DIR
2527 | BPCTLI_CTRL_SWDPIN1));
2529 } else if (pbpctl_dev->bp_540) {
2530 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
2531 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2532 (ctrl | BP10G_SDP1_DIR |
2537 else if (!pbpctl_dev->bp_10g)
2538 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
2539 (ctrl | BPCTLI_CTRL_SWDPIO0 |
2540 BPCTLI_CTRL_SWDPIN0));
2543 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2544 (ctrl | BP10G_SDP0_DATA |
2548 if (pbpctl_dev->bp_10g9) {
2549 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2550 ((ctrl | BP10G_SDP3_DIR) &
2553 } else if (pbpctl_dev->bp_fiber5) {
2554 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
2556 BPCTLI_CTRL_EXT_SDP6_DIR) &
2557 ~BPCTLI_CTRL_EXT_SDP6_DATA));
2559 } else if (pbpctl_dev->bp_10gb) {
2560 if ((bpctl_dev_arr->func == 1)
2561 || (bpctl_dev_arr->func == 3))
2562 BP10GB_WRITE_REG(pbpctl_dev,
2565 BP10GB_GPIO0_CLR_P1) &
2566 ~(BP10GB_GPIO0_SET_P1 |
2567 BP10GB_GPIO0_OE_P1));
2569 BP10GB_WRITE_REG(pbpctl_dev,
2572 BP10GB_GPIO0_OE_P0 |
2573 BP10GB_GPIO0_CLR_P0));
2575 } else if (pbpctl_dev->bp_i80) {
2576 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
2578 BPCTLI_CTRL_SDP1_DIR) &
2579 ~BPCTLI_CTRL_SWDPIN1));
2580 } else if (pbpctl_dev->bp_540) {
2581 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
2582 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2583 ((ctrl | BP10G_SDP1_DIR) &
2587 else if (!pbpctl_dev->bp_10g) {
2588 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
2589 ((ctrl | BPCTLI_CTRL_SWDPIO0)
2590 & ~BPCTLI_CTRL_SWDPIN0));
2591 if (!PEGF_IF_SERIES(pbpctl_dev->subdevice)) {
2592 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
2595 (BPCTLI_CTRL_SDP0_DATA
2597 BPCTLI_CTRL_SDP0_DIR)));
2600 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2601 ((ctrl | BP10G_SDP0_DIR) &
2612 /* SET_FORCE_LINK (non-Bypass command :)) */
2613 static int set_bp_force_link(bpctl_dev_t *pbpctl_dev, int tx_state)
2615 int ret = 0, ctrl = 0;
2617 if (DBI_IF_SERIES(pbpctl_dev->subdevice)) {
2619 if ((pbpctl_dev->bp_10g) || (pbpctl_dev->bp_10g9)) {
2621 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL);
2623 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2624 ctrl & ~BP10G_SDP1_DIR);
2626 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2627 ((ctrl | BP10G_SDP1_DIR) &
2636 /*RESET_CONT 0x20 */
2637 int reset_cont(bpctl_dev_t *pbpctl_dev)
2639 int ret = BP_NOT_CAP;
2641 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
2642 if (INTEL_IF_SERIES(pbpctl_dev->subdevice))
2644 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER)
2645 write_data(pbpctl_dev, RESET_CONT);
2647 data_pulse(pbpctl_dev, RESET_CONT);
2653 /*DIS_BYPASS_CAP 0x22 */
2654 int dis_bypass_cap(bpctl_dev_t *pbpctl_dev)
2657 if (pbpctl_dev->bp_caps & BP_DIS_CAP) {
2658 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
2659 write_data_int(pbpctl_dev, DIS_BYPASS_CAP_INT);
2660 msec_delay_bp(BYPASS_DELAY_INT);
2662 write_data(pbpctl_dev, BYPASS_OFF);
2663 msec_delay_bp(LATCH_DELAY);
2664 write_data(pbpctl_dev, DIS_BYPASS_CAP);
2665 msec_delay_bp(BYPASS_CAP_DELAY);
2672 /*EN_BYPASS_CAP 0x24 */
2673 int en_bypass_cap(bpctl_dev_t *pbpctl_dev)
2675 if (pbpctl_dev->bp_caps & BP_DIS_CAP) {
2676 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
2677 write_data_int(pbpctl_dev, PWROFF_BYPASS_ON_INT);
2678 msec_delay_bp(BYPASS_DELAY_INT);
2680 write_data(pbpctl_dev, EN_BYPASS_CAP);
2681 msec_delay_bp(BYPASS_CAP_DELAY);
2688 /* BYPASS_STATE_PWRON 0x26*/
2689 int bypass_state_pwron(bpctl_dev_t *pbpctl_dev)
2691 if (pbpctl_dev->bp_caps & BP_PWUP_CTL_CAP) {
2692 write_data(pbpctl_dev, BYPASS_STATE_PWRON);
2693 if (pbpctl_dev->bp_ext_ver == PXG2BPI_VER)
2694 msec_delay_bp(DFLT_PWRON_DELAY);
2696 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2702 /* NORMAL_STATE_PWRON 0x28*/
2703 int normal_state_pwron(bpctl_dev_t *pbpctl_dev)
2705 if ((pbpctl_dev->bp_caps & BP_PWUP_CTL_CAP)
2706 || (pbpctl_dev->bp_caps & TAP_PWUP_CTL_CAP)) {
2707 write_data(pbpctl_dev, NORMAL_STATE_PWRON);
2708 if (pbpctl_dev->bp_ext_ver == PXG2BPI_VER)
2709 msec_delay_bp(DFLT_PWRON_DELAY);
2711 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2717 /* BYPASS_STATE_PWROFF 0x27*/
2718 int bypass_state_pwroff(bpctl_dev_t *pbpctl_dev)
2720 if (pbpctl_dev->bp_caps & BP_PWOFF_CTL_CAP) {
2721 write_data(pbpctl_dev, BYPASS_STATE_PWROFF);
2722 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2728 /* NORMAL_STATE_PWROFF 0x29*/
2729 int normal_state_pwroff(bpctl_dev_t *pbpctl_dev)
2731 if ((pbpctl_dev->bp_caps & BP_PWOFF_CTL_CAP)) {
2732 write_data(pbpctl_dev, NORMAL_STATE_PWROFF);
2733 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2739 /*TAP_STATE_PWRON 0x2a*/
2740 int tap_state_pwron(bpctl_dev_t *pbpctl_dev)
2742 if (pbpctl_dev->bp_caps & TAP_PWUP_CTL_CAP) {
2743 write_data(pbpctl_dev, TAP_STATE_PWRON);
2744 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2750 /*DIS_TAP_CAP 0x2c*/
2751 int dis_tap_cap(bpctl_dev_t *pbpctl_dev)
2753 if (pbpctl_dev->bp_caps & TAP_DIS_CAP) {
2754 write_data(pbpctl_dev, DIS_TAP_CAP);
2755 msec_delay_bp(BYPASS_CAP_DELAY);
2762 int en_tap_cap(bpctl_dev_t *pbpctl_dev)
2764 if (pbpctl_dev->bp_caps & TAP_DIS_CAP) {
2765 write_data(pbpctl_dev, EN_TAP_CAP);
2766 msec_delay_bp(BYPASS_CAP_DELAY);
2772 /*DISC_STATE_PWRON 0x2a*/
2773 int disc_state_pwron(bpctl_dev_t *pbpctl_dev)
2775 if (pbpctl_dev->bp_caps & DISC_PWUP_CTL_CAP) {
2776 if (pbpctl_dev->bp_ext_ver >= 0x8) {
2777 write_data(pbpctl_dev, DISC_STATE_PWRON);
2778 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2785 /*DIS_DISC_CAP 0x2c*/
2786 int dis_disc_cap(bpctl_dev_t *pbpctl_dev)
2788 if (pbpctl_dev->bp_caps & DISC_DIS_CAP) {
2789 if (pbpctl_dev->bp_ext_ver >= 0x8) {
2790 write_data(pbpctl_dev, DIS_DISC_CAP);
2791 msec_delay_bp(BYPASS_CAP_DELAY);
2798 /*DISC_STATE_PWRON 0x2a*/
2799 int disc_port_state_pwron(bpctl_dev_t *pbpctl_dev)
2802 bpctl_dev_t *pbpctl_dev_m;
2806 if ((is_bypass_fn(pbpctl_dev)) == 1)
2807 pbpctl_dev_m = pbpctl_dev;
2809 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
2810 if (pbpctl_dev_m == NULL)
2813 if (pbpctl_dev_m->bp_caps_ex & DISC_PORT_CAP_EX) {
2814 if (is_bypass_fn(pbpctl_dev) == 1)
2815 write_data(pbpctl_dev_m, TX_DISA_PWRUP);
2817 write_data(pbpctl_dev_m, TX_DISB_PWRUP);
2819 msec_delay_bp(LATCH_DELAY);
2825 int normal_port_state_pwron(bpctl_dev_t *pbpctl_dev)
2828 bpctl_dev_t *pbpctl_dev_m;
2831 if ((is_bypass_fn(pbpctl_dev)) == 1)
2832 pbpctl_dev_m = pbpctl_dev;
2834 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
2835 if (pbpctl_dev_m == NULL)
2838 if (pbpctl_dev_m->bp_caps_ex & DISC_PORT_CAP_EX) {
2839 if (is_bypass_fn(pbpctl_dev) == 1)
2840 write_data(pbpctl_dev_m, TX_ENA_PWRUP);
2842 write_data(pbpctl_dev_m, TX_ENB_PWRUP);
2844 msec_delay_bp(LATCH_DELAY);
2851 int en_disc_cap(bpctl_dev_t *pbpctl_dev)
2853 if (pbpctl_dev->bp_caps & DISC_DIS_CAP) {
2854 if (pbpctl_dev->bp_ext_ver >= 0x8) {
2855 write_data(pbpctl_dev, EN_DISC_CAP);
2856 msec_delay_bp(BYPASS_CAP_DELAY);
2863 int std_nic_on(bpctl_dev_t *pbpctl_dev)
2866 if (pbpctl_dev->bp_caps & STD_NIC_CAP) {
2868 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
2869 write_data_int(pbpctl_dev, DIS_BYPASS_CAP_INT);
2870 msec_delay_bp(BYPASS_DELAY_INT);
2871 pbpctl_dev->bp_status_un = 0;
2875 if (pbpctl_dev->bp_ext_ver >= 0x8) {
2876 write_data(pbpctl_dev, STD_NIC_ON);
2877 msec_delay_bp(BYPASS_CAP_DELAY);
2882 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
2883 wdt_off(pbpctl_dev);
2885 if (pbpctl_dev->bp_caps & BP_CAP) {
2886 write_data(pbpctl_dev, BYPASS_OFF);
2887 msec_delay_bp(LATCH_DELAY);
2890 if (pbpctl_dev->bp_caps & TAP_CAP) {
2891 write_data(pbpctl_dev, TAP_OFF);
2892 msec_delay_bp(LATCH_DELAY);
2895 write_data(pbpctl_dev, NORMAL_STATE_PWRON);
2896 if (pbpctl_dev->bp_ext_ver == PXG2BPI_VER)
2897 msec_delay_bp(DFLT_PWRON_DELAY);
2899 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2901 if (pbpctl_dev->bp_caps & BP_DIS_CAP) {
2902 write_data(pbpctl_dev, DIS_BYPASS_CAP);
2903 msec_delay_bp(BYPASS_CAP_DELAY);
2906 if (pbpctl_dev->bp_caps & TAP_DIS_CAP) {
2907 write_data(pbpctl_dev, DIS_TAP_CAP);
2908 msec_delay_bp(BYPASS_CAP_DELAY);
2917 int std_nic_off(bpctl_dev_t *pbpctl_dev)
2920 if (pbpctl_dev->bp_caps & STD_NIC_CAP) {
2921 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
2922 write_data_int(pbpctl_dev, PWROFF_BYPASS_ON_INT);
2923 msec_delay_bp(BYPASS_DELAY_INT);
2926 if (pbpctl_dev->bp_ext_ver >= 0x8) {
2927 write_data(pbpctl_dev, STD_NIC_OFF);
2928 msec_delay_bp(BYPASS_CAP_DELAY);
2933 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
2935 if (pbpctl_dev->bp_caps & TAP_PWUP_CTL_CAP) {
2936 write_data(pbpctl_dev, TAP_STATE_PWRON);
2937 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2940 if (pbpctl_dev->bp_caps & BP_PWUP_CTL_CAP) {
2941 write_data(pbpctl_dev, BYPASS_STATE_PWRON);
2942 if (pbpctl_dev->bp_ext_ver > PXG2BPI_VER)
2943 msec_delay_bp(LATCH_DELAY +
2946 msec_delay_bp(DFLT_PWRON_DELAY);
2949 if (pbpctl_dev->bp_caps & TAP_DIS_CAP) {
2950 write_data(pbpctl_dev, EN_TAP_CAP);
2951 msec_delay_bp(BYPASS_CAP_DELAY);
2953 if (pbpctl_dev->bp_caps & DISC_DIS_CAP) {
2954 write_data(pbpctl_dev, EN_DISC_CAP);
2955 msec_delay_bp(BYPASS_CAP_DELAY);
2958 if (pbpctl_dev->bp_caps & BP_DIS_CAP) {
2959 write_data(pbpctl_dev, EN_BYPASS_CAP);
2960 msec_delay_bp(BYPASS_CAP_DELAY);
2969 int wdt_time_left(bpctl_dev_t *pbpctl_dev)
2972 /* unsigned long curr_time=((long long)(jiffies*1000))/HZ, delta_time=0,wdt_on_time=((long long)(pbpctl_dev->bypass_wdt_on_time*1000))/HZ; */
2973 unsigned long curr_time = jiffies, delta_time = 0, wdt_on_time =
2974 pbpctl_dev->bypass_wdt_on_time, delta_time_msec = 0;
2977 switch (pbpctl_dev->wdt_status) {
2978 case WDT_STATUS_DIS:
2984 wdt_on_time) ? (curr_time - wdt_on_time) : (~wdt_on_time +
2986 delta_time_msec = jiffies_to_msecs(delta_time);
2987 time_left = pbpctl_dev->bypass_timer_interval - delta_time_msec;
2988 if (time_left < 0) {
2990 pbpctl_dev->wdt_status = WDT_STATUS_EXP;
2993 case WDT_STATUS_EXP:
3001 static int wdt_timer(bpctl_dev_t *pbpctl_dev, int *time_left)
3004 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
3006 if (pbpctl_dev->wdt_status == WDT_STATUS_UNKNOWN)
3009 *time_left = wdt_time_left(pbpctl_dev);
3017 static int wdt_timer_reload(bpctl_dev_t *pbpctl_dev)
3022 if ((pbpctl_dev->bp_caps & WD_CTL_CAP) &&
3023 (pbpctl_dev->wdt_status != WDT_STATUS_UNKNOWN)) {
3024 if (pbpctl_dev->wdt_status == WDT_STATUS_DIS)
3026 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER)
3027 ret = wdt_pulse(pbpctl_dev);
3028 else if (INTEL_IF_SERIES(pbpctl_dev->subdevice))
3029 ret = wdt_pulse_int(pbpctl_dev);
3031 ret = send_wdt_pulse(pbpctl_dev);
3033 mod_timer(&pbpctl_dev->bp_timer, jiffies+1);*/
3039 static void wd_reset_timer(unsigned long param)
3041 bpctl_dev_t *pbpctl_dev = (bpctl_dev_t *) param;
3043 struct sk_buff *skb_tmp;
3046 if ((pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) &&
3047 ((atomic_read(&pbpctl_dev->wdt_busy)) == 1)) {
3048 mod_timer(&pbpctl_dev->bp_timer, jiffies + 1);
3053 if (pbpctl_dev->bp_self_test_flag == 1) {
3054 skb_tmp = dev_alloc_skb(BPTEST_DATA_LEN + 2);
3055 if ((skb_tmp) && (pbpctl_dev->ndev) && (pbpctl_dev->bp_tx_data)) {
3056 memcpy(skb_put(skb_tmp, BPTEST_DATA_LEN),
3057 pbpctl_dev->bp_tx_data, BPTEST_DATA_LEN);
3058 skb_tmp->dev = pbpctl_dev->ndev;
3060 eth_type_trans(skb_tmp, pbpctl_dev->ndev);
3061 skb_tmp->ip_summed = CHECKSUM_UNNECESSARY;
3062 netif_receive_skb(skb_tmp);
3063 goto bp_timer_reload;
3069 wdt_timer_reload(pbpctl_dev);
3073 if (pbpctl_dev->reset_time) {
3074 mod_timer(&pbpctl_dev->bp_timer,
3075 jiffies + (HZ * pbpctl_dev->reset_time) / 1000);
3079 /*WAIT_AT_PWRUP 0x80 */
3080 int bp_wait_at_pwup_en(bpctl_dev_t *pbpctl_dev)
3083 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3084 if (pbpctl_dev->bp_ext_ver >= BP_FW_EXT_VER8) {
3085 write_data(pbpctl_dev, BP_WAIT_AT_PWUP_EN);
3086 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
3094 /*DIS_WAIT_AT_PWRUP 0x81 */
3095 int bp_wait_at_pwup_dis(bpctl_dev_t *pbpctl_dev)
3098 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3100 if (pbpctl_dev->bp_ext_ver >= BP_FW_EXT_VER8) {
3101 write_data(pbpctl_dev, BP_WAIT_AT_PWUP_DIS);
3102 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
3110 /*EN_HW_RESET 0x82 */
3112 int bp_hw_reset_en(bpctl_dev_t *pbpctl_dev)
3115 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3116 if (pbpctl_dev->bp_ext_ver >= BP_FW_EXT_VER8) {
3117 write_data(pbpctl_dev, BP_HW_RESET_EN);
3118 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
3126 /*DIS_HW_RESET 0x83 */
3128 int bp_hw_reset_dis(bpctl_dev_t *pbpctl_dev)
3131 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3132 if (pbpctl_dev->bp_ext_ver >= BP_FW_EXT_VER8) {
3133 write_data(pbpctl_dev, BP_HW_RESET_DIS);
3134 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
3143 int wdt_exp_mode(bpctl_dev_t *pbpctl_dev, int mode)
3145 uint32_t status_reg = 0, status_reg1 = 0;
3147 if ((pbpctl_dev->bp_caps & (TAP_STATUS_CAP | DISC_CAP)) &&
3148 (pbpctl_dev->bp_caps & BP_CAP)) {
3149 if (pbpctl_dev->bp_ext_ver >= PXE2TBPI_VER) {
3151 if ((pbpctl_dev->bp_ext_ver >= 0x8) &&
3152 (mode == 2) && (pbpctl_dev->bp_caps & DISC_CAP)) {
3154 read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR);
3155 if (!(status_reg1 & WDTE_DISC_BPN_MASK))
3156 write_reg(pbpctl_dev,
3159 STATUS_DISC_REG_ADDR);
3163 status_reg = read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR);
3165 if ((mode == 0) && (pbpctl_dev->bp_caps & BP_CAP)) {
3166 if (pbpctl_dev->bp_ext_ver >= 0x8) {
3168 read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR);
3169 if (status_reg1 & WDTE_DISC_BPN_MASK)
3170 write_reg(pbpctl_dev,
3172 ~WDTE_DISC_BPN_MASK,
3173 STATUS_DISC_REG_ADDR);
3175 if (status_reg & WDTE_TAP_BPN_MASK)
3176 write_reg(pbpctl_dev,
3177 status_reg & ~WDTE_TAP_BPN_MASK,
3178 STATUS_TAP_REG_ADDR);
3181 } else if ((mode == 1) && (pbpctl_dev->bp_caps & TAP_CAP)) {
3182 if (!(status_reg & WDTE_TAP_BPN_MASK))
3183 write_reg(pbpctl_dev,
3184 status_reg | WDTE_TAP_BPN_MASK,
3185 STATUS_TAP_REG_ADDR);
3186 /*else return BP_NOT_CAP; */
3194 int bypass_fw_ver(bpctl_dev_t *pbpctl_dev)
3196 if (is_bypass_fn(pbpctl_dev))
3197 return read_reg(pbpctl_dev, VER_REG_ADDR);
3202 int bypass_sign_check(bpctl_dev_t *pbpctl_dev)
3205 if (is_bypass_fn(pbpctl_dev))
3206 return (((read_reg(pbpctl_dev, PIC_SIGN_REG_ADDR)) ==
3207 PIC_SIGN_VALUE) ? 1 : 0);
3212 static int tx_status(bpctl_dev_t *pbpctl_dev)
3215 bpctl_dev_t *pbpctl_dev_m;
3216 if ((is_bypass_fn(pbpctl_dev)) == 1)
3217 pbpctl_dev_m = pbpctl_dev;
3219 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
3220 if (pbpctl_dev_m == NULL)
3222 if (pbpctl_dev_m->bp_caps_ex & DISC_PORT_CAP_EX) {
3224 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL);
3225 if (pbpctl_dev->bp_i80)
3226 return ((ctrl & BPCTLI_CTRL_SWDPIN1) != 0 ? 0 : 1);
3227 if (pbpctl_dev->bp_540) {
3228 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
3230 return ((ctrl & BP10G_SDP1_DATA) != 0 ? 0 : 1);
3235 if (pbpctl_dev->bp_caps & TX_CTL_CAP) {
3236 if (PEG5_IF_SERIES(pbpctl_dev->subdevice)) {
3240 (pbpctl_dev, BPCTLI_PHY_CONTROL, &mii_reg))) {
3241 if (mii_reg & BPCTLI_MII_CR_POWER_DOWN)
3250 if (pbpctl_dev->bp_10g9) {
3251 return ((BP10G_READ_REG(pbpctl_dev, ESDP) &
3252 BP10G_SDP3_DATA) != 0 ? 0 : 1);
3254 } else if (pbpctl_dev->bp_fiber5) {
3255 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
3256 if (ctrl & BPCTLI_CTRL_EXT_SDP6_DATA)
3259 } else if (pbpctl_dev->bp_10gb) {
3260 ctrl = BP10GB_READ_REG(pbpctl_dev, MISC_REG_GPIO);
3261 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_GPIO,
3262 (ctrl | BP10GB_GPIO0_OE_P1) &
3263 ~(BP10GB_GPIO0_SET_P1 |
3264 BP10GB_GPIO0_CLR_P1));
3266 if ((pbpctl_dev->func == 1) || (pbpctl_dev->func == 3))
3267 return (((BP10GB_READ_REG
3269 MISC_REG_GPIO)) & BP10GB_GPIO0_P1) !=
3272 return (((BP10GB_READ_REG
3274 MISC_REG_GPIO)) & BP10GB_GPIO0_P0) !=
3278 if (!pbpctl_dev->bp_10g) {
3280 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL);
3281 if (pbpctl_dev->bp_i80)
3282 return ((ctrl & BPCTLI_CTRL_SWDPIN1) !=
3284 if (pbpctl_dev->bp_540) {
3285 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
3287 return ((ctrl & BP10G_SDP1_DATA) != 0 ? 0 : 1);
3290 return ((ctrl & BPCTLI_CTRL_SWDPIN0) != 0 ? 0 : 1);
3292 return ((BP10G_READ_REG(pbpctl_dev, ESDP) &
3293 BP10G_SDP0_DATA) != 0 ? 0 : 1);
3299 static int bp_force_link_status(bpctl_dev_t *pbpctl_dev)
3302 if (DBI_IF_SERIES(pbpctl_dev->subdevice)) {
3304 if ((pbpctl_dev->bp_10g) || (pbpctl_dev->bp_10g9)) {
3305 return ((BP10G_READ_REG(pbpctl_dev, ESDP) &
3306 BP10G_SDP1_DIR) != 0 ? 1 : 0);
3313 int bypass_from_last_read(bpctl_dev_t *pbpctl_dev)
3315 uint32_t ctrl_ext = 0;
3316 bpctl_dev_t *pbpctl_dev_b = NULL;
3318 if ((pbpctl_dev->bp_caps & SW_CTL_CAP)
3319 && (pbpctl_dev_b = get_status_port_fn(pbpctl_dev))) {
3320 ctrl_ext = BPCTL_READ_REG(pbpctl_dev_b, CTRL_EXT);
3321 BPCTL_BP_WRITE_REG(pbpctl_dev_b, CTRL_EXT,
3322 (ctrl_ext & ~BPCTLI_CTRL_EXT_SDP7_DIR));
3323 ctrl_ext = BPCTL_READ_REG(pbpctl_dev_b, CTRL_EXT);
3324 if (ctrl_ext & BPCTLI_CTRL_EXT_SDP7_DATA)
3331 int bypass_status_clear(bpctl_dev_t *pbpctl_dev)
3333 bpctl_dev_t *pbpctl_dev_b = NULL;
3335 if ((pbpctl_dev->bp_caps & SW_CTL_CAP)
3336 && (pbpctl_dev_b = get_status_port_fn(pbpctl_dev))) {
3338 send_bypass_clear_pulse(pbpctl_dev_b, 1);
3344 int bypass_flag_status(bpctl_dev_t *pbpctl_dev)
3347 if ((pbpctl_dev->bp_caps & BP_CAP)) {
3348 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3349 return ((((read_reg(pbpctl_dev, STATUS_REG_ADDR)) &
3350 BYPASS_FLAG_MASK) ==
3351 BYPASS_FLAG_MASK) ? 1 : 0);
3357 int bypass_flag_status_clear(bpctl_dev_t *pbpctl_dev)
3360 if (pbpctl_dev->bp_caps & BP_CAP) {
3361 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3362 uint32_t status_reg = 0;
3363 status_reg = read_reg(pbpctl_dev, STATUS_REG_ADDR);
3364 write_reg(pbpctl_dev, status_reg & ~BYPASS_FLAG_MASK,
3372 int bypass_change_status(bpctl_dev_t *pbpctl_dev)
3374 int ret = BP_NOT_CAP;
3376 if (pbpctl_dev->bp_caps & BP_STATUS_CHANGE_CAP) {
3377 if (pbpctl_dev->bp_ext_ver >= 0x8) {
3378 ret = bypass_flag_status(pbpctl_dev);
3379 bypass_flag_status_clear(pbpctl_dev);
3380 } else if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3381 ret = bypass_flag_status(pbpctl_dev);
3382 bypass_flag_status_clear(pbpctl_dev);
3384 ret = bypass_from_last_read(pbpctl_dev);
3385 bypass_status_clear(pbpctl_dev);
3391 int bypass_off_status(bpctl_dev_t *pbpctl_dev)
3394 if (pbpctl_dev->bp_caps & BP_CAP) {
3395 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3396 return ((((read_reg(pbpctl_dev, STATUS_REG_ADDR)) &
3397 BYPASS_OFF_MASK) == BYPASS_OFF_MASK) ? 1 : 0);
3403 static int bypass_status(bpctl_dev_t *pbpctl_dev)
3406 if (pbpctl_dev->bp_caps & BP_CAP) {
3408 bpctl_dev_t *pbpctl_dev_b = NULL;
3410 if (!(pbpctl_dev_b = get_status_port_fn(pbpctl_dev)))
3413 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
3415 if (!pbpctl_dev->bp_status_un)
3416 return (((BPCTL_READ_REG
3419 BPCTLI_CTRL_EXT_SDP7_DATA) !=
3424 if (pbpctl_dev->bp_ext_ver >= 0x8) {
3426 if (pbpctl_dev->bp_10g9) {
3427 ctrl_ext = BP10G_READ_REG(pbpctl_dev_b, I2CCTL);
3428 BP10G_WRITE_REG(pbpctl_dev_b, I2CCTL,
3429 (ctrl_ext | BP10G_I2C_CLK_OUT));
3430 return ((BP10G_READ_REG(pbpctl_dev_b, I2CCTL) &
3431 BP10G_I2C_CLK_IN) != 0 ? 0 : 1);
3433 } else if (pbpctl_dev->bp_540) {
3434 return (((BP10G_READ_REG(pbpctl_dev_b, ESDP)) &
3435 BP10G_SDP0_DATA) != 0 ? 0 : 1);
3438 else if ((pbpctl_dev->bp_fiber5)
3439 || (pbpctl_dev->bp_i80)) {
3440 return (((BPCTL_READ_REG(pbpctl_dev_b, CTRL)) &
3441 BPCTLI_CTRL_SWDPIN0) != 0 ? 0 : 1);
3442 } else if (pbpctl_dev->bp_10gb) {
3444 BP10GB_READ_REG(pbpctl_dev, MISC_REG_GPIO);
3445 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_GPIO,
3446 (ctrl_ext | BP10GB_GPIO3_OE_P0)
3447 & ~(BP10GB_GPIO3_SET_P0 |
3448 BP10GB_GPIO3_CLR_P0));
3450 return (((BP10GB_READ_REG
3452 MISC_REG_GPIO)) & BP10GB_GPIO3_P0) !=
3456 else if (!pbpctl_dev->bp_10g)
3457 return (((BPCTL_READ_REG
3460 BPCTLI_CTRL_EXT_SDP7_DATA) !=
3464 ctrl_ext = BP10G_READ_REG(pbpctl_dev_b, EODSDP);
3465 BP10G_WRITE_REG(pbpctl_dev_b, EODSDP,
3467 BP10G_SDP7_DATA_OUT));
3468 return ((BP10G_READ_REG(pbpctl_dev_b, EODSDP) &
3469 BP10G_SDP7_DATA_IN) != 0 ? 0 : 1);
3472 } else if (pbpctl_dev->media_type == bp_copper) {
3474 return (((BPCTL_READ_REG(pbpctl_dev_b, CTRL)) &
3475 BPCTLI_CTRL_SWDPIN1) != 0 ? 1 : 0);
3477 if ((bypass_status_clear(pbpctl_dev)) >= 0)
3478 return bypass_from_last_read(pbpctl_dev);
3485 int default_pwron_status(bpctl_dev_t *pbpctl_dev)
3488 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3489 if (pbpctl_dev->bp_caps & BP_PWUP_CTL_CAP) {
3490 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3493 STATUS_REG_ADDR)) & DFLT_PWRON_MASK)
3494 == DFLT_PWRON_MASK) ? 0 : 1);
3496 } /*else if ((!pbpctl_dev->bp_caps&BP_DIS_CAP)&&
3497 (pbpctl_dev->bp_caps&BP_PWUP_ON_CAP))
3503 static int default_pwroff_status(bpctl_dev_t *pbpctl_dev)
3506 /*if ((!pbpctl_dev->bp_caps&BP_DIS_CAP)&&
3507 (pbpctl_dev->bp_caps&BP_PWOFF_ON_CAP))
3509 if ((pbpctl_dev->bp_caps & SW_CTL_CAP)
3510 && (pbpctl_dev->bp_caps & BP_PWOFF_CTL_CAP)) {
3511 return ((((read_reg(pbpctl_dev, STATUS_REG_ADDR)) &
3512 DFLT_PWROFF_MASK) == DFLT_PWROFF_MASK) ? 0 : 1);
3517 int dis_bypass_cap_status(bpctl_dev_t *pbpctl_dev)
3520 if (pbpctl_dev->bp_caps & BP_DIS_CAP) {
3521 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3522 return ((((read_reg(pbpctl_dev, STATUS_REG_ADDR)) &
3523 DIS_BYPASS_CAP_MASK) ==
3524 DIS_BYPASS_CAP_MASK) ? 1 : 0);
3530 int cmd_en_status(bpctl_dev_t *pbpctl_dev)
3533 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3534 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3535 return ((((read_reg(pbpctl_dev, STATUS_REG_ADDR)) &
3536 CMND_EN_MASK) == CMND_EN_MASK) ? 1 : 0);
3542 int wdt_en_status(bpctl_dev_t *pbpctl_dev)
3545 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
3546 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3547 return ((((read_reg(pbpctl_dev, STATUS_REG_ADDR)) &
3548 WDT_EN_MASK) == WDT_EN_MASK) ? 1 : 0);
3554 int wdt_programmed(bpctl_dev_t *pbpctl_dev, int *timeout)
3557 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
3558 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3559 if ((read_reg(pbpctl_dev, STATUS_REG_ADDR)) &
3562 wdt_val = read_reg(pbpctl_dev, WDT_REG_ADDR);
3563 *timeout = (1 << wdt_val) * 100;
3567 int curr_wdt_status = pbpctl_dev->wdt_status;
3568 if (curr_wdt_status == WDT_STATUS_UNKNOWN)
3573 0 ? 0 : pbpctl_dev->bypass_timer_interval;
3580 int bypass_support(bpctl_dev_t *pbpctl_dev)
3584 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3585 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER) {
3587 ((((read_reg(pbpctl_dev, PRODUCT_CAP_REG_ADDR)) &
3588 BYPASS_SUPPORT_MASK) ==
3589 BYPASS_SUPPORT_MASK) ? 1 : 0);
3590 } else if (pbpctl_dev->bp_ext_ver == PXG2BPI_VER)
3597 int tap_support(bpctl_dev_t *pbpctl_dev)
3601 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3602 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER) {
3604 ((((read_reg(pbpctl_dev, PRODUCT_CAP_REG_ADDR)) &
3605 TAP_SUPPORT_MASK) == TAP_SUPPORT_MASK) ? 1 : 0);
3606 } else if (pbpctl_dev->bp_ext_ver == PXG2BPI_VER)
3613 int normal_support(bpctl_dev_t *pbpctl_dev)
3615 int ret = BP_NOT_CAP;
3617 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3618 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER) {
3620 ((((read_reg(pbpctl_dev, PRODUCT_CAP_REG_ADDR)) &
3621 NORMAL_UNSUPPORT_MASK) ==
3622 NORMAL_UNSUPPORT_MASK) ? 0 : 1);
3629 int get_bp_prod_caps(bpctl_dev_t *pbpctl_dev)
3631 if ((pbpctl_dev->bp_caps & SW_CTL_CAP) &&
3632 (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER))
3633 return read_reg(pbpctl_dev, PRODUCT_CAP_REG_ADDR);
3638 int tap_flag_status(bpctl_dev_t *pbpctl_dev)
3641 if (pbpctl_dev->bp_caps & TAP_STATUS_CAP) {
3642 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER)
3643 return ((((read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR)) &
3644 TAP_FLAG_MASK) == TAP_FLAG_MASK) ? 1 : 0);
3650 int tap_flag_status_clear(bpctl_dev_t *pbpctl_dev)
3652 uint32_t status_reg = 0;
3653 if (pbpctl_dev->bp_caps & TAP_STATUS_CAP) {
3654 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER) {
3655 status_reg = read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR);
3656 write_reg(pbpctl_dev, status_reg & ~TAP_FLAG_MASK,
3657 STATUS_TAP_REG_ADDR);
3664 int tap_change_status(bpctl_dev_t *pbpctl_dev)
3666 int ret = BP_NOT_CAP;
3667 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER) {
3668 if (pbpctl_dev->bp_caps & TAP_CAP) {
3669 if (pbpctl_dev->bp_caps & BP_CAP) {
3670 ret = tap_flag_status(pbpctl_dev);
3671 tap_flag_status_clear(pbpctl_dev);
3673 ret = bypass_from_last_read(pbpctl_dev);
3674 bypass_status_clear(pbpctl_dev);
3681 int tap_off_status(bpctl_dev_t *pbpctl_dev)
3683 if (pbpctl_dev->bp_caps & TAP_CAP) {
3684 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER)
3685 return ((((read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR)) &
3686 TAP_OFF_MASK) == TAP_OFF_MASK) ? 1 : 0);
3691 int tap_status(bpctl_dev_t *pbpctl_dev)
3695 if (pbpctl_dev->bp_caps & TAP_CAP) {
3696 bpctl_dev_t *pbpctl_dev_b = NULL;
3698 if (!(pbpctl_dev_b = get_status_port_fn(pbpctl_dev)))
3701 if (pbpctl_dev->bp_ext_ver >= 0x8) {
3702 if (!pbpctl_dev->bp_10g)
3703 return (((BPCTL_READ_REG
3706 BPCTLI_CTRL_EXT_SDP6_DATA) !=
3709 ctrl_ext = BP10G_READ_REG(pbpctl_dev_b, EODSDP);
3710 BP10G_WRITE_REG(pbpctl_dev_b, EODSDP,
3712 BP10G_SDP6_DATA_OUT));
3713 return ((BP10G_READ_REG(pbpctl_dev_b, EODSDP) &
3714 BP10G_SDP6_DATA_IN) != 0 ? 0 : 1);
3717 } else if (pbpctl_dev->media_type == bp_copper)
3718 return (((BPCTL_READ_REG(pbpctl_dev, CTRL)) &
3719 BPCTLI_CTRL_SWDPIN0) != 0 ? 1 : 0);
3721 if ((bypass_status_clear(pbpctl_dev)) >= 0)
3722 return bypass_from_last_read(pbpctl_dev);
3729 int default_pwron_tap_status(bpctl_dev_t *pbpctl_dev)
3731 if (pbpctl_dev->bp_caps & TAP_PWUP_CTL_CAP) {
3732 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER)
3733 return ((((read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR)) &
3734 DFLT_PWRON_TAP_MASK) ==
3735 DFLT_PWRON_TAP_MASK) ? 1 : 0);
3740 int dis_tap_cap_status(bpctl_dev_t *pbpctl_dev)
3742 if (pbpctl_dev->bp_caps & TAP_PWUP_CTL_CAP) {
3743 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER)
3744 return ((((read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR)) &
3745 DIS_TAP_CAP_MASK) ==
3746 DIS_TAP_CAP_MASK) ? 1 : 0);
3751 int disc_flag_status(bpctl_dev_t *pbpctl_dev)
3754 if (pbpctl_dev->bp_caps & DISC_CAP) {
3755 if (pbpctl_dev->bp_ext_ver >= 0x8)
3756 return ((((read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR)) &
3757 DISC_FLAG_MASK) == DISC_FLAG_MASK) ? 1 : 0);
3763 int disc_flag_status_clear(bpctl_dev_t *pbpctl_dev)
3765 uint32_t status_reg = 0;
3766 if (pbpctl_dev->bp_caps & DISC_CAP) {
3767 if (pbpctl_dev->bp_ext_ver >= 0x8) {
3768 status_reg = read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR);
3769 write_reg(pbpctl_dev, status_reg & ~DISC_FLAG_MASK,
3770 STATUS_DISC_REG_ADDR);
3777 int disc_change_status(bpctl_dev_t *pbpctl_dev)
3779 int ret = BP_NOT_CAP;
3780 if (pbpctl_dev->bp_caps & DISC_CAP) {
3781 ret = disc_flag_status(pbpctl_dev);
3782 disc_flag_status_clear(pbpctl_dev);
3788 int disc_off_status(bpctl_dev_t *pbpctl_dev)
3790 bpctl_dev_t *pbpctl_dev_b = NULL;
3793 if (pbpctl_dev->bp_caps & DISC_CAP) {
3794 if (!(pbpctl_dev_b = get_status_port_fn(pbpctl_dev)))
3796 if (DISCF_IF_SERIES(pbpctl_dev->subdevice))
3797 return ((((read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR)) &
3798 DISC_OFF_MASK) == DISC_OFF_MASK) ? 1 : 0);
3800 if (pbpctl_dev->bp_i80) {
3801 return (((BPCTL_READ_REG(pbpctl_dev_b, CTRL_EXT)) &
3802 BPCTLI_CTRL_EXT_SDP6_DATA) != 0 ? 1 : 0);
3805 if (pbpctl_dev->bp_540) {
3806 ctrl_ext = BP10G_READ_REG(pbpctl_dev_b, ESDP);
3807 return ((BP10G_READ_REG(pbpctl_dev_b, ESDP) &
3808 BP10G_SDP2_DATA) != 0 ? 1 : 0);
3811 if (pbpctl_dev->media_type == bp_copper) {
3814 return ((((read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR)) &
3815 DISC_OFF_MASK) == DISC_OFF_MASK) ? 1 : 0);
3817 if (!pbpctl_dev->bp_10g)
3818 return (((BPCTL_READ_REG(pbpctl_dev_b, CTRL)) &
3819 BPCTLI_CTRL_SWDPIN1) != 0 ? 1 : 0);
3821 return ((BP10G_READ_REG(pbpctl_dev_b, ESDP) &
3822 BP10G_SDP1_DATA) != 0 ? 1 : 0);
3826 if (pbpctl_dev->bp_10g9) {
3827 ctrl_ext = BP10G_READ_REG(pbpctl_dev_b, I2CCTL);
3828 BP10G_WRITE_REG(pbpctl_dev_b, I2CCTL,
3830 BP10G_I2C_DATA_OUT));
3831 return ((BP10G_READ_REG(pbpctl_dev_b, I2CCTL) &
3832 BP10G_I2C_DATA_IN) != 0 ? 1 : 0);
3834 } else if (pbpctl_dev->bp_fiber5) {
3835 return (((BPCTL_READ_REG(pbpctl_dev_b, CTRL)) &
3836 BPCTLI_CTRL_SWDPIN1) != 0 ? 1 : 0);
3837 } else if (pbpctl_dev->bp_10gb) {
3839 BP10GB_READ_REG(pbpctl_dev, MISC_REG_GPIO);
3840 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_GPIO,
3841 (ctrl_ext | BP10GB_GPIO3_OE_P1)
3842 & ~(BP10GB_GPIO3_SET_P1 |
3843 BP10GB_GPIO3_CLR_P1));
3845 return (((BP10GB_READ_REG
3847 MISC_REG_GPIO)) & BP10GB_GPIO3_P1) !=
3850 if (!pbpctl_dev->bp_10g) {
3852 return (((BPCTL_READ_REG
3855 BPCTLI_CTRL_EXT_SDP6_DATA) !=
3858 ctrl_ext = BP10G_READ_REG(pbpctl_dev_b, EODSDP);
3859 BP10G_WRITE_REG(pbpctl_dev_b, EODSDP,
3861 BP10G_SDP6_DATA_OUT));
3862 return (((BP10G_READ_REG(pbpctl_dev_b, EODSDP))
3863 & BP10G_SDP6_DATA_IN) != 0 ? 1 : 0);
3871 static int disc_status(bpctl_dev_t *pbpctl_dev)
3874 if (pbpctl_dev->bp_caps & DISC_CAP) {
3876 if ((ctrl = disc_off_status(pbpctl_dev)) < 0)
3878 return ((ctrl == 0) ? 1 : 0);
3884 int default_pwron_disc_status(bpctl_dev_t *pbpctl_dev)
3886 if (pbpctl_dev->bp_caps & DISC_PWUP_CTL_CAP) {
3887 if (pbpctl_dev->bp_ext_ver >= 0x8)
3888 return ((((read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR)) &
3889 DFLT_PWRON_DISC_MASK) ==
3890 DFLT_PWRON_DISC_MASK) ? 1 : 0);
3895 int dis_disc_cap_status(bpctl_dev_t *pbpctl_dev)
3897 if (pbpctl_dev->bp_caps & DIS_DISC_CAP) {
3898 if (pbpctl_dev->bp_ext_ver >= 0x8)
3899 return ((((read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR)) &
3900 DIS_DISC_CAP_MASK) ==
3901 DIS_DISC_CAP_MASK) ? 1 : 0);
3906 int disc_port_status(bpctl_dev_t *pbpctl_dev)
3908 int ret = BP_NOT_CAP;
3909 bpctl_dev_t *pbpctl_dev_m;
3911 if ((is_bypass_fn(pbpctl_dev)) == 1)
3912 pbpctl_dev_m = pbpctl_dev;
3914 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
3915 if (pbpctl_dev_m == NULL)
3918 if (pbpctl_dev_m->bp_caps_ex & DISC_PORT_CAP_EX) {
3919 if (is_bypass_fn(pbpctl_dev) == 1) {
3920 return ((((read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR)) &
3921 TX_DISA_MASK) == TX_DISA_MASK) ? 1 : 0);
3923 return ((((read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR)) &
3924 TX_DISB_MASK) == TX_DISB_MASK) ? 1 : 0);
3930 int default_pwron_disc_port_status(bpctl_dev_t *pbpctl_dev)
3932 int ret = BP_NOT_CAP;
3933 bpctl_dev_t *pbpctl_dev_m;
3935 if ((is_bypass_fn(pbpctl_dev)) == 1)
3936 pbpctl_dev_m = pbpctl_dev;
3938 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
3939 if (pbpctl_dev_m == NULL)
3942 if (pbpctl_dev_m->bp_caps_ex & DISC_PORT_CAP_EX) {
3943 if (is_bypass_fn(pbpctl_dev) == 1)
3945 /* return((((read_reg(pbpctl_dev,STATUS_TAP_REG_ADDR)) & TX_DISA_MASK)==TX_DISA_MASK)?1:0); */
3948 /* return((((read_reg(pbpctl_dev,STATUS_TAP_REG_ADDR)) & TX_DISA_MASK)==TX_DISA_MASK)?1:0); */
3954 int wdt_exp_mode_status(bpctl_dev_t *pbpctl_dev)
3956 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
3957 if (pbpctl_dev->bp_ext_ver <= PXG2BPI_VER)
3958 return 0; /* bypass mode */
3959 else if (pbpctl_dev->bp_ext_ver == PXG2TBPI_VER)
3960 return 1; /* tap mode */
3961 else if (pbpctl_dev->bp_ext_ver >= PXE2TBPI_VER) {
3962 if (pbpctl_dev->bp_ext_ver >= 0x8) {
3965 STATUS_DISC_REG_ADDR)) &
3966 WDTE_DISC_BPN_MASK) == WDTE_DISC_BPN_MASK)
3969 return ((((read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR)) &
3970 WDTE_TAP_BPN_MASK) ==
3971 WDTE_TAP_BPN_MASK) ? 1 : 0);
3977 int tpl2_flag_status(bpctl_dev_t *pbpctl_dev)
3980 if (pbpctl_dev->bp_caps_ex & TPL2_CAP_EX) {
3981 return ((((read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR)) &
3982 TPL2_FLAG_MASK) == TPL2_FLAG_MASK) ? 1 : 0);
3988 int tpl_hw_status(bpctl_dev_t *pbpctl_dev)
3990 bpctl_dev_t *pbpctl_dev_b = NULL;
3992 if (!(pbpctl_dev_b = get_status_port_fn(pbpctl_dev)))
3995 if (TPL_IF_SERIES(pbpctl_dev->subdevice))
3996 return (((BPCTL_READ_REG(pbpctl_dev, CTRL)) &
3997 BPCTLI_CTRL_SWDPIN0) != 0 ? 1 : 0);
4002 int bp_wait_at_pwup_status(bpctl_dev_t *pbpctl_dev)
4004 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
4005 if (pbpctl_dev->bp_ext_ver >= 0x8)
4006 return ((((read_reg(pbpctl_dev, CONT_CONFIG_REG_ADDR)) &
4007 WAIT_AT_PWUP_MASK) ==
4008 WAIT_AT_PWUP_MASK) ? 1 : 0);
4013 int bp_hw_reset_status(bpctl_dev_t *pbpctl_dev)
4016 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
4018 if (pbpctl_dev->bp_ext_ver >= 0x8)
4019 return ((((read_reg(pbpctl_dev, CONT_CONFIG_REG_ADDR)) &
4020 EN_HW_RESET_MASK) ==
4021 EN_HW_RESET_MASK) ? 1 : 0);
4027 int std_nic_status(bpctl_dev_t *pbpctl_dev)
4031 if (pbpctl_dev->bp_caps & STD_NIC_CAP) {
4032 if (INTEL_IF_SERIES(pbpctl_dev->subdevice))
4034 if (pbpctl_dev->bp_ext_ver >= BP_FW_EXT_VER8) {
4035 return ((((read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR)) &
4036 STD_NIC_ON_MASK) == STD_NIC_ON_MASK) ? 1 : 0);
4039 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
4040 if (pbpctl_dev->bp_caps & BP_CAP) {
4042 read_reg(pbpctl_dev, STATUS_REG_ADDR);
4043 if (((!(status_val & WDT_EN_MASK))
4044 && ((status_val & STD_NIC_MASK) ==
4050 if (pbpctl_dev->bp_caps & TAP_CAP) {
4052 read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR);
4053 if ((status_val & STD_NIC_TAP_MASK) ==
4059 if (pbpctl_dev->bp_caps & TAP_CAP) {
4060 if ((disc_off_status(pbpctl_dev)))
4072 /******************************************************/
4073 /**************SW_INIT*********************************/
4074 /******************************************************/
4075 void bypass_caps_init(bpctl_dev_t *pbpctl_dev)
4077 u_int32_t ctrl_ext = 0;
4078 bpctl_dev_t *pbpctl_dev_m = NULL;
4082 if (!(INTEL_IF_SERIES(adapter->bp_device_block.subdevice))) {
4083 ret = read_reg(pbpctl_dev, VER_REG_ADDR);
4084 printk("VER_REG reg1=%x\n", ret);
4085 ret = read_reg(pbpctl_dev, PRODUCT_CAP_REG_ADDR);
4086 printk("PRODUCT_CAP reg=%x\n", ret);
4087 ret = read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR);
4088 printk("STATUS_TAP reg1=%x\n", ret);
4089 ret = read_reg(pbpctl_dev, 0x7);
4090 printk("SIG_REG reg1=%x\n", ret);
4091 ret = read_reg(pbpctl_dev, STATUS_REG_ADDR);
4092 printk("STATUS_REG_ADDR=%x\n", ret);
4093 ret = read_reg(pbpctl_dev, WDT_REG_ADDR);
4094 printk("WDT_REG_ADDR=%x\n", ret);
4095 ret = read_reg(pbpctl_dev, TMRL_REG_ADDR);
4096 printk("TMRL_REG_ADDR=%x\n", ret);
4097 ret = read_reg(pbpctl_dev, TMRH_REG_ADDR);
4098 printk("TMRH_REG_ADDR=%x\n", ret);
4101 if ((pbpctl_dev->bp_fiber5) || (pbpctl_dev->bp_10g9)) {
4102 pbpctl_dev->media_type = bp_fiber;
4103 } else if (pbpctl_dev->bp_10gb) {
4104 if (BP10GB_CX4_SERIES(pbpctl_dev->subdevice))
4105 pbpctl_dev->media_type = bp_cx4;
4107 pbpctl_dev->media_type = bp_fiber;
4111 else if (pbpctl_dev->bp_540)
4112 pbpctl_dev->media_type = bp_none;
4113 else if (!pbpctl_dev->bp_10g) {
4115 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
4116 if ((ctrl_ext & BPCTLI_CTRL_EXT_LINK_MODE_MASK) == 0x0)
4117 pbpctl_dev->media_type = bp_copper;
4119 pbpctl_dev->media_type = bp_fiber;
4122 if (BP10G_CX4_SERIES(pbpctl_dev->subdevice))
4123 pbpctl_dev->media_type = bp_cx4;
4125 pbpctl_dev->media_type = bp_fiber;
4128 if (is_bypass_fn(pbpctl_dev)) {
4130 pbpctl_dev->bp_caps |= BP_PWOFF_ON_CAP;
4131 if (pbpctl_dev->media_type == bp_fiber)
4132 pbpctl_dev->bp_caps |=
4133 (TX_CTL_CAP | TX_STATUS_CAP | TPL_CAP);
4135 if (TPL_IF_SERIES(pbpctl_dev->subdevice)) {
4136 pbpctl_dev->bp_caps |= TPL_CAP;
4139 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
4140 pbpctl_dev->bp_caps |=
4141 (BP_CAP | BP_STATUS_CAP | SW_CTL_CAP |
4142 BP_PWUP_ON_CAP | BP_PWUP_OFF_CAP | BP_PWOFF_OFF_CAP
4143 | WD_CTL_CAP | WD_STATUS_CAP | STD_NIC_CAP |
4146 pbpctl_dev->bp_ext_ver = OLD_IF_VER;
4150 if ((pbpctl_dev->bp_fw_ver == 0xff) &&
4151 OLD_IF_SERIES(pbpctl_dev->subdevice)) {
4153 pbpctl_dev->bp_caps |=
4154 (BP_CAP | BP_STATUS_CAP | BP_STATUS_CHANGE_CAP |
4155 SW_CTL_CAP | BP_PWUP_ON_CAP | WD_CTL_CAP |
4156 WD_STATUS_CAP | WD_TIMEOUT_CAP);
4158 pbpctl_dev->bp_ext_ver = OLD_IF_VER;
4163 switch (pbpctl_dev->bp_fw_ver) {
4166 pbpctl_dev->bp_ext_ver =
4168 bp_fw_ver & EXT_VER_MASK);
4172 if ((bypass_sign_check(pbpctl_dev)) !=
4174 pbpctl_dev->bp_caps = 0;
4177 pbpctl_dev->bp_ext_ver =
4179 bp_fw_ver & EXT_VER_MASK);
4184 if (pbpctl_dev->bp_ext_ver == PXG2BPI_VER)
4185 pbpctl_dev->bp_caps |=
4186 (BP_CAP | BP_STATUS_CAP | BP_STATUS_CHANGE_CAP |
4187 SW_CTL_CAP | BP_DIS_CAP | BP_DIS_STATUS_CAP |
4188 BP_PWUP_ON_CAP | BP_PWUP_OFF_CAP | BP_PWUP_CTL_CAP
4189 | WD_CTL_CAP | STD_NIC_CAP | WD_STATUS_CAP |
4191 else if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER) {
4194 pbpctl_dev->bp_caps |=
4195 (SW_CTL_CAP | WD_CTL_CAP | WD_STATUS_CAP |
4197 cap_reg = get_bp_prod_caps(pbpctl_dev);
4199 if ((cap_reg & NORMAL_UNSUPPORT_MASK) ==
4200 NORMAL_UNSUPPORT_MASK)
4201 pbpctl_dev->bp_caps |= NIC_CAP_NEG;
4203 pbpctl_dev->bp_caps |= STD_NIC_CAP;
4205 if ((normal_support(pbpctl_dev)) == 1)
4207 pbpctl_dev->bp_caps |= STD_NIC_CAP;
4210 pbpctl_dev->bp_caps |= NIC_CAP_NEG;
4211 if ((cap_reg & BYPASS_SUPPORT_MASK) ==
4212 BYPASS_SUPPORT_MASK) {
4213 pbpctl_dev->bp_caps |=
4214 (BP_CAP | BP_STATUS_CAP |
4215 BP_STATUS_CHANGE_CAP | BP_DIS_CAP |
4216 BP_DIS_STATUS_CAP | BP_PWUP_ON_CAP |
4217 BP_PWUP_OFF_CAP | BP_PWUP_CTL_CAP);
4218 if (pbpctl_dev->bp_ext_ver >= BP_FW_EXT_VER7)
4219 pbpctl_dev->bp_caps |=
4220 BP_PWOFF_ON_CAP | BP_PWOFF_OFF_CAP |
4223 if ((cap_reg & TAP_SUPPORT_MASK) == TAP_SUPPORT_MASK) {
4224 pbpctl_dev->bp_caps |=
4225 (TAP_CAP | TAP_STATUS_CAP |
4226 TAP_STATUS_CHANGE_CAP | TAP_DIS_CAP |
4227 TAP_DIS_STATUS_CAP | TAP_PWUP_ON_CAP |
4228 TAP_PWUP_OFF_CAP | TAP_PWUP_CTL_CAP);
4230 if (pbpctl_dev->bp_ext_ver >= BP_FW_EXT_VER8) {
4231 if ((cap_reg & DISC_SUPPORT_MASK) ==
4233 pbpctl_dev->bp_caps |=
4234 (DISC_CAP | DISC_DIS_CAP |
4236 if ((cap_reg & TPL2_SUPPORT_MASK) ==
4237 TPL2_SUPPORT_MASK) {
4238 pbpctl_dev->bp_caps_ex |= TPL2_CAP_EX;
4239 pbpctl_dev->bp_caps |= TPL_CAP;
4240 pbpctl_dev->bp_tpl_flag =
4241 tpl2_flag_status(pbpctl_dev);
4246 if (pbpctl_dev->bp_ext_ver >= BP_FW_EXT_VER9) {
4247 if ((cap_reg & DISC_PORT_SUPPORT_MASK) ==
4248 DISC_PORT_SUPPORT_MASK) {
4249 pbpctl_dev->bp_caps_ex |=
4251 pbpctl_dev->bp_caps |=
4252 (TX_CTL_CAP | TX_STATUS_CAP);
4258 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
4259 if ((read_reg(pbpctl_dev, STATUS_REG_ADDR)) &
4261 pbpctl_dev->wdt_status = WDT_STATUS_EN;
4263 pbpctl_dev->wdt_status = WDT_STATUS_DIS;
4266 } else if ((P2BPFI_IF_SERIES(pbpctl_dev->subdevice)) ||
4267 (PEGF5_IF_SERIES(pbpctl_dev->subdevice)) ||
4268 (PEGF80_IF_SERIES(pbpctl_dev->subdevice)) ||
4269 (BP10G9_IF_SERIES(pbpctl_dev->subdevice))) {
4270 pbpctl_dev->bp_caps |= (TX_CTL_CAP | TX_STATUS_CAP);
4272 if ((pbpctl_dev->subdevice & 0xa00) == 0xa00)
4273 pbpctl_dev->bp_caps |= (TX_CTL_CAP | TX_STATUS_CAP);
4274 if (PEG5_IF_SERIES(pbpctl_dev->subdevice))
4275 pbpctl_dev->bp_caps |= (TX_CTL_CAP | TX_STATUS_CAP);
4277 if (BP10GB_IF_SERIES(pbpctl_dev->subdevice)) {
4278 pbpctl_dev->bp_caps &= ~(TX_CTL_CAP | TX_STATUS_CAP);
4280 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
4281 if (pbpctl_dev_m != NULL) {
4283 if (pbpctl_dev_m->bp_ext_ver >= 0x9) {
4284 cap_reg = get_bp_prod_caps(pbpctl_dev_m);
4285 if ((cap_reg & DISC_PORT_SUPPORT_MASK) ==
4286 DISC_PORT_SUPPORT_MASK)
4287 pbpctl_dev->bp_caps |=
4288 (TX_CTL_CAP | TX_STATUS_CAP);
4289 pbpctl_dev->bp_caps_ex |= DISC_PORT_CAP_EX;
4294 int bypass_off_init(bpctl_dev_t *pbpctl_dev)
4298 if ((ret = cmnd_on(pbpctl_dev)) < 0)
4300 if (INTEL_IF_SERIES(pbpctl_dev->subdevice))
4301 return dis_bypass_cap(pbpctl_dev);
4302 wdt_off(pbpctl_dev);
4303 if (pbpctl_dev->bp_caps & BP_CAP)
4304 bypass_off(pbpctl_dev);
4305 if (pbpctl_dev->bp_caps & TAP_CAP)
4306 tap_off(pbpctl_dev);
4307 cmnd_off(pbpctl_dev);
4311 void remove_bypass_wd_auto(bpctl_dev_t *pbpctl_dev)
4314 bpctl_dev_t *pbpctl_dev_sl = NULL;
4317 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
4319 del_timer_sync(&pbpctl_dev->bp_timer);
4321 pbpctl_dev_sl = get_status_port_fn(pbpctl_dev);
4322 #if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,31))
4323 if (pbpctl_dev_sl && (pbpctl_dev_sl->ndev)
4324 && (pbpctl_dev_sl->ndev->hard_start_xmit)
4325 && (pbpctl_dev_sl->hard_start_xmit_save)) {
4327 pbpctl_dev_sl->ndev->hard_start_xmit =
4328 pbpctl_dev_sl->hard_start_xmit_save;
4332 if (pbpctl_dev_sl && (pbpctl_dev_sl->ndev)) {
4333 if ((pbpctl_dev_sl->ndev->netdev_ops)
4334 && (pbpctl_dev_sl->old_ops)) {
4336 pbpctl_dev_sl->ndev->netdev_ops =
4337 pbpctl_dev_sl->old_ops;
4338 pbpctl_dev_sl->old_ops = NULL;
4352 int init_bypass_wd_auto(bpctl_dev_t *pbpctl_dev)
4354 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
4355 init_timer(&pbpctl_dev->bp_timer);
4356 pbpctl_dev->bp_timer.function = &wd_reset_timer;
4357 pbpctl_dev->bp_timer.data = (unsigned long)pbpctl_dev;
4364 int bp_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
4366 bpctl_dev_t *pbpctl_dev = NULL, *pbpctl_dev_m = NULL;
4368 struct ethhdr *eth = (struct ethhdr *)skb->data;
4371 ((bpctl_dev_arr[idx_dev].ndev != NULL) && (idx_dev < device_num));
4373 if (bpctl_dev_arr[idx_dev].ndev == dev) {
4374 pbpctl_dev = &bpctl_dev_arr[idx_dev];
4380 if ((htons(ETH_P_BPTEST) == eth->h_proto)) {
4382 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
4385 if (bypass_status(pbpctl_dev_m)) {
4386 cmnd_on(pbpctl_dev_m);
4387 bypass_off(pbpctl_dev_m);
4388 cmnd_off(pbpctl_dev_m);
4390 wdt_timer_reload(pbpctl_dev_m);
4392 dev_kfree_skb_irq(skb);
4395 return pbpctl_dev->hard_start_xmit_save(skb, dev);
4399 int set_bypass_wd_auto(bpctl_dev_t *pbpctl_dev, unsigned int param)
4401 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
4402 if (pbpctl_dev->reset_time != param) {
4403 if (INTEL_IF_SERIES(pbpctl_dev->subdevice))
4404 pbpctl_dev->reset_time =
4406 WDT_AUTO_MIN_INT) ? WDT_AUTO_MIN_INT :
4409 pbpctl_dev->reset_time = param;
4411 mod_timer(&pbpctl_dev->bp_timer, jiffies);
4418 int get_bypass_wd_auto(bpctl_dev_t *pbpctl_dev)
4421 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
4422 return pbpctl_dev->reset_time;
4429 int set_bp_self_test(bpctl_dev_t *pbpctl_dev, unsigned int param)
4431 bpctl_dev_t *pbpctl_dev_sl = NULL;
4433 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
4434 pbpctl_dev->bp_self_test_flag = param == 0 ? 0 : 1;
4435 pbpctl_dev_sl = get_status_port_fn(pbpctl_dev);
4436 #if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,31))
4437 if ((pbpctl_dev_sl->ndev) &&
4438 (pbpctl_dev_sl->ndev->hard_start_xmit)) {
4440 if (pbpctl_dev->bp_self_test_flag == 1) {
4442 pbpctl_dev_sl->hard_start_xmit_save =
4443 pbpctl_dev_sl->ndev->hard_start_xmit;
4444 pbpctl_dev_sl->ndev->hard_start_xmit =
4446 } else if (pbpctl_dev_sl->hard_start_xmit_save) {
4447 pbpctl_dev_sl->ndev->hard_start_xmit =
4448 pbpctl_dev_sl->hard_start_xmit_save;
4453 if ((pbpctl_dev_sl->ndev) && (pbpctl_dev_sl->ndev->netdev_ops)) {
4455 if (pbpctl_dev->bp_self_test_flag == 1) {
4457 pbpctl_dev_sl->old_ops =
4458 pbpctl_dev_sl->ndev->netdev_ops;
4459 pbpctl_dev_sl->new_ops =
4460 *pbpctl_dev_sl->old_ops;
4461 pbpctl_dev_sl->new_ops.ndo_start_xmit =
4463 pbpctl_dev_sl->ndev->netdev_ops =
4464 &pbpctl_dev_sl->new_ops;
4466 } else if (pbpctl_dev_sl->old_ops) {
4467 pbpctl_dev_sl->ndev->netdev_ops =
4468 pbpctl_dev_sl->old_ops;
4469 pbpctl_dev_sl->old_ops = NULL;
4475 set_bypass_wd_auto(pbpctl_dev, param);
4481 int get_bp_self_test(bpctl_dev_t *pbpctl_dev)
4484 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
4485 if (pbpctl_dev->bp_self_test_flag == 1)
4486 return pbpctl_dev->reset_time;
4495 /**************************************************************/
4496 /************************* API ********************************/
4497 /**************************************************************/
4499 int is_bypass_fn(bpctl_dev_t *pbpctl_dev)
4504 return (((pbpctl_dev->func == 0) || (pbpctl_dev->func == 2)) ? 1 : 0);
4507 int set_bypass_fn(bpctl_dev_t *pbpctl_dev, int bypass_mode)
4511 if (!(pbpctl_dev->bp_caps & BP_CAP))
4513 if ((ret = cmnd_on(pbpctl_dev)) < 0)
4516 ret = bypass_off(pbpctl_dev);
4518 ret = bypass_on(pbpctl_dev);
4519 cmnd_off(pbpctl_dev);
4524 int get_bypass_fn(bpctl_dev_t *pbpctl_dev)
4526 return bypass_status(pbpctl_dev);
4529 int get_bypass_change_fn(bpctl_dev_t *pbpctl_dev)
4534 return bypass_change_status(pbpctl_dev);
4537 int set_dis_bypass_fn(bpctl_dev_t *pbpctl_dev, int dis_param)
4543 if (!(pbpctl_dev->bp_caps & BP_DIS_CAP))
4545 if ((ret = cmnd_on(pbpctl_dev)) < 0)
4548 ret = dis_bypass_cap(pbpctl_dev);
4550 ret = en_bypass_cap(pbpctl_dev);
4551 cmnd_off(pbpctl_dev);
4555 int get_dis_bypass_fn(bpctl_dev_t *pbpctl_dev)
4560 return dis_bypass_cap_status(pbpctl_dev);
4563 int set_bypass_pwoff_fn(bpctl_dev_t *pbpctl_dev, int bypass_mode)
4569 if (!(pbpctl_dev->bp_caps & BP_PWOFF_CTL_CAP))
4571 if ((ret = cmnd_on(pbpctl_dev)) < 0)
4574 ret = bypass_state_pwroff(pbpctl_dev);
4576 ret = normal_state_pwroff(pbpctl_dev);
4577 cmnd_off(pbpctl_dev);
4581 int get_bypass_pwoff_fn(bpctl_dev_t *pbpctl_dev)
4586 return default_pwroff_status(pbpctl_dev);
4589 int set_bypass_pwup_fn(bpctl_dev_t *pbpctl_dev, int bypass_mode)
4595 if (!(pbpctl_dev->bp_caps & BP_PWUP_CTL_CAP))
4597 if ((ret = cmnd_on(pbpctl_dev)) < 0)
4600 ret = bypass_state_pwron(pbpctl_dev);
4602 ret = normal_state_pwron(pbpctl_dev);
4603 cmnd_off(pbpctl_dev);
4607 int get_bypass_pwup_fn(bpctl_dev_t *pbpctl_dev)
4612 return default_pwron_status(pbpctl_dev);
4615 int set_bypass_wd_fn(bpctl_dev_t *pbpctl_dev, int timeout)
4621 if (!(pbpctl_dev->bp_caps & WD_CTL_CAP))
4624 if ((ret = cmnd_on(pbpctl_dev)) < 0)
4627 ret = wdt_off(pbpctl_dev);
4629 wdt_on(pbpctl_dev, timeout);
4630 ret = pbpctl_dev->bypass_timer_interval;
4632 cmnd_off(pbpctl_dev);
4636 int get_bypass_wd_fn(bpctl_dev_t *pbpctl_dev, int *timeout)
4641 return wdt_programmed(pbpctl_dev, timeout);
4644 int get_wd_expire_time_fn(bpctl_dev_t *pbpctl_dev, int *time_left)
4649 return wdt_timer(pbpctl_dev, time_left);
4652 int reset_bypass_wd_timer_fn(bpctl_dev_t *pbpctl_dev)
4657 return wdt_timer_reload(pbpctl_dev);
4660 int get_wd_set_caps_fn(bpctl_dev_t *pbpctl_dev)
4664 unsigned int step_value = TIMEOUT_MAX_STEP + 1, bit_cnt = 0;
4668 if (INTEL_IF_SERIES(pbpctl_dev->subdevice))
4671 while ((step_value >>= 1))
4674 if (is_bypass_fn(pbpctl_dev)) {
4676 WD_STEP_COUNT_MASK(bit_cnt) | WDT_STEP_TIME |
4677 WD_MIN_TIME_MASK(TIMEOUT_UNIT / 100);
4684 int set_std_nic_fn(bpctl_dev_t *pbpctl_dev, int nic_mode)
4690 if (!(pbpctl_dev->bp_caps & STD_NIC_CAP))
4693 if ((ret = cmnd_on(pbpctl_dev)) < 0)
4696 ret = std_nic_on(pbpctl_dev);
4698 ret = std_nic_off(pbpctl_dev);
4699 cmnd_off(pbpctl_dev);
4703 int get_std_nic_fn(bpctl_dev_t *pbpctl_dev)
4708 return std_nic_status(pbpctl_dev);
4711 int set_tap_fn(bpctl_dev_t *pbpctl_dev, int tap_mode)
4716 if ((pbpctl_dev->bp_caps & TAP_CAP) && ((cmnd_on(pbpctl_dev)) >= 0)) {
4718 tap_off(pbpctl_dev);
4721 cmnd_off(pbpctl_dev);
4727 int get_tap_fn(bpctl_dev_t *pbpctl_dev)
4732 return tap_status(pbpctl_dev);
4735 int set_tap_pwup_fn(bpctl_dev_t *pbpctl_dev, int tap_mode)
4741 if ((pbpctl_dev->bp_caps & TAP_PWUP_CTL_CAP)
4742 && ((cmnd_on(pbpctl_dev)) >= 0)) {
4744 ret = tap_state_pwron(pbpctl_dev);
4746 ret = normal_state_pwron(pbpctl_dev);
4747 cmnd_off(pbpctl_dev);
4753 int get_tap_pwup_fn(bpctl_dev_t *pbpctl_dev)
4759 if ((ret = default_pwron_tap_status(pbpctl_dev)) < 0)
4761 return ((ret == 0) ? 1 : 0);
4764 int get_tap_change_fn(bpctl_dev_t *pbpctl_dev)
4769 return tap_change_status(pbpctl_dev);
4772 int set_dis_tap_fn(bpctl_dev_t *pbpctl_dev, int dis_param)
4778 if ((pbpctl_dev->bp_caps & TAP_DIS_CAP) && ((cmnd_on(pbpctl_dev)) >= 0)) {
4780 ret = dis_tap_cap(pbpctl_dev);
4782 ret = en_tap_cap(pbpctl_dev);
4783 cmnd_off(pbpctl_dev);
4789 int get_dis_tap_fn(bpctl_dev_t *pbpctl_dev)
4794 return dis_tap_cap_status(pbpctl_dev);
4797 int set_disc_fn(bpctl_dev_t *pbpctl_dev, int disc_mode)
4802 if ((pbpctl_dev->bp_caps & DISC_CAP) && ((cmnd_on(pbpctl_dev)) >= 0)) {
4804 disc_off(pbpctl_dev);
4806 disc_on(pbpctl_dev);
4807 cmnd_off(pbpctl_dev);
4814 int get_disc_fn(bpctl_dev_t *pbpctl_dev)
4820 ret = disc_status(pbpctl_dev);
4825 int set_disc_pwup_fn(bpctl_dev_t *pbpctl_dev, int disc_mode)
4831 if ((pbpctl_dev->bp_caps & DISC_PWUP_CTL_CAP)
4832 && ((cmnd_on(pbpctl_dev)) >= 0)) {
4834 ret = disc_state_pwron(pbpctl_dev);
4836 ret = normal_state_pwron(pbpctl_dev);
4837 cmnd_off(pbpctl_dev);
4843 int get_disc_pwup_fn(bpctl_dev_t *pbpctl_dev)
4849 ret = default_pwron_disc_status(pbpctl_dev);
4850 return (ret == 0 ? 1 : (ret < 0 ? BP_NOT_CAP : 0));
4853 int get_disc_change_fn(bpctl_dev_t *pbpctl_dev)
4859 ret = disc_change_status(pbpctl_dev);
4863 int set_dis_disc_fn(bpctl_dev_t *pbpctl_dev, int dis_param)
4869 if ((pbpctl_dev->bp_caps & DISC_DIS_CAP)
4870 && ((cmnd_on(pbpctl_dev)) >= 0)) {
4872 ret = dis_disc_cap(pbpctl_dev);
4874 ret = en_disc_cap(pbpctl_dev);
4875 cmnd_off(pbpctl_dev);
4881 int get_dis_disc_fn(bpctl_dev_t *pbpctl_dev)
4887 ret = dis_disc_cap_status(pbpctl_dev);
4892 int set_disc_port_fn(bpctl_dev_t *pbpctl_dev, int disc_mode)
4894 int ret = BP_NOT_CAP;
4899 ret = disc_port_off(pbpctl_dev);
4901 ret = disc_port_on(pbpctl_dev);
4906 int get_disc_port_fn(bpctl_dev_t *pbpctl_dev)
4911 return disc_port_status(pbpctl_dev);
4914 int set_disc_port_pwup_fn(bpctl_dev_t *pbpctl_dev, int disc_mode)
4916 int ret = BP_NOT_CAP;
4921 ret = normal_port_state_pwron(pbpctl_dev);
4923 ret = disc_port_state_pwron(pbpctl_dev);
4928 int get_disc_port_pwup_fn(bpctl_dev_t *pbpctl_dev)
4934 if ((ret = default_pwron_disc_port_status(pbpctl_dev)) < 0)
4936 return ((ret == 0) ? 1 : 0);
4939 int get_wd_exp_mode_fn(bpctl_dev_t *pbpctl_dev)
4944 return wdt_exp_mode_status(pbpctl_dev);
4947 int set_wd_exp_mode_fn(bpctl_dev_t *pbpctl_dev, int param)
4952 return wdt_exp_mode(pbpctl_dev, param);
4955 int reset_cont_fn(bpctl_dev_t *pbpctl_dev)
4961 if ((ret = cmnd_on(pbpctl_dev)) < 0)
4963 return reset_cont(pbpctl_dev);
4966 int set_tx_fn(bpctl_dev_t *pbpctl_dev, int tx_state)
4969 bpctl_dev_t *pbpctl_dev_b = NULL;
4973 if ((pbpctl_dev->bp_caps & TPL_CAP) &&
4974 (pbpctl_dev->bp_caps & SW_CTL_CAP)) {
4975 if ((pbpctl_dev->bp_tpl_flag))
4977 } else if ((pbpctl_dev_b = get_master_port_fn(pbpctl_dev))) {
4978 if ((pbpctl_dev_b->bp_caps & TPL_CAP) &&
4979 (pbpctl_dev_b->bp_tpl_flag))
4982 return set_tx(pbpctl_dev, tx_state);
4985 int set_bp_force_link_fn(int dev_num, int tx_state)
4987 static bpctl_dev_t *bpctl_dev_curr;
4989 if ((dev_num < 0) || (dev_num > device_num)
4990 || (bpctl_dev_arr[dev_num].pdev == NULL))
4992 bpctl_dev_curr = &bpctl_dev_arr[dev_num];
4994 return set_bp_force_link(bpctl_dev_curr, tx_state);
4997 int set_wd_autoreset_fn(bpctl_dev_t *pbpctl_dev, int param)
5002 return set_bypass_wd_auto(pbpctl_dev, param);
5005 int get_wd_autoreset_fn(bpctl_dev_t *pbpctl_dev)
5010 return get_bypass_wd_auto(pbpctl_dev);
5014 int set_bp_self_test_fn(bpctl_dev_t *pbpctl_dev, int param)
5019 return set_bp_self_test(pbpctl_dev, param);
5022 int get_bp_self_test_fn(bpctl_dev_t *pbpctl_dev)
5027 return get_bp_self_test(pbpctl_dev);
5032 int get_bypass_caps_fn(bpctl_dev_t *pbpctl_dev)
5037 return pbpctl_dev->bp_caps;
5041 int get_bypass_slave_fn(bpctl_dev_t *pbpctl_dev, bpctl_dev_t **pbpctl_dev_out)
5047 if ((pbpctl_dev->func == 0) || (pbpctl_dev->func == 2)) {
5049 ((bpctl_dev_arr[idx_dev].pdev != NULL)
5050 && (idx_dev < device_num)); idx_dev++) {
5051 if ((bpctl_dev_arr[idx_dev].bus == pbpctl_dev->bus)
5052 && (bpctl_dev_arr[idx_dev].slot ==
5053 pbpctl_dev->slot)) {
5054 if ((pbpctl_dev->func == 0)
5055 && (bpctl_dev_arr[idx_dev].func == 1)) {
5057 &bpctl_dev_arr[idx_dev];
5060 if ((pbpctl_dev->func == 2) &&
5061 (bpctl_dev_arr[idx_dev].func == 3)) {
5063 &bpctl_dev_arr[idx_dev];
5073 int is_bypass(bpctl_dev_t *pbpctl_dev)
5078 if ((pbpctl_dev->func == 0) || (pbpctl_dev->func == 2))
5084 int get_tx_fn(bpctl_dev_t *pbpctl_dev)
5086 bpctl_dev_t *pbpctl_dev_b = NULL;
5090 if ((pbpctl_dev->bp_caps & TPL_CAP) &&
5091 (pbpctl_dev->bp_caps & SW_CTL_CAP)) {
5092 if ((pbpctl_dev->bp_tpl_flag))
5094 } else if ((pbpctl_dev_b = get_master_port_fn(pbpctl_dev))) {
5095 if ((pbpctl_dev_b->bp_caps & TPL_CAP) &&
5096 (pbpctl_dev_b->bp_tpl_flag))
5099 return tx_status(pbpctl_dev);
5102 int get_bp_force_link_fn(int dev_num)
5104 static bpctl_dev_t *bpctl_dev_curr;
5106 if ((dev_num < 0) || (dev_num > device_num)
5107 || (bpctl_dev_arr[dev_num].pdev == NULL))
5109 bpctl_dev_curr = &bpctl_dev_arr[dev_num];
5111 return bp_force_link_status(bpctl_dev_curr);
5114 static int get_bypass_link_status(bpctl_dev_t *pbpctl_dev)
5119 if (pbpctl_dev->media_type == bp_fiber)
5120 return ((BPCTL_READ_REG(pbpctl_dev, CTRL) &
5121 BPCTLI_CTRL_SWDPIN1));
5123 return ((BPCTL_READ_REG(pbpctl_dev, STATUS) &
5128 static void bp_tpl_timer_fn(unsigned long param)
5130 bpctl_dev_t *pbpctl_dev = (bpctl_dev_t *) param;
5131 uint32_t link1, link2;
5132 bpctl_dev_t *pbpctl_dev_b = NULL;
5134 if (!(pbpctl_dev_b = get_status_port_fn(pbpctl_dev)))
5137 if (!pbpctl_dev->bp_tpl_flag) {
5138 set_tx(pbpctl_dev_b, 1);
5139 set_tx(pbpctl_dev, 1);
5142 link1 = get_bypass_link_status(pbpctl_dev);
5144 link2 = get_bypass_link_status(pbpctl_dev_b);
5145 if ((link1) && (tx_status(pbpctl_dev))) {
5146 if ((!link2) && (tx_status(pbpctl_dev_b))) {
5147 set_tx(pbpctl_dev, 0);
5148 } else if (!tx_status(pbpctl_dev_b)) {
5149 set_tx(pbpctl_dev_b, 1);
5151 } else if ((!link1) && (tx_status(pbpctl_dev))) {
5152 if ((link2) && (tx_status(pbpctl_dev_b))) {
5153 set_tx(pbpctl_dev_b, 0);
5155 } else if ((link1) && (!tx_status(pbpctl_dev))) {
5156 if ((link2) && (tx_status(pbpctl_dev_b))) {
5157 set_tx(pbpctl_dev, 1);
5159 } else if ((!link1) && (!tx_status(pbpctl_dev))) {
5160 if ((link2) && (tx_status(pbpctl_dev_b))) {
5161 set_tx(pbpctl_dev, 1);
5165 mod_timer(&pbpctl_dev->bp_tpl_timer, jiffies + BP_LINK_MON_DELAY * HZ);
5168 void remove_bypass_tpl_auto(bpctl_dev_t *pbpctl_dev)
5170 bpctl_dev_t *pbpctl_dev_b = NULL;
5173 pbpctl_dev_b = get_status_port_fn(pbpctl_dev);
5175 if (pbpctl_dev->bp_caps & TPL_CAP) {
5176 del_timer_sync(&pbpctl_dev->bp_tpl_timer);
5177 pbpctl_dev->bp_tpl_flag = 0;
5178 pbpctl_dev_b = get_status_port_fn(pbpctl_dev);
5180 set_tx(pbpctl_dev_b, 1);
5181 set_tx(pbpctl_dev, 1);
5186 int init_bypass_tpl_auto(bpctl_dev_t *pbpctl_dev)
5190 if (pbpctl_dev->bp_caps & TPL_CAP) {
5191 init_timer(&pbpctl_dev->bp_tpl_timer);
5192 pbpctl_dev->bp_tpl_timer.function = &bp_tpl_timer_fn;
5193 pbpctl_dev->bp_tpl_timer.data = (unsigned long)pbpctl_dev;
5199 int set_bypass_tpl_auto(bpctl_dev_t *pbpctl_dev, unsigned int param)
5203 if (pbpctl_dev->bp_caps & TPL_CAP) {
5204 if ((param) && (!pbpctl_dev->bp_tpl_flag)) {
5205 pbpctl_dev->bp_tpl_flag = param;
5206 mod_timer(&pbpctl_dev->bp_tpl_timer, jiffies + 1);
5209 if ((!param) && (pbpctl_dev->bp_tpl_flag))
5210 remove_bypass_tpl_auto(pbpctl_dev);
5217 int get_bypass_tpl_auto(bpctl_dev_t *pbpctl_dev)
5221 if (pbpctl_dev->bp_caps & TPL_CAP) {
5222 return pbpctl_dev->bp_tpl_flag;
5227 int set_tpl_fn(bpctl_dev_t *pbpctl_dev, int tpl_mode)
5230 bpctl_dev_t *pbpctl_dev_b = NULL;
5234 pbpctl_dev_b = get_status_port_fn(pbpctl_dev);
5236 if (pbpctl_dev->bp_caps & TPL_CAP) {
5238 if ((pbpctl_dev_b = get_status_port_fn(pbpctl_dev)))
5239 set_tx(pbpctl_dev_b, 1);
5240 set_tx(pbpctl_dev, 1);
5242 if ((TPL_IF_SERIES(pbpctl_dev->subdevice)) ||
5243 (pbpctl_dev->bp_caps_ex & TPL2_CAP_EX)) {
5244 pbpctl_dev->bp_tpl_flag = tpl_mode;
5246 tpl_hw_off(pbpctl_dev);
5248 tpl_hw_on(pbpctl_dev);
5250 set_bypass_tpl_auto(pbpctl_dev, tpl_mode);
5256 int get_tpl_fn(bpctl_dev_t *pbpctl_dev)
5258 int ret = BP_NOT_CAP;
5262 if (pbpctl_dev->bp_caps & TPL_CAP) {
5263 if (pbpctl_dev->bp_caps_ex & TPL2_CAP_EX)
5264 return tpl2_flag_status(pbpctl_dev);
5265 ret = pbpctl_dev->bp_tpl_flag;
5270 int set_bp_wait_at_pwup_fn(bpctl_dev_t *pbpctl_dev, int tap_mode)
5275 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
5276 /* bp_lock(pbp_device_block); */
5277 cmnd_on(pbpctl_dev);
5279 bp_wait_at_pwup_dis(pbpctl_dev);
5281 bp_wait_at_pwup_en(pbpctl_dev);
5282 cmnd_off(pbpctl_dev);
5284 /* bp_unlock(pbp_device_block); */
5290 int get_bp_wait_at_pwup_fn(bpctl_dev_t *pbpctl_dev)
5296 /* bp_lock(pbp_device_block); */
5297 ret = bp_wait_at_pwup_status(pbpctl_dev);
5298 /* bp_unlock(pbp_device_block); */
5303 int set_bp_hw_reset_fn(bpctl_dev_t *pbpctl_dev, int tap_mode)
5308 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
5309 /* bp_lock(pbp_device_block); */
5310 cmnd_on(pbpctl_dev);
5313 bp_hw_reset_dis(pbpctl_dev);
5315 bp_hw_reset_en(pbpctl_dev);
5316 cmnd_off(pbpctl_dev);
5317 /* bp_unlock(pbp_device_block); */
5323 int get_bp_hw_reset_fn(bpctl_dev_t *pbpctl_dev)
5329 /* bp_lock(pbp_device_block); */
5330 ret = bp_hw_reset_status(pbpctl_dev);
5332 /* bp_unlock(pbp_device_block); */
5338 int get_bypass_info_fn(bpctl_dev_t *pbpctl_dev, char *dev_name,
5343 if (!is_bypass_fn(pbpctl_dev))
5345 strcpy(dev_name, pbpctl_dev->name);
5346 *add_param = pbpctl_dev->bp_fw_ver;
5350 int get_dev_idx_bsf(int bus, int slot, int func)
5354 ((bpctl_dev_arr[idx_dev].pdev != NULL) && (idx_dev < device_num));
5356 if ((bus == bpctl_dev_arr[idx_dev].bus)
5357 && (slot == bpctl_dev_arr[idx_dev].slot)
5358 && (func == bpctl_dev_arr[idx_dev].func))
5365 static void str_low(char *str)
5369 for (i = 0; i < strlen(str); i++)
5370 if ((str[i] >= 65) && (str[i] <= 90))
5374 static unsigned long str_to_hex(char *p)
5376 unsigned long hex = 0;
5377 unsigned long length = strlen(p), shift = 0;
5378 unsigned char dig = 0;
5388 dig = dig < 'a' ? (dig - '0') : (dig - 'a' + 0xa);
5389 hex |= (dig << shift);
5395 static int get_dev_idx(int ifindex)
5400 ((bpctl_dev_arr[idx_dev].pdev != NULL) && (idx_dev < device_num));
5402 if (ifindex == bpctl_dev_arr[idx_dev].ifindex)
5409 static bpctl_dev_t *get_dev_idx_p(int ifindex)
5414 ((bpctl_dev_arr[idx_dev].pdev != NULL) && (idx_dev < device_num));
5416 if (ifindex == bpctl_dev_arr[idx_dev].ifindex)
5417 return &bpctl_dev_arr[idx_dev];
5423 static void if_scan_init(void)
5426 struct net_device *dev;
5428 /* rcu_read_lock(); */
5430 /* rcu_read_lock(); */
5432 #if (LINUX_VERSION_CODE >= 0x020618)
5433 for_each_netdev(&init_net, dev)
5434 #elif (LINUX_VERSION_CODE >= 0x20616)
5435 for_each_netdev(dev)
5437 for (dev = dev_base; dev; dev = dev->next)
5441 struct ethtool_drvinfo drvinfo;
5446 int bus = 0, slot = 0, func = 0;
5447 ifindex = dev->ifindex;
5450 memset(&drvinfo, 0, sizeof(struct ethtool_drvinfo));
5452 if (dev->ethtool_ops && dev->ethtool_ops->get_drvinfo) {
5453 memset(&drvinfo, 0, sizeof(drvinfo));
5454 dev->ethtool_ops->get_drvinfo(dev, &drvinfo);
5457 if (!drvinfo.bus_info)
5459 if (!strcmp(drvinfo.bus_info, "N/A"))
5461 memcpy(&cbuf, drvinfo.bus_info, 32);
5464 while (*buf++ != ':') ;
5465 for (i = 0; i < 10; i++, buf++) {
5472 bus = str_to_hex(res);
5475 for (i = 0; i < 10; i++, buf++) {
5482 slot = str_to_hex(res);
5483 func = str_to_hex(buf);
5484 idx_dev = get_dev_idx_bsf(bus, slot, func);
5486 if (idx_dev != -1) {
5488 bpctl_dev_arr[idx_dev].ifindex = ifindex;
5489 bpctl_dev_arr[idx_dev].ndev = dev;
5495 /* rtnl_unlock(); */
5496 /* rcu_read_unlock(); */
5500 #if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30))
5501 static int device_ioctl(struct inode *inode, /* see include/linux/fs.h */
5502 struct file *file, /* ditto */
5503 unsigned int ioctl_num, /* number and param for ioctl */
5504 unsigned long ioctl_param)
5506 static long device_ioctl(struct file *file, /* ditto */
5507 unsigned int ioctl_num, /* number and param for ioctl */
5508 unsigned long ioctl_param)
5511 struct bpctl_cmd bpctl_cmd;
5513 bpctl_dev_t *pbpctl_dev_out;
5514 void __user *argp = (void __user *)ioctl_param;
5516 unsigned long flags;
5518 static bpctl_dev_t *pbpctl_dev;
5520 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30))
5521 /* lock_kernel(); */
5524 /* local_irq_save(flags); */
5525 /* if(!spin_trylock_irqsave(&bpvm_lock)){
5526 local_irq_restore(flags);
5531 /* spin_lock_irqsave(&bpvm_lock, flags); */
5534 * Switch according to the ioctl called
5536 if (ioctl_num == IOCTL_TX_MSG(IF_SCAN)) {
5541 if (copy_from_user(&bpctl_cmd, argp, sizeof(struct bpctl_cmd))) {
5547 if (ioctl_num == IOCTL_TX_MSG(GET_DEV_NUM)) {
5548 bpctl_cmd.out_param[0] = device_num;
5550 (argp, (void *)&bpctl_cmd, sizeof(struct bpctl_cmd))) {
5559 /* preempt_disable(); */
5560 local_irq_save(flags);
5561 if (!spin_trylock(&bpvm_lock)) {
5562 local_irq_restore(flags);
5567 /* preempt_disable();
5569 spin_lock_irqsave(&bpvm_lock, flags);
5571 if ((bpctl_cmd.in_param[5]) ||
5572 (bpctl_cmd.in_param[6]) || (bpctl_cmd.in_param[7]))
5573 dev_idx = get_dev_idx_bsf(bpctl_cmd.in_param[5],
5574 bpctl_cmd.in_param[6],
5575 bpctl_cmd.in_param[7]);
5576 else if (bpctl_cmd.in_param[1] == 0)
5577 dev_idx = bpctl_cmd.in_param[0];
5579 dev_idx = get_dev_idx(bpctl_cmd.in_param[1]);
5581 if (dev_idx < 0 || dev_idx > device_num) {
5583 preempt_enable(); */
5585 /* preempt_enable();
5586 rcu_read_unlock(); */
5587 spin_unlock_irqrestore(&bpvm_lock, flags);
5591 bpctl_cmd.out_param[0] = bpctl_dev_arr[dev_idx].bus;
5592 bpctl_cmd.out_param[1] = bpctl_dev_arr[dev_idx].slot;
5593 bpctl_cmd.out_param[2] = bpctl_dev_arr[dev_idx].func;
5594 bpctl_cmd.out_param[3] = bpctl_dev_arr[dev_idx].ifindex;
5596 if ((bpctl_dev_arr[dev_idx].bp_10gb)
5597 && (!(bpctl_dev_arr[dev_idx].ifindex))) {
5598 printk("Please load network driver for %s adapter!\n",
5599 bpctl_dev_arr[dev_idx].name);
5600 bpctl_cmd.status = -1;
5602 /* preempt_enable(); */
5603 /* rcu_read_unlock(); */
5604 spin_unlock_irqrestore(&bpvm_lock, flags);
5608 if ((bpctl_dev_arr[dev_idx].bp_10gb) && (bpctl_dev_arr[dev_idx].ndev)) {
5609 if (!(bpctl_dev_arr[dev_idx].ndev->flags & IFF_UP)) {
5610 if (!(bpctl_dev_arr[dev_idx].ndev->flags & IFF_UP)) {
5612 ("Please bring up network interfaces for %s adapter!\n",
5613 bpctl_dev_arr[dev_idx].name);
5614 bpctl_cmd.status = -1;
5616 /* preempt_enable(); */
5617 /* rcu_read_unlock(); */
5618 spin_unlock_irqrestore(&bpvm_lock, flags);
5625 if ((dev_idx < 0) || (dev_idx > device_num)
5626 || (bpctl_dev_arr[dev_idx].pdev == NULL)) {
5627 bpctl_cmd.status = -1;
5631 pbpctl_dev = &bpctl_dev_arr[dev_idx];
5633 switch (ioctl_num) {
5634 case IOCTL_TX_MSG(SET_BYPASS_PWOFF):
5636 set_bypass_pwoff_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5639 case IOCTL_TX_MSG(GET_BYPASS_PWOFF):
5640 bpctl_cmd.status = get_bypass_pwoff_fn(pbpctl_dev);
5643 case IOCTL_TX_MSG(SET_BYPASS_PWUP):
5645 set_bypass_pwup_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5648 case IOCTL_TX_MSG(GET_BYPASS_PWUP):
5649 bpctl_cmd.status = get_bypass_pwup_fn(pbpctl_dev);
5652 case IOCTL_TX_MSG(SET_BYPASS_WD):
5654 set_bypass_wd_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5657 case IOCTL_TX_MSG(GET_BYPASS_WD):
5659 get_bypass_wd_fn(pbpctl_dev, (int *)&(bpctl_cmd.data[0]));
5662 case IOCTL_TX_MSG(GET_WD_EXPIRE_TIME):
5664 get_wd_expire_time_fn(pbpctl_dev,
5665 (int *)&(bpctl_cmd.data[0]));
5668 case IOCTL_TX_MSG(RESET_BYPASS_WD_TIMER):
5669 bpctl_cmd.status = reset_bypass_wd_timer_fn(pbpctl_dev);
5672 case IOCTL_TX_MSG(GET_WD_SET_CAPS):
5673 bpctl_cmd.status = get_wd_set_caps_fn(pbpctl_dev);
5676 case IOCTL_TX_MSG(SET_STD_NIC):
5678 set_std_nic_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5681 case IOCTL_TX_MSG(GET_STD_NIC):
5682 bpctl_cmd.status = get_std_nic_fn(pbpctl_dev);
5685 case IOCTL_TX_MSG(SET_TAP):
5687 set_tap_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5690 case IOCTL_TX_MSG(GET_TAP):
5691 bpctl_cmd.status = get_tap_fn(pbpctl_dev);
5694 case IOCTL_TX_MSG(GET_TAP_CHANGE):
5695 bpctl_cmd.status = get_tap_change_fn(pbpctl_dev);
5698 case IOCTL_TX_MSG(SET_DIS_TAP):
5700 set_dis_tap_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5703 case IOCTL_TX_MSG(GET_DIS_TAP):
5704 bpctl_cmd.status = get_dis_tap_fn(pbpctl_dev);
5707 case IOCTL_TX_MSG(SET_TAP_PWUP):
5709 set_tap_pwup_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5712 case IOCTL_TX_MSG(GET_TAP_PWUP):
5713 bpctl_cmd.status = get_tap_pwup_fn(pbpctl_dev);
5716 case IOCTL_TX_MSG(SET_WD_EXP_MODE):
5718 set_wd_exp_mode_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5721 case IOCTL_TX_MSG(GET_WD_EXP_MODE):
5722 bpctl_cmd.status = get_wd_exp_mode_fn(pbpctl_dev);
5725 case IOCTL_TX_MSG(GET_DIS_BYPASS):
5726 bpctl_cmd.status = get_dis_bypass_fn(pbpctl_dev);
5729 case IOCTL_TX_MSG(SET_DIS_BYPASS):
5731 set_dis_bypass_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5734 case IOCTL_TX_MSG(GET_BYPASS_CHANGE):
5735 bpctl_cmd.status = get_bypass_change_fn(pbpctl_dev);
5738 case IOCTL_TX_MSG(GET_BYPASS):
5739 bpctl_cmd.status = get_bypass_fn(pbpctl_dev);
5742 case IOCTL_TX_MSG(SET_BYPASS):
5744 set_bypass_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5747 case IOCTL_TX_MSG(GET_BYPASS_CAPS):
5748 bpctl_cmd.status = get_bypass_caps_fn(pbpctl_dev);
5749 /*preempt_enable(); */
5750 /*rcu_read_unlock();*/
5751 spin_unlock_irqrestore(&bpvm_lock, flags);
5753 (argp, (void *)&bpctl_cmd, sizeof(struct bpctl_cmd))) {
5754 /*unlock_bpctl(); */
5755 /*preempt_enable(); */
5761 case IOCTL_TX_MSG(GET_BYPASS_SLAVE):
5763 get_bypass_slave_fn(pbpctl_dev, &pbpctl_dev_out);
5764 if (bpctl_cmd.status == 1) {
5765 bpctl_cmd.out_param[4] = pbpctl_dev_out->bus;
5766 bpctl_cmd.out_param[5] = pbpctl_dev_out->slot;
5767 bpctl_cmd.out_param[6] = pbpctl_dev_out->func;
5768 bpctl_cmd.out_param[7] = pbpctl_dev_out->ifindex;
5772 case IOCTL_TX_MSG(IS_BYPASS):
5773 bpctl_cmd.status = is_bypass(pbpctl_dev);
5775 case IOCTL_TX_MSG(SET_TX):
5776 bpctl_cmd.status = set_tx_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5778 case IOCTL_TX_MSG(GET_TX):
5779 bpctl_cmd.status = get_tx_fn(pbpctl_dev);
5781 case IOCTL_TX_MSG(SET_WD_AUTORESET):
5783 set_wd_autoreset_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5786 case IOCTL_TX_MSG(GET_WD_AUTORESET):
5788 bpctl_cmd.status = get_wd_autoreset_fn(pbpctl_dev);
5790 case IOCTL_TX_MSG(SET_DISC):
5792 set_disc_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5794 case IOCTL_TX_MSG(GET_DISC):
5795 bpctl_cmd.status = get_disc_fn(pbpctl_dev);
5797 case IOCTL_TX_MSG(GET_DISC_CHANGE):
5798 bpctl_cmd.status = get_disc_change_fn(pbpctl_dev);
5800 case IOCTL_TX_MSG(SET_DIS_DISC):
5802 set_dis_disc_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5804 case IOCTL_TX_MSG(GET_DIS_DISC):
5805 bpctl_cmd.status = get_dis_disc_fn(pbpctl_dev);
5807 case IOCTL_TX_MSG(SET_DISC_PWUP):
5809 set_disc_pwup_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5811 case IOCTL_TX_MSG(GET_DISC_PWUP):
5812 bpctl_cmd.status = get_disc_pwup_fn(pbpctl_dev);
5815 case IOCTL_TX_MSG(GET_BYPASS_INFO):
5818 get_bypass_info_fn(pbpctl_dev, (char *)&bpctl_cmd.data,
5819 (char *)&bpctl_cmd.out_param[4]);
5822 case IOCTL_TX_MSG(SET_TPL):
5824 set_tpl_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5827 case IOCTL_TX_MSG(GET_TPL):
5828 bpctl_cmd.status = get_tpl_fn(pbpctl_dev);
5830 case IOCTL_TX_MSG(SET_BP_WAIT_AT_PWUP):
5832 set_bp_wait_at_pwup_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5835 case IOCTL_TX_MSG(GET_BP_WAIT_AT_PWUP):
5836 bpctl_cmd.status = get_bp_wait_at_pwup_fn(pbpctl_dev);
5838 case IOCTL_TX_MSG(SET_BP_HW_RESET):
5840 set_bp_hw_reset_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5843 case IOCTL_TX_MSG(GET_BP_HW_RESET):
5844 bpctl_cmd.status = get_bp_hw_reset_fn(pbpctl_dev);
5847 case IOCTL_TX_MSG(SET_BP_SELF_TEST):
5849 set_bp_self_test_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5852 case IOCTL_TX_MSG(GET_BP_SELF_TEST):
5853 bpctl_cmd.status = get_bp_self_test_fn(pbpctl_dev);
5858 case IOCTL_TX_MSG(SET_DISC_PORT):
5860 set_disc_port_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5863 case IOCTL_TX_MSG(GET_DISC_PORT):
5864 bpctl_cmd.status = get_disc_port_fn(pbpctl_dev);
5867 case IOCTL_TX_MSG(SET_DISC_PORT_PWUP):
5869 set_disc_port_pwup_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5872 case IOCTL_TX_MSG(GET_DISC_PORT_PWUP):
5873 bpctl_cmd.status = get_disc_port_pwup_fn(pbpctl_dev);
5876 case IOCTL_TX_MSG(SET_BP_FORCE_LINK):
5878 set_bp_force_link_fn(dev_idx, bpctl_cmd.in_param[2]);
5881 case IOCTL_TX_MSG(GET_BP_FORCE_LINK):
5882 bpctl_cmd.status = get_bp_force_link_fn(dev_idx);
5886 /* unlock_bpctl(); */
5889 /* preempt_enable(); */
5890 /* rcu_read_unlock();*/
5891 spin_unlock_irqrestore(&bpvm_lock, flags);
5894 /* unlock_bpctl(); */
5895 /* preempt_enable(); */
5897 /* rcu_read_unlock(); */
5898 spin_unlock_irqrestore(&bpvm_lock, flags);
5899 if (copy_to_user(argp, (void *)&bpctl_cmd, sizeof(struct bpctl_cmd)))
5903 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30))
5904 /* unlock_kernel(); */
5906 /* spin_unlock_irqrestore(&bpvm_lock, flags); */
5908 /* unlock_kernel(); */
5912 struct file_operations Fops = {
5913 .owner = THIS_MODULE,
5914 #if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30))
5915 .ioctl = device_ioctl,
5917 .unlocked_ioctl = device_ioctl,
5920 .open = device_open,
5921 .release = device_release, /* a.k.a. close */
5925 #define PCI_DEVICE(vend,dev) \
5926 .vendor = (vend), .device = (dev), \
5927 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
5930 #define SILICOM_E1000BP_ETHERNET_DEVICE(device_id) {\
5931 PCI_DEVICE(SILICOM_VID, device_id)}
6093 typedef struct _bpmod_info_t {
6094 unsigned int vendor;
6095 unsigned int device;
6096 unsigned int subvendor;
6097 unsigned int subdevice;
6103 typedef struct _dev_desc {
6107 dev_desc_t dev_desc[] = {
6108 {"Silicom Bypass PXG2BPFI-SD series adapter"},
6109 {"Silicom Bypass PXG2BPFIL-SD series adapter"},
6110 {"Silicom Bypass PXG2BPFILX-SD series adapter"},
6111 {"Silicom Bypass PXG2BPFILLX-SD series adapter"},
6112 {"Silicom Bypass PXG2BPI-SD series adapter"},
6113 {"Silicom Bypass PXG2BPIG-SD series adapter"},
6114 {"Silicom Bypass PXG2TBFI-SD series adapter"},
6115 {"Silicom Bypass PXG4BPI-SD series adapter"},
6116 {"Silicom Bypass PXG4BPFI-SD series adapter"},
6117 {"Silicom Bypass PEG4BPI-SD series adapter"},
6118 {"Silicom Bypass PEG2BPI-SD series adapter"},
6119 {"Silicom Bypass PEG4BPIN-SD series adapter"},
6120 {"Silicom Bypass PEG2BPFI-SD series adapter"},
6121 {"Silicom Bypass PEG2BPFI-LX-SD series adapter"},
6122 {"Silicom Bypass PMCX2BPFI-SD series adapter"},
6123 {"Silicom Bypass PMCX2BPFI-N series adapter"},
6124 {"Intel Bypass PEG2BPII series adapter"},
6125 {"Intel Bypass PEG2BPFII series adapter"},
6126 {"Silicom Bypass PXG4BPFILX-SD series adapter"},
6127 {"Silicom Bypass PMCX2BPI-N series adapter"},
6128 {"Silicom Bypass PMCX4BPI-N series adapter"},
6129 {"Silicom Bypass PXG2BISC1-SD series adapter"},
6130 {"Silicom Bypass PEG2TBFI-SD series adapter"},
6131 {"Silicom Bypass PXG2TBI-SD series adapter"},
6132 {"Silicom Bypass PXG4BPFID-SD series adapter"},
6133 {"Silicom Bypass PEG4BPFI-SD series adapter"},
6134 {"Silicom Bypass PEG4BPIPT-SD series adapter"},
6135 {"Silicom Bypass PXG6BPI-SD series adapter"},
6136 {"Silicom Bypass PEG4BPIL-SD series adapter"},
6137 {"Silicom Bypass PMCX2BPI-N2 series adapter"},
6138 {"Silicom Bypass PMCX4BPI-N2 series adapter"},
6139 {"Silicom Bypass PMCX2BPI-SD series adapter"},
6140 {"Silicom Bypass PEG2BPFID-SD series adapter"},
6141 {"Silicom Bypass PEG2BPFIDLX-SD series adapter"},
6142 {"Silicom Bypass PMCX4BPI-SD series adapter"},
6143 {"Silicom Bypass MEG2BPFILN-SD series adapter"},
6144 {"Silicom Bypass MEG2BPFINX-SD series adapter"},
6145 {"Silicom Bypass PEG4BPFILX-SD series adapter"},
6146 {"Silicom Bypass PE10G2BPISR-SD series adapter"},
6147 {"Silicom Bypass PE10G2BPILR-SD series adapter"},
6148 {"Silicom Bypass MHIO8AD-SD series adapter"},
6149 {"Silicom Bypass PE10G2BPICX4-SD series adapter"},
6150 {"Silicom Bypass PEG2BPI5-SD series adapter"},
6151 {"Silicom Bypass PEG6BPI5-SD series adapter"},
6152 {"Silicom Bypass PEG4BPFI5-SD series adapter"},
6153 {"Silicom Bypass PEG4BPFI5LX-SD series adapter"},
6154 {"Silicom Bypass MEG2BPFILXLN-SD series adapter"},
6155 {"Silicom Bypass PEG2BPIX1-SD series adapter"},
6156 {"Silicom Bypass MEG2BPFILXNX-SD series adapter"},
6157 {"Silicom Bypass XE10G2BPIT-SD series adapter"},
6158 {"Silicom Bypass XE10G2BPICX4-SD series adapter"},
6159 {"Silicom Bypass XE10G2BPISR-SD series adapter"},
6160 {"Silicom Bypass XE10G2BPILR-SD series adapter"},
6161 {"Intel Bypass PEG2BPFII0 series adapter"},
6162 {"Silicom Bypass XE10G2BPIXR series adapter"},
6163 {"Silicom Bypass PE10G2DBISR series adapter"},
6164 {"Silicom Bypass PEG2BI5SC6 series adapter"},
6165 {"Silicom Bypass PEG6BPI5FC series adapter"},
6167 {"Silicom Bypass PE10G2BPTCX4 series adapter"},
6168 {"Silicom Bypass PE10G2BPTSR series adapter"},
6169 {"Silicom Bypass PE10G2BPTLR series adapter"},
6170 {"Silicom Bypass PE10G2BPTT series adapter"},
6171 {"Silicom Bypass PEG4BPI6 series adapter"},
6172 {"Silicom Bypass PEG4BPFI6 series adapter"},
6173 {"Silicom Bypass PEG4BPFI6LX series adapter"},
6174 {"Silicom Bypass PEG4BPFI6ZX series adapter"},
6175 {"Silicom Bypass PEG2BPI6 series adapter"},
6176 {"Silicom Bypass PEG2BPFI6 series adapter"},
6177 {"Silicom Bypass PEG2BPFI6LX series adapter"},
6178 {"Silicom Bypass PEG2BPFI6ZX series adapter"},
6179 {"Silicom Bypass PEG2BPFI6FLXM series adapter"},
6180 {"Silicom Bypass PEG4BPI6FC series adapter"},
6181 {"Silicom Bypass PEG4BPFI6FC series adapter"},
6182 {"Silicom Bypass PEG4BPFI6FCLX series adapter"},
6183 {"Silicom Bypass PEG4BPFI6FCZX series adapter"},
6184 {"Silicom Bypass PEG6BPI6 series adapter"},
6185 {"Silicom Bypass PEG2BPI6SC6 series adapter"},
6186 {"Silicom Bypass MEG2BPI6 series adapter"},
6187 {"Silicom Bypass XEG2BPI6 series adapter"},
6188 {"Silicom Bypass MEG4BPI6 series adapter"},
6189 {"Silicom Bypass PEG2BPFI5-SD series adapter"},
6190 {"Silicom Bypass PEG2BPFI5LX-SD series adapter"},
6191 {"Silicom Bypass PXEG4BPFI-SD series adapter"},
6192 {"Silicom Bypass MxEG2BPI6 series adapter"},
6193 {"Silicom Bypass MxEG2BPFI6 series adapter"},
6194 {"Silicom Bypass MxEG2BPFI6LX series adapter"},
6195 {"Silicom Bypass MxEG2BPFI6ZX series adapter"},
6196 {"Silicom Bypass MxEG4BPI6 series adapter"},
6197 {"Silicom Bypass MxEG4BPFI6 series adapter"},
6198 {"Silicom Bypass MxEG4BPFI6LX series adapter"},
6199 {"Silicom Bypass MxEG4BPFI6ZX series adapter"},
6200 {"Silicom Bypass MxEG6BPI6 series adapter"},
6201 {"Silicom Bypass MxE2G4BPi80 series adapter"},
6202 {"Silicom Bypass MxE2G4BPFi80 series adapter"},
6203 {"Silicom Bypass MxE2G4BPFi80LX series adapter"},
6204 {"Silicom Bypass MxE2G4BPFi80ZX series adapter"},
6206 {"Silicom Bypass PE210G2SPI9 series adapter"},
6208 {"Silicom Bypass MxE210G2BPI9CX4 series adapter"},
6209 {"Silicom Bypass MxE210G2BPI9SR series adapter"},
6210 {"Silicom Bypass MxE210G2BPI9LR series adapter"},
6211 {"Silicom Bypass MxE210G2BPI9T series adapter"},
6213 {"Silicom Bypass PE210G2BPI9CX4 series adapter"},
6214 {"Silicom Bypass PE210G2BPI9SR series adapter"},
6215 {"Silicom Bypass PE210G2BPI9LR series adapter"},
6216 {"Silicom Bypass PE210G2BPI9T series adapter"},
6218 {"Silicom Bypass M2EG2BPFI6 series adapter"},
6219 {"Silicom Bypass M2EG2BPFI6LX series adapter"},
6220 {"Silicom Bypass M2EG2BPFI6ZX series adapter"},
6221 {"Silicom Bypass M2EG4BPI6 series adapter"},
6222 {"Silicom Bypass M2EG4BPFI6 series adapter"},
6223 {"Silicom Bypass M2EG4BPFI6LX series adapter"},
6224 {"Silicom Bypass M2EG4BPFI6ZX series adapter"},
6225 {"Silicom Bypass M2EG6BPI6 series adapter"},
6227 {"Silicom Bypass PEG2DBI6 series adapter"},
6228 {"Silicom Bypass PEG2DBFI6 series adapter"},
6229 {"Silicom Bypass PEG2DBFI6LX series adapter"},
6230 {"Silicom Bypass PEG2DBFI6ZX series adapter"},
6232 {"Silicom Bypass PE2G4BPi80 series adapter"},
6233 {"Silicom Bypass PE2G4BPFi80 series adapter"},
6234 {"Silicom Bypass PE2G4BPFi80LX series adapter"},
6235 {"Silicom Bypass PE2G4BPFi80ZX series adapter"},
6237 {"Silicom Bypass PE2G4BPi80L series adapter"},
6238 {"Silicom Bypass MxE2G8BPi80A series adapter"},
6240 {"Silicom Bypass PE2G2BPi35 series adapter"},
6241 {"Silicom Bypass PAC1200BPi35 series adapter"},
6242 {"Silicom Bypass PE2G2BPFi35 series adapter"},
6243 {"Silicom Bypass PE2G2BPFi35LX series adapter"},
6244 {"Silicom Bypass PE2G2BPFi35ZX series adapter"},
6246 {"Silicom Bypass PE2G4BPi35 series adapter"},
6247 {"Silicom Bypass PE2G4BPi35L series adapter"},
6248 {"Silicom Bypass PE2G4BPFi35 series adapter"},
6249 {"Silicom Bypass PE2G4BPFi35LX series adapter"},
6250 {"Silicom Bypass PE2G4BPFi35ZX series adapter"},
6252 {"Silicom Bypass PE2G6BPi35 series adapter"},
6253 {"Silicom Bypass PE2G6BPi35CX series adapter"},
6255 {"Silicom Bypass PE2G2BPi80 series adapter"},
6256 {"Silicom Bypass PE2G2BPFi80 series adapter"},
6257 {"Silicom Bypass PE2G2BPFi80LX series adapter"},
6258 {"Silicom Bypass PE2G2BPFi80ZX series adapter"},
6260 {"Silicom Bypass M2E10G2BPI9CX4 series adapter"},
6261 {"Silicom Bypass M2E10G2BPI9SR series adapter"},
6262 {"Silicom Bypass M2E10G2BPI9LR series adapter"},
6263 {"Silicom Bypass M2E10G2BPI9T series adapter"},
6264 {"Silicom Bypass MxE2G8BPi80 series adapter"},
6265 {"Silicom Bypass PE210G2DBi9SR series adapter"},
6266 {"Silicom Bypass PE210G2DBi9SRRB series adapter"},
6267 {"Silicom Bypass PE210G2DBi9LR series adapter"},
6268 {"Silicom Bypass PE210G2DBi9LRRB series adapter"},
6269 {"Silicom Bypass PE310G4DBi9-SR series adapter"},
6270 {"Silicom Bypass PE310G4BPi9T series adapter"},
6271 {"Silicom Bypass PE310G4BPi9SR series adapter"},
6272 {"Silicom Bypass PE310G4BPi9LR series adapter"},
6273 {"Silicom Bypass PE210G2BPi40T series adapter"},
6277 static bpmod_info_t tx_ctl_pci_tbl[] = {
6278 {0x8086, 0x107a, SILICOM_SVID, SILICOM_PXG2BPFI_SSID, PXG2BPFI,
6280 {0x8086, 0x107a, SILICOM_SVID, SILICOM_PXG2BPFIL_SSID, PXG2BPFIL,
6282 {0x8086, 0x107a, SILICOM_SVID, SILICOM_PXG2BPFILX_SSID, PXG2BPFILX,
6284 {0x8086, 0x107a, SILICOM_SVID, SILICOM_PXG2BPFILLX_SSID, PXG2BPFILLX,
6286 {0x8086, 0x1010, SILICOM_SVID, SILICOM_PXGBPI_SSID, PXGBPI,
6288 {0x8086, 0x1079, SILICOM_SVID, SILICOM_PXGBPIG_SSID, PXGBPIG,
6290 {0x8086, 0x107a, SILICOM_SVID, SILICOM_PXG2TBFI_SSID, PXG2TBFI,
6292 {0x8086, 0x1079, SILICOM_SVID, SILICOM_PXG4BPI_SSID, PXG4BPI,
6294 {0x8086, 0x107a, SILICOM_SVID, SILICOM_PXG4BPFI_SSID, PXG4BPFI,
6296 {0x8086, 0x107a, SILICOM_SVID, SILICOM_PXG4BPFILX_SSID, PXG4BPFILX,
6298 {0x8086, 0x1079, SILICOM_SVID, SILICOM_PEG4BPI_SSID, PEG4BPI,
6300 {0x8086, 0x105e, SILICOM_SVID, SILICOM_PEG2BPI_SSID, PEG2BPI,
6302 {0x8086, 0x105e, SILICOM_SVID, SILICOM_PEG4BPIN_SSID, PEG4BPIN,
6304 {0x8086, 0x105f, SILICOM_SVID, SILICOM_PEG2BPFI_SSID, PEG2BPFI,
6306 {0x8086, 0x105f, SILICOM_SVID, SILICOM_PEG2BPFILX_SSID, PEG2BPFILX,
6308 {0x8086, 0x107a, SILICOM_SVID, SILICOM_PMCXG2BPFI_SSID, PMCXG2BPFI,
6310 {0x8086, 0x107a, NOKIA_PMCXG2BPFIN_SVID, NOKIA_PMCXG2BPFIN_SSID,
6311 PMCXG2BPFIN, "PMCX2BPFI-N"},
6312 {0x8086, INTEL_PEG4BPII_PID, 0x8086, INTEL_PEG4BPII_SSID, PEG4BPII,
6314 {0x8086, INTEL_PEG4BPIIO_PID, 0x8086, INTEL_PEG4BPIIO_SSID, PEG4BPIIO,
6316 {0x8086, INTEL_PEG4BPFII_PID, 0x8086, INTEL_PEG4BPFII_SSID, PEG4BPFII,
6318 {0x8086, 0x1079, NOKIA_PMCXG2BPFIN_SVID, NOKIA_PMCXG2BPIN_SSID,
6319 PMCXG2BPIN, "PMCX2BPI-N"},
6320 {0x8086, 0x1079, NOKIA_PMCXG2BPFIN_SVID, NOKIA_PMCXG4BPIN_SSID,
6321 PMCXG4BPIN, "PMCX4BPI-N"},
6322 {0x8086, 0x1079, SILICOM_SVID, SILICOM_PXG2BISC1_SSID, PXG2BISC1,
6324 {0x8086, 0x105f, SILICOM_SVID, SILICOM_PEG2TBFI_SSID, PEG2TBFI,
6326 {0x8086, 0x1079, SILICOM_SVID, SILICOM_PXG2TBI_SSID, PXG2TBI,
6328 {0x8086, 0x107a, SILICOM_SVID, SILICOM_PXG4BPFID_SSID, PXG4BPFID,
6330 {0x8086, 0x105f, SILICOM_SVID, SILICOM_PEG4BPFI_SSID, PEG4BPFI,
6332 {0x8086, 0x105e, SILICOM_SVID, SILICOM_PEG4BPIPT_SSID, PEG4BPIPT,
6334 {0x8086, 0x1079, SILICOM_SVID, SILICOM_PXG6BPI_SSID, PXG6BPI,
6336 {0x8086, 0x10a7, SILICOM_SVID /*PCI_ANY_ID */ ,
6337 SILICOM_PEG4BPIL_SSID /*PCI_ANY_ID */ , PEG4BPIL, "PEG4BPIL-SD"},
6338 {0x8086, 0x1079, NOKIA_PMCXG2BPFIN_SVID, NOKIA_PMCXG2BPIN2_SSID,
6339 PMCXG2BPIN2, "PMCX2BPI-N2"},
6340 {0x8086, 0x1079, NOKIA_PMCXG2BPFIN_SVID, NOKIA_PMCXG4BPIN2_SSID,
6341 PMCXG4BPIN2, "PMCX4BPI-N2"},
6342 {0x8086, 0x1079, SILICOM_SVID, SILICOM_PMCX2BPI_SSID, PMCX2BPI,
6344 {0x8086, 0x1079, SILICOM_SVID, SILICOM_PMCX4BPI_SSID, PMCX4BPI,
6346 {0x8086, 0x105f, SILICOM_SVID, SILICOM_PEG2BPFID_SSID, PEG2BPFID,
6348 {0x8086, 0x105f, SILICOM_SVID, SILICOM_PEG2BPFIDLX_SSID, PEG2BPFIDLX,
6350 {0x8086, 0x105f, SILICOM_SVID, SILICOM_MEG2BPFILN_SSID, MEG2BPFILN,
6352 {0x8086, 0x105f, SILICOM_SVID, SILICOM_MEG2BPFINX_SSID, MEG2BPFINX,
6354 {0x8086, 0x105f, SILICOM_SVID, SILICOM_PEG4BPFILX_SSID, PEG4BPFILX,
6356 {0x8086, PCI_ANY_ID, SILICOM_SVID, SILICOM_PE10G2BPISR_SSID,
6357 PE10G2BPISR, "PE10G2BPISR"},
6358 {0x8086, PCI_ANY_ID, SILICOM_SVID, SILICOM_PE10G2BPILR_SSID,
6359 PE10G2BPILR, "PE10G2BPILR"},
6360 {0x8086, 0x10a9, SILICOM_SVID, SILICOM_MHIO8AD_SSID, MHIO8AD,
6362 {0x8086, PCI_ANY_ID, SILICOM_SVID, SILICOM_PE10G2BPICX4_SSID,
6363 PE10G2BPISR, "PE10G2BPICX4"},
6364 {0x8086, 0x10a7, SILICOM_SVID /*PCI_ANY_ID */ ,
6365 SILICOM_PEG2BPI5_SSID /*PCI_ANY_ID */ , PEG2BPI5, "PEG2BPI5-SD"},
6366 {0x8086, 0x10a7, SILICOM_SVID /*PCI_ANY_ID */ ,
6367 SILICOM_PEG6BPI_SSID /*PCI_ANY_ID */ , PEG6BPI, "PEG6BPI5"},
6368 {0x8086, 0x10a9, SILICOM_SVID /*PCI_ANY_ID */ , SILICOM_PEG4BPFI5_SSID,
6369 PEG4BPFI5, "PEG4BPFI5"},
6370 {0x8086, 0x10a9, SILICOM_SVID /*PCI_ANY_ID */ ,
6371 SILICOM_PEG4BPFI5LX_SSID, PEG4BPFI5LX, "PEG4BPFI5LX"},
6372 {0x8086, 0x105f, SILICOM_SVID, SILICOM_MEG2BPFILXLN_SSID, MEG2BPFILXLN,
6374 {0x8086, 0x105e, SILICOM_SVID, SILICOM_PEG2BPIX1_SSID, PEG2BPIX1,
6376 {0x8086, 0x105f, SILICOM_SVID, SILICOM_MEG2BPFILXNX_SSID, MEG2BPFILXNX,
6378 {0x8086, PCI_ANY_ID, SILICOM_SVID, SILICOM_XE10G2BPIT_SSID, XE10G2BPIT,
6380 {0x8086, PCI_ANY_ID, SILICOM_SVID, SILICOM_XE10G2BPICX4_SSID,
6381 XE10G2BPICX4, "XE10G2BPICX4"},
6382 {0x8086, 0x10C6, SILICOM_SVID, SILICOM_XE10G2BPISR_SSID, XE10G2BPISR,
6384 {0x8086, 0x10C6, SILICOM_SVID, SILICOM_XE10G2BPILR_SSID, XE10G2BPILR,
6386 {0x8086, 0x10C6, NOKIA_XE10G2BPIXR_SVID, NOKIA_XE10G2BPIXR_SSID,
6387 XE10G2BPIXR, "XE10G2BPIXR"},
6388 {0x8086, 0x10C6, SILICOM_SVID, SILICOM_PE10GDBISR_SSID, PE10GDBISR,
6390 {0x8086, 0x10C6, SILICOM_SVID, SILICOM_PE10GDBILR_SSID, PE10GDBILR,
6392 {0x8086, 0x10a7, SILICOM_SVID /*PCI_ANY_ID */ ,
6393 SILICOM_PEG2BISC6_SSID /*PCI_ANY_ID */ , PEG2BISC6, "PEG2BI5SC6"},
6394 {0x8086, 0x10a7, SILICOM_SVID /*PCI_ANY_ID */ ,
6395 SILICOM_PEG6BPIFC_SSID /*PCI_ANY_ID */ , PEG6BPIFC, "PEG6BPI5FC"},
6397 {BROADCOM_VID, BROADCOM_PE10G2_PID, SILICOM_SVID,
6398 SILICOM_PE10G2BPTCX4_SSID, PE10G2BPTCX4, "PE10G2BPTCX4"},
6399 {BROADCOM_VID, BROADCOM_PE10G2_PID, SILICOM_SVID,
6400 SILICOM_PE10G2BPTSR_SSID, PE10G2BPTSR, "PE10G2BPTSR"},
6401 {BROADCOM_VID, BROADCOM_PE10G2_PID, SILICOM_SVID,
6402 SILICOM_PE10G2BPTLR_SSID, PE10G2BPTLR, "PE10G2BPTLR"},
6403 {BROADCOM_VID, BROADCOM_PE10G2_PID, SILICOM_SVID,
6404 SILICOM_PE10G2BPTT_SSID, PE10G2BPTT, "PE10G2BPTT"},
6406 /* {BROADCOM_VID, BROADCOM_PE10G2_PID, PCI_ANY_ID, PCI_ANY_ID, PE10G2BPTCX4, "PE10G2BPTCX4"}, */
6408 {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6409 SILICOM_PEG4BPI6_SSID /*PCI_ANY_ID */ , PEG4BPI6, "PEG4BPI6"},
6410 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6411 SILICOM_PEG4BPFI6_SSID /*PCI_ANY_ID */ , PEG4BPFI6, "PEG4BPFI6"},
6412 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6413 SILICOM_PEG4BPFI6LX_SSID /*PCI_ANY_ID */ , PEG4BPFI6LX, "PEG4BPFI6LX"},
6414 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6415 SILICOM_PEG4BPFI6ZX_SSID /*PCI_ANY_ID */ , PEG4BPFI6ZX, "PEG4BPFI6ZX"},
6416 {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6417 SILICOM_PEG2BPI6_SSID /*PCI_ANY_ID */ , PEG2BPI6, "PEG2BPI6"},
6418 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6419 SILICOM_PEG2BPFI6_SSID /*PCI_ANY_ID */ , PEG2BPFI6, "PEG2BPFI6"},
6420 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6421 SILICOM_PEG2BPFI6LX_SSID /*PCI_ANY_ID */ , PEG2BPFI6LX, "PEG2BPFI6LX"},
6422 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6423 SILICOM_PEG2BPFI6ZX_SSID /*PCI_ANY_ID */ , PEG2BPFI6ZX, "PEG2BPFI6ZX"},
6424 {0x8086, 0x10e7, SILICOM_SVID /*PCI_ANY_ID */ ,
6425 SILICOM_PEG2BPFI6FLXM_SSID /*PCI_ANY_ID */ , PEG2BPFI6FLXM,
6427 {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6428 SILICOM_PEG4BPI6FC_SSID /*PCI_ANY_ID */ , PEG4BPI6FC, "PEG4BPI6FC"},
6429 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6430 SILICOM_PEG4BPFI6FC_SSID /*PCI_ANY_ID */ , PEG4BPFI6FC, "PEG4BPFI6FC"},
6431 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6432 SILICOM_PEG4BPFI6FCLX_SSID /*PCI_ANY_ID */ , PEG4BPFI6FCLX,
6434 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6435 SILICOM_PEG4BPFI6FCZX_SSID /*PCI_ANY_ID */ , PEG4BPFI6FCZX,
6437 {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6438 SILICOM_PEG6BPI6_SSID /*PCI_ANY_ID */ , PEG6BPI6, "PEG6BPI6"},
6439 {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6440 SILICOM_PEG2BPI6SC6_SSID /*PCI_ANY_ID */ , PEG2BPI6SC6,
6442 {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6443 SILICOM_MEG2BPI6_SSID /*PCI_ANY_ID */ , MEG2BPI6, "MEG2BPI6"},
6444 {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6445 SILICOM_XEG2BPI6_SSID /*PCI_ANY_ID */ , XEG2BPI6, "XEG2BPI6"},
6446 {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6447 SILICOM_MEG4BPI6_SSID /*PCI_ANY_ID */ , MEG4BPI6, "MEG4BPI6"},
6449 {0x8086, 0x10a9, SILICOM_SVID /*PCI_ANY_ID */ , SILICOM_PEG2BPFI5_SSID,
6450 PEG2BPFI5, "PEG2BPFI5"},
6451 {0x8086, 0x10a9, SILICOM_SVID /*PCI_ANY_ID */ ,
6452 SILICOM_PEG2BPFI5LX_SSID, PEG2BPFI5LX, "PEG2BPFI5LX"},
6454 {0x8086, 0x105f, SILICOM_SVID, SILICOM_PXEG4BPFI_SSID, PXEG4BPFI,
6457 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6458 SILICOM_M1EG2BPI6_SSID /*PCI_ANY_ID */ , M1EG2BPI6, "MxEG2BPI6"},
6460 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6461 SILICOM_M1EG2BPFI6_SSID /*PCI_ANY_ID */ , M1EG2BPFI6, "MxEG2BPFI6"},
6462 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6463 SILICOM_M1EG2BPFI6LX_SSID /*PCI_ANY_ID */ , M1EG2BPFI6LX,
6465 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6466 SILICOM_M1EG2BPFI6ZX_SSID /*PCI_ANY_ID */ , M1EG2BPFI6ZX,
6469 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6470 SILICOM_M1EG4BPI6_SSID /*PCI_ANY_ID */ , M1EG4BPI6, "MxEG4BPI6"},
6472 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6473 SILICOM_M1EG4BPFI6_SSID /*PCI_ANY_ID */ , M1EG4BPFI6, "MxEG4BPFI6"},
6474 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6475 SILICOM_M1EG4BPFI6LX_SSID /*PCI_ANY_ID */ , M1EG4BPFI6LX,
6477 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6478 SILICOM_M1EG4BPFI6ZX_SSID /*PCI_ANY_ID */ , M1EG4BPFI6ZX,
6481 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6482 SILICOM_M1EG6BPI6_SSID /*PCI_ANY_ID */ , M1EG6BPI6, "MxEG6BPI6"},
6484 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6485 SILICOM_M1E2G4BPi80_SSID /*PCI_ANY_ID */ , M1E2G4BPi80, "MxE2G4BPi80"},
6486 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6487 SILICOM_M1E2G4BPFi80_SSID /*PCI_ANY_ID */ , M1E2G4BPFi80,
6489 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6490 SILICOM_M1E2G4BPFi80LX_SSID /*PCI_ANY_ID */ , M1E2G4BPFi80LX,
6492 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6493 SILICOM_M1E2G4BPFi80ZX_SSID /*PCI_ANY_ID */ , M1E2G4BPFi80ZX,
6496 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6497 SILICOM_M2EG2BPFI6_SSID /*PCI_ANY_ID */ , M2EG2BPFI6, "M2EG2BPFI6"},
6498 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6499 SILICOM_M2EG2BPFI6LX_SSID /*PCI_ANY_ID */ , M2EG2BPFI6LX,
6501 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6502 SILICOM_M2EG2BPFI6ZX_SSID /*PCI_ANY_ID */ , M2EG2BPFI6ZX,
6505 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6506 SILICOM_M2EG4BPI6_SSID /*PCI_ANY_ID */ , M2EG4BPI6, "M2EG4BPI6"},
6508 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6509 SILICOM_M2EG4BPFI6_SSID /*PCI_ANY_ID */ , M2EG4BPFI6, "M2EG4BPFI6"},
6510 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6511 SILICOM_M2EG4BPFI6LX_SSID /*PCI_ANY_ID */ , M2EG4BPFI6LX,
6513 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6514 SILICOM_M2EG4BPFI6ZX_SSID /*PCI_ANY_ID */ , M2EG4BPFI6ZX,
6517 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6518 SILICOM_M2EG6BPI6_SSID /*PCI_ANY_ID */ , M2EG6BPI6, "M2EG6BPI6"},
6520 {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6521 SILICOM_PEG2DBI6_SSID /*PCI_ANY_ID */ , PEG2DBI6, "PEG2DBI6"},
6522 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6523 SILICOM_PEG2DBFI6_SSID /*PCI_ANY_ID */ , PEG2DBFI6, "PEG2DBFI6"},
6524 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6525 SILICOM_PEG2DBFI6LX_SSID /*PCI_ANY_ID */ , PEG2DBFI6LX, "PEG2DBFI6LX"},
6526 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6527 SILICOM_PEG2DBFI6ZX_SSID /*PCI_ANY_ID */ , PEG2DBFI6ZX, "PEG2DBFI6ZX"},
6529 {0x8086, 0x10F9, SILICOM_SVID /*PCI_ANY_ID */ ,
6530 SILICOM_PE210G2DBi9SR_SSID, PE210G2DBi9SR, "PE210G2DBi9SR"},
6531 {0x8086, 0x10F9, SILICOM_SVID /*PCI_ANY_ID */ ,
6532 SILICOM_PE210G2DBi9LR_SSID, PE210G2DBi9LR, "PE210G2DBi9LR"},
6533 {0x8086, 0x10F9, SILICOM_SVID /*PCI_ANY_ID */ ,
6534 SILICOM_PE310G4DBi940SR_SSID, PE310G4DBi940SR, "PE310G4DBi9SR"},
6536 {0x8086, 0x10Fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6537 SILICOM_PE310G4BPi9T_SSID, PE310G4BPi9T, "PE310G4BPi9T"},
6538 {0x8086, 0x10Fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6539 SILICOM_PE310G4BPi9SR_SSID, PE310G4BPi9SR, "PE310G4BPi9SR"},
6540 {0x8086, 0x10Fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6541 SILICOM_PE310G4BPi9LR_SSID, PE310G4BPi9LR, "PE310G4BPi9LR"},
6543 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6544 SILICOM_PE2G4BPi80_SSID /*PCI_ANY_ID */ , PE2G4BPi80, "PE2G4BPi80"},
6545 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6546 SILICOM_PE2G4BPFi80_SSID /*PCI_ANY_ID */ , PE2G4BPFi80, "PE2G4BPFi80"},
6547 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6548 SILICOM_PE2G4BPFi80LX_SSID /*PCI_ANY_ID */ , PE2G4BPFi80LX,
6550 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6551 SILICOM_PE2G4BPFi80ZX_SSID /*PCI_ANY_ID */ , PE2G4BPFi80ZX,
6554 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6555 SILICOM_PE2G4BPi80L_SSID /*PCI_ANY_ID */ , PE2G4BPi80L, "PE2G4BPi80L"},
6557 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6558 SILICOM_M6E2G8BPi80A_SSID /*PCI_ANY_ID */ , M6E2G8BPi80A,
6561 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6562 SILICOM_PE2G2BPi35_SSID /*PCI_ANY_ID */ , PE2G2BPi35, "PE2G2BPi35"},
6563 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6564 SILICOM_PAC1200BPi35_SSID /*PCI_ANY_ID */ , PAC1200BPi35,
6567 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6568 SILICOM_PE2G2BPFi35_SSID /*PCI_ANY_ID */ , PE2G2BPFi35, "PE2G2BPFi35"},
6569 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6570 SILICOM_PE2G2BPFi35LX_SSID /*PCI_ANY_ID */ , PE2G2BPFi35LX,
6572 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6573 SILICOM_PE2G2BPFi35ZX_SSID /*PCI_ANY_ID */ , PE2G2BPFi35ZX,
6576 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6577 SILICOM_PE2G4BPi35_SSID /*PCI_ANY_ID */ , PE2G4BPi35, "PE2G4BPi35"},
6579 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6580 SILICOM_PE2G4BPi35L_SSID /*PCI_ANY_ID */ , PE2G4BPi35L, "PE2G4BPi35L"},
6582 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6583 SILICOM_PE2G4BPFi35_SSID /*PCI_ANY_ID */ , PE2G4BPFi35, "PE2G4BPFi35"},
6584 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6585 SILICOM_PE2G4BPFi35LX_SSID /*PCI_ANY_ID */ , PE2G4BPFi35LX,
6587 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6588 SILICOM_PE2G4BPFi35ZX_SSID /*PCI_ANY_ID */ , PE2G4BPFi35ZX,
6591 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6592 SILICOM_PE2G6BPi35_SSID /*PCI_ANY_ID */ , PE2G6BPi35, "PE2G6BPi35"},
6595 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa0, PE2G6BPi35CX,
6597 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa1, PE2G6BPi35CX,
6599 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa2, PE2G6BPi35CX,
6601 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa3, PE2G6BPi35CX,
6603 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa4, PE2G6BPi35CX,
6605 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa5, PE2G6BPi35CX,
6607 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa6, PE2G6BPi35CX,
6609 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa7, PE2G6BPi35CX,
6611 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa8, PE2G6BPi35CX,
6613 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa9, PE2G6BPi35CX,
6615 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaaa, PE2G6BPi35CX,
6617 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaab, PE2G6BPi35CX,
6619 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaac, PE2G6BPi35CX,
6621 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaad, PE2G6BPi35CX,
6623 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaae, PE2G6BPi35CX,
6625 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaaf, PE2G6BPi35CX,
6627 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab0, PE2G6BPi35CX,
6629 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab1, PE2G6BPi35CX,
6631 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab2, PE2G6BPi35CX,
6633 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab3, PE2G6BPi35CX,
6635 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab4, PE2G6BPi35CX,
6637 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab5, PE2G6BPi35CX,
6639 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab6, PE2G6BPi35CX,
6641 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab7, PE2G6BPi35CX,
6643 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab8, PE2G6BPi35CX,
6645 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab9, PE2G6BPi35CX,
6647 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaba, PE2G6BPi35CX,
6649 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xabb, PE2G6BPi35CX,
6651 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xabc, PE2G6BPi35CX,
6653 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xabd, PE2G6BPi35CX,
6655 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xabe, PE2G6BPi35CX,
6657 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xabf, PE2G6BPi35CX,
6660 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6661 SILICOM_PE2G2BPi80_SSID /*PCI_ANY_ID */ , PE2G2BPi80, "PE2G2BPi80"},
6662 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6663 SILICOM_PE2G2BPFi80_SSID /*PCI_ANY_ID */ , PE2G2BPFi80, "PE2G2BPFi80"},
6664 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6665 SILICOM_PE2G2BPFi80LX_SSID /*PCI_ANY_ID */ , PE2G2BPFi80LX,
6667 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6668 SILICOM_PE2G2BPFi80ZX_SSID /*PCI_ANY_ID */ , PE2G2BPFi80ZX,
6671 {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6672 SILICOM_MEG2BPI6_SSID /*PCI_ANY_ID */ , MEG2BPI6, "MEG2BPI6"},
6673 {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6674 SILICOM_XEG2BPI6_SSID /*PCI_ANY_ID */ , XEG2BPI6, "XEG2BPI6"},
6677 {0x8086, 0x10fb, 0x8086, INTEL_PE210G2SPI9_SSID, PE210G2SPI9,
6680 {0x8086, 0x10fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6681 SILICOM_M1E10G2BPI9CX4_SSID /*PCI_ANY_ID */ , M1E10G2BPI9CX4,
6683 {0x8086, 0x10fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6684 SILICOM_M1E10G2BPI9SR_SSID /*PCI_ANY_ID */ , M1E10G2BPI9SR,
6686 {0x8086, 0x10fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6687 SILICOM_M1E10G2BPI9LR_SSID /*PCI_ANY_ID */ , M1E10G2BPI9LR,
6689 {0x8086, 0x10fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6690 SILICOM_M1E10G2BPI9T_SSID /*PCI_ANY_ID */ , M1E10G2BPI9T,
6693 {0x8086, 0x10fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6694 SILICOM_M2E10G2BPI9CX4_SSID /*PCI_ANY_ID */ , M2E10G2BPI9CX4,
6696 {0x8086, 0x10fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6697 SILICOM_M2E10G2BPI9SR_SSID /*PCI_ANY_ID */ , M2E10G2BPI9SR,
6699 {0x8086, 0x10fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6700 SILICOM_M2E10G2BPI9LR_SSID /*PCI_ANY_ID */ , M2E10G2BPI9LR,
6702 {0x8086, 0x10fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6703 SILICOM_M2E10G2BPI9T_SSID /*PCI_ANY_ID */ , M2E10G2BPI9T,
6706 {0x8086, 0x10fb, SILICOM_SVID, SILICOM_PE210G2BPI9CX4_SSID,
6707 PE210G2BPI9CX4, "PE210G2BPI9CX4"},
6708 {0x8086, 0x10fb, SILICOM_SVID, SILICOM_PE210G2BPI9SR_SSID,
6709 PE210G2BPI9SR, "PE210G2BPI9SR"},
6710 {0x8086, 0x10fb, SILICOM_SVID, SILICOM_PE210G2BPI9LR_SSID,
6711 PE210G2BPI9LR, "PE210G2BPI9LR"},
6712 {0x8086, 0x10fb, SILICOM_SVID, SILICOM_PE210G2BPI9T_SSID, PE210G2BPI9T,
6716 {0x1374, 0x2c, SILICOM_SVID, SILICOM_PXG4BPI_SSID, PXG4BPI,
6719 {0x1374, 0x2d, SILICOM_SVID, SILICOM_PXG4BPFI_SSID, PXG4BPFI,
6722 {0x1374, 0x3f, SILICOM_SVID, SILICOM_PXG2TBI_SSID, PXG2TBI,
6725 {0x1374, 0x3d, SILICOM_SVID, SILICOM_PXG2BISC1_SSID, PXG2BISC1,
6728 {0x1374, 0x40, SILICOM_SVID, SILICOM_PEG4BPFI_SSID, PEG4BPFI,
6732 {0x1374, 0x28, SILICOM_SVID, 0x28, PXGBPI, "PXG2BPI-SD"},
6735 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6736 SILICOM_M6E2G8BPi80_SSID /*PCI_ANY_ID */ , M6E2G8BPi80, "MxE2G8BPi80"},
6737 {0x8086, 0x1528, SILICOM_SVID /*PCI_ANY_ID */ ,
6738 SILICOM_PE210G2BPi40_SSID /*PCI_ANY_ID */ , PE210G2BPi40,
6741 /* required last entry */
6746 * Initialize the module - Register the character device
6749 static int __init bypass_init_module(void)
6751 int ret_val, idx, idx_dev = 0;
6752 struct pci_dev *pdev1 = NULL;
6753 unsigned long mmio_start, mmio_len;
6755 printk(BP_MOD_DESCR " v" BP_MOD_VER "\n");
6756 ret_val = register_chrdev(major_num, DEVICE_NAME, &Fops);
6758 printk("%s failed with %d\n", DEVICE_NAME, ret_val);
6761 major_num = ret_val; /* dynamic */
6762 for (idx = 0; tx_ctl_pci_tbl[idx].vendor; idx++) {
6763 while ((pdev1 = pci_get_subsys(tx_ctl_pci_tbl[idx].vendor,
6764 tx_ctl_pci_tbl[idx].device,
6765 tx_ctl_pci_tbl[idx].subvendor,
6766 tx_ctl_pci_tbl[idx].subdevice,
6773 printk("No such device\n");
6774 unregister_chrdev(major_num, DEVICE_NAME);
6778 bpctl_dev_arr = kmalloc((device_num) * sizeof(bpctl_dev_t), GFP_KERNEL);
6780 if (!bpctl_dev_arr) {
6781 printk("Allocation error\n");
6782 unregister_chrdev(major_num, DEVICE_NAME);
6785 memset(bpctl_dev_arr, 0, ((device_num) * sizeof(bpctl_dev_t)));
6788 for (idx = 0; tx_ctl_pci_tbl[idx].vendor; idx++) {
6789 while ((pdev1 = pci_get_subsys(tx_ctl_pci_tbl[idx].vendor,
6790 tx_ctl_pci_tbl[idx].device,
6791 tx_ctl_pci_tbl[idx].subvendor,
6792 tx_ctl_pci_tbl[idx].subdevice,
6794 bpctl_dev_arr[idx_dev].pdev = pdev1;
6796 mmio_start = pci_resource_start(pdev1, 0);
6797 mmio_len = pci_resource_len(pdev1, 0);
6799 bpctl_dev_arr[idx_dev].desc =
6800 dev_desc[tx_ctl_pci_tbl[idx].index].name;
6801 bpctl_dev_arr[idx_dev].name =
6802 tx_ctl_pci_tbl[idx].bp_name;
6803 bpctl_dev_arr[idx_dev].device =
6804 tx_ctl_pci_tbl[idx].device;
6805 bpctl_dev_arr[idx_dev].vendor =
6806 tx_ctl_pci_tbl[idx].vendor;
6807 bpctl_dev_arr[idx_dev].subdevice =
6808 tx_ctl_pci_tbl[idx].subdevice;
6809 bpctl_dev_arr[idx_dev].subvendor =
6810 tx_ctl_pci_tbl[idx].subvendor;
6811 /* bpctl_dev_arr[idx_dev].pdev=pdev1; */
6812 bpctl_dev_arr[idx_dev].func = PCI_FUNC(pdev1->devfn);
6813 bpctl_dev_arr[idx_dev].slot = PCI_SLOT(pdev1->devfn);
6814 bpctl_dev_arr[idx_dev].bus = pdev1->bus->number;
6815 bpctl_dev_arr[idx_dev].mem_map =
6816 (unsigned long)ioremap(mmio_start, mmio_len);
6818 spin_lock_init(&bpctl_dev_arr[idx_dev].bypass_wr_lock);
6820 if (BP10G9_IF_SERIES(bpctl_dev_arr[idx_dev].subdevice))
6821 bpctl_dev_arr[idx_dev].bp_10g9 = 1;
6822 if (BP10G_IF_SERIES(bpctl_dev_arr[idx_dev].subdevice))
6823 bpctl_dev_arr[idx_dev].bp_10g = 1;
6824 if (PEG540_IF_SERIES(bpctl_dev_arr[idx_dev].subdevice)) {
6826 bpctl_dev_arr[idx_dev].bp_540 = 1;
6828 if (PEGF5_IF_SERIES(bpctl_dev_arr[idx_dev].subdevice))
6829 bpctl_dev_arr[idx_dev].bp_fiber5 = 1;
6830 if (PEG80_IF_SERIES(bpctl_dev_arr[idx_dev].subdevice))
6831 bpctl_dev_arr[idx_dev].bp_i80 = 1;
6832 if (PEGF80_IF_SERIES(bpctl_dev_arr[idx_dev].subdevice))
6833 bpctl_dev_arr[idx_dev].bp_i80 = 1;
6834 if ((bpctl_dev_arr[idx_dev].subdevice & 0xa00) == 0xa00)
6835 bpctl_dev_arr[idx_dev].bp_i80 = 1;
6836 if (BP10GB_IF_SERIES(bpctl_dev_arr[idx_dev].subdevice)) {
6837 if (bpctl_dev_arr[idx_dev].ifindex == 0) {
6838 unregister_chrdev(major_num,
6841 ("Please load network driver for %s adapter!\n",
6842 bpctl_dev_arr[idx_dev].name);
6846 if (bpctl_dev_arr[idx_dev].ndev) {
6848 (bpctl_dev_arr[idx_dev].ndev->
6851 (bpctl_dev_arr[idx_dev].
6852 ndev->flags & IFF_UP)) {
6857 ("Please bring up network interfaces for %s adapter!\n",
6865 bpctl_dev_arr[idx_dev].bp_10gb = 1;
6868 if (!bpctl_dev_arr[idx_dev].bp_10g9) {
6870 if (is_bypass_fn(&bpctl_dev_arr[idx_dev])) {
6871 printk(KERN_INFO "%s found, ",
6872 bpctl_dev_arr[idx_dev].name);
6874 (bpctl_dev_arr[idx_dev].subdevice))
6877 (bpctl_dev_arr[idx_dev].
6879 bpctl_dev_arr[idx_dev].
6882 bpctl_dev_arr[idx_dev].
6884 bypass_fw_ver(&bpctl_dev_arr
6886 if ((bpctl_dev_arr[idx_dev].bp_10gb ==
6888 && (bpctl_dev_arr[idx_dev].
6889 bp_fw_ver == 0xff)) {
6904 bpctl_dev_arr[idx_dev].
6910 bpctl_dev_arr[idx_dev].
6922 /* bpctl_dev_arr[idx_dev].bp_fw_ver=0xa8; */
6923 printk("firmware version: 0x%x\n",
6924 bpctl_dev_arr[idx_dev].
6927 bpctl_dev_arr[idx_dev].wdt_status =
6929 bpctl_dev_arr[idx_dev].reset_time = 0;
6930 atomic_set(&bpctl_dev_arr[idx_dev].wdt_busy, 0);
6931 bpctl_dev_arr[idx_dev].bp_status_un = 1;
6933 bypass_caps_init(&bpctl_dev_arr[idx_dev]);
6935 init_bypass_wd_auto(&bpctl_dev_arr[idx_dev]);
6936 init_bypass_tpl_auto(&bpctl_dev_arr[idx_dev]);
6938 (bpctl_dev_arr[idx_dev].subdevice))
6939 reset_cont(&bpctl_dev_arr[idx_dev]);
6942 if ((bpctl_dev_arr[idx_dev].bp_tx_data =
6943 kmalloc(BPTEST_DATA_LEN, GFP_KERNEL))) {
6945 memset(bpctl_dev_arr[idx_dev].bp_tx_data, 0x0,
6948 memset(bpctl_dev_arr[idx_dev].bp_tx_data, 0xff,
6950 memset(bpctl_dev_arr[idx_dev].bp_tx_data + 6,
6952 memset(bpctl_dev_arr[idx_dev].bp_tx_data + 7,
6955 #if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,9))
6956 bpctl_dev_arr[idx_dev].bp_tx_data[12] =
6957 (ETH_P_BPTEST >> 8) & 0xff;
6958 bpctl_dev_arr[idx_dev].bp_tx_data[13] =
6959 ETH_P_BPTEST & 0xff;
6961 *(__be16 *) (bpctl_dev_arr[idx_dev].bp_tx_data +
6962 12) = htons(ETH_P_BPTEST);
6966 printk("bp_ctl: Memory allocation error!\n");
6974 sema_init(&bpctl_sema, 1);
6975 spin_lock_init(&bpvm_lock);
6978 bpctl_dev_t *pbpctl_dev_c = NULL;
6980 ((bpctl_dev_arr[idx_dev].pdev != NULL)
6981 && (idx_dev < device_num)); idx_dev++) {
6982 if (bpctl_dev_arr[idx_dev].bp_10g9) {
6984 get_status_port_fn(&bpctl_dev_arr[idx_dev]);
6985 if (is_bypass_fn(&bpctl_dev_arr[idx_dev])) {
6986 printk(KERN_INFO "%s found, ",
6987 bpctl_dev_arr[idx_dev].name);
6988 bpctl_dev_arr[idx_dev].bp_fw_ver =
6989 bypass_fw_ver(&bpctl_dev_arr
6991 printk("firmware version: 0x%x\n",
6992 bpctl_dev_arr[idx_dev].
6996 bpctl_dev_arr[idx_dev].wdt_status =
6998 bpctl_dev_arr[idx_dev].reset_time = 0;
6999 atomic_set(&bpctl_dev_arr[idx_dev].wdt_busy, 0);
7000 bpctl_dev_arr[idx_dev].bp_status_un = 1;
7002 bypass_caps_init(&bpctl_dev_arr[idx_dev]);
7004 init_bypass_wd_auto(&bpctl_dev_arr[idx_dev]);
7005 init_bypass_tpl_auto(&bpctl_dev_arr[idx_dev]);
7012 #if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0))
7013 inter_module_register("is_bypass_sd", THIS_MODULE, &is_bypass_sd);
7014 inter_module_register("get_bypass_slave_sd", THIS_MODULE,
7015 &get_bypass_slave_sd);
7016 inter_module_register("get_bypass_caps_sd", THIS_MODULE,
7017 &get_bypass_caps_sd);
7018 inter_module_register("get_wd_set_caps_sd", THIS_MODULE,
7019 &get_wd_set_caps_sd);
7020 inter_module_register("set_bypass_sd", THIS_MODULE, &set_bypass_sd);
7021 inter_module_register("get_bypass_sd", THIS_MODULE, &get_bypass_sd);
7022 inter_module_register("get_bypass_change_sd", THIS_MODULE,
7023 &get_bypass_change_sd);
7024 inter_module_register("set_dis_bypass_sd", THIS_MODULE,
7025 &set_dis_bypass_sd);
7026 inter_module_register("get_dis_bypass_sd", THIS_MODULE,
7027 &get_dis_bypass_sd);
7028 inter_module_register("set_bypass_pwoff_sd", THIS_MODULE,
7029 &set_bypass_pwoff_sd);
7030 inter_module_register("get_bypass_pwoff_sd", THIS_MODULE,
7031 &get_bypass_pwoff_sd);
7032 inter_module_register("set_bypass_pwup_sd", THIS_MODULE,
7033 &set_bypass_pwup_sd);
7034 inter_module_register("get_bypass_pwup_sd", THIS_MODULE,
7035 &get_bypass_pwup_sd);
7036 inter_module_register("get_bypass_wd_sd", THIS_MODULE,
7038 inter_module_register("set_bypass_wd_sd", THIS_MODULE,
7040 inter_module_register("get_wd_expire_time_sd", THIS_MODULE,
7041 &get_wd_expire_time_sd);
7042 inter_module_register("reset_bypass_wd_timer_sd", THIS_MODULE,
7043 &reset_bypass_wd_timer_sd);
7044 inter_module_register("set_std_nic_sd", THIS_MODULE, &set_std_nic_sd);
7045 inter_module_register("get_std_nic_sd", THIS_MODULE, &get_std_nic_sd);
7046 inter_module_register("set_tx_sd", THIS_MODULE, &set_tx_sd);
7047 inter_module_register("get_tx_sd", THIS_MODULE, &get_tx_sd);
7048 inter_module_register("set_tpl_sd", THIS_MODULE, &set_tpl_sd);
7049 inter_module_register("get_tpl_sd", THIS_MODULE, &get_tpl_sd);
7051 inter_module_register("set_bp_hw_reset_sd", THIS_MODULE,
7052 &set_bp_hw_reset_sd);
7053 inter_module_register("get_bp_hw_reset_sd", THIS_MODULE,
7054 &get_bp_hw_reset_sd);
7056 inter_module_register("set_tap_sd", THIS_MODULE, &set_tap_sd);
7057 inter_module_register("get_tap_sd", THIS_MODULE, &get_tap_sd);
7058 inter_module_register("get_tap_change_sd", THIS_MODULE,
7059 &get_tap_change_sd);
7060 inter_module_register("set_dis_tap_sd", THIS_MODULE, &set_dis_tap_sd);
7061 inter_module_register("get_dis_tap_sd", THIS_MODULE, &get_dis_tap_sd);
7062 inter_module_register("set_tap_pwup_sd", THIS_MODULE, &set_tap_pwup_sd);
7063 inter_module_register("get_tap_pwup_sd", THIS_MODULE, &get_tap_pwup_sd);
7064 inter_module_register("set_bp_disc_sd", THIS_MODULE, &set_bp_disc_sd);
7065 inter_module_register("get_bp_disc_sd", THIS_MODULE, &get_bp_disc_sd);
7066 inter_module_register("get_bp_disc_change_sd", THIS_MODULE,
7067 &get_bp_disc_change_sd);
7068 inter_module_register("set_bp_dis_disc_sd", THIS_MODULE,
7069 &set_bp_dis_disc_sd);
7070 inter_module_register("get_bp_dis_disc_sd", THIS_MODULE,
7071 &get_bp_dis_disc_sd);
7072 inter_module_register("set_bp_disc_pwup_sd", THIS_MODULE,
7073 &set_bp_disc_pwup_sd);
7074 inter_module_register("get_bp_disc_pwup_sd", THIS_MODULE,
7075 &get_bp_disc_pwup_sd);
7076 inter_module_register("set_wd_exp_mode_sd", THIS_MODULE,
7077 &set_wd_exp_mode_sd);
7078 inter_module_register("get_wd_exp_mode_sd", THIS_MODULE,
7079 &get_wd_exp_mode_sd);
7080 inter_module_register("set_wd_autoreset_sd", THIS_MODULE,
7081 &set_wd_autoreset_sd);
7082 inter_module_register("get_wd_autoreset_sd", THIS_MODULE,
7083 &get_wd_autoreset_sd);
7084 inter_module_register("get_bypass_info_sd", THIS_MODULE,
7085 &get_bypass_info_sd);
7086 inter_module_register("bp_if_scan_sd", THIS_MODULE, &bp_if_scan_sd);
7089 register_netdevice_notifier(&bp_notifier_block);
7090 #ifdef BP_PROC_SUPPORT
7093 /* unsigned long flags; */
7094 /* rcu_read_lock(); */
7096 for (i = 0; i < device_num; i++) {
7097 if (bpctl_dev_arr[i].ifindex) {
7098 /* spin_lock_irqsave(&bpvm_lock, flags); */
7099 bypass_proc_remove_dev_sd(&bpctl_dev_arr[i]);
7100 bypass_proc_create_dev_sd(&bpctl_dev_arr[i]);
7101 /* spin_unlock_irqrestore(&bpvm_lock, flags); */
7105 /* rcu_read_unlock(); */
7113 * Cleanup - unregister the appropriate file from /proc
7115 static void __exit bypass_cleanup_module(void)
7118 #if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23))
7121 unregister_netdevice_notifier(&bp_notifier_block);
7123 #if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0))
7124 inter_module_unregister("is_bypass_sd");
7125 inter_module_unregister("get_bypass_slave_sd");
7126 inter_module_unregister("get_bypass_caps_sd");
7127 inter_module_unregister("get_wd_set_caps_sd");
7128 inter_module_unregister("set_bypass_sd");
7129 inter_module_unregister("get_bypass_sd");
7130 inter_module_unregister("get_bypass_change_sd");
7131 inter_module_unregister("set_dis_bypass_sd");
7132 inter_module_unregister("get_dis_bypass_sd");
7133 inter_module_unregister("set_bypass_pwoff_sd");
7134 inter_module_unregister("get_bypass_pwoff_sd");
7135 inter_module_unregister("set_bypass_pwup_sd");
7136 inter_module_unregister("get_bypass_pwup_sd");
7137 inter_module_unregister("set_bypass_wd_sd");
7138 inter_module_unregister("get_bypass_wd_sd");
7139 inter_module_unregister("get_wd_expire_time_sd");
7140 inter_module_unregister("reset_bypass_wd_timer_sd");
7141 inter_module_unregister("set_std_nic_sd");
7142 inter_module_unregister("get_std_nic_sd");
7143 inter_module_unregister("set_tx_sd");
7144 inter_module_unregister("get_tx_sd");
7145 inter_module_unregister("set_tpl_sd");
7146 inter_module_unregister("get_tpl_sd");
7147 inter_module_unregister("set_tap_sd");
7148 inter_module_unregister("get_tap_sd");
7149 inter_module_unregister("get_tap_change_sd");
7150 inter_module_unregister("set_dis_tap_sd");
7151 inter_module_unregister("get_dis_tap_sd");
7152 inter_module_unregister("set_tap_pwup_sd");
7153 inter_module_unregister("get_tap_pwup_sd");
7154 inter_module_unregister("set_bp_disc_sd");
7155 inter_module_unregister("get_bp_disc_sd");
7156 inter_module_unregister("get_bp_disc_change_sd");
7157 inter_module_unregister("set_bp_dis_disc_sd");
7158 inter_module_unregister("get_bp_dis_disc_sd");
7159 inter_module_unregister("set_bp_disc_pwup_sd");
7160 inter_module_unregister("get_bp_disc_pwup_sd");
7161 inter_module_unregister("set_wd_exp_mode_sd");
7162 inter_module_unregister("get_wd_exp_mode_sd");
7163 inter_module_unregister("set_wd_autoreset_sd");
7164 inter_module_unregister("get_wd_autoreset_sd");
7165 inter_module_unregister("get_bypass_info_sd");
7166 inter_module_unregister("bp_if_scan_sd");
7170 for (i = 0; i < device_num; i++) {
7171 /* unsigned long flags; */
7172 #ifdef BP_PROC_SUPPORT
7173 /* spin_lock_irqsave(&bpvm_lock, flags);
7175 bypass_proc_remove_dev_sd(&bpctl_dev_arr[i]);
7176 /* spin_unlock_irqrestore(&bpvm_lock, flags);
7177 rcu_read_unlock(); */
7179 remove_bypass_wd_auto(&bpctl_dev_arr[i]);
7180 bpctl_dev_arr[i].reset_time = 0;
7182 remove_bypass_tpl_auto(&bpctl_dev_arr[i]);
7185 /* unmap all devices */
7186 for (i = 0; i < device_num; i++) {
7188 if (bpctl_dev_arr[i].bp_tx_data)
7189 kfree(bpctl_dev_arr[i].bp_tx_data);
7191 iounmap((void *)(bpctl_dev_arr[i].mem_map));
7194 /* free all devices space */
7196 kfree(bpctl_dev_arr);
7199 * Unregister the device
7201 #if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23))
7202 ret = unregister_chrdev(major_num, DEVICE_NAME);
7204 * If there's an error, report it
7207 printk("Error in module_unregister_chrdev: %d\n", ret);
7209 unregister_chrdev(major_num, DEVICE_NAME);
7214 module_init(bypass_init_module);
7215 module_exit(bypass_cleanup_module);
7217 int is_bypass_sd(int ifindex)
7219 return is_bypass(get_dev_idx_p(ifindex));
7222 int set_bypass_sd(int ifindex, int bypass_mode)
7225 return set_bypass_fn(get_dev_idx_p(ifindex), bypass_mode);
7228 int get_bypass_sd(int ifindex)
7231 return get_bypass_fn(get_dev_idx_p(ifindex));
7234 int get_bypass_change_sd(int ifindex)
7237 return get_bypass_change_fn(get_dev_idx_p(ifindex));
7240 int set_dis_bypass_sd(int ifindex, int dis_param)
7242 return set_dis_bypass_fn(get_dev_idx_p(ifindex), dis_param);
7245 int get_dis_bypass_sd(int ifindex)
7248 return get_dis_bypass_fn(get_dev_idx_p(ifindex));
7251 int set_bypass_pwoff_sd(int ifindex, int bypass_mode)
7253 return set_bypass_pwoff_fn(get_dev_idx_p(ifindex), bypass_mode);
7257 int get_bypass_pwoff_sd(int ifindex)
7259 return get_bypass_pwoff_fn(get_dev_idx_p(ifindex));
7263 int set_bypass_pwup_sd(int ifindex, int bypass_mode)
7265 return set_bypass_pwup_fn(get_dev_idx_p(ifindex), bypass_mode);
7269 int get_bypass_pwup_sd(int ifindex)
7271 return get_bypass_pwup_fn(get_dev_idx_p(ifindex));
7275 int set_bypass_wd_sd(int if_index, int ms_timeout, int *ms_timeout_set)
7277 if ((is_bypass(get_dev_idx_p(if_index))) <= 0)
7279 *ms_timeout_set = set_bypass_wd_fn(get_dev_idx_p(if_index), ms_timeout);
7283 int get_bypass_wd_sd(int ifindex, int *timeout)
7285 return get_bypass_wd_fn(get_dev_idx_p(ifindex), timeout);
7289 int get_wd_expire_time_sd(int ifindex, int *time_left)
7291 return get_wd_expire_time_fn(get_dev_idx_p(ifindex), time_left);
7294 int reset_bypass_wd_timer_sd(int ifindex)
7296 return reset_bypass_wd_timer_fn(get_dev_idx_p(ifindex));
7300 int get_wd_set_caps_sd(int ifindex)
7302 return get_wd_set_caps_fn(get_dev_idx_p(ifindex));
7306 int set_std_nic_sd(int ifindex, int nic_mode)
7308 return set_std_nic_fn(get_dev_idx_p(ifindex), nic_mode);
7312 int get_std_nic_sd(int ifindex)
7314 return get_std_nic_fn(get_dev_idx_p(ifindex));
7318 int set_tap_sd(int ifindex, int tap_mode)
7320 return set_tap_fn(get_dev_idx_p(ifindex), tap_mode);
7324 int get_tap_sd(int ifindex)
7326 return get_tap_fn(get_dev_idx_p(ifindex));
7330 int set_tap_pwup_sd(int ifindex, int tap_mode)
7332 return set_tap_pwup_fn(get_dev_idx_p(ifindex), tap_mode);
7336 int get_tap_pwup_sd(int ifindex)
7338 return get_tap_pwup_fn(get_dev_idx_p(ifindex));
7342 int get_tap_change_sd(int ifindex)
7344 return get_tap_change_fn(get_dev_idx_p(ifindex));
7348 int set_dis_tap_sd(int ifindex, int dis_param)
7350 return set_dis_tap_fn(get_dev_idx_p(ifindex), dis_param);
7354 int get_dis_tap_sd(int ifindex)
7356 return get_dis_tap_fn(get_dev_idx_p(ifindex));
7360 int set_bp_disc_sd(int ifindex, int disc_mode)
7362 return set_disc_fn(get_dev_idx_p(ifindex), disc_mode);
7366 int get_bp_disc_sd(int ifindex)
7368 return get_disc_fn(get_dev_idx_p(ifindex));
7372 int set_bp_disc_pwup_sd(int ifindex, int disc_mode)
7374 return set_disc_pwup_fn(get_dev_idx_p(ifindex), disc_mode);
7378 int get_bp_disc_pwup_sd(int ifindex)
7380 return get_disc_pwup_fn(get_dev_idx_p(ifindex));
7384 int get_bp_disc_change_sd(int ifindex)
7386 return get_disc_change_fn(get_dev_idx_p(ifindex));
7390 int set_bp_dis_disc_sd(int ifindex, int dis_param)
7392 return set_dis_disc_fn(get_dev_idx_p(ifindex), dis_param);
7396 int get_bp_dis_disc_sd(int ifindex)
7398 return get_dis_disc_fn(get_dev_idx_p(ifindex));
7402 int get_wd_exp_mode_sd(int ifindex)
7404 return get_wd_exp_mode_fn(get_dev_idx_p(ifindex));
7407 int set_wd_exp_mode_sd(int ifindex, int param)
7409 return set_wd_exp_mode_fn(get_dev_idx_p(ifindex), param);
7413 int reset_cont_sd(int ifindex)
7415 return reset_cont_fn(get_dev_idx_p(ifindex));
7419 int set_tx_sd(int ifindex, int tx_state)
7421 return set_tx_fn(get_dev_idx_p(ifindex), tx_state);
7425 int set_tpl_sd(int ifindex, int tpl_state)
7427 return set_tpl_fn(get_dev_idx_p(ifindex), tpl_state);
7431 int set_bp_hw_reset_sd(int ifindex, int status)
7433 return set_bp_hw_reset_fn(get_dev_idx_p(ifindex), status);
7437 int set_wd_autoreset_sd(int ifindex, int param)
7439 return set_wd_autoreset_fn(get_dev_idx_p(ifindex), param);
7443 int get_wd_autoreset_sd(int ifindex)
7445 return get_wd_autoreset_fn(get_dev_idx_p(ifindex));
7449 int get_bypass_caps_sd(int ifindex)
7451 return get_bypass_caps_fn(get_dev_idx_p(ifindex));
7454 int get_bypass_slave_sd(int ifindex)
7456 bpctl_dev_t *pbpctl_dev_out;
7457 int ret = get_bypass_slave_fn(get_dev_idx_p(ifindex), &pbpctl_dev_out);
7459 return pbpctl_dev_out->ifindex;
7464 int get_tx_sd(int ifindex)
7466 return get_tx_fn(get_dev_idx_p(ifindex));
7470 int get_tpl_sd(int ifindex)
7472 return get_tpl_fn(get_dev_idx_p(ifindex));
7476 int get_bp_hw_reset_sd(int ifindex)
7478 return get_bp_hw_reset_fn(get_dev_idx_p(ifindex));
7482 int get_bypass_info_sd(int ifindex, struct bp_info *bp_info)
7484 return get_bypass_info_fn(get_dev_idx_p(ifindex), bp_info->prod_name, &bp_info->fw_ver);
7487 int bp_if_scan_sd(void)
7493 EXPORT_SYMBOL_NOVERS(is_bypass_sd);
7494 EXPORT_SYMBOL_NOVERS(get_bypass_slave_sd);
7495 EXPORT_SYMBOL_NOVERS(get_bypass_caps_sd);
7496 EXPORT_SYMBOL_NOVERS(get_wd_set_caps_sd);
7497 EXPORT_SYMBOL_NOVERS(set_bypass_sd);
7498 EXPORT_SYMBOL_NOVERS(get_bypass_sd);
7499 EXPORT_SYMBOL_NOVERS(get_bypass_change_sd);
7500 EXPORT_SYMBOL_NOVERS(set_dis_bypass_sd);
7501 EXPORT_SYMBOL_NOVERS(get_dis_bypass_sd);
7502 EXPORT_SYMBOL_NOVERS(set_bypass_pwoff_sd);
7503 EXPORT_SYMBOL_NOVERS(get_bypass_pwoff_sd);
7504 EXPORT_SYMBOL_NOVERS(set_bypass_pwup_sd);
7505 EXPORT_SYMBOL_NOVERS(get_bypass_pwup_sd);
7506 EXPORT_SYMBOL_NOVERS(set_bypass_wd_sd);
7507 EXPORT_SYMBOL_NOVERS(get_bypass_wd_sd);
7508 EXPORT_SYMBOL_NOVERS(get_wd_expire_time_sd);
7509 EXPORT_SYMBOL_NOVERS(reset_bypass_wd_timer_sd);
7510 EXPORT_SYMBOL_NOVERS(set_std_nic_sd);
7511 EXPORT_SYMBOL_NOVERS(get_std_nic_sd);
7512 EXPORT_SYMBOL_NOVERS(set_tx_sd);
7513 EXPORT_SYMBOL_NOVERS(get_tx_sd);
7514 EXPORT_SYMBOL_NOVERS(set_tpl_sd);
7515 EXPORT_SYMBOL_NOVERS(get_tpl_sd);
7516 EXPORT_SYMBOL_NOVERS(set_bp_hw_reset_sd);
7517 EXPORT_SYMBOL_NOVERS(get_bp_hw_reset_sd);
7518 EXPORT_SYMBOL_NOVERS(set_tap_sd);
7519 EXPORT_SYMBOL_NOVERS(get_tap_sd);
7520 EXPORT_SYMBOL_NOVERS(get_tap_change_sd);
7521 EXPORT_SYMBOL_NOVERS(set_dis_tap_sd);
7522 EXPORT_SYMBOL_NOVERS(get_dis_tap_sd);
7523 EXPORT_SYMBOL_NOVERS(set_tap_pwup_sd);
7524 EXPORT_SYMBOL_NOVERS(get_tap_pwup_sd);
7525 EXPORT_SYMBOL_NOVERS(set_wd_exp_mode_sd);
7526 EXPORT_SYMBOL_NOVERS(get_wd_exp_mode_sd);
7527 EXPORT_SYMBOL_NOVERS(set_wd_autoreset_sd);
7528 EXPORT_SYMBOL_NOVERS(get_wd_autoreset_sd);
7529 EXPORT_SYMBOL_NOVERS(set_bp_disc_sd);
7530 EXPORT_SYMBOL_NOVERS(get_bp_disc_sd);
7531 EXPORT_SYMBOL_NOVERS(get_bp_disc_change_sd);
7532 EXPORT_SYMBOL_NOVERS(set_bp_dis_disc_sd);
7533 EXPORT_SYMBOL_NOVERS(get_bp_dis_disc_sd);
7534 EXPORT_SYMBOL_NOVERS(set_bp_disc_pwup_sd);
7535 EXPORT_SYMBOL_NOVERS(get_bp_disc_pwup_sd);
7536 EXPORT_SYMBOL_NOVERS(get_bypass_info_sd);
7537 EXPORT_SYMBOL_NOVERS(bp_if_scan_sd);
7539 #define BP_PROC_DIR "bypass"
7541 #define GPIO6_SET_ENTRY_SD "gpio6_set"
7542 #define GPIO6_CLEAR_ENTRY_SD "gpio6_clear"
7544 #define GPIO7_SET_ENTRY_SD "gpio7_set"
7545 #define GPIO7_CLEAR_ENTRY_SD "gpio7_clear"
7547 #define PULSE_SET_ENTRY_SD "pulse_set"
7548 #define ZERO_SET_ENTRY_SD "zero_set"
7549 #define PULSE_GET1_ENTRY_SD "pulse_get1"
7550 #define PULSE_GET2_ENTRY_SD "pulse_get2"
7552 #define CMND_ON_ENTRY_SD "cmnd_on"
7553 #define CMND_OFF_ENTRY_SD "cmnd_off"
7554 #define RESET_CONT_ENTRY_SD "reset_cont"
7557 #define BYPASS_INFO_ENTRY_SD "bypass_info"
7558 #define BYPASS_SLAVE_ENTRY_SD "bypass_slave"
7559 #define BYPASS_CAPS_ENTRY_SD "bypass_caps"
7560 #define WD_SET_CAPS_ENTRY_SD "wd_set_caps"
7561 #define BYPASS_ENTRY_SD "bypass"
7562 #define BYPASS_CHANGE_ENTRY_SD "bypass_change"
7563 #define BYPASS_WD_ENTRY_SD "bypass_wd"
7564 #define WD_EXPIRE_TIME_ENTRY_SD "wd_expire_time"
7565 #define RESET_BYPASS_WD_ENTRY_SD "reset_bypass_wd"
7566 #define DIS_BYPASS_ENTRY_SD "dis_bypass"
7567 #define BYPASS_PWUP_ENTRY_SD "bypass_pwup"
7568 #define BYPASS_PWOFF_ENTRY_SD "bypass_pwoff"
7569 #define STD_NIC_ENTRY_SD "std_nic"
7570 #define STD_NIC_ENTRY_SD "std_nic"
7571 #define TAP_ENTRY_SD "tap"
7572 #define TAP_CHANGE_ENTRY_SD "tap_change"
7573 #define DIS_TAP_ENTRY_SD "dis_tap"
7574 #define TAP_PWUP_ENTRY_SD "tap_pwup"
7575 #define TWO_PORT_LINK_ENTRY_SD "two_port_link"
7576 #define WD_EXP_MODE_ENTRY_SD "wd_exp_mode"
7577 #define WD_AUTORESET_ENTRY_SD "wd_autoreset"
7578 #define TPL_ENTRY_SD "tpl"
7579 #define WAIT_AT_PWUP_ENTRY_SD "wait_at_pwup"
7580 #define HW_RESET_ENTRY_SD "hw_reset"
7581 #define DISC_ENTRY_SD "disc"
7582 #define DISC_CHANGE_ENTRY_SD "disc_change"
7583 #define DIS_DISC_ENTRY_SD "dis_disc"
7584 #define DISC_PWUP_ENTRY_SD "disc_pwup"
7585 static struct proc_dir_entry *bp_procfs_dir;
7587 static struct proc_dir_entry *proc_getdir(char *name,
7588 struct proc_dir_entry *proc_dir)
7590 struct proc_dir_entry *pde = proc_dir;
7592 for (pde = pde->subdir; pde; pde = pde->next) {
7593 if (pde->namelen && (strcmp(name, pde->name) == 0)) {
7594 /* directory exists */
7598 if (pde == (struct proc_dir_entry *)0) {
7599 /* create the directory */
7600 #if (LINUX_VERSION_CODE > 0x20300)
7601 pde = proc_mkdir(name, proc_dir);
7603 pde = create_proc_entry(name, S_IFDIR, proc_dir);
7605 if (pde == (struct proc_dir_entry *)0) {
7614 int bp_proc_create(void)
7616 bp_procfs_dir = proc_getdir(BP_PROC_DIR, init_net.proc_net);
7617 if (bp_procfs_dir == (struct proc_dir_entry *)0) {
7619 "Could not create procfs nicinfo directory %s\n",
7627 bypass_proc_create_entry_sd(struct pfs_unit_sd *pfs_unit_curr,
7629 write_proc_t *write_proc,
7630 read_proc_t *read_proc,
7631 struct proc_dir_entry *parent_pfs, void *data)
7633 strcpy(pfs_unit_curr->proc_name, proc_name);
7634 pfs_unit_curr->proc_entry = create_proc_entry(pfs_unit_curr->proc_name,
7637 S_IROTH, parent_pfs);
7638 if (pfs_unit_curr->proc_entry == NULL)
7641 pfs_unit_curr->proc_entry->read_proc = read_proc;
7642 pfs_unit_curr->proc_entry->write_proc = write_proc;
7643 pfs_unit_curr->proc_entry->data = data;
7650 get_bypass_info_pfs(char *page, char **start, off_t off, int count,
7651 int *eof, void *data)
7653 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7656 len += sprintf(page, "Name\t\t\t%s\n", pbp_device_block->name);
7658 sprintf(page + len, "Firmware version\t0x%x\n",
7659 pbp_device_block->bp_fw_ver);
7666 get_bypass_slave_pfs(char *page, char **start, off_t off, int count,
7667 int *eof, void *data)
7669 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7672 bpctl_dev_t *pbp_device_block_slave = NULL;
7674 struct net_device *net_slave_dev = NULL;
7676 if ((pbp_device_block->func == 0) || (pbp_device_block->func == 2)) {
7678 ((bpctl_dev_arr[idx_dev].pdev != NULL)
7679 && (idx_dev < device_num)); idx_dev++) {
7680 if ((bpctl_dev_arr[idx_dev].bus ==
7681 pbp_device_block->bus)
7682 && (bpctl_dev_arr[idx_dev].slot ==
7683 pbp_device_block->slot)) {
7684 if ((pbp_device_block->func == 0)
7685 && (bpctl_dev_arr[idx_dev].func == 1)) {
7686 pbp_device_block_slave =
7687 &bpctl_dev_arr[idx_dev];
7690 if ((pbp_device_block->func == 2) &&
7691 (bpctl_dev_arr[idx_dev].func == 3)) {
7692 pbp_device_block_slave =
7693 &bpctl_dev_arr[idx_dev];
7699 pbp_device_block_slave = pbp_device_block;
7700 if (!pbp_device_block_slave) {
7701 len = sprintf(page, "fail\n");
7705 net_slave_dev = pbp_device_block_slave->ndev;
7706 if (net_slave_dev) {
7708 len = sprintf(page, "%s\n", net_slave_dev->name);
7710 len = sprintf(page, "fail\n");
7719 get_bypass_caps_pfs(char *page, char **start, off_t off, int count,
7720 int *eof, void *data)
7722 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7724 int len = 0, ret = 0;
7726 ret = get_bypass_caps_fn(pbp_device_block);
7727 if (ret == BP_NOT_CAP)
7728 len = sprintf(page, "-1\n");
7730 len = sprintf(page, "0x%x\n", ret);
7737 get_wd_set_caps_pfs(char *page, char **start, off_t off, int count,
7738 int *eof, void *data)
7740 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7742 int len = 0, ret = 0;
7744 ret = get_wd_set_caps_fn(pbp_device_block);
7745 if (ret == BP_NOT_CAP)
7746 len = sprintf(page, "-1\n");
7748 len = sprintf(page, "0x%x\n", ret);
7754 set_bypass_pfs(struct file *file, const char *buffer,
7755 unsigned long count, void *data)
7759 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7761 int bypass_param = 0, length = 0;
7763 if (count > (sizeof(kbuf) - 1))
7766 if (copy_from_user(&kbuf, buffer, count)) {
7771 length = strlen(kbuf);
7772 if (kbuf[length - 1] == '\n')
7773 kbuf[--length] = '\0';
7775 if (strcmp(kbuf, "on") == 0)
7777 else if (strcmp(kbuf, "off") == 0)
7780 set_bypass_fn(pbp_device_block, bypass_param);
7786 set_tap_pfs(struct file *file, const char *buffer,
7787 unsigned long count, void *data)
7791 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7793 int tap_param = 0, length = 0;
7795 if (count > (sizeof(kbuf) - 1))
7798 if (copy_from_user(&kbuf, buffer, count)) {
7803 length = strlen(kbuf);
7804 if (kbuf[length - 1] == '\n')
7805 kbuf[--length] = '\0';
7807 if (strcmp(kbuf, "on") == 0)
7809 else if (strcmp(kbuf, "off") == 0)
7812 set_tap_fn(pbp_device_block, tap_param);
7818 set_disc_pfs(struct file *file, const char *buffer,
7819 unsigned long count, void *data)
7823 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7825 int tap_param = 0, length = 0;
7827 if (count > (sizeof(kbuf) - 1))
7830 if (copy_from_user(&kbuf, buffer, count)) {
7835 length = strlen(kbuf);
7836 if (kbuf[length - 1] == '\n')
7837 kbuf[--length] = '\0';
7839 if (strcmp(kbuf, "on") == 0)
7841 else if (strcmp(kbuf, "off") == 0)
7844 set_disc_fn(pbp_device_block, tap_param);
7850 get_bypass_pfs(char *page, char **start, off_t off, int count,
7851 int *eof, void *data)
7853 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7855 int len = 0, ret = 0;
7857 ret = get_bypass_fn(pbp_device_block);
7858 if (ret == BP_NOT_CAP)
7859 len = sprintf(page, "fail\n");
7861 len = sprintf(page, "on\n");
7863 len = sprintf(page, "off\n");
7870 get_tap_pfs(char *page, char **start, off_t off, int count,
7871 int *eof, void *data)
7873 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7875 int len = 0, ret = 0;
7877 ret = get_tap_fn(pbp_device_block);
7878 if (ret == BP_NOT_CAP)
7879 len = sprintf(page, "fail\n");
7881 len = sprintf(page, "on\n");
7883 len = sprintf(page, "off\n");
7890 get_disc_pfs(char *page, char **start, off_t off, int count,
7891 int *eof, void *data)
7893 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7895 int len = 0, ret = 0;
7897 ret = get_disc_fn(pbp_device_block);
7898 if (ret == BP_NOT_CAP)
7899 len = sprintf(page, "fail\n");
7901 len = sprintf(page, "on\n");
7903 len = sprintf(page, "off\n");
7910 get_bypass_change_pfs(char *page, char **start, off_t off, int count,
7911 int *eof, void *data)
7913 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7915 int len = 0, ret = 0;
7917 ret = get_bypass_change_fn(pbp_device_block);
7919 len = sprintf(page, "on\n");
7921 len = sprintf(page, "off\n");
7923 len = sprintf(page, "fail\n");
7930 get_tap_change_pfs(char *page, char **start, off_t off, int count,
7931 int *eof, void *data)
7933 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7935 int len = 0, ret = 0;
7937 ret = get_tap_change_fn(pbp_device_block);
7939 len = sprintf(page, "on\n");
7941 len = sprintf(page, "off\n");
7943 len = sprintf(page, "fail\n");
7950 get_disc_change_pfs(char *page, char **start, off_t off, int count,
7951 int *eof, void *data)
7953 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7955 int len = 0, ret = 0;
7957 ret = get_disc_change_fn(pbp_device_block);
7959 len = sprintf(page, "on\n");
7961 len = sprintf(page, "off\n");
7963 len = sprintf(page, "fail\n");
7969 #define isdigit(c) (c >= '0' && c <= '9')
7970 __inline static int atoi(char **s)
7973 while (isdigit(**s))
7974 i = i * 10 + *((*s)++) - '0';
7979 set_bypass_wd_pfs(struct file *file, const char *buffer,
7980 unsigned long count, void *data)
7982 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7986 ret = kstrtoint_from_user(buffer, count, 10, &timeout);
7989 set_bypass_wd_fn(pbp_device_block, timeout);
7995 get_bypass_wd_pfs(char *page, char **start, off_t off, int count,
7996 int *eof, void *data)
7998 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8000 int len = 0, ret = 0, timeout = 0;
8002 ret = get_bypass_wd_fn(pbp_device_block, &timeout);
8003 if (ret == BP_NOT_CAP)
8004 len = sprintf(page, "fail\n");
8005 else if (timeout == -1)
8006 len = sprintf(page, "unknown\n");
8007 else if (timeout == 0)
8008 len = sprintf(page, "disable\n");
8010 len = sprintf(page, "%d\n", timeout);
8017 get_wd_expire_time_pfs(char *page, char **start, off_t off, int count,
8018 int *eof, void *data)
8020 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8022 int len = 0, ret = 0, timeout = 0;
8024 ret = get_wd_expire_time_fn(pbp_device_block, &timeout);
8025 if (ret == BP_NOT_CAP)
8026 len = sprintf(page, "fail\n");
8027 else if (timeout == -1)
8028 len = sprintf(page, "expire\n");
8029 else if (timeout == 0)
8030 len = sprintf(page, "disable\n");
8033 len = sprintf(page, "%d\n", timeout);
8039 get_tpl_pfs(char *page, char **start, off_t off, int count,
8040 int *eof, void *data)
8042 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8044 int len = 0, ret = 0;
8046 ret = get_tpl_fn(pbp_device_block);
8047 if (ret == BP_NOT_CAP)
8048 len = sprintf(page, "fail\n");
8050 len = sprintf(page, "on\n");
8052 len = sprintf(page, "off\n");
8060 get_wait_at_pwup_pfs(char *page, char **start, off_t off, int count,
8061 int *eof, void *data)
8063 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8065 int len = 0, ret = 0;
8067 ret = get_bp_wait_at_pwup_fn(pbp_device_block);
8068 if (ret == BP_NOT_CAP)
8069 len = sprintf(page, "fail\n");
8071 len = sprintf(page, "on\n");
8073 len = sprintf(page, "off\n");
8080 get_hw_reset_pfs(char *page, char **start, off_t off, int count,
8081 int *eof, void *data)
8083 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8085 int len = 0, ret = 0;
8087 ret = get_bp_hw_reset_fn(pbp_device_block);
8088 if (ret == BP_NOT_CAP)
8089 len = sprintf(page, "fail\n");
8091 len = sprintf(page, "on\n");
8093 len = sprintf(page, "off\n");
8099 #endif /*PMC_WAIT_FLAG */
8102 reset_bypass_wd_pfs(char *page, char **start, off_t off, int count,
8103 int *eof, void *data)
8105 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8107 int len = 0, ret = 0;
8109 ret = reset_bypass_wd_timer_fn(pbp_device_block);
8110 if (ret == BP_NOT_CAP)
8111 len = sprintf(page, "fail\n");
8113 len = sprintf(page, "disable\n");
8115 len = sprintf(page, "success\n");
8122 set_dis_bypass_pfs(struct file *file, const char *buffer,
8123 unsigned long count, void *data)
8127 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8129 int bypass_param = 0, length = 0;
8131 if (count >= sizeof(kbuf))
8134 if (copy_from_user(&kbuf, buffer, count)) {
8139 length = strlen(kbuf);
8140 if (kbuf[length - 1] == '\n')
8141 kbuf[--length] = '\0';
8143 if (strcmp(kbuf, "on") == 0)
8145 else if (strcmp(kbuf, "off") == 0)
8148 set_dis_bypass_fn(pbp_device_block, bypass_param);
8154 set_dis_tap_pfs(struct file *file, const char *buffer,
8155 unsigned long count, void *data)
8159 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8161 int tap_param = 0, length = 0;
8163 if (count >= sizeof(kbuf))
8166 if (copy_from_user(&kbuf, buffer, count)) {
8171 length = strlen(kbuf);
8172 if (kbuf[length - 1] == '\n')
8173 kbuf[--length] = '\0';
8175 if (strcmp(kbuf, "on") == 0)
8177 else if (strcmp(kbuf, "off") == 0)
8180 set_dis_tap_fn(pbp_device_block, tap_param);
8186 set_dis_disc_pfs(struct file *file, const char *buffer,
8187 unsigned long count, void *data)
8191 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8193 int tap_param = 0, length = 0;
8195 if (count >= sizeof(kbuf))
8198 if (copy_from_user(&kbuf, buffer, count)) {
8203 length = strlen(kbuf);
8204 if (kbuf[length - 1] == '\n')
8205 kbuf[--length] = '\0';
8207 if (strcmp(kbuf, "on") == 0)
8209 else if (strcmp(kbuf, "off") == 0)
8212 set_dis_disc_fn(pbp_device_block, tap_param);
8218 get_dis_bypass_pfs(char *page, char **start, off_t off, int count,
8219 int *eof, void *data)
8221 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8223 int len = 0, ret = 0;
8225 ret = get_dis_bypass_fn(pbp_device_block);
8226 if (ret == BP_NOT_CAP)
8227 len = sprintf(page, "fail\n");
8229 len = sprintf(page, "off\n");
8231 len = sprintf(page, "on\n");
8238 get_dis_tap_pfs(char *page, char **start, off_t off, int count,
8239 int *eof, void *data)
8241 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8243 int len = 0, ret = 0;
8245 ret = get_dis_tap_fn(pbp_device_block);
8246 if (ret == BP_NOT_CAP)
8247 len = sprintf(page, "fail\n");
8249 len = sprintf(page, "off\n");
8251 len = sprintf(page, "on\n");
8258 get_dis_disc_pfs(char *page, char **start, off_t off, int count,
8259 int *eof, void *data)
8261 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8263 int len = 0, ret = 0;
8265 ret = get_dis_disc_fn(pbp_device_block);
8266 if (ret == BP_NOT_CAP)
8267 len = sprintf(page, "fail\n");
8269 len = sprintf(page, "off\n");
8271 len = sprintf(page, "on\n");
8278 set_bypass_pwup_pfs(struct file *file, const char *buffer,
8279 unsigned long count, void *data)
8283 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8285 int bypass_param = 0, length = 0;
8287 if (count >= sizeof(kbuf))
8290 if (copy_from_user(&kbuf, buffer, count)) {
8295 length = strlen(kbuf);
8296 if (kbuf[length - 1] == '\n')
8297 kbuf[--length] = '\0';
8299 if (strcmp(kbuf, "on") == 0)
8301 else if (strcmp(kbuf, "off") == 0)
8304 set_bypass_pwup_fn(pbp_device_block, bypass_param);
8310 set_bypass_pwoff_pfs(struct file *file, const char *buffer,
8311 unsigned long count, void *data)
8315 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8317 int bypass_param = 0, length = 0;
8319 if (count >= sizeof(kbuf))
8322 if (copy_from_user(&kbuf, buffer, count)) {
8327 length = strlen(kbuf);
8328 if (kbuf[length - 1] == '\n')
8329 kbuf[--length] = '\0';
8331 if (strcmp(kbuf, "on") == 0)
8333 else if (strcmp(kbuf, "off") == 0)
8336 set_bypass_pwoff_fn(pbp_device_block, bypass_param);
8342 set_tap_pwup_pfs(struct file *file, const char *buffer,
8343 unsigned long count, void *data)
8347 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8349 int tap_param = 0, length = 0;
8351 if (count >= sizeof(kbuf))
8354 if (copy_from_user(&kbuf, buffer, count)) {
8359 length = strlen(kbuf);
8360 if (kbuf[length - 1] == '\n')
8361 kbuf[--length] = '\0';
8363 if (strcmp(kbuf, "on") == 0)
8365 else if (strcmp(kbuf, "off") == 0)
8368 set_tap_pwup_fn(pbp_device_block, tap_param);
8374 set_disc_pwup_pfs(struct file *file, const char *buffer,
8375 unsigned long count, void *data)
8379 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8381 int tap_param = 0, length = 0;
8383 if (count >= sizeof(kbuf))
8386 if (copy_from_user(&kbuf, buffer, count)) {
8391 length = strlen(kbuf);
8392 if (kbuf[length - 1] == '\n')
8393 kbuf[--length] = '\0';
8395 if (strcmp(kbuf, "on") == 0)
8397 else if (strcmp(kbuf, "off") == 0)
8400 set_disc_pwup_fn(pbp_device_block, tap_param);
8406 get_bypass_pwup_pfs(char *page, char **start, off_t off, int count,
8407 int *eof, void *data)
8409 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8411 int len = 0, ret = 0;
8413 ret = get_bypass_pwup_fn(pbp_device_block);
8414 if (ret == BP_NOT_CAP)
8415 len = sprintf(page, "fail\n");
8417 len = sprintf(page, "off\n");
8419 len = sprintf(page, "on\n");
8426 get_bypass_pwoff_pfs(char *page, char **start, off_t off, int count,
8427 int *eof, void *data)
8429 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8431 int len = 0, ret = 0;
8433 ret = get_bypass_pwoff_fn(pbp_device_block);
8434 if (ret == BP_NOT_CAP)
8435 len = sprintf(page, "fail\n");
8437 len = sprintf(page, "off\n");
8439 len = sprintf(page, "on\n");
8446 get_tap_pwup_pfs(char *page, char **start, off_t off, int count,
8447 int *eof, void *data)
8449 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8451 int len = 0, ret = 0;
8453 ret = get_tap_pwup_fn(pbp_device_block);
8454 if (ret == BP_NOT_CAP)
8455 len = sprintf(page, "fail\n");
8457 len = sprintf(page, "off\n");
8459 len = sprintf(page, "on\n");
8466 get_disc_pwup_pfs(char *page, char **start, off_t off, int count,
8467 int *eof, void *data)
8469 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8471 int len = 0, ret = 0;
8473 ret = get_disc_pwup_fn(pbp_device_block);
8474 if (ret == BP_NOT_CAP)
8475 len = sprintf(page, "fail\n");
8477 len = sprintf(page, "off\n");
8479 len = sprintf(page, "on\n");
8486 set_std_nic_pfs(struct file *file, const char *buffer,
8487 unsigned long count, void *data)
8491 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8493 int bypass_param = 0, length = 0;
8495 if (count >= sizeof(kbuf))
8498 if (copy_from_user(&kbuf, buffer, count)) {
8503 length = strlen(kbuf);
8504 if (kbuf[length - 1] == '\n')
8505 kbuf[--length] = '\0';
8507 if (strcmp(kbuf, "on") == 0)
8509 else if (strcmp(kbuf, "off") == 0)
8512 set_std_nic_fn(pbp_device_block, bypass_param);
8518 get_std_nic_pfs(char *page, char **start, off_t off, int count,
8519 int *eof, void *data)
8521 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8523 int len = 0, ret = 0;
8525 ret = get_std_nic_fn(pbp_device_block);
8526 if (ret == BP_NOT_CAP)
8527 len = sprintf(page, "fail\n");
8529 len = sprintf(page, "off\n");
8531 len = sprintf(page, "on\n");
8538 get_wd_exp_mode_pfs(char *page, char **start, off_t off, int count,
8539 int *eof, void *data)
8541 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8543 int len = 0, ret = 0;
8545 ret = get_wd_exp_mode_fn(pbp_device_block);
8547 len = sprintf(page, "tap\n");
8549 len = sprintf(page, "bypass\n");
8551 len = sprintf(page, "disc\n");
8554 len = sprintf(page, "fail\n");
8561 set_wd_exp_mode_pfs(struct file *file, const char *buffer,
8562 unsigned long count, void *data)
8566 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8568 int bypass_param = 0, length = 0;
8570 if (count > (sizeof(kbuf) - 1))
8573 if (copy_from_user(&kbuf, buffer, count)) {
8578 length = strlen(kbuf);
8579 if (kbuf[length - 1] == '\n')
8580 kbuf[--length] = '\0';
8582 if (strcmp(kbuf, "tap") == 0)
8584 else if (strcmp(kbuf, "bypass") == 0)
8586 else if (strcmp(kbuf, "disc") == 0)
8589 set_wd_exp_mode_fn(pbp_device_block, bypass_param);
8595 get_wd_autoreset_pfs(char *page, char **start, off_t off, int count,
8596 int *eof, void *data)
8598 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8600 int len = 0, ret = 0;
8602 ret = get_wd_autoreset_fn(pbp_device_block);
8604 len = sprintf(page, "%d\n", ret);
8606 len = sprintf(page, "fail\n");
8613 set_wd_autoreset_pfs(struct file *file, const char *buffer,
8614 unsigned long count, void *data)
8616 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8620 ret = kstrtoint_from_user(buffer, count, 10, &timeout);
8623 set_wd_autoreset_fn(pbp_device_block, timeout);
8629 set_tpl_pfs(struct file *file, const char *buffer,
8630 unsigned long count, void *data)
8634 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8636 int tpl_param = 0, length = 0;
8638 if (count > (sizeof(kbuf) - 1))
8641 if (copy_from_user(&kbuf, buffer, count)) {
8646 length = strlen(kbuf);
8647 if (kbuf[length - 1] == '\n')
8648 kbuf[--length] = '\0';
8650 if (strcmp(kbuf, "on") == 0)
8652 else if (strcmp(kbuf, "off") == 0)
8655 set_tpl_fn(pbp_device_block, tpl_param);
8662 set_wait_at_pwup_pfs(struct file *file, const char *buffer,
8663 unsigned long count, void *data)
8667 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8669 int tpl_param = 0, length = 0;
8671 if (count > (sizeof(kbuf) - 1))
8674 if (copy_from_user(&kbuf, buffer, count)) {
8679 length = strlen(kbuf);
8680 if (kbuf[length - 1] == '\n')
8681 kbuf[--length] = '\0';
8683 if (strcmp(kbuf, "on") == 0)
8685 else if (strcmp(kbuf, "off") == 0)
8688 set_bp_wait_at_pwup_fn(pbp_device_block, tpl_param);
8694 set_hw_reset_pfs(struct file *file, const char *buffer,
8695 unsigned long count, void *data)
8699 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8701 int tpl_param = 0, length = 0;
8703 if (count > (sizeof(kbuf) - 1))
8706 if (copy_from_user(&kbuf, buffer, count)) {
8711 length = strlen(kbuf);
8712 if (kbuf[length - 1] == '\n')
8713 kbuf[--length] = '\0';
8715 if (strcmp(kbuf, "on") == 0)
8717 else if (strcmp(kbuf, "off") == 0)
8720 set_bp_hw_reset_fn(pbp_device_block, tpl_param);
8725 #endif /*PMC_FIX_FLAG */
8727 int bypass_proc_create_dev_sd(bpctl_dev_t *pbp_device_block)
8729 struct bypass_pfs_sd *current_pfs = &(pbp_device_block->bypass_pfs_set);
8730 static struct proc_dir_entry *procfs_dir = NULL;
8733 if (!pbp_device_block->ndev)
8735 sprintf(current_pfs->dir_name, "bypass_%s",
8736 pbp_device_block->ndev->name);
8741 /* create device proc dir */
8742 procfs_dir = proc_getdir(current_pfs->dir_name, bp_procfs_dir);
8743 if (procfs_dir == 0) {
8744 printk(KERN_DEBUG "Could not create procfs directory %s\n",
8745 current_pfs->dir_name);
8748 current_pfs->bypass_entry = procfs_dir;
8750 if (bypass_proc_create_entry_sd(&(current_pfs->bypass_info), BYPASS_INFO_ENTRY_SD, NULL, /* write */
8751 get_bypass_info_pfs, /* read */
8752 procfs_dir, pbp_device_block))
8755 if (pbp_device_block->bp_caps & SW_CTL_CAP) {
8757 /* Create set param proc's */
8758 if (bypass_proc_create_entry_sd(&(current_pfs->bypass_slave), BYPASS_SLAVE_ENTRY_SD, NULL, /* write */
8759 get_bypass_slave_pfs, /* read */
8760 procfs_dir, pbp_device_block))
8763 if (bypass_proc_create_entry_sd(&(current_pfs->bypass_caps), BYPASS_CAPS_ENTRY_SD, NULL, /* write */
8764 get_bypass_caps_pfs, /* read */
8765 procfs_dir, pbp_device_block))
8768 if (bypass_proc_create_entry_sd(&(current_pfs->wd_set_caps), WD_SET_CAPS_ENTRY_SD, NULL, /* write */
8769 get_wd_set_caps_pfs, /* read */
8770 procfs_dir, pbp_device_block))
8772 if (bypass_proc_create_entry_sd(&(current_pfs->bypass_wd), BYPASS_WD_ENTRY_SD, set_bypass_wd_pfs, /* write */
8773 get_bypass_wd_pfs, /* read */
8774 procfs_dir, pbp_device_block))
8777 if (bypass_proc_create_entry_sd(&(current_pfs->wd_expire_time), WD_EXPIRE_TIME_ENTRY_SD, NULL, /* write */
8778 get_wd_expire_time_pfs, /* read */
8779 procfs_dir, pbp_device_block))
8782 if (bypass_proc_create_entry_sd(&(current_pfs->reset_bypass_wd), RESET_BYPASS_WD_ENTRY_SD, NULL, /* write */
8783 reset_bypass_wd_pfs, /* read */
8784 procfs_dir, pbp_device_block))
8787 if (bypass_proc_create_entry_sd(&(current_pfs->std_nic), STD_NIC_ENTRY_SD, set_std_nic_pfs, /* write */
8788 get_std_nic_pfs, /* read */
8789 procfs_dir, pbp_device_block))
8792 if (pbp_device_block->bp_caps & BP_CAP) {
8793 if (bypass_proc_create_entry_sd(&(current_pfs->bypass), BYPASS_ENTRY_SD, set_bypass_pfs, /* write */
8794 get_bypass_pfs, /* read */
8799 if (bypass_proc_create_entry_sd(&(current_pfs->dis_bypass), DIS_BYPASS_ENTRY_SD, set_dis_bypass_pfs, /* write */
8800 get_dis_bypass_pfs, /* read */
8805 if (bypass_proc_create_entry_sd(&(current_pfs->bypass_pwup), BYPASS_PWUP_ENTRY_SD, set_bypass_pwup_pfs, /* write */
8806 get_bypass_pwup_pfs, /* read */
8810 if (bypass_proc_create_entry_sd(&(current_pfs->bypass_pwoff), BYPASS_PWOFF_ENTRY_SD, set_bypass_pwoff_pfs, /* write */
8811 get_bypass_pwoff_pfs, /* read */
8816 if (bypass_proc_create_entry_sd(&(current_pfs->bypass_change), BYPASS_CHANGE_ENTRY_SD, NULL, /* write */
8817 get_bypass_change_pfs, /* read */
8823 if (pbp_device_block->bp_caps & TAP_CAP) {
8825 if (bypass_proc_create_entry_sd(&(current_pfs->tap), TAP_ENTRY_SD, set_tap_pfs, /* write */
8826 get_tap_pfs, /* read */
8831 if (bypass_proc_create_entry_sd(&(current_pfs->dis_tap), DIS_TAP_ENTRY_SD, set_dis_tap_pfs, /* write */
8832 get_dis_tap_pfs, /* read */
8837 if (bypass_proc_create_entry_sd(&(current_pfs->tap_pwup), TAP_PWUP_ENTRY_SD, set_tap_pwup_pfs, /* write */
8838 get_tap_pwup_pfs, /* read */
8843 if (bypass_proc_create_entry_sd(&(current_pfs->tap_change), TAP_CHANGE_ENTRY_SD, NULL, /* write */
8844 get_tap_change_pfs, /* read */
8849 if (pbp_device_block->bp_caps & DISC_CAP) {
8851 if (bypass_proc_create_entry_sd(&(current_pfs->tap), DISC_ENTRY_SD, set_disc_pfs, /* write */
8852 get_disc_pfs, /* read */
8858 if (bypass_proc_create_entry_sd(&(current_pfs->dis_tap), DIS_DISC_ENTRY_SD, set_dis_disc_pfs, /* write */
8859 get_dis_disc_pfs, /* read */
8865 if (bypass_proc_create_entry_sd(&(current_pfs->tap_pwup), DISC_PWUP_ENTRY_SD, set_disc_pwup_pfs, /* write */
8866 get_disc_pwup_pfs, /* read */
8871 if (bypass_proc_create_entry_sd(&(current_pfs->tap_change), DISC_CHANGE_ENTRY_SD, NULL, /* write */
8872 get_disc_change_pfs, /* read */
8878 if (bypass_proc_create_entry_sd(&(current_pfs->wd_exp_mode), WD_EXP_MODE_ENTRY_SD, set_wd_exp_mode_pfs, /* write */
8879 get_wd_exp_mode_pfs, /* read */
8880 procfs_dir, pbp_device_block))
8883 if (bypass_proc_create_entry_sd(&(current_pfs->wd_autoreset), WD_AUTORESET_ENTRY_SD, set_wd_autoreset_pfs, /* write */
8884 get_wd_autoreset_pfs, /* read */
8885 procfs_dir, pbp_device_block))
8887 if (bypass_proc_create_entry_sd(&(current_pfs->tpl), TPL_ENTRY_SD, set_tpl_pfs, /* write */
8888 get_tpl_pfs, /* read */
8889 procfs_dir, pbp_device_block))
8892 if (bypass_proc_create_entry_sd(&(current_pfs->tpl), WAIT_AT_PWUP_ENTRY_SD, set_wait_at_pwup_pfs, /* write */
8893 get_wait_at_pwup_pfs, /* read */
8894 procfs_dir, pbp_device_block))
8896 if (bypass_proc_create_entry_sd(&(current_pfs->tpl), HW_RESET_ENTRY_SD, set_hw_reset_pfs, /* write */
8897 get_hw_reset_pfs, /* read */
8898 procfs_dir, pbp_device_block))
8905 printk(KERN_DEBUG "Create proc entry failed\n");
8910 int bypass_proc_remove_dev_sd(bpctl_dev_t *pbp_device_block)
8913 struct bypass_pfs_sd *current_pfs = &pbp_device_block->bypass_pfs_set;
8914 struct proc_dir_entry *pde = current_pfs->bypass_entry, *pde_curr =
8920 for (pde = pde->subdir; pde;) {
8921 strcpy(name, pde->name);
8924 remove_proc_entry(name, current_pfs->bypass_entry);
8927 remove_proc_entry(current_pfs->dir_name, bp_procfs_dir);
8928 current_pfs->bypass_entry = NULL;