2 * SBE 2T3E3 synchronous serial card driver for Linux
4 * Copyright (C) 2009-2010 Krzysztof Halasa <khc@pm.waw.pl>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of version 2 of the GNU General Public License
8 * as published by the Free Software Foundation.
10 * This code is based on a driver written by SBE Inc.
13 #include <linux/netdevice.h>
14 #include <linux/types.h>
15 #include <linux/errno.h>
20 void dc_init(struct channel *sc)
25 /*dc_reset(sc);*/ /* do not want to reset here */
30 val = SBE_2T3E3_21143_VAL_READ_LINE_ENABLE |
31 SBE_2T3E3_21143_VAL_READ_MULTIPLE_ENABLE |
32 SBE_2T3E3_21143_VAL_TRANSMIT_AUTOMATIC_POLLING_200us |
33 SBE_2T3E3_21143_VAL_BUS_ARBITRATION_RR;
35 if (sc->h.command & 16)
36 val |= SBE_2T3E3_21143_VAL_WRITE_AND_INVALIDATE_ENABLE;
38 switch (sc->h.cache_size) {
40 val |= SBE_2T3E3_21143_VAL_CACHE_ALIGNMENT_32;
43 val |= SBE_2T3E3_21143_VAL_CACHE_ALIGNMENT_16;
46 val |= SBE_2T3E3_21143_VAL_CACHE_ALIGNMENT_8;
52 dc_write(sc->addr, SBE_2T3E3_21143_REG_BUS_MODE, val);
54 /* OPERATION_MODE (CSR6) */
55 val = SBE_2T3E3_21143_VAL_RECEIVE_ALL |
56 SBE_2T3E3_21143_VAL_MUST_BE_ONE |
57 SBE_2T3E3_21143_VAL_THRESHOLD_CONTROL_BITS_1 |
58 SBE_2T3E3_21143_VAL_LOOPBACK_OFF |
59 SBE_2T3E3_21143_VAL_PASS_ALL_MULTICAST |
60 SBE_2T3E3_21143_VAL_PROMISCUOUS_MODE |
61 SBE_2T3E3_21143_VAL_PASS_BAD_FRAMES;
62 dc_write(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE, val);
63 if (sc->p.loopback == SBE_2T3E3_LOOPBACK_ETHERNET)
64 sc->p.loopback = SBE_2T3E3_LOOPBACK_NONE;
67 * GENERAL_PURPOSE_TIMER_AND_INTERRUPT_MITIGATION_CONTROL (CSR11)
69 val = SBE_2T3E3_21143_VAL_CYCLE_SIZE |
70 SBE_2T3E3_21143_VAL_TRANSMIT_TIMER |
71 SBE_2T3E3_21143_VAL_NUMBER_OF_TRANSMIT_PACKETS |
72 SBE_2T3E3_21143_VAL_RECEIVE_TIMER |
73 SBE_2T3E3_21143_VAL_NUMBER_OF_RECEIVE_PACKETS;
74 dc_write(sc->addr, SBE_2T3E3_21143_REG_GENERAL_PURPOSE_TIMER_AND_INTERRUPT_MITIGATION_CONTROL, val);
76 /* prepare descriptors and data for receive and transmit processes */
77 if (dc_init_descriptor_list(sc) != 0)
80 /* clear ethernet interrupts status */
81 dc_write(sc->addr, SBE_2T3E3_21143_REG_STATUS, 0xFFFFFFFF);
83 /* SIA mode registers */
84 dc_set_output_port(sc);
87 void dc_start(struct channel *sc)
91 if (!(sc->r.flags & SBE_2T3E3_FLAG_NETWORK_UP))
96 /* get actual LOS and OOF status */
97 switch (sc->p.frame_type) {
98 case SBE_2T3E3_FRAME_TYPE_E3_G751:
99 case SBE_2T3E3_FRAME_TYPE_E3_G832:
100 val = exar7250_read(sc, SBE_2T3E3_FRAMER_REG_E3_RX_CONFIGURATION_STATUS_2);
101 dev_dbg(&sc->pdev->dev, "Start Framer Rx Status = %02X\n", val);
102 sc->s.OOF = val & SBE_2T3E3_FRAMER_VAL_E3_RX_OOF ? 1 : 0;
104 case SBE_2T3E3_FRAME_TYPE_T3_CBIT:
105 case SBE_2T3E3_FRAME_TYPE_T3_M13:
106 val = exar7250_read(sc, SBE_2T3E3_FRAMER_REG_T3_RX_CONFIGURATION_STATUS);
107 dev_dbg(&sc->pdev->dev, "Start Framer Rx Status = %02X\n", val);
108 sc->s.OOF = val & SBE_2T3E3_FRAMER_VAL_T3_RX_OOF ? 1 : 0;
115 /* start receive and transmit processes */
116 dc_transmitter_onoff(sc, SBE_2T3E3_ON);
117 dc_receiver_onoff(sc, SBE_2T3E3_ON);
119 /* start interrupts */
123 #define MAX_INT_WAIT_CNT 12000
124 void dc_stop(struct channel *sc)
128 /* stop receive and transmit processes */
129 dc_receiver_onoff(sc, SBE_2T3E3_OFF);
130 dc_transmitter_onoff(sc, SBE_2T3E3_OFF);
132 /* turn off ethernet interrupts */
135 /* wait to ensure the interrupts have been completed */
136 for (wcnt = 0; wcnt < MAX_INT_WAIT_CNT; wcnt++) {
138 if (!sc->interrupt_active)
141 if (wcnt >= MAX_INT_WAIT_CNT)
142 dev_warn(&sc->pdev->dev, "SBE 2T3E3: Interrupt active too long\n");
144 /* clear all receive/transmit data */
145 dc_drop_descriptor_list(sc);
148 void dc_start_intr(struct channel *sc)
150 if (sc->p.loopback == SBE_2T3E3_LOOPBACK_NONE && sc->s.OOF)
153 if (sc->p.receiver_on || sc->p.transmitter_on) {
154 if (!sc->ether.interrupt_enable_mask)
155 dc_write(sc->addr, SBE_2T3E3_21143_REG_STATUS, 0xFFFFFFFF);
157 sc->ether.interrupt_enable_mask =
158 SBE_2T3E3_21143_VAL_NORMAL_INTERRUPT_SUMMARY_ENABLE |
159 SBE_2T3E3_21143_VAL_ABNORMAL_INTERRUPT_SUMMARY_ENABLE |
160 SBE_2T3E3_21143_VAL_RECEIVE_STOPPED_ENABLE |
161 SBE_2T3E3_21143_VAL_RECEIVE_BUFFER_UNAVAILABLE_ENABLE |
162 SBE_2T3E3_21143_VAL_RECEIVE_INTERRUPT_ENABLE |
163 SBE_2T3E3_21143_VAL_TRANSMIT_UNDERFLOW_INTERRUPT_ENABLE |
164 SBE_2T3E3_21143_VAL_TRANSMIT_BUFFER_UNAVAILABLE_ENABLE |
165 SBE_2T3E3_21143_VAL_TRANSMIT_STOPPED_ENABLE |
166 SBE_2T3E3_21143_VAL_TRANSMIT_INTERRUPT_ENABLE;
168 dc_write(sc->addr, SBE_2T3E3_21143_REG_INTERRUPT_ENABLE,
169 sc->ether.interrupt_enable_mask);
173 void dc_stop_intr(struct channel *sc)
175 sc->ether.interrupt_enable_mask = 0;
176 dc_write(sc->addr, SBE_2T3E3_21143_REG_INTERRUPT_ENABLE, 0);
179 void dc_reset(struct channel *sc)
181 /* turn off ethernet interrupts */
182 dc_write(sc->addr, SBE_2T3E3_21143_REG_INTERRUPT_ENABLE, 0);
183 dc_write(sc->addr, SBE_2T3E3_21143_REG_STATUS, 0xFFFFFFFF);
186 dc_set_bits(sc->addr, SBE_2T3E3_21143_REG_BUS_MODE,
187 SBE_2T3E3_21143_VAL_SOFTWARE_RESET);
188 udelay(4); /* 50 PCI cycles < 2us */
190 /* clear hardware configuration */
191 dc_write(sc->addr, SBE_2T3E3_21143_REG_BUS_MODE, 0);
193 /* clear software configuration */
194 dc_write(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE, 0);
196 /* turn off SIA reset */
197 dc_set_bits(sc->addr, SBE_2T3E3_21143_REG_SIA_CONNECTIVITY,
198 SBE_2T3E3_21143_VAL_SIA_RESET);
199 dc_write(sc->addr, SBE_2T3E3_21143_REG_SIA_TRANSMIT_AND_RECEIVE, 0);
200 dc_write(sc->addr, SBE_2T3E3_21143_REG_SIA_AND_GENERAL_PURPOSE_PORT, 0);
204 void dc_receiver_onoff(struct channel *sc, u32 mode)
208 if (sc->p.receiver_on == mode)
213 if (dc_read(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE) &
214 SBE_2T3E3_21143_VAL_RECEIVE_START) {
215 dc_clear_bits(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE,
216 SBE_2T3E3_21143_VAL_RECEIVE_START);
218 for (i = 0; i < 16; i++) {
219 state = dc_read(sc->addr, SBE_2T3E3_21143_REG_STATUS) &
220 SBE_2T3E3_21143_VAL_RECEIVE_PROCESS_STATE;
221 if (state == SBE_2T3E3_21143_VAL_RX_STOPPED)
225 if (state != SBE_2T3E3_21143_VAL_RX_STOPPED)
226 dev_warn(&sc->pdev->dev, "SBE 2T3E3: Rx failed to stop\n");
228 dev_info(&sc->pdev->dev, "SBE 2T3E3: Rx off\n");
232 dc_set_bits(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE,
233 SBE_2T3E3_21143_VAL_RECEIVE_START);
235 dc_write(sc->addr, SBE_2T3E3_21143_REG_RECEIVE_POLL_DEMAND, 0xFFFFFFFF);
241 sc->p.receiver_on = mode;
244 void dc_transmitter_onoff(struct channel *sc, u32 mode)
248 if (sc->p.transmitter_on == mode)
253 if (dc_read(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE) &
254 SBE_2T3E3_21143_VAL_TRANSMISSION_START) {
255 dc_clear_bits(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE,
256 SBE_2T3E3_21143_VAL_TRANSMISSION_START);
258 for (i = 0; i < 16; i++) {
259 state = dc_read(sc->addr, SBE_2T3E3_21143_REG_STATUS) &
260 SBE_2T3E3_21143_VAL_TRANSMISSION_PROCESS_STATE;
261 if (state == SBE_2T3E3_21143_VAL_TX_STOPPED)
265 if (state != SBE_2T3E3_21143_VAL_TX_STOPPED)
266 dev_warn(&sc->pdev->dev, "SBE 2T3E3: Tx failed to stop\n");
270 dc_set_bits(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE,
271 SBE_2T3E3_21143_VAL_TRANSMISSION_START);
273 dc_write(sc->addr, SBE_2T3E3_21143_REG_TRANSMIT_POLL_DEMAND, 0xFFFFFFFF);
279 sc->p.transmitter_on = mode;
284 void dc_set_loopback(struct channel *sc, u32 mode)
289 case SBE_2T3E3_21143_VAL_LOOPBACK_OFF:
290 case SBE_2T3E3_21143_VAL_LOOPBACK_INTERNAL:
296 /* select loopback mode */
297 val = dc_read(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE) &
298 ~SBE_2T3E3_21143_VAL_OPERATING_MODE;
300 dc_write(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE, val);
302 if (mode == SBE_2T3E3_21143_VAL_LOOPBACK_OFF)
303 dc_set_bits(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE,
304 SBE_2T3E3_21143_VAL_FULL_DUPLEX_MODE);
306 dc_clear_bits(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE,
307 SBE_2T3E3_21143_VAL_FULL_DUPLEX_MODE);
310 u32 dc_init_descriptor_list(struct channel *sc)
315 if (sc->ether.rx_ring == NULL)
316 sc->ether.rx_ring = kzalloc(SBE_2T3E3_RX_DESC_RING_SIZE *
317 sizeof(t3e3_rx_desc_t), GFP_KERNEL);
318 if (sc->ether.rx_ring == NULL) {
319 dev_err(&sc->pdev->dev, "SBE 2T3E3: no buffer space for RX ring\n");
323 if (sc->ether.tx_ring == NULL)
324 sc->ether.tx_ring = kzalloc(SBE_2T3E3_TX_DESC_RING_SIZE *
325 sizeof(t3e3_tx_desc_t), GFP_KERNEL);
326 if (sc->ether.tx_ring == NULL) {
327 kfree(sc->ether.rx_ring);
328 sc->ether.rx_ring = NULL;
329 dev_err(&sc->pdev->dev, "SBE 2T3E3: no buffer space for RX ring\n");
337 for (i = 0; i < SBE_2T3E3_RX_DESC_RING_SIZE; i++) {
338 sc->ether.rx_ring[i].rdes0 = SBE_2T3E3_RX_DESC_21143_OWN;
339 sc->ether.rx_ring[i].rdes1 =
340 SBE_2T3E3_RX_DESC_SECOND_ADDRESS_CHAINED | SBE_2T3E3_MTU;
342 if (sc->ether.rx_data[i] == NULL) {
343 if (!(m = dev_alloc_skb(MCLBYTES))) {
344 for (j = 0; j < i; j++) {
345 dev_kfree_skb_any(sc->ether.rx_data[j]);
346 sc->ether.rx_data[j] = NULL;
348 kfree(sc->ether.rx_ring);
349 sc->ether.rx_ring = NULL;
350 kfree(sc->ether.tx_ring);
351 sc->ether.tx_ring = NULL;
352 dev_err(&sc->pdev->dev, "SBE 2T3E3: token_alloc err:"
353 " no buffer space for RX ring\n");
356 sc->ether.rx_data[i] = m;
358 sc->ether.rx_ring[i].rdes2 = virt_to_phys(sc->ether.rx_data[i]->data);
360 sc->ether.rx_ring[i].rdes3 = virt_to_phys(
361 &sc->ether.rx_ring[(i + 1) % SBE_2T3E3_RX_DESC_RING_SIZE]);
363 sc->ether.rx_ring[SBE_2T3E3_RX_DESC_RING_SIZE - 1].rdes1 |=
364 SBE_2T3E3_RX_DESC_END_OF_RING;
365 sc->ether.rx_ring_current_read = 0;
367 dc_write(sc->addr, SBE_2T3E3_21143_REG_RECEIVE_LIST_BASE_ADDRESS,
368 virt_to_phys(&sc->ether.rx_ring[0]));
373 for (i = 0; i < SBE_2T3E3_TX_DESC_RING_SIZE; i++) {
374 sc->ether.tx_ring[i].tdes0 = 0;
375 sc->ether.tx_ring[i].tdes1 = SBE_2T3E3_TX_DESC_SECOND_ADDRESS_CHAINED |
376 SBE_2T3E3_TX_DESC_DISABLE_PADDING;
378 sc->ether.tx_ring[i].tdes2 = 0;
379 sc->ether.tx_data[i] = NULL;
381 sc->ether.tx_ring[i].tdes3 = virt_to_phys(
382 &sc->ether.tx_ring[(i + 1) % SBE_2T3E3_TX_DESC_RING_SIZE]);
384 sc->ether.tx_ring[SBE_2T3E3_TX_DESC_RING_SIZE - 1].tdes1 |=
385 SBE_2T3E3_TX_DESC_END_OF_RING;
387 dc_write(sc->addr, SBE_2T3E3_21143_REG_TRANSMIT_LIST_BASE_ADDRESS,
388 virt_to_phys(&sc->ether.tx_ring[0]));
389 sc->ether.tx_ring_current_read = 0;
390 sc->ether.tx_ring_current_write = 0;
391 sc->ether.tx_free_cnt = SBE_2T3E3_TX_DESC_RING_SIZE;
392 spin_lock_init(&sc->ether.tx_lock);
397 void dc_clear_descriptor_list(struct channel *sc)
401 /* clear CSR3 and CSR4 */
402 dc_write(sc->addr, SBE_2T3E3_21143_REG_RECEIVE_LIST_BASE_ADDRESS, 0);
403 dc_write(sc->addr, SBE_2T3E3_21143_REG_TRANSMIT_LIST_BASE_ADDRESS, 0);
405 /* free all data buffers on TX ring */
406 for (i = 0; i < SBE_2T3E3_TX_DESC_RING_SIZE; i++) {
407 if (sc->ether.tx_data[i] != NULL) {
408 dev_kfree_skb_any(sc->ether.tx_data[i]);
409 sc->ether.tx_data[i] = NULL;
414 void dc_drop_descriptor_list(struct channel *sc)
418 dc_clear_descriptor_list(sc);
420 /* free all data buffers on RX ring */
421 for (i = 0; i < SBE_2T3E3_RX_DESC_RING_SIZE; i++) {
422 if (sc->ether.rx_data[i] != NULL) {
423 dev_kfree_skb_any(sc->ether.rx_data[i]);
424 sc->ether.rx_data[i] = NULL;
428 kfree(sc->ether.rx_ring);
429 sc->ether.rx_ring = NULL;
430 kfree(sc->ether.tx_ring);
431 sc->ether.tx_ring = NULL;
435 void dc_set_output_port(struct channel *sc)
437 dc_clear_bits(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE,
438 SBE_2T3E3_21143_VAL_PORT_SELECT);
440 dc_write(sc->addr, SBE_2T3E3_21143_REG_SIA_STATUS, 0x00000301);
441 dc_write(sc->addr, SBE_2T3E3_21143_REG_SIA_CONNECTIVITY, 0);
442 dc_write(sc->addr, SBE_2T3E3_21143_REG_SIA_TRANSMIT_AND_RECEIVE, 0);
443 dc_write(sc->addr, SBE_2T3E3_21143_REG_SIA_AND_GENERAL_PURPOSE_PORT, 0x08000011);
445 dc_set_bits(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE,
446 SBE_2T3E3_21143_VAL_TRANSMIT_THRESHOLD_MODE_100Mbs |
447 SBE_2T3E3_21143_VAL_HEARTBEAT_DISABLE |
448 SBE_2T3E3_21143_VAL_PORT_SELECT |
449 SBE_2T3E3_21143_VAL_FULL_DUPLEX_MODE);
452 void dc_restart(struct channel *sc)
454 dev_warn(&sc->pdev->dev, "SBE 2T3E3: 21143 restart\n");
458 dc_init(sc); /* stop + reset + init */