Pileus Git - ~andy/linux/blob - drivers/staging/rts_pstor/sd.c

   1 /* Driver for Realtek PCI-Express card reader
   2  *
   3  * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License as published by the
   7  * Free Software Foundation; either version 2, or (at your option) any
   8  * later version.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program; if not, see <http://www.gnu.org/licenses/>.
  17  *
  18  * Author:
  19  *   wwang (wei_wang@realsil.com.cn)
  20  *   No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
  21  */
  22
  23 #include <linux/blkdev.h>
  24 #include <linux/kthread.h>
  25 #include <linux/sched.h>
  26
  27 #include "rtsx.h"
  28 #include "rtsx_transport.h"
  29 #include "rtsx_scsi.h"
  30 #include "rtsx_card.h"
  31 #include "sd.h"
  32
  33 #define SD_MAX_RETRY_COUNT      3
  34
  35 static u16 REG_SD_CFG1;
  36 static u16 REG_SD_CFG2;
  37 static u16 REG_SD_CFG3;
  38 static u16 REG_SD_STAT1;
  39 static u16 REG_SD_STAT2;
  40 static u16 REG_SD_BUS_STAT;
  41 static u16 REG_SD_PAD_CTL;
  42 static u16 REG_SD_SAMPLE_POINT_CTL;
  43 static u16 REG_SD_PUSH_POINT_CTL;
  44 static u16 REG_SD_CMD0;
  45 static u16 REG_SD_CMD1;
  46 static u16 REG_SD_CMD2;
  47 static u16 REG_SD_CMD3;
  48 static u16 REG_SD_CMD4;
  49 static u16 REG_SD_CMD5;
  50 static u16 REG_SD_BYTE_CNT_L;
  51 static u16 REG_SD_BYTE_CNT_H;
  52 static u16 REG_SD_BLOCK_CNT_L;
  53 static u16 REG_SD_BLOCK_CNT_H;
  54 static u16 REG_SD_TRANSFER;
  55 static u16 REG_SD_VPCLK0_CTL;
  56 static u16 REG_SD_VPCLK1_CTL;
  57 static u16 REG_SD_DCMPS0_CTL;
  58 static u16 REG_SD_DCMPS1_CTL;
  59
  60 static inline void sd_set_err_code(struct rtsx_chip *chip, u8 err_code)
  61 {
  62         struct sd_info *sd_card = &(chip->sd_card);
  63
  64         sd_card->err_code |= err_code;
  65 }
  66
  67 static inline void sd_clr_err_code(struct rtsx_chip *chip)
  68 {
  69         struct sd_info *sd_card = &(chip->sd_card);
  70
  71         sd_card->err_code = 0;
  72 }
  73
  74 static inline int sd_check_err_code(struct rtsx_chip *chip, u8 err_code)
  75 {
  76         struct sd_info *sd_card = &(chip->sd_card);
  77
  78         return sd_card->err_code & err_code;
  79 }
  80
  81 static void sd_init_reg_addr(struct rtsx_chip *chip)
  82 {
  83         if (CHECK_PID(chip, 0x5209)) {
  84                 REG_SD_CFG1 = SD_CFG1;
  85                 REG_SD_CFG2 = SD_CFG2;
  86                 REG_SD_CFG3 = SD_CFG3;
  87                 REG_SD_STAT1 = SD_STAT1;
  88                 REG_SD_STAT2 = SD_STAT2;
  89                 REG_SD_BUS_STAT = SD_BUS_STAT;
  90                 REG_SD_PAD_CTL = SD_PAD_CTL;
  91                 REG_SD_SAMPLE_POINT_CTL = SD_SAMPLE_POINT_CTL;
  92                 REG_SD_PUSH_POINT_CTL = SD_PUSH_POINT_CTL;
  93                 REG_SD_CMD0 = SD_CMD0;
  94                 REG_SD_CMD1 = SD_CMD1;
  95                 REG_SD_CMD2 = SD_CMD2;
  96                 REG_SD_CMD3 = SD_CMD3;
  97                 REG_SD_CMD4 = SD_CMD4;
  98                 REG_SD_CMD5 = SD_CMD5;
  99                 REG_SD_BYTE_CNT_L = SD_BYTE_CNT_L;
 100                 REG_SD_BYTE_CNT_H = SD_BYTE_CNT_H;
 101                 REG_SD_BLOCK_CNT_L = SD_BLOCK_CNT_L;
 102                 REG_SD_BLOCK_CNT_H = SD_BLOCK_CNT_H;
 103                 REG_SD_TRANSFER = SD_TRANSFER;
 104                 REG_SD_VPCLK0_CTL = SD_VPCLK0_CTL;
 105                 REG_SD_VPCLK1_CTL = SD_VPCLK1_CTL;
 106                 REG_SD_DCMPS0_CTL = SD_DCMPS0_CTL;
 107                 REG_SD_DCMPS1_CTL = SD_DCMPS1_CTL;
 108         } else {
 109                 REG_SD_CFG1 = 0xFD31;
 110                 REG_SD_CFG2 = 0xFD33;
 111                 REG_SD_CFG3 = 0xFD3E;
 112                 REG_SD_STAT1 = 0xFD30;
 113                 REG_SD_STAT2 = 0;
 114                 REG_SD_BUS_STAT = 0;
 115                 REG_SD_PAD_CTL = 0;
 116                 REG_SD_SAMPLE_POINT_CTL = 0;
 117                 REG_SD_PUSH_POINT_CTL = 0;
 118                 REG_SD_CMD0 = 0xFD34;
 119                 REG_SD_CMD1 = 0xFD35;
 120                 REG_SD_CMD2 = 0xFD36;
 121                 REG_SD_CMD3 = 0xFD37;
 122                 REG_SD_CMD4 = 0xFD38;
 123                 REG_SD_CMD5 = 0xFD5A;
 124                 REG_SD_BYTE_CNT_L = 0xFD39;
 125                 REG_SD_BYTE_CNT_H = 0xFD3A;
 126                 REG_SD_BLOCK_CNT_L = 0xFD3B;
 127                 REG_SD_BLOCK_CNT_H = 0xFD3C;
 128                 REG_SD_TRANSFER = 0xFD32;
 129                 REG_SD_VPCLK0_CTL = 0;
 130                 REG_SD_VPCLK1_CTL = 0;
 131                 REG_SD_DCMPS0_CTL = 0;
 132                 REG_SD_DCMPS1_CTL = 0;
 133         }
 134 }
 135
 136 static int sd_check_data0_status(struct rtsx_chip *chip)
 137 {
 138         u8 stat;
 139
 140         if (CHECK_PID(chip, 0x5209))
 141                 RTSX_READ_REG(chip, REG_SD_BUS_STAT, &stat);
 142         else
 143                 RTSX_READ_REG(chip, REG_SD_STAT1, &stat);
 144
 145         if (!(stat & SD_DAT0_STATUS)) {
 146                 sd_set_err_code(chip, SD_BUSY);
 147                 TRACE_RET(chip, STATUS_FAIL);
 148         }
 149
 150         return STATUS_SUCCESS;
 151 }
 152
 153 static int sd_send_cmd_get_rsp(struct rtsx_chip *chip, u8 cmd_idx,
 154                 u32 arg, u8 rsp_type, u8 *rsp, int rsp_len)
 155 {
 156         struct sd_info *sd_card = &(chip->sd_card);
 157         int retval;
 158         int timeout = 100;
 159         u16 reg_addr;
 160         u8 *ptr;
 161         int stat_idx = 0;
 162         int rty_cnt = 0;
 163
 164         sd_clr_err_code(chip);
 165
 166         RTSX_DEBUGP("SD/MMC CMD %d, arg = 0x%08x\n", cmd_idx, arg);
 167
 168         if (rsp_type == SD_RSP_TYPE_R1b)
 169                 timeout = 3000;
 170
 171 RTY_SEND_CMD:
 172
 173         rtsx_init_cmd(chip);
 174
 175         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF, 0x40 | cmd_idx);
 176         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD1, 0xFF, (u8)(arg >> 24));
 177         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD2, 0xFF, (u8)(arg >> 16));
 178         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD3, 0xFF, (u8)(arg >> 8));
 179         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD4, 0xFF, (u8)arg);
 180
 181         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, rsp_type);
 182         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE,
 183                         0x01, PINGPONG_BUFFER);
 184         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER,
 185                         0xFF, SD_TM_CMD_RSP | SD_TRANSFER_START);
 186         rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER,
 187                      SD_TRANSFER_END | SD_STAT_IDLE, SD_TRANSFER_END | SD_STAT_IDLE);
 188
 189         if (rsp_type == SD_RSP_TYPE_R2) {
 190                 for (reg_addr = PPBUF_BASE2; reg_addr < PPBUF_BASE2 + 16; reg_addr++)
 191                         rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0);
 192
 193                 stat_idx = 16;
 194         } else if (rsp_type != SD_RSP_TYPE_R0) {
 195                 for (reg_addr = REG_SD_CMD0; reg_addr <= REG_SD_CMD4; reg_addr++) {
 196                         rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0);
 197                 }
 198                 stat_idx = 5;
 199         }
 200
 201         rtsx_add_cmd(chip, READ_REG_CMD, REG_SD_STAT1, 0, 0);
 202
 203         retval = rtsx_send_cmd(chip, SD_CARD, timeout);
 204         if (retval < 0) {
 205                 u8 val;
 206
 207                 rtsx_read_register(chip, REG_SD_STAT1, &val);
 208                 RTSX_DEBUGP("SD_STAT1: 0x%x\n", val);
 209
 210                 if (CHECK_PID(chip, 0x5209)) {
 211                         rtsx_read_register(chip, REG_SD_STAT2, &val);
 212                         RTSX_DEBUGP("SD_STAT2: 0x%x\n", val);
 213
 214                         if (val & SD_RSP_80CLK_TIMEOUT) {
 215                                 rtsx_clear_sd_error(chip);
 216                                 sd_set_err_code(chip, SD_RSP_TIMEOUT);
 217                                 TRACE_RET(chip, STATUS_FAIL);
 218                         }
 219
 220                         rtsx_read_register(chip, REG_SD_BUS_STAT, &val);
 221                         RTSX_DEBUGP("SD_BUS_STAT: 0x%x\n", val);
 222                 } else {
 223                         rtsx_read_register(chip, REG_SD_CFG3, &val);
 224                         RTSX_DEBUGP("SD_CFG3: 0x%x\n", val);
 225                 }
 226
 227                 if (retval == -ETIMEDOUT) {
 228                         if (rsp_type & SD_WAIT_BUSY_END) {
 229                                 retval = sd_check_data0_status(chip);
 230                                 if (retval != STATUS_SUCCESS) {
 231                                         rtsx_clear_sd_error(chip);
 232                                         TRACE_RET(chip, retval);
 233                                 }
 234                         } else {
 235                                 sd_set_err_code(chip, SD_TO_ERR);
 236                         }
 237                         retval = STATUS_TIMEDOUT;
 238                 } else {
 239                         retval = STATUS_FAIL;
 240                 }
 241                 rtsx_clear_sd_error(chip);
 242
 243                 TRACE_RET(chip, retval);
 244         }
 245
 246         if (rsp_type == SD_RSP_TYPE_R0)
 247                 return STATUS_SUCCESS;
 248
 249         ptr = rtsx_get_cmd_data(chip) + 1;
 250
 251         if ((ptr[0] & 0xC0) != 0) {
 252                 sd_set_err_code(chip, SD_STS_ERR);
 253                 TRACE_RET(chip, STATUS_FAIL);
 254         }
 255
 256         if (!(rsp_type & SD_NO_CHECK_CRC7)) {
 257                 if (ptr[stat_idx] & SD_CRC7_ERR) {
 258                         if (cmd_idx == WRITE_MULTIPLE_BLOCK) {
 259                                 sd_set_err_code(chip, SD_CRC_ERR);
 260                                 TRACE_RET(chip, STATUS_FAIL);
 261                         }
 262                         if (rty_cnt < SD_MAX_RETRY_COUNT) {
 263                                 wait_timeout(20);
 264                                 rty_cnt++;
 265                                 goto RTY_SEND_CMD;
 266                         } else {
 267                                 sd_set_err_code(chip, SD_CRC_ERR);
 268                                 TRACE_RET(chip, STATUS_FAIL);
 269                         }
 270                 }
 271         }
 272
 273         if ((rsp_type == SD_RSP_TYPE_R1) || (rsp_type == SD_RSP_TYPE_R1b)) {
 274                 if ((cmd_idx != SEND_RELATIVE_ADDR) && (cmd_idx != SEND_IF_COND)) {
 275                         if (cmd_idx != STOP_TRANSMISSION) {
 276                                 if (ptr[1] & 0x80) {
 277                                         TRACE_RET(chip, STATUS_FAIL);
 278                                 }
 279                         }
 280 #ifdef SUPPORT_SD_LOCK
 281                         if (ptr[1] & 0x7D)
 282 #else
 283                         if (ptr[1] & 0x7F)
 284 #endif
 285                         {
 286                                 RTSX_DEBUGP("ptr[1]: 0x%02x\n", ptr[1]);
 287                                 TRACE_RET(chip, STATUS_FAIL);
 288                         }
 289                         if (ptr[2] & 0xFF) {
 290                                 RTSX_DEBUGP("ptr[2]: 0x%02x\n", ptr[2]);
 291                                 TRACE_RET(chip, STATUS_FAIL);
 292                         }
 293                         if (ptr[3] & 0x80) {
 294                                 RTSX_DEBUGP("ptr[3]: 0x%02x\n", ptr[3]);
 295                                 TRACE_RET(chip, STATUS_FAIL);
 296                         }
 297                         if (ptr[3] & 0x01) {
 298                                 sd_card->sd_data_buf_ready = 1;
 299                         } else {
 300                                 sd_card->sd_data_buf_ready = 0;
 301                         }
 302                 }
 303         }
 304
 305         if (rsp && rsp_len)
 306                 memcpy(rsp, ptr, rsp_len);
 307
 308         return STATUS_SUCCESS;
 309 }
 310
 311 static int sd_read_data(struct rtsx_chip *chip,
 312                         u8 trans_mode, u8 *cmd, int cmd_len, u16 byte_cnt,
 313                         u16 blk_cnt, u8 bus_width, u8 *buf, int buf_len,
 314                         int timeout)
 315 {
 316         struct sd_info *sd_card = &(chip->sd_card);
 317         int retval;
 318         int i;
 319
 320         sd_clr_err_code(chip);
 321
 322         if (!buf)
 323                 buf_len = 0;
 324
 325         if (buf_len > 512) {
 326                 TRACE_RET(chip, STATUS_FAIL);
 327         }
 328
 329         rtsx_init_cmd(chip);
 330
 331         if (cmd_len) {
 332                 RTSX_DEBUGP("SD/MMC CMD %d\n", cmd[0] - 0x40);
 333                 for (i = 0; i < (cmd_len < 6 ? cmd_len : 6); i++) {
 334                         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0 + i, 0xFF, cmd[i]);
 335                 }
 336         }
 337         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, (u8)byte_cnt);
 338         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF, (u8)(byte_cnt >> 8));
 339         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF, (u8)blk_cnt);
 340         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF, (u8)(blk_cnt >> 8));
 341
 342         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1, 0x03, bus_width);
 343
 344         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF,
 345                         SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | SD_NO_WAIT_BUSY_END |
 346                         SD_CHECK_CRC7 | SD_RSP_LEN_6);
 347         if (trans_mode != SD_TM_AUTO_TUNING) {
 348                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER);
 349         }
 350         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF, trans_mode | SD_TRANSFER_START);
 351         rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END, SD_TRANSFER_END);
 352
 353         retval = rtsx_send_cmd(chip, SD_CARD, timeout);
 354         if (retval < 0) {
 355                 if (retval == -ETIMEDOUT) {
 356                         sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
 357                                             SD_RSP_TYPE_R1, NULL, 0);
 358                 }
 359
 360                 TRACE_RET(chip, STATUS_FAIL);
 361         }
 362
 363         if (buf && buf_len) {
 364                 retval = rtsx_read_ppbuf(chip, buf, buf_len);
 365                 if (retval != STATUS_SUCCESS) {
 366                         TRACE_RET(chip, STATUS_FAIL);
 367                 }
 368         }
 369
 370         return STATUS_SUCCESS;
 371 }
 372
 373 static int sd_write_data(struct rtsx_chip *chip, u8 trans_mode,
 374                 u8 *cmd, int cmd_len, u16 byte_cnt, u16 blk_cnt, u8 bus_width,
 375                 u8 *buf, int buf_len, int timeout)
 376 {
 377         struct sd_info *sd_card = &(chip->sd_card);
 378         int retval;
 379         int i;
 380
 381         sd_clr_err_code(chip);
 382
 383         if (!buf)
 384                 buf_len = 0;
 385
 386         if (buf_len > 512) {
 387                 /* This function can't write data more than one page */
 388                 TRACE_RET(chip, STATUS_FAIL);
 389         }
 390
 391         if (buf && buf_len) {
 392                 retval = rtsx_write_ppbuf(chip, buf, buf_len);
 393                 if (retval != STATUS_SUCCESS) {
 394                         TRACE_RET(chip, STATUS_FAIL);
 395                 }
 396         }
 397
 398         rtsx_init_cmd(chip);
 399
 400         if (cmd_len) {
 401                 RTSX_DEBUGP("SD/MMC CMD %d\n", cmd[0] - 0x40);
 402                 for (i = 0; i < (cmd_len < 6 ? cmd_len : 6); i++) {
 403                         rtsx_add_cmd(chip, WRITE_REG_CMD,
 404                                      REG_SD_CMD0 + i, 0xFF, cmd[i]);
 405                 }
 406         }
 407         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, (u8)byte_cnt);
 408         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF, (u8)(byte_cnt >> 8));
 409         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF, (u8)blk_cnt);
 410         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF, (u8)(blk_cnt >> 8));
 411
 412         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1, 0x03, bus_width);
 413
 414         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF,
 415                 SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | SD_NO_WAIT_BUSY_END |
 416                 SD_CHECK_CRC7 | SD_RSP_LEN_6);
 417
 418         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF, trans_mode | SD_TRANSFER_START);
 419         rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END, SD_TRANSFER_END);
 420
 421         retval = rtsx_send_cmd(chip, SD_CARD, timeout);
 422         if (retval < 0) {
 423                 if (retval == -ETIMEDOUT) {
 424                         sd_send_cmd_get_rsp(chip, SEND_STATUS,
 425                                 sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
 426                 }
 427
 428                 TRACE_RET(chip, STATUS_FAIL);
 429         }
 430
 431         return STATUS_SUCCESS;
 432 }
 433
 434 static int sd_check_csd(struct rtsx_chip *chip, char check_wp)
 435 {
 436         struct sd_info *sd_card = &(chip->sd_card);
 437         int retval;
 438         int i;
 439         u8 csd_ver, trans_speed;
 440         u8 rsp[16];
 441
 442         for (i = 0; i < 6; i++) {
 443                 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
 444                         sd_set_err_code(chip, SD_NO_CARD);
 445                         TRACE_RET(chip, STATUS_FAIL);
 446                 }
 447
 448                 retval = sd_send_cmd_get_rsp(chip, SEND_CSD, sd_card->sd_addr, SD_RSP_TYPE_R2, rsp, 16);
 449                 if (retval == STATUS_SUCCESS)
 450                         break;
 451         }
 452
 453         if (i == 6) {
 454                 TRACE_RET(chip, STATUS_FAIL);
 455         }
 456
 457         memcpy(sd_card->raw_csd, rsp + 1, 15);
 458
 459         if (CHECK_PID(chip, 0x5209)) {
 460                 RTSX_READ_REG(chip, REG_SD_CMD5, sd_card->raw_csd + 15);
 461         }
 462
 463         RTSX_DEBUGP("CSD Response:\n");
 464         RTSX_DUMP(sd_card->raw_csd, 16);
 465
 466         csd_ver = (rsp[1] & 0xc0) >> 6;
 467         RTSX_DEBUGP("csd_ver = %d\n", csd_ver);
 468
 469         trans_speed = rsp[4];
 470         if ((trans_speed & 0x07) == 0x02) {
 471                 if ((trans_speed & 0xf8) >= 0x30) {
 472                         if (chip->asic_code) {
 473                                 sd_card->sd_clock = 47;
 474                         } else {
 475                                 sd_card->sd_clock = CLK_50;
 476                         }
 477                 } else if ((trans_speed & 0xf8) == 0x28) {
 478                         if (chip->asic_code) {
 479                                 sd_card->sd_clock = 39;
 480                         } else {
 481                                 sd_card->sd_clock = CLK_40;
 482                         }
 483                 } else if ((trans_speed & 0xf8) == 0x20) {
 484                         if (chip->asic_code) {
 485                                 sd_card->sd_clock = 29;
 486                         } else {
 487                                 sd_card->sd_clock = CLK_30;
 488                         }
 489                 } else if ((trans_speed & 0xf8) >= 0x10) {
 490                         if (chip->asic_code) {
 491                                 sd_card->sd_clock = 23;
 492                         } else {
 493                                 sd_card->sd_clock = CLK_20;
 494                         }
 495                 } else if ((trans_speed & 0x08) >= 0x08) {
 496                         if (chip->asic_code) {
 497                                 sd_card->sd_clock = 19;
 498                         } else {
 499                                 sd_card->sd_clock = CLK_20;
 500                         }
 501                 } else {
 502                         TRACE_RET(chip, STATUS_FAIL);
 503                 }
 504         } else {
 505                 TRACE_RET(chip, STATUS_FAIL);
 506         }
 507
 508         if (CHK_MMC_SECTOR_MODE(sd_card)) {
 509                 sd_card->capacity = 0;
 510         } else {
 511                 if ((!CHK_SD_HCXC(sd_card)) || (csd_ver == 0)) {
 512                         u8 blk_size, c_size_mult;
 513                         u16 c_size;
 514                         blk_size = rsp[6] & 0x0F;
 515                         c_size =  ((u16)(rsp[7] & 0x03) << 10)
 516                                         + ((u16)rsp[8] << 2)
 517                                         + ((u16)(rsp[9] & 0xC0) >> 6);
 518                         c_size_mult = (u8)((rsp[10] & 0x03) << 1);
 519                         c_size_mult += (rsp[11] & 0x80) >> 7;
 520                         sd_card->capacity = (((u32)(c_size + 1)) * (1 << (c_size_mult + 2))) << (blk_size - 9);
 521                 } else {
 522                         u32 total_sector = 0;
 523                         total_sector = (((u32)rsp[8] & 0x3f) << 16) |
 524                                 ((u32)rsp[9] << 8) | (u32)rsp[10];
 525                         sd_card->capacity = (total_sector + 1) << 10;
 526                 }
 527         }
 528
 529         if (check_wp) {
 530                 if (rsp[15] & 0x30) {
 531                         chip->card_wp |= SD_CARD;
 532                 }
 533                 RTSX_DEBUGP("CSD WP Status: 0x%x\n", rsp[15]);
 534         }
 535
 536         return STATUS_SUCCESS;
 537 }
 538
 539 static int sd_set_sample_push_timing(struct rtsx_chip *chip)
 540 {
 541         struct sd_info *sd_card = &(chip->sd_card);
 542
 543         if (CHECK_PID(chip, 0x5209)) {
 544                 if (CHK_SD_SDR104(sd_card) || CHK_SD_SDR50(sd_card)) {
 545                         RTSX_WRITE_REG(chip, SD_CFG1, 0x0C | SD_ASYNC_FIFO_NOT_RST,
 546                                         SD_30_MODE | SD_ASYNC_FIFO_NOT_RST);
 547                         RTSX_WRITE_REG(chip, CLK_CTL, CLK_LOW_FREQ, CLK_LOW_FREQ);
 548                         RTSX_WRITE_REG(chip, CARD_CLK_SOURCE, 0xFF,
 549                                         CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
 550                         RTSX_WRITE_REG(chip, CLK_CTL, CLK_LOW_FREQ, 0);
 551                 } else if (CHK_SD_DDR50(sd_card) || CHK_MMC_DDR52(sd_card)) {
 552                         RTSX_WRITE_REG(chip, SD_CFG1, 0x0C | SD_ASYNC_FIFO_NOT_RST,
 553                                         SD_DDR_MODE | SD_ASYNC_FIFO_NOT_RST);
 554                         RTSX_WRITE_REG(chip, CLK_CTL, CLK_LOW_FREQ, CLK_LOW_FREQ);
 555                         RTSX_WRITE_REG(chip, CARD_CLK_SOURCE, 0xFF,
 556                                         CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
 557                         RTSX_WRITE_REG(chip, CLK_CTL, CLK_LOW_FREQ, 0);
 558                         RTSX_WRITE_REG(chip, SD_PUSH_POINT_CTL, DDR_VAR_TX_CMD_DAT,
 559                                         DDR_VAR_TX_CMD_DAT);
 560                         RTSX_WRITE_REG(chip, SD_SAMPLE_POINT_CTL, DDR_VAR_RX_DAT | DDR_VAR_RX_CMD,
 561                                         DDR_VAR_RX_DAT | DDR_VAR_RX_CMD);
 562                 } else {
 563                         u8 val = 0;
 564
 565                         RTSX_WRITE_REG(chip, SD_CFG1, 0x0C, SD_20_MODE);
 566                         RTSX_WRITE_REG(chip, CLK_CTL, CLK_LOW_FREQ, CLK_LOW_FREQ);
 567                         RTSX_WRITE_REG(chip, CARD_CLK_SOURCE, 0xFF,
 568                                         CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1);
 569                         RTSX_WRITE_REG(chip, CLK_CTL, CLK_LOW_FREQ, 0);
 570
 571                         if ((chip->sd_ctl & SD_PUSH_POINT_CTL_MASK) == SD_PUSH_POINT_AUTO) {
 572                                 val = SD20_TX_NEG_EDGE;
 573                         } else if ((chip->sd_ctl & SD_PUSH_POINT_CTL_MASK) == SD_PUSH_POINT_DELAY) {
 574                                 val = SD20_TX_14_AHEAD;
 575                         } else {
 576                                 val = SD20_TX_NEG_EDGE;
 577                         }
 578                         RTSX_WRITE_REG(chip, SD_PUSH_POINT_CTL, SD20_TX_SEL_MASK, val);
 579
 580                         if ((chip->sd_ctl & SD_SAMPLE_POINT_CTL_MASK) == SD_SAMPLE_POINT_AUTO) {
 581                                 if (chip->asic_code) {
 582                                         if (CHK_SD_HS(sd_card) || CHK_MMC_52M(sd_card)) {
 583                                                 val = SD20_RX_14_DELAY;
 584                                         } else {
 585                                                 val = SD20_RX_POS_EDGE;
 586                                         }
 587                                 } else {
 588                                         val = SD20_RX_14_DELAY;
 589                                 }
 590                         } else if ((chip->sd_ctl & SD_SAMPLE_POINT_CTL_MASK) == SD_SAMPLE_POINT_DELAY) {
 591                                 val = SD20_RX_14_DELAY;
 592                         } else {
 593                                 val = SD20_RX_POS_EDGE;
 594                         }
 595                         RTSX_WRITE_REG(chip, SD_SAMPLE_POINT_CTL, SD20_RX_SEL_MASK, val);
 596                 }
 597         } else {
 598                 u8 val = 0;
 599
 600                 if ((chip->sd_ctl & SD_PUSH_POINT_CTL_MASK) == SD_PUSH_POINT_DELAY) {
 601                         val |= 0x10;
 602                 }
 603
 604                 if ((chip->sd_ctl & SD_SAMPLE_POINT_CTL_MASK) == SD_SAMPLE_POINT_AUTO) {
 605                         if (chip->asic_code) {
 606                                 if (CHK_SD_HS(sd_card) || CHK_MMC_52M(sd_card)) {
 607                                         if (val & 0x10) {
 608                                                 val |= 0x04;
 609                                         } else {
 610                                                 val |= 0x08;
 611                                         }
 612                                 }
 613                         } else {
 614                                 if (val & 0x10) {
 615                                         val |= 0x04;
 616                                 } else {
 617                                         val |= 0x08;
 618                                 }
 619                         }
 620                 } else if ((chip->sd_ctl & SD_SAMPLE_POINT_CTL_MASK) == SD_SAMPLE_POINT_DELAY) {
 621                         if (val & 0x10) {
 622                                 val |= 0x04;
 623                         } else {
 624                                 val |= 0x08;
 625                         }
 626                 }
 627
 628                 RTSX_WRITE_REG(chip, REG_SD_CFG1, 0x1C, val);
 629         }
 630
 631         return STATUS_SUCCESS;
 632 }
 633
 634 static void sd_choose_proper_clock(struct rtsx_chip *chip)
 635 {
 636         struct sd_info *sd_card = &(chip->sd_card);
 637
 638         if (CHK_SD_SDR104(sd_card)) {
 639                 if (chip->asic_code) {
 640                         sd_card->sd_clock = chip->asic_sd_sdr104_clk;
 641                 } else {
 642                         sd_card->sd_clock = chip->fpga_sd_sdr104_clk;
 643                 }
 644         } else if (CHK_SD_DDR50(sd_card)) {
 645                 if (chip->asic_code) {
 646                         sd_card->sd_clock = chip->asic_sd_ddr50_clk;
 647                 } else {
 648                         sd_card->sd_clock = chip->fpga_sd_ddr50_clk;
 649                 }
 650         } else if (CHK_SD_SDR50(sd_card)) {
 651                 if (chip->asic_code) {
 652                         sd_card->sd_clock = chip->asic_sd_sdr50_clk;
 653                 } else {
 654                         sd_card->sd_clock = chip->fpga_sd_sdr50_clk;
 655                 }
 656         } else if (CHK_SD_HS(sd_card)) {
 657                 if (chip->asic_code) {
 658                         sd_card->sd_clock = chip->asic_sd_hs_clk;
 659                 } else {
 660                         sd_card->sd_clock = chip->fpga_sd_hs_clk;
 661                 }
 662         } else if (CHK_MMC_52M(sd_card) || CHK_MMC_DDR52(sd_card)) {
 663                 if (chip->asic_code) {
 664                         sd_card->sd_clock = chip->asic_mmc_52m_clk;
 665                 } else {
 666                         sd_card->sd_clock = chip->fpga_mmc_52m_clk;
 667                 }
 668         } else if (CHK_MMC_26M(sd_card)) {
 669                 if (chip->asic_code) {
 670                         sd_card->sd_clock = 48;
 671                 } else {
 672                         sd_card->sd_clock = CLK_50;
 673                 }
 674         }
 675 }
 676
 677 static int sd_set_clock_divider(struct rtsx_chip *chip, u8 clk_div)
 678 {
 679         u8 mask = 0, val = 0;
 680
 681         if (CHECK_PID(chip, 0x5209)) {
 682                 mask = SD_CLK_DIVIDE_MASK;
 683                 val = clk_div;
 684         } else {
 685                 mask = 0x60;
 686                 if (clk_div == SD_CLK_DIVIDE_0) {
 687                         val = 0x00;
 688                 } else if (clk_div == SD_CLK_DIVIDE_128) {
 689                         val = 0x40;
 690                 } else if (clk_div == SD_CLK_DIVIDE_256) {
 691                         val = 0x20;
 692                 }
 693         }
 694
 695         RTSX_WRITE_REG(chip, REG_SD_CFG1, mask, val);
 696
 697         return STATUS_SUCCESS;
 698 }
 699
 700 static int sd_set_init_para(struct rtsx_chip *chip)
 701 {
 702         struct sd_info *sd_card = &(chip->sd_card);
 703         int retval;
 704
 705         retval = sd_set_sample_push_timing(chip);
 706         if (retval != STATUS_SUCCESS) {
 707                 TRACE_RET(chip, STATUS_FAIL);
 708         }
 709
 710         sd_choose_proper_clock(chip);
 711
 712         retval = switch_clock(chip, sd_card->sd_clock);
 713         if (retval != STATUS_SUCCESS) {
 714                 TRACE_RET(chip, STATUS_FAIL);
 715         }
 716
 717         return STATUS_SUCCESS;
 718 }
 719
 720 int sd_select_card(struct rtsx_chip *chip, int select)
 721 {
 722         struct sd_info *sd_card = &(chip->sd_card);
 723         int retval;
 724         u8 cmd_idx, cmd_type;
 725         u32 addr;
 726
 727         if (select) {
 728                 cmd_idx = SELECT_CARD;
 729                 cmd_type = SD_RSP_TYPE_R1;
 730                 addr = sd_card->sd_addr;
 731         } else {
 732                 cmd_idx = DESELECT_CARD;
 733                 cmd_type = SD_RSP_TYPE_R0;
 734                 addr = 0;
 735         }
 736
 737         retval = sd_send_cmd_get_rsp(chip, cmd_idx, addr, cmd_type, NULL, 0);
 738         if (retval != STATUS_SUCCESS) {
 739                 TRACE_RET(chip, STATUS_FAIL);
 740         }
 741
 742         return STATUS_SUCCESS;
 743 }
 744
 745 #ifdef SUPPORT_SD_LOCK
 746 static int sd_update_lock_status(struct rtsx_chip *chip)
 747 {
 748         struct sd_info *sd_card = &(chip->sd_card);
 749         int retval;
 750         u8 rsp[5];
 751
 752         retval = sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr, SD_RSP_TYPE_R1, rsp, 5);
 753         if (retval != STATUS_SUCCESS) {
 754                 TRACE_RET(chip, STATUS_FAIL);
 755         }
 756
 757         if (rsp[1] & 0x02) {
 758                 sd_card->sd_lock_status |= SD_LOCKED;
 759         } else {
 760                 sd_card->sd_lock_status &= ~SD_LOCKED;
 761         }
 762
 763         RTSX_DEBUGP("sd_card->sd_lock_status = 0x%x\n", sd_card->sd_lock_status);
 764
 765         if (rsp[1] & 0x01) {
 766                 TRACE_RET(chip, STATUS_FAIL);
 767         }
 768
 769         return STATUS_SUCCESS;
 770 }
 771 #endif
 772
 773 static int sd_wait_state_data_ready(struct rtsx_chip *chip, u8 state, u8 data_ready, int polling_cnt)
 774 {
 775         struct sd_info *sd_card = &(chip->sd_card);
 776         int retval, i;
 777         u8 rsp[5];
 778
 779         for (i = 0; i < polling_cnt; i++) {
 780                 retval = sd_send_cmd_get_rsp(chip, SEND_STATUS,
 781                                              sd_card->sd_addr, SD_RSP_TYPE_R1, rsp, 5);
 782                 if (retval != STATUS_SUCCESS) {
 783                         TRACE_RET(chip, STATUS_FAIL);
 784                 }
 785
 786                 if (((rsp[3] & 0x1E) == state) && ((rsp[3] & 0x01) == data_ready)) {
 787                         return STATUS_SUCCESS;
 788                 }
 789         }
 790
 791         TRACE_RET(chip, STATUS_FAIL);
 792 }
 793
 794 static int sd_change_bank_voltage(struct rtsx_chip *chip, u8 voltage)
 795 {
 796         int retval;
 797
 798         if (voltage == SD_IO_3V3) {
 799                 if (chip->asic_code) {
 800                         retval = rtsx_write_phy_register(chip, 0x08, 0x4FC0 | chip->phy_voltage);
 801                         if (retval != STATUS_SUCCESS) {
 802                                 TRACE_RET(chip, STATUS_FAIL);
 803                         }
 804                 } else {
 805                         RTSX_WRITE_REG(chip, SD_PAD_CTL, SD_IO_USING_1V8, 0);
 806                 }
 807         } else if (voltage == SD_IO_1V8) {
 808                 if (chip->asic_code) {
 809                         retval = rtsx_write_phy_register(chip, 0x08, 0x4C40 | chip->phy_voltage);
 810                         if (retval != STATUS_SUCCESS) {
 811                                 TRACE_RET(chip, STATUS_FAIL);
 812                         }
 813                 } else {
 814                         RTSX_WRITE_REG(chip, SD_PAD_CTL, SD_IO_USING_1V8, SD_IO_USING_1V8);
 815                 }
 816         } else {
 817                 TRACE_RET(chip, STATUS_FAIL);
 818         }
 819
 820         return STATUS_SUCCESS;
 821 }
 822
 823 static int sd_voltage_switch(struct rtsx_chip *chip)
 824 {
 825         int retval;
 826         u8 stat;
 827
 828         RTSX_WRITE_REG(chip, SD_BUS_STAT, SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, SD_CLK_TOGGLE_EN);
 829
 830         retval = sd_send_cmd_get_rsp(chip, VOLTAGE_SWITCH, 0, SD_RSP_TYPE_R1, NULL, 0);
 831         if (retval != STATUS_SUCCESS) {
 832                 TRACE_RET(chip, STATUS_FAIL);
 833         }
 834
 835         udelay(chip->sd_voltage_switch_delay);
 836
 837         RTSX_READ_REG(chip, SD_BUS_STAT, &stat);
 838         if (stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
 839                                 SD_DAT1_STATUS | SD_DAT0_STATUS)) {
 840                 TRACE_RET(chip, STATUS_FAIL);
 841         }
 842
 843         RTSX_WRITE_REG(chip, SD_BUS_STAT, 0xFF, SD_CLK_FORCE_STOP);
 844         retval = sd_change_bank_voltage(chip, SD_IO_1V8);
 845         if (retval != STATUS_SUCCESS) {
 846                 TRACE_RET(chip, STATUS_FAIL);
 847         }
 848         wait_timeout(50);
 849
 850         RTSX_WRITE_REG(chip, SD_BUS_STAT, 0xFF, SD_CLK_TOGGLE_EN);
 851         wait_timeout(10);
 852
 853         RTSX_READ_REG(chip, SD_BUS_STAT, &stat);
 854         if ((stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
 855                                 SD_DAT1_STATUS | SD_DAT0_STATUS)) !=
 856                         (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
 857                                 SD_DAT1_STATUS | SD_DAT0_STATUS)) {
 858                 RTSX_DEBUGP("SD_BUS_STAT: 0x%x\n", stat);
 859                 rtsx_write_register(chip, SD_BUS_STAT, SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
 860                 rtsx_write_register(chip, CARD_CLK_EN, 0xFF, 0);
 861                 TRACE_RET(chip, STATUS_FAIL);
 862         }
 863
 864         RTSX_WRITE_REG(chip, SD_BUS_STAT, SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
 865
 866         return STATUS_SUCCESS;
 867 }
 868
 869 static int sd_reset_dcm(struct rtsx_chip *chip, u8 tune_dir)
 870 {
 871         if (tune_dir == TUNE_RX) {
 872                 RTSX_WRITE_REG(chip, DCM_DRP_CTL, 0xFF, DCM_RESET | DCM_RX);
 873                 RTSX_WRITE_REG(chip, DCM_DRP_CTL, 0xFF, DCM_RX);
 874         } else {
 875                 RTSX_WRITE_REG(chip, DCM_DRP_CTL, 0xFF, DCM_RESET | DCM_TX);
 876                 RTSX_WRITE_REG(chip, DCM_DRP_CTL, 0xFF, DCM_TX);
 877         }
 878
 879         return STATUS_SUCCESS;
 880 }
 881
 882 static int sd_change_phase(struct rtsx_chip *chip, u8 sample_point, u8 tune_dir)
 883 {
 884         struct sd_info *sd_card = &(chip->sd_card);
 885         u16 SD_VP_CTL, SD_DCMPS_CTL;
 886         u8 val;
 887         int retval;
 888         int ddr_rx = 0;
 889
 890         RTSX_DEBUGP("sd_change_phase (sample_point = %d, tune_dir = %d)\n",
 891                                 sample_point, tune_dir);
 892
 893         if (tune_dir == TUNE_RX) {
 894                 SD_VP_CTL = SD_VPRX_CTL;
 895                 SD_DCMPS_CTL = SD_DCMPS_RX_CTL;
 896                 if (CHK_SD_DDR50(sd_card)) {
 897                         ddr_rx = 1;
 898                 }
 899         } else {
 900                 SD_VP_CTL = SD_VPTX_CTL;
 901                 SD_DCMPS_CTL = SD_DCMPS_TX_CTL;
 902         }
 903
 904         if (chip->asic_code) {
 905                 RTSX_WRITE_REG(chip, CLK_CTL, CHANGE_CLK, CHANGE_CLK);
 906                 RTSX_WRITE_REG(chip, SD_VP_CTL, 0x1F, sample_point);
 907                 RTSX_WRITE_REG(chip, SD_VPCLK0_CTL, PHASE_NOT_RESET, 0);
 908                 RTSX_WRITE_REG(chip, SD_VPCLK0_CTL, PHASE_NOT_RESET, PHASE_NOT_RESET);
 909                 RTSX_WRITE_REG(chip, CLK_CTL, CHANGE_CLK, 0);
 910         } else {
 911 #ifdef CONFIG_RTS_PSTOR_DEBUG
 912                 rtsx_read_register(chip, SD_VP_CTL, &val);
 913                 RTSX_DEBUGP("SD_VP_CTL: 0x%x\n", val);
 914                 rtsx_read_register(chip, SD_DCMPS_CTL, &val);
 915                 RTSX_DEBUGP("SD_DCMPS_CTL: 0x%x\n", val);
 916 #endif
 917
 918                 if (ddr_rx) {
 919                         RTSX_WRITE_REG(chip, SD_VP_CTL, PHASE_CHANGE, PHASE_CHANGE);
 920                         udelay(50);
 921                         RTSX_WRITE_REG(chip, SD_VP_CTL, 0xFF,
 922                                         PHASE_CHANGE | PHASE_NOT_RESET | sample_point);
 923                 } else {
 924                         RTSX_WRITE_REG(chip, CLK_CTL, CHANGE_CLK, CHANGE_CLK);
 925                         udelay(50);
 926                         RTSX_WRITE_REG(chip, SD_VP_CTL, 0xFF,
 927                                         PHASE_NOT_RESET | sample_point);
 928                 }
 929                 udelay(100);
 930
 931                 rtsx_init_cmd(chip);
 932                 rtsx_add_cmd(chip, WRITE_REG_CMD, SD_DCMPS_CTL, DCMPS_CHANGE, DCMPS_CHANGE);
 933                 rtsx_add_cmd(chip, CHECK_REG_CMD, SD_DCMPS_CTL, DCMPS_CHANGE_DONE, DCMPS_CHANGE_DONE);
 934                 retval = rtsx_send_cmd(chip, SD_CARD, 100);
 935                 if (retval != STATUS_SUCCESS) {
 936                         TRACE_GOTO(chip, Fail);
 937                 }
 938
 939                 val = *rtsx_get_cmd_data(chip);
 940                 if (val & DCMPS_ERROR) {
 941                         TRACE_GOTO(chip, Fail);
 942                 }
 943                 if ((val & DCMPS_CURRENT_PHASE) != sample_point) {
 944                         TRACE_GOTO(chip, Fail);
 945                 }
 946                 RTSX_WRITE_REG(chip, SD_DCMPS_CTL, DCMPS_CHANGE, 0);
 947                 if (ddr_rx) {
 948                         RTSX_WRITE_REG(chip, SD_VP_CTL, PHASE_CHANGE, 0);
 949                 } else {
 950                         RTSX_WRITE_REG(chip, CLK_CTL, CHANGE_CLK, 0);
 951                 }
 952                 udelay(50);
 953         }
 954
 955         RTSX_WRITE_REG(chip, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0);
 956
 957         return STATUS_SUCCESS;
 958
 959 Fail:
 960 #ifdef CONFIG_RTS_PSTOR_DEBUG
 961         rtsx_read_register(chip, SD_VP_CTL, &val);
 962         RTSX_DEBUGP("SD_VP_CTL: 0x%x\n", val);
 963         rtsx_read_register(chip, SD_DCMPS_CTL, &val);
 964         RTSX_DEBUGP("SD_DCMPS_CTL: 0x%x\n", val);
 965 #endif
 966
 967         rtsx_write_register(chip, SD_DCMPS_CTL, DCMPS_CHANGE, 0);
 968         rtsx_write_register(chip, SD_VP_CTL, PHASE_CHANGE, 0);
 969         wait_timeout(10);
 970         sd_reset_dcm(chip, tune_dir);
 971         return STATUS_FAIL;
 972 }
 973
 974 static int sd_check_spec(struct rtsx_chip *chip, u8 bus_width)
 975 {
 976         struct sd_info *sd_card = &(chip->sd_card);
 977         int retval;
 978         u8 cmd[5], buf[8];
 979
 980         retval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
 981         if (retval != STATUS_SUCCESS) {
 982                 TRACE_RET(chip, STATUS_FAIL);
 983         }
 984
 985         cmd[0] = 0x40 | SEND_SCR;
 986         cmd[1] = 0;
 987         cmd[2] = 0;
 988         cmd[3] = 0;
 989         cmd[4] = 0;
 990
 991         retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, 8, 1, bus_width, buf, 8, 250);
 992         if (retval != STATUS_SUCCESS) {
 993                 rtsx_clear_sd_error(chip);
 994                 TRACE_RET(chip, STATUS_FAIL);
 995         }
 996
 997         memcpy(sd_card->raw_scr, buf, 8);
 998
 999         if ((buf[0] & 0x0F) == 0) {
1000                 TRACE_RET(chip, STATUS_FAIL);
1001         }
1002
1003         return STATUS_SUCCESS;
1004 }
1005
1006 static int sd_query_switch_result(struct rtsx_chip *chip, u8 func_group, u8 func_to_switch,
1007                 u8 *buf, int buf_len)
1008 {
1009         u8 support_mask = 0, query_switch = 0, switch_busy = 0;
1010         int support_offset = 0, query_switch_offset = 0, check_busy_offset = 0;
1011
1012         if (func_group == SD_FUNC_GROUP_1) {
1013                 support_offset = FUNCTION_GROUP1_SUPPORT_OFFSET;
1014                 query_switch_offset = FUNCTION_GROUP1_QUERY_SWITCH_OFFSET;
1015                 check_busy_offset = FUNCTION_GROUP1_CHECK_BUSY_OFFSET;
1016
1017                 switch (func_to_switch) {
1018                 case HS_SUPPORT:
1019                         support_mask = HS_SUPPORT_MASK;
1020                         query_switch = HS_QUERY_SWITCH_OK;
1021                         switch_busy = HS_SWITCH_BUSY;
1022                         break;
1023
1024                 case SDR50_SUPPORT:
1025                         support_mask = SDR50_SUPPORT_MASK;
1026                         query_switch = SDR50_QUERY_SWITCH_OK;
1027                         switch_busy = SDR50_SWITCH_BUSY;
1028                         break;
1029
1030                 case SDR104_SUPPORT:
1031                         support_mask = SDR104_SUPPORT_MASK;
1032                         query_switch = SDR104_QUERY_SWITCH_OK;
1033                         switch_busy = SDR104_SWITCH_BUSY;
1034                         break;
1035
1036                 case DDR50_SUPPORT:
1037                         support_mask = DDR50_SUPPORT_MASK;
1038                         query_switch = DDR50_QUERY_SWITCH_OK;
1039                         switch_busy = DDR50_SWITCH_BUSY;
1040                         break;
1041
1042                 default:
1043                         TRACE_RET(chip, STATUS_FAIL);
1044                 }
1045         } else if (func_group == SD_FUNC_GROUP_3) {
1046                 support_offset = FUNCTION_GROUP3_SUPPORT_OFFSET;
1047                 query_switch_offset = FUNCTION_GROUP3_QUERY_SWITCH_OFFSET;
1048                 check_busy_offset = FUNCTION_GROUP3_CHECK_BUSY_OFFSET;
1049
1050                 switch (func_to_switch) {
1051                 case DRIVING_TYPE_A:
1052                         support_mask = DRIVING_TYPE_A_MASK;
1053                         query_switch = TYPE_A_QUERY_SWITCH_OK;
1054                         switch_busy = TYPE_A_SWITCH_BUSY;
1055                         break;
1056
1057                 case DRIVING_TYPE_C:
1058                         support_mask = DRIVING_TYPE_C_MASK;
1059                         query_switch = TYPE_C_QUERY_SWITCH_OK;
1060                         switch_busy = TYPE_C_SWITCH_BUSY;
1061                         break;
1062
1063                 case DRIVING_TYPE_D:
1064                         support_mask = DRIVING_TYPE_D_MASK;
1065                         query_switch = TYPE_D_QUERY_SWITCH_OK;
1066                         switch_busy = TYPE_D_SWITCH_BUSY;
1067                         break;
1068
1069                 default:
1070                         TRACE_RET(chip, STATUS_FAIL);
1071                 }
1072         } else if (func_group == SD_FUNC_GROUP_4) {
1073                 support_offset = FUNCTION_GROUP4_SUPPORT_OFFSET;
1074                 query_switch_offset = FUNCTION_GROUP4_QUERY_SWITCH_OFFSET;
1075                 check_busy_offset = FUNCTION_GROUP4_CHECK_BUSY_OFFSET;
1076
1077                 switch (func_to_switch) {
1078                 case CURRENT_LIMIT_400:
1079                         support_mask = CURRENT_LIMIT_400_MASK;
1080                         query_switch = CURRENT_LIMIT_400_QUERY_SWITCH_OK;
1081                         switch_busy = CURRENT_LIMIT_400_SWITCH_BUSY;
1082                         break;
1083
1084                 case CURRENT_LIMIT_600:
1085                         support_mask = CURRENT_LIMIT_600_MASK;
1086                         query_switch = CURRENT_LIMIT_600_QUERY_SWITCH_OK;
1087                         switch_busy = CURRENT_LIMIT_600_SWITCH_BUSY;
1088                         break;
1089
1090                 case CURRENT_LIMIT_800:
1091                         support_mask = CURRENT_LIMIT_800_MASK;
1092                         query_switch = CURRENT_LIMIT_800_QUERY_SWITCH_OK;
1093                         switch_busy = CURRENT_LIMIT_800_SWITCH_BUSY;
1094                         break;
1095
1096                 default:
1097                         TRACE_RET(chip, STATUS_FAIL);
1098                 }
1099         } else {
1100                 TRACE_RET(chip, STATUS_FAIL);
1101         }
1102
1103         if (func_group == SD_FUNC_GROUP_1) {
1104                 if (!(buf[support_offset] & support_mask) ||
1105                                 ((buf[query_switch_offset] & 0x0F) != query_switch)) {
1106                         TRACE_RET(chip, STATUS_FAIL);
1107                 }
1108         }
1109
1110         /* Check 'Busy Status' */
1111         if ((buf[DATA_STRUCTURE_VER_OFFSET] == 0x01) &&
1112                     ((buf[check_busy_offset] & switch_busy) == switch_busy)) {
1113                 TRACE_RET(chip, STATUS_FAIL);
1114         }
1115
1116         return STATUS_SUCCESS;
1117 }
1118
1119 static int sd_check_switch_mode(struct rtsx_chip *chip, u8 mode,
1120                 u8 func_group, u8 func_to_switch, u8 bus_width)
1121 {
1122         struct sd_info *sd_card = &(chip->sd_card);
1123         int retval;
1124         u8 cmd[5], buf[64];
1125
1126         RTSX_DEBUGP("sd_check_switch_mode (mode = %d, func_group = %d, func_to_switch = %d)\n",
1127                         mode, func_group, func_to_switch);
1128
1129         cmd[0] = 0x40 | SWITCH;
1130         cmd[1] = mode;
1131
1132         if (func_group == SD_FUNC_GROUP_1) {
1133                 cmd[2] = 0xFF;
1134                 cmd[3] = 0xFF;
1135                 cmd[4] = 0xF0 + func_to_switch;
1136         } else if (func_group == SD_FUNC_GROUP_3) {
1137                 cmd[2] = 0xFF;
1138                 cmd[3] = 0xF0 + func_to_switch;
1139                 cmd[4] = 0xFF;
1140         } else if (func_group == SD_FUNC_GROUP_4) {
1141                 cmd[2] = 0xFF;
1142                 cmd[3] = 0x0F + (func_to_switch << 4);
1143                 cmd[4] = 0xFF;
1144         } else {
1145                 cmd[1] = SD_CHECK_MODE;
1146                 cmd[2] = 0xFF;
1147                 cmd[3] = 0xFF;
1148                 cmd[4] = 0xFF;
1149         }
1150
1151         retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, 64, 1, bus_width, buf, 64, 250);
1152         if (retval != STATUS_SUCCESS) {
1153                 rtsx_clear_sd_error(chip);
1154                 TRACE_RET(chip, STATUS_FAIL);
1155         }
1156
1157         RTSX_DUMP(buf, 64);
1158
1159         if (func_group == NO_ARGUMENT) {
1160                 sd_card->func_group1_mask = buf[0x0D];
1161                 sd_card->func_group2_mask = buf[0x0B];
1162                 sd_card->func_group3_mask = buf[0x09];
1163                 sd_card->func_group4_mask = buf[0x07];
1164
1165                 RTSX_DEBUGP("func_group1_mask = 0x%02x\n", buf[0x0D]);
1166                 RTSX_DEBUGP("func_group2_mask = 0x%02x\n", buf[0x0B]);
1167                 RTSX_DEBUGP("func_group3_mask = 0x%02x\n", buf[0x09]);
1168                 RTSX_DEBUGP("func_group4_mask = 0x%02x\n", buf[0x07]);
1169         } else {
1170                 /* Maximum current consumption, check whether current is acceptable;
1171                  * bit[511:496] = 0x0000 means some error happened.
1172                  */
1173                 u16 cc = ((u16)buf[0] << 8) | buf[1];
1174                 RTSX_DEBUGP("Maximum current consumption: %dmA\n", cc);
1175                 if ((cc == 0) || (cc > 800)) {
1176                         TRACE_RET(chip, STATUS_FAIL);
1177                 }
1178                 retval = sd_query_switch_result(chip, func_group, func_to_switch, buf, 64);
1179                 if (retval != STATUS_SUCCESS) {
1180                         TRACE_RET(chip, STATUS_FAIL);
1181                 }
1182
1183                 if ((cc > 400) || (func_to_switch > CURRENT_LIMIT_400)) {
1184                         RTSX_WRITE_REG(chip, OCPPARA2, SD_OCP_THD_MASK, chip->sd_800mA_ocp_thd);
1185                         RTSX_WRITE_REG(chip, CARD_PWR_CTL, PMOS_STRG_MASK, PMOS_STRG_800mA);
1186                 }
1187         }
1188
1189         return STATUS_SUCCESS;
1190 }
1191
1192 static u8 downgrade_switch_mode(u8 func_group, u8 func_to_switch)
1193 {
1194         if (func_group == SD_FUNC_GROUP_1) {
1195                 if (func_to_switch > HS_SUPPORT) {
1196                         func_to_switch--;
1197                 }
1198         } else if (func_group == SD_FUNC_GROUP_4) {
1199                 if (func_to_switch > CURRENT_LIMIT_200) {
1200                         func_to_switch--;
1201                 }
1202         }
1203
1204         return func_to_switch;
1205 }
1206
1207 static int sd_check_switch(struct rtsx_chip *chip,
1208                 u8 func_group, u8 func_to_switch, u8 bus_width)
1209 {
1210         int retval;
1211         int i;
1212         int switch_good = 0;
1213
1214         for (i = 0; i < 3; i++) {
1215                 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
1216                         sd_set_err_code(chip, SD_NO_CARD);
1217                         TRACE_RET(chip, STATUS_FAIL);
1218                 }
1219
1220                 retval = sd_check_switch_mode(chip, SD_CHECK_MODE, func_group,
1221                                 func_to_switch, bus_width);
1222                 if (retval == STATUS_SUCCESS) {
1223                         u8 stat;
1224
1225                         retval = sd_check_switch_mode(chip, SD_SWITCH_MODE,
1226                                         func_group, func_to_switch, bus_width);
1227                         if (retval == STATUS_SUCCESS) {
1228                                 switch_good = 1;
1229                                 break;
1230                         }
1231
1232                         RTSX_READ_REG(chip, SD_STAT1, &stat);
1233                         if (stat & SD_CRC16_ERR) {
1234                                 RTSX_DEBUGP("SD CRC16 error when switching mode\n");
1235                                 TRACE_RET(chip, STATUS_FAIL);
1236                         }
1237                 }
1238
1239                 func_to_switch = downgrade_switch_mode(func_group, func_to_switch);
1240
1241                 wait_timeout(20);
1242         }
1243
1244         if (!switch_good) {
1245                 TRACE_RET(chip, STATUS_FAIL);
1246         }
1247
1248         return STATUS_SUCCESS;
1249 }
1250
1251 static int sd_switch_function(struct rtsx_chip *chip, u8 bus_width)
1252 {
1253         struct sd_info *sd_card = &(chip->sd_card);
1254         int retval;
1255         int i;
1256         u8 func_to_switch = 0;
1257
1258         /* Get supported functions */
1259         retval = sd_check_switch_mode(chip, SD_CHECK_MODE,
1260                         NO_ARGUMENT, NO_ARGUMENT, bus_width);
1261         if (retval != STATUS_SUCCESS) {
1262                 TRACE_RET(chip, STATUS_FAIL);
1263         }
1264
1265         sd_card->func_group1_mask &= ~(sd_card->sd_switch_fail);
1266
1267         /* Function Group 1: Access Mode */
1268         for (i = 0; i < 4; i++) {
1269                 switch ((u8)(chip->sd_speed_prior >> (i*8))) {
1270                 case SDR104_SUPPORT:
1271                         if ((sd_card->func_group1_mask & SDR104_SUPPORT_MASK)
1272                                         && chip->sdr104_en) {
1273                                 func_to_switch = SDR104_SUPPORT;
1274                         }
1275                         break;
1276
1277                 case DDR50_SUPPORT:
1278                         if ((sd_card->func_group1_mask & DDR50_SUPPORT_MASK)
1279                                         && chip->ddr50_en) {
1280                                 func_to_switch = DDR50_SUPPORT;
1281                         }
1282                         break;
1283
1284                 case SDR50_SUPPORT:
1285                         if ((sd_card->func_group1_mask & SDR50_SUPPORT_MASK)
1286                                         && chip->sdr50_en) {
1287                                 func_to_switch = SDR50_SUPPORT;
1288                         }
1289                         break;
1290
1291                 case HS_SUPPORT:
1292                         if (sd_card->func_group1_mask & HS_SUPPORT_MASK) {
1293                                 func_to_switch = HS_SUPPORT;
1294                         }
1295                         break;
1296
1297                 default:
1298                         continue;
1299                 }
1300
1301
1302                 if (func_to_switch) {
1303                         break;
1304                 }
1305         }
1306         RTSX_DEBUGP("SD_FUNC_GROUP_1: func_to_switch = 0x%02x", func_to_switch);
1307
1308 #ifdef SUPPORT_SD_LOCK
1309         if ((sd_card->sd_lock_status & SD_SDR_RST)
1310                         && (DDR50_SUPPORT == func_to_switch)
1311                         && (sd_card->func_group1_mask & SDR50_SUPPORT_MASK)) {
1312                 func_to_switch = SDR50_SUPPORT;
1313                 RTSX_DEBUGP("Using SDR50 instead of DDR50 for SD Lock\n");
1314         }
1315 #endif
1316
1317         if (func_to_switch) {
1318                 retval = sd_check_switch(chip, SD_FUNC_GROUP_1, func_to_switch, bus_width);
1319                 if (retval != STATUS_SUCCESS) {
1320                         if (func_to_switch == SDR104_SUPPORT) {
1321                                 sd_card->sd_switch_fail = SDR104_SUPPORT_MASK;
1322                         } else if (func_to_switch == DDR50_SUPPORT) {
1323                                 sd_card->sd_switch_fail =
1324                                         SDR104_SUPPORT_MASK | DDR50_SUPPORT_MASK;
1325                         } else if (func_to_switch == SDR50_SUPPORT) {
1326                                 sd_card->sd_switch_fail =
1327                                         SDR104_SUPPORT_MASK | DDR50_SUPPORT_MASK |
1328                                         SDR50_SUPPORT_MASK;
1329                         }
1330                         TRACE_RET(chip, STATUS_FAIL);
1331                 }
1332
1333                 if (func_to_switch == SDR104_SUPPORT) {
1334                         SET_SD_SDR104(sd_card);
1335                 } else if (func_to_switch == DDR50_SUPPORT) {
1336                         SET_SD_DDR50(sd_card);
1337                 } else if (func_to_switch == SDR50_SUPPORT) {
1338                         SET_SD_SDR50(sd_card);
1339                 } else {
1340                         SET_SD_HS(sd_card);
1341                 }
1342         }
1343
1344         if (CHK_SD_DDR50(sd_card)) {
1345                 RTSX_WRITE_REG(chip, SD_PUSH_POINT_CTL, 0x06, 0x04);
1346                 retval = sd_set_sample_push_timing(chip);
1347                 if (retval != STATUS_SUCCESS) {
1348                         TRACE_RET(chip, STATUS_FAIL);
1349                 }
1350         }
1351
1352         if (!func_to_switch || (func_to_switch == HS_SUPPORT)) {
1353                 /* Do not try to switch current limit if the card doesn't
1354                  * support UHS mode or we don't want it to support UHS mode
1355                  */
1356                 return STATUS_SUCCESS;
1357         }
1358
1359         /* Function Group 4: Current Limit */
1360         func_to_switch = 0xFF;
1361
1362         for (i = 0; i < 4; i++) {
1363                 switch ((u8)(chip->sd_current_prior >> (i*8))) {
1364                 case CURRENT_LIMIT_800:
1365                         if (sd_card->func_group4_mask & CURRENT_LIMIT_800_MASK) {
1366                                 func_to_switch = CURRENT_LIMIT_800;
1367                         }
1368                         break;
1369
1370                 case CURRENT_LIMIT_600:
1371                         if (sd_card->func_group4_mask & CURRENT_LIMIT_600_MASK) {
1372                                 func_to_switch = CURRENT_LIMIT_600;
1373                         }
1374                         break;
1375
1376                 case CURRENT_LIMIT_400:
1377                         if (sd_card->func_group4_mask & CURRENT_LIMIT_400_MASK) {
1378                                 func_to_switch = CURRENT_LIMIT_400;
1379                         }
1380                         break;
1381
1382                 case CURRENT_LIMIT_200:
1383                         if (sd_card->func_group4_mask & CURRENT_LIMIT_200_MASK) {
1384                                 func_to_switch = CURRENT_LIMIT_200;
1385                         }
1386                         break;
1387
1388                 default:
1389                         continue;
1390                 }
1391
1392                 if (func_to_switch != 0xFF) {
1393                         break;
1394                 }
1395         }
1396
1397         RTSX_DEBUGP("SD_FUNC_GROUP_4: func_to_switch = 0x%02x", func_to_switch);
1398
1399         if (func_to_switch <= CURRENT_LIMIT_800) {
1400                 retval = sd_check_switch(chip, SD_FUNC_GROUP_4, func_to_switch, bus_width);
1401                 if (retval != STATUS_SUCCESS) {
1402                         if (sd_check_err_code(chip, SD_NO_CARD)) {
1403                                 TRACE_RET(chip, STATUS_FAIL);
1404                         }
1405                 }
1406                 RTSX_DEBUGP("Switch current limit finished! (%d)\n", retval);
1407         }
1408
1409         if (CHK_SD_DDR50(sd_card)) {
1410                 RTSX_WRITE_REG(chip, SD_PUSH_POINT_CTL, 0x06, 0);
1411         }
1412
1413         return STATUS_SUCCESS;
1414 }
1415
1416 static int sd_wait_data_idle(struct rtsx_chip *chip)
1417 {
1418         int retval = STATUS_TIMEDOUT;
1419         int i;
1420         u8 val = 0;
1421
1422         for (i = 0; i < 100; i++) {
1423                 RTSX_READ_REG(chip, SD_DATA_STATE, &val);
1424                 if (val & SD_DATA_IDLE) {
1425                         retval = STATUS_SUCCESS;
1426                         break;
1427                 }
1428                 udelay(100);
1429         }
1430         RTSX_DEBUGP("SD_DATA_STATE: 0x%02x\n", val);
1431
1432         return retval;
1433 }
1434
1435 static int sd_sdr_tuning_rx_cmd(struct rtsx_chip *chip, u8 sample_point)
1436 {
1437         int retval;
1438         u8 cmd[5];
1439
1440         retval = sd_change_phase(chip, sample_point, TUNE_RX);
1441         if (retval != STATUS_SUCCESS) {
1442                 TRACE_RET(chip, STATUS_FAIL);
1443         }
1444
1445         cmd[0] = 0x40 | SEND_TUNING_PATTERN;
1446         cmd[1] = 0;
1447         cmd[2] = 0;
1448         cmd[3] = 0;
1449         cmd[4] = 0;
1450
1451         retval = sd_read_data(chip, SD_TM_AUTO_TUNING,
1452                         cmd, 5, 0x40, 1, SD_BUS_WIDTH_4, NULL, 0, 100);
1453         if (retval != STATUS_SUCCESS) {
1454                 (void)sd_wait_data_idle(chip);
1455
1456                 rtsx_clear_sd_error(chip);
1457                 TRACE_RET(chip, STATUS_FAIL);
1458         }
1459
1460         return STATUS_SUCCESS;
1461 }
1462
1463 static int sd_ddr_tuning_rx_cmd(struct rtsx_chip *chip, u8 sample_point)
1464 {
1465         struct sd_info *sd_card = &(chip->sd_card);
1466         int retval;
1467         u8 cmd[5];
1468
1469         retval = sd_change_phase(chip, sample_point, TUNE_RX);
1470         if (retval != STATUS_SUCCESS) {
1471                 TRACE_RET(chip, STATUS_FAIL);
1472         }
1473
1474         RTSX_DEBUGP("sd ddr tuning rx\n");
1475
1476         retval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
1477         if (retval != STATUS_SUCCESS) {
1478                 TRACE_RET(chip, STATUS_FAIL);
1479         }
1480
1481         cmd[0] = 0x40 | SD_STATUS;
1482         cmd[1] = 0;
1483         cmd[2] = 0;
1484         cmd[3] = 0;
1485         cmd[4] = 0;
1486
1487         retval = sd_read_data(chip, SD_TM_NORMAL_READ,
1488                         cmd, 5, 64, 1, SD_BUS_WIDTH_4, NULL, 0, 100);
1489         if (retval != STATUS_SUCCESS) {
1490                 (void)sd_wait_data_idle(chip);
1491
1492                 rtsx_clear_sd_error(chip);
1493                 TRACE_RET(chip, STATUS_FAIL);
1494         }
1495
1496         return STATUS_SUCCESS;
1497 }
1498
1499 static int mmc_ddr_tunning_rx_cmd(struct rtsx_chip *chip, u8 sample_point)
1500 {
1501         struct sd_info *sd_card = &(chip->sd_card);
1502         int retval;
1503         u8 cmd[5], bus_width;
1504
1505         if (CHK_MMC_8BIT(sd_card)) {
1506                 bus_width = SD_BUS_WIDTH_8;
1507         } else if (CHK_MMC_4BIT(sd_card)) {
1508                 bus_width = SD_BUS_WIDTH_4;
1509         } else {
1510                 bus_width = SD_BUS_WIDTH_1;
1511         }
1512
1513         retval = sd_change_phase(chip, sample_point, TUNE_RX);
1514         if (retval != STATUS_SUCCESS) {
1515                 TRACE_RET(chip, STATUS_FAIL);
1516         }
1517
1518         RTSX_DEBUGP("mmc ddr tuning rx\n");
1519
1520         cmd[0] = 0x40 | SEND_EXT_CSD;
1521         cmd[1] = 0;
1522         cmd[2] = 0;
1523         cmd[3] = 0;
1524         cmd[4] = 0;
1525
1526         retval = sd_read_data(chip, SD_TM_NORMAL_READ,
1527                         cmd, 5, 0x200, 1, bus_width, NULL, 0, 100);
1528         if (retval != STATUS_SUCCESS) {
1529                 (void)sd_wait_data_idle(chip);
1530
1531                 rtsx_clear_sd_error(chip);
1532                 TRACE_RET(chip, STATUS_FAIL);
1533         }
1534
1535         return STATUS_SUCCESS;
1536 }
1537
1538 static int sd_sdr_tuning_tx_cmd(struct rtsx_chip *chip, u8 sample_point)
1539 {
1540         struct sd_info *sd_card = &(chip->sd_card);
1541         int retval;
1542
1543         retval = sd_change_phase(chip, sample_point, TUNE_TX);
1544         if (retval != STATUS_SUCCESS) {
1545                 TRACE_RET(chip, STATUS_FAIL);
1546         }
1547
1548         RTSX_WRITE_REG(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, SD_RSP_80CLK_TIMEOUT_EN);
1549
1550         retval = sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
1551                 SD_RSP_TYPE_R1, NULL, 0);
1552         if (retval != STATUS_SUCCESS) {
1553                 if (sd_check_err_code(chip, SD_RSP_TIMEOUT)) {
1554                         rtsx_write_register(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 0);
1555                         TRACE_RET(chip, STATUS_FAIL);
1556                 }
1557         }
1558
1559         RTSX_WRITE_REG(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 0);
1560
1561         return STATUS_SUCCESS;
1562 }
1563
1564 static int sd_ddr_tuning_tx_cmd(struct rtsx_chip *chip, u8 sample_point)
1565 {
1566         struct sd_info *sd_card = &(chip->sd_card);
1567         int retval;
1568         u8 cmd[5], bus_width;
1569
1570         retval = sd_change_phase(chip, sample_point, TUNE_TX);
1571         if (retval != STATUS_SUCCESS) {
1572                 TRACE_RET(chip, STATUS_FAIL);
1573         }
1574
1575         if (CHK_SD(sd_card)) {
1576                 bus_width = SD_BUS_WIDTH_4;
1577         } else {
1578                 if (CHK_MMC_8BIT(sd_card)) {
1579                         bus_width = SD_BUS_WIDTH_8;
1580                 } else if (CHK_MMC_4BIT(sd_card)) {
1581                         bus_width = SD_BUS_WIDTH_4;
1582                 } else {
1583                         bus_width = SD_BUS_WIDTH_1;
1584                 }
1585         }
1586
1587         retval = sd_wait_state_data_ready(chip, 0x08, 1, 1000);
1588         if (retval != STATUS_SUCCESS) {
1589                 TRACE_RET(chip, STATUS_FAIL);
1590         }
1591
1592         RTSX_WRITE_REG(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, SD_RSP_80CLK_TIMEOUT_EN);
1593
1594         cmd[0] = 0x40 | PROGRAM_CSD;
1595         cmd[1] = 0;
1596         cmd[2] = 0;
1597         cmd[3] = 0;
1598         cmd[4] = 0;
1599
1600         retval = sd_write_data(chip, SD_TM_AUTO_WRITE_2,
1601                         cmd, 5, 16, 1, bus_width, sd_card->raw_csd, 16, 100);
1602         if (retval != STATUS_SUCCESS) {
1603                 rtsx_clear_sd_error(chip);
1604                 rtsx_write_register(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 0);
1605                 TRACE_RET(chip, STATUS_FAIL);
1606         }
1607
1608         RTSX_WRITE_REG(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 0);
1609
1610         sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
1611
1612         return STATUS_SUCCESS;
1613 }
1614
1615 static u8 sd_search_final_phase(struct rtsx_chip *chip, u32 phase_map, u8 tune_dir)
1616 {
1617         struct sd_info *sd_card = &(chip->sd_card);
1618         struct timing_phase_path path[MAX_PHASE + 1];
1619         int i, j, cont_path_cnt;
1620         int new_block, max_len, final_path_idx;
1621         u8 final_phase = 0xFF;
1622
1623         if (phase_map == 0xFFFFFFFF) {
1624                 if (tune_dir == TUNE_RX) {
1625                         final_phase = (u8)chip->sd_default_rx_phase;
1626                 } else {
1627                         final_phase = (u8)chip->sd_default_tx_phase;
1628                 }
1629
1630                 goto Search_Finish;
1631         }
1632
1633         cont_path_cnt = 0;
1634         new_block = 1;
1635         j = 0;
1636         for (i = 0; i < MAX_PHASE + 1; i++) {
1637                 if (phase_map & (1 << i)) {
1638                         if (new_block) {
1639                                 new_block = 0;
1640                                 j = cont_path_cnt++;
1641                                 path[j].start = i;
1642                                 path[j].end = i;
1643                         } else {
1644                                 path[j].end = i;
1645                         }
1646                 } else {
1647                         new_block = 1;
1648                         if (cont_path_cnt) {
1649                                 int idx = cont_path_cnt - 1;
1650                                 path[idx].len = path[idx].end - path[idx].start + 1;
1651                                 path[idx].mid = path[idx].start + path[idx].len / 2;
1652                         }
1653                 }
1654         }
1655
1656         if (cont_path_cnt == 0) {
1657                 RTSX_DEBUGP("No continuous phase path\n");
1658                 goto Search_Finish;
1659         } else {
1660                 int idx = cont_path_cnt - 1;
1661                 path[idx].len = path[idx].end - path[idx].start + 1;
1662                 path[idx].mid = path[idx].start + path[idx].len / 2;
1663         }
1664
1665         if ((path[0].start == 0) && (path[cont_path_cnt - 1].end == MAX_PHASE)) {
1666                 path[0].start = path[cont_path_cnt - 1].start - MAX_PHASE - 1;
1667                 path[0].len += path[cont_path_cnt - 1].len;
1668                 path[0].mid = path[0].start + path[0].len / 2;
1669                 if (path[0].mid < 0) {
1670                         path[0].mid += MAX_PHASE + 1;
1671                 }
1672                 cont_path_cnt--;
1673         }
1674
1675         max_len = 0;
1676         final_phase = 0;
1677         final_path_idx = 0;
1678         for (i = 0; i < cont_path_cnt; i++) {
1679                 if (path[i].len > max_len) {
1680                         max_len = path[i].len;
1681                         final_phase = (u8)path[i].mid;
1682                         final_path_idx = i;
1683                 }
1684
1685                 RTSX_DEBUGP("path[%d].start = %d\n", i, path[i].start);
1686                 RTSX_DEBUGP("path[%d].end = %d\n", i, path[i].end);
1687                 RTSX_DEBUGP("path[%d].len = %d\n", i, path[i].len);
1688                 RTSX_DEBUGP("path[%d].mid = %d\n", i, path[i].mid);
1689                 RTSX_DEBUGP("\n");
1690         }
1691
1692         if (tune_dir == TUNE_TX) {
1693                 if (CHK_SD_SDR104(sd_card)) {
1694                         if (max_len > 15) {
1695                                 int temp_mid = (max_len - 16) / 2;
1696                                 int temp_final_phase =
1697                                         path[final_path_idx].end - (max_len - (6 + temp_mid));
1698
1699                                 if (temp_final_phase < 0) {
1700                                         final_phase = (u8)(temp_final_phase + MAX_PHASE + 1);
1701                                 } else {
1702                                         final_phase = (u8)temp_final_phase;
1703                                 }
1704                         }
1705                 } else if (CHK_SD_SDR50(sd_card)) {
1706                         if (max_len > 12) {
1707                                 int temp_mid = (max_len - 13) / 2;
1708                                 int temp_final_phase =
1709                                         path[final_path_idx].end - (max_len - (3 + temp_mid));
1710
1711                                 if (temp_final_phase < 0) {
1712                                         final_phase = (u8)(temp_final_phase + MAX_PHASE + 1);
1713                                 } else {
1714                                         final_phase = (u8)temp_final_phase;
1715                                 }
1716                         }
1717                 }
1718         }
1719
1720 Search_Finish:
1721         RTSX_DEBUGP("Final chosen phase: %d\n", final_phase);
1722         return final_phase;
1723 }
1724
1725 static int sd_tuning_rx(struct rtsx_chip *chip)
1726 {
1727         struct sd_info *sd_card = &(chip->sd_card);
1728         int retval;
1729         int i, j;
1730         u32 raw_phase_map[3], phase_map;
1731         u8 final_phase;
1732         int (*tuning_cmd)(struct rtsx_chip *chip, u8 sample_point);
1733
1734         if (CHK_SD(sd_card)) {
1735                 if (CHK_SD_DDR50(sd_card)) {
1736                         tuning_cmd = sd_ddr_tuning_rx_cmd;
1737                 } else {
1738                         tuning_cmd = sd_sdr_tuning_rx_cmd;
1739                 }
1740         } else {
1741                 if (CHK_MMC_DDR52(sd_card)) {
1742                         tuning_cmd = mmc_ddr_tunning_rx_cmd;
1743                 } else {
1744                         TRACE_RET(chip, STATUS_FAIL);
1745                 }
1746         }
1747
1748         for (i = 0; i < 3; i++) {
1749                 raw_phase_map[i] = 0;
1750                 for (j = MAX_PHASE; j >= 0; j--) {
1751                         if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
1752                                 sd_set_err_code(chip, SD_NO_CARD);
1753                                 TRACE_RET(chip, STATUS_FAIL);
1754                         }
1755
1756                         retval = tuning_cmd(chip, (u8)j);
1757                         if (retval == STATUS_SUCCESS) {
1758                                 raw_phase_map[i] |= 1 << j;
1759                         }
1760                 }
1761         }
1762
1763         phase_map = raw_phase_map[0] & raw_phase_map[1] & raw_phase_map[2];
1764         for (i = 0; i < 3; i++) {
1765                 RTSX_DEBUGP("RX raw_phase_map[%d] = 0x%08x\n", i, raw_phase_map[i]);
1766         }
1767         RTSX_DEBUGP("RX phase_map = 0x%08x\n", phase_map);
1768
1769         final_phase = sd_search_final_phase(chip, phase_map, TUNE_RX);
1770         if (final_phase == 0xFF) {
1771                 TRACE_RET(chip, STATUS_FAIL);
1772         }
1773
1774         retval = sd_change_phase(chip, final_phase, TUNE_RX);
1775         if (retval != STATUS_SUCCESS) {
1776                 TRACE_RET(chip, STATUS_FAIL);
1777         }
1778
1779         return STATUS_SUCCESS;
1780 }
1781
1782 static int sd_ddr_pre_tuning_tx(struct rtsx_chip *chip)
1783 {
1784         struct sd_info *sd_card = &(chip->sd_card);
1785         int retval;
1786         int i;
1787         u32 phase_map;
1788         u8 final_phase;
1789
1790         RTSX_WRITE_REG(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, SD_RSP_80CLK_TIMEOUT_EN);
1791
1792         phase_map = 0;
1793         for (i = MAX_PHASE; i >= 0; i--) {
1794                 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
1795                         sd_set_err_code(chip, SD_NO_CARD);
1796                         rtsx_write_register(chip, SD_CFG3,
1797                                                 SD_RSP_80CLK_TIMEOUT_EN, 0);
1798                         TRACE_RET(chip, STATUS_FAIL);
1799                 }
1800
1801                 retval = sd_change_phase(chip, (u8)i, TUNE_TX);
1802                 if (retval != STATUS_SUCCESS) {
1803                         continue;
1804                 }
1805
1806                 retval = sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
1807                                 SD_RSP_TYPE_R1, NULL, 0);
1808                 if ((retval == STATUS_SUCCESS) || !sd_check_err_code(chip, SD_RSP_TIMEOUT)) {
1809                         phase_map |= 1 << i;
1810                 }
1811         }
1812
1813         RTSX_WRITE_REG(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 0);
1814
1815         RTSX_DEBUGP("DDR TX pre tune phase_map = 0x%08x\n", phase_map);
1816
1817         final_phase = sd_search_final_phase(chip, phase_map, TUNE_TX);
1818         if (final_phase == 0xFF) {
1819                 TRACE_RET(chip, STATUS_FAIL);
1820         }
1821
1822         retval = sd_change_phase(chip, final_phase, TUNE_TX);
1823         if (retval != STATUS_SUCCESS) {
1824                 TRACE_RET(chip, STATUS_FAIL);
1825         }
1826
1827         RTSX_DEBUGP("DDR TX pre tune phase: %d\n", (int)final_phase);
1828
1829         return STATUS_SUCCESS;
1830 }
1831
1832 static int sd_tuning_tx(struct rtsx_chip *chip)
1833 {
1834         struct sd_info *sd_card = &(chip->sd_card);
1835         int retval;
1836         int i, j;
1837         u32 raw_phase_map[3], phase_map;
1838         u8 final_phase;
1839         int (*tuning_cmd)(struct rtsx_chip *chip, u8 sample_point);
1840
1841         if (CHK_SD(sd_card)) {
1842                 if (CHK_SD_DDR50(sd_card)) {
1843                         tuning_cmd = sd_ddr_tuning_tx_cmd;
1844                 } else {
1845                         tuning_cmd = sd_sdr_tuning_tx_cmd;
1846                 }
1847         } else {
1848                 if (CHK_MMC_DDR52(sd_card)) {
1849                         tuning_cmd = sd_ddr_tuning_tx_cmd;
1850                 } else {
1851                         TRACE_RET(chip, STATUS_FAIL);
1852                 }
1853         }
1854
1855         for (i = 0; i < 3; i++) {
1856                 raw_phase_map[i] = 0;
1857                 for (j = MAX_PHASE; j >= 0; j--) {
1858                         if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
1859                                 sd_set_err_code(chip, SD_NO_CARD);
1860                                 rtsx_write_register(chip, SD_CFG3,
1861                                                     SD_RSP_80CLK_TIMEOUT_EN, 0);
1862                                 TRACE_RET(chip, STATUS_FAIL);
1863                         }
1864
1865                         retval = tuning_cmd(chip, (u8)j);
1866                         if (retval == STATUS_SUCCESS) {
1867                                 raw_phase_map[i] |= 1 << j;
1868                         }
1869                 }
1870         }
1871
1872         phase_map = raw_phase_map[0] & raw_phase_map[1] & raw_phase_map[2];
1873         for (i = 0; i < 3; i++) {
1874                 RTSX_DEBUGP("TX raw_phase_map[%d] = 0x%08x\n", i, raw_phase_map[i]);
1875         }
1876         RTSX_DEBUGP("TX phase_map = 0x%08x\n", phase_map);
1877
1878         final_phase = sd_search_final_phase(chip, phase_map, TUNE_TX);
1879         if (final_phase == 0xFF) {
1880                 TRACE_RET(chip, STATUS_FAIL);
1881         }
1882
1883         retval = sd_change_phase(chip, final_phase, TUNE_TX);
1884         if (retval != STATUS_SUCCESS) {
1885                 TRACE_RET(chip, STATUS_FAIL);
1886         }
1887
1888         return STATUS_SUCCESS;
1889 }
1890
1891 static int sd_sdr_tuning(struct rtsx_chip *chip)
1892 {
1893         int retval;
1894
1895         retval = sd_tuning_tx(chip);
1896         if (retval != STATUS_SUCCESS) {
1897                 TRACE_RET(chip, STATUS_FAIL);
1898         }
1899
1900         retval = sd_tuning_rx(chip);
1901         if (retval != STATUS_SUCCESS) {
1902                 TRACE_RET(chip, STATUS_FAIL);
1903         }
1904
1905         return STATUS_SUCCESS;
1906 }
1907
1908 static int sd_ddr_tuning(struct rtsx_chip *chip)
1909 {
1910         int retval;
1911
1912         if (!(chip->sd_ctl & SD_DDR_TX_PHASE_SET_BY_USER)) {
1913                 retval = sd_ddr_pre_tuning_tx(chip);
1914                 if (retval != STATUS_SUCCESS) {
1915                         TRACE_RET(chip, STATUS_FAIL);
1916                 }
1917         } else {
1918                 retval = sd_change_phase(chip, (u8)chip->sd_ddr_tx_phase, TUNE_TX);
1919                 if (retval != STATUS_SUCCESS) {
1920                         TRACE_RET(chip, STATUS_FAIL);
1921                 }
1922         }
1923
1924         retval = sd_tuning_rx(chip);
1925         if (retval != STATUS_SUCCESS) {
1926                 TRACE_RET(chip, STATUS_FAIL);
1927         }
1928
1929         if (!(chip->sd_ctl & SD_DDR_TX_PHASE_SET_BY_USER)) {
1930                 retval = sd_tuning_tx(chip);
1931                 if (retval != STATUS_SUCCESS) {
1932                         TRACE_RET(chip, STATUS_FAIL);
1933                 }
1934         }
1935
1936         return STATUS_SUCCESS;
1937 }
1938
1939 static int mmc_ddr_tuning(struct rtsx_chip *chip)
1940 {
1941         int retval;
1942
1943         if (!(chip->sd_ctl & MMC_DDR_TX_PHASE_SET_BY_USER)) {
1944                 retval = sd_ddr_pre_tuning_tx(chip);
1945                 if (retval != STATUS_SUCCESS) {
1946                         TRACE_RET(chip, STATUS_FAIL);
1947                 }
1948         } else {
1949                 retval = sd_change_phase(chip, (u8)chip->mmc_ddr_tx_phase, TUNE_TX);
1950                 if (retval != STATUS_SUCCESS) {
1951                         TRACE_RET(chip, STATUS_FAIL);
1952                 }
1953         }
1954
1955         retval = sd_tuning_rx(chip);
1956         if (retval != STATUS_SUCCESS) {
1957                 TRACE_RET(chip, STATUS_FAIL);
1958         }
1959
1960         if (!(chip->sd_ctl & MMC_DDR_TX_PHASE_SET_BY_USER)) {
1961                 retval = sd_tuning_tx(chip);
1962                 if (retval != STATUS_SUCCESS) {
1963                         TRACE_RET(chip, STATUS_FAIL);
1964                 }
1965         }
1966
1967         return STATUS_SUCCESS;
1968 }
1969
1970 int sd_switch_clock(struct rtsx_chip *chip)
1971 {
1972         struct sd_info *sd_card = &(chip->sd_card);
1973         int retval;
1974         int re_tuning = 0;
1975
1976         retval = select_card(chip, SD_CARD);
1977         if (retval != STATUS_SUCCESS) {
1978                 TRACE_RET(chip, STATUS_FAIL);
1979         }
1980
1981         if (CHECK_PID(chip, 0x5209) &&
1982                         (CHK_SD30_SPEED(sd_card) || CHK_MMC_DDR52(sd_card))) {
1983                 if (sd_card->need_retune && (sd_card->sd_clock != chip->cur_clk)) {
1984                         re_tuning = 1;
1985                         sd_card->need_retune = 0;
1986                 }
1987         }
1988
1989         retval = switch_clock(chip, sd_card->sd_clock);
1990         if (retval != STATUS_SUCCESS) {
1991                 TRACE_RET(chip, STATUS_FAIL);
1992         }
1993
1994         if (re_tuning) {
1995                 if (CHK_SD(sd_card)) {
1996                         if (CHK_SD_DDR50(sd_card)) {
1997                                 retval = sd_ddr_tuning(chip);
1998                         } else {
1999                                 retval = sd_sdr_tuning(chip);
2000                         }
2001                 } else {
2002                         if (CHK_MMC_DDR52(sd_card)) {
2003                                 retval = mmc_ddr_tuning(chip);
2004                         }
2005                 }
2006
2007                 if (retval != STATUS_SUCCESS) {
2008                         TRACE_RET(chip, STATUS_FAIL);
2009                 }
2010         }
2011
2012         return STATUS_SUCCESS;
2013 }
2014
2015 static int sd_prepare_reset(struct rtsx_chip *chip)
2016 {
2017         struct sd_info *sd_card = &(chip->sd_card);
2018         int retval;
2019
2020         if (chip->asic_code) {
2021                 sd_card->sd_clock = 29;
2022         } else {
2023                 sd_card->sd_clock = CLK_30;
2024         }
2025
2026         sd_card->sd_type = 0;
2027         sd_card->seq_mode = 0;
2028         sd_card->sd_data_buf_ready = 0;
2029         sd_card->capacity = 0;
2030
2031 #ifdef SUPPORT_SD_LOCK
2032         sd_card->sd_lock_status = 0;
2033         sd_card->sd_erase_status = 0;
2034 #endif
2035
2036         chip->capacity[chip->card2lun[SD_CARD]] = 0;
2037         chip->sd_io = 0;
2038
2039         retval = sd_set_init_para(chip);
2040         if (retval != STATUS_SUCCESS) {
2041                 TRACE_RET(chip, retval);
2042         }
2043
2044         if (CHECK_PID(chip, 0x5209)) {
2045                 RTSX_WRITE_REG(chip, REG_SD_CFG1, 0xFF,
2046                         SD_CLK_DIVIDE_128 | SD_20_MODE | SD_BUS_WIDTH_1);
2047                 RTSX_WRITE_REG(chip, SD_SAMPLE_POINT_CTL, 0xFF, SD20_RX_POS_EDGE);
2048                 RTSX_WRITE_REG(chip, SD_PUSH_POINT_CTL, 0xFF, 0);
2049         } else {
2050                 RTSX_WRITE_REG(chip, REG_SD_CFG1, 0xFF, 0x40);
2051         }
2052
2053         RTSX_WRITE_REG(chip, CARD_STOP, SD_STOP | SD_CLR_ERR, SD_STOP | SD_CLR_ERR);
2054
2055         retval = select_card(chip, SD_CARD);
2056         if (retval != STATUS_SUCCESS) {
2057                 TRACE_RET(chip, STATUS_FAIL);
2058         }
2059
2060         return STATUS_SUCCESS;
2061 }
2062
2063 static int sd_pull_ctl_disable(struct rtsx_chip *chip)
2064 {
2065         if (CHECK_PID(chip, 0x5209)) {
2066                 RTSX_WRITE_REG(chip, CARD_PULL_CTL1, 0xFF, 0x55);
2067                 RTSX_WRITE_REG(chip, CARD_PULL_CTL2, 0xFF, 0x55);
2068                 RTSX_WRITE_REG(chip, CARD_PULL_CTL3, 0xFF, 0xD5);
2069         } else if (CHECK_PID(chip, 0x5208)) {
2070                 RTSX_WRITE_REG(chip, CARD_PULL_CTL1, 0xFF,
2071                         XD_D3_PD | SD_D7_PD | SD_CLK_PD | SD_D5_PD);
2072                 RTSX_WRITE_REG(chip, CARD_PULL_CTL2, 0xFF,
2073                         SD_D6_PD | SD_D0_PD | SD_D1_PD | XD_D5_PD);
2074                 RTSX_WRITE_REG(chip, CARD_PULL_CTL3, 0xFF,
2075                         SD_D4_PD | XD_CE_PD | XD_CLE_PD | XD_CD_PU);
2076                 RTSX_WRITE_REG(chip, CARD_PULL_CTL4, 0xFF,
2077                         XD_RDY_PD | SD_D3_PD | SD_D2_PD | XD_ALE_PD);
2078                 RTSX_WRITE_REG(chip, CARD_PULL_CTL5, 0xFF,
2079                         MS_INS_PU | SD_WP_PD | SD_CD_PU | SD_CMD_PD);
2080                 RTSX_WRITE_REG(chip, CARD_PULL_CTL6, 0xFF, MS_D5_PD | MS_D4_PD);
2081         } else if (CHECK_PID(chip, 0x5288)) {
2082                 if (CHECK_BARO_PKG(chip, QFN)) {
2083                         RTSX_WRITE_REG(chip, CARD_PULL_CTL1, 0xFF, 0x55);
2084                         RTSX_WRITE_REG(chip, CARD_PULL_CTL2, 0xFF, 0x55);
2085                         RTSX_WRITE_REG(chip, CARD_PULL_CTL3, 0xFF, 0x4B);
2086                         RTSX_WRITE_REG(chip, CARD_PULL_CTL4, 0xFF, 0x69);
2087                 }
2088         }
2089
2090         return STATUS_SUCCESS;
2091 }
2092
2093 int sd_pull_ctl_enable(struct rtsx_chip *chip)
2094 {
2095         int retval;
2096
2097         rtsx_init_cmd(chip);
2098
2099         if (CHECK_PID(chip, 0x5209)) {
2100                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 0xAA);
2101                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0xAA);
2102                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 0xE9);
2103         } else if (CHECK_PID(chip, 0x5208)) {
2104                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF,
2105                         XD_D3_PD | SD_DAT7_PU | SD_CLK_NP | SD_D5_PU);
2106                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF,
2107                         SD_D6_PU | SD_D0_PU | SD_D1_PU | XD_D5_PD);
2108                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF,
2109                         SD_D4_PU | XD_CE_PD | XD_CLE_PD | XD_CD_PU);
2110                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF,
2111                         XD_RDY_PD | SD_D3_PU | SD_D2_PU | XD_ALE_PD);
2112                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF,
2113                         MS_INS_PU | SD_WP_PU | SD_CD_PU | SD_CMD_PU);
2114                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF, MS_D5_PD | MS_D4_PD);
2115         } else if (CHECK_PID(chip, 0x5288)) {
2116                 if (CHECK_BARO_PKG(chip, QFN)) {
2117                         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 0xA8);
2118                         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0x5A);
2119                         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 0x95);
2120                         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 0xAA);
2121                 }
2122         }
2123
2124         retval = rtsx_send_cmd(chip, SD_CARD, 100);
2125         if (retval < 0) {
2126                 TRACE_RET(chip, STATUS_FAIL);
2127         }
2128
2129         return STATUS_SUCCESS;
2130 }
2131
2132 static int sd_init_power(struct rtsx_chip *chip)
2133 {
2134         int retval;
2135
2136         if (CHECK_PID(chip, 0x5209)) {
2137                 RTSX_WRITE_REG(chip, PWR_GATE_CTRL, LDO3318_PWR_MASK, LDO_OFF);
2138         }
2139
2140         retval = sd_power_off_card3v3(chip);
2141         if (retval != STATUS_SUCCESS) {
2142                 TRACE_RET(chip, STATUS_FAIL);
2143         }
2144
2145         if (!chip->ft2_fast_mode) {
2146                 wait_timeout(250);
2147         }
2148
2149         retval = enable_card_clock(chip, SD_CARD);
2150         if (retval != STATUS_SUCCESS) {
2151                 TRACE_RET(chip, STATUS_FAIL);
2152         }
2153
2154         if (chip->asic_code) {
2155                 retval = sd_pull_ctl_enable(chip);
2156                 if (retval != STATUS_SUCCESS) {
2157                         TRACE_RET(chip, STATUS_FAIL);
2158                 }
2159         } else {
2160                 RTSX_WRITE_REG(chip, FPGA_PULL_CTL, FPGA_SD_PULL_CTL_BIT | 0x20, 0);
2161         }
2162
2163         if (chip->ft2_fast_mode) {
2164                 if (CHECK_PID(chip, 0x5209)) {
2165                         RTSX_WRITE_REG(chip, PWR_GATE_CTRL, LDO3318_PWR_MASK, LDO_ON);
2166                 }
2167         } else {
2168                 retval = card_power_on(chip, SD_CARD);
2169                 if (retval != STATUS_SUCCESS) {
2170                         TRACE_RET(chip, STATUS_FAIL);
2171                 }
2172                 wait_timeout(260);
2173
2174 #ifdef SUPPORT_OCP
2175                 if (chip->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) {
2176                         RTSX_DEBUGP("Over current, OCPSTAT is 0x%x\n", chip->ocp_stat);
2177                         TRACE_RET(chip, STATUS_FAIL);
2178                 }
2179 #endif
2180         }
2181
2182         RTSX_WRITE_REG(chip, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN);
2183
2184         return STATUS_SUCCESS;
2185 }
2186
2187 static int sd_dummy_clock(struct rtsx_chip *chip)
2188 {
2189         if (CHECK_PID(chip, 0x5209)) {
2190                 RTSX_WRITE_REG(chip, SD_BUS_STAT, SD_CLK_TOGGLE_EN, SD_CLK_TOGGLE_EN);
2191                 wait_timeout(5);
2192                 RTSX_WRITE_REG(chip, SD_BUS_STAT, SD_CLK_TOGGLE_EN, 0x00);
2193         } else {
2194                 RTSX_WRITE_REG(chip, REG_SD_CFG3, 0x01, 0x01);
2195                 wait_timeout(5);
2196                 RTSX_WRITE_REG(chip, REG_SD_CFG3, 0x01, 0);
2197         }
2198
2199         return STATUS_SUCCESS;
2200 }
2201
2202 static int sd_read_lba0(struct rtsx_chip *chip)
2203 {
2204         struct sd_info *sd_card = &(chip->sd_card);
2205         int retval;
2206         u8 cmd[5], bus_width;
2207
2208         cmd[0] = 0x40 | READ_SINGLE_BLOCK;
2209         cmd[1] = 0;
2210         cmd[2] = 0;
2211         cmd[3] = 0;
2212         cmd[4] = 0;
2213
2214         if (CHK_SD(sd_card)) {
2215                 bus_width = SD_BUS_WIDTH_4;
2216         } else {
2217                 if (CHK_MMC_8BIT(sd_card)) {
2218                         bus_width = SD_BUS_WIDTH_8;
2219                 } else if (CHK_MMC_4BIT(sd_card)) {
2220                         bus_width = SD_BUS_WIDTH_4;
2221                 } else {
2222                         bus_width = SD_BUS_WIDTH_1;
2223                 }
2224         }
2225
2226         retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd,
2227                 5, 512, 1, bus_width, NULL, 0, 100);
2228         if (retval != STATUS_SUCCESS) {
2229                 rtsx_clear_sd_error(chip);
2230                 TRACE_RET(chip, STATUS_FAIL);
2231         }
2232
2233         return STATUS_SUCCESS;
2234 }
2235
2236 static int sd_check_wp_state(struct rtsx_chip *chip)
2237 {
2238         struct sd_info *sd_card = &(chip->sd_card);
2239         int retval;
2240         u32 val;
2241         u16 sd_card_type;
2242         u8 cmd[5], buf[64];
2243
2244         retval = sd_send_cmd_get_rsp(chip, APP_CMD,
2245                         sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
2246         if (retval != STATUS_SUCCESS) {
2247                 TRACE_RET(chip, STATUS_FAIL);
2248         }
2249
2250         cmd[0] = 0x40 | SD_STATUS;
2251         cmd[1] = 0;
2252         cmd[2] = 0;
2253         cmd[3] = 0;
2254         cmd[4] = 0;
2255
2256         retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, 64, 1, SD_BUS_WIDTH_4, buf, 64, 250);
2257         if (retval != STATUS_SUCCESS) {
2258                 rtsx_clear_sd_error(chip);
2259
2260                 sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
2261                 TRACE_RET(chip, STATUS_FAIL);
2262         }
2263
2264         RTSX_DEBUGP("ACMD13:\n");
2265         RTSX_DUMP(buf, 64);
2266
2267         sd_card_type = ((u16)buf[2] << 8) | buf[3];
2268         RTSX_DEBUGP("sd_card_type = 0x%04x\n", sd_card_type);
2269         if ((sd_card_type == 0x0001) || (sd_card_type == 0x0002)) {
2270                 /* ROM card or OTP */
2271                 chip->card_wp |= SD_CARD;
2272         }
2273
2274         /* Check SD Machanical Write-Protect Switch */
2275         val = rtsx_readl(chip, RTSX_BIPR);
2276         if (val & SD_WRITE_PROTECT) {
2277                 chip->card_wp |= SD_CARD;
2278         }
2279
2280         return STATUS_SUCCESS;
2281 }
2282
2283 static int reset_sd(struct rtsx_chip *chip)
2284 {
2285         struct sd_info *sd_card = &(chip->sd_card);
2286         int retval, i = 0, j = 0, k = 0, hi_cap_flow = 0;
2287         int sd_dont_switch = 0;
2288         int support_1v8 = 0;
2289         int try_sdio = 1;
2290         u8 rsp[16];
2291         u8 switch_bus_width;
2292         u32 voltage = 0;
2293         int sd20_mode = 0;
2294
2295         SET_SD(sd_card);
2296
2297 Switch_Fail:
2298
2299         i = 0;
2300         j = 0;
2301         k = 0;
2302         hi_cap_flow = 0;
2303
2304 #ifdef SUPPORT_SD_LOCK
2305         if (sd_card->sd_lock_status & SD_UNLOCK_POW_ON)
2306                 goto SD_UNLOCK_ENTRY;
2307 #endif
2308
2309         retval = sd_prepare_reset(chip);
2310         if (retval != STATUS_SUCCESS) {
2311                 TRACE_RET(chip, STATUS_FAIL);
2312         }
2313
2314         retval = sd_dummy_clock(chip);
2315         if (retval != STATUS_SUCCESS) {
2316                 TRACE_RET(chip, STATUS_FAIL);
2317         }
2318
2319         if (CHK_SDIO_EXIST(chip) && !CHK_SDIO_IGNORED(chip) && try_sdio) {
2320                 int rty_cnt = 0;
2321
2322                 for (; rty_cnt < chip->sdio_retry_cnt; rty_cnt++) {
2323                         if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
2324                                 sd_set_err_code(chip, SD_NO_CARD);
2325                                 TRACE_RET(chip, STATUS_FAIL);
2326                         }
2327
2328                         retval = sd_send_cmd_get_rsp(chip, IO_SEND_OP_COND, 0, SD_RSP_TYPE_R4, rsp, 5);
2329                         if (retval == STATUS_SUCCESS) {
2330                                 int func_num = (rsp[1] >> 4) & 0x07;
2331                                 if (func_num) {
2332                                         RTSX_DEBUGP("SD_IO card (Function number: %d)!\n", func_num);
2333                                         chip->sd_io = 1;
2334                                         TRACE_RET(chip, STATUS_FAIL);
2335                                 }
2336
2337                                 break;
2338                         }
2339
2340                         sd_init_power(chip);
2341
2342                         sd_dummy_clock(chip);
2343                 }
2344
2345                 RTSX_DEBUGP("Normal card!\n");
2346         }
2347
2348         /* Start Initialization Process of SD Card */
2349 RTY_SD_RST:
2350         retval = sd_send_cmd_get_rsp(chip, GO_IDLE_STATE, 0, SD_RSP_TYPE_R0, NULL, 0);
2351         if (retval != STATUS_SUCCESS) {
2352                TRACE_RET(chip, STATUS_FAIL);
2353         }
2354
2355         wait_timeout(20);
2356
2357         retval = sd_send_cmd_get_rsp(chip, SEND_IF_COND, 0x000001AA, SD_RSP_TYPE_R7, rsp, 5);
2358         if (retval == STATUS_SUCCESS) {
2359                 if ((rsp[4] == 0xAA) && ((rsp[3] & 0x0f) == 0x01)) {
2360                         hi_cap_flow = 1;
2361                         if (CHECK_PID(chip, 0x5209)) {
2362                                 if (sd20_mode) {
2363                                         voltage = SUPPORT_VOLTAGE |
2364                                                 SUPPORT_HIGH_AND_EXTENDED_CAPACITY;
2365                                 } else {
2366                                         voltage = SUPPORT_VOLTAGE |
2367                                                 SUPPORT_HIGH_AND_EXTENDED_CAPACITY |
2368                                                 SUPPORT_MAX_POWER_PERMANCE | SUPPORT_1V8;
2369                                 }
2370                         } else {
2371                                 voltage = SUPPORT_VOLTAGE | 0x40000000;
2372                         }
2373                 }
2374         }
2375
2376         if (!hi_cap_flow) {
2377                 voltage = SUPPORT_VOLTAGE;
2378
2379                 retval = sd_send_cmd_get_rsp(chip, GO_IDLE_STATE, 0, SD_RSP_TYPE_R0, NULL, 0);
2380                 if (retval != STATUS_SUCCESS) {
2381                        TRACE_RET(chip, STATUS_FAIL);
2382                 }
2383
2384                 wait_timeout(20);
2385         }
2386
2387         do {
2388                 retval = sd_send_cmd_get_rsp(chip, APP_CMD, 0, SD_RSP_TYPE_R1, NULL, 0);
2389                 if (retval != STATUS_SUCCESS) {
2390                         if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
2391                                 sd_set_err_code(chip, SD_NO_CARD);
2392                                 TRACE_RET(chip, STATUS_FAIL);
2393                         }
2394
2395                         j++;
2396                         if (j < 3) {
2397                                 goto RTY_SD_RST;
2398                         } else {
2399                                 TRACE_RET(chip, STATUS_FAIL);
2400                         }
2401                 }
2402
2403                 retval = sd_send_cmd_get_rsp(chip, SD_APP_OP_COND, voltage, SD_RSP_TYPE_R3, rsp, 5);
2404                 if (retval != STATUS_SUCCESS) {
2405                         k++;
2406                         if (k < 3) {
2407                                 goto RTY_SD_RST;
2408                         } else {
2409                                 TRACE_RET(chip, STATUS_FAIL);
2410                         }
2411                 }
2412
2413                 i++;
2414                 wait_timeout(20);
2415         } while (!(rsp[1] & 0x80) && (i < 255));
2416
2417         if (i == 255) {
2418                 TRACE_RET(chip, STATUS_FAIL);
2419         }
2420
2421         if (hi_cap_flow) {
2422                 if (rsp[1] & 0x40) {
2423                         SET_SD_HCXC(sd_card);
2424                 } else {
2425                         CLR_SD_HCXC(sd_card);
2426                 }
2427                 if (CHECK_PID(chip, 0x5209) && CHK_SD_HCXC(sd_card) && !sd20_mode) {
2428                         support_1v8 = (rsp[1] & 0x01) ? 1 : 0;
2429                 } else {
2430                         support_1v8 = 0;
2431                 }
2432         } else {
2433                 CLR_SD_HCXC(sd_card);
2434                 support_1v8 = 0;
2435         }
2436         RTSX_DEBUGP("support_1v8 = %d\n", support_1v8);
2437
2438         if (support_1v8) {
2439                 retval = sd_voltage_switch(chip);
2440                 if (retval != STATUS_SUCCESS) {
2441                         TRACE_RET(chip, STATUS_FAIL);
2442                 }
2443         }
2444
2445         retval = sd_send_cmd_get_rsp(chip, ALL_SEND_CID, 0, SD_RSP_TYPE_R2, NULL, 0);
2446         if (retval != STATUS_SUCCESS) {
2447                 TRACE_RET(chip, STATUS_FAIL);
2448         }
2449
2450         for (i = 0; i < 3; i++) {
2451                 retval = sd_send_cmd_get_rsp(chip, SEND_RELATIVE_ADDR, 0, SD_RSP_TYPE_R6, rsp, 5);
2452                 if (retval != STATUS_SUCCESS) {
2453                         TRACE_RET(chip, STATUS_FAIL);
2454                 }
2455
2456                 sd_card->sd_addr = (u32)rsp[1] << 24;
2457                 sd_card->sd_addr += (u32)rsp[2] << 16;
2458
2459                 if (sd_card->sd_addr) {
2460                         break;
2461                 }
2462         }
2463
2464         retval = sd_check_csd(chip, 1);
2465         if (retval != STATUS_SUCCESS) {
2466                 TRACE_RET(chip, STATUS_FAIL);
2467         }
2468
2469         retval = sd_select_card(chip, 1);
2470         if (retval != STATUS_SUCCESS) {
2471                 TRACE_RET(chip, STATUS_FAIL);
2472         }
2473
2474 #ifdef SUPPORT_SD_LOCK
2475 SD_UNLOCK_ENTRY:
2476         retval = sd_update_lock_status(chip);
2477         if (retval != STATUS_SUCCESS) {
2478                 TRACE_RET(chip, STATUS_FAIL);
2479         }
2480
2481         if (sd_card->sd_lock_status & SD_LOCKED) {
2482                 sd_card->sd_lock_status |= (SD_LOCK_1BIT_MODE | SD_PWD_EXIST);
2483                 return STATUS_SUCCESS;
2484         } else if (!(sd_card->sd_lock_status & SD_UNLOCK_POW_ON)) {
2485                 sd_card->sd_lock_status &= ~SD_PWD_EXIST;
2486         }
2487 #endif
2488
2489         retval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
2490         if (retval != STATUS_SUCCESS) {
2491                 TRACE_RET(chip, STATUS_FAIL);
2492         }
2493         retval = sd_send_cmd_get_rsp(chip, SET_CLR_CARD_DETECT, 0, SD_RSP_TYPE_R1, NULL, 0);
2494         if (retval != STATUS_SUCCESS) {
2495                 TRACE_RET(chip, STATUS_FAIL);
2496         }
2497
2498         if (support_1v8) {
2499                 retval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
2500                 if (retval != STATUS_SUCCESS) {
2501                         TRACE_RET(chip, STATUS_FAIL);
2502                 }
2503                 retval = sd_send_cmd_get_rsp(chip, SET_BUS_WIDTH, 2, SD_RSP_TYPE_R1, NULL, 0);
2504                 if (retval != STATUS_SUCCESS) {
2505                         TRACE_RET(chip, STATUS_FAIL);
2506                 }
2507
2508                 switch_bus_width = SD_BUS_WIDTH_4;
2509         } else {
2510                 switch_bus_width = SD_BUS_WIDTH_1;
2511         }
2512
2513         retval = sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, 0x200, SD_RSP_TYPE_R1, NULL, 0);
2514         if (retval != STATUS_SUCCESS) {
2515                 TRACE_RET(chip, STATUS_FAIL);
2516         }
2517
2518         retval = sd_set_clock_divider(chip, SD_CLK_DIVIDE_0);
2519         if (retval != STATUS_SUCCESS) {
2520                 TRACE_RET(chip, STATUS_FAIL);
2521         }
2522
2523         if (!(sd_card->raw_csd[4] & 0x40))
2524                 sd_dont_switch = 1;
2525
2526         if (!sd_dont_switch) {
2527                 if (sd20_mode) {
2528                         /* Set sd_switch_fail here, because we needn't
2529                          * switch to UHS mode
2530                          */
2531                         sd_card->sd_switch_fail = SDR104_SUPPORT_MASK |
2532                                 DDR50_SUPPORT_MASK | SDR50_SUPPORT_MASK;
2533                 }
2534
2535                 /* Check the card whether follow SD1.1 spec or higher */
2536                 retval = sd_check_spec(chip, switch_bus_width);
2537                 if (retval == STATUS_SUCCESS) {
2538                         retval = sd_switch_function(chip, switch_bus_width);
2539                         if (retval != STATUS_SUCCESS) {
2540                                 if (CHECK_PID(chip, 0x5209)) {
2541                                         sd_change_bank_voltage(chip, SD_IO_3V3);
2542                                 }
2543                                 sd_init_power(chip);
2544                                 sd_dont_switch = 1;
2545                                 try_sdio = 0;
2546
2547                                 goto Switch_Fail;
2548                         }
2549                 } else {
2550                         if (support_1v8) {
2551                                 if (CHECK_PID(chip, 0x5209)) {
2552                                         sd_change_bank_voltage(chip, SD_IO_3V3);
2553                                 }
2554                                 sd_init_power(chip);
2555                                 sd_dont_switch = 1;
2556                                 try_sdio = 0;
2557
2558                                 goto Switch_Fail;
2559                         }
2560                 }
2561         }
2562
2563         if (!support_1v8) {
2564                 retval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
2565                 if (retval != STATUS_SUCCESS) {
2566                         TRACE_RET(chip, STATUS_FAIL);
2567                 }
2568                 retval = sd_send_cmd_get_rsp(chip, SET_BUS_WIDTH, 2, SD_RSP_TYPE_R1, NULL, 0);
2569                 if (retval != STATUS_SUCCESS) {
2570                         TRACE_RET(chip, STATUS_FAIL);
2571                 }
2572         }
2573
2574 #ifdef SUPPORT_SD_LOCK
2575         sd_card->sd_lock_status &= ~SD_LOCK_1BIT_MODE;
2576 #endif
2577
2578         if (!sd20_mode && CHK_SD30_SPEED(sd_card)) {
2579                 int read_lba0 = 1;
2580
2581                 RTSX_WRITE_REG(chip, SD30_DRIVE_SEL, 0x07, chip->sd30_drive_sel_1v8);
2582
2583                 retval = sd_set_init_para(chip);
2584                 if (retval != STATUS_SUCCESS) {
2585                         TRACE_RET(chip, STATUS_FAIL);
2586                 }
2587
2588                 if (CHK_SD_DDR50(sd_card)) {
2589                         retval = sd_ddr_tuning(chip);
2590                 } else {
2591                         retval = sd_sdr_tuning(chip);
2592                 }
2593
2594                 if (retval != STATUS_SUCCESS) {
2595                         if (sd20_mode) {
2596                                 TRACE_RET(chip, STATUS_FAIL);
2597                         } else {
2598                                 retval = sd_init_power(chip);
2599                                 if (retval != STATUS_SUCCESS) {
2600                                         TRACE_RET(chip, STATUS_FAIL);
2601                                 }
2602                                 try_sdio = 0;
2603                                 sd20_mode = 1;
2604                                 goto Switch_Fail;
2605                         }
2606                 }
2607
2608                 sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
2609
2610                 if (CHK_SD_DDR50(sd_card)) {
2611                         retval = sd_wait_state_data_ready(chip, 0x08, 1, 1000);
2612                         if (retval != STATUS_SUCCESS) {
2613                                 read_lba0 = 0;
2614                         }
2615                 }
2616
2617                 if (read_lba0) {
2618                         retval = sd_read_lba0(chip);
2619                         if (retval != STATUS_SUCCESS) {
2620                                 if (sd20_mode) {
2621                                         TRACE_RET(chip, STATUS_FAIL);
2622                                 } else {
2623                                         retval = sd_init_power(chip);
2624                                         if (retval != STATUS_SUCCESS) {
2625                                                 TRACE_RET(chip, STATUS_FAIL);
2626                                         }
2627                                         try_sdio = 0;
2628                                         sd20_mode = 1;
2629                                         goto Switch_Fail;
2630                                 }
2631                         }
2632                 }
2633         }
2634
2635         retval = sd_check_wp_state(chip);
2636         if (retval != STATUS_SUCCESS) {
2637                 TRACE_RET(chip, STATUS_FAIL);
2638         }
2639
2640         chip->card_bus_width[chip->card2lun[SD_CARD]] = 4;
2641
2642 #ifdef SUPPORT_SD_LOCK
2643         if (sd_card->sd_lock_status & SD_UNLOCK_POW_ON) {
2644                 RTSX_WRITE_REG(chip, REG_SD_BLOCK_CNT_H, 0xFF, 0x02);
2645                 RTSX_WRITE_REG(chip, REG_SD_BLOCK_CNT_L, 0xFF, 0x00);
2646         }
2647 #endif
2648
2649         return STATUS_SUCCESS;
2650 }
2651
2652
2653 static int mmc_test_switch_bus(struct rtsx_chip *chip, u8 width)
2654 {
2655         struct sd_info *sd_card = &(chip->sd_card);
2656         int retval;
2657         u8 buf[8] = {0}, bus_width, *ptr;
2658         u16 byte_cnt;
2659         int len;
2660
2661         retval = sd_send_cmd_get_rsp(chip, BUSTEST_W, 0, SD_RSP_TYPE_R1, NULL, 0);
2662         if (retval != STATUS_SUCCESS) {
2663                 TRACE_RET(chip, SWITCH_FAIL);
2664         }
2665
2666         if (width == MMC_8BIT_BUS) {
2667                 buf[0] = 0x55;
2668                 buf[1] = 0xAA;
2669                 len = 8;
2670                 byte_cnt = 8;
2671                 bus_width = SD_BUS_WIDTH_8;
2672         } else {
2673                 buf[0] = 0x5A;
2674                 len = 4;
2675                 byte_cnt = 4;
2676                 bus_width = SD_BUS_WIDTH_4;
2677         }
2678
2679         if (!CHECK_PID(chip, 0x5209)) {
2680                 retval = rtsx_write_register(chip, REG_SD_CFG3, 0x02, 0x02);
2681                 if (retval != STATUS_SUCCESS)
2682                         TRACE_RET(chip, SWITCH_ERR);
2683         }
2684
2685         retval = sd_write_data(chip, SD_TM_AUTO_WRITE_3,
2686                         NULL, 0, byte_cnt, 1, bus_width, buf, len, 100);
2687         if (retval != STATUS_SUCCESS) {
2688                 if (CHECK_PID(chip, 0x5209)) {
2689                         u8 val1 = 0, val2 = 0;
2690                         rtsx_read_register(chip, REG_SD_STAT1, &val1);
2691                         rtsx_read_register(chip, REG_SD_STAT2, &val2);
2692                         rtsx_clear_sd_error(chip);
2693                         if ((val1 & 0xE0) || val2) {
2694                                 TRACE_RET(chip, SWITCH_ERR);
2695                         }
2696                 } else {
2697                         rtsx_clear_sd_error(chip);
2698                         rtsx_write_register(chip, REG_SD_CFG3, 0x02, 0);
2699                         TRACE_RET(chip, SWITCH_ERR);
2700                 }
2701         }
2702
2703         if (!CHECK_PID(chip, 0x5209)) {
2704                 retval = rtsx_write_register(chip, REG_SD_CFG3, 0x02, 0);
2705                 if (retval != STATUS_SUCCESS)
2706                         TRACE_RET(chip, SWITCH_ERR);
2707         }
2708
2709         RTSX_DEBUGP("SD/MMC CMD %d\n", BUSTEST_R);
2710
2711         rtsx_init_cmd(chip);
2712
2713         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF, 0x40 | BUSTEST_R);
2714
2715         if (width == MMC_8BIT_BUS) {
2716                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, 0x08);
2717         } else {
2718                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, 0x04);
2719         }
2720
2721         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF, 1);
2722         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF, 0);
2723
2724         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF,
2725                         SD_CALCULATE_CRC7 | SD_NO_CHECK_CRC16 | SD_NO_WAIT_BUSY_END |
2726                         SD_CHECK_CRC7 | SD_RSP_LEN_6);
2727         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER);
2728         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF, SD_TM_NORMAL_READ | SD_TRANSFER_START);
2729         rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END, SD_TRANSFER_END);
2730
2731         rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2, 0, 0);
2732         if (width == MMC_8BIT_BUS) {
2733                 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 1, 0, 0);
2734         }
2735
2736         retval = rtsx_send_cmd(chip, SD_CARD, 100);
2737         if (retval < 0) {
2738                 rtsx_clear_sd_error(chip);
2739                 TRACE_RET(chip, SWITCH_ERR);
2740         }
2741
2742         ptr = rtsx_get_cmd_data(chip) + 1;
2743
2744         if (width == MMC_8BIT_BUS) {
2745                 RTSX_DEBUGP("BUSTEST_R [8bits]: 0x%02x 0x%02x\n", ptr[0], ptr[1]);
2746                 if ((ptr[0] == 0xAA) && (ptr[1] == 0x55)) {
2747                         u8 rsp[5];
2748                         u32 arg;
2749
2750                         if (CHK_MMC_DDR52(sd_card)) {
2751                                 arg = 0x03B70600;
2752                         } else {
2753                                 arg = 0x03B70200;
2754                         }
2755                         retval = sd_send_cmd_get_rsp(chip, SWITCH, arg, SD_RSP_TYPE_R1b, rsp, 5);
2756                         if ((retval == STATUS_SUCCESS) && !(rsp[4] & MMC_SWITCH_ERR)) {
2757                                 return SWITCH_SUCCESS;
2758                         }
2759                 }
2760         } else {
2761                 RTSX_DEBUGP("BUSTEST_R [4bits]: 0x%02x\n", ptr[0]);
2762                 if (ptr[0] == 0xA5) {
2763                         u8 rsp[5];
2764                         u32 arg;
2765
2766                         if (CHK_MMC_DDR52(sd_card)) {
2767                                 arg = 0x03B70500;
2768                         } else {
2769                                 arg = 0x03B70100;
2770                         }
2771                         retval = sd_send_cmd_get_rsp(chip, SWITCH, arg, SD_RSP_TYPE_R1b, rsp, 5);
2772                         if ((retval == STATUS_SUCCESS) && !(rsp[4] & MMC_SWITCH_ERR)) {
2773                                 return SWITCH_SUCCESS;
2774                         }
2775                 }
2776         }
2777
2778         TRACE_RET(chip, SWITCH_FAIL);
2779 }
2780
2781
2782 static int mmc_switch_timing_bus(struct rtsx_chip *chip, int switch_ddr)
2783 {
2784         struct sd_info *sd_card = &(chip->sd_card);
2785         int retval;
2786         u8 *ptr, card_type, card_type_mask = 0;
2787
2788         CLR_MMC_HS(sd_card);
2789
2790         RTSX_DEBUGP("SD/MMC CMD %d\n", SEND_EXT_CSD);
2791
2792         rtsx_init_cmd(chip);
2793
2794         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF, 0x40 | SEND_EXT_CSD);
2795         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD1, 0xFF, 0);
2796         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD2, 0xFF, 0);
2797         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD3, 0xFF, 0);
2798         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD4, 0xFF, 0);
2799
2800         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, 0);
2801         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF, 2);
2802         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF, 1);
2803         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF, 0);
2804
2805         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF,
2806                         SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | SD_NO_WAIT_BUSY_END |
2807                         SD_CHECK_CRC7 | SD_RSP_LEN_6);
2808         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER);
2809         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF, SD_TM_NORMAL_READ | SD_TRANSFER_START);
2810         rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END, SD_TRANSFER_END);
2811
2812         rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 196, 0xFF, 0);
2813         rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 212, 0xFF, 0);
2814         rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 213, 0xFF, 0);
2815         rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 214, 0xFF, 0);
2816         rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 215, 0xFF, 0);
2817
2818         retval = rtsx_send_cmd(chip, SD_CARD, 1000);
2819         if (retval < 0) {
2820                 if (retval == -ETIMEDOUT) {
2821                         rtsx_clear_sd_error(chip);
2822                         sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
2823                                         SD_RSP_TYPE_R1, NULL, 0);
2824                 }
2825                 TRACE_RET(chip, STATUS_FAIL);
2826         }
2827
2828         ptr = rtsx_get_cmd_data(chip);
2829         if (ptr[0] & SD_TRANSFER_ERR) {
2830                 sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
2831                 TRACE_RET(chip, STATUS_FAIL);
2832         }
2833
2834         if (CHK_MMC_SECTOR_MODE(sd_card)) {
2835                 sd_card->capacity = ((u32)ptr[5] << 24) | ((u32)ptr[4] << 16) |
2836                         ((u32)ptr[3] << 8) | ((u32)ptr[2]);
2837         }
2838
2839         if (CHECK_PID(chip, 0x5209)) {
2840 #ifdef SUPPORT_SD_LOCK
2841                 if (!(sd_card->sd_lock_status & SD_SDR_RST) &&
2842                                 (chip->sd_ctl & SUPPORT_MMC_DDR_MODE)) {
2843                         card_type_mask = 0x07;
2844                 } else {
2845                         card_type_mask = 0x03;
2846                 }
2847 #else
2848                 if (chip->sd_ctl & SUPPORT_MMC_DDR_MODE) {
2849                         card_type_mask = 0x07;
2850                 } else {
2851                         card_type_mask = 0x03;
2852                 }
2853 #endif
2854         } else {
2855                 card_type_mask = 0x03;
2856         }
2857         card_type = ptr[1] & card_type_mask;
2858         if (card_type) {
2859                 u8 rsp[5];
2860
2861                 if (card_type & 0x04) {
2862                         if (switch_ddr) {
2863                                 SET_MMC_DDR52(sd_card);
2864                         } else {
2865                                 SET_MMC_52M(sd_card);
2866                         }
2867                 } else if (card_type & 0x02) {
2868                         SET_MMC_52M(sd_card);
2869                 } else {
2870                         SET_MMC_26M(sd_card);
2871                 }
2872
2873                 retval = sd_send_cmd_get_rsp(chip, SWITCH,
2874                                 0x03B90100, SD_RSP_TYPE_R1b, rsp, 5);
2875                 if ((retval != STATUS_SUCCESS) || (rsp[4] & MMC_SWITCH_ERR)) {
2876                         CLR_MMC_HS(sd_card);
2877                 }
2878         }
2879
2880         sd_choose_proper_clock(chip);
2881         retval = switch_clock(chip, sd_card->sd_clock);
2882         if (retval != STATUS_SUCCESS) {
2883                 TRACE_RET(chip, STATUS_FAIL);
2884         }
2885
2886         /* Test Bus Procedure */
2887         retval = mmc_test_switch_bus(chip, MMC_8BIT_BUS);
2888         if (retval == SWITCH_SUCCESS) {
2889                 SET_MMC_8BIT(sd_card);
2890                 chip->card_bus_width[chip->card2lun[SD_CARD]] = 8;
2891 #ifdef SUPPORT_SD_LOCK
2892                 sd_card->sd_lock_status &= ~SD_LOCK_1BIT_MODE;
2893 #endif
2894         } else if (retval == SWITCH_FAIL) {
2895                 retval = mmc_test_switch_bus(chip, MMC_4BIT_BUS);
2896                 if (retval == SWITCH_SUCCESS) {
2897                         SET_MMC_4BIT(sd_card);
2898                         chip->card_bus_width[chip->card2lun[SD_CARD]] = 4;
2899 #ifdef SUPPORT_SD_LOCK
2900                         sd_card->sd_lock_status &= ~SD_LOCK_1BIT_MODE;
2901 #endif
2902                 } else if (retval == SWITCH_FAIL) {
2903                         CLR_MMC_8BIT(sd_card);
2904                         CLR_MMC_4BIT(sd_card);
2905                 } else {
2906                         TRACE_RET(chip, STATUS_FAIL);
2907                 }
2908         } else {
2909                 TRACE_RET(chip, STATUS_FAIL);
2910         }
2911
2912         return STATUS_SUCCESS;
2913 }
2914
2915
2916 static int reset_mmc(struct rtsx_chip *chip)
2917 {
2918         struct sd_info *sd_card = &(chip->sd_card);
2919         int retval, i = 0, j = 0, k = 0;
2920         int switch_ddr = 1;
2921         u8 rsp[16];
2922         u8 spec_ver = 0;
2923         u32 temp;
2924
2925 #ifdef SUPPORT_SD_LOCK
2926         if (sd_card->sd_lock_status & SD_UNLOCK_POW_ON)
2927                 goto MMC_UNLOCK_ENTRY;
2928 #endif
2929
2930 Switch_Fail:
2931         retval = sd_prepare_reset(chip);
2932         if (retval != STATUS_SUCCESS) {
2933                 TRACE_RET(chip, retval);
2934         }
2935
2936         SET_MMC(sd_card);
2937
2938 RTY_MMC_RST:
2939         retval = sd_send_cmd_get_rsp(chip, GO_IDLE_STATE, 0, SD_RSP_TYPE_R0, NULL, 0);
2940         if (retval != STATUS_SUCCESS) {
2941                TRACE_RET(chip, STATUS_FAIL);
2942         }
2943
2944         do {
2945                 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
2946                         sd_set_err_code(chip, SD_NO_CARD);
2947                         TRACE_RET(chip, STATUS_FAIL);
2948                 }
2949
2950                 retval = sd_send_cmd_get_rsp(chip, SEND_OP_COND,
2951                                 (SUPPORT_VOLTAGE|0x40000000), SD_RSP_TYPE_R3, rsp, 5);
2952                 if (retval != STATUS_SUCCESS) {
2953                         if (sd_check_err_code(chip, SD_BUSY) || sd_check_err_code(chip, SD_TO_ERR)) {
2954                                 k++;
2955                                 if (k < 20) {
2956                                         sd_clr_err_code(chip);
2957                                         goto RTY_MMC_RST;
2958                                 } else {
2959                                         TRACE_RET(chip, STATUS_FAIL);
2960                                 }
2961                         } else {
2962                                 j++;
2963                                 if (j < 100) {
2964                                         sd_clr_err_code(chip);
2965                                         goto RTY_MMC_RST;
2966                                 } else {
2967                                         TRACE_RET(chip, STATUS_FAIL);
2968                                 }
2969                         }
2970                 }
2971
2972                 wait_timeout(20);
2973                 i++;
2974         } while (!(rsp[1] & 0x80) && (i < 255));
2975
2976         if (i == 255) {
2977                 TRACE_RET(chip, STATUS_FAIL);
2978         }
2979
2980         if ((rsp[1] & 0x60) == 0x40) {
2981                 SET_MMC_SECTOR_MODE(sd_card);
2982         } else {
2983                 CLR_MMC_SECTOR_MODE(sd_card);
2984         }
2985
2986         retval = sd_send_cmd_get_rsp(chip, ALL_SEND_CID, 0, SD_RSP_TYPE_R2, NULL, 0);
2987         if (retval != STATUS_SUCCESS) {
2988                 TRACE_RET(chip, STATUS_FAIL);
2989         }
2990
2991         sd_card->sd_addr = 0x00100000;
2992         retval = sd_send_cmd_get_rsp(chip, SET_RELATIVE_ADDR, sd_card->sd_addr, SD_RSP_TYPE_R6, rsp, 5);
2993         if (retval != STATUS_SUCCESS) {
2994                 TRACE_RET(chip, STATUS_FAIL);
2995         }
2996
2997         retval = sd_check_csd(chip, 1);
2998         if (retval != STATUS_SUCCESS) {
2999                 TRACE_RET(chip, STATUS_FAIL);
3000         }
3001
3002         spec_ver = (sd_card->raw_csd[0] & 0x3C) >> 2;
3003
3004         retval = sd_select_card(chip, 1);
3005         if (retval != STATUS_SUCCESS) {
3006                 TRACE_RET(chip, STATUS_FAIL);
3007         }
3008
3009         retval = sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, 0x200, SD_RSP_TYPE_R1, NULL, 0);
3010         if (retval != STATUS_SUCCESS) {
3011                 TRACE_RET(chip, STATUS_FAIL);
3012         }
3013
3014 #ifdef SUPPORT_SD_LOCK
3015 MMC_UNLOCK_ENTRY:
3016         retval = sd_update_lock_status(chip);
3017         if (retval != STATUS_SUCCESS) {
3018                 TRACE_RET(chip, STATUS_FAIL);
3019         }
3020 #endif
3021
3022         retval = sd_set_clock_divider(chip, SD_CLK_DIVIDE_0);
3023         if (retval != STATUS_SUCCESS) {
3024                 TRACE_RET(chip, STATUS_FAIL);
3025         }
3026
3027         chip->card_bus_width[chip->card2lun[SD_CARD]] = 1;
3028
3029         if (!sd_card->mmc_dont_switch_bus) {
3030                 if (spec_ver == 4) {
3031                         /* MMC 4.x Cards */
3032                         retval = mmc_switch_timing_bus(chip, switch_ddr);
3033                         if (retval != STATUS_SUCCESS) {
3034                                 retval = sd_init_power(chip);
3035                                 if (retval != STATUS_SUCCESS)
3036                                         TRACE_RET(chip, STATUS_FAIL);
3037                                 sd_card->mmc_dont_switch_bus = 1;
3038                                 TRACE_GOTO(chip, Switch_Fail);
3039                         }
3040                 }
3041
3042                 if (CHK_MMC_SECTOR_MODE(sd_card) && (sd_card->capacity == 0)) {
3043                         TRACE_RET(chip, STATUS_FAIL);
3044                 }
3045
3046                 if (switch_ddr && CHK_MMC_DDR52(sd_card)) {
3047                         retval = sd_set_init_para(chip);
3048                         if (retval != STATUS_SUCCESS) {
3049                                 TRACE_RET(chip, STATUS_FAIL);
3050                         }
3051
3052                         retval = mmc_ddr_tuning(chip);
3053                         if (retval != STATUS_SUCCESS) {
3054                                 retval = sd_init_power(chip);
3055                                 if (retval != STATUS_SUCCESS) {
3056                                         TRACE_RET(chip, STATUS_FAIL);
3057                                 }
3058                                 switch_ddr = 0;
3059                                 TRACE_GOTO(chip, Switch_Fail);
3060                         }
3061
3062                         retval = sd_wait_state_data_ready(chip, 0x08, 1, 1000);
3063                         if (retval == STATUS_SUCCESS) {
3064                                 retval = sd_read_lba0(chip);
3065                                 if (retval != STATUS_SUCCESS) {
3066                                         retval = sd_init_power(chip);
3067                                         if (retval != STATUS_SUCCESS) {
3068                                                 TRACE_RET(chip, STATUS_FAIL);
3069                                         }
3070                                         switch_ddr = 0;
3071                                         TRACE_GOTO(chip, Switch_Fail);
3072                                 }
3073                         }
3074                 }
3075         }
3076
3077 #ifdef SUPPORT_SD_LOCK
3078         if (sd_card->sd_lock_status & SD_UNLOCK_POW_ON) {
3079                 RTSX_WRITE_REG(chip, REG_SD_BLOCK_CNT_H, 0xFF, 0x02);
3080                 RTSX_WRITE_REG(chip, REG_SD_BLOCK_CNT_L, 0xFF, 0x00);
3081         }
3082 #endif
3083
3084         temp = rtsx_readl(chip, RTSX_BIPR);
3085         if (temp & SD_WRITE_PROTECT) {
3086                 chip->card_wp |= SD_CARD;
3087         }
3088
3089         return STATUS_SUCCESS;
3090 }
3091
3092 int reset_sd_card(struct rtsx_chip *chip)
3093 {
3094         struct sd_info *sd_card = &(chip->sd_card);
3095         int retval;
3096
3097         sd_init_reg_addr(chip);
3098
3099         memset(sd_card, 0, sizeof(struct sd_info));
3100         chip->capacity[chip->card2lun[SD_CARD]] = 0;
3101
3102         retval = enable_card_clock(chip, SD_CARD);
3103         if (retval != STATUS_SUCCESS) {
3104                 TRACE_RET(chip, STATUS_FAIL);
3105         }
3106
3107         if (chip->ignore_sd && CHK_SDIO_EXIST(chip) && !CHK_SDIO_IGNORED(chip)) {
3108                 if (chip->asic_code) {
3109                         retval = sd_pull_ctl_enable(chip);
3110                         if (retval != STATUS_SUCCESS) {
3111                                 TRACE_RET(chip, STATUS_FAIL);
3112                         }
3113                 } else {
3114                         retval = rtsx_write_register(chip, FPGA_PULL_CTL,
3115                                                      FPGA_SD_PULL_CTL_BIT | 0x20, 0);
3116                         if (retval != STATUS_SUCCESS) {
3117                                 TRACE_RET(chip, STATUS_FAIL);
3118                         }
3119                 }
3120                 retval = card_share_mode(chip, SD_CARD);
3121                 if (retval != STATUS_SUCCESS) {
3122                         TRACE_RET(chip, STATUS_FAIL);
3123                 }
3124
3125                 chip->sd_io = 1;
3126                 TRACE_RET(chip, STATUS_FAIL);
3127         }
3128
3129         retval = sd_init_power(chip);
3130         if (retval != STATUS_SUCCESS) {
3131                 TRACE_RET(chip, STATUS_FAIL);
3132         }
3133
3134         if (chip->sd_ctl & RESET_MMC_FIRST) {
3135                 retval = reset_mmc(chip);
3136                 if (retval != STATUS_SUCCESS) {
3137                         if (sd_check_err_code(chip, SD_NO_CARD))
3138                                 TRACE_RET(chip, STATUS_FAIL);
3139
3140                         retval = reset_sd(chip);
3141                         if (retval != STATUS_SUCCESS) {
3142                                 if (CHECK_PID(chip, 0x5209))
3143                                         sd_change_bank_voltage(chip, SD_IO_3V3);
3144
3145                                 TRACE_RET(chip, STATUS_FAIL);
3146                         }
3147                 }
3148         } else {
3149                 retval = reset_sd(chip);
3150                 if (retval != STATUS_SUCCESS) {
3151                         if (sd_check_err_code(chip, SD_NO_CARD))
3152                                 TRACE_RET(chip, STATUS_FAIL);
3153
3154                         if (CHECK_PID(chip, 0x5209)) {
3155                                 retval = sd_change_bank_voltage(chip, SD_IO_3V3);
3156                                 if (retval != STATUS_SUCCESS)
3157                                         TRACE_RET(chip, STATUS_FAIL);
3158                         }
3159
3160                         if (chip->sd_io) {
3161                                 TRACE_RET(chip, STATUS_FAIL);
3162                         } else {
3163                                 retval = reset_mmc(chip);
3164                                 if (retval != STATUS_SUCCESS)
3165                                         TRACE_RET(chip, STATUS_FAIL);
3166                         }
3167                 }
3168         }
3169
3170         retval = sd_set_clock_divider(chip, SD_CLK_DIVIDE_0);
3171         if (retval != STATUS_SUCCESS) {
3172                 TRACE_RET(chip, STATUS_FAIL);
3173         }
3174         RTSX_WRITE_REG(chip, REG_SD_BYTE_CNT_L, 0xFF, 0);
3175         RTSX_WRITE_REG(chip, REG_SD_BYTE_CNT_H, 0xFF, 2);
3176
3177         chip->capacity[chip->card2lun[SD_CARD]] = sd_card->capacity;
3178
3179         retval = sd_set_init_para(chip);
3180         if (retval != STATUS_SUCCESS) {
3181                 TRACE_RET(chip, STATUS_FAIL);
3182         }
3183
3184         RTSX_DEBUGP("sd_card->sd_type = 0x%x\n", sd_card->sd_type);
3185
3186         return STATUS_SUCCESS;
3187 }
3188
3189 static int reset_mmc_only(struct rtsx_chip *chip)
3190 {
3191         struct sd_info *sd_card = &(chip->sd_card);
3192         int retval;
3193
3194         sd_card->sd_type = 0;
3195         sd_card->seq_mode = 0;
3196         sd_card->sd_data_buf_ready = 0;
3197         sd_card->capacity = 0;
3198         sd_card->sd_switch_fail = 0;
3199
3200 #ifdef SUPPORT_SD_LOCK
3201         sd_card->sd_lock_status = 0;
3202         sd_card->sd_erase_status = 0;
3203 #endif
3204
3205         chip->capacity[chip->card2lun[SD_CARD]] = sd_card->capacity = 0;
3206
3207         retval = enable_card_clock(chip, SD_CARD);
3208         if (retval != STATUS_SUCCESS) {
3209                 TRACE_RET(chip, STATUS_FAIL);
3210         }
3211
3212         retval = sd_init_power(chip);
3213         if (retval != STATUS_SUCCESS) {
3214                 TRACE_RET(chip, STATUS_FAIL);
3215         }
3216
3217         retval = reset_mmc(chip);
3218         if (retval != STATUS_SUCCESS) {
3219                 TRACE_RET(chip, STATUS_FAIL);
3220         }
3221
3222         retval = sd_set_clock_divider(chip, SD_CLK_DIVIDE_0);
3223         if (retval != STATUS_SUCCESS) {
3224                 TRACE_RET(chip, STATUS_FAIL);
3225         }
3226         RTSX_WRITE_REG(chip, REG_SD_BYTE_CNT_L, 0xFF, 0);
3227         RTSX_WRITE_REG(chip, REG_SD_BYTE_CNT_H, 0xFF, 2);
3228
3229         chip->capacity[chip->card2lun[SD_CARD]] = sd_card->capacity;
3230
3231         retval = sd_set_init_para(chip);
3232         if (retval != STATUS_SUCCESS) {
3233                 TRACE_RET(chip, STATUS_FAIL);
3234         }
3235
3236         RTSX_DEBUGP("In reset_mmc_only, sd_card->sd_type = 0x%x\n", sd_card->sd_type);
3237
3238         return STATUS_SUCCESS;
3239 }
3240
3241 #define WAIT_DATA_READY_RTY_CNT         255
3242
3243 static int wait_data_buf_ready(struct rtsx_chip *chip)
3244 {
3245         struct sd_info *sd_card = &(chip->sd_card);
3246         int i, retval;
3247
3248         for (i = 0; i < WAIT_DATA_READY_RTY_CNT; i++) {
3249                 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
3250                         sd_set_err_code(chip, SD_NO_CARD);
3251                         TRACE_RET(chip, STATUS_FAIL);
3252                 }
3253
3254                 sd_card->sd_data_buf_ready = 0;
3255
3256                 retval = sd_send_cmd_get_rsp(chip, SEND_STATUS,
3257                                 sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
3258                 if (retval != STATUS_SUCCESS) {
3259                         TRACE_RET(chip, STATUS_FAIL);
3260                 }
3261
3262                 if (sd_card->sd_data_buf_ready) {
3263                         return sd_send_cmd_get_rsp(chip, SEND_STATUS,
3264                                 sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
3265                 }
3266         }
3267
3268         sd_set_err_code(chip, SD_TO_ERR);
3269
3270         TRACE_RET(chip, STATUS_FAIL);
3271 }
3272
3273 void sd_stop_seq_mode(struct rtsx_chip *chip)
3274 {
3275         struct sd_info *sd_card = &(chip->sd_card);
3276         int retval;
3277
3278         if (sd_card->seq_mode) {
3279                 retval = sd_switch_clock(chip);
3280                 if (retval != STATUS_SUCCESS) {
3281                         return;
3282                 }
3283
3284                 retval = sd_send_cmd_get_rsp(chip, STOP_TRANSMISSION, 0,
3285                                 SD_RSP_TYPE_R1b, NULL, 0);
3286                 if (retval != STATUS_SUCCESS) {
3287                         sd_set_err_code(chip, SD_STS_ERR);
3288                 }
3289                 retval = sd_wait_state_data_ready(chip, 0x08, 1, 1000);
3290                 if (retval != STATUS_SUCCESS) {
3291                         sd_set_err_code(chip, SD_STS_ERR);
3292                 }
3293                 sd_card->seq_mode = 0;
3294
3295                 rtsx_write_register(chip, RBCTL, RB_FLUSH, RB_FLUSH);
3296         }
3297 }
3298
3299 static inline int sd_auto_tune_clock(struct rtsx_chip *chip)
3300 {
3301         struct sd_info *sd_card = &(chip->sd_card);
3302         int retval;
3303
3304         if (chip->asic_code) {
3305                 if (sd_card->sd_clock > 30) {
3306                         sd_card->sd_clock -= 20;
3307                 }
3308         } else {
3309                 switch (sd_card->sd_clock) {
3310                 case CLK_200:
3311                         sd_card->sd_clock = CLK_150;
3312                         break;
3313
3314                 case CLK_150:
3315                         sd_card->sd_clock = CLK_120;
3316                         break;
3317
3318                 case CLK_120:
3319                         sd_card->sd_clock = CLK_100;
3320                         break;
3321
3322                 case CLK_100:
3323                         sd_card->sd_clock = CLK_80;
3324                         break;
3325
3326                 case CLK_80:
3327                         sd_card->sd_clock = CLK_60;
3328                         break;
3329
3330                 case CLK_60:
3331                         sd_card->sd_clock = CLK_50;
3332                         break;
3333
3334                 default:
3335                         break;
3336                 }
3337         }
3338
3339         retval = sd_switch_clock(chip);
3340         if (retval != STATUS_SUCCESS) {
3341                 TRACE_RET(chip, STATUS_FAIL);
3342         }
3343
3344         return STATUS_SUCCESS;
3345 }
3346
3347 int sd_rw(struct scsi_cmnd *srb, struct rtsx_chip *chip, u32 start_sector, u16 sector_cnt)
3348 {
3349         struct sd_info *sd_card = &(chip->sd_card);
3350         u32 data_addr;
3351         u8 cfg2;
3352         int retval;
3353
3354         if (srb->sc_data_direction == DMA_FROM_DEVICE) {
3355                 RTSX_DEBUGP("sd_rw: Read %d %s from 0x%x\n", sector_cnt,
3356                              (sector_cnt > 1) ? "sectors" : "sector", start_sector);
3357         } else {
3358                 RTSX_DEBUGP("sd_rw: Write %d %s to 0x%x\n", sector_cnt,
3359                              (sector_cnt > 1) ? "sectors" : "sector", start_sector);
3360         }
3361
3362         sd_card->cleanup_counter = 0;
3363
3364         if (!(chip->card_ready & SD_CARD)) {
3365                 sd_card->seq_mode = 0;
3366
3367                 retval = reset_sd_card(chip);
3368                 if (retval == STATUS_SUCCESS) {
3369                         chip->card_ready |= SD_CARD;
3370                         chip->card_fail &= ~SD_CARD;
3371                 } else {
3372                         chip->card_ready &= ~SD_CARD;
3373                         chip->card_fail |= SD_CARD;
3374                         chip->capacity[chip->card2lun[SD_CARD]] = 0;
3375                         chip->rw_need_retry = 1;
3376                         TRACE_RET(chip, STATUS_FAIL);
3377                 }
3378         }
3379
3380         if (!CHK_SD_HCXC(sd_card) && !CHK_MMC_SECTOR_MODE(sd_card)) {
3381                 data_addr = start_sector << 9;
3382         } else {
3383                 data_addr = start_sector;
3384         }
3385
3386         sd_clr_err_code(chip);
3387
3388         retval = sd_switch_clock(chip);
3389         if (retval != STATUS_SUCCESS) {
3390                 sd_set_err_code(chip, SD_IO_ERR);
3391                 TRACE_GOTO(chip, RW_FAIL);
3392         }
3393
3394         if (sd_card->seq_mode && ((sd_card->pre_dir != srb->sc_data_direction)
3395                         || ((sd_card->pre_sec_addr + sd_card->pre_sec_cnt) != start_sector))) {
3396                 if ((sd_card->pre_sec_cnt < 0x80)
3397                                 && (sd_card->pre_dir == DMA_FROM_DEVICE)
3398                                 && !CHK_SD30_SPEED(sd_card)
3399                                 && !CHK_SD_HS(sd_card)
3400                                 && !CHK_MMC_HS(sd_card)) {
3401                         sd_send_cmd_get_rsp(chip, SEND_STATUS,
3402                                         sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
3403                 }
3404
3405                 retval = sd_send_cmd_get_rsp(chip, STOP_TRANSMISSION,
3406                                 0, SD_RSP_TYPE_R1b, NULL, 0);
3407                 if (retval != STATUS_SUCCESS) {
3408                         chip->rw_need_retry = 1;
3409                         sd_set_err_code(chip, SD_STS_ERR);
3410                         TRACE_GOTO(chip, RW_FAIL);
3411                 }
3412
3413                 sd_card->seq_mode = 0;
3414
3415                 retval = rtsx_write_register(chip, RBCTL, RB_FLUSH, RB_FLUSH);
3416                 if (retval != STATUS_SUCCESS) {
3417                         sd_set_err_code(chip, SD_IO_ERR);
3418                         TRACE_GOTO(chip, RW_FAIL);
3419                 }
3420
3421                 if ((sd_card->pre_sec_cnt < 0x80)
3422                                 && !CHK_SD30_SPEED(sd_card)
3423                                 && !CHK_SD_HS(sd_card)
3424                                 && !CHK_MMC_HS(sd_card)) {
3425                         sd_send_cmd_get_rsp(chip, SEND_STATUS,
3426                                         sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
3427                 }
3428         }
3429
3430         rtsx_init_cmd(chip);
3431
3432         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, 0x00);
3433         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF, 0x02);
3434         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF, (u8)sector_cnt);
3435         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF, (u8)(sector_cnt >> 8));
3436
3437         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER);
3438
3439         if (CHK_MMC_8BIT(sd_card)) {
3440                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1, 0x03, SD_BUS_WIDTH_8);
3441         } else if (CHK_MMC_4BIT(sd_card) || CHK_SD(sd_card)) {
3442                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1, 0x03, SD_BUS_WIDTH_4);
3443         } else {
3444                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1, 0x03, SD_BUS_WIDTH_1);
3445         }
3446
3447         if (sd_card->seq_mode) {
3448                 cfg2 = SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16 | SD_NO_WAIT_BUSY_END |
3449                                 SD_NO_CHECK_CRC7 | SD_RSP_LEN_0;
3450                 if (CHECK_PID(chip, 0x5209)) {
3451                         if (!CHK_SD30_SPEED(sd_card)) {
3452                                 cfg2 |= SD_NO_CHECK_WAIT_CRC_TO;
3453                         }
3454                 }
3455                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, cfg2);
3456
3457                 trans_dma_enable(srb->sc_data_direction, chip, sector_cnt * 512, DMA_512);
3458
3459                 if (srb->sc_data_direction == DMA_FROM_DEVICE) {
3460                         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
3461                                      SD_TM_AUTO_READ_3 | SD_TRANSFER_START);
3462                 } else {
3463                         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
3464                                      SD_TM_AUTO_WRITE_3 | SD_TRANSFER_START);
3465                 }
3466
3467                 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END, SD_TRANSFER_END);
3468
3469                 rtsx_send_cmd_no_wait(chip);
3470         } else {
3471                 if (srb->sc_data_direction == DMA_FROM_DEVICE) {
3472                         RTSX_DEBUGP("SD/MMC CMD %d\n", READ_MULTIPLE_BLOCK);
3473                         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF,
3474                                      0x40 | READ_MULTIPLE_BLOCK);
3475                         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD1, 0xFF, (u8)(data_addr >> 24));
3476                         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD2, 0xFF, (u8)(data_addr >> 16));
3477                         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD3, 0xFF, (u8)(data_addr >> 8));
3478                         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD4, 0xFF, (u8)data_addr);
3479
3480                         cfg2 = SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | SD_NO_WAIT_BUSY_END |
3481                                         SD_CHECK_CRC7 | SD_RSP_LEN_6;
3482                         if (CHECK_PID(chip, 0x5209)) {
3483                                 if (!CHK_SD30_SPEED(sd_card)) {
3484                                         cfg2 |= SD_NO_CHECK_WAIT_CRC_TO;
3485                                 }
3486                         }
3487                         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, cfg2);
3488
3489                         trans_dma_enable(srb->sc_data_direction, chip, sector_cnt * 512, DMA_512);
3490
3491                         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
3492                                      SD_TM_AUTO_READ_2 | SD_TRANSFER_START);
3493                         rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER,
3494                                      SD_TRANSFER_END, SD_TRANSFER_END);
3495
3496                         rtsx_send_cmd_no_wait(chip);
3497                 } else {
3498                         retval = rtsx_send_cmd(chip, SD_CARD, 50);
3499                         if (retval < 0) {
3500                                 rtsx_clear_sd_error(chip);
3501
3502                                 chip->rw_need_retry = 1;
3503                                 sd_set_err_code(chip, SD_TO_ERR);
3504                                 TRACE_GOTO(chip, RW_FAIL);
3505                         }
3506
3507                         retval = wait_data_buf_ready(chip);
3508                         if (retval != STATUS_SUCCESS) {
3509                                 chip->rw_need_retry = 1;
3510                                 sd_set_err_code(chip, SD_TO_ERR);
3511                                 TRACE_GOTO(chip, RW_FAIL);
3512                         }
3513
3514                         retval = sd_send_cmd_get_rsp(chip, WRITE_MULTIPLE_BLOCK,
3515                                         data_addr, SD_RSP_TYPE_R1, NULL, 0);
3516                         if (retval != STATUS_SUCCESS) {
3517                                 chip->rw_need_retry = 1;
3518                                 TRACE_GOTO(chip, RW_FAIL);
3519                         }
3520
3521                         rtsx_init_cmd(chip);
3522
3523                         cfg2 = SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16 | SD_NO_WAIT_BUSY_END |
3524                                         SD_NO_CHECK_CRC7 | SD_RSP_LEN_0;
3525                         if (CHECK_PID(chip, 0x5209)) {
3526                                 if (!CHK_SD30_SPEED(sd_card)) {
3527                                         cfg2 |= SD_NO_CHECK_WAIT_CRC_TO;
3528                                 }
3529                         }
3530                         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, cfg2);
3531
3532                         trans_dma_enable(srb->sc_data_direction, chip, sector_cnt * 512, DMA_512);
3533
3534                         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
3535                                      SD_TM_AUTO_WRITE_3 | SD_TRANSFER_START);
3536                         rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER,
3537                                      SD_TRANSFER_END, SD_TRANSFER_END);
3538
3539                         rtsx_send_cmd_no_wait(chip);
3540                 }
3541
3542                 sd_card->seq_mode = 1;
3543         }
3544
3545         retval = rtsx_transfer_data(chip, SD_CARD, scsi_sglist(srb), scsi_bufflen(srb),
3546                         scsi_sg_count(srb), srb->sc_data_direction, chip->sd_timeout);
3547         if (retval < 0) {
3548                 u8 stat = 0;
3549                 int err;
3550
3551                 sd_card->seq_mode = 0;
3552
3553                 if (retval == -ETIMEDOUT) {
3554                         err = STATUS_TIMEDOUT;
3555                 } else {
3556                         err = STATUS_FAIL;
3557                 }
3558
3559                 rtsx_read_register(chip, REG_SD_STAT1, &stat);
3560                 rtsx_clear_sd_error(chip);
3561                 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
3562                         chip->rw_need_retry = 0;
3563                         RTSX_DEBUGP("No card exist, exit sd_rw\n");
3564                         TRACE_RET(chip, STATUS_FAIL);
3565                 }
3566
3567                 chip->rw_need_retry = 1;
3568
3569                 retval = sd_send_cmd_get_rsp(chip, STOP_TRANSMISSION, 0, SD_RSP_TYPE_R1b, NULL, 0);
3570                 if (retval != STATUS_SUCCESS) {
3571                         sd_set_err_code(chip, SD_STS_ERR);
3572                         TRACE_GOTO(chip, RW_FAIL);
3573                 }
3574
3575                 if (stat & (SD_CRC7_ERR | SD_CRC16_ERR | SD_CRC_WRITE_ERR)) {
3576                         RTSX_DEBUGP("SD CRC error, tune clock!\n");
3577                         sd_set_err_code(chip, SD_CRC_ERR);
3578                         TRACE_GOTO(chip, RW_FAIL);
3579                 }
3580
3581                 if (err == STATUS_TIMEDOUT) {
3582                         sd_set_err_code(chip, SD_TO_ERR);
3583                         TRACE_GOTO(chip, RW_FAIL);
3584                 }
3585
3586                 TRACE_RET(chip, err);
3587         }
3588
3589         sd_card->pre_sec_addr = start_sector;
3590         sd_card->pre_sec_cnt = sector_cnt;
3591         sd_card->pre_dir = srb->sc_data_direction;
3592
3593         return STATUS_SUCCESS;
3594
3595 RW_FAIL:
3596         sd_card->seq_mode = 0;
3597
3598         if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
3599                 chip->rw_need_retry = 0;
3600                 RTSX_DEBUGP("No card exist, exit sd_rw\n");
3601                 TRACE_RET(chip, STATUS_FAIL);
3602         }
3603
3604         if (sd_check_err_code(chip, SD_CRC_ERR)) {
3605                 if (CHK_MMC_4BIT(sd_card) || CHK_MMC_8BIT(sd_card)) {
3606                         sd_card->mmc_dont_switch_bus = 1;
3607                         reset_mmc_only(chip);
3608                         sd_card->mmc_dont_switch_bus = 0;
3609                 } else {
3610                         sd_card->need_retune = 1;
3611                         sd_auto_tune_clock(chip);
3612                 }
3613         } else if (sd_check_err_code(chip, SD_TO_ERR | SD_STS_ERR)) {
3614                 retval = reset_sd_card(chip);
3615                 if (retval != STATUS_SUCCESS) {
3616                         chip->card_ready &= ~SD_CARD;
3617                         chip->card_fail |= SD_CARD;
3618                         chip->capacity[chip->card2lun[SD_CARD]] = 0;
3619                 }
3620         }
3621
3622         TRACE_RET(chip, STATUS_FAIL);
3623 }
3624
3625 #ifdef SUPPORT_CPRM
3626 int soft_reset_sd_card(struct rtsx_chip *chip)
3627 {
3628         return reset_sd(chip);
3629 }
3630
3631 int ext_sd_send_cmd_get_rsp(struct rtsx_chip *chip, u8 cmd_idx,
3632                 u32 arg, u8 rsp_type, u8 *rsp, int rsp_len, int special_check)
3633 {
3634         int retval;
3635         int timeout = 100;
3636         u16 reg_addr;
3637         u8 *ptr;
3638         int stat_idx = 0;
3639         int rty_cnt = 0;
3640
3641         RTSX_DEBUGP("EXT SD/MMC CMD %d\n", cmd_idx);
3642
3643         if (rsp_type == SD_RSP_TYPE_R1b) {
3644                 timeout = 3000;
3645         }
3646
3647 RTY_SEND_CMD:
3648
3649         rtsx_init_cmd(chip);
3650
3651         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF, 0x40 | cmd_idx);
3652         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD1, 0xFF, (u8)(arg >> 24));
3653         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD2, 0xFF, (u8)(arg >> 16));
3654         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD3, 0xFF, (u8)(arg >> 8));
3655         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD4, 0xFF, (u8)arg);
3656
3657         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, rsp_type);
3658         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE,
3659                         0x01, PINGPONG_BUFFER);
3660         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER,
3661                         0xFF, SD_TM_CMD_RSP | SD_TRANSFER_START);
3662         rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END, SD_TRANSFER_END);
3663
3664         if (rsp_type == SD_RSP_TYPE_R2) {
3665                 for (reg_addr = PPBUF_BASE2; reg_addr < PPBUF_BASE2 + 16; reg_addr++) {
3666                         rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0);
3667                 }
3668                 stat_idx = 17;
3669         } else if (rsp_type != SD_RSP_TYPE_R0) {
3670                 for (reg_addr = REG_SD_CMD0; reg_addr <= REG_SD_CMD4; reg_addr++) {
3671                         rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0);
3672                 }
3673                 stat_idx = 6;
3674         }
3675         rtsx_add_cmd(chip, READ_REG_CMD, REG_SD_CMD5, 0, 0);
3676
3677         rtsx_add_cmd(chip, READ_REG_CMD, REG_SD_STAT1, 0, 0);
3678
3679         retval = rtsx_send_cmd(chip, SD_CARD, timeout);
3680         if (retval < 0) {
3681                 if (retval == -ETIMEDOUT) {
3682                         rtsx_clear_sd_error(chip);
3683
3684                         if (rsp_type & SD_WAIT_BUSY_END) {
3685                                 retval = sd_check_data0_status(chip);
3686                                 if (retval != STATUS_SUCCESS) {
3687                                         TRACE_RET(chip, retval);
3688                                 }
3689                         } else {
3690                                 sd_set_err_code(chip, SD_TO_ERR);
3691                         }
3692                 }
3693                 TRACE_RET(chip, STATUS_FAIL);
3694         }
3695
3696         if (rsp_type == SD_RSP_TYPE_R0) {
3697                 return STATUS_SUCCESS;
3698         }
3699
3700         ptr = rtsx_get_cmd_data(chip) + 1;
3701
3702         if ((ptr[0] & 0xC0) != 0) {
3703                 sd_set_err_code(chip, SD_STS_ERR);
3704                 TRACE_RET(chip, STATUS_FAIL);
3705         }
3706
3707         if (!(rsp_type & SD_NO_CHECK_CRC7)) {
3708                 if (ptr[stat_idx] & SD_CRC7_ERR) {
3709                         if (cmd_idx == WRITE_MULTIPLE_BLOCK) {
3710                                 sd_set_err_code(chip, SD_CRC_ERR);
3711                                 TRACE_RET(chip, STATUS_FAIL);
3712                         }
3713                         if (rty_cnt < SD_MAX_RETRY_COUNT) {
3714                                 wait_timeout(20);
3715                                 rty_cnt++;
3716                                 goto RTY_SEND_CMD;
3717                         } else {
3718                                 sd_set_err_code(chip, SD_CRC_ERR);
3719                                 TRACE_RET(chip, STATUS_FAIL);
3720                         }
3721                 }
3722         }
3723
3724         if ((cmd_idx == SELECT_CARD) || (cmd_idx == APP_CMD) ||
3725                         (cmd_idx == SEND_STATUS) || (cmd_idx == STOP_TRANSMISSION)) {
3726                 if ((cmd_idx != STOP_TRANSMISSION) && (special_check == 0)) {
3727                         if (ptr[1] & 0x80) {
3728                                 TRACE_RET(chip, STATUS_FAIL);
3729                         }
3730                 }
3731 #ifdef SUPPORT_SD_LOCK
3732                 if (ptr[1] & 0x7D)
3733 #else
3734                 if (ptr[1] & 0x7F)
3735 #endif
3736                 {
3737                         TRACE_RET(chip, STATUS_FAIL);
3738                 }
3739                 if (ptr[2] & 0xF8) {
3740                         TRACE_RET(chip, STATUS_FAIL);
3741                 }
3742
3743                 if (cmd_idx == SELECT_CARD) {
3744                         if (rsp_type == SD_RSP_TYPE_R2) {
3745                                 if ((ptr[3] & 0x1E) != 0x04) {
3746                                         TRACE_RET(chip, STATUS_FAIL);
3747                                 }
3748                         } else if (rsp_type == SD_RSP_TYPE_R0) {
3749                                 if ((ptr[3] & 0x1E) != 0x03) {
3750                                         TRACE_RET(chip, STATUS_FAIL);
3751                                 }
3752                         }
3753                 }
3754         }
3755
3756         if (rsp && rsp_len) {
3757                 memcpy(rsp, ptr, rsp_len);
3758         }
3759
3760         return STATUS_SUCCESS;
3761 }
3762
3763 int ext_sd_get_rsp(struct rtsx_chip *chip, int len, u8 *rsp, u8 rsp_type)
3764 {
3765         int retval, rsp_len;
3766         u16 reg_addr;
3767
3768         if (rsp_type == SD_RSP_TYPE_R0) {
3769                 return STATUS_SUCCESS;
3770         }
3771
3772         rtsx_init_cmd(chip);
3773
3774         if (rsp_type == SD_RSP_TYPE_R2) {
3775                 for (reg_addr = PPBUF_BASE2; reg_addr < PPBUF_BASE2 + 16; reg_addr++) {
3776                         rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0xFF, 0);
3777                 }
3778                 rsp_len = 17;
3779         } else if (rsp_type != SD_RSP_TYPE_R0) {
3780                 for (reg_addr = REG_SD_CMD0; reg_addr <= REG_SD_CMD4; reg_addr++) {
3781                         rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0xFF, 0);
3782                 }
3783                 rsp_len = 6;
3784         }
3785         rtsx_add_cmd(chip, READ_REG_CMD, REG_SD_CMD5, 0xFF, 0);
3786
3787         retval = rtsx_send_cmd(chip, SD_CARD, 100);
3788         if (retval != STATUS_SUCCESS) {
3789                 TRACE_RET(chip, STATUS_FAIL);
3790         }
3791
3792         if (rsp) {
3793                 int min_len = (rsp_len < len) ? rsp_len : len;
3794
3795                 memcpy(rsp, rtsx_get_cmd_data(chip), min_len);
3796
3797                 RTSX_DEBUGP("min_len = %d\n", min_len);
3798                 RTSX_DEBUGP("Response in cmd buf: 0x%x 0x%x 0x%x 0x%x\n",
3799                         rsp[0], rsp[1], rsp[2], rsp[3]);
3800         }
3801
3802         return STATUS_SUCCESS;
3803 }
3804
3805 int sd_pass_thru_mode(struct scsi_cmnd *srb, struct rtsx_chip *chip)
3806 {
3807         struct sd_info *sd_card = &(chip->sd_card);
3808         unsigned int lun = SCSI_LUN(srb);
3809         int len;
3810         u8 buf[18] = {
3811                 0x00,
3812                 0x00,
3813                 0x00,
3814                 0x0E,
3815                 0x00,
3816                 0x00,
3817                 0x00,
3818                 0x00,
3819                 0x53,
3820                 0x44,
3821                 0x20,
3822                 0x43,
3823                 0x61,
3824                 0x72,
3825                 0x64,
3826                 0x00,
3827                 0x00,
3828                 0x00,
3829         };
3830
3831         sd_card->pre_cmd_err = 0;
3832
3833         if (!(CHK_BIT(chip->lun_mc, lun))) {
3834                 SET_BIT(chip->lun_mc, lun);
3835                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE);
3836                 TRACE_RET(chip, TRANSPORT_FAILED);
3837         }
3838
3839         if ((0x53 != srb->cmnd[2]) || (0x44 != srb->cmnd[3]) || (0x20 != srb->cmnd[4]) ||
3840                         (0x43 != srb->cmnd[5]) || (0x61 != srb->cmnd[6]) ||
3841                         (0x72 != srb->cmnd[7]) || (0x64 != srb->cmnd[8])) {
3842                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
3843                 TRACE_RET(chip, TRANSPORT_FAILED);
3844         }
3845
3846         switch (srb->cmnd[1] & 0x0F) {
3847         case 0:
3848                 sd_card->sd_pass_thru_en = 0;
3849                 break;
3850
3851         case 1:
3852                 sd_card->sd_pass_thru_en = 1;
3853                 break;
3854
3855         default:
3856                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
3857                 TRACE_RET(chip, TRANSPORT_FAILED);
3858         }
3859
3860         buf[5] = (1 == CHK_SD(sd_card)) ?  0x01 : 0x02;
3861         if (chip->card_wp & SD_CARD) {
3862                 buf[5] |= 0x80;
3863         }
3864
3865         buf[6] = (u8)(sd_card->sd_addr >> 16);
3866         buf[7] = (u8)(sd_card->sd_addr >> 24);
3867
3868         buf[15] = chip->max_lun;
3869
3870         len = min(18, (int)scsi_bufflen(srb));
3871         rtsx_stor_set_xfer_buf(buf, len, srb);
3872
3873         return TRANSPORT_GOOD;
3874 }
3875
3876 static inline int get_rsp_type(struct scsi_cmnd *srb, u8 *rsp_type, int *rsp_len)
3877 {
3878         if (!rsp_type || !rsp_len) {
3879                 return STATUS_FAIL;
3880         }
3881
3882         switch (srb->cmnd[10]) {
3883         case 0x03:
3884                 *rsp_type = SD_RSP_TYPE_R0;
3885                 *rsp_len = 0;
3886                 break;
3887
3888         case 0x04:
3889                 *rsp_type = SD_RSP_TYPE_R1;
3890                 *rsp_len = 6;
3891                 break;
3892
3893         case 0x05:
3894                 *rsp_type = SD_RSP_TYPE_R1b;
3895                 *rsp_len = 6;
3896                 break;
3897
3898         case 0x06:
3899                 *rsp_type = SD_RSP_TYPE_R2;
3900                 *rsp_len = 17;
3901                 break;
3902
3903         case 0x07:
3904                 *rsp_type = SD_RSP_TYPE_R3;
3905                 *rsp_len = 6;
3906                 break;
3907
3908         default:
3909                 return STATUS_FAIL;
3910         }
3911
3912         return STATUS_SUCCESS;
3913 }
3914
3915 int sd_execute_no_data(struct scsi_cmnd *srb, struct rtsx_chip *chip)
3916 {
3917         struct sd_info *sd_card = &(chip->sd_card);
3918         unsigned int lun = SCSI_LUN(srb);
3919         int retval, rsp_len;
3920         u8 cmd_idx, rsp_type;
3921         u8 standby = 0, acmd = 0;
3922         u32 arg;
3923
3924         if (!sd_card->sd_pass_thru_en) {
3925                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
3926                 TRACE_RET(chip, TRANSPORT_FAILED);
3927         }
3928
3929         retval = sd_switch_clock(chip);
3930         if (retval != STATUS_SUCCESS) {
3931                 TRACE_RET(chip, TRANSPORT_FAILED);
3932         }
3933
3934         if (sd_card->pre_cmd_err) {
3935                 sd_card->pre_cmd_err = 0;
3936                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE);
3937                 TRACE_RET(chip, TRANSPORT_FAILED);
3938         }
3939
3940         cmd_idx = srb->cmnd[2] & 0x3F;
3941         if (srb->cmnd[1] & 0x02) {
3942                 standby = 1;
3943         }
3944         if (srb->cmnd[1] & 0x01) {
3945                 acmd = 1;
3946         }
3947
3948         arg = ((u32)srb->cmnd[3] << 24) | ((u32)srb->cmnd[4] << 16) |
3949                 ((u32)srb->cmnd[5] << 8) | srb->cmnd[6];
3950
3951         retval = get_rsp_type(srb, &rsp_type, &rsp_len);
3952         if (retval != STATUS_SUCCESS) {
3953                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
3954                 TRACE_RET(chip, TRANSPORT_FAILED);
3955         }
3956         sd_card->last_rsp_type = rsp_type;
3957
3958         retval = sd_switch_clock(chip);
3959         if (retval != STATUS_SUCCESS) {
3960                 TRACE_RET(chip, TRANSPORT_FAILED);
3961         }
3962
3963 #ifdef SUPPORT_SD_LOCK
3964         if ((sd_card->sd_lock_status & SD_LOCK_1BIT_MODE) == 0) {
3965                 if (CHK_MMC_8BIT(sd_card)) {
3966                         retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03, SD_BUS_WIDTH_8);
3967                         if (retval != STATUS_SUCCESS) {
3968                                 TRACE_RET(chip, TRANSPORT_FAILED);
3969                         }
3970                 } else if (CHK_SD(sd_card) || CHK_MMC_4BIT(sd_card)) {
3971                         retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03, SD_BUS_WIDTH_4);
3972                         if (retval != STATUS_SUCCESS) {
3973                                 TRACE_RET(chip, TRANSPORT_FAILED);
3974                         }
3975                 }
3976         }
3977 #else
3978         retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03, SD_BUS_WIDTH_4);
3979         if (retval != STATUS_SUCCESS) {
3980                 TRACE_RET(chip, TRANSPORT_FAILED);
3981         }
3982 #endif
3983
3984         if (standby) {
3985                 retval = sd_select_card(chip, 0);
3986                 if (retval != STATUS_SUCCESS) {
3987                         TRACE_GOTO(chip, SD_Execute_Cmd_Failed);
3988                 }
3989         }
3990
3991         if (acmd) {
3992                 retval = ext_sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr,
3993                                 SD_RSP_TYPE_R1, NULL, 0, 0);
3994                 if (retval != STATUS_SUCCESS) {
3995                         TRACE_GOTO(chip, SD_Execute_Cmd_Failed);
3996                 }
3997         }
3998
3999         retval = ext_sd_send_cmd_get_rsp(chip, cmd_idx, arg, rsp_type,
4000                         sd_card->rsp, rsp_len, 0);
4001         if (retval != STATUS_SUCCESS) {
4002                 TRACE_GOTO(chip, SD_Execute_Cmd_Failed);
4003         }
4004
4005         if (standby) {
4006                 retval = sd_select_card(chip, 1);
4007                 if (retval != STATUS_SUCCESS) {
4008                         TRACE_GOTO(chip, SD_Execute_Cmd_Failed);
4009                 }
4010         }
4011
4012 #ifdef SUPPORT_SD_LOCK
4013         retval = sd_update_lock_status(chip);
4014         if (retval != STATUS_SUCCESS) {
4015                 TRACE_GOTO(chip, SD_Execute_Cmd_Failed);
4016         }
4017 #endif
4018
4019         scsi_set_resid(srb, 0);
4020         return TRANSPORT_GOOD;
4021
4022 SD_Execute_Cmd_Failed:
4023         sd_card->pre_cmd_err = 1;
4024         set_sense_type(chip, lun, SENSE_TYPE_NO_SENSE);
4025         release_sd_card(chip);
4026         do_reset_sd_card(chip);
4027         if (!(chip->card_ready & SD_CARD)) {
4028                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
4029         }
4030
4031         TRACE_RET(chip, TRANSPORT_FAILED);
4032 }
4033
4034 int sd_execute_read_data(struct scsi_cmnd *srb, struct rtsx_chip *chip)
4035 {
4036         struct sd_info *sd_card = &(chip->sd_card);
4037         unsigned int lun = SCSI_LUN(srb);
4038         int retval, rsp_len, i;
4039         int cmd13_checkbit = 0, read_err = 0;
4040         u8 cmd_idx, rsp_type, bus_width;
4041         u8 send_cmd12 = 0, standby = 0, acmd = 0;
4042         u32 data_len;
4043
4044         if (!sd_card->sd_pass_thru_en) {
4045                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4046                 TRACE_RET(chip, TRANSPORT_FAILED);
4047         }
4048
4049         if (sd_card->pre_cmd_err) {
4050                 sd_card->pre_cmd_err = 0;
4051                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE);
4052                 TRACE_RET(chip, TRANSPORT_FAILED);
4053         }
4054
4055         retval = sd_switch_clock(chip);
4056         if (retval != STATUS_SUCCESS) {
4057                 TRACE_RET(chip, TRANSPORT_FAILED);
4058         }
4059
4060         cmd_idx = srb->cmnd[2] & 0x3F;
4061         if (srb->cmnd[1] & 0x04) {
4062                 send_cmd12 = 1;
4063         }
4064         if (srb->cmnd[1] & 0x02) {
4065                 standby = 1;
4066         }
4067         if (srb->cmnd[1] & 0x01) {
4068                 acmd = 1;
4069         }
4070
4071         data_len = ((u32)srb->cmnd[7] << 16) | ((u32)srb->cmnd[8] << 8) | srb->cmnd[9];
4072
4073         retval = get_rsp_type(srb, &rsp_type, &rsp_len);
4074         if (retval != STATUS_SUCCESS) {
4075                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4076                 TRACE_RET(chip, TRANSPORT_FAILED);
4077         }
4078         sd_card->last_rsp_type = rsp_type;
4079
4080         retval = sd_switch_clock(chip);
4081         if (retval != STATUS_SUCCESS) {
4082                 TRACE_RET(chip, TRANSPORT_FAILED);
4083         }
4084
4085 #ifdef SUPPORT_SD_LOCK
4086         if ((sd_card->sd_lock_status & SD_LOCK_1BIT_MODE) == 0) {
4087                 if (CHK_MMC_8BIT(sd_card)) {
4088                         bus_width = SD_BUS_WIDTH_8;
4089                 } else if (CHK_SD(sd_card) || CHK_MMC_4BIT(sd_card)) {
4090                         bus_width = SD_BUS_WIDTH_4;
4091                 } else {
4092                         bus_width = SD_BUS_WIDTH_1;
4093                 }
4094         } else {
4095                 bus_width = SD_BUS_WIDTH_4;
4096         }
4097         RTSX_DEBUGP("bus_width = %d\n", bus_width);
4098 #else
4099         bus_width = SD_BUS_WIDTH_4;
4100 #endif
4101
4102         if (data_len < 512) {
4103                 retval = ext_sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, data_len,
4104                                 SD_RSP_TYPE_R1, NULL, 0, 0);
4105                 if (retval != STATUS_SUCCESS) {
4106                         TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
4107                 }
4108         }
4109
4110         if (standby) {
4111                 retval = sd_select_card(chip, 0);
4112                 if (retval != STATUS_SUCCESS) {
4113                         TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
4114                 }
4115         }
4116
4117         if (acmd) {
4118                 retval = ext_sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr,
4119                                 SD_RSP_TYPE_R1, NULL, 0, 0);
4120                 if (retval != STATUS_SUCCESS) {
4121                         TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
4122                 }
4123         }
4124
4125         if (data_len <= 512) {
4126                 int min_len;
4127                 u8 *buf;
4128                 u16 byte_cnt, blk_cnt;
4129                 u8 cmd[5];
4130
4131                 byte_cnt = ((u16)(srb->cmnd[8] & 0x03) << 8) | srb->cmnd[9];
4132                 blk_cnt = 1;
4133
4134                 cmd[0] = 0x40 | cmd_idx;
4135                 cmd[1] = srb->cmnd[3];
4136                 cmd[2] = srb->cmnd[4];
4137                 cmd[3] = srb->cmnd[5];
4138                 cmd[4] = srb->cmnd[6];
4139
4140                 buf = kmalloc(data_len, GFP_KERNEL);
4141                 if (buf == NULL) {
4142                         TRACE_RET(chip, TRANSPORT_ERROR);
4143                 }
4144
4145                 retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, byte_cnt,
4146                                        blk_cnt, bus_width, buf, data_len, 2000);
4147                 if (retval != STATUS_SUCCESS) {
4148                         read_err = 1;
4149                         kfree(buf);
4150                         rtsx_clear_sd_error(chip);
4151                         TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
4152                 }
4153
4154                 min_len = min(data_len, scsi_bufflen(srb));
4155                 rtsx_stor_set_xfer_buf(buf, min_len, srb);
4156
4157                 kfree(buf);
4158         } else if (!(data_len & 0x1FF)) {
4159                 rtsx_init_cmd(chip);
4160
4161                 trans_dma_enable(DMA_FROM_DEVICE, chip, data_len, DMA_512);
4162
4163                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF, 0x02);
4164                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, 0x00);
4165                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H,
4166                                 0xFF, (srb->cmnd[7] & 0xFE) >> 1);
4167                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L,
4168                                 0xFF, (u8)((data_len & 0x0001FE00) >> 9));
4169
4170                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF, 0x40 | cmd_idx);
4171                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD1, 0xFF, srb->cmnd[3]);
4172                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD2, 0xFF, srb->cmnd[4]);
4173                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD3, 0xFF, srb->cmnd[5]);
4174                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD4, 0xFF, srb->cmnd[6]);
4175
4176                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1, 0x03, bus_width);
4177                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, rsp_type);
4178
4179                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER,
4180                              0xFF, SD_TM_AUTO_READ_2 | SD_TRANSFER_START);
4181                 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END, SD_TRANSFER_END);
4182
4183                 rtsx_send_cmd_no_wait(chip);
4184
4185                 retval = rtsx_transfer_data(chip, SD_CARD, scsi_sglist(srb), scsi_bufflen(srb),
4186                         scsi_sg_count(srb), DMA_FROM_DEVICE, 10000);
4187                 if (retval < 0) {
4188                         read_err = 1;
4189                         rtsx_clear_sd_error(chip);
4190                         TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
4191                 }
4192
4193         } else {
4194                 TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
4195         }
4196
4197         retval = ext_sd_get_rsp(chip, rsp_len, sd_card->rsp, rsp_type);
4198         if (retval != STATUS_SUCCESS) {
4199                 TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
4200         }
4201
4202         if (standby) {
4203                 retval = sd_select_card(chip, 1);
4204                 if (retval != STATUS_SUCCESS) {
4205                         TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
4206                 }
4207         }
4208
4209         if (send_cmd12) {
4210                 retval = ext_sd_send_cmd_get_rsp(chip, STOP_TRANSMISSION,
4211                                 0, SD_RSP_TYPE_R1b, NULL, 0, 0);
4212                 if (retval != STATUS_SUCCESS) {
4213                         TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
4214                 }
4215         }
4216
4217         if (data_len < 512) {
4218                 retval = ext_sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, 0x200,
4219                                 SD_RSP_TYPE_R1, NULL, 0, 0);
4220                 if (retval != STATUS_SUCCESS) {
4221                         TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
4222                 }
4223
4224                 retval = rtsx_write_register(chip, SD_BYTE_CNT_H, 0xFF, 0x02);
4225                 if (retval != STATUS_SUCCESS) {
4226                         TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
4227                 }
4228                 retval = rtsx_write_register(chip, SD_BYTE_CNT_L, 0xFF, 0x00);
4229                 if (retval != STATUS_SUCCESS) {
4230                         TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
4231                 }
4232         }
4233
4234         if ((srb->cmnd[1] & 0x02) || (srb->cmnd[1] & 0x04)) {
4235                 cmd13_checkbit = 1;
4236         }
4237
4238         for (i = 0; i < 3; i++) {
4239                 retval = ext_sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
4240                         SD_RSP_TYPE_R1, NULL, 0, cmd13_checkbit);
4241                 if (retval == STATUS_SUCCESS) {
4242                         break;
4243                 }
4244         }
4245         if (retval != STATUS_SUCCESS) {
4246                 TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
4247         }
4248
4249         scsi_set_resid(srb, 0);
4250         return TRANSPORT_GOOD;
4251
4252 SD_Execute_Read_Cmd_Failed:
4253         sd_card->pre_cmd_err = 1;
4254         set_sense_type(chip, lun, SENSE_TYPE_NO_SENSE);
4255         if (read_err) {
4256                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
4257         }
4258         release_sd_card(chip);
4259         do_reset_sd_card(chip);
4260         if (!(chip->card_ready & SD_CARD)) {
4261                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
4262         }
4263
4264         TRACE_RET(chip, TRANSPORT_FAILED);
4265 }
4266
4267 int sd_execute_write_data(struct scsi_cmnd *srb, struct rtsx_chip *chip)
4268 {
4269         struct sd_info *sd_card = &(chip->sd_card);
4270         unsigned int lun = SCSI_LUN(srb);
4271         int retval, rsp_len, i;
4272         int cmd13_checkbit = 0, write_err = 0;
4273         u8 cmd_idx, rsp_type;
4274         u8 send_cmd12 = 0, standby = 0, acmd = 0;
4275         u32 data_len, arg;
4276 #ifdef SUPPORT_SD_LOCK
4277         int lock_cmd_fail = 0;
4278         u8 sd_lock_state = 0;
4279         u8 lock_cmd_type = 0;
4280 #endif
4281
4282         if (!sd_card->sd_pass_thru_en) {
4283                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4284                 TRACE_RET(chip, TRANSPORT_FAILED);
4285         }
4286
4287         if (sd_card->pre_cmd_err) {
4288                 sd_card->pre_cmd_err = 0;
4289                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE);
4290                 TRACE_RET(chip, TRANSPORT_FAILED);
4291         }
4292
4293         retval = sd_switch_clock(chip);
4294         if (retval != STATUS_SUCCESS) {
4295                 TRACE_RET(chip, TRANSPORT_FAILED);
4296         }
4297
4298         cmd_idx = srb->cmnd[2] & 0x3F;
4299         if (srb->cmnd[1] & 0x04) {
4300                 send_cmd12 = 1;
4301         }
4302         if (srb->cmnd[1] & 0x02) {
4303                 standby = 1;
4304         }
4305         if (srb->cmnd[1] & 0x01) {
4306                 acmd = 1;
4307         }
4308
4309         data_len = ((u32)srb->cmnd[7] << 16) | ((u32)srb->cmnd[8] << 8) | srb->cmnd[9];
4310         arg = ((u32)srb->cmnd[3] << 24) | ((u32)srb->cmnd[4] << 16) |
4311                 ((u32)srb->cmnd[5] << 8) | srb->cmnd[6];
4312
4313 #ifdef SUPPORT_SD_LOCK
4314         if (cmd_idx == LOCK_UNLOCK) {
4315                 sd_lock_state = sd_card->sd_lock_status;
4316                 sd_lock_state &= SD_LOCKED;
4317         }
4318 #endif
4319
4320         retval = get_rsp_type(srb, &rsp_type, &rsp_len);
4321         if (retval != STATUS_SUCCESS) {
4322                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4323                 TRACE_RET(chip, TRANSPORT_FAILED);
4324         }
4325         sd_card->last_rsp_type = rsp_type;
4326
4327         retval = sd_switch_clock(chip);
4328         if (retval != STATUS_SUCCESS) {
4329                 TRACE_RET(chip, TRANSPORT_FAILED);
4330         }
4331
4332 #ifdef SUPPORT_SD_LOCK
4333         if ((sd_card->sd_lock_status & SD_LOCK_1BIT_MODE) == 0) {
4334                 if (CHK_MMC_8BIT(sd_card)) {
4335                         retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03, SD_BUS_WIDTH_8);
4336                         if (retval != STATUS_SUCCESS) {
4337                                 TRACE_RET(chip, TRANSPORT_FAILED);
4338                         }
4339                 } else if (CHK_SD(sd_card) || CHK_MMC_4BIT(sd_card)) {
4340                         retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03, SD_BUS_WIDTH_4);
4341                         if (retval != STATUS_SUCCESS) {
4342                                 TRACE_RET(chip, TRANSPORT_FAILED);
4343                         }
4344                 }
4345         }
4346 #else
4347         retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03, SD_BUS_WIDTH_4);
4348         if (retval != STATUS_SUCCESS) {
4349                 TRACE_RET(chip, TRANSPORT_FAILED);
4350         }
4351 #endif
4352
4353         if (data_len < 512) {
4354                 retval = ext_sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, data_len,
4355                                 SD_RSP_TYPE_R1, NULL, 0, 0);
4356                 if (retval != STATUS_SUCCESS) {
4357                         TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4358                 }
4359         }
4360
4361         if (standby) {
4362                 retval = sd_select_card(chip, 0);
4363                 if (retval != STATUS_SUCCESS) {
4364                         TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4365                 }
4366         }
4367
4368         if (acmd) {
4369                 retval = ext_sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr,
4370                                 SD_RSP_TYPE_R1, NULL, 0, 0);
4371                 if (retval != STATUS_SUCCESS) {
4372                         TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4373                 }
4374         }
4375
4376         retval = ext_sd_send_cmd_get_rsp(chip, cmd_idx, arg, rsp_type,
4377                         sd_card->rsp, rsp_len, 0);
4378         if (retval != STATUS_SUCCESS) {
4379                 TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4380         }
4381
4382         if (data_len <= 512) {
4383                 u16 i;
4384                 u8 *buf;
4385
4386                 buf = kmalloc(data_len, GFP_KERNEL);
4387                 if (buf == NULL) {
4388                         TRACE_RET(chip, TRANSPORT_ERROR);
4389                 }
4390
4391                 rtsx_stor_get_xfer_buf(buf, data_len, srb);
4392
4393 #ifdef SUPPORT_SD_LOCK
4394                 if (cmd_idx == LOCK_UNLOCK) {
4395                         lock_cmd_type = buf[0] & 0x0F;
4396                 }
4397 #endif
4398
4399                 if (data_len > 256) {
4400                         rtsx_init_cmd(chip);
4401                         for (i = 0; i < 256; i++) {
4402                                 rtsx_add_cmd(chip, WRITE_REG_CMD,
4403                                                 PPBUF_BASE2 + i, 0xFF, buf[i]);
4404                         }
4405                         retval = rtsx_send_cmd(chip, 0, 250);
4406                         if (retval != STATUS_SUCCESS) {
4407                                 kfree(buf);
4408                                 TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4409                         }
4410
4411                         rtsx_init_cmd(chip);
4412                         for (i = 256; i < data_len; i++) {
4413                                 rtsx_add_cmd(chip, WRITE_REG_CMD,
4414                                                 PPBUF_BASE2 + i, 0xFF, buf[i]);
4415                         }
4416                         retval = rtsx_send_cmd(chip, 0, 250);
4417                         if (retval != STATUS_SUCCESS) {
4418                                 kfree(buf);
4419                                 TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4420                         }
4421                 } else {
4422                         rtsx_init_cmd(chip);
4423                         for (i = 0; i < data_len; i++) {
4424                                 rtsx_add_cmd(chip, WRITE_REG_CMD,
4425                                                 PPBUF_BASE2 + i, 0xFF, buf[i]);
4426                         }
4427                         retval = rtsx_send_cmd(chip, 0, 250);
4428                         if (retval != STATUS_SUCCESS) {
4429                                 kfree(buf);
4430                                 TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4431                         }
4432                 }
4433
4434                 kfree(buf);
4435
4436                 rtsx_init_cmd(chip);
4437
4438                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF, srb->cmnd[8] & 0x03);
4439                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, srb->cmnd[9]);
4440                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF, 0x00);
4441                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF, 0x01);
4442                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER);
4443
4444                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
4445                              SD_TM_AUTO_WRITE_3 | SD_TRANSFER_START);
4446                 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END, SD_TRANSFER_END);
4447
4448                 retval = rtsx_send_cmd(chip, SD_CARD, 250);
4449         } else if (!(data_len & 0x1FF)) {
4450                 rtsx_init_cmd(chip);
4451
4452                 trans_dma_enable(DMA_TO_DEVICE, chip, data_len, DMA_512);
4453
4454                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF, 0x02);
4455                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, 0x00);
4456                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H,
4457                                 0xFF, (srb->cmnd[7] & 0xFE) >> 1);
4458                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L,
4459                                 0xFF, (u8)((data_len & 0x0001FE00) >> 9));
4460
4461                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF, SD_TM_AUTO_WRITE_3 | SD_TRANSFER_START);
4462                 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END, SD_TRANSFER_END);
4463
4464                 rtsx_send_cmd_no_wait(chip);
4465
4466                 retval = rtsx_transfer_data(chip, SD_CARD, scsi_sglist(srb), scsi_bufflen(srb),
4467                         scsi_sg_count(srb), DMA_TO_DEVICE, 10000);
4468
4469         } else {
4470                 TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4471         }
4472
4473         if (retval < 0) {
4474                 write_err = 1;
4475                 rtsx_clear_sd_error(chip);
4476                 TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4477         }
4478
4479 #ifdef SUPPORT_SD_LOCK
4480         if (cmd_idx == LOCK_UNLOCK) {
4481                 if (lock_cmd_type == SD_ERASE) {
4482                         sd_card->sd_erase_status = SD_UNDER_ERASING;
4483                         scsi_set_resid(srb, 0);
4484                         return TRANSPORT_GOOD;
4485                 }
4486
4487                 rtsx_init_cmd(chip);
4488                 if (CHECK_PID(chip, 0x5209)) {
4489                         rtsx_add_cmd(chip, CHECK_REG_CMD, SD_BUS_STAT, SD_DAT0_STATUS, SD_DAT0_STATUS);
4490                 } else {
4491                         rtsx_add_cmd(chip, CHECK_REG_CMD, 0xFD30, 0x02, 0x02);
4492                 }
4493                 rtsx_send_cmd(chip, SD_CARD, 250);
4494
4495                 retval = sd_update_lock_status(chip);
4496                 if (retval != STATUS_SUCCESS) {
4497                         RTSX_DEBUGP("Lock command fail!\n");
4498                         lock_cmd_fail = 1;
4499                 }
4500         }
4501 #endif /* SUPPORT_SD_LOCK */
4502
4503         if (standby) {
4504                 retval = sd_select_card(chip, 1);
4505                 if (retval != STATUS_SUCCESS) {
4506                         TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4507                 }
4508         }
4509
4510         if (send_cmd12) {
4511                 retval = ext_sd_send_cmd_get_rsp(chip, STOP_TRANSMISSION,
4512                                 0, SD_RSP_TYPE_R1b, NULL, 0, 0);
4513                 if (retval != STATUS_SUCCESS) {
4514                         TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4515                 }
4516         }
4517
4518         if (data_len < 512) {
4519                 retval = ext_sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, 0x200,
4520                                 SD_RSP_TYPE_R1, NULL, 0, 0);
4521                 if (retval != STATUS_SUCCESS) {
4522                         TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4523                 }
4524
4525                 retval = rtsx_write_register(chip, SD_BYTE_CNT_H, 0xFF, 0x02);
4526                 if (retval != STATUS_SUCCESS) {
4527                         TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4528                 }
4529                 rtsx_write_register(chip, SD_BYTE_CNT_L, 0xFF, 0x00);
4530                 if (retval != STATUS_SUCCESS) {
4531                         TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4532                 }
4533         }
4534
4535         if ((srb->cmnd[1] & 0x02) || (srb->cmnd[1] & 0x04)) {
4536                 cmd13_checkbit = 1;
4537         }
4538
4539         for (i = 0; i < 3; i++) {
4540                 retval = ext_sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
4541                         SD_RSP_TYPE_R1, NULL, 0, cmd13_checkbit);
4542                 if (retval == STATUS_SUCCESS) {
4543                         break;
4544                 }
4545         }
4546         if (retval != STATUS_SUCCESS) {
4547                 TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4548         }
4549
4550 #ifdef SUPPORT_SD_LOCK
4551         if (cmd_idx == LOCK_UNLOCK) {
4552                 if (!lock_cmd_fail) {
4553                         RTSX_DEBUGP("lock_cmd_type = 0x%x\n", lock_cmd_type);
4554                         if (lock_cmd_type & SD_CLR_PWD) {
4555                                 sd_card->sd_lock_status &= ~SD_PWD_EXIST;
4556                         }
4557                         if (lock_cmd_type & SD_SET_PWD) {
4558                                 sd_card->sd_lock_status |= SD_PWD_EXIST;
4559                         }
4560                 }
4561
4562                 RTSX_DEBUGP("sd_lock_state = 0x%x, sd_card->sd_lock_status = 0x%x\n",
4563                              sd_lock_state, sd_card->sd_lock_status);
4564                 if (sd_lock_state ^ (sd_card->sd_lock_status & SD_LOCKED)) {
4565                         sd_card->sd_lock_notify = 1;
4566                         if (sd_lock_state) {
4567                                 if (sd_card->sd_lock_status & SD_LOCK_1BIT_MODE) {
4568                                         sd_card->sd_lock_status |= (SD_UNLOCK_POW_ON | SD_SDR_RST);
4569                                         if (CHK_SD(sd_card)) {
4570                                                 retval = reset_sd(chip);
4571                                                 if (retval != STATUS_SUCCESS) {
4572                                                         sd_card->sd_lock_status &= ~(SD_UNLOCK_POW_ON | SD_SDR_RST);
4573                                                         TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4574                                                 }
4575                                         }
4576
4577                                         sd_card->sd_lock_status &= ~(SD_UNLOCK_POW_ON | SD_SDR_RST);
4578                                 }
4579                         }
4580                 }
4581         }
4582
4583         if (lock_cmd_fail) {
4584                 scsi_set_resid(srb, 0);
4585                 set_sense_type(chip, lun, SENSE_TYPE_NO_SENSE);
4586                 TRACE_RET(chip, TRANSPORT_FAILED);
4587         }
4588 #endif  /* SUPPORT_SD_LOCK */
4589
4590         scsi_set_resid(srb, 0);
4591         return TRANSPORT_GOOD;
4592
4593 SD_Execute_Write_Cmd_Failed:
4594         sd_card->pre_cmd_err = 1;
4595         set_sense_type(chip, lun, SENSE_TYPE_NO_SENSE);
4596         if (write_err) {
4597                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_WRITE_ERR);
4598         }
4599         release_sd_card(chip);
4600         do_reset_sd_card(chip);
4601         if (!(chip->card_ready & SD_CARD)) {
4602                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
4603         }
4604
4605         TRACE_RET(chip, TRANSPORT_FAILED);
4606 }
4607
4608 int sd_get_cmd_rsp(struct scsi_cmnd *srb, struct rtsx_chip *chip)
4609 {
4610         struct sd_info *sd_card = &(chip->sd_card);
4611         unsigned int lun = SCSI_LUN(srb);
4612         int count;
4613         u16 data_len;
4614
4615         if (!sd_card->sd_pass_thru_en) {
4616                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4617                 TRACE_RET(chip, TRANSPORT_FAILED);
4618         }
4619
4620         if (sd_card->pre_cmd_err) {
4621                 sd_card->pre_cmd_err = 0;
4622                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE);
4623                 TRACE_RET(chip, TRANSPORT_FAILED);
4624         }
4625
4626         data_len = ((u16)srb->cmnd[7] << 8) | srb->cmnd[8];
4627
4628         if (sd_card->last_rsp_type == SD_RSP_TYPE_R0) {
4629                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4630                 TRACE_RET(chip, TRANSPORT_FAILED);
4631         } else if (sd_card->last_rsp_type == SD_RSP_TYPE_R2) {
4632                 count = (data_len < 17) ? data_len : 17;
4633         } else {
4634                 count = (data_len < 6) ? data_len : 6;
4635         }
4636         rtsx_stor_set_xfer_buf(sd_card->rsp, count, srb);
4637
4638         RTSX_DEBUGP("Response length: %d\n", data_len);
4639         RTSX_DEBUGP("Response: 0x%x 0x%x 0x%x 0x%x\n",
4640                 sd_card->rsp[0], sd_card->rsp[1], sd_card->rsp[2], sd_card->rsp[3]);
4641
4642         scsi_set_resid(srb, 0);
4643         return TRANSPORT_GOOD;
4644 }
4645
4646 int sd_hw_rst(struct scsi_cmnd *srb, struct rtsx_chip *chip)
4647 {
4648         struct sd_info *sd_card = &(chip->sd_card);
4649         unsigned int lun = SCSI_LUN(srb);
4650         int retval;
4651
4652         if (!sd_card->sd_pass_thru_en) {
4653                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4654                 TRACE_RET(chip, TRANSPORT_FAILED);
4655         }
4656
4657         if (sd_card->pre_cmd_err) {
4658                 sd_card->pre_cmd_err = 0;
4659                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE);
4660                 TRACE_RET(chip, TRANSPORT_FAILED);
4661         }
4662
4663         if ((0x53 != srb->cmnd[2]) || (0x44 != srb->cmnd[3]) || (0x20 != srb->cmnd[4]) ||
4664                         (0x43 != srb->cmnd[5]) || (0x61 != srb->cmnd[6]) ||
4665                         (0x72 != srb->cmnd[7]) || (0x64 != srb->cmnd[8])) {
4666                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4667                 TRACE_RET(chip, TRANSPORT_FAILED);
4668         }
4669
4670         switch (srb->cmnd[1] & 0x0F) {
4671         case 0:
4672 #ifdef SUPPORT_SD_LOCK
4673                 if (0x64 == srb->cmnd[9]) {
4674                         sd_card->sd_lock_status |= SD_SDR_RST;
4675                 }
4676 #endif
4677                 retval = reset_sd_card(chip);
4678                 if (retval != STATUS_SUCCESS) {
4679 #ifdef SUPPORT_SD_LOCK
4680                         sd_card->sd_lock_status &= ~SD_SDR_RST;
4681 #endif
4682                         set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
4683                         sd_card->pre_cmd_err = 1;
4684                         TRACE_RET(chip, TRANSPORT_FAILED);
4685                 }
4686 #ifdef SUPPORT_SD_LOCK
4687                 sd_card->sd_lock_status &= ~SD_SDR_RST;
4688 #endif
4689                 break;
4690
4691         case 1:
4692                 retval = soft_reset_sd_card(chip);
4693                 if (retval != STATUS_SUCCESS) {
4694                         set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
4695                         sd_card->pre_cmd_err = 1;
4696                         TRACE_RET(chip, TRANSPORT_FAILED);
4697                 }
4698                 break;
4699
4700         default:
4701                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4702                 TRACE_RET(chip, TRANSPORT_FAILED);
4703         }
4704
4705         scsi_set_resid(srb, 0);
4706         return TRANSPORT_GOOD;
4707 }
4708 #endif
4709
4710 void sd_cleanup_work(struct rtsx_chip *chip)
4711 {
4712         struct sd_info *sd_card = &(chip->sd_card);
4713
4714         if (sd_card->seq_mode) {
4715                 RTSX_DEBUGP("SD: stop transmission\n");
4716                 sd_stop_seq_mode(chip);
4717                 sd_card->cleanup_counter = 0;
4718         }
4719 }
4720
4721 int sd_power_off_card3v3(struct rtsx_chip *chip)
4722 {
4723         int retval;
4724
4725         retval = disable_card_clock(chip, SD_CARD);
4726         if (retval != STATUS_SUCCESS) {
4727                 TRACE_RET(chip, STATUS_FAIL);
4728         }
4729
4730         RTSX_WRITE_REG(chip, CARD_OE, SD_OUTPUT_EN, 0);
4731
4732         if (!chip->ft2_fast_mode) {
4733                 retval = card_power_off(chip, SD_CARD);
4734                 if (retval != STATUS_SUCCESS) {
4735                         TRACE_RET(chip, STATUS_FAIL);
4736                 }
4737
4738                 wait_timeout(50);
4739         }
4740
4741         if (chip->asic_code) {
4742                 retval = sd_pull_ctl_disable(chip);
4743                 if (retval != STATUS_SUCCESS) {
4744                         TRACE_RET(chip, STATUS_FAIL);
4745                 }
4746         } else {
4747                 RTSX_WRITE_REG(chip, FPGA_PULL_CTL,
4748                         FPGA_SD_PULL_CTL_BIT | 0x20, FPGA_SD_PULL_CTL_BIT);
4749         }
4750
4751         return STATUS_SUCCESS;
4752 }
4753
4754 int release_sd_card(struct rtsx_chip *chip)
4755 {
4756         struct sd_info *sd_card = &(chip->sd_card);
4757         int retval;
4758
4759         RTSX_DEBUGP("release_sd_card\n");
4760
4761         chip->card_ready &= ~SD_CARD;
4762         chip->card_fail &= ~SD_CARD;
4763         chip->card_wp &= ~SD_CARD;
4764
4765         chip->sd_io = 0;
4766         chip->sd_int = 0;
4767
4768 #ifdef SUPPORT_SD_LOCK
4769         sd_card->sd_lock_status = 0;
4770         sd_card->sd_erase_status = 0;
4771 #endif
4772
4773         memset(sd_card->raw_csd, 0, 16);
4774         memset(sd_card->raw_scr, 0, 8);
4775
4776         retval = sd_power_off_card3v3(chip);
4777         if (retval != STATUS_SUCCESS) {
4778                 TRACE_RET(chip, STATUS_FAIL);
4779         }
4780
4781         if (CHECK_PID(chip, 0x5209)) {
4782                 retval = sd_change_bank_voltage(chip, SD_IO_3V3);
4783                 if (retval != STATUS_SUCCESS) {
4784                         TRACE_RET(chip, STATUS_FAIL);
4785                 }
4786
4787                 if (CHK_SD30_SPEED(sd_card)) {
4788                         RTSX_WRITE_REG(chip, SD30_DRIVE_SEL, 0x07, chip->sd30_drive_sel_3v3);
4789                 }
4790
4791                 RTSX_WRITE_REG(chip, OCPPARA2, SD_OCP_THD_MASK, chip->sd_400mA_ocp_thd);
4792         }
4793
4794         return STATUS_SUCCESS;
4795 }