Pileus Git - ~andy/linux/blob - drivers/staging/rts5139/sd.c

   1 /* Driver for Realtek RTS51xx USB card reader
   2  *
   3  * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License as published by the
   7  * Free Software Foundation; either version 2, or (at your option) any
   8  * later version.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program; if not, see <http://www.gnu.org/licenses/>.
  17  *
  18  * Author:
  19  *   wwang (wei_wang@realsil.com.cn)
  20  *   No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
  21  * Maintainer:
  22  *   Edwin Rong (edwin_rong@realsil.com.cn)
  23  *   No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
  24  */
  25
  26 #include <linux/blkdev.h>
  27 #include <linux/kthread.h>
  28 #include <linux/sched.h>
  29
  30 #include "debug.h"
  31 #include "trace.h"
  32 #include "rts51x.h"
  33 #include "rts51x_transport.h"
  34 #include "rts51x_scsi.h"
  35 #include "rts51x_card.h"
  36 #include "sd.h"
  37
  38 static inline void sd_set_reset_fail(struct rts51x_chip *chip, u8 err_code)
  39 {
  40         struct sd_info *sd_card = &(chip->sd_card);
  41
  42         sd_card->sd_reset_fail |= err_code;
  43 }
  44
  45 static inline void sd_clear_reset_fail(struct rts51x_chip *chip)
  46 {
  47         struct sd_info *sd_card = &(chip->sd_card);
  48
  49         sd_card->sd_reset_fail = 0;
  50 }
  51
  52 static inline int sd_check_reset_fail(struct rts51x_chip *chip, u8 err_code)
  53 {
  54         struct sd_info *sd_card = &(chip->sd_card);
  55
  56         return sd_card->sd_reset_fail & err_code;
  57 }
  58
  59 static inline void sd_set_err_code(struct rts51x_chip *chip, u8 err_code)
  60 {
  61         struct sd_info *sd_card = &(chip->sd_card);
  62
  63         sd_card->err_code |= err_code;
  64 }
  65
  66 static inline void sd_clr_err_code(struct rts51x_chip *chip)
  67 {
  68         struct sd_info *sd_card = &(chip->sd_card);
  69
  70         sd_card->err_code = 0;
  71 }
  72
  73 static inline int sd_check_err_code(struct rts51x_chip *chip, u8 err_code)
  74 {
  75         struct sd_info *sd_card = &(chip->sd_card);
  76
  77         return sd_card->err_code & err_code;
  78 }
  79
  80 static int sd_parse_err_code(struct rts51x_chip *chip)
  81 {
  82         TRACE_RET(chip, STATUS_FAIL);
  83 }
  84
  85 int sd_check_data0_status(struct rts51x_chip *chip)
  86 {
  87         int retval;
  88         u8 stat;
  89
  90         retval = rts51x_ep0_read_register(chip, SD_BUS_STAT, &stat);
  91         if (retval != STATUS_SUCCESS)
  92                 TRACE_RET(chip, retval);
  93         if (!(stat & SD_DAT0_STATUS)) {
  94                 sd_set_err_code(chip, SD_BUSY);
  95                 TRACE_RET(chip, STATUS_FAIL);
  96         }
  97
  98         return STATUS_SUCCESS;
  99 }
 100
 101 static int sd_send_cmd_get_rsp(struct rts51x_chip *chip, u8 cmd_idx,
 102                                u32 arg, u8 rsp_type, u8 *rsp, int rsp_len)
 103 {
 104         struct sd_info *sd_card = &(chip->sd_card);
 105         int retval;
 106         int timeout = 50;
 107         u16 reg_addr;
 108         u8 buf[17], stat;
 109         int len = 2;
 110         int rty_cnt = 0;
 111
 112         sd_clr_err_code(chip);
 113
 114         RTS51X_DEBUGP("SD/MMC CMD %d, arg = 0x%08x\n", cmd_idx, arg);
 115
 116         if (rsp_type == SD_RSP_TYPE_R1b)
 117                 timeout = 3000;
 118
 119 RTY_SEND_CMD:
 120
 121         rts51x_init_cmd(chip);
 122
 123         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CMD0, 0xFF, 0x40 | cmd_idx);
 124         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CMD1, 0xFF, (u8) (arg >> 24));
 125         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CMD2, 0xFF, (u8) (arg >> 16));
 126         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CMD3, 0xFF, (u8) (arg >> 8));
 127         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CMD4, 0xFF, (u8) arg);
 128
 129         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CFG2, 0xFF, rsp_type);
 130         rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,
 131                        PINGPONG_BUFFER);
 132         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
 133                        SD_TM_CMD_RSP | SD_TRANSFER_START);
 134         rts51x_add_cmd(chip, CHECK_REG_CMD, SD_TRANSFER,
 135                        SD_TRANSFER_END | SD_STAT_IDLE,
 136                        SD_TRANSFER_END | SD_STAT_IDLE);
 137
 138         rts51x_add_cmd(chip, READ_REG_CMD, SD_STAT1, 0, 0);
 139
 140         if (CHECK_USB(chip, USB_20)) {
 141                 if (rsp_type == SD_RSP_TYPE_R2) {
 142                         /* Read data from ping-pong buffer */
 143                         for (reg_addr = PPBUF_BASE2;
 144                              reg_addr < PPBUF_BASE2 + 16; reg_addr++) {
 145                                 rts51x_add_cmd(chip, READ_REG_CMD, reg_addr, 0,
 146                                                0);
 147                         }
 148                         len = 18;
 149                 } else if (rsp_type != SD_RSP_TYPE_R0) {
 150                         /* Read data from SD_CMDx registers */
 151                         for (reg_addr = SD_CMD0; reg_addr <= SD_CMD4;
 152                              reg_addr++) {
 153                                 rts51x_add_cmd(chip, READ_REG_CMD, reg_addr, 0,
 154                                                0);
 155                         }
 156                         len = 7;
 157                 } else {
 158                         len = 2;
 159                 }
 160         } else {
 161                 len = 2;
 162         }
 163
 164         retval = rts51x_send_cmd(chip, MODE_CR, 100);
 165         if (retval != STATUS_SUCCESS)
 166                 TRACE_RET(chip, retval);
 167
 168         retval = rts51x_get_rsp(chip, len, timeout);
 169
 170         if (CHECK_SD_TRANS_FAIL(chip, retval)) {
 171                 u8 val;
 172
 173                 rts51x_ep0_read_register(chip, SD_STAT1, &val);
 174                 RTS51X_DEBUGP("SD_STAT1: 0x%x\n", val);
 175
 176                 rts51x_ep0_read_register(chip, SD_STAT2, &val);
 177                 RTS51X_DEBUGP("SD_STAT2: 0x%x\n", val);
 178
 179                 if (val & SD_RSP_80CLK_TIMEOUT)
 180                         sd_set_err_code(chip, SD_RSP_TIMEOUT);
 181
 182                 rts51x_ep0_read_register(chip, SD_BUS_STAT, &val);
 183                 RTS51X_DEBUGP("SD_BUS_STAT: 0x%x\n", val);
 184
 185                 if (retval == STATUS_TIMEDOUT) {
 186                         if (rsp_type & SD_WAIT_BUSY_END) {
 187                                 retval = sd_check_data0_status(chip);
 188                                 if (retval != STATUS_SUCCESS)
 189                                         TRACE_RET(chip, retval);
 190                         } else {
 191                                 sd_set_err_code(chip, SD_TO_ERR);
 192                         }
 193                 }
 194                 rts51x_clear_sd_error(chip);
 195
 196                 TRACE_RET(chip, STATUS_FAIL);
 197         }
 198
 199         if (rsp_type == SD_RSP_TYPE_R0)
 200                 return STATUS_SUCCESS;
 201
 202         if (CHECK_USB(chip, USB_20)) {
 203                 rts51x_read_rsp_buf(chip, 2, buf, len - 2);
 204         } else {
 205                 if (rsp_type == SD_RSP_TYPE_R2) {
 206                         reg_addr = PPBUF_BASE2;
 207                         len = 16;
 208                 } else {
 209                         reg_addr = SD_CMD0;
 210                         len = 5;
 211                 }
 212                 retval = rts51x_seq_read_register(chip, reg_addr,
 213                                                      (unsigned short)len, buf);
 214                 if (retval != STATUS_SUCCESS)
 215                         TRACE_RET(chip, retval);
 216         }
 217         stat = chip->rsp_buf[1];
 218
 219         /* Check (Start,Transmission) bit of Response */
 220         if ((buf[0] & 0xC0) != 0) {
 221                 sd_set_err_code(chip, SD_STS_ERR);
 222                 TRACE_RET(chip, STATUS_FAIL);
 223         }
 224         /* Check CRC7 */
 225         if (!(rsp_type & SD_NO_CHECK_CRC7)) {
 226                 if (stat & SD_CRC7_ERR) {
 227                         if (cmd_idx == WRITE_MULTIPLE_BLOCK) {
 228                                 sd_set_err_code(chip, SD_CRC_ERR);
 229                                 TRACE_RET(chip, STATUS_FAIL);
 230                         }
 231                         if (rty_cnt < SD_MAX_RETRY_COUNT) {
 232                                 wait_timeout(20);
 233                                 rty_cnt++;
 234                                 goto RTY_SEND_CMD;
 235                         } else {
 236                                 sd_set_err_code(chip, SD_CRC_ERR);
 237                                 TRACE_RET(chip, STATUS_FAIL);
 238                         }
 239                 }
 240         }
 241         /* Check Status */
 242         if ((rsp_type == SD_RSP_TYPE_R1) || (rsp_type == SD_RSP_TYPE_R1b)) {
 243                 if ((cmd_idx != SEND_RELATIVE_ADDR)
 244                     && (cmd_idx != SEND_IF_COND)) {
 245                         if (cmd_idx != STOP_TRANSMISSION) {
 246                                 if (buf[1] & 0x80)
 247                                         TRACE_RET(chip, STATUS_FAIL);
 248                         }
 249                         if (buf[1] & 0x7F) {
 250                                 RTS51X_DEBUGP("buf[1]: 0x%02x\n", buf[1]);
 251                                 TRACE_RET(chip, STATUS_FAIL);
 252                         }
 253                         if (buf[2] & 0xFF) {
 254                                 RTS51X_DEBUGP("buf[2]: 0x%02x\n", buf[2]);
 255                                 TRACE_RET(chip, STATUS_FAIL);
 256                         }
 257                         if (buf[3] & 0x80) {
 258                                 RTS51X_DEBUGP("buf[3]: 0x%02x\n", buf[3]);
 259                                 TRACE_RET(chip, STATUS_FAIL);
 260                         }
 261                         if (buf[3] & 0x01) {
 262                                 /* Get "READY_FOR_DATA" bit */
 263                                 sd_card->sd_data_buf_ready = 1;
 264                         } else {
 265                                 sd_card->sd_data_buf_ready = 0;
 266                         }
 267                 }
 268         }
 269
 270         if (rsp && rsp_len)
 271                 memcpy(rsp, buf, rsp_len);
 272
 273         return STATUS_SUCCESS;
 274 }
 275
 276 static inline void sd_print_debug_reg(struct rts51x_chip *chip)
 277 {
 278 #ifdef CONFIG_RTS5139_DEBUG
 279         u8 val = 0;
 280
 281         rts51x_ep0_read_register(chip, SD_STAT1, &val);
 282         RTS51X_DEBUGP("SD_STAT1: 0x%x\n", val);
 283         rts51x_ep0_read_register(chip, SD_STAT2, &val);
 284         RTS51X_DEBUGP("SD_STAT2: 0x%x\n", val);
 285         rts51x_ep0_read_register(chip, SD_BUS_STAT, &val);
 286         RTS51X_DEBUGP("SD_BUS_STAT: 0x%x\n", val);
 287 #endif
 288 }
 289
 290 int sd_read_data(struct rts51x_chip *chip, u8 trans_mode, u8 *cmd, int cmd_len,
 291                  u16 byte_cnt, u16 blk_cnt, u8 bus_width, u8 *buf, int buf_len,
 292                  int timeout)
 293 {
 294         struct sd_info *sd_card = &(chip->sd_card);
 295         int retval;
 296         int i;
 297
 298         sd_clr_err_code(chip);
 299
 300         if (!buf)
 301                 buf_len = 0;
 302
 303         if (buf_len > 512)
 304                 /* This function can't read data more than one page */
 305                 TRACE_RET(chip, STATUS_FAIL);
 306
 307         rts51x_init_cmd(chip);
 308
 309         if (cmd_len) {
 310                 RTS51X_DEBUGP("SD/MMC CMD %d\n", cmd[0] - 0x40);
 311                 for (i = 0; i < (cmd_len < 6 ? cmd_len : 6); i++) {
 312                         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CMD0 + i, 0xFF,
 313                                        cmd[i]);
 314                 }
 315         }
 316         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, (u8) byte_cnt);
 317         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_BYTE_CNT_H, 0xFF,
 318                        (u8) (byte_cnt >> 8));
 319         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, (u8) blk_cnt);
 320         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF,
 321                        (u8) (blk_cnt >> 8));
 322
 323         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CFG1, 0x03, bus_width);
 324
 325         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CFG2, 0xFF,
 326                        SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | SD_NO_WAIT_BUSY_END
 327                        | SD_CHECK_CRC7 | SD_RSP_LEN_6);
 328         if (trans_mode != SD_TM_AUTO_TUNING) {
 329                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,
 330                                PINGPONG_BUFFER);
 331         }
 332         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
 333                        trans_mode | SD_TRANSFER_START);
 334         rts51x_add_cmd(chip, CHECK_REG_CMD, SD_TRANSFER, SD_TRANSFER_END,
 335                        SD_TRANSFER_END);
 336
 337         retval = rts51x_send_cmd(chip, MODE_CR, 100);
 338         if (retval != STATUS_SUCCESS)
 339                 TRACE_RET(chip, retval);
 340
 341         retval = rts51x_get_rsp(chip, 1, timeout);
 342
 343         if (CHECK_SD_TRANS_FAIL(chip, retval)) {
 344                 sd_print_debug_reg(chip);
 345                 if (retval == STATUS_TIMEDOUT) {
 346                         sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
 347                                             SD_RSP_TYPE_R1, NULL, 0);
 348                 }
 349
 350                 TRACE_RET(chip, STATUS_FAIL);
 351         }
 352
 353         if (buf && buf_len) {
 354                 retval = rts51x_read_ppbuf(chip, buf, buf_len);
 355                 if (retval != STATUS_SUCCESS)
 356                         TRACE_RET(chip, retval);
 357         }
 358
 359         return STATUS_SUCCESS;
 360 }
 361
 362 static int sd_write_data(struct rts51x_chip *chip, u8 trans_mode,
 363                          u8 *cmd, int cmd_len, u16 byte_cnt, u16 blk_cnt,
 364                          u8 bus_width, u8 *buf, int buf_len, int timeout)
 365 {
 366         struct sd_info *sd_card = &(chip->sd_card);
 367         int retval;
 368         int i;
 369
 370         sd_clr_err_code(chip);
 371
 372         if (!buf)
 373                 buf_len = 0;
 374
 375         /* This function can't write data more than one page */
 376         if (buf_len > 512)
 377                 TRACE_RET(chip, STATUS_FAIL);
 378
 379         if (buf && buf_len) {
 380                 retval = rts51x_write_ppbuf(chip, buf, buf_len);
 381                 if (retval != STATUS_SUCCESS)
 382                         TRACE_RET(chip, retval);
 383         }
 384
 385         rts51x_init_cmd(chip);
 386
 387         if (cmd_len) {
 388                 RTS51X_DEBUGP("SD/MMC CMD %d\n", cmd[0] - 0x40);
 389                 for (i = 0; i < (cmd_len < 6 ? cmd_len : 6); i++) {
 390                         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CMD0 + i, 0xFF,
 391                                        cmd[i]);
 392                 }
 393         }
 394         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, (u8) byte_cnt);
 395         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_BYTE_CNT_H, 0xFF,
 396                        (u8) (byte_cnt >> 8));
 397         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, (u8) blk_cnt);
 398         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF,
 399                        (u8) (blk_cnt >> 8));
 400
 401         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CFG1, 0x03, bus_width);
 402
 403         if (cmd_len) {
 404                 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CFG2, 0xFF,
 405                                SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
 406                                SD_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_6);
 407
 408         } else {
 409                 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CFG2, 0xFF,
 410                                SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
 411                                SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 |
 412                                SD_RSP_LEN_6);
 413         }
 414
 415         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
 416                        trans_mode | SD_TRANSFER_START);
 417         rts51x_add_cmd(chip, CHECK_REG_CMD, SD_TRANSFER, SD_TRANSFER_END,
 418                        SD_TRANSFER_END);
 419
 420         retval = rts51x_send_cmd(chip, MODE_CR, 100);
 421         if (retval != STATUS_SUCCESS)
 422                 TRACE_RET(chip, retval);
 423
 424         retval = rts51x_get_rsp(chip, 1, timeout);
 425
 426         if (CHECK_SD_TRANS_FAIL(chip, retval)) {
 427                 sd_print_debug_reg(chip);
 428
 429                 if (retval == STATUS_TIMEDOUT)
 430                         sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
 431                                             SD_RSP_TYPE_R1, NULL, 0);
 432
 433                 TRACE_RET(chip, STATUS_FAIL);
 434         }
 435
 436         return STATUS_SUCCESS;
 437 }
 438
 439 static int sd_check_csd(struct rts51x_chip *chip, char check_wp)
 440 {
 441         struct sd_info *sd_card = &(chip->sd_card);
 442         int retval;
 443         int i;
 444         u8 csd_ver, trans_speed;
 445         u8 rsp[16];
 446
 447         for (i = 0; i < 6; i++) {
 448                 if (monitor_card_cd(chip, SD_CARD) == CD_NOT_EXIST) {
 449                         sd_set_reset_fail(chip, SD_RESET_FAIL);
 450                         TRACE_RET(chip, STATUS_FAIL);
 451                 }
 452
 453                 retval =
 454                     sd_send_cmd_get_rsp(chip, SEND_CSD, sd_card->sd_addr,
 455                                         SD_RSP_TYPE_R2, rsp, 16);
 456                 if (retval == STATUS_SUCCESS)
 457                         break;
 458         }
 459
 460         if (i == 6)
 461                 TRACE_RET(chip, STATUS_FAIL);
 462         memcpy(sd_card->raw_csd, rsp + 1, 15);
 463         /* Get CRC7 */
 464         RTS51X_READ_REG(chip, SD_CMD5, sd_card->raw_csd + 15);
 465
 466         RTS51X_DEBUGP("CSD Response:\n");
 467         RTS51X_DUMP(rsp, 16);
 468
 469         /* Get CSD Version */
 470         csd_ver = (rsp[1] & 0xc0) >> 6;
 471         RTS51X_DEBUGP("csd_ver = %d\n", csd_ver);
 472
 473         trans_speed = rsp[4];
 474         if ((trans_speed & 0x07) == 0x02) {     /* 10Mbits/s */
 475                 if ((trans_speed & 0xf8) >= 0x30) {     /* >25Mbits/s */
 476                         if (chip->asic_code)
 477                                 sd_card->sd_clock = 46;
 478                         else
 479                                 sd_card->sd_clock = CLK_50;
 480                 } else if ((trans_speed & 0xf8) == 0x28) { /* 20Mbits/s */
 481                         if (chip->asic_code)
 482                                 sd_card->sd_clock = 39;
 483                         else
 484                                 sd_card->sd_clock = CLK_40;
 485                 } else if ((trans_speed & 0xf8) == 0x20) { /* 15Mbits/s */
 486                         if (chip->asic_code)
 487                                 sd_card->sd_clock = 29;
 488                         else
 489                                 sd_card->sd_clock = CLK_30;
 490                 } else if ((trans_speed & 0xf8) >= 0x10) { /* 12Mbits/s */
 491                         if (chip->asic_code)
 492                                 sd_card->sd_clock = 23;
 493                         else
 494                                 sd_card->sd_clock = CLK_20;
 495                 } else if ((trans_speed & 0x08) >= 0x08) { /* 10Mbits/s */
 496                         if (chip->asic_code)
 497                                 sd_card->sd_clock = 19;
 498                         else
 499                                 sd_card->sd_clock = CLK_20;
 500                 } /*else { */
 501                         /*If this ,then slow card will use 30M clock */
 502                         /* TRACE_RET(chip, STATUS_FAIL); */
 503                 /* } */
 504         }
 505         /*else {
 506            TRACE_RET(chip, STATUS_FAIL);
 507            } */
 508         if (CHK_MMC_SECTOR_MODE(sd_card)) {
 509                 sd_card->capacity = 0;
 510         } else {
 511                 /* For High-Capacity Card, CSD_STRUCTURE always be "0x1" */
 512                 if ((!CHK_SD_HCXC(sd_card)) || (csd_ver == 0)) {
 513                         /* Calculate total sector according to C_SIZE,
 514                          * C_SIZE_MULT & READ_BL_LEN */
 515                         u8 blk_size, c_size_mult;
 516                         u16 c_size;
 517                         /* Get READ_BL_LEN */
 518                         blk_size = rsp[6] & 0x0F;
 519                         /* Get C_SIZE */
 520                         c_size = ((u16) (rsp[7] & 0x03) << 10)
 521                             + ((u16) rsp[8] << 2)
 522                             + ((u16) (rsp[9] & 0xC0) >> 6);
 523                         /* Get C_SIZE_MUL */
 524                         c_size_mult = (u8) ((rsp[10] & 0x03) << 1);
 525                         c_size_mult += (rsp[11] & 0x80) >> 7;
 526                         /* Calculate total Capacity  */
 527                         sd_card->capacity =
 528                             (((u32) (c_size + 1)) *
 529                              (1 << (c_size_mult + 2))) << (blk_size - 9);
 530                 } else {
 531                         /* High Capacity Card and Use CSD2.0 Version */
 532                         u32 total_sector = 0;
 533                         total_sector = (((u32) rsp[8] & 0x3f) << 16) |
 534                             ((u32) rsp[9] << 8) | (u32) rsp[10];
 535                         /* Total Capacity= (C_SIZE+1) *
 536                          * 512K Byte = (C_SIZE+1)K Sector,1K = 1024 Bytes */
 537                         sd_card->capacity = (total_sector + 1) << 10;
 538                 }
 539         }
 540
 541         /* We need check Write-Protected Status by Field PERM WP or TEMP WP */
 542         if (check_wp) {
 543                 if (rsp[15] & 0x30)
 544                         chip->card_wp |= SD_CARD;
 545                 RTS51X_DEBUGP("CSD WP Status: 0x%x\n", rsp[15]);
 546         }
 547
 548         return STATUS_SUCCESS;
 549 }
 550
 551 static int sd_set_sample_push_timing(struct rts51x_chip *chip)
 552 {
 553         struct sd_info *sd_card = &(chip->sd_card);
 554         int retval;
 555
 556         rts51x_init_cmd(chip);
 557
 558         if (CHK_SD_SDR104(sd_card) || CHK_SD_SDR50(sd_card)) {
 559                 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CFG1,
 560                                0x0C | SD_ASYNC_FIFO_RST,
 561                                SD_30_MODE | SD_ASYNC_FIFO_RST);
 562                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
 563                                CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
 564         } else if (CHK_SD_DDR50(sd_card) || CHK_MMC_DDR52(sd_card)) {
 565                 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CFG1,
 566                                0x0C | SD_ASYNC_FIFO_RST,
 567                                SD_DDR_MODE | SD_ASYNC_FIFO_RST);
 568                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
 569                                CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
 570                 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_PUSH_POINT_CTL,
 571                                DDR_VAR_TX_CMD_DAT, DDR_VAR_TX_CMD_DAT);
 572                 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
 573                                DDR_VAR_RX_DAT | DDR_VAR_RX_CMD,
 574                                DDR_VAR_RX_DAT | DDR_VAR_RX_CMD);
 575         } else {
 576                 u8 val = 0;
 577
 578                 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CFG1, 0x0C, SD_20_MODE);
 579                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
 580                                CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1);
 581
 582                 if ((chip->option.sd_ctl & SD_PUSH_POINT_CTL_MASK) ==
 583                     SD_PUSH_POINT_AUTO) {
 584                         val = SD20_TX_NEG_EDGE;
 585                 } else if ((chip->option.sd_ctl & SD_PUSH_POINT_CTL_MASK) ==
 586                            SD_PUSH_POINT_DELAY) {
 587                         val = SD20_TX_14_AHEAD;
 588                 } else {
 589                         val = SD20_TX_NEG_EDGE;
 590                 }
 591                 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_PUSH_POINT_CTL,
 592                                SD20_TX_SEL_MASK, val);
 593
 594                 if ((chip->option.sd_ctl & SD_SAMPLE_POINT_CTL_MASK) ==
 595                     SD_SAMPLE_POINT_AUTO) {
 596                         if (chip->asic_code) {
 597                                 if (CHK_SD_HS(sd_card) || CHK_MMC_52M(sd_card))
 598                                         val = SD20_RX_14_DELAY;
 599                                 else
 600                                         val = SD20_RX_POS_EDGE;
 601                         } else {
 602                                 val = SD20_RX_14_DELAY;
 603                         }
 604                 } else if ((chip->option.sd_ctl & SD_SAMPLE_POINT_CTL_MASK) ==
 605                            SD_SAMPLE_POINT_DELAY) {
 606                         val = SD20_RX_14_DELAY;
 607                 } else {
 608                         val = SD20_RX_POS_EDGE;
 609                 }
 610                 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
 611                                SD20_RX_SEL_MASK, val);
 612         }
 613
 614         if (CHK_MMC_DDR52(sd_card) && CHK_MMC_8BIT(sd_card)) {
 615                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_DMA1_CTL,
 616                                EXTEND_DMA1_ASYNC_SIGNAL, 0);
 617         }
 618
 619         retval = rts51x_send_cmd(chip, MODE_C, 100);
 620         if (retval != STATUS_SUCCESS)
 621                 TRACE_RET(chip, retval);
 622
 623         return STATUS_SUCCESS;
 624 }
 625
 626 static void sd_choose_proper_clock(struct rts51x_chip *chip)
 627 {
 628         struct sd_info *sd_card = &(chip->sd_card);
 629
 630         if (CHK_SD_SDR104(sd_card)) {
 631                 if (chip->asic_code)
 632                         sd_card->sd_clock = chip->option.asic_sd_sdr104_clk;
 633                 else
 634                         sd_card->sd_clock = chip->option.fpga_sd_sdr104_clk;
 635         } else if (CHK_SD_DDR50(sd_card)) {
 636                 if (chip->asic_code)
 637                         sd_card->sd_clock = chip->option.asic_sd_ddr50_clk;
 638                 else
 639                         sd_card->sd_clock = chip->option.fpga_sd_ddr50_clk;
 640         } else if (CHK_SD_SDR50(sd_card)) {
 641                 if (chip->asic_code)
 642                         sd_card->sd_clock = chip->option.asic_sd_sdr50_clk;
 643                 else
 644                         sd_card->sd_clock = chip->option.fpga_sd_sdr50_clk;
 645         } else if (CHK_SD_HS(sd_card)) {
 646                 if (chip->asic_code)
 647                         sd_card->sd_clock = chip->option.asic_sd_hs_clk;
 648                 else
 649                         sd_card->sd_clock = chip->option.fpga_sd_hs_clk;
 650         } else if (CHK_MMC_52M(sd_card) || CHK_MMC_DDR52(sd_card)) {
 651                 if (chip->asic_code)
 652                         sd_card->sd_clock = chip->option.asic_mmc_52m_clk;
 653                 else
 654                         sd_card->sd_clock = chip->option.fpga_mmc_52m_clk;
 655         } else if (CHK_MMC_26M(sd_card)) {
 656                 if (chip->asic_code) {
 657                         sd_card->sd_clock = 46;
 658                         RTS51X_DEBUGP("Set MMC clock to 22.5MHz\n");
 659                 } else {
 660                         sd_card->sd_clock = CLK_50;
 661                 }
 662         }
 663 }
 664
 665 static int sd_set_init_para(struct rts51x_chip *chip)
 666 {
 667         struct sd_info *sd_card = &(chip->sd_card);
 668         int retval;
 669
 670         retval = sd_set_sample_push_timing(chip);
 671         if (retval != STATUS_SUCCESS)
 672                 TRACE_RET(chip, retval);
 673
 674         sd_choose_proper_clock(chip);
 675
 676         retval = switch_clock(chip, sd_card->sd_clock);
 677         if (retval != STATUS_SUCCESS)
 678                 TRACE_RET(chip, retval);
 679
 680         return STATUS_SUCCESS;
 681 }
 682
 683 int rts51x_sd_select_card(struct rts51x_chip *chip, int select)
 684 {
 685         struct sd_info *sd_card = &(chip->sd_card);
 686         int retval;
 687         u8 cmd_idx, cmd_type;
 688         u32 addr;
 689
 690         if (select) {
 691                 cmd_idx = SELECT_CARD;
 692                 cmd_type = SD_RSP_TYPE_R1;
 693                 addr = sd_card->sd_addr;
 694         } else {
 695                 cmd_idx = DESELECT_CARD;
 696                 cmd_type = SD_RSP_TYPE_R0;
 697                 addr = 0;
 698         }
 699
 700         retval = sd_send_cmd_get_rsp(chip, cmd_idx, addr, cmd_type, NULL, 0);
 701         if (retval != STATUS_SUCCESS)
 702                 TRACE_RET(chip, retval);
 703
 704         return STATUS_SUCCESS;
 705 }
 706
 707 static int sd_wait_currentstate_dataready(struct rts51x_chip *chip, u8 statechk,
 708                                    u8 rdychk, u16 pollingcnt)
 709 {
 710         struct sd_info *sd_card = &(chip->sd_card);
 711         int retval;
 712         u8 rsp[5];
 713         u16 i;
 714
 715         for (i = 0; i < pollingcnt; i++) {
 716
 717                 retval =
 718                     sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
 719                                         SD_RSP_TYPE_R1, rsp, 5);
 720                 if (retval == STATUS_SUCCESS) {
 721                         if (((rsp[3] & 0x1E) == statechk)
 722                             && ((rsp[3] & 0x01) == rdychk)) {
 723                                 return STATUS_SUCCESS;
 724                         }
 725                 } else {
 726                         rts51x_clear_sd_error(chip);
 727                         TRACE_RET(chip, STATUS_FAIL);
 728                 }
 729         }
 730
 731         return STATUS_TIMEDOUT;
 732 }
 733
 734 static int sd_voltage_switch(struct rts51x_chip *chip)
 735 {
 736         int retval;
 737         u8 stat;
 738
 739         RTS51X_WRITE_REG(chip, SD_BUS_STAT,
 740                          SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP,
 741                          SD_CLK_TOGGLE_EN);
 742
 743         retval =
 744             sd_send_cmd_get_rsp(chip, VOLTAGE_SWITCH, 0, SD_RSP_TYPE_R1, NULL,
 745                                 0);
 746         if (retval != STATUS_SUCCESS)
 747                 TRACE_RET(chip, retval);
 748
 749         RTS51X_READ_REG(chip, SD_BUS_STAT, &stat);
 750         if (stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
 751                     SD_DAT1_STATUS | SD_DAT0_STATUS))
 752                 TRACE_RET(chip, STATUS_FAIL);
 753
 754         rts51x_init_cmd(chip);
 755         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_BUS_STAT, 0xFF,
 756                        SD_CLK_FORCE_STOP);
 757         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_PAD_CTL, SD_IO_USING_1V8,
 758                        SD_IO_USING_1V8);
 759         if (chip->asic_code)
 760                 rts51x_add_cmd(chip, WRITE_REG_CMD, LDO_POWER_CFG,
 761                                TUNE_SD18_MASK, TUNE_SD18_1V8);
 762         retval = rts51x_send_cmd(chip, MODE_C, 100);
 763         if (retval != STATUS_SUCCESS)
 764                 TRACE_RET(chip, retval);
 765
 766         wait_timeout(chip->option.D3318_off_delay);
 767
 768         RTS51X_WRITE_REG(chip, SD_BUS_STAT, 0xFF, SD_CLK_TOGGLE_EN);
 769         wait_timeout(10);
 770
 771         RTS51X_READ_REG(chip, SD_BUS_STAT, &stat);
 772         if ((stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
 773                      SD_DAT1_STATUS | SD_DAT0_STATUS)) !=
 774             (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
 775              SD_DAT1_STATUS | SD_DAT0_STATUS)) {
 776                 rts51x_init_cmd(chip);
 777                 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_BUS_STAT, 0xFF,
 778                                SD_CLK_FORCE_STOP);
 779                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_CLK_EN, 0xFF, 0);
 780                 rts51x_send_cmd(chip, MODE_C, 100);
 781                 TRACE_RET(chip, STATUS_FAIL);
 782         }
 783         RTS51X_WRITE_REG(chip, SD_BUS_STAT,
 784                          SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
 785
 786         return STATUS_SUCCESS;
 787 }
 788
 789 static int sd_change_phase(struct rts51x_chip *chip, u8 sample_point,
 790                            u8 tune_dir)
 791 {
 792         u16 SD_VP_CTL, SD_DCMPS_CTL;
 793         u8 val;
 794         int retval;
 795
 796         RTS51X_DEBUGP("sd_change_phase (sample_point = %d, tune_dir = %d)\n",
 797                        sample_point, tune_dir);
 798
 799         if (tune_dir == TUNE_RX) {
 800                 SD_VP_CTL = SD_VPCLK1_CTL;
 801                 SD_DCMPS_CTL = SD_DCMPS1_CTL;
 802         } else {
 803                 SD_VP_CTL = SD_VPCLK0_CTL;
 804                 SD_DCMPS_CTL = SD_DCMPS0_CTL;
 805         }
 806
 807         if (chip->asic_code) {
 808                 RTS51X_WRITE_REG(chip, CLK_DIV, CLK_CHANGE, CLK_CHANGE);
 809                 RTS51X_WRITE_REG(chip, SD_VP_CTL, 0x1F, sample_point);
 810                 RTS51X_WRITE_REG(chip, SD_VPCLK0_CTL, PHASE_NOT_RESET, 0);
 811                 RTS51X_WRITE_REG(chip, SD_VPCLK0_CTL, PHASE_NOT_RESET,
 812                                  PHASE_NOT_RESET);
 813                 RTS51X_WRITE_REG(chip, CLK_DIV, CLK_CHANGE, 0);
 814         } else {
 815 #ifdef CONFIG_RTS5139_DEBUG
 816                 RTS51X_READ_REG(chip, SD_VP_CTL, &val);
 817                 RTS51X_DEBUGP("SD_VP_CTL: 0x%x\n", val);
 818                 RTS51X_READ_REG(chip, SD_DCMPS_CTL, &val);
 819                 RTS51X_DEBUGP("SD_DCMPS_CTL: 0x%x\n", val);
 820 #endif
 821
 822                 RTS51X_WRITE_REG(chip, CLK_DIV, CLK_CHANGE, CLK_CHANGE);
 823                 udelay(100);
 824                 RTS51X_WRITE_REG(chip, SD_VP_CTL, 0xFF,
 825                                  PHASE_NOT_RESET | sample_point);
 826                 udelay(200);
 827
 828                 rts51x_init_cmd(chip);
 829                 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_DCMPS_CTL, DCMPS_CHANGE,
 830                                DCMPS_CHANGE);
 831                 rts51x_add_cmd(chip, CHECK_REG_CMD, SD_DCMPS_CTL,
 832                                DCMPS_CHANGE_DONE, DCMPS_CHANGE_DONE);
 833                 retval = rts51x_send_cmd(chip, MODE_CR, 100);
 834                 if (retval != STATUS_SUCCESS)
 835                         TRACE_GOTO(chip, Fail);
 836
 837                 retval = rts51x_get_rsp(chip, 1, 500);
 838                 if (retval != STATUS_SUCCESS)
 839                         TRACE_GOTO(chip, Fail);
 840
 841                 val = chip->rsp_buf[0];
 842                 if (val & DCMPS_ERROR)
 843                         TRACE_GOTO(chip, Fail);
 844                 if ((val & DCMPS_CURRENT_PHASE) != sample_point)
 845                         TRACE_GOTO(chip, Fail);
 846                 RTS51X_WRITE_REG(chip, SD_DCMPS_CTL, DCMPS_CHANGE, 0);
 847                 RTS51X_WRITE_REG(chip, CLK_DIV, CLK_CHANGE, 0);
 848                 udelay(100);
 849         }
 850
 851         RTS51X_WRITE_REG(chip, SD_CFG1, SD_ASYNC_FIFO_RST, 0);
 852
 853         return STATUS_SUCCESS;
 854
 855 Fail:
 856 #ifdef CONFIG_RTS5139_DEBUG
 857         rts51x_ep0_read_register(chip, SD_VP_CTL, &val);
 858         RTS51X_DEBUGP("SD_VP_CTL: 0x%x\n", val);
 859         rts51x_ep0_read_register(chip, SD_DCMPS_CTL, &val);
 860         RTS51X_DEBUGP("SD_DCMPS_CTL: 0x%x\n", val);
 861 #endif
 862
 863         RTS51X_WRITE_REG(chip, SD_DCMPS_CTL, DCMPS_CHANGE, 0);
 864         RTS51X_WRITE_REG(chip, SD_VP_CTL, PHASE_CHANGE, 0);
 865         wait_timeout(10);
 866
 867         return STATUS_FAIL;
 868 }
 869
 870 static int sd_check_spec(struct rts51x_chip *chip, u8 bus_width)
 871 {
 872         struct sd_info *sd_card = &(chip->sd_card);
 873         int retval;
 874         u8 cmd[5], buf[8];
 875
 876         retval =
 877             sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr, SD_RSP_TYPE_R1,
 878                                 NULL, 0);
 879         if (retval != STATUS_SUCCESS)
 880                 TRACE_RET(chip, STATUS_FAIL);
 881
 882         cmd[0] = 0x40 | SEND_SCR;
 883         cmd[1] = 0;
 884         cmd[2] = 0;
 885         cmd[3] = 0;
 886         cmd[4] = 0;
 887
 888         retval =
 889             sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, 8, 1, bus_width, buf,
 890                          8, 250);
 891         if (retval != STATUS_SUCCESS) {
 892                 rts51x_clear_sd_error(chip);
 893                 TRACE_RET(chip, retval);
 894         }
 895
 896         memcpy(sd_card->raw_scr, buf, 8);
 897
 898         if ((buf[0] & 0x0F) == 0)
 899                 TRACE_RET(chip, STATUS_FAIL);
 900
 901         return STATUS_SUCCESS;
 902 }
 903
 904 static int sd_query_switch_result(struct rts51x_chip *chip, u8 func_group,
 905                                   u8 func_to_switch, u8 *buf, int buf_len)
 906 {
 907         u8 support_mask = 0, query_switch = 0, switch_busy = 0;
 908         int support_offset = 0, query_switch_offset = 0, check_busy_offset = 0;
 909
 910         if (func_group == SD_FUNC_GROUP_1) {
 911                 support_offset = FUNCTION_GROUP1_SUPPORT_OFFSET;
 912                 query_switch_offset = FUNCTION_GROUP1_QUERY_SWITCH_OFFSET;
 913                 check_busy_offset = FUNCTION_GROUP1_CHECK_BUSY_OFFSET;
 914
 915                 switch (func_to_switch) {
 916                 case HS_SUPPORT:
 917                         support_mask = HS_SUPPORT_MASK;
 918                         query_switch = HS_QUERY_SWITCH_OK;
 919                         switch_busy = HS_SWITCH_BUSY;
 920                         break;
 921
 922                 case SDR50_SUPPORT:
 923                         support_mask = SDR50_SUPPORT_MASK;
 924                         query_switch = SDR50_QUERY_SWITCH_OK;
 925                         switch_busy = SDR50_SWITCH_BUSY;
 926                         break;
 927
 928                 case SDR104_SUPPORT:
 929                         support_mask = SDR104_SUPPORT_MASK;
 930                         query_switch = SDR104_QUERY_SWITCH_OK;
 931                         switch_busy = SDR104_SWITCH_BUSY;
 932                         break;
 933
 934                 case DDR50_SUPPORT:
 935                         support_mask = DDR50_SUPPORT_MASK;
 936                         query_switch = DDR50_QUERY_SWITCH_OK;
 937                         switch_busy = DDR50_SWITCH_BUSY;
 938                         break;
 939
 940                 default:
 941                         TRACE_RET(chip, STATUS_FAIL);
 942                 }
 943         } else if (func_group == SD_FUNC_GROUP_3) {
 944                 support_offset = FUNCTION_GROUP3_SUPPORT_OFFSET;
 945                 query_switch_offset = FUNCTION_GROUP3_QUERY_SWITCH_OFFSET;
 946                 check_busy_offset = FUNCTION_GROUP3_CHECK_BUSY_OFFSET;
 947
 948                 switch (func_to_switch) {
 949                 case DRIVING_TYPE_A:
 950                         support_mask = DRIVING_TYPE_A_MASK;
 951                         query_switch = TYPE_A_QUERY_SWITCH_OK;
 952                         switch_busy = TYPE_A_SWITCH_BUSY;
 953                         break;
 954
 955                 case DRIVING_TYPE_C:
 956                         support_mask = DRIVING_TYPE_C_MASK;
 957                         query_switch = TYPE_C_QUERY_SWITCH_OK;
 958                         switch_busy = TYPE_C_SWITCH_BUSY;
 959                         break;
 960
 961                 case DRIVING_TYPE_D:
 962                         support_mask = DRIVING_TYPE_D_MASK;
 963                         query_switch = TYPE_D_QUERY_SWITCH_OK;
 964                         switch_busy = TYPE_D_SWITCH_BUSY;
 965                         break;
 966
 967                 default:
 968                         TRACE_RET(chip, STATUS_FAIL);
 969                 }
 970         } else if (func_group == SD_FUNC_GROUP_4) {
 971                 support_offset = FUNCTION_GROUP4_SUPPORT_OFFSET;
 972                 query_switch_offset = FUNCTION_GROUP4_QUERY_SWITCH_OFFSET;
 973                 check_busy_offset = FUNCTION_GROUP4_CHECK_BUSY_OFFSET;
 974
 975                 switch (func_to_switch) {
 976                 case CURRENT_LIMIT_400:
 977                         support_mask = CURRENT_LIMIT_400_MASK;
 978                         query_switch = CURRENT_LIMIT_400_QUERY_SWITCH_OK;
 979                         switch_busy = CURRENT_LIMIT_400_SWITCH_BUSY;
 980                         break;
 981
 982                 case CURRENT_LIMIT_600:
 983                         support_mask = CURRENT_LIMIT_600_MASK;
 984                         query_switch = CURRENT_LIMIT_600_QUERY_SWITCH_OK;
 985                         switch_busy = CURRENT_LIMIT_600_SWITCH_BUSY;
 986                         break;
 987
 988                 case CURRENT_LIMIT_800:
 989                         support_mask = CURRENT_LIMIT_800_MASK;
 990                         query_switch = CURRENT_LIMIT_800_QUERY_SWITCH_OK;
 991                         switch_busy = CURRENT_LIMIT_800_SWITCH_BUSY;
 992                         break;
 993
 994                 default:
 995                         TRACE_RET(chip, STATUS_FAIL);
 996                 }
 997         } else {
 998                 TRACE_RET(chip, STATUS_FAIL);
 999         }
1000
1001         if (func_group == SD_FUNC_GROUP_4)
1002                 buf[query_switch_offset] =
1003                     (buf[query_switch_offset] & 0xf0) >> 4;
1004         if (!(buf[support_offset] & support_mask) ||
1005             ((buf[query_switch_offset] & 0x0F) != query_switch))
1006                 TRACE_RET(chip, STATUS_FAIL);
1007
1008         if ((buf[DATA_STRUCTURE_VER_OFFSET] == 0x01) &&
1009             ((buf[check_busy_offset] & switch_busy) == switch_busy))
1010                 TRACE_RET(chip, STATUS_FAIL);
1011
1012         return STATUS_SUCCESS;
1013 }
1014
1015 static int sd_check_switch_mode(struct rts51x_chip *chip, u8 mode,
1016                                 u8 func_group, u8 func_to_switch, u8 bus_width)
1017 {
1018         struct sd_info *sd_card = &(chip->sd_card);
1019         int retval;
1020         u8 cmd[5], buf[64];
1021
1022         RTS51X_DEBUGP("sd_check_switch_mode (mode = %d, func_group = %d,"
1023                 "func_to_switch = %d)\n", mode, func_group, func_to_switch);
1024
1025         cmd[0] = 0x40 | SWITCH;
1026         cmd[1] = mode;
1027
1028         if (func_group == SD_FUNC_GROUP_1) {
1029                 cmd[2] = 0xFF;
1030                 cmd[3] = 0xFF;
1031                 cmd[4] = 0xF0 + func_to_switch;
1032         } else if (func_group == SD_FUNC_GROUP_3) {
1033                 cmd[2] = 0xFF;
1034                 cmd[3] = 0xF0 + func_to_switch;
1035                 cmd[4] = 0xFF;
1036         } else if (func_group == SD_FUNC_GROUP_4) {
1037                 cmd[2] = 0xFF;
1038                 cmd[3] = 0x0F + (func_to_switch << 4);
1039                 cmd[4] = 0xFF;
1040         } else {
1041                 cmd[1] = SD_CHECK_MODE;
1042                 cmd[2] = 0xFF;
1043                 cmd[3] = 0xFF;
1044                 cmd[4] = 0xFF;
1045         }
1046
1047         retval =
1048             sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, 64, 1, bus_width, buf,
1049                          64, 250);
1050         if (retval != STATUS_SUCCESS) {
1051                 rts51x_clear_sd_error(chip);
1052                 TRACE_RET(chip, retval);
1053         }
1054
1055         if (func_group == NO_ARGUMENT) {
1056                 sd_card->func_group1_mask = buf[0x0D];
1057                 sd_card->func_group2_mask = buf[0x0B];
1058                 sd_card->func_group3_mask = buf[0x09];
1059                 sd_card->func_group4_mask = buf[0x07];
1060
1061                 RTS51X_DEBUGP("func_group1_mask = 0x%02x\n", buf[0x0D]);
1062                 RTS51X_DEBUGP("func_group2_mask = 0x%02x\n", buf[0x0B]);
1063                 RTS51X_DEBUGP("func_group3_mask = 0x%02x\n", buf[0x09]);
1064                 RTS51X_DEBUGP("func_group4_mask = 0x%02x\n", buf[0x07]);
1065         } else {
1066                 if ((buf[0] == 0) && (buf[1] == 0))
1067                         TRACE_RET(chip, STATUS_FAIL);
1068                 retval =
1069                     sd_query_switch_result(chip, func_group, func_to_switch,
1070                                            buf, 64);
1071                 if (retval != STATUS_SUCCESS)
1072                         TRACE_RET(chip, retval);
1073         }
1074
1075         return STATUS_SUCCESS;
1076 }
1077
1078 static int sd_check_switch(struct rts51x_chip *chip,
1079                            u8 func_group, u8 func_to_switch, u8 bus_width)
1080 {
1081         int retval;
1082         int i;
1083         int switch_good = 0;
1084
1085         for (i = 0; i < 3; i++) {
1086                 if (monitor_card_cd(chip, SD_CARD) == CD_NOT_EXIST) {
1087                         sd_set_reset_fail(chip, SD_RESET_FAIL);
1088                         TRACE_RET(chip, STATUS_FAIL);
1089                 }
1090
1091                 retval = sd_check_switch_mode(chip, SD_CHECK_MODE, func_group,
1092                                               func_to_switch, bus_width);
1093                 if (retval == STATUS_SUCCESS) {
1094                         u8 stat;
1095
1096                         retval = sd_check_switch_mode(chip, SD_SWITCH_MODE,
1097                                         func_group, func_to_switch, bus_width);
1098                         if (retval == STATUS_SUCCESS) {
1099                                 switch_good = 1;
1100                                 break;
1101                         }
1102
1103                         RTS51X_READ_REG(chip, SD_STAT1, &stat);
1104
1105                         if (stat & SD_CRC16_ERR) {
1106                                 RTS51X_DEBUGP("SD CRC16 error when switching"
1107                                                         "mode\n");
1108                                 TRACE_RET(chip, STATUS_FAIL);
1109                         }
1110                 }
1111
1112                 wait_timeout(20);
1113         }
1114
1115         if (!switch_good)
1116                 TRACE_RET(chip, STATUS_FAIL);
1117
1118         return STATUS_SUCCESS;
1119 }
1120
1121 static int sd_switch_function(struct rts51x_chip *chip, u8 bus_width)
1122 {
1123         struct sd_info *sd_card = &(chip->sd_card);
1124         int retval;
1125         int i;
1126         u8 func_to_switch = 0;
1127
1128         /* Get supported functions */
1129         retval = sd_check_switch_mode(chip, SD_CHECK_MODE,
1130                                       NO_ARGUMENT, NO_ARGUMENT, bus_width);
1131         if (retval != STATUS_SUCCESS)
1132                 TRACE_RET(chip, retval);
1133
1134         sd_card->func_group1_mask &= ~(sd_card->sd_switch_fail);
1135
1136         for (i = 0; i < 4; i++) {
1137                 switch ((u8) (chip->option.sd_speed_prior >> (i * 8))) {
1138                 case DDR50_SUPPORT:
1139                         if ((sd_card->func_group1_mask & DDR50_SUPPORT_MASK)
1140                             && (CHECK_UHS50(chip)))
1141                                 func_to_switch = DDR50_SUPPORT;
1142                         break;
1143
1144                 case SDR50_SUPPORT:
1145                         if ((sd_card->func_group1_mask & SDR50_SUPPORT_MASK)
1146                             && (CHECK_UHS50(chip)))
1147                                 func_to_switch = SDR50_SUPPORT;
1148                         break;
1149
1150                 case HS_SUPPORT:
1151                         if (sd_card->func_group1_mask & HS_SUPPORT_MASK)
1152                                 func_to_switch = HS_SUPPORT;
1153                         break;
1154
1155                 default:
1156                         continue;
1157                 }
1158
1159                 if (func_to_switch)
1160                         break;
1161         }
1162         RTS51X_DEBUGP("SD_FUNC_GROUP_1: func_to_switch = 0x%02x",
1163                        func_to_switch);
1164
1165         if (func_to_switch) {
1166                 retval =
1167                     sd_check_switch(chip, SD_FUNC_GROUP_1, func_to_switch,
1168                                     bus_width);
1169                 if (retval != STATUS_SUCCESS) {
1170                         if (func_to_switch == SDR104_SUPPORT)
1171                                 sd_card->sd_switch_fail = SDR104_SUPPORT_MASK;
1172                         else if (func_to_switch == DDR50_SUPPORT)
1173                                 sd_card->sd_switch_fail = DDR50_SUPPORT_MASK;
1174                         else if (func_to_switch == SDR50_SUPPORT)
1175                                 sd_card->sd_switch_fail = SDR50_SUPPORT_MASK;
1176                         else if (func_to_switch == HS_SUPPORT)
1177                                 sd_card->sd_switch_fail = HS_SUPPORT_MASK;
1178
1179                         TRACE_RET(chip, retval);
1180                 }
1181
1182                 if (func_to_switch == SDR104_SUPPORT)
1183                         SET_SD_SDR104(sd_card);
1184                 else if (func_to_switch == DDR50_SUPPORT)
1185                         SET_SD_DDR50(sd_card);
1186                 else if (func_to_switch == SDR50_SUPPORT)
1187                         SET_SD_SDR50(sd_card);
1188                 else
1189                         SET_SD_HS(sd_card);
1190         }
1191
1192         if (CHK_SD_DDR50(sd_card))
1193                 RTS51X_WRITE_REG(chip, SD_CFG1, 0x0C, SD_DDR_MODE);
1194
1195         func_to_switch = 0;
1196         if (sd_card->func_group4_mask & CURRENT_LIMIT_400_MASK)
1197                 func_to_switch = CURRENT_LIMIT_400;
1198
1199         if (func_to_switch) {
1200                 RTS51X_DEBUGP("Try to switch current_limit_400\n");
1201                 retval =
1202                     sd_check_switch(chip, SD_FUNC_GROUP_4, func_to_switch,
1203                                     bus_width);
1204                 RTS51X_DEBUGP("Switch current_limit_400 status: (%d)\n",
1205                                retval);
1206         }
1207
1208         return STATUS_SUCCESS;
1209 }
1210
1211 static int sd_wait_data_idle(struct rts51x_chip *chip)
1212 {
1213         int retval = STATUS_TIMEDOUT;
1214         int i;
1215         u8 val = 0;
1216
1217         for (i = 0; i < 100; i++) {
1218                 retval = rts51x_ep0_read_register(chip, SD_DATA_STATE, &val);
1219                 if (retval != STATUS_SUCCESS)
1220                         TRACE_RET(chip, STATUS_FAIL);
1221                 if (val & SD_DATA_IDLE) {
1222                         retval = STATUS_SUCCESS;
1223                         break;
1224                 }
1225                 udelay(100);
1226         }
1227         RTS51X_DEBUGP("SD_DATA_STATE: 0x%02x\n", val);
1228
1229         return retval;
1230 }
1231
1232 static int sd_sdr_tuning_rx_cmd(struct rts51x_chip *chip, u8 sample_point)
1233 {
1234         int retval;
1235         u8 cmd[5];
1236
1237         retval = sd_change_phase(chip, sample_point, TUNE_RX);
1238         if (retval != STATUS_SUCCESS)
1239                 TRACE_RET(chip, retval);
1240
1241         cmd[0] = 0x40 | SEND_TUNING_PATTERN;
1242         cmd[1] = 0;
1243         cmd[2] = 0;
1244         cmd[3] = 0;
1245         cmd[4] = 0;
1246
1247         retval = sd_read_data(chip, SD_TM_AUTO_TUNING,
1248                               cmd, 5, 0x40, 1, SD_BUS_WIDTH_4, NULL, 0, 100);
1249         if (retval != STATUS_SUCCESS) {
1250                 /* Wait till SD DATA IDLE */
1251                 (void)sd_wait_data_idle(chip);
1252
1253                 rts51x_clear_sd_error(chip);
1254                 TRACE_RET(chip, STATUS_FAIL);
1255         }
1256
1257         return STATUS_SUCCESS;
1258 }
1259
1260 static int sd_ddr_tuning_rx_cmd(struct rts51x_chip *chip, u8 sample_point)
1261 {
1262         struct sd_info *sd_card = &(chip->sd_card);
1263         int retval;
1264         u8 cmd[5];
1265
1266         retval = sd_change_phase(chip, sample_point, TUNE_RX);
1267         if (retval != STATUS_SUCCESS)
1268                 TRACE_RET(chip, retval);
1269
1270         RTS51X_DEBUGP("sd ddr tuning rx\n");
1271
1272         retval =
1273             sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr, SD_RSP_TYPE_R1,
1274                                 NULL, 0);
1275         if (retval != STATUS_SUCCESS)
1276                 TRACE_RET(chip, retval);
1277
1278         cmd[0] = 0x40 | SD_STATUS;
1279         cmd[1] = 0;
1280         cmd[2] = 0;
1281         cmd[3] = 0;
1282         cmd[4] = 0;
1283
1284         retval = sd_read_data(chip, SD_TM_NORMAL_READ,
1285                               cmd, 5, 64, 1, SD_BUS_WIDTH_4, NULL, 0, 100);
1286         if (retval != STATUS_SUCCESS) {
1287                 /* Wait till SD DATA IDLE */
1288                 (void)sd_wait_data_idle(chip);
1289
1290                 rts51x_clear_sd_error(chip);
1291                 TRACE_RET(chip, STATUS_FAIL);
1292         }
1293
1294         return STATUS_SUCCESS;
1295 }
1296
1297 static int mmc_ddr_tunning_rx_cmd(struct rts51x_chip *chip, u8 sample_point)
1298 {
1299         struct sd_info *sd_card = &(chip->sd_card);
1300         int retval;
1301         u8 cmd[5], bus_width;
1302
1303         if (CHK_MMC_8BIT(sd_card))
1304                 bus_width = SD_BUS_WIDTH_8;
1305         else if (CHK_MMC_4BIT(sd_card))
1306                 bus_width = SD_BUS_WIDTH_4;
1307         else
1308                 bus_width = SD_BUS_WIDTH_1;
1309
1310         retval = sd_change_phase(chip, sample_point, TUNE_RX);
1311         if (retval != STATUS_SUCCESS)
1312                 TRACE_RET(chip, retval);
1313
1314         RTS51X_DEBUGP("mmc ddr tuning rx\n");
1315
1316         cmd[0] = 0x40 | SEND_EXT_CSD;
1317         cmd[1] = 0;
1318         cmd[2] = 0;
1319         cmd[3] = 0;
1320         cmd[4] = 0;
1321
1322         retval = sd_read_data(chip, SD_TM_NORMAL_READ,
1323                               cmd, 5, 0x200, 1, bus_width, NULL, 0, 100);
1324         if (retval != STATUS_SUCCESS) {
1325                 /* Wait till SD DATA IDLE */
1326                 (void)sd_wait_data_idle(chip);
1327
1328                 rts51x_clear_sd_error(chip);
1329                 TRACE_RET(chip, STATUS_FAIL);
1330         }
1331
1332         return STATUS_SUCCESS;
1333 }
1334
1335 static int sd_sdr_tuning_tx_cmd(struct rts51x_chip *chip, u8 sample_point)
1336 {
1337         struct sd_info *sd_card = &(chip->sd_card);
1338         int retval;
1339
1340         retval = sd_change_phase(chip, sample_point, TUNE_TX);
1341         if (retval != STATUS_SUCCESS)
1342                 TRACE_RET(chip, retval);
1343
1344         RTS51X_WRITE_REG(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN,
1345                          SD_RSP_80CLK_TIMEOUT_EN);
1346
1347         retval = sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
1348                                      SD_RSP_TYPE_R1, NULL, 0);
1349         if (retval != STATUS_SUCCESS) {
1350                 if (sd_check_err_code(chip, SD_RSP_TIMEOUT)) {
1351                         /* Tunning TX fail */
1352                         rts51x_ep0_write_register(chip, SD_CFG3,
1353                                                   SD_RSP_80CLK_TIMEOUT_EN, 0);
1354                         TRACE_RET(chip, STATUS_FAIL);
1355                 }
1356         }
1357
1358         RTS51X_WRITE_REG(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 0);
1359
1360         return STATUS_SUCCESS;
1361 }
1362
1363 static int sd_ddr_tuning_tx_cmd(struct rts51x_chip *chip, u8 sample_point)
1364 {
1365         struct sd_info *sd_card = &(chip->sd_card);
1366         int retval;
1367         u8 cmd[5], bus_width;
1368
1369         retval = sd_change_phase(chip, sample_point, TUNE_TX);
1370         if (retval != STATUS_SUCCESS)
1371                 TRACE_RET(chip, retval);
1372
1373         if (CHK_SD(sd_card)) {
1374                 bus_width = SD_BUS_WIDTH_4;
1375         } else {
1376                 if (CHK_MMC_8BIT(sd_card))
1377                         bus_width = SD_BUS_WIDTH_8;
1378                 else if (CHK_MMC_4BIT(sd_card))
1379                         bus_width = SD_BUS_WIDTH_4;
1380                 else
1381                         bus_width = SD_BUS_WIDTH_1;
1382         }
1383         retval = sd_wait_currentstate_dataready(chip, 0x08, 1, 20);
1384         if (retval != STATUS_SUCCESS)
1385                 TRACE_RET(chip, STATUS_FAIL);
1386
1387         RTS51X_WRITE_REG(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN,
1388                          SD_RSP_80CLK_TIMEOUT_EN);
1389
1390         cmd[0] = 0x40 | PROGRAM_CSD;
1391         cmd[1] = 0;
1392         cmd[2] = 0;
1393         cmd[3] = 0;
1394         cmd[4] = 0;
1395
1396         retval = sd_write_data(chip, SD_TM_AUTO_WRITE_2,
1397                         cmd, 5, 16, 1, bus_width, sd_card->raw_csd, 16, 100);
1398         if (retval != STATUS_SUCCESS) {
1399                 rts51x_clear_sd_error(chip);
1400                 /* Tunning TX fail */
1401                 rts51x_ep0_write_register(chip, SD_CFG3,
1402                                           SD_RSP_80CLK_TIMEOUT_EN, 0);
1403                 TRACE_RET(chip, STATUS_FAIL);
1404         }
1405
1406         RTS51X_WRITE_REG(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 0);
1407
1408         sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr, SD_RSP_TYPE_R1,
1409                             NULL, 0);
1410
1411         return STATUS_SUCCESS;
1412 }
1413
1414 static u8 sd_search_final_phase(struct rts51x_chip *chip, u32 phase_map,
1415                                 u8 tune_dir)
1416 {
1417         struct sd_info *sd_card = &(chip->sd_card);
1418         struct timing_phase_path path[MAX_PHASE + 1];
1419         int i, j, cont_path_cnt;
1420         int new_block, max_len;
1421         u8 final_phase = 0xFF;
1422         int final_path_idx;
1423
1424         if (phase_map == 0xffff) {
1425                 if (CHK_SD_DDR50(sd_card)) {
1426                         if (tune_dir == TUNE_TX)
1427                                 final_phase = chip->option.ddr50_tx_phase;
1428                         else
1429                                 final_phase = chip->option.ddr50_rx_phase;
1430                         RTS51X_DEBUGP("DDR50 tuning dir:%d all pass,"
1431                                         "so select default phase:0x%x.\n",
1432                                         tune_dir, final_phase);
1433                 } else {
1434                         if (tune_dir == TUNE_TX)
1435                                 final_phase = chip->option.sdr50_tx_phase;
1436                         else
1437                                 final_phase = chip->option.sdr50_rx_phase;
1438                         RTS51X_DEBUGP("SDR50 tuning dir:%d all pass,"
1439                                         "so select default phase:0x%x.\n",
1440                                         tune_dir, final_phase);
1441                 }
1442                 goto Search_Finish;
1443         }
1444
1445         cont_path_cnt = 0;
1446         new_block = 1;
1447         j = 0;
1448         for (i = 0; i < MAX_PHASE + 1; i++) {
1449                 if (phase_map & (1 << i)) {
1450                         if (new_block) {
1451                                 new_block = 0;
1452                                 j = cont_path_cnt++;
1453                                 path[j].start = i;
1454                                 path[j].end = i;
1455                         } else {
1456                                 path[j].end = i;
1457                         }
1458                 } else {
1459                         new_block = 1;
1460                         if (cont_path_cnt) {
1461                                 int idx = cont_path_cnt - 1;
1462                                 path[idx].len =
1463                                     path[idx].end - path[idx].start + 1;
1464                                 path[idx].mid =
1465                                     path[idx].start + path[idx].len / 2;
1466                         }
1467                 }
1468         }
1469
1470         if (cont_path_cnt == 0) {
1471                 RTS51X_DEBUGP("No continuous phase path\n");
1472                 goto Search_Finish;
1473         } else {
1474                 int idx = cont_path_cnt - 1;
1475                 path[idx].len = path[idx].end - path[idx].start + 1;
1476                 path[idx].mid = path[idx].start + path[idx].len / 2;
1477         }
1478
1479         if ((path[0].start == 0) &&
1480                         (path[cont_path_cnt - 1].end == MAX_PHASE)) {
1481                 path[0].start = path[cont_path_cnt - 1].start - MAX_PHASE - 1;
1482                 path[0].len += path[cont_path_cnt - 1].len;
1483                 path[0].mid = path[0].start + path[0].len / 2;
1484                 if (path[0].mid < 0)
1485                         path[0].mid += MAX_PHASE + 1;
1486                 cont_path_cnt--;
1487         }
1488         max_len = 0;
1489         final_phase = 0;
1490         final_path_idx = 0;
1491         for (i = 0; i < cont_path_cnt; i++) {
1492                 if (path[i].len > max_len) {
1493                         max_len = path[i].len;
1494                         final_phase = (u8) path[i].mid;
1495                         final_path_idx = i;
1496                 }
1497
1498                 RTS51X_DEBUGP("path[%d].start = %d\n", i, path[i].start);
1499                 RTS51X_DEBUGP("path[%d].end = %d\n", i, path[i].end);
1500                 RTS51X_DEBUGP("path[%d].len = %d\n", i, path[i].len);
1501                 RTS51X_DEBUGP("path[%d].mid = %d\n", i, path[i].mid);
1502                 RTS51X_DEBUGP("\n");
1503         }
1504
1505         if ((tune_dir == TUNE_TX) && (CHK_SD_SDR50(sd_card))
1506             && chip->option.sdr50_phase_sel) {
1507                 if (max_len > 6) {
1508                         int temp_mid = (max_len - 6) / 2;
1509                         int temp_final_phase =
1510                             path[final_path_idx].end - (max_len -
1511                                                         (3 + temp_mid));
1512
1513                         if (temp_final_phase < 0)
1514                                 final_phase = temp_final_phase + MAX_PHASE + 1;
1515                         else
1516                                 final_phase = (u8) temp_final_phase;
1517                 }
1518         }
1519
1520 Search_Finish:
1521         RTS51X_DEBUGP("Final chosen phase: %d\n", final_phase);
1522         return final_phase;
1523 }
1524
1525 static int sd_tuning_rx(struct rts51x_chip *chip)
1526 {
1527         struct sd_info *sd_card = &(chip->sd_card);
1528         int retval;
1529         int i, j;
1530         u32 raw_phase_map[3], phase_map;
1531         u8 final_phase;
1532         int (*tuning_cmd) (struct rts51x_chip *chip, u8 sample_point);
1533
1534         if (CHK_SD(sd_card)) {
1535                 if (CHK_SD_DDR50(sd_card))
1536                         tuning_cmd = sd_ddr_tuning_rx_cmd;
1537                 else
1538                         tuning_cmd = sd_sdr_tuning_rx_cmd;
1539         } else {
1540                 if (CHK_MMC_DDR52(sd_card))
1541                         tuning_cmd = mmc_ddr_tunning_rx_cmd;
1542                 else
1543                         TRACE_RET(chip, STATUS_FAIL);
1544         }
1545
1546         for (i = 0; i < 3; i++) {
1547                 raw_phase_map[i] = 0;
1548                 for (j = MAX_PHASE; j >= 0; j--) {
1549                         if (monitor_card_cd(chip, SD_CARD) == CD_NOT_EXIST) {
1550                                 sd_set_reset_fail(chip, SD_RESET_FAIL);
1551                                 TRACE_RET(chip, STATUS_FAIL);
1552                         }
1553
1554                         retval = tuning_cmd(chip, (u8) j);
1555                         if (retval == STATUS_SUCCESS)
1556                                 raw_phase_map[i] |= 1 << j;
1557                         else
1558                                 RTS51X_DEBUGP("Tuning phase %d fail\n", j);
1559                 }
1560         }
1561
1562         phase_map = raw_phase_map[0] & raw_phase_map[1] & raw_phase_map[2];
1563         for (i = 0; i < 3; i++)
1564                 RTS51X_DEBUGP("RX raw_phase_map[%d] = 0x%04x\n", i,
1565                                raw_phase_map[i]);
1566         RTS51X_DEBUGP("RX phase_map = 0x%04x\n", phase_map);
1567
1568         final_phase = sd_search_final_phase(chip, phase_map, TUNE_RX);
1569         if (final_phase == 0xFF)
1570                 TRACE_RET(chip, STATUS_FAIL);
1571
1572         retval = tuning_cmd(chip, final_phase);
1573         if (retval != STATUS_SUCCESS)
1574                 TRACE_RET(chip, retval);
1575
1576         return STATUS_SUCCESS;
1577 }
1578
1579 static int sd_ddr_pre_tuning_tx(struct rts51x_chip *chip)
1580 {
1581         struct sd_info *sd_card = &(chip->sd_card);
1582         int retval;
1583         u8 i;
1584         u8 pre_tune_tx_phase;
1585         u32 pre_tune_phase_map;
1586
1587         RTS51X_WRITE_REG(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN,
1588                          SD_RSP_80CLK_TIMEOUT_EN);
1589
1590         pre_tune_tx_phase = 0xFF;
1591         pre_tune_phase_map = 0x0000;
1592         for (i = 0; i < MAX_PHASE + 1; i++) {
1593                 if (monitor_card_cd(chip, SD_CARD) == CD_NOT_EXIST) {
1594                         sd_set_reset_fail(chip, SD_RESET_FAIL);
1595                         TRACE_RET(chip, STATUS_FAIL);
1596                 }
1597
1598                 retval = sd_change_phase(chip, (u8) i, TUNE_TX);
1599                 if (retval != STATUS_SUCCESS)
1600                         TRACE_RET(chip, retval);
1601
1602                 retval =
1603                     sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
1604                                         SD_RSP_TYPE_R1, NULL, 0);
1605                 if ((retval == STATUS_SUCCESS)
1606                     || !sd_check_err_code(chip, SD_RSP_TIMEOUT))
1607                         pre_tune_phase_map |= (u32) 1 << i;
1608         }
1609
1610         RTS51X_WRITE_REG(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 0);
1611
1612         pre_tune_tx_phase =
1613             sd_search_final_phase(chip, pre_tune_phase_map, TUNE_TX);
1614         if (pre_tune_tx_phase == 0xFF)
1615                 TRACE_RET(chip, STATUS_FAIL);
1616
1617         sd_change_phase(chip, pre_tune_tx_phase, TUNE_TX);
1618         RTS51X_DEBUGP("DDR TX pre tune phase: %d\n", (int)pre_tune_tx_phase);
1619
1620         return STATUS_SUCCESS;
1621 }
1622
1623 static int sd_tuning_tx(struct rts51x_chip *chip)
1624 {
1625         struct sd_info *sd_card = &(chip->sd_card);
1626         int retval;
1627         int i, j;
1628         u32 raw_phase_map[3], phase_map;
1629         u8 final_phase;
1630         int (*tuning_cmd) (struct rts51x_chip *chip, u8 sample_point);
1631
1632         if (CHK_SD(sd_card)) {
1633                 if (CHK_SD_DDR50(sd_card))
1634                         tuning_cmd = sd_ddr_tuning_tx_cmd;
1635                 else
1636                         tuning_cmd = sd_sdr_tuning_tx_cmd;
1637         } else {
1638                 if (CHK_MMC_DDR52(sd_card))
1639                         tuning_cmd = sd_ddr_tuning_tx_cmd;
1640                 else
1641                         TRACE_RET(chip, STATUS_FAIL);
1642         }
1643
1644         for (i = 0; i < 3; i++) {
1645                 raw_phase_map[i] = 0;
1646                 for (j = MAX_PHASE; j >= 0; j--) {
1647                         if (monitor_card_cd(chip, SD_CARD) == CD_NOT_EXIST) {
1648                                 sd_set_reset_fail(chip, SD_RESET_FAIL);
1649                                 TRACE_RET(chip, STATUS_FAIL);
1650                         }
1651
1652                         retval = tuning_cmd(chip, (u8) j);
1653                         if (retval == STATUS_SUCCESS)
1654                                 raw_phase_map[i] |= 1 << j;
1655                         else
1656                                 RTS51X_DEBUGP("Tuning phase %d fail\n", j);
1657                 }
1658         }
1659
1660         phase_map = raw_phase_map[0] & raw_phase_map[1] & raw_phase_map[2];
1661         for (i = 0; i < 3; i++)
1662                 RTS51X_DEBUGP("TX raw_phase_map[%d] = 0x%04x\n", i,
1663                                raw_phase_map[i]);
1664         RTS51X_DEBUGP("TX phase_map = 0x%04x\n", phase_map);
1665
1666         final_phase = sd_search_final_phase(chip, phase_map, TUNE_TX);
1667         if (final_phase == 0xFF)
1668                 TRACE_RET(chip, STATUS_FAIL);
1669
1670         retval = tuning_cmd(chip, final_phase);
1671         if (retval != STATUS_SUCCESS)
1672                 TRACE_RET(chip, retval);
1673
1674         return STATUS_SUCCESS;
1675 }
1676
1677 static int sd_sdr_tuning(struct rts51x_chip *chip)
1678 {
1679         int retval;
1680
1681         retval = sd_tuning_tx(chip);
1682         if (retval != STATUS_SUCCESS)
1683                 TRACE_RET(chip, retval);
1684
1685         retval = sd_tuning_rx(chip);
1686         if (retval != STATUS_SUCCESS)
1687                 TRACE_RET(chip, retval);
1688
1689         return STATUS_SUCCESS;
1690 }
1691
1692 static int sd_ddr_tuning(struct rts51x_chip *chip)
1693 {
1694         int retval;
1695
1696         if (!(chip->option.sd_ctl & SD_DDR_TX_PHASE_SET_BY_USER)) {
1697                 retval = sd_ddr_pre_tuning_tx(chip);
1698                 if (retval != STATUS_SUCCESS)
1699                         TRACE_RET(chip, retval);
1700         } else {
1701                 retval =
1702                     sd_change_phase(chip, (u8) chip->option.sd_ddr_tx_phase,
1703                                     TUNE_TX);
1704                 if (retval != STATUS_SUCCESS)
1705                         TRACE_RET(chip, retval);
1706         }
1707
1708         retval = sd_tuning_rx(chip);
1709         if (retval != STATUS_SUCCESS)
1710                 TRACE_RET(chip, retval);
1711
1712         if (!(chip->option.sd_ctl & SD_DDR_TX_PHASE_SET_BY_USER)) {
1713                 retval = sd_tuning_tx(chip);
1714                 if (retval != STATUS_SUCCESS)
1715                         TRACE_RET(chip, retval);
1716         }
1717
1718         return STATUS_SUCCESS;
1719 }
1720
1721 static int mmc_ddr_tuning(struct rts51x_chip *chip)
1722 {
1723         int retval;
1724
1725         if (!(chip->option.sd_ctl & MMC_DDR_TX_PHASE_SET_BY_USER)) {
1726                 retval = sd_ddr_pre_tuning_tx(chip);
1727                 if (retval != STATUS_SUCCESS)
1728                         TRACE_RET(chip, retval);
1729         } else {
1730                 retval =
1731                     sd_change_phase(chip, (u8) chip->option.mmc_ddr_tx_phase,
1732                                     TUNE_TX);
1733                 if (retval != STATUS_SUCCESS)
1734                         TRACE_RET(chip, retval);
1735         }
1736
1737         retval = sd_tuning_rx(chip);
1738         if (retval != STATUS_SUCCESS)
1739                 TRACE_RET(chip, retval);
1740
1741         if (!(chip->option.sd_ctl & MMC_DDR_TX_PHASE_SET_BY_USER)) {
1742                 retval = sd_tuning_tx(chip);
1743                 if (retval != STATUS_SUCCESS)
1744                         TRACE_RET(chip, retval);
1745         }
1746
1747         return STATUS_SUCCESS;
1748 }
1749
1750 int rts51x_sd_switch_clock(struct rts51x_chip *chip)
1751 {
1752         struct sd_info *sd_card = &(chip->sd_card);
1753         int retval;
1754         int re_tuning = 0;
1755
1756         retval = rts51x_select_card(chip, SD_CARD);
1757         if (retval != STATUS_SUCCESS)
1758                 TRACE_RET(chip, retval);
1759
1760         if (CHK_SD30_SPEED(sd_card) || CHK_MMC_DDR52(sd_card)) {
1761                 if (sd_card->sd_clock != chip->cur_clk)
1762                         re_tuning = 1;
1763         }
1764
1765         retval = switch_clock(chip, sd_card->sd_clock);
1766         if (retval != STATUS_SUCCESS)
1767                 TRACE_RET(chip, retval);
1768
1769         if (re_tuning) {
1770                 if (CHK_SD(sd_card)) {
1771                         if (CHK_SD_DDR50(sd_card))
1772                                 retval = sd_ddr_tuning(chip);
1773                         else
1774                                 retval = sd_sdr_tuning(chip);
1775                 } else {
1776                         if (CHK_MMC_DDR52(sd_card))
1777                                 retval = mmc_ddr_tuning(chip);
1778                 }
1779
1780                 if (retval != STATUS_SUCCESS)
1781                         TRACE_RET(chip, retval);
1782         }
1783
1784         return STATUS_SUCCESS;
1785 }
1786
1787 static int sd_prepare_reset(struct rts51x_chip *chip)
1788 {
1789         struct sd_info *sd_card = &(chip->sd_card);
1790         int retval;
1791
1792         if (chip->asic_code)
1793                 sd_card->sd_clock = 29;
1794         else
1795                 sd_card->sd_clock = CLK_30;
1796
1797         /* Set SD Clocks */
1798         retval = sd_set_init_para(chip);
1799         if (retval != STATUS_SUCCESS)
1800                 TRACE_RET(chip, retval);
1801
1802         rts51x_init_cmd(chip);
1803
1804         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CFG1, 0xFF,
1805                        SD_CLK_DIVIDE_128 | SD_20_MODE | SD_BUS_WIDTH_1);
1806         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL, 0xFF,
1807                        SD20_RX_POS_EDGE);
1808         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_PUSH_POINT_CTL, 0xFF, 0);
1809
1810         retval = rts51x_send_cmd(chip, MODE_C, 100);
1811         if (retval != STATUS_SUCCESS)
1812                 TRACE_RET(chip, retval);
1813
1814         retval = rts51x_select_card(chip, SD_CARD);
1815         if (retval != STATUS_SUCCESS)
1816                 TRACE_RET(chip, retval);
1817
1818         return STATUS_SUCCESS;
1819 }
1820
1821 static void sd_pull_ctl_disable(struct rts51x_chip *chip)
1822 {
1823         if (CHECK_PKG(chip, LQFP48)) {
1824                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 0x55);
1825                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0x55);
1826                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 0x95);
1827                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 0x55);
1828                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF, 0x55);
1829                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF, 0xA5);
1830         } else {
1831                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 0x65);
1832                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0x55);
1833                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 0x95);
1834                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 0x55);
1835                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF, 0x56);
1836                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF, 0x59);
1837         }
1838 }
1839
1840 static void sd_pull_ctl_enable(struct rts51x_chip *chip)
1841 {
1842         if (CHECK_PKG(chip, LQFP48)) {
1843                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 0xAA);
1844                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0xAA);
1845                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 0xA9);
1846                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 0x55);
1847                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF, 0x55);
1848                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF, 0xA5);
1849         } else {
1850                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 0xA5);
1851                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0x9A);
1852                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 0xA5);
1853                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 0x9A);
1854                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF, 0x65);
1855                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF, 0x5A);
1856         }
1857 }
1858
1859 static int sd_init_power(struct rts51x_chip *chip)
1860 {
1861         int retval;
1862
1863         rts51x_init_cmd(chip);
1864
1865         rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PWR_CTL, LDO3318_PWR_MASK,
1866                        LDO_ON);
1867         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_PAD_CTL, SD_IO_USING_1V8,
1868                        SD_IO_USING_3V3);
1869         if (chip->asic_code)
1870                 rts51x_add_cmd(chip, WRITE_REG_CMD, LDO_POWER_CFG,
1871                                TUNE_SD18_MASK, TUNE_SD18_3V3);
1872         if (chip->asic_code)
1873                 sd_pull_ctl_disable(chip);
1874         else
1875                 rts51x_add_cmd(chip, WRITE_REG_CMD, FPGA_PULL_CTL,
1876                                FPGA_SD_PULL_CTL_BIT | 0x20,
1877                                FPGA_SD_PULL_CTL_BIT);
1878         rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_OE, SD_OUTPUT_EN, 0);
1879         if (!chip->option.FT2_fast_mode)
1880                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PWR_CTL, POWER_MASK,
1881                                POWER_OFF);
1882
1883         retval = rts51x_send_cmd(chip, MODE_C, 100);
1884         if (retval != STATUS_SUCCESS)
1885                 TRACE_RET(chip, retval);
1886         if (!chip->option.FT2_fast_mode) {
1887 #ifdef SD_XD_IO_FOLLOW_PWR
1888                 if (CHECK_PKG(chip, LQFP48)
1889                     || chip->option.rts5129_D3318_off_enable)
1890                         rts51x_write_register(chip, CARD_PWR_CTL,
1891                                         LDO_OFF, LDO_OFF);
1892 #endif
1893                 wait_timeout(250);
1894
1895 #ifdef SD_XD_IO_FOLLOW_PWR
1896                 if (CHECK_PKG(chip, LQFP48)
1897                     || chip->option.rts5129_D3318_off_enable) {
1898                         rts51x_init_cmd(chip);
1899                         if (chip->asic_code)
1900                                 sd_pull_ctl_enable(chip);
1901                         else
1902                                 rts51x_add_cmd(chip, WRITE_REG_CMD,
1903                                                FPGA_PULL_CTL,
1904                                                FPGA_SD_PULL_CTL_BIT | 0x20, 0);
1905                         retval = rts51x_send_cmd(chip, MODE_C, 100);
1906                         if (retval != STATUS_SUCCESS)
1907                                 TRACE_RET(chip, retval);
1908                 } else {
1909                         if (chip->asic_code)
1910                                 rts51x_write_register(chip, CARD_PULL_CTL6,
1911                                                       0x03, 0x00);
1912                 }
1913 #endif
1914
1915                 /* Power on card */
1916                 retval = rts51x_card_power_on(chip, SD_CARD);
1917                 if (retval != STATUS_SUCCESS)
1918                         TRACE_RET(chip, retval);
1919
1920                 wait_timeout(260);
1921
1922 #ifdef SUPPORT_OCP
1923                 rts51x_get_card_status(chip, &(chip->card_status));
1924                 chip->ocp_stat = (chip->card_status >> 4) & 0x03;
1925
1926                 if (chip->ocp_stat & (MS_OCP_NOW | MS_OCP_EVER)) {
1927                         RTS51X_DEBUGP("Over current, OCPSTAT is 0x%x\n",
1928                                        chip->ocp_stat);
1929                         TRACE_RET(chip, STATUS_FAIL);
1930                 }
1931 #endif
1932         }
1933
1934         rts51x_init_cmd(chip);
1935         if (chip->asic_code) {
1936                 sd_pull_ctl_enable(chip);
1937         } else {
1938                 rts51x_add_cmd(chip, WRITE_REG_CMD, FPGA_PULL_CTL,
1939                                FPGA_SD_PULL_CTL_BIT | 0x20, 0);
1940         }
1941         retval = rts51x_send_cmd(chip, MODE_C, 100);
1942         if (retval != STATUS_SUCCESS)
1943                 TRACE_RET(chip, retval);
1944 #ifdef SD_XD_IO_FOLLOW_PWR
1945         rts51x_write_register(chip, CARD_INT_PEND, XD_INT | MS_INT | SD_INT,
1946                               XD_INT | MS_INT | SD_INT);
1947 #endif
1948
1949         RTS51X_WRITE_REG(chip, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN);
1950
1951         return STATUS_SUCCESS;
1952 }
1953
1954 static int sd_dummy_clock(struct rts51x_chip *chip)
1955 {
1956         RTS51X_WRITE_REG(chip, SD_BUS_STAT, SD_CLK_TOGGLE_EN, SD_CLK_TOGGLE_EN);
1957         wait_timeout(5);
1958         RTS51X_WRITE_REG(chip, SD_BUS_STAT, SD_CLK_TOGGLE_EN, 0x00);
1959
1960         return STATUS_SUCCESS;
1961 }
1962
1963 int reset_sd(struct rts51x_chip *chip)
1964 {
1965         struct sd_info *sd_card = &(chip->sd_card);
1966         int retval, i = 0, j = 0, k = 0, hi_cap_flow = 0;
1967         int sd_dont_switch = 0;
1968         int support_1v8 = 0;
1969         u8 rsp[16];
1970         u8 switch_bus_width;
1971         u32 voltage = 0;
1972         u8 cmd[5], buf[64];
1973         u16 sd_card_type;
1974
1975         SET_SD(sd_card);
1976         CLR_RETRY_SD20_MODE(sd_card);
1977 Switch_Fail:
1978         i = 0;
1979         j = 0;
1980         k = 0;
1981         hi_cap_flow = 0;
1982         support_1v8 = 0;
1983
1984         retval = sd_prepare_reset(chip);
1985         if (retval != STATUS_SUCCESS)
1986                 TRACE_RET(chip, retval);
1987
1988         sd_dummy_clock(chip);
1989
1990         /* Start Initialization Process of SD Card */
1991 RTY_SD_RST:
1992         retval =
1993             sd_send_cmd_get_rsp(chip, GO_IDLE_STATE, 0, SD_RSP_TYPE_R0, NULL,
1994                                 0);
1995         if (retval != STATUS_SUCCESS)
1996                 TRACE_RET(chip, retval);
1997
1998         wait_timeout(20);
1999
2000         retval =
2001             sd_send_cmd_get_rsp(chip, SEND_IF_COND, 0x000001AA, SD_RSP_TYPE_R7,
2002                                 rsp, 5);
2003         if (retval == STATUS_SUCCESS) {
2004                 if ((rsp[4] == 0xAA) && ((rsp[3] & 0x0f) == 0x01)) {
2005                         hi_cap_flow = 1;
2006                         if (CHK_RETRY_SD20_MODE(sd_card)) {
2007                                 voltage =
2008                                     SUPPORT_VOLTAGE |
2009                                     SUPPORT_HIGH_AND_EXTENDED_CAPACITY;
2010                         } else {
2011                                 voltage =
2012                                     SUPPORT_VOLTAGE |
2013                                     SUPPORT_HIGH_AND_EXTENDED_CAPACITY |
2014                                     SUPPORT_MAX_POWER_PERMANCE | SUPPORT_1V8;
2015                         }
2016                 }
2017         }
2018
2019         if (!hi_cap_flow) {
2020                 voltage = SUPPORT_VOLTAGE;
2021
2022                 retval =
2023                     sd_send_cmd_get_rsp(chip, GO_IDLE_STATE, 0, SD_RSP_TYPE_R0,
2024                                         NULL, 0);
2025                 if (retval != STATUS_SUCCESS)
2026                         TRACE_RET(chip, retval);
2027                 wait_timeout(20);
2028         }
2029
2030         /* ACMD41 */
2031         do {
2032                 {
2033                         u8 temp = 0;
2034                         rts51x_read_register(chip, CARD_INT_PEND, &temp);
2035                         RTS51X_DEBUGP("CARD_INT_PEND:%x\n", temp);
2036                         if (temp & SD_INT) {
2037                                 chip->reset_need_retry = 1;
2038                                 rts51x_write_register(chip, CARD_INT_PEND,
2039                                                       XD_INT | SD_INT | MS_INT,
2040                                                       XD_INT | SD_INT | MS_INT);
2041                                 sd_set_reset_fail(chip, SD_RESET_FAIL);
2042                                 TRACE_RET(chip, STATUS_FAIL);
2043                         }
2044                 }
2045
2046 RTY_CMD55:
2047                 retval =
2048                     sd_send_cmd_get_rsp(chip, APP_CMD, 0, SD_RSP_TYPE_R1, NULL,
2049                                         0);
2050                 if (retval != STATUS_SUCCESS) {
2051                         if (monitor_card_cd(chip, SD_CARD) == CD_NOT_EXIST) {
2052                                 sd_set_reset_fail(chip, SD_RESET_FAIL);
2053                                 TRACE_RET(chip, STATUS_FAIL);
2054                         }
2055
2056                         j++;
2057                         if (chip->option.speed_mmc) {
2058                                 if (j < 2)
2059                                         goto RTY_CMD55;
2060                                 else
2061                                         TRACE_RET(chip, STATUS_FAIL);
2062                         } else {
2063                                 if (j < 3)
2064                                         goto RTY_SD_RST;
2065                                 else
2066                                         TRACE_RET(chip, STATUS_FAIL);
2067                         }
2068                 }
2069
2070                 retval =
2071                     sd_send_cmd_get_rsp(chip, SD_APP_OP_COND, voltage,
2072                                         SD_RSP_TYPE_R3, rsp, 5);
2073                 if (retval != STATUS_SUCCESS) {
2074                         k++;
2075                         if (k < 3)
2076                                 goto RTY_SD_RST;
2077                         else
2078                                 TRACE_RET(chip, STATUS_FAIL);
2079                 }
2080
2081                 i++;
2082                 wait_timeout(20);
2083         } while (!(rsp[1] & 0x80) && (i < 255)); /* Not complete power on */
2084
2085         if (i == 255) {
2086                 /* Time out */
2087                 TRACE_RET(chip, STATUS_FAIL);
2088         }
2089
2090         if (hi_cap_flow) {
2091                 if (rsp[1] & 0x40)
2092                         SET_SD_HCXC(sd_card);
2093                 else
2094                         CLR_SD_HCXC(sd_card);
2095                 if (!CHK_RETRY_SD20_MODE(sd_card)) {
2096                         if ((CHK_SD_HCXC(sd_card)) && (CHECK_UHS50(chip))) {
2097                                 support_1v8 = (rsp[1] & 0x01) ? 1 : 0;
2098                                 RTS51X_DEBUGP("support_1v8 = %d\n",
2099                                                support_1v8);
2100                         }
2101                 }
2102         } else {
2103                 CLR_SD_HCXC(sd_card);
2104                 support_1v8 = 0;
2105         }
2106
2107         /* CMD11: Switch Voltage */
2108         if (support_1v8 && CHECK_UHS50(chip)
2109             && !(((u8) chip->option.sd_speed_prior & SDR104_SUPPORT) ==
2110                  HS_SUPPORT)) {
2111                 retval = sd_voltage_switch(chip);
2112                 if (retval != STATUS_SUCCESS) {
2113                         SET_RETRY_SD20_MODE(sd_card);
2114                         sd_init_power(chip);
2115                         RTS51X_DEBUGP("1.8v switch fail\n");
2116                         goto Switch_Fail;
2117                 }
2118         }
2119
2120         /* CMD 2 */
2121         retval =
2122             sd_send_cmd_get_rsp(chip, ALL_SEND_CID, 0, SD_RSP_TYPE_R2, NULL, 0);
2123         if (retval != STATUS_SUCCESS)
2124                 TRACE_RET(chip, retval);
2125
2126         /* CMD 3 */
2127         retval =
2128             sd_send_cmd_get_rsp(chip, SEND_RELATIVE_ADDR, 0, SD_RSP_TYPE_R6,
2129                                 rsp, 5);
2130         if (retval != STATUS_SUCCESS)
2131                 TRACE_RET(chip, retval);
2132
2133         sd_card->sd_addr = (u32) rsp[1] << 24;
2134         sd_card->sd_addr += (u32) rsp[2] << 16;
2135
2136         /* Get CSD register for Calculating Timing,Capacity,
2137          * Check CSD to determine as if this is the SD ROM card */
2138         retval = sd_check_csd(chip, 1);
2139         if (retval != STATUS_SUCCESS)
2140                 TRACE_RET(chip, retval);
2141         /* Select SD card */
2142         retval = rts51x_sd_select_card(chip, 1);
2143         if (retval != STATUS_SUCCESS)
2144                 TRACE_RET(chip, retval);
2145
2146         /* ACMD42 */
2147         retval =
2148             sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr, SD_RSP_TYPE_R1,
2149                                 NULL, 0);
2150         if (retval != STATUS_SUCCESS)
2151                 TRACE_RET(chip, retval);
2152
2153         retval =
2154             sd_send_cmd_get_rsp(chip, SET_CLR_CARD_DETECT, 0, SD_RSP_TYPE_R1,
2155                                 NULL, 0);
2156         if (retval != STATUS_SUCCESS)
2157                 TRACE_RET(chip, retval);
2158
2159         if (support_1v8) {
2160                 /* ACMD6 */
2161                 retval =
2162                     sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr,
2163                                         SD_RSP_TYPE_R1, NULL, 0);
2164                 if (retval != STATUS_SUCCESS)
2165                         TRACE_RET(chip, retval);
2166                 /* Enable 4 bit data bus */
2167                 retval =
2168                     sd_send_cmd_get_rsp(chip, SET_BUS_WIDTH, 2, SD_RSP_TYPE_R1,
2169                                         NULL, 0);
2170                 if (retval != STATUS_SUCCESS)
2171                         TRACE_RET(chip, retval);
2172                 switch_bus_width = SD_BUS_WIDTH_4;
2173         } else {
2174                 switch_bus_width = SD_BUS_WIDTH_1;
2175         }
2176
2177         /* Set block length 512 bytes for all block commands */
2178         retval = sd_send_cmd_get_rsp(chip, SET_BLOCKLEN,
2179                         0x200, SD_RSP_TYPE_R1, NULL, 0);
2180         if (retval != STATUS_SUCCESS)
2181                 TRACE_RET(chip, retval);
2182
2183         RTS51X_WRITE_REG(chip, SD_CFG1, SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_0);
2184
2185         if (!(sd_card->raw_csd[4] & 0x40)) {
2186                 sd_dont_switch = 1;
2187                 RTS51X_DEBUGP("Not support class ten\n");
2188         }
2189
2190         if (!sd_dont_switch) {
2191                 /* Check the card whether flow SD1.1 spec or higher */
2192                 retval = sd_check_spec(chip, switch_bus_width);
2193                 if (retval == STATUS_SUCCESS) {
2194                         retval = sd_switch_function(chip, switch_bus_width);
2195                         if (retval != STATUS_SUCCESS) {
2196                                 if ((sd_card->sd_switch_fail ==
2197                                      SDR104_SUPPORT_MASK)
2198                                     || (sd_card->sd_switch_fail ==
2199                                         DDR50_SUPPORT_MASK)
2200                                     || (sd_card->sd_switch_fail ==
2201                                             SDR50_SUPPORT_MASK)) {
2202                                         sd_init_power(chip);
2203                                         SET_RETRY_SD20_MODE(sd_card);
2204                                 } else if (sd_card->sd_switch_fail ==
2205                                                 HS_SUPPORT_MASK) {
2206                                         sd_dont_switch = 1;
2207                                 }
2208                                 goto Switch_Fail;
2209                         }
2210                 } else {
2211                         if (support_1v8) {
2212                                 SET_RETRY_SD20_MODE(sd_card);
2213                                 sd_init_power(chip);
2214                                 sd_dont_switch = 1;
2215
2216                                 goto Switch_Fail;
2217                         }
2218                 }
2219         }
2220
2221         if (!support_1v8) {
2222                 /* ACMD6 */
2223                 retval =
2224                     sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr,
2225                                         SD_RSP_TYPE_R1, NULL, 0);
2226                 if (retval != STATUS_SUCCESS)
2227                         TRACE_RET(chip, retval);
2228                 /* Enable 4 bit data bus */
2229                 retval =
2230                     sd_send_cmd_get_rsp(chip, SET_BUS_WIDTH, 2, SD_RSP_TYPE_R1,
2231                                         NULL, 0);
2232                 if (retval != STATUS_SUCCESS)
2233                         TRACE_RET(chip, retval);
2234         }
2235
2236         if (CHK_SD30_SPEED(sd_card)) {
2237                 rts51x_write_register(chip, SD30_DRIVE_SEL, SD30_DRIVE_MASK,
2238                                       0x03);
2239
2240                 retval = sd_set_init_para(chip);
2241                 if (retval != STATUS_SUCCESS)
2242                         TRACE_RET(chip, retval);
2243
2244                 if (CHK_SD_DDR50(sd_card))
2245                         retval = sd_ddr_tuning(chip);
2246                 else
2247                         retval = sd_sdr_tuning(chip);
2248
2249                 if (retval != STATUS_SUCCESS) {
2250                         SET_RETRY_SD20_MODE(sd_card);
2251                         RTS51X_DEBUGP("tuning phase fail,goto SD20 mode\n");
2252                         sd_init_power(chip);
2253                         CLR_SD30_SPEED(sd_card);
2254                         goto Switch_Fail;
2255                 }
2256                 if (STATUS_SUCCESS ==
2257                     sd_wait_currentstate_dataready(chip, 0x08, 1, 20)) {
2258                         cmd[0] = 0x40 | READ_SINGLE_BLOCK;
2259                         cmd[1] = 0x00;
2260                         cmd[2] = 0x00;
2261                         cmd[3] = 0x00;
2262                         cmd[4] = 0x00;
2263                         retval =
2264                             sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, 512,
2265                                          1, SD_BUS_WIDTH_4, NULL, 0, 600);
2266                         if (retval != STATUS_SUCCESS) {
2267                                 SET_RETRY_SD20_MODE(sd_card);
2268                                 RTS51X_DEBUGP("read lba0 fail,"
2269                                                         "goto SD20 mode\n");
2270                                 sd_init_power(chip);
2271                                 CLR_SD30_SPEED(sd_card);
2272                                 goto Switch_Fail;
2273                         }
2274                 }
2275         }
2276         sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr, SD_RSP_TYPE_R1,
2277                             NULL, 0);
2278
2279         retval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr,
2280                         SD_RSP_TYPE_R1, NULL, 0);
2281         if (retval == STATUS_SUCCESS) {
2282                 int ret;
2283                 cmd[0] = 0x40 | SEND_STATUS;
2284                 cmd[1] = 0x00;
2285                 cmd[2] = 0x00;
2286                 cmd[3] = 0x00;
2287                 cmd[4] = 0x00;
2288                 ret =
2289                     sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, 64, 1,
2290                                  SD_BUS_WIDTH_4, buf, 64, 600);
2291                 if (ret == STATUS_SUCCESS) {
2292                         sd_card_type = ((u16) buf[2] << 8) | (u16) buf[3];
2293                         RTS51X_DEBUGP("sd_card_type:0x%4x\n", sd_card_type);
2294                         if ((sd_card_type == 0x0001)
2295                             || (sd_card_type == 0x0002))
2296                                 chip->card_wp |= SD_CARD;
2297                 } else {
2298                         rts51x_clear_sd_error(chip);
2299                         sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
2300                                             SD_RSP_TYPE_R1, NULL, 0);
2301                 }
2302         } else {
2303                 rts51x_clear_sd_error(chip);
2304                 sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
2305                                     SD_RSP_TYPE_R1, NULL, 0);
2306         }
2307
2308         /* Check SD Machanical Write-Protect Switch */
2309         retval = rts51x_get_card_status(chip, &(chip->card_status));
2310         if (retval != STATUS_SUCCESS)
2311                 TRACE_RET(chip, retval);
2312         if (chip->card_status & SD_WP)
2313                 chip->card_wp |= SD_CARD;
2314
2315         chip->card_bus_width[chip->card2lun[SD_CARD]] = 4;
2316
2317         return STATUS_SUCCESS;
2318 }
2319
2320 static int mmc_test_switch_bus(struct rts51x_chip *chip, u8 width)
2321 {
2322         struct sd_info *sd_card = &(chip->sd_card);
2323         int retval;
2324         u8 buf[8] = { 0 }, bus_width;
2325         u16 byte_cnt;
2326         int len;
2327
2328         retval =
2329             sd_send_cmd_get_rsp(chip, BUSTEST_W, 0, SD_RSP_TYPE_R1, NULL, 0);
2330         if (retval != STATUS_SUCCESS)
2331                 TRACE_RET(chip, retval);
2332
2333         if (width == MMC_8BIT_BUS) {
2334                 buf[0] = 0x55;
2335                 buf[1] = 0xAA;
2336                 len = 8;
2337                 byte_cnt = 8;
2338                 bus_width = SD_BUS_WIDTH_8;
2339         } else {
2340                 buf[0] = 0x5A;
2341                 len = 4;
2342                 byte_cnt = 4;
2343                 bus_width = SD_BUS_WIDTH_4;
2344         }
2345
2346         retval = sd_write_data(chip, SD_TM_AUTO_WRITE_3,
2347                                NULL, 0, byte_cnt, 1, bus_width, buf, len, 100);
2348         if (retval != STATUS_SUCCESS) {
2349                 u8 val1 = 0, val2 = 0;
2350                 rts51x_ep0_read_register(chip, SD_STAT1, &val1);
2351                 rts51x_ep0_read_register(chip, SD_STAT2, &val2);
2352                 rts51x_clear_sd_error(chip);
2353                 if ((val1 & 0xE0) || val2)
2354                         TRACE_RET(chip, STATUS_FAIL);
2355         }
2356         RTS51X_DEBUGP("SD/MMC CMD %d\n", BUSTEST_R);
2357
2358         rts51x_init_cmd(chip);
2359
2360         /* CMD14 */
2361         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CMD0, 0xFF, 0x40 | BUSTEST_R);
2362
2363         if (width == MMC_8BIT_BUS)
2364                 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, 0x08);
2365         else
2366                 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, 0x04);
2367
2368         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, 1);
2369         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, 0);
2370
2371         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CFG2, 0xFF,
2372                        SD_CALCULATE_CRC7 | SD_NO_CHECK_CRC16 |
2373                        SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_6);
2374         rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,
2375                        PINGPONG_BUFFER);
2376         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
2377                        SD_TM_NORMAL_READ | SD_TRANSFER_START);
2378         rts51x_add_cmd(chip, CHECK_REG_CMD, SD_TRANSFER, SD_TRANSFER_END,
2379                        SD_TRANSFER_END);
2380
2381         rts51x_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2, 0, 0);
2382         if (width == MMC_8BIT_BUS) {
2383                 len = 3;
2384                 rts51x_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 1, 0, 0);
2385         } else {
2386                 len = 2;
2387         }
2388
2389         retval = rts51x_send_cmd(chip, MODE_CR, 100);
2390         if (retval != STATUS_SUCCESS)
2391                 TRACE_RET(chip, retval);
2392
2393         retval = rts51x_get_rsp(chip, len, 100);
2394         if (CHECK_SD_TRANS_FAIL(chip, retval)) {
2395                 rts51x_clear_sd_error(chip);
2396                 TRACE_RET(chip, STATUS_FAIL);
2397         }
2398
2399         rts51x_read_rsp_buf(chip, 1, buf, 2);
2400
2401         if (width == MMC_8BIT_BUS) {
2402                 RTS51X_DEBUGP("BUSTEST_R [8bits]: 0x%02x 0x%02x\n",
2403                                         buf[0], buf[1]);
2404                 if ((buf[0] == 0xAA) && (buf[1] == 0x55)) {
2405                         u8 rsp[5];
2406                         u32 arg;
2407
2408                         if (CHK_MMC_DDR52(sd_card))
2409                                 arg = 0x03B70600;
2410                         else
2411                                 arg = 0x03B70200;
2412                         /* Switch MMC to  8-bit mode */
2413                         retval =
2414                             sd_send_cmd_get_rsp(chip, SWITCH, arg,
2415                                                 SD_RSP_TYPE_R1b, rsp, 5);
2416                         if ((retval == STATUS_SUCCESS)
2417                             && !(rsp[4] & MMC_SWITCH_ERR))
2418                                 return STATUS_SUCCESS;
2419                 }
2420         } else {
2421                 RTS51X_DEBUGP("BUSTEST_R [4bits]: 0x%02x\n", buf[0]);
2422                 if (buf[0] == 0xA5) {
2423                         u8 rsp[5];
2424                         u32 arg;
2425
2426                         if (CHK_MMC_DDR52(sd_card))
2427                                 arg = 0x03B70500;
2428                         else
2429                                 arg = 0x03B70100;
2430                         /* Switch MMC to  4-bit mode */
2431                         retval =
2432                             sd_send_cmd_get_rsp(chip, SWITCH, arg,
2433                                                 SD_RSP_TYPE_R1b, rsp, 5);
2434                         if ((retval == STATUS_SUCCESS)
2435                             && !(rsp[4] & MMC_SWITCH_ERR))
2436                                 return STATUS_SUCCESS;
2437                 }
2438         }
2439
2440         TRACE_RET(chip, STATUS_FAIL);
2441 }
2442
2443 static int mmc_switch_timing_bus(struct rts51x_chip *chip)
2444 {
2445         struct sd_info *sd_card = &(chip->sd_card);
2446         int retval;
2447         u8 card_type, card_type_mask = 0;
2448         u8 buf[6];
2449
2450         CLR_MMC_HS(sd_card);
2451
2452         RTS51X_DEBUGP("SD/MMC CMD %d\n", SEND_EXT_CSD);
2453
2454         rts51x_init_cmd(chip);
2455
2456         /* SEND_EXT_CSD command */
2457         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CMD0, 0xFF,
2458                         0x40 | SEND_EXT_CSD);
2459         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CMD1, 0xFF, 0);
2460         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CMD2, 0xFF, 0);
2461         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CMD3, 0xFF, 0);
2462         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CMD4, 0xFF, 0);
2463
2464         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, 0);
2465         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_BYTE_CNT_H, 0xFF, 2);
2466         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, 1);
2467         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, 0);
2468
2469         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CFG2, 0xFF,
2470                        SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | SD_NO_WAIT_BUSY_END
2471                        | SD_CHECK_CRC7 | SD_RSP_LEN_6);
2472         rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,
2473                        PINGPONG_BUFFER);
2474         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
2475                        SD_TM_NORMAL_READ | SD_TRANSFER_START);
2476         rts51x_add_cmd(chip, CHECK_REG_CMD, SD_TRANSFER, SD_TRANSFER_END,
2477                        SD_TRANSFER_END);
2478
2479         rts51x_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 196, 0xFF, 0);
2480         rts51x_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 212, 0xFF, 0);
2481         rts51x_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 213, 0xFF, 0);
2482         rts51x_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 214, 0xFF, 0);
2483         rts51x_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 215, 0xFF, 0);
2484
2485         retval = rts51x_send_cmd(chip, MODE_CR, 100);
2486         if (retval != STATUS_SUCCESS)
2487                 TRACE_RET(chip, retval);
2488
2489         retval = rts51x_get_rsp(chip, 6, 1000);
2490
2491         if (CHECK_SD_TRANS_FAIL(chip, retval)) {
2492                 if (retval == STATUS_TIMEDOUT) {
2493                         rts51x_clear_sd_error(chip);
2494                         sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
2495                                             SD_RSP_TYPE_R1, NULL, 0);
2496                 }
2497                 TRACE_RET(chip, STATUS_FAIL);
2498         }
2499
2500         rts51x_read_rsp_buf(chip, 0, buf, 6);
2501
2502         if (buf[0] & SD_TRANSFER_ERR) {
2503                 sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
2504                                     SD_RSP_TYPE_R1, NULL, 0);
2505                 TRACE_RET(chip, STATUS_FAIL);
2506         }
2507         if (CHK_MMC_SECTOR_MODE(sd_card))
2508                 sd_card->capacity =
2509                     ((u32) buf[5] << 24) | ((u32) buf[4] << 16) |
2510                     ((u32) buf[3] << 8) | ((u32) buf[2]);
2511         if (CHECK_UHS50(chip))
2512                 card_type_mask = 0x07;
2513         else
2514                 card_type_mask = 0x03;
2515
2516         card_type = buf[1] & card_type_mask;
2517         if (card_type) {
2518                 /* CARD TYPE FIELD = DDR52MHz, 52MHz or 26MHz */
2519                 u8 rsp[5];
2520
2521                 if (card_type & 0x04)
2522                         SET_MMC_DDR52(sd_card);
2523                 else if (card_type & 0x02)
2524                         SET_MMC_52M(sd_card);
2525                 else
2526                         SET_MMC_26M(sd_card);
2527
2528                 retval =
2529                     sd_send_cmd_get_rsp(chip, SWITCH, 0x03B90100,
2530                                         SD_RSP_TYPE_R1b, rsp, 5);
2531                 if ((retval != STATUS_SUCCESS) || (rsp[4] & MMC_SWITCH_ERR))
2532                         CLR_MMC_HS(sd_card);
2533         }
2534         sd_choose_proper_clock(chip);
2535         retval = switch_clock(chip, sd_card->sd_clock);
2536         if (retval != STATUS_SUCCESS)
2537                 TRACE_RET(chip, retval);
2538
2539         /* Test Bus Procedure */
2540         if (mmc_test_switch_bus(chip, MMC_8BIT_BUS) == STATUS_SUCCESS) {
2541                 SET_MMC_8BIT(sd_card);
2542                 chip->card_bus_width[chip->card2lun[SD_CARD]] = 8;
2543         } else if (mmc_test_switch_bus(chip, MMC_4BIT_BUS) == STATUS_SUCCESS) {
2544                 SET_MMC_4BIT(sd_card);
2545                 chip->card_bus_width[chip->card2lun[SD_CARD]] = 4;
2546         } else {
2547                 CLR_MMC_8BIT(sd_card);
2548                 CLR_MMC_4BIT(sd_card);
2549         }
2550
2551         return STATUS_SUCCESS;
2552 }
2553
2554 static int reset_mmc(struct rts51x_chip *chip)
2555 {
2556         struct sd_info *sd_card = &(chip->sd_card);
2557         int retval, i = 0, j = 0, k = 0;
2558         u8 rsp[16];
2559         u8 spec_ver = 0;
2560         u8 change_to_ddr52 = 1;
2561         u8 cmd[5];
2562
2563 MMC_DDR_FAIL:
2564
2565         retval = sd_prepare_reset(chip);
2566         if (retval != STATUS_SUCCESS)
2567                 TRACE_RET(chip, retval);
2568
2569         SET_MMC(sd_card);
2570
2571 RTY_MMC_RST:
2572         retval =
2573             sd_send_cmd_get_rsp(chip, GO_IDLE_STATE, 0, SD_RSP_TYPE_R0, NULL,
2574                                 0);
2575         if (retval != STATUS_SUCCESS)
2576                 TRACE_RET(chip, retval);
2577
2578         do {
2579                 {
2580                         u8 temp = 0;
2581                         rts51x_read_register(chip, CARD_INT_PEND, &temp);
2582                         if (temp & SD_INT) {
2583                                 chip->reset_need_retry = 1;
2584                                 rts51x_write_register(chip, CARD_INT_PEND,
2585                                                       XD_INT | SD_INT | MS_INT,
2586                                                       XD_INT | SD_INT | MS_INT);
2587                                 sd_set_reset_fail(chip, MMC_RESET_FAIL);
2588                                 TRACE_RET(chip, STATUS_FAIL);
2589                         }
2590                 }
2591
2592                 /* CMD  1 */
2593                 retval = sd_send_cmd_get_rsp(chip, SEND_OP_COND,
2594                                              (SUPPORT_VOLTAGE | 0x40000000),
2595                                              SD_RSP_TYPE_R3, rsp, 5);
2596                 if (retval != STATUS_SUCCESS) {
2597                         if (monitor_card_cd(chip, SD_CARD) == CD_NOT_EXIST) {
2598                                 sd_set_reset_fail(chip, MMC_RESET_FAIL);
2599                                 TRACE_RET(chip, STATUS_FAIL);
2600                         }
2601
2602                         if (sd_check_err_code(chip, SD_BUSY)
2603                             || sd_check_err_code(chip, SD_TO_ERR)) {
2604                                 k++;
2605                                 if (k < 20) {
2606                                         sd_clr_err_code(chip);
2607                                         goto RTY_MMC_RST;
2608                                 } else {
2609                                         TRACE_RET(chip, STATUS_FAIL);
2610                                 }
2611                         } else {
2612                                 j++;
2613                                 if (j < 100) {
2614                                         sd_clr_err_code(chip);
2615                                         goto RTY_MMC_RST;
2616                                 } else {
2617                                         TRACE_RET(chip, STATUS_FAIL);
2618                                 }
2619                         }
2620                 }
2621
2622                 wait_timeout(20);
2623                 i++;
2624         } while (!(rsp[1] & 0x80) && (i < 100)); /* Not complete power on */
2625
2626         if (i == 100) {
2627                 /* Time out */
2628                 TRACE_RET(chip, STATUS_FAIL);
2629         }
2630
2631         if ((rsp[1] & 0x60) == 0x40)
2632                 SET_MMC_SECTOR_MODE(sd_card);
2633         else
2634                 CLR_MMC_SECTOR_MODE(sd_card);
2635
2636         /* CMD 2 */
2637         retval =
2638             sd_send_cmd_get_rsp(chip, ALL_SEND_CID, 0, SD_RSP_TYPE_R2, NULL, 0);
2639         if (retval != STATUS_SUCCESS)
2640                 TRACE_RET(chip, retval);
2641
2642         /* CMD 3 */
2643         sd_card->sd_addr = 0x00100000;
2644         retval =
2645             sd_send_cmd_get_rsp(chip, SET_RELATIVE_ADDR, sd_card->sd_addr,
2646                                 SD_RSP_TYPE_R6, rsp, 5);
2647         if (retval != STATUS_SUCCESS)
2648                 TRACE_RET(chip, retval);
2649
2650         /* Get CSD register for Calculating Timing,Capacity
2651          * Check CSD to determine as if this is the SD ROM card */
2652         retval = sd_check_csd(chip, 1);
2653         if (retval != STATUS_SUCCESS)
2654                 TRACE_RET(chip, retval);
2655         /* Get MMC Spec_Ver in the CSD register */
2656         spec_ver = (sd_card->raw_csd[0] & 0x3C) >> 2;
2657
2658         /* Select MMC card */
2659         retval = rts51x_sd_select_card(chip, 1);
2660         if (retval != STATUS_SUCCESS)
2661                 TRACE_RET(chip, retval);
2662
2663         /* Set block length 512 bytes for all block commands */
2664         retval =
2665             sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, 0x200, SD_RSP_TYPE_R1, NULL,
2666                                 0);
2667         if (retval != STATUS_SUCCESS)
2668                 TRACE_RET(chip, retval);
2669
2670         RTS51X_WRITE_REG(chip, SD_CFG1, SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_0);
2671
2672         if (chip->ic_version < 2)
2673                 rts51x_write_register(chip, SD30_DRIVE_SEL, SD30_DRIVE_MASK,
2674                                       0x02);
2675         rts51x_write_register(chip, CARD_DRIVE_SEL, SD20_DRIVE_MASK, DRIVE_8mA);
2676
2677         chip->card_bus_width[chip->card2lun[SD_CARD]] = 1;
2678         if (spec_ver == 4) {
2679                 /* MMC 4.x Cards */
2680                 (void)mmc_switch_timing_bus(chip);
2681         }
2682
2683         if (CHK_MMC_SECTOR_MODE(sd_card) && (sd_card->capacity == 0))
2684                 TRACE_RET(chip, STATUS_FAIL);
2685
2686         if (CHK_MMC_DDR52(sd_card) && change_to_ddr52) {
2687                 /* Card is extracted while identifying */
2688                 if (monitor_card_cd(chip, SD_CARD) == CD_NOT_EXIST)
2689                         TRACE_RET(chip, STATUS_FAIL);
2690
2691                 retval = sd_set_init_para(chip);
2692                 if (retval != STATUS_SUCCESS) {
2693                         CLR_MMC_DDR52(sd_card);
2694                         sd_init_power(chip);
2695                         change_to_ddr52 = 0;
2696                         goto MMC_DDR_FAIL;
2697                 }
2698
2699                 retval = mmc_ddr_tuning(chip);
2700                 if (retval != STATUS_SUCCESS) {
2701                         CLR_MMC_DDR52(sd_card);
2702                         sd_init_power(chip);
2703                         change_to_ddr52 = 0;
2704                         goto MMC_DDR_FAIL;
2705                 }
2706
2707                 if (STATUS_SUCCESS ==
2708                     sd_wait_currentstate_dataready(chip, 0x08, 1, 20)) {
2709                         cmd[0] = 0x40 | READ_SINGLE_BLOCK;
2710                         cmd[1] = 0x00;
2711                         cmd[2] = 0x00;
2712                         cmd[3] = 0x00;
2713                         cmd[4] = 0x00;
2714                         if (CHK_MMC_8BIT(sd_card)) {
2715                                 retval =
2716                                     sd_read_data(chip, SD_TM_NORMAL_READ, cmd,
2717                                                  5, 512, 1, SD_BUS_WIDTH_8,
2718                                                  NULL, 0, 600);
2719                         } else if (CHK_MMC_4BIT(sd_card)) {
2720                                 retval =
2721                                     sd_read_data(chip, SD_TM_NORMAL_READ, cmd,
2722                                                  5, 512, 1, SD_BUS_WIDTH_4,
2723                                                  NULL, 0, 600);
2724                         } else {
2725                                 retval =
2726                                     sd_read_data(chip, SD_TM_NORMAL_READ, cmd,
2727                                                  5, 512, 1, SD_BUS_WIDTH_1,
2728                                                  NULL, 0, 600);
2729                         }
2730
2731                         if (retval != STATUS_SUCCESS) {
2732                                 CLR_MMC_DDR52(sd_card);
2733                                 change_to_ddr52 = 0;
2734                                 RTS51X_DEBUGP("read lba0 fail,"
2735                                                         "goto SD20 mode\n");
2736                                 sd_init_power(chip);
2737                                 goto MMC_DDR_FAIL;
2738                         }
2739                 }
2740         }
2741
2742         retval = rts51x_get_card_status(chip, &(chip->card_status));
2743         if (retval != STATUS_SUCCESS)
2744                 TRACE_RET(chip, retval);
2745         if (chip->card_status & SD_WP)
2746                 chip->card_wp |= SD_CARD;
2747
2748         return STATUS_SUCCESS;
2749 }
2750
2751 int rts51x_reset_sd_card(struct rts51x_chip *chip)
2752 {
2753         struct sd_info *sd_card = &(chip->sd_card);
2754         int retval;
2755         int i;
2756
2757         memset(sd_card, 0, sizeof(struct sd_info));
2758
2759         /* Init variables */
2760         sd_card->sd_type = 0;
2761         sd_card->seq_mode = 0;
2762         sd_card->sd_data_buf_ready = 0;
2763         sd_card->capacity = 0;
2764         sd_card->sd_switch_fail = 0;
2765
2766         sd_clear_reset_fail(chip);
2767         rts51x_enable_card_clock(chip, SD_CARD);
2768
2769         sd_init_power(chip);
2770
2771         chip->reset_need_retry = 0;
2772         for (i = 0; i < 3; i++) {
2773                 if (!chip->option.reset_mmc_first) { /* reset sd first */
2774                         retval = reset_sd(chip);
2775                         if (retval != STATUS_SUCCESS) {
2776                                 /* Switch SD bus to 3V3 signal */
2777                                 RTS51X_WRITE_REG(chip, SD_PAD_CTL,
2778                                                  SD_IO_USING_1V8, 0);
2779                                 if (sd_check_reset_fail(chip, SD_RESET_FAIL))
2780                                         sd_clear_reset_fail(chip);
2781                                 else
2782                                         retval = reset_mmc(chip);
2783                         }
2784                 } else { /* reset MMC first */
2785                         retval = reset_mmc(chip);
2786                         if (retval != STATUS_SUCCESS) {
2787                                 if (sd_check_reset_fail(chip, MMC_RESET_FAIL)) {
2788                                         sd_clear_reset_fail(chip);
2789                                 } else {
2790                                         retval = reset_sd(chip);
2791                                         if (retval != STATUS_SUCCESS) {
2792                                                 /* Switch SD bus to
2793                                                  * 3V3 signal */
2794                                                 RTS51X_WRITE_REG(chip,
2795                                                         SD_PAD_CTL,
2796                                                         SD_IO_USING_1V8, 0);
2797                                         }
2798                                 }
2799                         }
2800                 }
2801
2802                 if ((retval == STATUS_SUCCESS) || (!chip->reset_need_retry)) {
2803                         /* if reset success or don't need retry,then break */
2804                         break;
2805                 }
2806                 if (monitor_card_cd(chip, SD_CARD) == CD_NOT_EXIST) {
2807                         /* card is extracted */
2808                         break;
2809                 }
2810                 RTS51X_DEBUGP("retry reset sd card,%d\n", i);
2811                 chip->reset_need_retry = 0;
2812         }
2813
2814         sd_clear_reset_fail(chip);
2815         chip->reset_need_retry = 0;
2816
2817         if (retval == STATUS_SUCCESS) {
2818                 rts51x_init_cmd(chip);
2819                 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CFG1, SD_CLK_DIVIDE_MASK,
2820                                SD_CLK_DIVIDE_0);
2821                 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, 0);
2822                 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_BYTE_CNT_H, 0xFF, 2);
2823                 retval = rts51x_send_cmd(chip, MODE_C, 100);
2824                 if (retval != STATUS_SUCCESS)
2825                         TRACE_RET(chip, retval);
2826         } else {
2827                 chip->capacity[chip->card2lun[SD_CARD]] = sd_card->capacity = 0;
2828                 if (chip->option.reset_or_rw_fail_set_pad_drive) {
2829                         rts51x_write_register(chip, CARD_DRIVE_SEL,
2830                                               SD20_DRIVE_MASK, DRIVE_8mA);
2831                 }
2832                 TRACE_RET(chip, STATUS_FAIL);
2833         }
2834
2835         chip->capacity[chip->card2lun[SD_CARD]] = sd_card->capacity;
2836
2837         if (chip->option.sd_send_status_en) {
2838                 sd_card->sd_send_status_en = 1;
2839         } else {
2840                 if (sd_card->capacity > 0x20000) { /* 64MB */
2841                         sd_card->sd_send_status_en = 0;
2842                 } else {
2843                         sd_card->sd_send_status_en = 1;
2844                 }
2845         }
2846         RTS51X_DEBUGP("sd_card->sd_send_status = %d\n",
2847                        sd_card->sd_send_status_en);
2848
2849         retval = sd_set_init_para(chip);
2850         if (retval != STATUS_SUCCESS)
2851                 TRACE_RET(chip, retval);
2852
2853         RTS51X_DEBUGP("sd_card->sd_type = 0x%x\n", sd_card->sd_type);
2854
2855         return STATUS_SUCCESS;
2856 }
2857
2858 #define WAIT_DATA_READY_RTY_CNT         255
2859
2860 static int wait_data_buf_ready(struct rts51x_chip *chip)
2861 {
2862         struct sd_info *sd_card = &(chip->sd_card);
2863         int i, retval;
2864
2865         for (i = 0; i < WAIT_DATA_READY_RTY_CNT; i++) {
2866                 if (monitor_card_cd(chip, SD_CARD) == CD_NOT_EXIST)
2867                         TRACE_RET(chip, STATUS_FAIL);
2868
2869                 sd_card->sd_data_buf_ready = 0;
2870
2871                 retval = sd_send_cmd_get_rsp(chip, SEND_STATUS,
2872                                              sd_card->sd_addr, SD_RSP_TYPE_R1,
2873                                              NULL, 0);
2874                 if (retval != STATUS_SUCCESS)
2875                         TRACE_RET(chip, retval);
2876
2877                 if (sd_card->sd_data_buf_ready)
2878                         return sd_send_cmd_get_rsp(chip, SEND_STATUS,
2879                                                    sd_card->sd_addr,
2880                                                    SD_RSP_TYPE_R1, NULL, 0);
2881         }
2882
2883         sd_set_err_code(chip, SD_TO_ERR);
2884
2885         TRACE_RET(chip, STATUS_FAIL);
2886 }
2887
2888 static void sd_stop_seq_mode(struct rts51x_chip *chip)
2889 {
2890         struct sd_info *sd_card = &(chip->sd_card);
2891         int retval;
2892
2893         if (sd_card->seq_mode) {
2894                 retval = rts51x_sd_switch_clock(chip);
2895                 if (retval != STATUS_SUCCESS)
2896                         return;
2897
2898                 retval = sd_send_cmd_get_rsp(chip, STOP_TRANSMISSION, 0,
2899                                              SD_RSP_TYPE_R1b, NULL, 0);
2900                 if (retval != STATUS_SUCCESS)
2901                         sd_set_err_code(chip, SD_STS_ERR);
2902                 sd_card->seq_mode = 0;
2903
2904                 rts51x_ep0_write_register(chip, MC_FIFO_CTL, FIFO_FLUSH,
2905                                           FIFO_FLUSH);
2906         }
2907 }
2908
2909 static inline int sd_auto_tune_clock(struct rts51x_chip *chip)
2910 {
2911         struct sd_info *sd_card = &(chip->sd_card);
2912         int retval;
2913
2914         if (chip->asic_code) {
2915                 if (sd_card->sd_clock > 30)
2916                         sd_card->sd_clock -= 20;
2917         } else {
2918                 if (sd_card->sd_clock == CLK_100)
2919                         sd_card->sd_clock = CLK_80;
2920                 else if (sd_card->sd_clock == CLK_80)
2921                         sd_card->sd_clock = CLK_60;
2922                 else if (sd_card->sd_clock == CLK_60)
2923                         sd_card->sd_clock = CLK_50;
2924         }
2925
2926         retval = rts51x_sd_switch_clock(chip);
2927         if (retval != STATUS_SUCCESS)
2928                 TRACE_RET(chip, retval);
2929
2930         return STATUS_SUCCESS;
2931 }
2932
2933 int rts51x_sd_rw(struct scsi_cmnd *srb, struct rts51x_chip *chip, u32 start_sector,
2934           u16 sector_cnt)
2935 {
2936         struct sd_info *sd_card = &(chip->sd_card);
2937         u32 data_addr;
2938         int retval;
2939         u8 flag;
2940         unsigned int pipe;
2941         u8 stageflag;
2942
2943         sd_card->counter = 0;
2944
2945         if (!CHK_SD_HCXC(sd_card) && !CHK_MMC_SECTOR_MODE(sd_card))
2946                 data_addr = start_sector << 9;
2947         else
2948                 data_addr = start_sector;
2949
2950         RTS51X_DEBUGP("rts51x_sd_rw, data_addr = 0x%x\n", data_addr);
2951
2952         sd_clr_err_code(chip);
2953
2954         retval = rts51x_sd_switch_clock(chip);
2955         if (retval != STATUS_SUCCESS)
2956                 TRACE_RET(chip, retval);
2957
2958         if (sd_card->seq_mode && ((sd_card->pre_dir != srb->sc_data_direction)
2959                                   ||
2960                                   ((sd_card->pre_sec_addr +
2961                                     sd_card->pre_sec_cnt) != start_sector))) {
2962                 if ((sd_card->pre_dir == DMA_FROM_DEVICE)
2963                     && !CHK_SD30_SPEED(sd_card)
2964                     && !CHK_SD_HS(sd_card)
2965                     && !CHK_MMC_HS(sd_card)
2966                     && sd_card->sd_send_status_en) {
2967                         sd_send_cmd_get_rsp(chip, SEND_STATUS,
2968                                             sd_card->sd_addr, SD_RSP_TYPE_R1,
2969                                             NULL, 0);
2970                 }
2971
2972                 retval =
2973                     sd_send_cmd_get_rsp(chip, STOP_TRANSMISSION, 0,
2974                                         SD_RSP_TYPE_R1b, NULL, 0);
2975                 if (retval != STATUS_SUCCESS) {
2976                         sd_set_err_code(chip, SD_STS_ERR);
2977                         TRACE_RET(chip, sd_parse_err_code(chip));
2978                 }
2979
2980                 sd_card->seq_mode = 0;
2981
2982                 RTS51X_WRITE_REG(chip, MC_FIFO_CTL, FIFO_FLUSH, FIFO_FLUSH);
2983
2984                 if (!CHK_SD30_SPEED(sd_card)
2985                     && !CHK_SD_HS(sd_card)
2986                     && !CHK_MMC_HS(sd_card)
2987                     && sd_card->sd_send_status_en) {
2988                         /* random rw, so pre_sec_cnt < 0x80 */
2989                         sd_send_cmd_get_rsp(chip, SEND_STATUS,
2990                                             sd_card->sd_addr, SD_RSP_TYPE_R1,
2991                                             NULL, 0);
2992                 }
2993         }
2994
2995         rts51x_init_cmd(chip);
2996
2997         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, 0x00);
2998         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_BYTE_CNT_H, 0xFF, 0x02);
2999         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF,
3000                        (u8) sector_cnt);
3001         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF,
3002                        (u8) (sector_cnt >> 8));
3003
3004         rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,
3005                        RING_BUFFER);
3006
3007         if (CHK_MMC_8BIT(sd_card))
3008                 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CFG1, 0x03,
3009                                SD_BUS_WIDTH_8);
3010         else if (CHK_MMC_4BIT(sd_card) || CHK_SD(sd_card))
3011                 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CFG1, 0x03,
3012                                SD_BUS_WIDTH_4);
3013         else
3014                 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CFG1, 0x03,
3015                                SD_BUS_WIDTH_1);
3016
3017         if (sd_card->seq_mode) {
3018                 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CFG2, 0xFF,
3019                                SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16 |
3020                                SD_NO_WAIT_BUSY_END | SD_NO_CHECK_CRC7 |
3021                                SD_RSP_LEN_0);
3022
3023                 rts51x_trans_dma_enable(srb->sc_data_direction, chip, sector_cnt * 512,
3024                                  DMA_512);
3025
3026                 if (srb->sc_data_direction == DMA_FROM_DEVICE) {
3027                         flag = MODE_CDIR;
3028                         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
3029                                        SD_TM_AUTO_READ_3 | SD_TRANSFER_START);
3030                 } else {
3031                         flag = MODE_CDOR;
3032                         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
3033                                        SD_TM_AUTO_WRITE_3 | SD_TRANSFER_START);
3034                 }
3035
3036                 rts51x_add_cmd(chip, CHECK_REG_CMD, SD_TRANSFER,
3037                                SD_TRANSFER_END, SD_TRANSFER_END);
3038
3039                 retval = rts51x_send_cmd(chip, flag, 100);
3040                 if (retval != STATUS_SUCCESS)
3041                         TRACE_RET(chip, retval);
3042         } else {
3043                 if (srb->sc_data_direction == DMA_FROM_DEVICE) {
3044                         RTS51X_DEBUGP("SD/MMC CMD %d\n", READ_MULTIPLE_BLOCK);
3045                         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CMD0, 0xFF,
3046                                        0x40 | READ_MULTIPLE_BLOCK);
3047                         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CMD1, 0xFF,
3048                                        (u8) (data_addr >> 24));
3049                         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CMD2, 0xFF,
3050                                        (u8) (data_addr >> 16));
3051                         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CMD3, 0xFF,
3052                                        (u8) (data_addr >> 8));
3053                         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CMD4, 0xFF,
3054                                        (u8) data_addr);
3055
3056                         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CFG2, 0xFF,
3057                                        SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
3058                                        SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 |
3059                                        SD_RSP_LEN_6);
3060
3061                         rts51x_trans_dma_enable(srb->sc_data_direction, chip,
3062                                          sector_cnt * 512, DMA_512);
3063
3064                         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
3065                                        SD_TM_AUTO_READ_2 | SD_TRANSFER_START);
3066                         rts51x_add_cmd(chip, CHECK_REG_CMD, SD_TRANSFER,
3067                                        SD_TRANSFER_END, SD_TRANSFER_END);
3068
3069                         retval = rts51x_send_cmd(chip, MODE_CDIR, 100);
3070                         if (retval != STATUS_SUCCESS)
3071                                 TRACE_RET(chip, retval);
3072                 } else {
3073                         retval = rts51x_send_cmd(chip, MODE_C, 50);
3074                         if (retval != STATUS_SUCCESS) {
3075                                 rts51x_clear_sd_error(chip);
3076
3077                                 sd_set_err_code(chip, SD_TO_ERR);
3078                                 TRACE_RET(chip, sd_parse_err_code(chip));
3079                         }
3080
3081                         retval = wait_data_buf_ready(chip);
3082                         if (retval != STATUS_SUCCESS) {
3083                                 sd_set_err_code(chip, SD_TO_ERR);
3084                                 TRACE_RET(chip, sd_parse_err_code(chip));
3085                         }
3086
3087                         retval = sd_send_cmd_get_rsp(chip, WRITE_MULTIPLE_BLOCK,
3088                                                      data_addr, SD_RSP_TYPE_R1,
3089                                                      NULL, 0);
3090                         if (retval != STATUS_SUCCESS) {
3091                                 sd_set_err_code(chip, SD_CRC_ERR);
3092                                 TRACE_RET(chip, sd_parse_err_code(chip));
3093                         }
3094
3095                         rts51x_init_cmd(chip);
3096
3097                         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CFG2, 0xFF,
3098                                        SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16 |
3099                                        SD_NO_WAIT_BUSY_END | SD_NO_CHECK_CRC7 |
3100                                        SD_RSP_LEN_0);
3101
3102                         rts51x_trans_dma_enable(srb->sc_data_direction, chip,
3103                                          sector_cnt * 512, DMA_512);
3104
3105                         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
3106                                        SD_TM_AUTO_WRITE_3 | SD_TRANSFER_START);
3107                         rts51x_add_cmd(chip, CHECK_REG_CMD, SD_TRANSFER,
3108                                        SD_TRANSFER_END, SD_TRANSFER_END);
3109
3110                         retval = rts51x_send_cmd(chip, MODE_CDOR, 100);
3111                         if (retval != STATUS_SUCCESS)
3112                                 TRACE_RET(chip, retval);
3113                 }
3114
3115                 sd_card->seq_mode = 1;
3116         }
3117
3118         if (srb->sc_data_direction == DMA_FROM_DEVICE) {
3119                 pipe = RCV_BULK_PIPE(chip);
3120                 stageflag = STAGE_DI;
3121         } else {
3122                 pipe = SND_BULK_PIPE(chip);
3123                 stageflag = STAGE_DO;
3124         }
3125
3126         retval =
3127             rts51x_transfer_data_rcc(chip, pipe, scsi_sglist(srb),
3128                                      scsi_bufflen(srb), scsi_sg_count(srb),
3129                                      NULL, 10000, stageflag);
3130         if (retval != STATUS_SUCCESS) {
3131                 u8 stat = 0;
3132                 int err = retval;
3133
3134                 sd_print_debug_reg(chip);
3135
3136                 rts51x_ep0_read_register(chip, SD_STAT1, &stat);
3137                 RTS51X_DEBUGP("SD_STAT1: 0x%x\n", stat);
3138
3139                 rts51x_clear_sd_error(chip);
3140
3141                 retval =
3142                     sd_send_cmd_get_rsp(chip, STOP_TRANSMISSION, 0,
3143                                         SD_RSP_TYPE_R1b, NULL, 0);
3144                 if (retval != STATUS_SUCCESS) {
3145                         sd_set_err_code(chip, SD_STS_ERR);
3146                         TRACE_RET(chip, retval);
3147                 }
3148
3149                 if (stat & (SD_CRC7_ERR | SD_CRC16_ERR | SD_CRC_WRITE_ERR)) {
3150                         RTS51X_DEBUGP("SD CRC error, tune clock!\n");
3151                         sd_auto_tune_clock(chip);
3152                 }
3153
3154                 sd_card->seq_mode = 0;
3155
3156                 TRACE_RET(chip, err);
3157         }
3158         retval = rts51x_get_rsp(chip, 1, 2000);
3159         if (CHECK_SD_TRANS_FAIL(chip, retval)) {
3160                 rts51x_clear_sd_error(chip);
3161                 TRACE_RET(chip, STATUS_FAIL);
3162         }
3163
3164         sd_card->pre_sec_addr = start_sector;
3165         sd_card->pre_sec_cnt = sector_cnt;
3166         sd_card->pre_dir = srb->sc_data_direction;
3167
3168         return STATUS_SUCCESS;
3169 }
3170
3171 void rts51x_sd_cleanup_work(struct rts51x_chip *chip)
3172 {
3173         struct sd_info *sd_card = &(chip->sd_card);
3174
3175         if (sd_card->seq_mode) {
3176                 RTS51X_DEBUGP("SD: stop transmission\n");
3177                 sd_stop_seq_mode(chip);
3178                 sd_card->counter = 0;
3179         }
3180 }
3181
3182 static inline void sd_fill_power_off_card3v3(struct rts51x_chip *chip)
3183 {
3184         rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_CLK_EN, SD_CLK_EN, 0);
3185
3186         rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_OE, SD_OUTPUT_EN, 0);
3187         if (!chip->option.FT2_fast_mode) {
3188 #ifdef SD_XD_IO_FOLLOW_PWR
3189                 if (CHECK_PKG(chip, LQFP48)
3190                     || chip->option.rts5129_D3318_off_enable)
3191                         rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PWR_CTL,
3192                                        POWER_MASK | LDO_OFF,
3193                                        POWER_OFF | LDO_OFF);
3194                 else
3195                         rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PWR_CTL,
3196                                        POWER_MASK, POWER_OFF);
3197 #else
3198                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PWR_CTL, POWER_MASK,
3199                                POWER_OFF);
3200 #endif
3201         }
3202 }
3203
3204 static int sd_power_off_card3v3(struct rts51x_chip *chip)
3205 {
3206         int retval;
3207
3208         rts51x_init_cmd(chip);
3209
3210         sd_fill_power_off_card3v3(chip);
3211
3212         retval = rts51x_send_cmd(chip, MODE_C, 100);
3213         if (retval != STATUS_SUCCESS)
3214                 TRACE_RET(chip, retval);
3215 #ifdef SD_XD_IO_FOLLOW_PWR
3216         if (!chip->option.FT2_fast_mode)
3217                 wait_timeout(chip->option.D3318_off_delay);
3218 #endif
3219
3220         return STATUS_SUCCESS;
3221 }
3222
3223 int rts51x_release_sd_card(struct rts51x_chip *chip)
3224 {
3225         struct sd_info *sd_card = &(chip->sd_card);
3226         int retval;
3227
3228         RTS51X_DEBUGP("rts51x_release_sd_card\n");
3229
3230         chip->card_ready &= ~SD_CARD;
3231         chip->card_fail &= ~SD_CARD;
3232         chip->card_wp &= ~SD_CARD;
3233
3234         memset(sd_card->raw_csd, 0, 16);
3235         memset(sd_card->raw_scr, 0, 8);
3236
3237         rts51x_write_register(chip, SFSM_ED, HW_CMD_STOP, HW_CMD_STOP);
3238         rts51x_write_register(chip, SD_PAD_CTL, SD_IO_USING_1V8, 0);
3239         if (CHECK_PKG(chip, LQFP48) || chip->option.rts5129_D3318_off_enable)
3240                 sd_power_off_card3v3(chip);
3241
3242         rts51x_init_cmd(chip);
3243         if (!(CHECK_PKG(chip, LQFP48) || chip->option.rts5129_D3318_off_enable))
3244                 sd_fill_power_off_card3v3(chip);
3245
3246         if (chip->asic_code)
3247                 sd_pull_ctl_disable(chip);
3248         else
3249                 rts51x_add_cmd(chip, WRITE_REG_CMD, FPGA_PULL_CTL,
3250                                FPGA_SD_PULL_CTL_BIT | 0x20,
3251                                FPGA_SD_PULL_CTL_BIT);
3252
3253         /* Switch LDO3318 to 3.3V */
3254         rts51x_add_cmd(chip, WRITE_REG_CMD, LDO_POWER_CFG, TUNE_SD18_MASK,
3255                        TUNE_SD18_3V3);
3256
3257         if (CHK_MMC_DDR52(sd_card) && CHK_MMC_8BIT(sd_card))
3258                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_DMA1_CTL,
3259                                EXTEND_DMA1_ASYNC_SIGNAL,
3260                                EXTEND_DMA1_ASYNC_SIGNAL);
3261         if (CHK_SD30_SPEED(sd_card) || CHK_MMC(sd_card))
3262                 rts51x_add_cmd(chip, WRITE_REG_CMD, SD30_DRIVE_SEL,
3263                                SD30_DRIVE_MASK, chip->option.sd30_pad_drive);
3264         /* Suspend LDO3318 */
3265         rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PWR_CTL, LDO3318_PWR_MASK,
3266                        LDO_SUSPEND);
3267
3268         retval = rts51x_send_cmd(chip, MODE_C, 100);
3269         if (retval != STATUS_SUCCESS)
3270                 TRACE_RET(chip, retval);
3271         wait_timeout(20);
3272
3273         return STATUS_SUCCESS;
3274 }