Pileus Git - ~andy/linux/blob - drivers/staging/rts5139/rts51x_card.h

   1 /* Driver for Realtek RTS51xx USB card reader
   2  * Header file
   3  *
   4  * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License as published by the
   8  * Free Software Foundation; either version 2, or (at your option) any
   9  * later version.
  10  *
  11  * This program is distributed in the hope that it will be useful, but
  12  * WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along
  17  * with this program; if not, see <http://www.gnu.org/licenses/>.
  18  *
  19  * Author:
  20  *   wwang (wei_wang@realsil.com.cn)
  21  *   No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
  22  * Maintainer:
  23  *   Edwin Rong (edwin_rong@realsil.com.cn)
  24  *   No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
  25  */
  26
  27 #ifndef __RTS51X_CARD_H
  28 #define __RTS51X_CARD_H
  29
  30 #include "rts51x_chip.h"
  31
  32 /* Register bit definition */
  33
  34 /* Card Power Control Register */
  35 #define POWER_OFF                       0x03
  36 #define PARTIAL_POWER_ON                0x02
  37 #define POWER_ON                        0x00
  38 #define POWER_MASK                      0x03
  39 #define LDO3318_PWR_MASK                0x0C
  40 #define LDO_ON                          0x00
  41 #define LDO_SUSPEND                     0x08
  42 #define LDO_OFF                         0x0C
  43 #define DV3318_AUTO_PWR_OFF             0x10
  44 #define FORCE_LDO_POWERB        0x60
  45
  46 /* Card Output Enable Register */
  47 #define XD_OUTPUT_EN                    0x02
  48 #define SD_OUTPUT_EN                    0x04
  49 #define MS_OUTPUT_EN                    0x08
  50
  51 /* System Clock Control Register */
  52
  53 /* System Clock Divider Register */
  54 #define CLK_CHANGE                      0x80
  55 #define CLK_DIV_1                       0x00
  56 #define CLK_DIV_2                       0x01
  57 #define CLK_DIV_4                       0x02
  58 #define CLK_DIV_8                       0x03
  59
  60 /* System Clock Select Register */
  61 #define SSC_60                          0
  62 #define SSC_80                          1
  63 #define SSC_100                         2
  64 #define SSC_120                         3
  65 #define SSC_150                         4
  66
  67 /* Card Clock Enable Register */
  68 #define XD_CLK_EN                       0x02
  69 #define SD_CLK_EN                       0x04
  70 #define MS_CLK_EN                       0x08
  71
  72 /* Card Select Register */
  73 #define XD_MOD_SEL                      1
  74 #define SD_MOD_SEL                      2
  75 #define MS_MOD_SEL                      3
  76
  77 /* Card Transfer Reset Register */
  78 #define XD_STOP                         0x02
  79 #define SD_STOP                         0x04
  80 #define MS_STOP                         0x08
  81 #define XD_CLR_ERR                      0x20
  82 #define SD_CLR_ERR                      0x40
  83 #define MS_CLR_ERR                      0x80
  84
  85 /* SD30_drive_sel */
  86 #define SD30_DRIVE_MASK 0x07
  87
  88 /* CARD_DRIVE_SEL */
  89 #define SD20_DRIVE_MASK 0x03
  90 #define DRIVE_4mA                       0x00
  91 #define DRIVE_8mA                       0x01
  92 #define DRIVE_12mA                      0x02
  93
  94 /* FPGA_PULL_CTL */
  95 #define FPGA_MS_PULL_CTL_EN             0xEF
  96 #define FPGA_SD_PULL_CTL_EN             0xF7
  97 #define FPGA_XD_PULL_CTL_EN1            0xFE
  98 #define FPGA_XD_PULL_CTL_EN2            0xFD
  99 #define FPGA_XD_PULL_CTL_EN3            0xFB
 100
 101 #define FPGA_MS_PULL_CTL_BIT            0x10
 102 #define FPGA_SD_PULL_CTL_BIT            0x08
 103
 104 /* Card Data Source Register */
 105 #define PINGPONG_BUFFER                 0x01
 106 #define RING_BUFFER                     0x00
 107
 108 /* SFSM_ED */
 109 #define HW_CMD_STOP                     0x80
 110 #define CLR_STAGE_STALL                 0x08
 111 #define CARD_ERR                                0x10
 112
 113 /* CARD_SHARE_MODE */
 114 #define CARD_SHARE_LQFP48               0x04
 115 #define CARD_SHARE_QFN24                0x00
 116 #define CARD_SHARE_LQFP_SEL             0x04
 117 #define CARD_SHARE_XD                   0x00
 118 #define CARD_SHARE_SD                   0x01
 119 #define CARD_SHARE_MS                   0x02
 120 #define CARD_SHARE_MASK                 0x03
 121
 122 /* CARD_AUTO_BLINK */
 123 #define BLINK_ENABLE                    0x08
 124 #define BLINK_SPEED_MASK                0x07
 125
 126 /* CARD_GPIO */
 127 #define GPIO_OE                         0x02
 128 #define GPIO_OUTPUT                     0x01
 129
 130 /* CARD_CLK_SOURCE */
 131 #define CRC_FIX_CLK                     (0x00 << 0)
 132 #define CRC_VAR_CLK0                    (0x01 << 0)
 133 #define CRC_VAR_CLK1                    (0x02 << 0)
 134 #define SD30_FIX_CLK                    (0x00 << 2)
 135 #define SD30_VAR_CLK0                   (0x01 << 2)
 136 #define SD30_VAR_CLK1                   (0x02 << 2)
 137 #define SAMPLE_FIX_CLK                  (0x00 << 4)
 138 #define SAMPLE_VAR_CLK0                 (0x01 << 4)
 139 #define SAMPLE_VAR_CLK1                 (0x02 << 4)
 140
 141 /* DCM_DRP_CTL */
 142 #define DCM_RESET                       0x08
 143 #define DCM_LOCKED                      0x04
 144 #define DCM_208M                        0x00
 145 #define DCM_TX                          0x01
 146 #define DCM_RX                          0x02
 147
 148 /* DCM_DRP_TRIG */
 149 #define DRP_START                       0x80
 150 #define DRP_DONE                        0x40
 151
 152 /* DCM_DRP_CFG */
 153 #define DRP_WRITE                       0x80
 154 #define DRP_READ                        0x00
 155 #define DCM_WRITE_ADDRESS_50            0x50
 156 #define DCM_WRITE_ADDRESS_51            0x51
 157 #define DCM_READ_ADDRESS_00             0x00
 158 #define DCM_READ_ADDRESS_51             0x51
 159
 160 /* HW_VERSION */
 161 #define FPGA_VER                        0x80
 162 #define HW_VER_MASK                     0x0F
 163
 164 /* CD_DEGLITCH_EN */
 165 #define DISABLE_SD_CD                   0x08
 166 #define DISABLE_MS_CD                   0x10
 167 #define DISABLE_XD_CD                   0x20
 168 #define SD_CD_DEGLITCH_EN               0x01
 169 #define MS_CD_DEGLITCH_EN               0x02
 170 #define XD_CD_DEGLITCH_EN               0x04
 171
 172 /* OCPCTL */
 173 #define CARD_OC_DETECT_EN               0x08
 174 #define CARD_OC_CLR                     0x01
 175
 176 /* CARD_DMA1_CTL */
 177 #define EXTEND_DMA1_ASYNC_SIGNAL        0x02
 178
 179 /* HS_USB_STAT */
 180 #define USB_HI_SPEED                    0x01
 181
 182 /* CFG_MODE_1 */
 183 #define RTS5179                         0x02
 184
 185 /* SYS_DUMMY0 */
 186 #define NYET_EN                         0x01
 187 #define NYET_MSAK                       0x01
 188
 189 /* SSC_CTL1 */
 190 #define SSC_RSTB                        0x80
 191 #define SSC_8X_EN                       0x40
 192 #define SSC_FIX_FRAC                    0x20
 193 #define SSC_SEL_1M                      0x00
 194 #define SSC_SEL_2M                      0x08
 195 #define SSC_SEL_4M                      0x10
 196 #define SSC_SEL_8M                      0x18
 197
 198 /* SSC_CTL2 */
 199 #define SSC_DEPTH_MASK                  0x03
 200 #define SSC_DEPTH_DISALBE               0x00
 201 #define SSC_DEPTH_2M                    0x01
 202 #define SSC_DEPTH_1M                    0x02
 203 #define SSC_DEPTH_512K                  0x03
 204
 205 /* LDO_POWER_CFG */
 206 #define TUNE_SD18_MASK                  0x1C
 207 #define TUNE_SD18_1V7                   0x00
 208 #define TUNE_SD18_1V8                   (0x01 << 2)
 209 #define TUNE_SD18_1V9                   (0x02 << 2)
 210 #define TUNE_SD18_2V0                   (0x03 << 2)
 211 #define TUNE_SD18_2V7                   (0x04 << 2)
 212 #define TUNE_SD18_2V8                   (0x05 << 2)
 213 #define TUNE_SD18_2V9                   (0x06 << 2)
 214 #define TUNE_SD18_3V3                   (0x07 << 2)
 215
 216 /* XD_CP_WAITTIME */
 217 #define WAIT_1F                         0x00
 218 #define WAIT_3F                         0x01
 219 #define WAIT_7F                         0x02
 220 #define WAIT_FF                         0x03
 221
 222 /* XD_INIT */
 223 #define XD_PWR_OFF_DELAY0               0x00
 224 #define XD_PWR_OFF_DELAY1               0x02
 225 #define XD_PWR_OFF_DELAY2               0x04
 226 #define XD_PWR_OFF_DELAY3               0x06
 227 #define XD_AUTO_PWR_OFF_EN              0xF7
 228 #define XD_NO_AUTO_PWR_OFF              0x08
 229
 230 /* XD_DTCTL */
 231 /* XD_CATCTL */
 232 #define XD_TIME_RWN_1                   0x00
 233 #define XD_TIME_RWN_STEP                0x20
 234 #define XD_TIME_RW_1                    0x00
 235 #define XD_TIME_RW_STEP                 0x04
 236 #define XD_TIME_SETUP_1                 0x00
 237 #define XD_TIME_SETUP_STEP              0x01
 238
 239 /* XD_CTL */
 240 #define XD_ECC2_UNCORRECTABLE           0x80
 241 #define XD_ECC2_ERROR                   0x40
 242 #define XD_ECC1_UNCORRECTABLE           0x20
 243 #define XD_ECC1_ERROR                   0x10
 244 #define XD_RDY                          0x04
 245 #define XD_CE_EN                        0xFD
 246 #define XD_CE_DISEN                     0x02
 247 #define XD_WP_EN                        0xFE
 248 #define XD_WP_DISEN                     0x01
 249
 250 /* XD_TRANSFER */
 251 #define XD_TRANSFER_START               0x80
 252 #define XD_TRANSFER_END                 0x40
 253 #define XD_PPB_EMPTY                    0x20
 254 #define XD_ERR                          0x10
 255 #define XD_RESET                        0x00
 256 #define XD_ERASE                        0x01
 257 #define XD_READ_STATUS                  0x02
 258 #define XD_READ_ID                      0x03
 259 #define XD_READ_REDUNDANT               0x04
 260 #define XD_READ_PAGES                   0x05
 261 #define XD_SET_CMD                      0x06
 262 #define XD_NORMAL_READ                  0x07
 263 #define XD_WRITE_PAGES                  0x08
 264 #define XD_NORMAL_WRITE                 0x09
 265 #define XD_WRITE_REDUNDANT              0x0A
 266 #define XD_SET_ADDR                     0x0B
 267 #define XD_COPY_PAGES                   0x0C
 268
 269 /* XD_CFG */
 270 #define XD_PPB_TO_SIE                   0x80
 271 #define XD_TO_PPB_ONLY                  0x00
 272 #define XD_BA_TRANSFORM                 0x40
 273 #define XD_BA_NO_TRANSFORM              0x00
 274 #define XD_NO_CALC_ECC                  0x20
 275 #define XD_CALC_ECC                     0x00
 276 #define XD_IGNORE_ECC                   0x10
 277 #define XD_CHECK_ECC                    0x00
 278 #define XD_DIRECT_TO_RB                 0x08
 279 #define XD_ADDR_MASK                    0x07
 280 #define XD_ADDR_LENGTH_0                0x00
 281 #define XD_ADDR_LENGTH_1                0x01
 282 #define XD_ADDR_LENGTH_2                0x02
 283 #define XD_ADDR_LENGTH_3                0x03
 284 #define XD_ADDR_LENGTH_4                0x04
 285
 286 /* XD_PAGE_STATUS */
 287 #define XD_GPG                          0xFF
 288 #define XD_BPG                          0x00
 289
 290 /* XD_BLOCK_STATUS */
 291 #define XD_GBLK                         0xFF
 292 #define XD_LATER_BBLK                   0xF0
 293
 294 /* XD_PARITY */
 295 #define XD_ECC2_ALL1                    0x80
 296 #define XD_ECC1_ALL1                    0x40
 297 #define XD_BA2_ALL0                     0x20
 298 #define XD_BA1_ALL0                     0x10
 299 #define XD_BA1_BA2_EQL                  0x04
 300 #define XD_BA2_VALID                    0x02
 301 #define XD_BA1_VALID                    0x01
 302
 303 /* XD_CHK_DATA_STATUS */
 304 #define XD_PGSTS_ZEROBIT_OVER4          0x00
 305 #define XD_PGSTS_NOT_FF                 0x02
 306 #define XD_AUTO_CHK_DATA_STATUS         0x01
 307
 308 /* SD_CFG1 */
 309 #define SD_CLK_DIVIDE_0                 0x00
 310 #define SD_CLK_DIVIDE_256               0xC0
 311 #define SD_CLK_DIVIDE_128               0x80
 312 #define SD_CLK_DIVIDE_MASK              0xC0
 313 #define SD_BUS_WIDTH_1                  0x00
 314 #define SD_BUS_WIDTH_4                  0x01
 315 #define SD_BUS_WIDTH_8                  0x02
 316 #define SD_ASYNC_FIFO_RST               0x10
 317 #define SD_20_MODE                      0x00
 318 #define SD_DDR_MODE                     0x04
 319 #define SD_30_MODE                      0x08
 320
 321 /* SD_CFG2 */
 322 #define SD_CALCULATE_CRC7               0x00
 323 #define SD_NO_CALCULATE_CRC7            0x80
 324 #define SD_CHECK_CRC16                  0x00
 325 #define SD_NO_CHECK_CRC16               0x40
 326 #define SD_WAIT_CRC_TO_EN               0x20
 327 #define SD_WAIT_BUSY_END                0x08
 328 #define SD_NO_WAIT_BUSY_END             0x00
 329 #define SD_CHECK_CRC7                   0x00
 330 #define SD_NO_CHECK_CRC7                0x04
 331 #define SD_RSP_LEN_0                    0x00
 332 #define SD_RSP_LEN_6                    0x01
 333 #define SD_RSP_LEN_17                   0x02
 334 /* SD/MMC Response Type Definition */
 335 /* SD_CALCULATE_CRC7, SD_CHECK_CRC16,
 336  * SD_NO_WAIT_BUSY_END, SD_NO_CHECK_CRC7,
 337  * SD_RSP_LEN_0 */
 338 #define SD_RSP_TYPE_R0                  0x04
 339 /* SD_CALCULATE_CRC7, SD_CHECK_CRC16,
 340  * SD_NO_WAIT_BUSY_END, SD_CHECK_CRC7,
 341  * SD_RSP_LEN_6 */
 342 #define SD_RSP_TYPE_R1                  0x01
 343 /* SD_CALCULATE_CRC7, SD_CHECK_CRC16,
 344  * SD_WAIT_BUSY_END, SD_CHECK_CRC7,
 345  * SD_RSP_LEN_6 */
 346 #define SD_RSP_TYPE_R1b                 0x09
 347 /* SD_CALCULATE_CRC7, SD_CHECK_CRC16,
 348  * SD_NO_WAIT_BUSY_END, SD_CHECK_CRC7,
 349  * SD_RSP_LEN_17 */
 350 #define SD_RSP_TYPE_R2                  0x02
 351 /* SD_CALCULATE_CRC7, SD_CHECK_CRC16,
 352  * SD_NO_WAIT_BUSY_END, SD_NO_CHECK_CRC7,
 353  * SD_RSP_LEN_6 */
 354 #define SD_RSP_TYPE_R3                  0x05
 355 /* SD_CALCULATE_CRC7, SD_CHECK_CRC16,
 356  * SD_NO_WAIT_BUSY_END, SD_NO_CHECK_CRC7,
 357  * SD_RSP_LEN_6 */
 358 #define SD_RSP_TYPE_R4                  0x05
 359 /* SD_CALCULATE_CRC7, SD_CHECK_CRC16,
 360  * SD_NO_WAIT_BUSY_END, SD_CHECK_CRC7,
 361  * SD_RSP_LEN_6 */
 362 #define SD_RSP_TYPE_R5                  0x01
 363 /* SD_CALCULATE_CRC7, SD_CHECK_CRC16,
 364  * SD_NO_WAIT_BUSY_END, SD_CHECK_CRC7,
 365  * SD_RSP_LEN_6 */
 366 #define SD_RSP_TYPE_R6                  0x01
 367 /* SD_CALCULATE_CRC7, SD_CHECK_CRC16,
 368  * SD_NO_WAIT_BUSY_END, SD_CHECK_CRC7,
 369  * SD_RSP_LEN_6  */
 370 #define SD_RSP_TYPE_R7                  0x01
 371
 372 /* SD_CFG3 */
 373 #define SD_RSP_80CLK_TIMEOUT_EN         0x01
 374
 375 /* SD_STAT1 */
 376 #define SD_CRC7_ERR                     0x80
 377 #define SD_CRC16_ERR                    0x40
 378 #define SD_CRC_WRITE_ERR                0x20
 379 #define SD_CRC_WRITE_ERR_MASK           0x1C
 380 #define GET_CRC_TIME_OUT                0x02
 381 #define SD_TUNING_COMPARE_ERR           0x01
 382
 383 /* SD_STAT2 */
 384 #define SD_RSP_80CLK_TIMEOUT            0x01
 385
 386 /* SD_BUS_STAT */
 387 #define SD_CLK_TOGGLE_EN                0x80
 388 #define SD_CLK_FORCE_STOP               0x40
 389 #define SD_DAT3_STATUS                  0x10
 390 #define SD_DAT2_STATUS                  0x08
 391 #define SD_DAT1_STATUS                  0x04
 392 #define SD_DAT0_STATUS                  0x02
 393 #define SD_CMD_STATUS                   0x01
 394
 395 /* SD_PAD_CTL */
 396 #define SD_IO_USING_1V8                 0x80
 397 #define SD_IO_USING_3V3                 0x7F
 398 #define TYPE_A_DRIVING                  0x00
 399 #define TYPE_B_DRIVING                  0x01
 400 #define TYPE_C_DRIVING                  0x02
 401 #define TYPE_D_DRIVING                  0x03
 402
 403 /* SD_SAMPLE_POINT_CTL */
 404 #define DDR_FIX_RX_DAT                  0x00
 405 #define DDR_VAR_RX_DAT                  0x80
 406 #define DDR_FIX_RX_DAT_EDGE             0x00
 407 #define DDR_FIX_RX_DAT_14_DELAY         0x40
 408 #define DDR_FIX_RX_CMD                  0x00
 409 #define DDR_VAR_RX_CMD                  0x20
 410 #define DDR_FIX_RX_CMD_POS_EDGE         0x00
 411 #define DDR_FIX_RX_CMD_14_DELAY         0x10
 412 #define SD20_RX_POS_EDGE                0x00
 413 #define SD20_RX_14_DELAY                0x08
 414 #define SD20_RX_SEL_MASK                0x08
 415
 416 /* SD_PUSH_POINT_CTL */
 417 #define DDR_FIX_TX_CMD_DAT              0x00
 418 #define DDR_VAR_TX_CMD_DAT              0x80
 419 #define DDR_FIX_TX_DAT_14_TSU           0x00
 420 #define DDR_FIX_TX_DAT_12_TSU           0x40
 421 #define DDR_FIX_TX_CMD_NEG_EDGE         0x00
 422 #define DDR_FIX_TX_CMD_14_AHEAD         0x20
 423 #define SD20_TX_NEG_EDGE                0x00
 424 #define SD20_TX_14_AHEAD                0x10
 425 #define SD20_TX_SEL_MASK                0x10
 426 #define DDR_VAR_SDCLK_POL_SWAP          0x01
 427
 428 /* SD_TRANSFER */
 429 #define SD_TRANSFER_START               0x80
 430 #define SD_TRANSFER_END                 0x40
 431 #define SD_STAT_IDLE                    0x20
 432 #define SD_TRANSFER_ERR                 0x10
 433 /* SD Transfer Mode definition */
 434 #define SD_TM_NORMAL_WRITE              0x00
 435 #define SD_TM_AUTO_WRITE_3              0x01
 436 #define SD_TM_AUTO_WRITE_4              0x02
 437 #define SD_TM_AUTO_READ_3               0x05
 438 #define SD_TM_AUTO_READ_4               0x06
 439 #define SD_TM_CMD_RSP                   0x08
 440 #define SD_TM_AUTO_WRITE_1              0x09
 441 #define SD_TM_AUTO_WRITE_2              0x0A
 442 #define SD_TM_NORMAL_READ               0x0C
 443 #define SD_TM_AUTO_READ_1               0x0D
 444 #define SD_TM_AUTO_READ_2               0x0E
 445 #define SD_TM_AUTO_TUNING               0x0F
 446
 447 /* SD_VPTX_CTL / SD_VPRX_CTL */
 448 #define PHASE_CHANGE                    0x80
 449 #define PHASE_NOT_RESET                 0x40
 450
 451 /* SD_DCMPS_TX_CTL / SD_DCMPS_RX_CTL */
 452 #define DCMPS_CHANGE                    0x80
 453 #define DCMPS_CHANGE_DONE               0x40
 454 #define DCMPS_ERROR                     0x20
 455 #define DCMPS_CURRENT_PHASE             0x1F
 456
 457 /* SD_CMD_STATE */
 458 #define SD_CMD_IDLE                     0x80
 459
 460 /* SD_DATA_STATE */
 461 #define SD_DATA_IDLE                    0x80
 462
 463 /* MS_BLKEND */
 464 #define SET_BLKEND                      0x01
 465
 466 /* MS_CFG */
 467 #define SAMPLE_TIME_RISING              0x00
 468 #define SAMPLE_TIME_FALLING             0x80
 469 #define PUSH_TIME_DEFAULT               0x00
 470 #define PUSH_TIME_ODD                   0x40
 471 #define NO_EXTEND_TOGGLE                0x00
 472 #define EXTEND_TOGGLE_CHK               0x20
 473 #define MS_BUS_WIDTH_1                  0x00
 474 #define MS_BUS_WIDTH_4                  0x10
 475 #define MS_BUS_WIDTH_8                  0x18
 476 #define MS_2K_SECTOR_MODE               0x04
 477 #define MS_512_SECTOR_MODE              0x00
 478 #define MS_TOGGLE_TIMEOUT_EN            0x00
 479 #define MS_TOGGLE_TIMEOUT_DISEN         0x01
 480 #define MS_NO_CHECK_INT                 0x02
 481
 482 /* MS_TRANS_CFG */
 483 #define WAIT_INT                        0x80
 484 #define NO_WAIT_INT                     0x00
 485 #define NO_AUTO_READ_INT_REG            0x00
 486 #define AUTO_READ_INT_REG               0x40
 487 #define MS_CRC16_ERR                    0x20
 488 #define MS_RDY_TIMEOUT                  0x10
 489 #define MS_INT_CMDNK                    0x08
 490 #define MS_INT_BREQ                     0x04
 491 #define MS_INT_ERR                      0x02
 492 #define MS_INT_CED                      0x01
 493
 494 /* MS_TRANSFER */
 495 #define MS_TRANSFER_START               0x80
 496 #define MS_TRANSFER_END                 0x40
 497 #define MS_TRANSFER_ERR                 0x20
 498 #define MS_BS_STATE                     0x10
 499 #define MS_TM_READ_BYTES                0x00
 500 #define MS_TM_NORMAL_READ               0x01
 501 #define MS_TM_WRITE_BYTES               0x04
 502 #define MS_TM_NORMAL_WRITE              0x05
 503 #define MS_TM_AUTO_READ                 0x08
 504 #define MS_TM_AUTO_WRITE                0x0C
 505 #define MS_TM_SET_CMD                   0x06
 506 #define MS_TM_COPY_PAGE                 0x07
 507 #define MS_TM_MULTI_READ                0x02
 508 #define MS_TM_MULTI_WRITE               0x03
 509
 510 /* MC_DMA_CTL */
 511 #define DMA_TC_EQ_0                     0x80
 512 #define DMA_DIR_TO_CARD                 0x00
 513 #define DMA_DIR_FROM_CARD               0x02
 514 #define DMA_EN                          0x01
 515 #define DMA_128                         (0 << 2)
 516 #define DMA_256                         (1 << 2)
 517 #define DMA_512                         (2 << 2)
 518 #define DMA_1024                        (3 << 2)
 519 #define DMA_PACK_SIZE_MASK              0x0C
 520
 521 /* CARD_INT_PEND */
 522 #define XD_INT                          0x10
 523 #define MS_INT                          0x08
 524 #define SD_INT                          0x04
 525
 526 /* MC_FIFO_CTL */
 527 #define FIFO_FLUSH                      0x01
 528
 529 /* AUTO_DELINK_EN */
 530 #define AUTO_DELINK                     0x02
 531 #define FORCE_DELINK                    0x01
 532
 533 /* MC_DMA_RST */
 534 #define DMA_RESET  0x01
 535
 536 #define SSC_POWER_MASK                  0x01
 537 #define SSC_POWER_DOWN                  0x01
 538 #define SSC_POWER_ON                    0x00
 539
 540 /* OCPCTL */
 541 #define MS_OCP_DETECT_EN                0x08
 542 #define MS_OCP_INT_EN                   0x04
 543 #define MS_OCP_INT_CLR                  0x02
 544 #define MS_OCP_CLEAR                    0x01
 545
 546 /* OCPSTAT */
 547 #define MS_OCP_DETECT                   0x80
 548 #define MS_OCP_NOW                      0x02
 549 #define MS_OCP_EVER                     0x01
 550
 551 /* MC_FIFO_STAT */
 552 #define FIFO_FULL               0x01
 553 #define FIFO_EMPTY              0x02
 554
 555 /* RCCTL */
 556 #define U_HW_CMD_EN_MASK                0x02
 557 #define U_HW_CMD_EN                     0x02
 558 #define U_HW_CMD_DIS                    0x00
 559
 560 /* Register address */
 561 #define FPDCTL                          0xFC00
 562 #define SSC_DIV_N_0                     0xFC07
 563 #define SSC_CTL1                        0xFC09
 564 #define SSC_CTL2                        0xFC0A
 565 #define CFG_MODE_1              0xFC0F
 566 #define RCCTL                   0xFC14
 567 #define SYS_DUMMY0                      0xFC30
 568 #define XD_CP_WAITTIME                  0xFD00
 569 #define XD_CP_PAGELEN                   0xFD01
 570 #define XD_CP_READADDR0                 0xFD02
 571 #define XD_CP_READADDR1                 0xFD03
 572 #define XD_CP_READADDR2                 0xFD04
 573 #define XD_CP_READADDR3                 0xFD05
 574 #define XD_CP_READADDR4                 0xFD06
 575 #define XD_CP_WRITEADDR0                0xFD07
 576 #define XD_CP_WRITEADDR1                0xFD08
 577 #define XD_CP_WRITEADDR2                0xFD09
 578 #define XD_CP_WRITEADDR3                0xFD0A
 579 #define XD_CP_WRITEADDR4                0xFD0B
 580 #define XD_INIT                         0xFD10
 581 #define XD_DTCTL                        0xFD11
 582 #define XD_CTL                          0xFD12
 583 #define XD_TRANSFER                     0xFD13
 584 #define XD_CFG                          0xFD14
 585 #define XD_ADDRESS0                     0xFD15
 586 #define XD_ADDRESS1                     0xFD16
 587 #define XD_ADDRESS2                     0xFD17
 588 #define XD_ADDRESS3                     0xFD18
 589 #define XD_ADDRESS4                     0xFD19
 590 #define XD_DAT                          0xFD1A
 591 #define XD_PAGE_CNT                     0xFD1B
 592 #define XD_PAGE_STATUS                  0xFD1C
 593 #define XD_BLOCK_STATUS                 0xFD1D
 594 #define XD_BLOCK_ADDR1_L                0xFD1E
 595 #define XD_BLOCK_ADDR1_H                0xFD1F
 596 #define XD_BLOCK_ADDR2_L                0xFD20
 597 #define XD_BLOCK_ADDR2_H                0xFD21
 598 #define XD_BYTE_CNT_L                   0xFD22
 599 #define XD_BYTE_CNT_H                   0xFD23
 600 #define XD_PARITY                       0xFD24
 601 #define XD_ECC_BIT1                     0xFD25
 602 #define XD_ECC_BYTE1                    0xFD26
 603 #define XD_ECC_BIT2                     0xFD27
 604 #define XD_ECC_BYTE2                    0xFD28
 605 #define XD_RESERVED0                    0xFD29
 606 #define XD_RESERVED1                    0xFD2A
 607 #define XD_RESERVED2                    0xFD2B
 608 #define XD_RESERVED3                    0xFD2C
 609 #define XD_CHK_DATA_STATUS              0xFD2D
 610 #define XD_CATCTL                       0xFD2E
 611
 612 #define MS_BLKEND                       0xFD30
 613 #define MS_READ_START                   0xFD31
 614 #define MS_READ_COUNT                   0xFD32
 615 #define MS_WRITE_START                  0xFD33
 616 #define MS_WRITE_COUNT                  0xFD34
 617 #define MS_COMMAND                      0xFD35
 618 #define MS_OLD_BLOCK_0                  0xFD36
 619 #define MS_OLD_BLOCK_1                  0xFD37
 620 #define MS_NEW_BLOCK_0                  0xFD38
 621 #define MS_NEW_BLOCK_1                  0xFD39
 622 #define MS_LOG_BLOCK_0                  0xFD3A
 623 #define MS_LOG_BLOCK_1                  0xFD3B
 624 #define MS_BUS_WIDTH                    0xFD3C
 625 #define MS_PAGE_START                   0xFD3D
 626 #define MS_PAGE_LENGTH                  0xFD3E
 627 #define MS_CFG                          0xFD40
 628 #define MS_TPC                          0xFD41
 629 #define MS_TRANS_CFG                    0xFD42
 630 #define MS_TRANSFER                     0xFD43
 631 #define MS_INT_REG                      0xFD44
 632 #define MS_BYTE_CNT                     0xFD45
 633 #define MS_SECTOR_CNT_L                 0xFD46
 634 #define MS_SECTOR_CNT_H                 0xFD47
 635 #define MS_DBUS_H                       0xFD48
 636
 637 #define CARD_DMA1_CTL                   0xFD5C
 638 #define CARD_PULL_CTL1                  0xFD60
 639 #define CARD_PULL_CTL2                  0xFD61
 640 #define CARD_PULL_CTL3                  0xFD62
 641 #define CARD_PULL_CTL4                  0xFD63
 642 #define CARD_PULL_CTL5                  0xFD64
 643 #define CARD_PULL_CTL6                  0xFD65
 644 #define CARD_EXIST                              0xFD6F
 645 #define CARD_INT_PEND                   0xFD71
 646
 647 #define LDO_POWER_CFG                   0xFD7B
 648
 649 #define SD_CFG1                         0xFDA0
 650 #define SD_CFG2                         0xFDA1
 651 #define SD_CFG3                         0xFDA2
 652 #define SD_STAT1                        0xFDA3
 653 #define SD_STAT2                        0xFDA4
 654 #define SD_BUS_STAT                     0xFDA5
 655 #define SD_PAD_CTL                      0xFDA6
 656 #define SD_SAMPLE_POINT_CTL             0xFDA7
 657 #define SD_PUSH_POINT_CTL               0xFDA8
 658 #define SD_CMD0                         0xFDA9
 659 #define SD_CMD1                         0xFDAA
 660 #define SD_CMD2                         0xFDAB
 661 #define SD_CMD3                         0xFDAC
 662 #define SD_CMD4                         0xFDAD
 663 #define SD_CMD5                         0xFDAE
 664 #define SD_BYTE_CNT_L                   0xFDAF
 665 #define SD_BYTE_CNT_H                   0xFDB0
 666 #define SD_BLOCK_CNT_L                  0xFDB1
 667 #define SD_BLOCK_CNT_H                  0xFDB2
 668 #define SD_TRANSFER                     0xFDB3
 669 #define SD_CMD_STATE                    0xFDB5
 670 #define SD_DATA_STATE                   0xFDB6
 671 #define SD_VPCLK0_CTL                   0xFC2A
 672 #define SD_VPCLK1_CTL                   0xFC2B
 673 #define SD_DCMPS0_CTL                   0xFC2C
 674 #define SD_DCMPS1_CTL                   0xFC2D
 675
 676 #define CARD_DMA1_CTL                   0xFD5C
 677
 678 #define HW_VERSION                      0xFC01
 679
 680 #define SSC_CLK_FPGA_SEL                0xFC02
 681 #define CLK_DIV                         0xFC03
 682 #define SFSM_ED                         0xFC04
 683
 684 #define CD_DEGLITCH_WIDTH               0xFC20
 685 #define CD_DEGLITCH_EN                  0xFC21
 686 #define AUTO_DELINK_EN                  0xFC23
 687
 688 #define FPGA_PULL_CTL                   0xFC1D
 689 #define CARD_CLK_SOURCE                 0xFC2E
 690
 691 #define CARD_SHARE_MODE                 0xFD51
 692 #define CARD_DRIVE_SEL                  0xFD52
 693 #define CARD_STOP                       0xFD53
 694 #define CARD_OE                         0xFD54
 695 #define CARD_AUTO_BLINK                 0xFD55
 696 #define CARD_GPIO                       0xFD56
 697 #define SD30_DRIVE_SEL          0xFD57
 698
 699 #define CARD_DATA_SOURCE                0xFD5D
 700 #define CARD_SELECT                     0xFD5E
 701
 702 #define CARD_CLK_EN                     0xFD79
 703 #define CARD_PWR_CTL                    0xFD7A
 704
 705 #define OCPCTL                          0xFD80
 706 #define OCPPARA1                        0xFD81
 707 #define OCPPARA2                        0xFD82
 708 #define OCPSTAT                         0xFD83
 709
 710 #define HS_USB_STAT                     0xFE01
 711 #define HS_VCONTROL                     0xFE26
 712 #define HS_VSTAIN                       0xFE27
 713 #define HS_VLOADM                       0xFE28
 714 #define HS_VSTAOUT                      0xFE29
 715
 716 #define MC_IRQ                          0xFF00
 717 #define MC_IRQEN                        0xFF01
 718 #define MC_FIFO_CTL                     0xFF02
 719 #define MC_FIFO_BC0                     0xFF03
 720 #define MC_FIFO_BC1                     0xFF04
 721 #define MC_FIFO_STAT                    0xFF05
 722 #define MC_FIFO_MODE                    0xFF06
 723 #define MC_FIFO_RD_PTR0         0xFF07
 724 #define MC_FIFO_RD_PTR1         0xFF08
 725 #define MC_DMA_CTL                      0xFF10
 726 #define MC_DMA_TC0                      0xFF11
 727 #define MC_DMA_TC1                      0xFF12
 728 #define MC_DMA_TC2                      0xFF13
 729 #define MC_DMA_TC3                      0xFF14
 730 #define MC_DMA_RST                      0xFF15
 731
 732 /* Memory mapping */
 733 #define RBUF_SIZE_MASK          0xFBFF
 734 #define RBUF_BASE                       0xF000
 735 #define PPBUF_BASE1                     0xF800
 736 #define PPBUF_BASE2                     0xFA00
 737
 738 /* int monitor_card_cd */
 739 #define CD_EXIST                        0
 740 #define CD_NOT_EXIST                    1
 741
 742 #define DEBOUNCE_CNT                    5
 743
 744 int monitor_card_cd(struct rts51x_chip *chip, u8 card);
 745
 746 void do_remaining_work(struct rts51x_chip *chip);
 747 void do_reset_xd_card(struct rts51x_chip *chip);
 748 void do_reset_sd_card(struct rts51x_chip *chip);
 749 void do_reset_ms_card(struct rts51x_chip *chip);
 750 void rts51x_init_cards(struct rts51x_chip *chip);
 751 void rts51x_release_cards(struct rts51x_chip *chip);
 752 int switch_ssc_clock(struct rts51x_chip *chip, int clk);
 753 int switch_normal_clock(struct rts51x_chip *chip, int clk);
 754 int card_rw(struct scsi_cmnd *srb, struct rts51x_chip *chip, u32 sec_addr,
 755             u16 sec_cnt);
 756 u8 get_lun_card(struct rts51x_chip *chip, unsigned int lun);
 757 int card_share_mode(struct rts51x_chip *chip, int card);
 758 int rts51x_select_card(struct rts51x_chip *chip, int card);
 759 void eject_card(struct rts51x_chip *chip, unsigned int lun);
 760 void trans_dma_enable(enum dma_data_direction dir, struct rts51x_chip *chip,
 761                       u32 byte_cnt, u8 pack_size);
 762 int enable_card_clock(struct rts51x_chip *chip, u8 card);
 763 int disable_card_clock(struct rts51x_chip *chip, u8 card);
 764 int card_power_on(struct rts51x_chip *chip, u8 card);
 765 int card_power_off(struct rts51x_chip *chip, u8 card);
 766 int toggle_gpio(struct rts51x_chip *chip, u8 gpio);
 767 int turn_on_led(struct rts51x_chip *chip, u8 gpio);
 768 int turn_off_led(struct rts51x_chip *chip, u8 gpio);
 769
 770 static inline int check_card_ready(struct rts51x_chip *chip, unsigned int lun)
 771 {
 772         if (chip->card_ready & chip->lun2card[lun])
 773                 return 1;
 774
 775         return 0;
 776 }
 777
 778 static inline int check_card_exist(struct rts51x_chip *chip, unsigned int lun)
 779 {
 780         if (chip->card_exist & chip->lun2card[lun])
 781                 return 1;
 782
 783         return 0;
 784 }
 785
 786 static inline int check_card_wp(struct rts51x_chip *chip, unsigned int lun)
 787 {
 788         if (chip->card_wp & chip->lun2card[lun])
 789                 return 1;
 790
 791         return 0;
 792 }
 793
 794 static inline int check_card_fail(struct rts51x_chip *chip, unsigned int lun)
 795 {
 796         if (chip->card_fail & chip->lun2card[lun])
 797                 return 1;
 798
 799         return 0;
 800 }
 801
 802 static inline int check_card_ejected(struct rts51x_chip *chip, unsigned int lun)
 803 {
 804         if (chip->card_ejected & chip->lun2card[lun])
 805                 return 1;
 806
 807         return 0;
 808 }
 809
 810 static inline int check_fake_card_ready(struct rts51x_chip *chip,
 811                                         unsigned int lun)
 812 {
 813         if (chip->fake_card_ready & chip->lun2card[lun])
 814                 return 1;
 815
 816         return 0;
 817 }
 818
 819 static inline u8 get_lun2card(struct rts51x_chip *chip, unsigned int lun)
 820 {
 821         return chip->lun2card[lun];
 822 }
 823
 824 static inline int check_lun_mc(struct rts51x_chip *chip, unsigned int lun)
 825 {
 826         return CHK_BIT(chip->lun_mc, lun);
 827 }
 828
 829 static inline void set_lun_mc(struct rts51x_chip *chip, unsigned int lun)
 830 {
 831         SET_BIT(chip->lun_mc, lun);
 832 }
 833
 834 static inline void clear_lun_mc(struct rts51x_chip *chip, unsigned int lun)
 835 {
 836         CLR_BIT(chip->lun_mc, lun);
 837 }
 838
 839 static inline int switch_clock(struct rts51x_chip *chip, int clk)
 840 {
 841         int retval = 0;
 842
 843         if (chip->asic_code)
 844                 retval = switch_ssc_clock(chip, clk);
 845         else
 846                 retval = switch_normal_clock(chip, clk);
 847
 848         return retval;
 849 }
 850
 851 static inline void rts51x_clear_xd_error(struct rts51x_chip *chip)
 852 {
 853         rts51x_ep0_write_register(chip, CARD_STOP,
 854                                   XD_STOP | XD_CLR_ERR, XD_STOP | XD_CLR_ERR);
 855
 856         rts51x_ep0_write_register(chip, MC_FIFO_CTL, FIFO_FLUSH, FIFO_FLUSH);
 857         rts51x_ep0_write_register(chip, MC_DMA_RST, DMA_RESET, DMA_RESET);
 858         rts51x_ep0_write_register(chip, SFSM_ED, 0xf8, 0xf8);
 859 }
 860
 861 static inline void rts51x_clear_sd_error(struct rts51x_chip *chip)
 862 {
 863         rts51x_ep0_write_register(chip, CARD_STOP,
 864                                   SD_STOP | SD_CLR_ERR, SD_STOP | SD_CLR_ERR);
 865
 866         rts51x_ep0_write_register(chip, MC_FIFO_CTL, FIFO_FLUSH, FIFO_FLUSH);
 867         rts51x_ep0_write_register(chip, MC_DMA_RST, DMA_RESET, DMA_RESET);
 868         rts51x_ep0_write_register(chip, SFSM_ED, 0xf8, 0xf8);
 869 }
 870
 871 static inline void rts51x_clear_ms_error(struct rts51x_chip *chip)
 872 {
 873         rts51x_ep0_write_register(chip, CARD_STOP,
 874                                   MS_STOP | MS_CLR_ERR, MS_STOP | MS_CLR_ERR);
 875
 876         rts51x_ep0_write_register(chip, MC_FIFO_CTL, FIFO_FLUSH, FIFO_FLUSH);
 877         rts51x_ep0_write_register(chip, MC_DMA_RST, DMA_RESET, DMA_RESET);
 878         rts51x_ep0_write_register(chip, SFSM_ED, 0xf8, 0xf8);
 879 }
 880
 881 #endif /* __RTS51X_CARD_H */