Pileus Git - ~andy/linux/blob - drivers/staging/rts5139/rts51x_card.c

   1 /* Driver for Realtek RTS51xx USB card reader
   2  *
   3  * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License as published by the
   7  * Free Software Foundation; either version 2, or (at your option) any
   8  * later version.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program; if not, see <http://www.gnu.org/licenses/>.
  17  *
  18  * Author:
  19  *   wwang (wei_wang@realsil.com.cn)
  20  *   No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
  21  * Maintainer:
  22  *   Edwin Rong (edwin_rong@realsil.com.cn)
  23  *   No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
  24  */
  25
  26 #include <linux/blkdev.h>
  27 #include <linux/kthread.h>
  28 #include <linux/sched.h>
  29 #include <linux/workqueue.h>
  30
  31 #include <scsi/scsi.h>
  32 #include <scsi/scsi_eh.h>
  33 #include <scsi/scsi_device.h>
  34
  35 #include "debug.h"
  36 #include "rts51x.h"
  37 #include "rts51x_chip.h"
  38 #include "rts51x_card.h"
  39 #include "rts51x_transport.h"
  40 #include "rts51x_sys.h"
  41 #include "xd.h"
  42 #include "sd.h"
  43 #include "ms.h"
  44
  45 void do_remaining_work(struct rts51x_chip *chip)
  46 {
  47         struct sd_info *sd_card = &(chip->sd_card);
  48         struct xd_info *xd_card = &(chip->xd_card);
  49         struct ms_info *ms_card = &(chip->ms_card);
  50
  51         if (chip->card_ready & SD_CARD) {
  52                 if (sd_card->seq_mode) {
  53                         RTS51X_SET_STAT(chip, STAT_RUN);
  54                         sd_card->counter++;
  55                 } else {
  56                         sd_card->counter = 0;
  57                 }
  58         }
  59
  60         if (chip->card_ready & XD_CARD) {
  61                 if (xd_card->delay_write.delay_write_flag) {
  62                         RTS51X_SET_STAT(chip, STAT_RUN);
  63                         xd_card->counter++;
  64                 } else {
  65                         xd_card->counter = 0;
  66                 }
  67         }
  68
  69         if (chip->card_ready & MS_CARD) {
  70                 if (CHK_MSPRO(ms_card)) {
  71                         if (ms_card->seq_mode) {
  72                                 RTS51X_SET_STAT(chip, STAT_RUN);
  73                                 ms_card->counter++;
  74                         } else {
  75                                 ms_card->counter = 0;
  76                         }
  77                 } else {
  78                         if (ms_card->delay_write.delay_write_flag) {
  79                                 RTS51X_SET_STAT(chip, STAT_RUN);
  80                                 ms_card->counter++;
  81                         } else {
  82                                 ms_card->counter = 0;
  83                         }
  84                 }
  85         }
  86
  87         if (sd_card->counter > POLLING_WAIT_CNT)
  88                 sd_cleanup_work(chip);
  89
  90         if (xd_card->counter > POLLING_WAIT_CNT)
  91                 xd_cleanup_work(chip);
  92
  93         if (ms_card->counter > POLLING_WAIT_CNT)
  94                 ms_cleanup_work(chip);
  95 }
  96
  97 void do_reset_xd_card(struct rts51x_chip *chip)
  98 {
  99         int retval;
 100
 101         if (chip->card2lun[XD_CARD] >= MAX_ALLOWED_LUN_CNT)
 102                 return;
 103
 104         retval = reset_xd_card(chip);
 105         if (retval == STATUS_SUCCESS) {
 106                 chip->card_ready |= XD_CARD;
 107                 chip->card_fail &= ~XD_CARD;
 108                 chip->rw_card[chip->card2lun[XD_CARD]] = xd_rw;
 109         } else {
 110                 chip->card_ready &= ~XD_CARD;
 111                 chip->card_fail |= XD_CARD;
 112                 chip->capacity[chip->card2lun[XD_CARD]] = 0;
 113                 chip->rw_card[chip->card2lun[XD_CARD]] = NULL;
 114
 115                 rts51x_init_cmd(chip);
 116                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_OE, XD_OUTPUT_EN, 0);
 117                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PWR_CTL, POWER_MASK,
 118                                POWER_OFF);
 119                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_CLK_EN, XD_CLK_EN, 0);
 120                 rts51x_send_cmd(chip, MODE_C, 100);
 121         }
 122 }
 123
 124 void do_reset_sd_card(struct rts51x_chip *chip)
 125 {
 126         int retval;
 127
 128         if (chip->card2lun[SD_CARD] >= MAX_ALLOWED_LUN_CNT)
 129                 return;
 130
 131         retval = reset_sd_card(chip);
 132         if (retval == STATUS_SUCCESS) {
 133                 chip->card_ready |= SD_CARD;
 134                 chip->card_fail &= ~SD_CARD;
 135                 chip->rw_card[chip->card2lun[SD_CARD]] = sd_rw;
 136         } else {
 137                 chip->card_ready &= ~SD_CARD;
 138                 chip->card_fail |= SD_CARD;
 139                 chip->capacity[chip->card2lun[SD_CARD]] = 0;
 140                 chip->rw_card[chip->card2lun[SD_CARD]] = NULL;
 141
 142                 rts51x_init_cmd(chip);
 143                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_OE, SD_OUTPUT_EN, 0);
 144                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PWR_CTL, POWER_MASK,
 145                                POWER_OFF);
 146                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_CLK_EN, SD_CLK_EN, 0);
 147                 rts51x_send_cmd(chip, MODE_C, 100);
 148         }
 149 }
 150
 151 void do_reset_ms_card(struct rts51x_chip *chip)
 152 {
 153         int retval;
 154
 155         if (chip->card2lun[MS_CARD] >= MAX_ALLOWED_LUN_CNT)
 156                 return;
 157
 158         retval = reset_ms_card(chip);
 159         if (retval == STATUS_SUCCESS) {
 160                 chip->card_ready |= MS_CARD;
 161                 chip->card_fail &= ~MS_CARD;
 162                 chip->rw_card[chip->card2lun[MS_CARD]] = ms_rw;
 163         } else {
 164                 chip->card_ready &= ~MS_CARD;
 165                 chip->card_fail |= MS_CARD;
 166                 chip->capacity[chip->card2lun[MS_CARD]] = 0;
 167                 chip->rw_card[chip->card2lun[MS_CARD]] = NULL;
 168
 169                 rts51x_init_cmd(chip);
 170                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_OE, MS_OUTPUT_EN, 0);
 171                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PWR_CTL, POWER_MASK,
 172                                POWER_OFF);
 173                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_CLK_EN, MS_CLK_EN, 0);
 174                 rts51x_send_cmd(chip, MODE_C, 100);
 175         }
 176 }
 177
 178 void card_cd_debounce(struct rts51x_chip *chip, u8 *need_reset,
 179                       u8 *need_release)
 180 {
 181         int retval;
 182         u8 release_map = 0, reset_map = 0;
 183         u8 value;
 184
 185         retval = rts51x_get_card_status(chip, &(chip->card_status));
 186 #ifdef SUPPORT_OCP
 187         chip->ocp_stat = (chip->card_status >> 4) & 0x03;
 188 #endif
 189
 190         if (retval != STATUS_SUCCESS)
 191                 goto Exit_Debounce;
 192
 193         if (chip->card_exist) {
 194                 retval = rts51x_read_register(chip, CARD_INT_PEND, &value);
 195                 if (retval != STATUS_SUCCESS) {
 196                         rts51x_ep0_write_register(chip, MC_FIFO_CTL, FIFO_FLUSH,
 197                                                   FIFO_FLUSH);
 198                         rts51x_ep0_write_register(chip, SFSM_ED, 0xf8, 0xf8);
 199                         value = 0;
 200                 }
 201
 202                 if (chip->card_exist & XD_CARD) {
 203                         if (!(chip->card_status & XD_CD))
 204                                 release_map |= XD_CARD;
 205                 } else if (chip->card_exist & SD_CARD) {
 206                         /* if (!(chip->card_status & SD_CD)) { */
 207                         if (!(chip->card_status & SD_CD) || (value & SD_INT))
 208                                 release_map |= SD_CARD;
 209                 } else if (chip->card_exist & MS_CARD) {
 210                         /* if (!(chip->card_status & MS_CD)) { */
 211                         if (!(chip->card_status & MS_CD) || (value & MS_INT))
 212                                 release_map |= MS_CARD;
 213                 }
 214         } else {
 215                 if (chip->card_status & XD_CD) {
 216                         reset_map |= XD_CARD;
 217                 } else if (chip->card_status & SD_CD) {
 218                         reset_map |= SD_CARD;
 219                 } else if (chip->card_status & MS_CD) {
 220                         reset_map |= MS_CARD;
 221                 }
 222         }
 223
 224         if (CHECK_PKG(chip, QFN24) && reset_map) {
 225                 if (chip->card_exist & XD_CARD) {
 226                         reset_map = 0;
 227                         goto Exit_Debounce;
 228                 }
 229         }
 230
 231         if (reset_map) {
 232                 int xd_cnt = 0, sd_cnt = 0, ms_cnt = 0;
 233                 int i;
 234
 235                 for (i = 0; i < (chip->option.debounce_num); i++) {
 236                         retval =
 237                             rts51x_get_card_status(chip, &(chip->card_status));
 238                         if (retval != STATUS_SUCCESS) {
 239                                 reset_map = release_map = 0;
 240                                 goto Exit_Debounce;
 241                         }
 242                         if (chip->card_status & XD_CD)
 243                                 xd_cnt++;
 244                         else
 245                                 xd_cnt = 0;
 246                         if (chip->card_status & SD_CD)
 247                                 sd_cnt++;
 248                         else
 249                                 sd_cnt = 0;
 250                         if (chip->card_status & MS_CD)
 251                                 ms_cnt++;
 252                         else
 253                                 ms_cnt = 0;
 254                         wait_timeout(30);
 255                 }
 256
 257                 reset_map = 0;
 258                 if (!(chip->card_exist & XD_CARD)
 259                     && (xd_cnt > (chip->option.debounce_num - 1))) {
 260                         reset_map |= XD_CARD;
 261                 }
 262                 if (!(chip->card_exist & SD_CARD)
 263                     && (sd_cnt > (chip->option.debounce_num - 1))) {
 264                         reset_map |= SD_CARD;
 265                 }
 266                 if (!(chip->card_exist & MS_CARD)
 267                     && (ms_cnt > (chip->option.debounce_num - 1))) {
 268                         reset_map |= MS_CARD;
 269                 }
 270         }
 271         rts51x_write_register(chip, CARD_INT_PEND, XD_INT | MS_INT | SD_INT,
 272                               XD_INT | MS_INT | SD_INT);
 273
 274 Exit_Debounce:
 275         if (need_reset)
 276                 *need_reset = reset_map;
 277         if (need_release)
 278                 *need_release = release_map;
 279 }
 280
 281 void rts51x_init_cards(struct rts51x_chip *chip)
 282 {
 283         u8 need_reset = 0, need_release = 0;
 284
 285         card_cd_debounce(chip, &need_reset, &need_release);
 286
 287         if (need_release) {
 288                 RTS51X_DEBUGP("need_release = 0x%x\n", need_release);
 289
 290                 rts51x_prepare_run(chip);
 291                 RTS51X_SET_STAT(chip, STAT_RUN);
 292
 293 #ifdef SUPPORT_OCP
 294                 if (chip->ocp_stat & (MS_OCP_NOW | MS_OCP_EVER)) {
 295                         rts51x_write_register(chip, OCPCTL, MS_OCP_CLEAR,
 296                                               MS_OCP_CLEAR);
 297                         chip->ocp_stat = 0;
 298                         RTS51X_DEBUGP("Clear OCP status.\n");
 299                 }
 300 #endif
 301
 302                 if (need_release & XD_CARD) {
 303                         chip->card_exist &= ~XD_CARD;
 304                         chip->card_ejected = 0;
 305                         if (chip->card_ready & XD_CARD) {
 306                                 release_xd_card(chip);
 307                                 chip->rw_card[chip->card2lun[XD_CARD]] = NULL;
 308                                 clear_bit(chip->card2lun[XD_CARD],
 309                                           &(chip->lun_mc));
 310                         }
 311                 }
 312
 313                 if (need_release & SD_CARD) {
 314                         chip->card_exist &= ~SD_CARD;
 315                         chip->card_ejected = 0;
 316                         if (chip->card_ready & SD_CARD) {
 317                                 release_sd_card(chip);
 318                                 chip->rw_card[chip->card2lun[SD_CARD]] = NULL;
 319                                 clear_bit(chip->card2lun[SD_CARD],
 320                                           &(chip->lun_mc));
 321                         }
 322                 }
 323
 324                 if (need_release & MS_CARD) {
 325                         chip->card_exist &= ~MS_CARD;
 326                         chip->card_ejected = 0;
 327                         if (chip->card_ready & MS_CARD) {
 328                                 release_ms_card(chip);
 329                                 chip->rw_card[chip->card2lun[MS_CARD]] = NULL;
 330                                 clear_bit(chip->card2lun[MS_CARD],
 331                                           &(chip->lun_mc));
 332                         }
 333                 }
 334         }
 335
 336         if (need_reset && !chip->card_ready) {
 337                 RTS51X_DEBUGP("need_reset = 0x%x\n", need_reset);
 338
 339                 rts51x_prepare_run(chip);
 340                 RTS51X_SET_STAT(chip, STAT_RUN);
 341
 342                 if (need_reset & XD_CARD) {
 343                         chip->card_exist |= XD_CARD;
 344                         do_reset_xd_card(chip);
 345                 } else if (need_reset & SD_CARD) {
 346                         chip->card_exist |= SD_CARD;
 347                         do_reset_sd_card(chip);
 348                 } else if (need_reset & MS_CARD) {
 349                         chip->card_exist |= MS_CARD;
 350                         do_reset_ms_card(chip);
 351                 }
 352         }
 353 }
 354
 355 void rts51x_release_cards(struct rts51x_chip *chip)
 356 {
 357         if (chip->card_ready & SD_CARD) {
 358                 sd_cleanup_work(chip);
 359                 release_sd_card(chip);
 360                 chip->card_ready &= ~SD_CARD;
 361         }
 362
 363         if (chip->card_ready & XD_CARD) {
 364                 xd_cleanup_work(chip);
 365                 release_xd_card(chip);
 366                 chip->card_ready &= ~XD_CARD;
 367         }
 368
 369         if (chip->card_ready & MS_CARD) {
 370                 ms_cleanup_work(chip);
 371                 release_ms_card(chip);
 372                 chip->card_ready &= ~MS_CARD;
 373         }
 374 }
 375
 376 static inline u8 double_depth(u8 depth)
 377 {
 378         return ((depth > 1) ? (depth - 1) : depth);
 379 }
 380
 381 int switch_ssc_clock(struct rts51x_chip *chip, int clk)
 382 {
 383         struct sd_info *sd_card = &(chip->sd_card);
 384         struct ms_info *ms_card = &(chip->ms_card);
 385         int retval;
 386         u8 N = (u8) (clk - 2), min_N, max_N;
 387         u8 mcu_cnt, div, max_div, ssc_depth;
 388         int sd_vpclk_phase_reset = 0;
 389
 390         if (chip->cur_clk == clk)
 391                 return STATUS_SUCCESS;
 392
 393         min_N = 60;
 394         max_N = 120;
 395         max_div = CLK_DIV_4;
 396
 397         RTS51X_DEBUGP("Switch SSC clock to %dMHz\n", clk);
 398
 399         if ((clk <= 2) || (N > max_N))
 400                 TRACE_RET(chip, STATUS_FAIL);
 401
 402         mcu_cnt = (u8) (60 / clk + 3);
 403         if (mcu_cnt > 15)
 404                 mcu_cnt = 15;
 405         /* To make sure that the SSC clock div_n is
 406          * equal or greater than min_N */
 407         div = CLK_DIV_1;
 408         while ((N < min_N) && (div < max_div)) {
 409                 N = (N + 2) * 2 - 2;
 410                 div++;
 411         }
 412         RTS51X_DEBUGP("N = %d, div = %d\n", N, div);
 413
 414         if (chip->option.ssc_en) {
 415                 if (chip->cur_card == SD_CARD) {
 416                         if (CHK_SD_SDR104(sd_card)) {
 417                                 ssc_depth = chip->option.ssc_depth_sd_sdr104;
 418                         } else if (CHK_SD_SDR50(sd_card)) {
 419                                 ssc_depth = chip->option.ssc_depth_sd_sdr50;
 420                         } else if (CHK_SD_DDR50(sd_card)) {
 421                                 ssc_depth =
 422                                     double_depth(chip->option.
 423                                                  ssc_depth_sd_ddr50);
 424                         } else if (CHK_SD_HS(sd_card)) {
 425                                 ssc_depth =
 426                                     double_depth(chip->option.ssc_depth_sd_hs);
 427                         } else if (CHK_MMC_52M(sd_card)
 428                                    || CHK_MMC_DDR52(sd_card)) {
 429                                 ssc_depth =
 430                                     double_depth(chip->option.
 431                                                  ssc_depth_mmc_52m);
 432                         } else {
 433                                 ssc_depth =
 434                                     double_depth(chip->option.
 435                                                  ssc_depth_low_speed);
 436                         }
 437                 } else if (chip->cur_card == MS_CARD) {
 438                         if (CHK_MSPRO(ms_card)) {
 439                                 if (CHK_HG8BIT(ms_card)) {
 440                                         ssc_depth =
 441                                             double_depth(chip->option.
 442                                                          ssc_depth_ms_hg);
 443                                 } else {
 444                                         ssc_depth =
 445                                             double_depth(chip->option.
 446                                                          ssc_depth_ms_4bit);
 447                                 }
 448                         } else {
 449                                 if (CHK_MS4BIT(ms_card)) {
 450                                         ssc_depth =
 451                                             double_depth(chip->option.
 452                                                          ssc_depth_ms_4bit);
 453                                 } else {
 454                                         ssc_depth =
 455                                             double_depth(chip->option.
 456                                                          ssc_depth_low_speed);
 457                                 }
 458                         }
 459                 } else {
 460                         ssc_depth =
 461                             double_depth(chip->option.ssc_depth_low_speed);
 462                 }
 463
 464                 if (ssc_depth) {
 465                         if (div == CLK_DIV_2) {
 466                                 /* If clock divided by 2, ssc depth must
 467                                  * be multiplied by 2 */
 468                                 if (ssc_depth > 1)
 469                                         ssc_depth -= 1;
 470                                 else
 471                                         ssc_depth = SSC_DEPTH_2M;
 472                         } else if (div == CLK_DIV_4) {
 473                                 /* If clock divided by 4, ssc depth must
 474                                  * be multiplied by 4 */
 475                                 if (ssc_depth > 2)
 476                                         ssc_depth -= 2;
 477                                 else
 478                                         ssc_depth = SSC_DEPTH_2M;
 479                         }
 480                 }
 481         } else {
 482                 /* Disable SSC */
 483                 ssc_depth = 0;
 484         }
 485
 486         RTS51X_DEBUGP("ssc_depth = %d\n", ssc_depth);
 487
 488         rts51x_init_cmd(chip);
 489         rts51x_add_cmd(chip, WRITE_REG_CMD, CLK_DIV, CLK_CHANGE, CLK_CHANGE);
 490         rts51x_add_cmd(chip, WRITE_REG_CMD, CLK_DIV, 0x3F,
 491                        (div << 4) | mcu_cnt);
 492         rts51x_add_cmd(chip, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0);
 493         rts51x_add_cmd(chip, WRITE_REG_CMD, SSC_CTL2, SSC_DEPTH_MASK,
 494                        ssc_depth);
 495         rts51x_add_cmd(chip, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, N);
 496         if (sd_vpclk_phase_reset) {
 497                 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_VPCLK0_CTL,
 498                                PHASE_NOT_RESET, 0);
 499                 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_VPCLK0_CTL,
 500                                PHASE_NOT_RESET, PHASE_NOT_RESET);
 501         }
 502
 503         retval = rts51x_send_cmd(chip, MODE_C, 2000);
 504         if (retval != STATUS_SUCCESS)
 505                 TRACE_RET(chip, retval);
 506         if (chip->option.ssc_en && ssc_depth)
 507                 rts51x_write_register(chip, SSC_CTL1, 0xff, 0xD0);
 508         else
 509                 rts51x_write_register(chip, SSC_CTL1, 0xff, 0x50);
 510         udelay(100);
 511         RTS51X_WRITE_REG(chip, CLK_DIV, CLK_CHANGE, 0);
 512
 513         chip->cur_clk = clk;
 514
 515         return STATUS_SUCCESS;
 516 }
 517
 518 int switch_normal_clock(struct rts51x_chip *chip, int clk)
 519 {
 520         int retval;
 521         u8 sel, div, mcu_cnt;
 522         int sd_vpclk_phase_reset = 0;
 523
 524         if (chip->cur_clk == clk)
 525                 return STATUS_SUCCESS;
 526
 527         if (chip->cur_card == SD_CARD) {
 528                 struct sd_info *sd_card = &(chip->sd_card);
 529                 if (CHK_SD30_SPEED(sd_card) || CHK_MMC_DDR52(sd_card))
 530                         sd_vpclk_phase_reset = 1;
 531         }
 532
 533         switch (clk) {
 534         case CLK_20:
 535                 RTS51X_DEBUGP("Switch clock to 20MHz\n");
 536                 sel = SSC_80;
 537                 div = CLK_DIV_4;
 538                 mcu_cnt = 5;
 539                 break;
 540
 541         case CLK_30:
 542                 RTS51X_DEBUGP("Switch clock to 30MHz\n");
 543                 sel = SSC_60;
 544                 div = CLK_DIV_2;
 545                 mcu_cnt = 4;
 546                 break;
 547
 548         case CLK_40:
 549                 RTS51X_DEBUGP("Switch clock to 40MHz\n");
 550                 sel = SSC_80;
 551                 div = CLK_DIV_2;
 552                 mcu_cnt = 3;
 553                 break;
 554
 555         case CLK_50:
 556                 RTS51X_DEBUGP("Switch clock to 50MHz\n");
 557                 sel = SSC_100;
 558                 div = CLK_DIV_2;
 559                 mcu_cnt = 3;
 560                 break;
 561
 562         case CLK_60:
 563                 RTS51X_DEBUGP("Switch clock to 60MHz\n");
 564                 sel = SSC_60;
 565                 div = CLK_DIV_1;
 566                 mcu_cnt = 3;
 567                 break;
 568
 569         case CLK_80:
 570                 RTS51X_DEBUGP("Switch clock to 80MHz\n");
 571                 sel = SSC_80;
 572                 div = CLK_DIV_1;
 573                 mcu_cnt = 2;
 574                 break;
 575
 576         case CLK_100:
 577                 RTS51X_DEBUGP("Switch clock to 100MHz\n");
 578                 sel = SSC_100;
 579                 div = CLK_DIV_1;
 580                 mcu_cnt = 2;
 581                 break;
 582
 583         /* case CLK_120:
 584                 RTS51X_DEBUGP("Switch clock to 120MHz\n");
 585                 sel = SSC_120;
 586                 div = CLK_DIV_1;
 587                 mcu_cnt = 2;
 588                 break;
 589
 590         case CLK_150:
 591                 RTS51X_DEBUGP("Switch clock to 150MHz\n");
 592                 sel = SSC_150;
 593                 div = CLK_DIV_1;
 594                 mcu_cnt = 2;
 595                 break; */
 596
 597         default:
 598                 RTS51X_DEBUGP("Try to switch to an illegal clock (%d)\n",
 599                                clk);
 600                 TRACE_RET(chip, STATUS_FAIL);
 601         }
 602
 603         if (!sd_vpclk_phase_reset) {
 604                 rts51x_init_cmd(chip);
 605
 606                 rts51x_add_cmd(chip, WRITE_REG_CMD, CLK_DIV, CLK_CHANGE,
 607                                CLK_CHANGE);
 608                 rts51x_add_cmd(chip, WRITE_REG_CMD, CLK_DIV, 0x3F,
 609                                (div << 4) | mcu_cnt);
 610                 rts51x_add_cmd(chip, WRITE_REG_CMD, SSC_CLK_FPGA_SEL, 0xFF,
 611                                sel);
 612                 rts51x_add_cmd(chip, WRITE_REG_CMD, CLK_DIV, CLK_CHANGE, 0);
 613
 614                 retval = rts51x_send_cmd(chip, MODE_C, 100);
 615                 if (retval != STATUS_SUCCESS)
 616                         TRACE_RET(chip, retval);
 617         } else {
 618                 rts51x_init_cmd(chip);
 619
 620                 rts51x_add_cmd(chip, WRITE_REG_CMD, CLK_DIV, CLK_CHANGE,
 621                                CLK_CHANGE);
 622                 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_VPCLK0_CTL,
 623                                PHASE_NOT_RESET, 0);
 624                 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_VPCLK1_CTL,
 625                                PHASE_NOT_RESET, 0);
 626                 rts51x_add_cmd(chip, WRITE_REG_CMD, CLK_DIV, 0x3F,
 627                                (div << 4) | mcu_cnt);
 628                 rts51x_add_cmd(chip, WRITE_REG_CMD, SSC_CLK_FPGA_SEL, 0xFF,
 629                                sel);
 630
 631                 retval = rts51x_send_cmd(chip, MODE_C, 100);
 632                 if (retval != STATUS_SUCCESS)
 633                         TRACE_RET(chip, retval);
 634
 635                 udelay(200);
 636
 637                 rts51x_init_cmd(chip);
 638
 639                 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_VPCLK0_CTL,
 640                                PHASE_NOT_RESET, PHASE_NOT_RESET);
 641                 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_VPCLK1_CTL,
 642                                PHASE_NOT_RESET, PHASE_NOT_RESET);
 643
 644                 retval = rts51x_send_cmd(chip, MODE_C, 100);
 645                 if (retval != STATUS_SUCCESS)
 646                         TRACE_RET(chip, retval);
 647
 648                 udelay(200);
 649
 650                 RTS51X_WRITE_REG(chip, CLK_DIV, CLK_CHANGE, 0);
 651         }
 652
 653         chip->cur_clk = clk;
 654
 655         return STATUS_SUCCESS;
 656 }
 657
 658 int card_rw(struct scsi_cmnd *srb, struct rts51x_chip *chip, u32 sec_addr,
 659             u16 sec_cnt)
 660 {
 661         int retval;
 662         unsigned int lun = SCSI_LUN(srb);
 663         int i;
 664
 665         if (chip->rw_card[lun] == NULL)
 666                 return STATUS_FAIL;
 667
 668         RTS51X_DEBUGP("%s card, sector addr: 0x%x, sector cnt: %d\n",
 669                        (srb->sc_data_direction ==
 670                         DMA_TO_DEVICE) ? "Write" : "Read", sec_addr, sec_cnt);
 671
 672         chip->rw_need_retry = 0;
 673         for (i = 0; i < 3; i++) {
 674                 retval = chip->rw_card[lun] (srb, chip, sec_addr, sec_cnt);
 675                 if (retval != STATUS_SUCCESS) {
 676                         CATCH_TRIGGER(chip);
 677                         if (chip->option.reset_or_rw_fail_set_pad_drive) {
 678                                 rts51x_write_register(chip, CARD_DRIVE_SEL,
 679                                                       SD20_DRIVE_MASK,
 680                                                       DRIVE_8mA);
 681                         }
 682                 }
 683
 684                 if (!chip->rw_need_retry)
 685                         break;
 686
 687                 RTS51X_DEBUGP("Retry RW, (i = %d\n)", i);
 688         }
 689
 690         return retval;
 691 }
 692
 693 u8 get_lun_card(struct rts51x_chip *chip, unsigned int lun)
 694 {
 695         if ((chip->card_ready & chip->lun2card[lun]) == XD_CARD)
 696                 return (u8) XD_CARD;
 697         else if ((chip->card_ready & chip->lun2card[lun]) == SD_CARD)
 698                 return (u8) SD_CARD;
 699         else if ((chip->card_ready & chip->lun2card[lun]) == MS_CARD)
 700                 return (u8) MS_CARD;
 701
 702         return 0;
 703 }
 704
 705 int card_share_mode(struct rts51x_chip *chip, int card)
 706 {
 707         u8 value;
 708
 709         if (card == SD_CARD)
 710                 value = CARD_SHARE_SD;
 711         else if (card == MS_CARD)
 712                 value = CARD_SHARE_MS;
 713         else if (card == XD_CARD)
 714                 value = CARD_SHARE_XD;
 715         else
 716                 TRACE_RET(chip, STATUS_FAIL);
 717
 718         RTS51X_WRITE_REG(chip, CARD_SHARE_MODE, CARD_SHARE_MASK, value);
 719
 720         return STATUS_SUCCESS;
 721 }
 722
 723 int rts51x_select_card(struct rts51x_chip *chip, int card)
 724 {
 725         int retval;
 726
 727         if (chip->cur_card != card) {
 728                 u8 mod;
 729
 730                 if (card == SD_CARD)
 731                         mod = SD_MOD_SEL;
 732                 else if (card == MS_CARD)
 733                         mod = MS_MOD_SEL;
 734                 else if (card == XD_CARD)
 735                         mod = XD_MOD_SEL;
 736                 else
 737                         TRACE_RET(chip, STATUS_FAIL);
 738                 RTS51X_WRITE_REG(chip, CARD_SELECT, 0x07, mod);
 739                 chip->cur_card = card;
 740
 741                 retval = card_share_mode(chip, card);
 742                 if (retval != STATUS_SUCCESS)
 743                         TRACE_RET(chip, retval);
 744         }
 745
 746         return STATUS_SUCCESS;
 747 }
 748
 749 void eject_card(struct rts51x_chip *chip, unsigned int lun)
 750 {
 751         RTS51X_DEBUGP("eject card\n");
 752         RTS51X_SET_STAT(chip, STAT_RUN);
 753         do_remaining_work(chip);
 754
 755         if ((chip->card_ready & chip->lun2card[lun]) == SD_CARD) {
 756                 release_sd_card(chip);
 757                 chip->card_ejected |= SD_CARD;
 758                 chip->card_ready &= ~SD_CARD;
 759                 chip->capacity[lun] = 0;
 760         } else if ((chip->card_ready & chip->lun2card[lun]) == XD_CARD) {
 761                 release_xd_card(chip);
 762                 chip->card_ejected |= XD_CARD;
 763                 chip->card_ready &= ~XD_CARD;
 764                 chip->capacity[lun] = 0;
 765         } else if ((chip->card_ready & chip->lun2card[lun]) == MS_CARD) {
 766                 release_ms_card(chip);
 767                 chip->card_ejected |= MS_CARD;
 768                 chip->card_ready &= ~MS_CARD;
 769                 chip->capacity[lun] = 0;
 770         }
 771         rts51x_write_register(chip, CARD_INT_PEND, XD_INT | MS_INT | SD_INT,
 772                               XD_INT | MS_INT | SD_INT);
 773 }
 774
 775 void trans_dma_enable(enum dma_data_direction dir, struct rts51x_chip *chip,
 776                       u32 byte_cnt, u8 pack_size)
 777 {
 778         if (pack_size > DMA_1024)
 779                 pack_size = DMA_512;
 780
 781         rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,
 782                        RING_BUFFER);
 783
 784         rts51x_add_cmd(chip, WRITE_REG_CMD, MC_DMA_TC3, 0xFF,
 785                        (u8) (byte_cnt >> 24));
 786         rts51x_add_cmd(chip, WRITE_REG_CMD, MC_DMA_TC2, 0xFF,
 787                        (u8) (byte_cnt >> 16));
 788         rts51x_add_cmd(chip, WRITE_REG_CMD, MC_DMA_TC1, 0xFF,
 789                        (u8) (byte_cnt >> 8));
 790         rts51x_add_cmd(chip, WRITE_REG_CMD, MC_DMA_TC0, 0xFF, (u8) byte_cnt);
 791
 792         if (dir == DMA_FROM_DEVICE) {
 793                 rts51x_add_cmd(chip, WRITE_REG_CMD, MC_DMA_CTL,
 794                                0x03 | DMA_PACK_SIZE_MASK,
 795                                DMA_DIR_FROM_CARD | DMA_EN | pack_size);
 796         } else {
 797                 rts51x_add_cmd(chip, WRITE_REG_CMD, MC_DMA_CTL,
 798                                0x03 | DMA_PACK_SIZE_MASK,
 799                                DMA_DIR_TO_CARD | DMA_EN | pack_size);
 800         }
 801 }
 802
 803 int enable_card_clock(struct rts51x_chip *chip, u8 card)
 804 {
 805         u8 clk_en = 0;
 806
 807         if (card & XD_CARD)
 808                 clk_en |= XD_CLK_EN;
 809         if (card & SD_CARD)
 810                 clk_en |= SD_CLK_EN;
 811         if (card & MS_CARD)
 812                 clk_en |= MS_CLK_EN;
 813
 814         RTS51X_WRITE_REG(chip, CARD_CLK_EN, clk_en, clk_en);
 815
 816         return STATUS_SUCCESS;
 817 }
 818
 819 int disable_card_clock(struct rts51x_chip *chip, u8 card)
 820 {
 821         u8 clk_en = 0;
 822
 823         if (card & XD_CARD)
 824                 clk_en |= XD_CLK_EN;
 825         if (card & SD_CARD)
 826                 clk_en |= SD_CLK_EN;
 827         if (card & MS_CARD)
 828                 clk_en |= MS_CLK_EN;
 829
 830         RTS51X_WRITE_REG(chip, CARD_CLK_EN, clk_en, 0);
 831
 832         return STATUS_SUCCESS;
 833 }
 834
 835 int card_power_on(struct rts51x_chip *chip, u8 card)
 836 {
 837         u8 mask, val1, val2;
 838
 839         mask = POWER_MASK;
 840         val1 = PARTIAL_POWER_ON;
 841         val2 = POWER_ON;
 842
 843 #ifdef SD_XD_IO_FOLLOW_PWR
 844         if ((card == SD_CARD) || (card == XD_CARD)) {
 845                 RTS51X_WRITE_REG(chip, CARD_PWR_CTL, mask | LDO3318_PWR_MASK,
 846                                  val1 | LDO_SUSPEND);
 847                 /* RTS51X_WRITE_REG(chip, CARD_PWR_CTL,
 848                                 LDO3318_PWR_MASK, LDO_SUSPEND); */
 849         }
 850         /* else if(card==XD_CARD)
 851         {
 852                 RTS51X_WRITE_REG(chip, CARD_PWR_CTL,
 853                         mask|LDO3318_PWR_MASK, val1|LDO_SUSPEND);
 854                 //RTS51X_WRITE_REG(chip, CARD_PWR_CTL,
 855                 //      LDO3318_PWR_MASK, LDO_SUSPEND);
 856         } */
 857         else {
 858 #endif
 859                 RTS51X_WRITE_REG(chip, CARD_PWR_CTL, mask, val1);
 860 #ifdef SD_XD_IO_FOLLOW_PWR
 861         }
 862 #endif
 863         udelay(chip->option.pwr_delay);
 864         RTS51X_WRITE_REG(chip, CARD_PWR_CTL, mask, val2);
 865 #ifdef SD_XD_IO_FOLLOW_PWR
 866         if (card == SD_CARD) {
 867                 rts51x_write_register(chip, CARD_PWR_CTL, LDO3318_PWR_MASK,
 868                                       LDO_ON);
 869         }
 870 #endif
 871
 872         return STATUS_SUCCESS;
 873 }
 874
 875 int card_power_off(struct rts51x_chip *chip, u8 card)
 876 {
 877         u8 mask, val;
 878
 879         mask = POWER_MASK;
 880         val = POWER_OFF;
 881         RTS51X_WRITE_REG(chip, CARD_PWR_CTL, mask, val);
 882
 883         return STATUS_SUCCESS;
 884 }
 885
 886 int monitor_card_cd(struct rts51x_chip *chip, u8 card)
 887 {
 888         int retval;
 889         u8 card_cd[32] = { 0 };
 890
 891         card_cd[SD_CARD] = SD_CD;
 892         card_cd[XD_CARD] = XD_CD;
 893         card_cd[MS_CARD] = MS_CD;
 894
 895         retval = rts51x_get_card_status(chip, &(chip->card_status));
 896         if (retval != STATUS_SUCCESS)
 897                 return CD_NOT_EXIST;
 898
 899         if (chip->card_status & card_cd[card])
 900                 return CD_EXIST;
 901
 902         return CD_NOT_EXIST;
 903 }
 904
 905 int toggle_gpio(struct rts51x_chip *chip, u8 gpio)
 906 {
 907         int retval;
 908         u8 temp_reg;
 909         u8 gpio_output[4] = {
 910                 0x01,
 911         };
 912         u8 gpio_oe[4] = {
 913                 0x02,
 914         };
 915         if (chip->rts5179) {
 916                 retval = rts51x_ep0_read_register(chip, CARD_GPIO, &temp_reg);
 917                 if (retval != STATUS_SUCCESS)
 918                         TRACE_RET(chip, STATUS_FAIL);
 919                 temp_reg ^= gpio_oe[gpio];
 920                 temp_reg &= 0xfe; /* bit 0 always set 0 */
 921                 retval =
 922                     rts51x_ep0_write_register(chip, CARD_GPIO, 0x03, temp_reg);
 923                 if (retval != STATUS_SUCCESS)
 924                         TRACE_RET(chip, STATUS_FAIL);
 925         } else {
 926                 retval = rts51x_ep0_read_register(chip, CARD_GPIO, &temp_reg);
 927                 if (retval != STATUS_SUCCESS)
 928                         TRACE_RET(chip, STATUS_FAIL);
 929                 temp_reg ^= gpio_output[gpio];
 930                 retval =
 931                     rts51x_ep0_write_register(chip, CARD_GPIO, 0xFF,
 932                                               temp_reg | gpio_oe[gpio]);
 933                 if (retval != STATUS_SUCCESS)
 934                         TRACE_RET(chip, STATUS_FAIL);
 935         }
 936
 937         return STATUS_SUCCESS;
 938 }
 939
 940 int turn_on_led(struct rts51x_chip *chip, u8 gpio)
 941 {
 942         int retval;
 943         u8 gpio_oe[4] = {
 944                 0x02,
 945         };
 946         u8 gpio_mask[4] = {
 947                 0x03,
 948         };
 949
 950         retval =
 951             rts51x_ep0_write_register(chip, CARD_GPIO, gpio_mask[gpio],
 952                                       gpio_oe[gpio]);
 953         if (retval != STATUS_SUCCESS)
 954                 TRACE_RET(chip, STATUS_FAIL);
 955
 956         return STATUS_SUCCESS;
 957 }
 958
 959 int turn_off_led(struct rts51x_chip *chip, u8 gpio)
 960 {
 961         int retval;
 962         u8 gpio_output[4] = {
 963                 0x01,
 964         };
 965         u8 gpio_oe[4] = {
 966                 0x02,
 967         };
 968         u8 gpio_mask[4] = {
 969                 0x03,
 970         };
 971
 972         retval =
 973             rts51x_ep0_write_register(chip, CARD_GPIO, gpio_mask[gpio],
 974                                       gpio_oe[gpio] | gpio_output[gpio]);
 975         if (retval != STATUS_SUCCESS)
 976                 TRACE_RET(chip, STATUS_FAIL);
 977
 978         return STATUS_SUCCESS;
 979 }