1 /* Driver for Realtek RTS51xx USB card reader
3 * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
19 * wwang (wei_wang@realsil.com.cn)
20 * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
22 * Edwin Rong (edwin_rong@realsil.com.cn)
23 * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
26 #include <linux/blkdev.h>
27 #include <linux/kthread.h>
28 #include <linux/sched.h>
29 #include <linux/workqueue.h>
31 #include <scsi/scsi.h>
32 #include <scsi/scsi_eh.h>
33 #include <scsi/scsi_device.h>
37 #include "rts51x_chip.h"
38 #include "rts51x_card.h"
39 #include "rts51x_transport.h"
44 void do_remaining_work(struct rts51x_chip *chip)
46 struct sd_info *sd_card = &(chip->sd_card);
47 struct xd_info *xd_card = &(chip->xd_card);
48 struct ms_info *ms_card = &(chip->ms_card);
50 if (chip->card_ready & SD_CARD) {
51 if (sd_card->seq_mode) {
52 RTS51X_SET_STAT(chip, STAT_RUN);
59 if (chip->card_ready & XD_CARD) {
60 if (xd_card->delay_write.delay_write_flag) {
61 RTS51X_SET_STAT(chip, STAT_RUN);
68 if (chip->card_ready & MS_CARD) {
69 if (CHK_MSPRO(ms_card)) {
70 if (ms_card->seq_mode) {
71 RTS51X_SET_STAT(chip, STAT_RUN);
77 if (ms_card->delay_write.delay_write_flag) {
78 RTS51X_SET_STAT(chip, STAT_RUN);
86 if (sd_card->counter > POLLING_WAIT_CNT)
87 sd_cleanup_work(chip);
89 if (xd_card->counter > POLLING_WAIT_CNT)
90 xd_cleanup_work(chip);
92 if (ms_card->counter > POLLING_WAIT_CNT)
93 ms_cleanup_work(chip);
96 static void do_reset_xd_card(struct rts51x_chip *chip)
100 if (chip->card2lun[XD_CARD] >= MAX_ALLOWED_LUN_CNT)
103 retval = reset_xd_card(chip);
104 if (retval == STATUS_SUCCESS) {
105 chip->card_ready |= XD_CARD;
106 chip->card_fail &= ~XD_CARD;
107 chip->rw_card[chip->card2lun[XD_CARD]] = xd_rw;
109 chip->card_ready &= ~XD_CARD;
110 chip->card_fail |= XD_CARD;
111 chip->capacity[chip->card2lun[XD_CARD]] = 0;
112 chip->rw_card[chip->card2lun[XD_CARD]] = NULL;
114 rts51x_init_cmd(chip);
115 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_OE, XD_OUTPUT_EN, 0);
116 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PWR_CTL, POWER_MASK,
118 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_CLK_EN, XD_CLK_EN, 0);
119 rts51x_send_cmd(chip, MODE_C, 100);
123 void do_reset_sd_card(struct rts51x_chip *chip)
127 if (chip->card2lun[SD_CARD] >= MAX_ALLOWED_LUN_CNT)
130 retval = reset_sd_card(chip);
131 if (retval == STATUS_SUCCESS) {
132 chip->card_ready |= SD_CARD;
133 chip->card_fail &= ~SD_CARD;
134 chip->rw_card[chip->card2lun[SD_CARD]] = sd_rw;
136 chip->card_ready &= ~SD_CARD;
137 chip->card_fail |= SD_CARD;
138 chip->capacity[chip->card2lun[SD_CARD]] = 0;
139 chip->rw_card[chip->card2lun[SD_CARD]] = NULL;
141 rts51x_init_cmd(chip);
142 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_OE, SD_OUTPUT_EN, 0);
143 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PWR_CTL, POWER_MASK,
145 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_CLK_EN, SD_CLK_EN, 0);
146 rts51x_send_cmd(chip, MODE_C, 100);
150 static void do_reset_ms_card(struct rts51x_chip *chip)
154 if (chip->card2lun[MS_CARD] >= MAX_ALLOWED_LUN_CNT)
157 retval = reset_ms_card(chip);
158 if (retval == STATUS_SUCCESS) {
159 chip->card_ready |= MS_CARD;
160 chip->card_fail &= ~MS_CARD;
161 chip->rw_card[chip->card2lun[MS_CARD]] = ms_rw;
163 chip->card_ready &= ~MS_CARD;
164 chip->card_fail |= MS_CARD;
165 chip->capacity[chip->card2lun[MS_CARD]] = 0;
166 chip->rw_card[chip->card2lun[MS_CARD]] = NULL;
168 rts51x_init_cmd(chip);
169 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_OE, MS_OUTPUT_EN, 0);
170 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PWR_CTL, POWER_MASK,
172 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_CLK_EN, MS_CLK_EN, 0);
173 rts51x_send_cmd(chip, MODE_C, 100);
177 static void card_cd_debounce(struct rts51x_chip *chip, u8 *need_reset,
181 u8 release_map = 0, reset_map = 0;
184 retval = rts51x_get_card_status(chip, &(chip->card_status));
186 chip->ocp_stat = (chip->card_status >> 4) & 0x03;
189 if (retval != STATUS_SUCCESS)
192 if (chip->card_exist) {
193 retval = rts51x_read_register(chip, CARD_INT_PEND, &value);
194 if (retval != STATUS_SUCCESS) {
195 rts51x_ep0_write_register(chip, MC_FIFO_CTL, FIFO_FLUSH,
197 rts51x_ep0_write_register(chip, SFSM_ED, 0xf8, 0xf8);
201 if (chip->card_exist & XD_CARD) {
202 if (!(chip->card_status & XD_CD))
203 release_map |= XD_CARD;
204 } else if (chip->card_exist & SD_CARD) {
205 /* if (!(chip->card_status & SD_CD)) { */
206 if (!(chip->card_status & SD_CD) || (value & SD_INT))
207 release_map |= SD_CARD;
208 } else if (chip->card_exist & MS_CARD) {
209 /* if (!(chip->card_status & MS_CD)) { */
210 if (!(chip->card_status & MS_CD) || (value & MS_INT))
211 release_map |= MS_CARD;
214 if (chip->card_status & XD_CD) {
215 reset_map |= XD_CARD;
216 } else if (chip->card_status & SD_CD) {
217 reset_map |= SD_CARD;
218 } else if (chip->card_status & MS_CD) {
219 reset_map |= MS_CARD;
223 if (CHECK_PKG(chip, QFN24) && reset_map) {
224 if (chip->card_exist & XD_CARD) {
231 int xd_cnt = 0, sd_cnt = 0, ms_cnt = 0;
234 for (i = 0; i < (chip->option.debounce_num); i++) {
236 rts51x_get_card_status(chip, &(chip->card_status));
237 if (retval != STATUS_SUCCESS) {
238 reset_map = release_map = 0;
241 if (chip->card_status & XD_CD)
245 if (chip->card_status & SD_CD)
249 if (chip->card_status & MS_CD)
257 if (!(chip->card_exist & XD_CARD)
258 && (xd_cnt > (chip->option.debounce_num - 1))) {
259 reset_map |= XD_CARD;
261 if (!(chip->card_exist & SD_CARD)
262 && (sd_cnt > (chip->option.debounce_num - 1))) {
263 reset_map |= SD_CARD;
265 if (!(chip->card_exist & MS_CARD)
266 && (ms_cnt > (chip->option.debounce_num - 1))) {
267 reset_map |= MS_CARD;
270 rts51x_write_register(chip, CARD_INT_PEND, XD_INT | MS_INT | SD_INT,
271 XD_INT | MS_INT | SD_INT);
275 *need_reset = reset_map;
277 *need_release = release_map;
280 void rts51x_init_cards(struct rts51x_chip *chip)
282 u8 need_reset = 0, need_release = 0;
284 card_cd_debounce(chip, &need_reset, &need_release);
287 RTS51X_DEBUGP("need_release = 0x%x\n", need_release);
289 rts51x_prepare_run(chip);
290 RTS51X_SET_STAT(chip, STAT_RUN);
293 if (chip->ocp_stat & (MS_OCP_NOW | MS_OCP_EVER)) {
294 rts51x_write_register(chip, OCPCTL, MS_OCP_CLEAR,
297 RTS51X_DEBUGP("Clear OCP status.\n");
301 if (need_release & XD_CARD) {
302 chip->card_exist &= ~XD_CARD;
303 chip->card_ejected = 0;
304 if (chip->card_ready & XD_CARD) {
305 release_xd_card(chip);
306 chip->rw_card[chip->card2lun[XD_CARD]] = NULL;
307 clear_bit(chip->card2lun[XD_CARD],
312 if (need_release & SD_CARD) {
313 chip->card_exist &= ~SD_CARD;
314 chip->card_ejected = 0;
315 if (chip->card_ready & SD_CARD) {
316 release_sd_card(chip);
317 chip->rw_card[chip->card2lun[SD_CARD]] = NULL;
318 clear_bit(chip->card2lun[SD_CARD],
323 if (need_release & MS_CARD) {
324 chip->card_exist &= ~MS_CARD;
325 chip->card_ejected = 0;
326 if (chip->card_ready & MS_CARD) {
327 release_ms_card(chip);
328 chip->rw_card[chip->card2lun[MS_CARD]] = NULL;
329 clear_bit(chip->card2lun[MS_CARD],
335 if (need_reset && !chip->card_ready) {
336 RTS51X_DEBUGP("need_reset = 0x%x\n", need_reset);
338 rts51x_prepare_run(chip);
339 RTS51X_SET_STAT(chip, STAT_RUN);
341 if (need_reset & XD_CARD) {
342 chip->card_exist |= XD_CARD;
343 do_reset_xd_card(chip);
344 } else if (need_reset & SD_CARD) {
345 chip->card_exist |= SD_CARD;
346 do_reset_sd_card(chip);
347 } else if (need_reset & MS_CARD) {
348 chip->card_exist |= MS_CARD;
349 do_reset_ms_card(chip);
354 void rts51x_release_cards(struct rts51x_chip *chip)
356 if (chip->card_ready & SD_CARD) {
357 sd_cleanup_work(chip);
358 release_sd_card(chip);
359 chip->card_ready &= ~SD_CARD;
362 if (chip->card_ready & XD_CARD) {
363 xd_cleanup_work(chip);
364 release_xd_card(chip);
365 chip->card_ready &= ~XD_CARD;
368 if (chip->card_ready & MS_CARD) {
369 ms_cleanup_work(chip);
370 release_ms_card(chip);
371 chip->card_ready &= ~MS_CARD;
375 static inline u8 double_depth(u8 depth)
377 return ((depth > 1) ? (depth - 1) : depth);
380 int switch_ssc_clock(struct rts51x_chip *chip, int clk)
382 struct sd_info *sd_card = &(chip->sd_card);
383 struct ms_info *ms_card = &(chip->ms_card);
385 u8 N = (u8) (clk - 2), min_N, max_N;
386 u8 mcu_cnt, div, max_div, ssc_depth;
387 int sd_vpclk_phase_reset = 0;
389 if (chip->cur_clk == clk)
390 return STATUS_SUCCESS;
396 RTS51X_DEBUGP("Switch SSC clock to %dMHz\n", clk);
398 if ((clk <= 2) || (N > max_N))
399 TRACE_RET(chip, STATUS_FAIL);
401 mcu_cnt = (u8) (60 / clk + 3);
404 /* To make sure that the SSC clock div_n is
405 * equal or greater than min_N */
407 while ((N < min_N) && (div < max_div)) {
411 RTS51X_DEBUGP("N = %d, div = %d\n", N, div);
413 if (chip->option.ssc_en) {
414 if (chip->cur_card == SD_CARD) {
415 if (CHK_SD_SDR104(sd_card)) {
416 ssc_depth = chip->option.ssc_depth_sd_sdr104;
417 } else if (CHK_SD_SDR50(sd_card)) {
418 ssc_depth = chip->option.ssc_depth_sd_sdr50;
419 } else if (CHK_SD_DDR50(sd_card)) {
421 double_depth(chip->option.
423 } else if (CHK_SD_HS(sd_card)) {
425 double_depth(chip->option.ssc_depth_sd_hs);
426 } else if (CHK_MMC_52M(sd_card)
427 || CHK_MMC_DDR52(sd_card)) {
429 double_depth(chip->option.
433 double_depth(chip->option.
434 ssc_depth_low_speed);
436 } else if (chip->cur_card == MS_CARD) {
437 if (CHK_MSPRO(ms_card)) {
438 if (CHK_HG8BIT(ms_card)) {
440 double_depth(chip->option.
444 double_depth(chip->option.
448 if (CHK_MS4BIT(ms_card)) {
450 double_depth(chip->option.
454 double_depth(chip->option.
455 ssc_depth_low_speed);
460 double_depth(chip->option.ssc_depth_low_speed);
464 if (div == CLK_DIV_2) {
465 /* If clock divided by 2, ssc depth must
466 * be multiplied by 2 */
470 ssc_depth = SSC_DEPTH_2M;
471 } else if (div == CLK_DIV_4) {
472 /* If clock divided by 4, ssc depth must
473 * be multiplied by 4 */
477 ssc_depth = SSC_DEPTH_2M;
485 RTS51X_DEBUGP("ssc_depth = %d\n", ssc_depth);
487 rts51x_init_cmd(chip);
488 rts51x_add_cmd(chip, WRITE_REG_CMD, CLK_DIV, CLK_CHANGE, CLK_CHANGE);
489 rts51x_add_cmd(chip, WRITE_REG_CMD, CLK_DIV, 0x3F,
490 (div << 4) | mcu_cnt);
491 rts51x_add_cmd(chip, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0);
492 rts51x_add_cmd(chip, WRITE_REG_CMD, SSC_CTL2, SSC_DEPTH_MASK,
494 rts51x_add_cmd(chip, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, N);
495 if (sd_vpclk_phase_reset) {
496 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_VPCLK0_CTL,
498 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_VPCLK0_CTL,
499 PHASE_NOT_RESET, PHASE_NOT_RESET);
502 retval = rts51x_send_cmd(chip, MODE_C, 2000);
503 if (retval != STATUS_SUCCESS)
504 TRACE_RET(chip, retval);
505 if (chip->option.ssc_en && ssc_depth)
506 rts51x_write_register(chip, SSC_CTL1, 0xff, 0xD0);
508 rts51x_write_register(chip, SSC_CTL1, 0xff, 0x50);
510 RTS51X_WRITE_REG(chip, CLK_DIV, CLK_CHANGE, 0);
514 return STATUS_SUCCESS;
517 int switch_normal_clock(struct rts51x_chip *chip, int clk)
520 u8 sel, div, mcu_cnt;
521 int sd_vpclk_phase_reset = 0;
523 if (chip->cur_clk == clk)
524 return STATUS_SUCCESS;
526 if (chip->cur_card == SD_CARD) {
527 struct sd_info *sd_card = &(chip->sd_card);
528 if (CHK_SD30_SPEED(sd_card) || CHK_MMC_DDR52(sd_card))
529 sd_vpclk_phase_reset = 1;
534 RTS51X_DEBUGP("Switch clock to 20MHz\n");
541 RTS51X_DEBUGP("Switch clock to 30MHz\n");
548 RTS51X_DEBUGP("Switch clock to 40MHz\n");
555 RTS51X_DEBUGP("Switch clock to 50MHz\n");
562 RTS51X_DEBUGP("Switch clock to 60MHz\n");
569 RTS51X_DEBUGP("Switch clock to 80MHz\n");
576 RTS51X_DEBUGP("Switch clock to 100MHz\n");
583 RTS51X_DEBUGP("Switch clock to 120MHz\n");
590 RTS51X_DEBUGP("Switch clock to 150MHz\n");
597 RTS51X_DEBUGP("Try to switch to an illegal clock (%d)\n",
599 TRACE_RET(chip, STATUS_FAIL);
602 if (!sd_vpclk_phase_reset) {
603 rts51x_init_cmd(chip);
605 rts51x_add_cmd(chip, WRITE_REG_CMD, CLK_DIV, CLK_CHANGE,
607 rts51x_add_cmd(chip, WRITE_REG_CMD, CLK_DIV, 0x3F,
608 (div << 4) | mcu_cnt);
609 rts51x_add_cmd(chip, WRITE_REG_CMD, SSC_CLK_FPGA_SEL, 0xFF,
611 rts51x_add_cmd(chip, WRITE_REG_CMD, CLK_DIV, CLK_CHANGE, 0);
613 retval = rts51x_send_cmd(chip, MODE_C, 100);
614 if (retval != STATUS_SUCCESS)
615 TRACE_RET(chip, retval);
617 rts51x_init_cmd(chip);
619 rts51x_add_cmd(chip, WRITE_REG_CMD, CLK_DIV, CLK_CHANGE,
621 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_VPCLK0_CTL,
623 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_VPCLK1_CTL,
625 rts51x_add_cmd(chip, WRITE_REG_CMD, CLK_DIV, 0x3F,
626 (div << 4) | mcu_cnt);
627 rts51x_add_cmd(chip, WRITE_REG_CMD, SSC_CLK_FPGA_SEL, 0xFF,
630 retval = rts51x_send_cmd(chip, MODE_C, 100);
631 if (retval != STATUS_SUCCESS)
632 TRACE_RET(chip, retval);
636 rts51x_init_cmd(chip);
638 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_VPCLK0_CTL,
639 PHASE_NOT_RESET, PHASE_NOT_RESET);
640 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_VPCLK1_CTL,
641 PHASE_NOT_RESET, PHASE_NOT_RESET);
643 retval = rts51x_send_cmd(chip, MODE_C, 100);
644 if (retval != STATUS_SUCCESS)
645 TRACE_RET(chip, retval);
649 RTS51X_WRITE_REG(chip, CLK_DIV, CLK_CHANGE, 0);
654 return STATUS_SUCCESS;
657 int card_rw(struct scsi_cmnd *srb, struct rts51x_chip *chip, u32 sec_addr,
661 unsigned int lun = SCSI_LUN(srb);
664 if (chip->rw_card[lun] == NULL)
667 RTS51X_DEBUGP("%s card, sector addr: 0x%x, sector cnt: %d\n",
668 (srb->sc_data_direction ==
669 DMA_TO_DEVICE) ? "Write" : "Read", sec_addr, sec_cnt);
671 chip->rw_need_retry = 0;
672 for (i = 0; i < 3; i++) {
673 retval = chip->rw_card[lun] (srb, chip, sec_addr, sec_cnt);
674 if (retval != STATUS_SUCCESS) {
676 if (chip->option.reset_or_rw_fail_set_pad_drive) {
677 rts51x_write_register(chip, CARD_DRIVE_SEL,
683 if (!chip->rw_need_retry)
686 RTS51X_DEBUGP("Retry RW, (i = %d\n)", i);
692 u8 get_lun_card(struct rts51x_chip *chip, unsigned int lun)
694 if ((chip->card_ready & chip->lun2card[lun]) == XD_CARD)
696 else if ((chip->card_ready & chip->lun2card[lun]) == SD_CARD)
698 else if ((chip->card_ready & chip->lun2card[lun]) == MS_CARD)
704 static int card_share_mode(struct rts51x_chip *chip, int card)
709 value = CARD_SHARE_SD;
710 else if (card == MS_CARD)
711 value = CARD_SHARE_MS;
712 else if (card == XD_CARD)
713 value = CARD_SHARE_XD;
715 TRACE_RET(chip, STATUS_FAIL);
717 RTS51X_WRITE_REG(chip, CARD_SHARE_MODE, CARD_SHARE_MASK, value);
719 return STATUS_SUCCESS;
722 int rts51x_select_card(struct rts51x_chip *chip, int card)
726 if (chip->cur_card != card) {
731 else if (card == MS_CARD)
733 else if (card == XD_CARD)
736 TRACE_RET(chip, STATUS_FAIL);
737 RTS51X_WRITE_REG(chip, CARD_SELECT, 0x07, mod);
738 chip->cur_card = card;
740 retval = card_share_mode(chip, card);
741 if (retval != STATUS_SUCCESS)
742 TRACE_RET(chip, retval);
745 return STATUS_SUCCESS;
748 void eject_card(struct rts51x_chip *chip, unsigned int lun)
750 RTS51X_DEBUGP("eject card\n");
751 RTS51X_SET_STAT(chip, STAT_RUN);
752 do_remaining_work(chip);
754 if ((chip->card_ready & chip->lun2card[lun]) == SD_CARD) {
755 release_sd_card(chip);
756 chip->card_ejected |= SD_CARD;
757 chip->card_ready &= ~SD_CARD;
758 chip->capacity[lun] = 0;
759 } else if ((chip->card_ready & chip->lun2card[lun]) == XD_CARD) {
760 release_xd_card(chip);
761 chip->card_ejected |= XD_CARD;
762 chip->card_ready &= ~XD_CARD;
763 chip->capacity[lun] = 0;
764 } else if ((chip->card_ready & chip->lun2card[lun]) == MS_CARD) {
765 release_ms_card(chip);
766 chip->card_ejected |= MS_CARD;
767 chip->card_ready &= ~MS_CARD;
768 chip->capacity[lun] = 0;
770 rts51x_write_register(chip, CARD_INT_PEND, XD_INT | MS_INT | SD_INT,
771 XD_INT | MS_INT | SD_INT);
774 void trans_dma_enable(enum dma_data_direction dir, struct rts51x_chip *chip,
775 u32 byte_cnt, u8 pack_size)
777 if (pack_size > DMA_1024)
780 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,
783 rts51x_add_cmd(chip, WRITE_REG_CMD, MC_DMA_TC3, 0xFF,
784 (u8) (byte_cnt >> 24));
785 rts51x_add_cmd(chip, WRITE_REG_CMD, MC_DMA_TC2, 0xFF,
786 (u8) (byte_cnt >> 16));
787 rts51x_add_cmd(chip, WRITE_REG_CMD, MC_DMA_TC1, 0xFF,
788 (u8) (byte_cnt >> 8));
789 rts51x_add_cmd(chip, WRITE_REG_CMD, MC_DMA_TC0, 0xFF, (u8) byte_cnt);
791 if (dir == DMA_FROM_DEVICE) {
792 rts51x_add_cmd(chip, WRITE_REG_CMD, MC_DMA_CTL,
793 0x03 | DMA_PACK_SIZE_MASK,
794 DMA_DIR_FROM_CARD | DMA_EN | pack_size);
796 rts51x_add_cmd(chip, WRITE_REG_CMD, MC_DMA_CTL,
797 0x03 | DMA_PACK_SIZE_MASK,
798 DMA_DIR_TO_CARD | DMA_EN | pack_size);
802 int enable_card_clock(struct rts51x_chip *chip, u8 card)
813 RTS51X_WRITE_REG(chip, CARD_CLK_EN, clk_en, clk_en);
815 return STATUS_SUCCESS;
818 int disable_card_clock(struct rts51x_chip *chip, u8 card)
829 RTS51X_WRITE_REG(chip, CARD_CLK_EN, clk_en, 0);
831 return STATUS_SUCCESS;
834 int card_power_on(struct rts51x_chip *chip, u8 card)
839 val1 = PARTIAL_POWER_ON;
842 #ifdef SD_XD_IO_FOLLOW_PWR
843 if ((card == SD_CARD) || (card == XD_CARD)) {
844 RTS51X_WRITE_REG(chip, CARD_PWR_CTL, mask | LDO3318_PWR_MASK,
846 /* RTS51X_WRITE_REG(chip, CARD_PWR_CTL,
847 LDO3318_PWR_MASK, LDO_SUSPEND); */
849 /* else if(card==XD_CARD)
851 RTS51X_WRITE_REG(chip, CARD_PWR_CTL,
852 mask|LDO3318_PWR_MASK, val1|LDO_SUSPEND);
853 //RTS51X_WRITE_REG(chip, CARD_PWR_CTL,
854 // LDO3318_PWR_MASK, LDO_SUSPEND);
858 RTS51X_WRITE_REG(chip, CARD_PWR_CTL, mask, val1);
859 #ifdef SD_XD_IO_FOLLOW_PWR
862 udelay(chip->option.pwr_delay);
863 RTS51X_WRITE_REG(chip, CARD_PWR_CTL, mask, val2);
864 #ifdef SD_XD_IO_FOLLOW_PWR
865 if (card == SD_CARD) {
866 rts51x_write_register(chip, CARD_PWR_CTL, LDO3318_PWR_MASK,
871 return STATUS_SUCCESS;
874 int card_power_off(struct rts51x_chip *chip, u8 card)
880 RTS51X_WRITE_REG(chip, CARD_PWR_CTL, mask, val);
882 return STATUS_SUCCESS;
885 int monitor_card_cd(struct rts51x_chip *chip, u8 card)
888 u8 card_cd[32] = { 0 };
890 card_cd[SD_CARD] = SD_CD;
891 card_cd[XD_CARD] = XD_CD;
892 card_cd[MS_CARD] = MS_CD;
894 retval = rts51x_get_card_status(chip, &(chip->card_status));
895 if (retval != STATUS_SUCCESS)
898 if (chip->card_status & card_cd[card])
904 int toggle_gpio(struct rts51x_chip *chip, u8 gpio)
908 u8 gpio_output[4] = {
915 retval = rts51x_ep0_read_register(chip, CARD_GPIO, &temp_reg);
916 if (retval != STATUS_SUCCESS)
917 TRACE_RET(chip, STATUS_FAIL);
918 temp_reg ^= gpio_oe[gpio];
919 temp_reg &= 0xfe; /* bit 0 always set 0 */
921 rts51x_ep0_write_register(chip, CARD_GPIO, 0x03, temp_reg);
922 if (retval != STATUS_SUCCESS)
923 TRACE_RET(chip, STATUS_FAIL);
925 retval = rts51x_ep0_read_register(chip, CARD_GPIO, &temp_reg);
926 if (retval != STATUS_SUCCESS)
927 TRACE_RET(chip, STATUS_FAIL);
928 temp_reg ^= gpio_output[gpio];
930 rts51x_ep0_write_register(chip, CARD_GPIO, 0xFF,
931 temp_reg | gpio_oe[gpio]);
932 if (retval != STATUS_SUCCESS)
933 TRACE_RET(chip, STATUS_FAIL);
936 return STATUS_SUCCESS;
939 int turn_on_led(struct rts51x_chip *chip, u8 gpio)
950 rts51x_ep0_write_register(chip, CARD_GPIO, gpio_mask[gpio],
952 if (retval != STATUS_SUCCESS)
953 TRACE_RET(chip, STATUS_FAIL);
955 return STATUS_SUCCESS;
958 int turn_off_led(struct rts51x_chip *chip, u8 gpio)
961 u8 gpio_output[4] = {
972 rts51x_ep0_write_register(chip, CARD_GPIO, gpio_mask[gpio],
973 gpio_oe[gpio] | gpio_output[gpio]);
974 if (retval != STATUS_SUCCESS)
975 TRACE_RET(chip, STATUS_FAIL);
977 return STATUS_SUCCESS;