Pileus Git - ~andy/linux/blob - drivers/staging/rts5139/rts51x_card.c

   1 /* Driver for Realtek RTS51xx USB card reader
   2  *
   3  * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License as published by the
   7  * Free Software Foundation; either version 2, or (at your option) any
   8  * later version.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program; if not, see <http://www.gnu.org/licenses/>.
  17  *
  18  * Author:
  19  *   wwang (wei_wang@realsil.com.cn)
  20  *   No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
  21  * Maintainer:
  22  *   Edwin Rong (edwin_rong@realsil.com.cn)
  23  *   No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
  24  */
  25
  26 #include <linux/blkdev.h>
  27 #include <linux/kthread.h>
  28 #include <linux/sched.h>
  29 #include <linux/workqueue.h>
  30
  31 #include <scsi/scsi.h>
  32 #include <scsi/scsi_eh.h>
  33 #include <scsi/scsi_device.h>
  34
  35 #include "debug.h"
  36 #include "rts51x.h"
  37 #include "rts51x_chip.h"
  38 #include "rts51x_card.h"
  39 #include "rts51x_transport.h"
  40 #include "xd.h"
  41 #include "sd.h"
  42 #include "ms.h"
  43
  44 void rts51x_do_remaining_work(struct rts51x_chip *chip)
  45 {
  46         struct sd_info *sd_card = &(chip->sd_card);
  47         struct xd_info *xd_card = &(chip->xd_card);
  48         struct ms_info *ms_card = &(chip->ms_card);
  49
  50         if (chip->card_ready & SD_CARD) {
  51                 if (sd_card->seq_mode) {
  52                         RTS51X_SET_STAT(chip, STAT_RUN);
  53                         sd_card->counter++;
  54                 } else {
  55                         sd_card->counter = 0;
  56                 }
  57         }
  58
  59         if (chip->card_ready & XD_CARD) {
  60                 if (xd_card->delay_write.delay_write_flag) {
  61                         RTS51X_SET_STAT(chip, STAT_RUN);
  62                         xd_card->counter++;
  63                 } else {
  64                         xd_card->counter = 0;
  65                 }
  66         }
  67
  68         if (chip->card_ready & MS_CARD) {
  69                 if (CHK_MSPRO(ms_card)) {
  70                         if (ms_card->seq_mode) {
  71                                 RTS51X_SET_STAT(chip, STAT_RUN);
  72                                 ms_card->counter++;
  73                         } else {
  74                                 ms_card->counter = 0;
  75                         }
  76                 } else {
  77                         if (ms_card->delay_write.delay_write_flag) {
  78                                 RTS51X_SET_STAT(chip, STAT_RUN);
  79                                 ms_card->counter++;
  80                         } else {
  81                                 ms_card->counter = 0;
  82                         }
  83                 }
  84         }
  85
  86         if (sd_card->counter > POLLING_WAIT_CNT)
  87                 rts51x_sd_cleanup_work(chip);
  88
  89         if (xd_card->counter > POLLING_WAIT_CNT)
  90                 rts51x_xd_cleanup_work(chip);
  91
  92         if (ms_card->counter > POLLING_WAIT_CNT)
  93                 rts51x_ms_cleanup_work(chip);
  94 }
  95
  96 static void do_rts51x_reset_xd_card(struct rts51x_chip *chip)
  97 {
  98         int retval;
  99
 100         if (chip->card2lun[XD_CARD] >= MAX_ALLOWED_LUN_CNT)
 101                 return;
 102
 103         retval = rts51x_reset_xd_card(chip);
 104         if (retval == STATUS_SUCCESS) {
 105                 chip->card_ready |= XD_CARD;
 106                 chip->card_fail &= ~XD_CARD;
 107                 chip->rw_card[chip->card2lun[XD_CARD]] = rts51x_xd_rw;
 108         } else {
 109                 chip->card_ready &= ~XD_CARD;
 110                 chip->card_fail |= XD_CARD;
 111                 chip->capacity[chip->card2lun[XD_CARD]] = 0;
 112                 chip->rw_card[chip->card2lun[XD_CARD]] = NULL;
 113
 114                 rts51x_init_cmd(chip);
 115                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_OE, XD_OUTPUT_EN, 0);
 116                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PWR_CTL, POWER_MASK,
 117                                POWER_OFF);
 118                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_CLK_EN, XD_CLK_EN, 0);
 119                 rts51x_send_cmd(chip, MODE_C, 100);
 120         }
 121 }
 122
 123 void rts51x_do_rts51x_reset_sd_card(struct rts51x_chip *chip)
 124 {
 125         int retval;
 126
 127         if (chip->card2lun[SD_CARD] >= MAX_ALLOWED_LUN_CNT)
 128                 return;
 129
 130         retval = rts51x_reset_sd_card(chip);
 131         if (retval == STATUS_SUCCESS) {
 132                 chip->card_ready |= SD_CARD;
 133                 chip->card_fail &= ~SD_CARD;
 134                 chip->rw_card[chip->card2lun[SD_CARD]] = rts51x_sd_rw;
 135         } else {
 136                 chip->card_ready &= ~SD_CARD;
 137                 chip->card_fail |= SD_CARD;
 138                 chip->capacity[chip->card2lun[SD_CARD]] = 0;
 139                 chip->rw_card[chip->card2lun[SD_CARD]] = NULL;
 140
 141                 rts51x_init_cmd(chip);
 142                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_OE, SD_OUTPUT_EN, 0);
 143                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PWR_CTL, POWER_MASK,
 144                                POWER_OFF);
 145                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_CLK_EN, SD_CLK_EN, 0);
 146                 rts51x_send_cmd(chip, MODE_C, 100);
 147         }
 148 }
 149
 150 static void do_rts51x_reset_ms_card(struct rts51x_chip *chip)
 151 {
 152         int retval;
 153
 154         if (chip->card2lun[MS_CARD] >= MAX_ALLOWED_LUN_CNT)
 155                 return;
 156
 157         retval = rts51x_reset_ms_card(chip);
 158         if (retval == STATUS_SUCCESS) {
 159                 chip->card_ready |= MS_CARD;
 160                 chip->card_fail &= ~MS_CARD;
 161                 chip->rw_card[chip->card2lun[MS_CARD]] = rts51x_ms_rw;
 162         } else {
 163                 chip->card_ready &= ~MS_CARD;
 164                 chip->card_fail |= MS_CARD;
 165                 chip->capacity[chip->card2lun[MS_CARD]] = 0;
 166                 chip->rw_card[chip->card2lun[MS_CARD]] = NULL;
 167
 168                 rts51x_init_cmd(chip);
 169                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_OE, MS_OUTPUT_EN, 0);
 170                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PWR_CTL, POWER_MASK,
 171                                POWER_OFF);
 172                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_CLK_EN, MS_CLK_EN, 0);
 173                 rts51x_send_cmd(chip, MODE_C, 100);
 174         }
 175 }
 176
 177 static void card_cd_debounce(struct rts51x_chip *chip, u8 *need_reset,
 178                       u8 *need_release)
 179 {
 180         int retval;
 181         u8 release_map = 0, reset_map = 0;
 182         u8 value;
 183
 184         retval = rts51x_get_card_status(chip, &(chip->card_status));
 185 #ifdef SUPPORT_OCP
 186         chip->ocp_stat = (chip->card_status >> 4) & 0x03;
 187 #endif
 188
 189         if (retval != STATUS_SUCCESS)
 190                 goto Exit_Debounce;
 191
 192         if (chip->card_exist) {
 193                 retval = rts51x_read_register(chip, CARD_INT_PEND, &value);
 194                 if (retval != STATUS_SUCCESS) {
 195                         rts51x_ep0_write_register(chip, MC_FIFO_CTL, FIFO_FLUSH,
 196                                                   FIFO_FLUSH);
 197                         rts51x_ep0_write_register(chip, SFSM_ED, 0xf8, 0xf8);
 198                         value = 0;
 199                 }
 200
 201                 if (chip->card_exist & XD_CARD) {
 202                         if (!(chip->card_status & XD_CD))
 203                                 release_map |= XD_CARD;
 204                 } else if (chip->card_exist & SD_CARD) {
 205                         /* if (!(chip->card_status & SD_CD)) { */
 206                         if (!(chip->card_status & SD_CD) || (value & SD_INT))
 207                                 release_map |= SD_CARD;
 208                 } else if (chip->card_exist & MS_CARD) {
 209                         /* if (!(chip->card_status & MS_CD)) { */
 210                         if (!(chip->card_status & MS_CD) || (value & MS_INT))
 211                                 release_map |= MS_CARD;
 212                 }
 213         } else {
 214                 if (chip->card_status & XD_CD)
 215                         reset_map |= XD_CARD;
 216                 else if (chip->card_status & SD_CD)
 217                         reset_map |= SD_CARD;
 218                 else if (chip->card_status & MS_CD)
 219                         reset_map |= MS_CARD;
 220         }
 221
 222         if (CHECK_PKG(chip, QFN24) && reset_map) {
 223                 if (chip->card_exist & XD_CARD) {
 224                         reset_map = 0;
 225                         goto Exit_Debounce;
 226                 }
 227         }
 228
 229         if (reset_map) {
 230                 int xd_cnt = 0, sd_cnt = 0, ms_cnt = 0;
 231                 int i;
 232
 233                 for (i = 0; i < (chip->option.debounce_num); i++) {
 234                         retval =
 235                             rts51x_get_card_status(chip, &(chip->card_status));
 236                         if (retval != STATUS_SUCCESS) {
 237                                 reset_map = release_map = 0;
 238                                 goto Exit_Debounce;
 239                         }
 240                         if (chip->card_status & XD_CD)
 241                                 xd_cnt++;
 242                         else
 243                                 xd_cnt = 0;
 244                         if (chip->card_status & SD_CD)
 245                                 sd_cnt++;
 246                         else
 247                                 sd_cnt = 0;
 248                         if (chip->card_status & MS_CD)
 249                                 ms_cnt++;
 250                         else
 251                                 ms_cnt = 0;
 252                         wait_timeout(30);
 253                 }
 254
 255                 reset_map = 0;
 256                 if (!(chip->card_exist & XD_CARD)
 257                     && (xd_cnt > (chip->option.debounce_num - 1))) {
 258                         reset_map |= XD_CARD;
 259                 }
 260                 if (!(chip->card_exist & SD_CARD)
 261                     && (sd_cnt > (chip->option.debounce_num - 1))) {
 262                         reset_map |= SD_CARD;
 263                 }
 264                 if (!(chip->card_exist & MS_CARD)
 265                     && (ms_cnt > (chip->option.debounce_num - 1))) {
 266                         reset_map |= MS_CARD;
 267                 }
 268         }
 269         rts51x_write_register(chip, CARD_INT_PEND, XD_INT | MS_INT | SD_INT,
 270                               XD_INT | MS_INT | SD_INT);
 271
 272 Exit_Debounce:
 273         if (need_reset)
 274                 *need_reset = reset_map;
 275         if (need_release)
 276                 *need_release = release_map;
 277 }
 278
 279 void rts51x_init_cards(struct rts51x_chip *chip)
 280 {
 281         u8 need_reset = 0, need_release = 0;
 282
 283         card_cd_debounce(chip, &need_reset, &need_release);
 284
 285         if (need_release) {
 286                 RTS51X_DEBUGP("need_release = 0x%x\n", need_release);
 287
 288                 rts51x_prepare_run(chip);
 289                 RTS51X_SET_STAT(chip, STAT_RUN);
 290
 291 #ifdef SUPPORT_OCP
 292                 if (chip->ocp_stat & (MS_OCP_NOW | MS_OCP_EVER)) {
 293                         rts51x_write_register(chip, OCPCTL, MS_OCP_CLEAR,
 294                                               MS_OCP_CLEAR);
 295                         chip->ocp_stat = 0;
 296                         RTS51X_DEBUGP("Clear OCP status.\n");
 297                 }
 298 #endif
 299
 300                 if (need_release & XD_CARD) {
 301                         chip->card_exist &= ~XD_CARD;
 302                         chip->card_ejected = 0;
 303                         if (chip->card_ready & XD_CARD) {
 304                                 rts51x_release_xd_card(chip);
 305                                 chip->rw_card[chip->card2lun[XD_CARD]] = NULL;
 306                                 clear_bit(chip->card2lun[XD_CARD],
 307                                           &(chip->lun_mc));
 308                         }
 309                 }
 310
 311                 if (need_release & SD_CARD) {
 312                         chip->card_exist &= ~SD_CARD;
 313                         chip->card_ejected = 0;
 314                         if (chip->card_ready & SD_CARD) {
 315                                 rts51x_release_sd_card(chip);
 316                                 chip->rw_card[chip->card2lun[SD_CARD]] = NULL;
 317                                 clear_bit(chip->card2lun[SD_CARD],
 318                                           &(chip->lun_mc));
 319                         }
 320                 }
 321
 322                 if (need_release & MS_CARD) {
 323                         chip->card_exist &= ~MS_CARD;
 324                         chip->card_ejected = 0;
 325                         if (chip->card_ready & MS_CARD) {
 326                                 rts51x_release_ms_card(chip);
 327                                 chip->rw_card[chip->card2lun[MS_CARD]] = NULL;
 328                                 clear_bit(chip->card2lun[MS_CARD],
 329                                           &(chip->lun_mc));
 330                         }
 331                 }
 332         }
 333
 334         if (need_reset && !chip->card_ready) {
 335                 RTS51X_DEBUGP("need_reset = 0x%x\n", need_reset);
 336
 337                 rts51x_prepare_run(chip);
 338                 RTS51X_SET_STAT(chip, STAT_RUN);
 339
 340                 if (need_reset & XD_CARD) {
 341                         chip->card_exist |= XD_CARD;
 342                         do_rts51x_reset_xd_card(chip);
 343                 } else if (need_reset & SD_CARD) {
 344                         chip->card_exist |= SD_CARD;
 345                         rts51x_do_rts51x_reset_sd_card(chip);
 346                 } else if (need_reset & MS_CARD) {
 347                         chip->card_exist |= MS_CARD;
 348                         do_rts51x_reset_ms_card(chip);
 349                 }
 350         }
 351 }
 352
 353 void rts51x_release_cards(struct rts51x_chip *chip)
 354 {
 355         if (chip->card_ready & SD_CARD) {
 356                 rts51x_sd_cleanup_work(chip);
 357                 rts51x_release_sd_card(chip);
 358                 chip->card_ready &= ~SD_CARD;
 359         }
 360
 361         if (chip->card_ready & XD_CARD) {
 362                 rts51x_xd_cleanup_work(chip);
 363                 rts51x_release_xd_card(chip);
 364                 chip->card_ready &= ~XD_CARD;
 365         }
 366
 367         if (chip->card_ready & MS_CARD) {
 368                 rts51x_ms_cleanup_work(chip);
 369                 rts51x_release_ms_card(chip);
 370                 chip->card_ready &= ~MS_CARD;
 371         }
 372 }
 373
 374 static inline u8 double_depth(u8 depth)
 375 {
 376         return (depth > 1) ? (depth - 1) : depth;
 377 }
 378
 379 int rts51x_switch_ssc_clock(struct rts51x_chip *chip, int clk)
 380 {
 381         struct sd_info *sd_card = &(chip->sd_card);
 382         struct ms_info *ms_card = &(chip->ms_card);
 383         int retval;
 384         u8 N = (u8) (clk - 2), min_N, max_N;
 385         u8 mcu_cnt, div, max_div, ssc_depth;
 386         int sd_vpclk_phase_reset = 0;
 387
 388         if (chip->cur_clk == clk)
 389                 return STATUS_SUCCESS;
 390
 391         min_N = 60;
 392         max_N = 120;
 393         max_div = CLK_DIV_4;
 394
 395         RTS51X_DEBUGP("Switch SSC clock to %dMHz\n", clk);
 396
 397         if ((clk <= 2) || (N > max_N))
 398                 TRACE_RET(chip, STATUS_FAIL);
 399
 400         mcu_cnt = (u8) (60 / clk + 3);
 401         if (mcu_cnt > 15)
 402                 mcu_cnt = 15;
 403         /* To make sure that the SSC clock div_n is
 404          * equal or greater than min_N */
 405         div = CLK_DIV_1;
 406         while ((N < min_N) && (div < max_div)) {
 407                 N = (N + 2) * 2 - 2;
 408                 div++;
 409         }
 410         RTS51X_DEBUGP("N = %d, div = %d\n", N, div);
 411
 412         if (chip->option.ssc_en) {
 413                 if (chip->cur_card == SD_CARD) {
 414                         if (CHK_SD_SDR104(sd_card)) {
 415                                 ssc_depth = chip->option.ssc_depth_sd_sdr104;
 416                         } else if (CHK_SD_SDR50(sd_card)) {
 417                                 ssc_depth = chip->option.ssc_depth_sd_sdr50;
 418                         } else if (CHK_SD_DDR50(sd_card)) {
 419                                 ssc_depth =
 420                                     double_depth(chip->option.
 421                                                  ssc_depth_sd_ddr50);
 422                         } else if (CHK_SD_HS(sd_card)) {
 423                                 ssc_depth =
 424                                     double_depth(chip->option.ssc_depth_sd_hs);
 425                         } else if (CHK_MMC_52M(sd_card)
 426                                    || CHK_MMC_DDR52(sd_card)) {
 427                                 ssc_depth =
 428                                     double_depth(chip->option.
 429                                                  ssc_depth_mmc_52m);
 430                         } else {
 431                                 ssc_depth =
 432                                     double_depth(chip->option.
 433                                                  ssc_depth_low_speed);
 434                         }
 435                 } else if (chip->cur_card == MS_CARD) {
 436                         if (CHK_MSPRO(ms_card)) {
 437                                 if (CHK_HG8BIT(ms_card)) {
 438                                         ssc_depth =
 439                                             double_depth(chip->option.
 440                                                          ssc_depth_ms_hg);
 441                                 } else {
 442                                         ssc_depth =
 443                                             double_depth(chip->option.
 444                                                          ssc_depth_ms_4bit);
 445                                 }
 446                         } else {
 447                                 if (CHK_MS4BIT(ms_card)) {
 448                                         ssc_depth =
 449                                             double_depth(chip->option.
 450                                                          ssc_depth_ms_4bit);
 451                                 } else {
 452                                         ssc_depth =
 453                                             double_depth(chip->option.
 454                                                          ssc_depth_low_speed);
 455                                 }
 456                         }
 457                 } else {
 458                         ssc_depth =
 459                             double_depth(chip->option.ssc_depth_low_speed);
 460                 }
 461
 462                 if (ssc_depth) {
 463                         if (div == CLK_DIV_2) {
 464                                 /* If clock divided by 2, ssc depth must
 465                                  * be multiplied by 2 */
 466                                 if (ssc_depth > 1)
 467                                         ssc_depth -= 1;
 468                                 else
 469                                         ssc_depth = SSC_DEPTH_2M;
 470                         } else if (div == CLK_DIV_4) {
 471                                 /* If clock divided by 4, ssc depth must
 472                                  * be multiplied by 4 */
 473                                 if (ssc_depth > 2)
 474                                         ssc_depth -= 2;
 475                                 else
 476                                         ssc_depth = SSC_DEPTH_2M;
 477                         }
 478                 }
 479         } else {
 480                 /* Disable SSC */
 481                 ssc_depth = 0;
 482         }
 483
 484         RTS51X_DEBUGP("ssc_depth = %d\n", ssc_depth);
 485
 486         rts51x_init_cmd(chip);
 487         rts51x_add_cmd(chip, WRITE_REG_CMD, CLK_DIV, CLK_CHANGE, CLK_CHANGE);
 488         rts51x_add_cmd(chip, WRITE_REG_CMD, CLK_DIV, 0x3F,
 489                        (div << 4) | mcu_cnt);
 490         rts51x_add_cmd(chip, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0);
 491         rts51x_add_cmd(chip, WRITE_REG_CMD, SSC_CTL2, SSC_DEPTH_MASK,
 492                        ssc_depth);
 493         rts51x_add_cmd(chip, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, N);
 494         if (sd_vpclk_phase_reset) {
 495                 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_VPCLK0_CTL,
 496                                PHASE_NOT_RESET, 0);
 497                 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_VPCLK0_CTL,
 498                                PHASE_NOT_RESET, PHASE_NOT_RESET);
 499         }
 500
 501         retval = rts51x_send_cmd(chip, MODE_C, 2000);
 502         if (retval != STATUS_SUCCESS)
 503                 TRACE_RET(chip, retval);
 504         if (chip->option.ssc_en && ssc_depth)
 505                 rts51x_write_register(chip, SSC_CTL1, 0xff, 0xD0);
 506         else
 507                 rts51x_write_register(chip, SSC_CTL1, 0xff, 0x50);
 508         udelay(100);
 509         RTS51X_WRITE_REG(chip, CLK_DIV, CLK_CHANGE, 0);
 510
 511         chip->cur_clk = clk;
 512
 513         return STATUS_SUCCESS;
 514 }
 515
 516 int rts51x_switch_normal_clock(struct rts51x_chip *chip, int clk)
 517 {
 518         int retval;
 519         u8 sel, div, mcu_cnt;
 520         int sd_vpclk_phase_reset = 0;
 521
 522         if (chip->cur_clk == clk)
 523                 return STATUS_SUCCESS;
 524
 525         if (chip->cur_card == SD_CARD) {
 526                 struct sd_info *sd_card = &(chip->sd_card);
 527                 if (CHK_SD30_SPEED(sd_card) || CHK_MMC_DDR52(sd_card))
 528                         sd_vpclk_phase_reset = 1;
 529         }
 530
 531         switch (clk) {
 532         case CLK_20:
 533                 RTS51X_DEBUGP("Switch clock to 20MHz\n");
 534                 sel = SSC_80;
 535                 div = CLK_DIV_4;
 536                 mcu_cnt = 5;
 537                 break;
 538
 539         case CLK_30:
 540                 RTS51X_DEBUGP("Switch clock to 30MHz\n");
 541                 sel = SSC_60;
 542                 div = CLK_DIV_2;
 543                 mcu_cnt = 4;
 544                 break;
 545
 546         case CLK_40:
 547                 RTS51X_DEBUGP("Switch clock to 40MHz\n");
 548                 sel = SSC_80;
 549                 div = CLK_DIV_2;
 550                 mcu_cnt = 3;
 551                 break;
 552
 553         case CLK_50:
 554                 RTS51X_DEBUGP("Switch clock to 50MHz\n");
 555                 sel = SSC_100;
 556                 div = CLK_DIV_2;
 557                 mcu_cnt = 3;
 558                 break;
 559
 560         case CLK_60:
 561                 RTS51X_DEBUGP("Switch clock to 60MHz\n");
 562                 sel = SSC_60;
 563                 div = CLK_DIV_1;
 564                 mcu_cnt = 3;
 565                 break;
 566
 567         case CLK_80:
 568                 RTS51X_DEBUGP("Switch clock to 80MHz\n");
 569                 sel = SSC_80;
 570                 div = CLK_DIV_1;
 571                 mcu_cnt = 2;
 572                 break;
 573
 574         case CLK_100:
 575                 RTS51X_DEBUGP("Switch clock to 100MHz\n");
 576                 sel = SSC_100;
 577                 div = CLK_DIV_1;
 578                 mcu_cnt = 2;
 579                 break;
 580
 581         /* case CLK_120:
 582                 RTS51X_DEBUGP("Switch clock to 120MHz\n");
 583                 sel = SSC_120;
 584                 div = CLK_DIV_1;
 585                 mcu_cnt = 2;
 586                 break;
 587
 588         case CLK_150:
 589                 RTS51X_DEBUGP("Switch clock to 150MHz\n");
 590                 sel = SSC_150;
 591                 div = CLK_DIV_1;
 592                 mcu_cnt = 2;
 593                 break; */
 594
 595         default:
 596                 RTS51X_DEBUGP("Try to switch to an illegal clock (%d)\n",
 597                                clk);
 598                 TRACE_RET(chip, STATUS_FAIL);
 599         }
 600
 601         if (!sd_vpclk_phase_reset) {
 602                 rts51x_init_cmd(chip);
 603
 604                 rts51x_add_cmd(chip, WRITE_REG_CMD, CLK_DIV, CLK_CHANGE,
 605                                CLK_CHANGE);
 606                 rts51x_add_cmd(chip, WRITE_REG_CMD, CLK_DIV, 0x3F,
 607                                (div << 4) | mcu_cnt);
 608                 rts51x_add_cmd(chip, WRITE_REG_CMD, SSC_CLK_FPGA_SEL, 0xFF,
 609                                sel);
 610                 rts51x_add_cmd(chip, WRITE_REG_CMD, CLK_DIV, CLK_CHANGE, 0);
 611
 612                 retval = rts51x_send_cmd(chip, MODE_C, 100);
 613                 if (retval != STATUS_SUCCESS)
 614                         TRACE_RET(chip, retval);
 615         } else {
 616                 rts51x_init_cmd(chip);
 617
 618                 rts51x_add_cmd(chip, WRITE_REG_CMD, CLK_DIV, CLK_CHANGE,
 619                                CLK_CHANGE);
 620                 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_VPCLK0_CTL,
 621                                PHASE_NOT_RESET, 0);
 622                 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_VPCLK1_CTL,
 623                                PHASE_NOT_RESET, 0);
 624                 rts51x_add_cmd(chip, WRITE_REG_CMD, CLK_DIV, 0x3F,
 625                                (div << 4) | mcu_cnt);
 626                 rts51x_add_cmd(chip, WRITE_REG_CMD, SSC_CLK_FPGA_SEL, 0xFF,
 627                                sel);
 628
 629                 retval = rts51x_send_cmd(chip, MODE_C, 100);
 630                 if (retval != STATUS_SUCCESS)
 631                         TRACE_RET(chip, retval);
 632
 633                 udelay(200);
 634
 635                 rts51x_init_cmd(chip);
 636
 637                 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_VPCLK0_CTL,
 638                                PHASE_NOT_RESET, PHASE_NOT_RESET);
 639                 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_VPCLK1_CTL,
 640                                PHASE_NOT_RESET, PHASE_NOT_RESET);
 641
 642                 retval = rts51x_send_cmd(chip, MODE_C, 100);
 643                 if (retval != STATUS_SUCCESS)
 644                         TRACE_RET(chip, retval);
 645
 646                 udelay(200);
 647
 648                 RTS51X_WRITE_REG(chip, CLK_DIV, CLK_CHANGE, 0);
 649         }
 650
 651         chip->cur_clk = clk;
 652
 653         return STATUS_SUCCESS;
 654 }
 655
 656 int rts51x_card_rw(struct scsi_cmnd *srb, struct rts51x_chip *chip,
 657                 u32 sec_addr, u16 sec_cnt)
 658 {
 659         int retval;
 660         unsigned int lun = SCSI_LUN(srb);
 661         int i;
 662
 663         if (chip->rw_card[lun] == NULL)
 664                 return STATUS_FAIL;
 665
 666         RTS51X_DEBUGP("%s card, sector addr: 0x%x, sector cnt: %d\n",
 667                        (srb->sc_data_direction ==
 668                         DMA_TO_DEVICE) ? "Write" : "Read", sec_addr, sec_cnt);
 669
 670         chip->rw_need_retry = 0;
 671         for (i = 0; i < 3; i++) {
 672                 retval = chip->rw_card[lun] (srb, chip, sec_addr, sec_cnt);
 673                 if (retval != STATUS_SUCCESS) {
 674                         CATCH_TRIGGER(chip);
 675                         if (chip->option.reset_or_rw_fail_set_pad_drive) {
 676                                 rts51x_write_register(chip, CARD_DRIVE_SEL,
 677                                                       SD20_DRIVE_MASK,
 678                                                       DRIVE_8mA);
 679                         }
 680                 }
 681
 682                 if (!chip->rw_need_retry)
 683                         break;
 684
 685                 RTS51X_DEBUGP("Retry RW, (i = %d\n)", i);
 686         }
 687
 688         return retval;
 689 }
 690
 691 u8 rts51x_get_lun_card(struct rts51x_chip *chip, unsigned int lun)
 692 {
 693         if ((chip->card_ready & chip->lun2card[lun]) == XD_CARD)
 694                 return (u8) XD_CARD;
 695         else if ((chip->card_ready & chip->lun2card[lun]) == SD_CARD)
 696                 return (u8) SD_CARD;
 697         else if ((chip->card_ready & chip->lun2card[lun]) == MS_CARD)
 698                 return (u8) MS_CARD;
 699
 700         return 0;
 701 }
 702
 703 static int card_share_mode(struct rts51x_chip *chip, int card)
 704 {
 705         u8 value;
 706
 707         if (card == SD_CARD)
 708                 value = CARD_SHARE_SD;
 709         else if (card == MS_CARD)
 710                 value = CARD_SHARE_MS;
 711         else if (card == XD_CARD)
 712                 value = CARD_SHARE_XD;
 713         else
 714                 TRACE_RET(chip, STATUS_FAIL);
 715
 716         RTS51X_WRITE_REG(chip, CARD_SHARE_MODE, CARD_SHARE_MASK, value);
 717
 718         return STATUS_SUCCESS;
 719 }
 720
 721 int rts51x_select_card(struct rts51x_chip *chip, int card)
 722 {
 723         int retval;
 724
 725         if (chip->cur_card != card) {
 726                 u8 mod;
 727
 728                 if (card == SD_CARD)
 729                         mod = SD_MOD_SEL;
 730                 else if (card == MS_CARD)
 731                         mod = MS_MOD_SEL;
 732                 else if (card == XD_CARD)
 733                         mod = XD_MOD_SEL;
 734                 else
 735                         TRACE_RET(chip, STATUS_FAIL);
 736                 RTS51X_WRITE_REG(chip, CARD_SELECT, 0x07, mod);
 737                 chip->cur_card = card;
 738
 739                 retval = card_share_mode(chip, card);
 740                 if (retval != STATUS_SUCCESS)
 741                         TRACE_RET(chip, retval);
 742         }
 743
 744         return STATUS_SUCCESS;
 745 }
 746
 747 void rts51x_eject_card(struct rts51x_chip *chip, unsigned int lun)
 748 {
 749         RTS51X_DEBUGP("eject card\n");
 750         RTS51X_SET_STAT(chip, STAT_RUN);
 751         rts51x_do_remaining_work(chip);
 752
 753         if ((chip->card_ready & chip->lun2card[lun]) == SD_CARD) {
 754                 rts51x_release_sd_card(chip);
 755                 chip->card_ejected |= SD_CARD;
 756                 chip->card_ready &= ~SD_CARD;
 757                 chip->capacity[lun] = 0;
 758         } else if ((chip->card_ready & chip->lun2card[lun]) == XD_CARD) {
 759                 rts51x_release_xd_card(chip);
 760                 chip->card_ejected |= XD_CARD;
 761                 chip->card_ready &= ~XD_CARD;
 762                 chip->capacity[lun] = 0;
 763         } else if ((chip->card_ready & chip->lun2card[lun]) == MS_CARD) {
 764                 rts51x_release_ms_card(chip);
 765                 chip->card_ejected |= MS_CARD;
 766                 chip->card_ready &= ~MS_CARD;
 767                 chip->capacity[lun] = 0;
 768         }
 769         rts51x_write_register(chip, CARD_INT_PEND, XD_INT | MS_INT | SD_INT,
 770                               XD_INT | MS_INT | SD_INT);
 771 }
 772
 773 void rts51x_trans_dma_enable(enum dma_data_direction dir,
 774                 struct rts51x_chip *chip, u32 byte_cnt, u8 pack_size)
 775 {
 776         if (pack_size > DMA_1024)
 777                 pack_size = DMA_512;
 778
 779         rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,
 780                        RING_BUFFER);
 781
 782         rts51x_add_cmd(chip, WRITE_REG_CMD, MC_DMA_TC3, 0xFF,
 783                        (u8) (byte_cnt >> 24));
 784         rts51x_add_cmd(chip, WRITE_REG_CMD, MC_DMA_TC2, 0xFF,
 785                        (u8) (byte_cnt >> 16));
 786         rts51x_add_cmd(chip, WRITE_REG_CMD, MC_DMA_TC1, 0xFF,
 787                        (u8) (byte_cnt >> 8));
 788         rts51x_add_cmd(chip, WRITE_REG_CMD, MC_DMA_TC0, 0xFF, (u8) byte_cnt);
 789
 790         if (dir == DMA_FROM_DEVICE) {
 791                 rts51x_add_cmd(chip, WRITE_REG_CMD, MC_DMA_CTL,
 792                                0x03 | DMA_PACK_SIZE_MASK,
 793                                DMA_DIR_FROM_CARD | DMA_EN | pack_size);
 794         } else {
 795                 rts51x_add_cmd(chip, WRITE_REG_CMD, MC_DMA_CTL,
 796                                0x03 | DMA_PACK_SIZE_MASK,
 797                                DMA_DIR_TO_CARD | DMA_EN | pack_size);
 798         }
 799 }
 800
 801 int rts51x_enable_card_clock(struct rts51x_chip *chip, u8 card)
 802 {
 803         u8 clk_en = 0;
 804
 805         if (card & XD_CARD)
 806                 clk_en |= XD_CLK_EN;
 807         if (card & SD_CARD)
 808                 clk_en |= SD_CLK_EN;
 809         if (card & MS_CARD)
 810                 clk_en |= MS_CLK_EN;
 811
 812         RTS51X_WRITE_REG(chip, CARD_CLK_EN, clk_en, clk_en);
 813
 814         return STATUS_SUCCESS;
 815 }
 816
 817 int rts51x_card_power_on(struct rts51x_chip *chip, u8 card)
 818 {
 819         u8 mask, val1, val2;
 820
 821         mask = POWER_MASK;
 822         val1 = PARTIAL_POWER_ON;
 823         val2 = POWER_ON;
 824
 825 #ifdef SD_XD_IO_FOLLOW_PWR
 826         if ((card == SD_CARD) || (card == XD_CARD)) {
 827                 RTS51X_WRITE_REG(chip, CARD_PWR_CTL, mask | LDO3318_PWR_MASK,
 828                                  val1 | LDO_SUSPEND);
 829         } else {
 830 #endif
 831                 RTS51X_WRITE_REG(chip, CARD_PWR_CTL, mask, val1);
 832 #ifdef SD_XD_IO_FOLLOW_PWR
 833         }
 834 #endif
 835         udelay(chip->option.pwr_delay);
 836         RTS51X_WRITE_REG(chip, CARD_PWR_CTL, mask, val2);
 837 #ifdef SD_XD_IO_FOLLOW_PWR
 838         if (card == SD_CARD) {
 839                 rts51x_write_register(chip, CARD_PWR_CTL, LDO3318_PWR_MASK,
 840                                       LDO_ON);
 841         }
 842 #endif
 843
 844         return STATUS_SUCCESS;
 845 }
 846
 847 int monitor_card_cd(struct rts51x_chip *chip, u8 card)
 848 {
 849         int retval;
 850         u8 card_cd[32] = { 0 };
 851
 852         card_cd[SD_CARD] = SD_CD;
 853         card_cd[XD_CARD] = XD_CD;
 854         card_cd[MS_CARD] = MS_CD;
 855
 856         retval = rts51x_get_card_status(chip, &(chip->card_status));
 857         if (retval != STATUS_SUCCESS)
 858                 return CD_NOT_EXIST;
 859
 860         if (chip->card_status & card_cd[card])
 861                 return CD_EXIST;
 862
 863         return CD_NOT_EXIST;
 864 }
 865
 866 int rts51x_toggle_gpio(struct rts51x_chip *chip, u8 gpio)
 867 {
 868         int retval;
 869         u8 temp_reg;
 870         u8 gpio_output[4] = {
 871                 0x01,
 872         };
 873         u8 gpio_oe[4] = {
 874                 0x02,
 875         };
 876         if (chip->rts5179) {
 877                 retval = rts51x_ep0_read_register(chip, CARD_GPIO, &temp_reg);
 878                 if (retval != STATUS_SUCCESS)
 879                         TRACE_RET(chip, STATUS_FAIL);
 880                 temp_reg ^= gpio_oe[gpio];
 881                 temp_reg &= 0xfe; /* bit 0 always set 0 */
 882                 retval =
 883                     rts51x_ep0_write_register(chip, CARD_GPIO, 0x03, temp_reg);
 884                 if (retval != STATUS_SUCCESS)
 885                         TRACE_RET(chip, STATUS_FAIL);
 886         } else {
 887                 retval = rts51x_ep0_read_register(chip, CARD_GPIO, &temp_reg);
 888                 if (retval != STATUS_SUCCESS)
 889                         TRACE_RET(chip, STATUS_FAIL);
 890                 temp_reg ^= gpio_output[gpio];
 891                 retval =
 892                     rts51x_ep0_write_register(chip, CARD_GPIO, 0xFF,
 893                                               temp_reg | gpio_oe[gpio]);
 894                 if (retval != STATUS_SUCCESS)
 895                         TRACE_RET(chip, STATUS_FAIL);
 896         }
 897
 898         return STATUS_SUCCESS;
 899 }
 900
 901 int rts51x_turn_on_led(struct rts51x_chip *chip, u8 gpio)
 902 {
 903         int retval;
 904         u8 gpio_oe[4] = {
 905                 0x02,
 906         };
 907         u8 gpio_mask[4] = {
 908                 0x03,
 909         };
 910
 911         retval =
 912             rts51x_ep0_write_register(chip, CARD_GPIO, gpio_mask[gpio],
 913                                       gpio_oe[gpio]);
 914         if (retval != STATUS_SUCCESS)
 915                 TRACE_RET(chip, STATUS_FAIL);
 916
 917         return STATUS_SUCCESS;
 918 }
 919
 920 int rts51x_turn_off_led(struct rts51x_chip *chip, u8 gpio)
 921 {
 922         int retval;
 923         u8 gpio_output[4] = {
 924                 0x01,
 925         };
 926         u8 gpio_oe[4] = {
 927                 0x02,
 928         };
 929         u8 gpio_mask[4] = {
 930                 0x03,
 931         };
 932
 933         retval =
 934             rts51x_ep0_write_register(chip, CARD_GPIO, gpio_mask[gpio],
 935                                       gpio_oe[gpio] | gpio_output[gpio]);
 936         if (retval != STATUS_SUCCESS)
 937                 TRACE_RET(chip, STATUS_FAIL);
 938
 939         return STATUS_SUCCESS;
 940 }