3 #include "r819xU_phy.h"
4 #include "r819xU_phyreg.h"
5 #include "r8190_rtl8256.h"
7 #include "r819xU_firmware_img.h"
10 static u32 RF_CHANNEL_TABLE_ZEBRA[] = {
29 #define rtl819XPHY_REG_1T2RArray Rtl8192UsbPHY_REG_1T2RArray
30 #define rtl819XMACPHY_Array_PG Rtl8192UsbMACPHY_Array_PG
31 #define rtl819XMACPHY_Array Rtl8192UsbMACPHY_Array
32 #define rtl819XRadioA_Array Rtl8192UsbRadioA_Array
33 #define rtl819XRadioB_Array Rtl8192UsbRadioB_Array
34 #define rtl819XRadioC_Array Rtl8192UsbRadioC_Array
35 #define rtl819XRadioD_Array Rtl8192UsbRadioD_Array
36 #define rtl819XAGCTAB_Array Rtl8192UsbAGCTAB_Array
38 /******************************************************************************
39 *function: This function read BB parameters from Header file we gen,
40 * and do register read/write
41 * input: u32 dwBitMask //taget bit pos in the addr to be modified
43 * return: u32 return the shift bit position of the mask
44 * ****************************************************************************/
45 u32 rtl8192_CalculateBitShift(u32 dwBitMask)
50 if (((dwBitMask>>i)&0x1) == 1)
55 /******************************************************************************
56 *function: This function check different RF type to execute legal judgement. If RF Path is illegal, we will return false.
59 * return: 0(illegal, false), 1(legal,true)
60 * ***************************************************************************/
61 u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device *dev, u32 eRFPath)
64 struct r8192_priv *priv = ieee80211_priv(dev);
65 if (priv->rf_type == RF_2T4R)
67 else if (priv->rf_type == RF_1T2R)
69 if (eRFPath == RF90_PATH_A || eRFPath == RF90_PATH_B)
71 else if (eRFPath == RF90_PATH_C || eRFPath == RF90_PATH_D)
76 /******************************************************************************
77 *function: This function set specific bits to BB register
78 * input: net_device dev
79 * u32 dwRegAddr //target addr to be modified
80 * u32 dwBitMask //taget bit pos in the addr to be modified
81 * u32 dwData //value to be write
85 * ****************************************************************************/
86 void rtl8192_setBBreg(struct net_device *dev, u32 dwRegAddr, u32 dwBitMask, u32 dwData)
89 u32 OriginalValue, BitShift, NewValue;
91 if(dwBitMask!= bMaskDWord)
92 {//if not "double word" write
93 read_nic_dword(dev, dwRegAddr, &OriginalValue);
94 BitShift = rtl8192_CalculateBitShift(dwBitMask);
95 NewValue = (((OriginalValue) & (~dwBitMask)) | (dwData << BitShift));
96 write_nic_dword(dev, dwRegAddr, NewValue);
98 write_nic_dword(dev, dwRegAddr, dwData);
101 /******************************************************************************
102 *function: This function reads specific bits from BB register
103 * input: net_device dev
104 * u32 dwRegAddr //target addr to be readback
105 * u32 dwBitMask //taget bit pos in the addr to be readback
107 * return: u32 Data //the readback register value
109 * ****************************************************************************/
110 u32 rtl8192_QueryBBReg(struct net_device *dev, u32 dwRegAddr, u32 dwBitMask)
112 u32 Ret = 0, OriginalValue, BitShift;
114 read_nic_dword(dev, dwRegAddr, &OriginalValue);
115 BitShift = rtl8192_CalculateBitShift(dwBitMask);
116 Ret =(OriginalValue & dwBitMask) >> BitShift;
120 static u32 phy_FwRFSerialRead( struct net_device *dev, RF90_RADIO_PATH_E eRFPath, u32 Offset );
122 static void phy_FwRFSerialWrite( struct net_device *dev, RF90_RADIO_PATH_E eRFPath, u32 Offset, u32 Data);
124 /******************************************************************************
125 *function: This function read register from RF chip
126 * input: net_device dev
127 * RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D
128 * u32 Offset //target address to be read
130 * return: u32 readback value
131 * notice: There are three types of serial operations:(1) Software serial write.(2)Hardware LSSI-Low Speed Serial Interface.(3)Hardware HSSI-High speed serial write. Driver here need to implement (1) and (2)---need more spec for this information.
132 * ****************************************************************************/
133 u32 rtl8192_phy_RFSerialRead(struct net_device *dev, RF90_RADIO_PATH_E eRFPath, u32 Offset)
135 struct r8192_priv *priv = ieee80211_priv(dev);
138 BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath];
139 rtl8192_setBBreg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData, 0);
140 //make sure RF register offset is correct
143 //switch page for 8256 RF IC
144 if (priv->rf_chip == RF_8256)
148 priv->RfReg0Value[eRFPath] |= 0x140;
149 //Switch to Reg_Mode2 for Reg 31-45
150 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16) );
152 NewOffset = Offset -30;
154 else if (Offset >= 16)
156 priv->RfReg0Value[eRFPath] |= 0x100;
157 priv->RfReg0Value[eRFPath] &= (~0x40);
158 //Switch to Reg_Mode 1 for Reg16-30
159 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16) );
161 NewOffset = Offset - 15;
168 RT_TRACE((COMP_PHY|COMP_ERR), "check RF type here, need to be 8256\n");
171 //put desired read addr to LSSI control Register
172 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress, NewOffset);
173 //Issue a posedge trigger
175 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x0);
176 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x1);
179 // TODO: we should not delay such a long time. Ask for help from SD3
182 ret = rtl8192_QueryBBReg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData);
185 // Switch back to Reg_Mode0;
186 if(priv->rf_chip == RF_8256)
188 priv->RfReg0Value[eRFPath] &= 0xebf;
192 pPhyReg->rf3wireOffset,
194 (priv->RfReg0Value[eRFPath] << 16));
201 /******************************************************************************
202 *function: This function write data to RF register
203 * input: net_device dev
204 * RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D
205 * u32 Offset //target address to be written
206 * u32 Data //The new register data to be written
209 * notice: For RF8256 only.
210 ===========================================================
211 *Reg Mode RegCTL[1] RegCTL[0] Note
212 * (Reg00[12]) (Reg00[10])
213 *===========================================================
214 *Reg_Mode0 0 x Reg 0 ~15(0x0 ~ 0xf)
215 *------------------------------------------------------------------
216 *Reg_Mode1 1 0 Reg 16 ~30(0x1 ~ 0xf)
217 *------------------------------------------------------------------
218 * Reg_Mode2 1 1 Reg 31 ~ 45(0x1 ~ 0xf)
219 *------------------------------------------------------------------
220 * ****************************************************************************/
221 void rtl8192_phy_RFSerialWrite(struct net_device *dev, RF90_RADIO_PATH_E eRFPath, u32 Offset, u32 Data)
223 struct r8192_priv *priv = ieee80211_priv(dev);
224 u32 DataAndAddr = 0, NewOffset = 0;
225 BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath];
228 //spin_lock_irqsave(&priv->rf_lock, flags);
229 // down(&priv->rf_sem);
230 if (priv->rf_chip == RF_8256)
235 priv->RfReg0Value[eRFPath] |= 0x140;
236 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath] << 16));
237 NewOffset = Offset - 30;
239 else if (Offset >= 16)
241 priv->RfReg0Value[eRFPath] |= 0x100;
242 priv->RfReg0Value[eRFPath] &= (~0x40);
243 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16));
244 NewOffset = Offset - 15;
251 RT_TRACE((COMP_PHY|COMP_ERR), "check RF type here, need to be 8256\n");
255 // Put write addr in [5:0] and write data in [31:16]
256 DataAndAddr = (Data<<16) | (NewOffset&0x3f);
259 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
263 priv->RfReg0Value[eRFPath] = Data;
265 // Switch back to Reg_Mode0;
266 if(priv->rf_chip == RF_8256)
270 priv->RfReg0Value[eRFPath] &= 0xebf;
273 pPhyReg->rf3wireOffset,
275 (priv->RfReg0Value[eRFPath] << 16));
278 //spin_unlock_irqrestore(&priv->rf_lock, flags);
279 // up(&priv->rf_sem);
283 /******************************************************************************
284 *function: This function set specific bits to RF register
285 * input: net_device dev
286 * RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D
287 * u32 RegAddr //target addr to be modified
288 * u32 BitMask //taget bit pos in the addr to be modified
289 * u32 Data //value to be write
293 * ****************************************************************************/
294 void rtl8192_phy_SetRFReg(struct net_device *dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask, u32 Data)
296 struct r8192_priv *priv = ieee80211_priv(dev);
297 u32 Original_Value, BitShift, New_Value;
300 if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
303 if (priv->Rf_Mode == RF_OP_By_FW)
305 if (BitMask != bMask12Bits) // RF data is 12 bits only
307 Original_Value = phy_FwRFSerialRead(dev, eRFPath, RegAddr);
308 BitShift = rtl8192_CalculateBitShift(BitMask);
309 New_Value = ((Original_Value) & (~BitMask)) | (Data<< BitShift);
311 phy_FwRFSerialWrite(dev, eRFPath, RegAddr, New_Value);
313 phy_FwRFSerialWrite(dev, eRFPath, RegAddr, Data);
320 if (BitMask != bMask12Bits) // RF data is 12 bits only
322 Original_Value = rtl8192_phy_RFSerialRead(dev, eRFPath, RegAddr);
323 BitShift = rtl8192_CalculateBitShift(BitMask);
324 New_Value = (((Original_Value) & (~BitMask)) | (Data<< BitShift));
326 rtl8192_phy_RFSerialWrite(dev, eRFPath, RegAddr, New_Value);
328 rtl8192_phy_RFSerialWrite(dev, eRFPath, RegAddr, Data);
333 /******************************************************************************
334 *function: This function reads specific bits from RF register
335 * input: net_device dev
336 * u32 RegAddr //target addr to be readback
337 * u32 BitMask //taget bit pos in the addr to be readback
339 * return: u32 Data //the readback register value
341 * ****************************************************************************/
342 u32 rtl8192_phy_QueryRFReg(struct net_device *dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask)
344 u32 Original_Value, Readback_Value, BitShift;
345 struct r8192_priv *priv = ieee80211_priv(dev);
348 if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
350 if (priv->Rf_Mode == RF_OP_By_FW)
352 Original_Value = phy_FwRFSerialRead(dev, eRFPath, RegAddr);
353 BitShift = rtl8192_CalculateBitShift(BitMask);
354 Readback_Value = (Original_Value & BitMask) >> BitShift;
356 return (Readback_Value);
360 Original_Value = rtl8192_phy_RFSerialRead(dev, eRFPath, RegAddr);
361 BitShift = rtl8192_CalculateBitShift(BitMask);
362 Readback_Value = (Original_Value & BitMask) >> BitShift;
363 return (Readback_Value);
366 /******************************************************************************
367 *function: We support firmware to execute RF-R/W.
372 * ***************************************************************************/
375 struct net_device *dev,
376 RF90_RADIO_PATH_E eRFPath,
383 //DbgPrint("FW RF CTRL\n\r");
384 /* 2007/11/02 MH Firmware RF Write control. By Francis' suggestion, we can
385 not execute the scheme in the initial step. Otherwise, RF-R/W will waste
386 much time. This is only for site survey. */
387 // 1. Read operation need not insert data. bit 0-11
388 //Data &= bMask12Bits;
389 // 2. Write RF register address. Bit 12-19
390 Data |= ((Offset&0xFF)<<12);
391 // 3. Write RF path. bit 20-21
392 Data |= ((eRFPath&0x3)<<20);
393 // 4. Set RF read indicator. bit 22=0
395 // 5. Trigger Fw to operate the command. bit 31
397 // 6. We can not execute read operation if bit 31 is 1.
398 read_nic_dword(dev, QPNR, &tmp);
399 while (tmp & 0x80000000)
401 // If FW can not finish RF-R/W for more than ?? times. We must reset FW.
404 //DbgPrint("FW not finish RF-R Time=%d\n\r", time);
406 read_nic_dword(dev, QPNR, &tmp);
411 // 7. Execute read operation.
412 write_nic_dword(dev, QPNR, Data);
413 // 8. Check if firmawre send back RF content.
414 read_nic_dword(dev, QPNR, &tmp);
415 while (tmp & 0x80000000)
417 // If FW can not finish RF-R/W for more than ?? times. We must reset FW.
420 //DbgPrint("FW not finish RF-W Time=%d\n\r", time);
422 read_nic_dword(dev, QPNR, &tmp);
427 read_nic_dword(dev, RF_DATA, &retValue);
431 } /* phy_FwRFSerialRead */
433 /******************************************************************************
434 *function: We support firmware to execute RF-R/W.
439 * ***************************************************************************/
442 struct net_device *dev,
443 RF90_RADIO_PATH_E eRFPath,
450 //DbgPrint("N FW RF CTRL RF-%d OF%02x DATA=%03x\n\r", eRFPath, Offset, Data);
451 /* 2007/11/02 MH Firmware RF Write control. By Francis' suggestion, we can
452 not execute the scheme in the initial step. Otherwise, RF-R/W will waste
453 much time. This is only for site survey. */
455 // 1. Set driver write bit and 12 bit data. bit 0-11
456 //Data &= bMask12Bits; // Done by uper layer.
457 // 2. Write RF register address. bit 12-19
458 Data |= ((Offset&0xFF)<<12);
459 // 3. Write RF path. bit 20-21
460 Data |= ((eRFPath&0x3)<<20);
461 // 4. Set RF write indicator. bit 22=1
463 // 5. Trigger Fw to operate the command. bit 31=1
466 // 6. Write operation. We can not write if bit 31 is 1.
467 read_nic_dword(dev, QPNR, &tmp);
468 while (tmp & 0x80000000)
470 // If FW can not finish RF-R/W for more than ?? times. We must reset FW.
473 //DbgPrint("FW not finish RF-W Time=%d\n\r", time);
475 read_nic_dword(dev, QPNR, &tmp);
480 // 7. No matter check bit. We always force the write. Because FW will
481 // not accept the command.
482 write_nic_dword(dev, QPNR, Data);
483 /* 2007/11/02 MH Acoording to test, we must delay 20us to wait firmware
484 to finish RF write operation. */
485 /* 2008/01/17 MH We support delay in firmware side now. */
488 } /* phy_FwRFSerialWrite */
491 /******************************************************************************
492 *function: This function read BB parameters from Header file we gen,
493 * and do register read/write
497 * notice: BB parameters may change all the time, so please make
498 * sure it has been synced with the newest.
499 * ***************************************************************************/
500 void rtl8192_phy_configmac(struct net_device *dev)
502 u32 dwArrayLen = 0, i;
503 u32 *pdwArray = NULL;
504 struct r8192_priv *priv = ieee80211_priv(dev);
506 if(priv->btxpowerdata_readfromEEPORM)
508 RT_TRACE(COMP_PHY, "Rtl819XMACPHY_Array_PG\n");
509 dwArrayLen = MACPHY_Array_PGLength;
510 pdwArray = rtl819XMACPHY_Array_PG;
515 RT_TRACE(COMP_PHY, "Rtl819XMACPHY_Array\n");
516 dwArrayLen = MACPHY_ArrayLength;
517 pdwArray = rtl819XMACPHY_Array;
519 for(i = 0; i<dwArrayLen; i=i+3){
520 if(pdwArray[i] == 0x318)
522 pdwArray[i+2] = 0x00000800;
523 //DbgPrint("ptrArray[i], ptrArray[i+1], ptrArray[i+2] = %x, %x, %x\n",
524 // ptrArray[i], ptrArray[i+1], ptrArray[i+2]);
527 RT_TRACE(COMP_DBG, "The Rtl8190MACPHY_Array[0] is %x Rtl8190MACPHY_Array[1] is %x Rtl8190MACPHY_Array[2] is %x\n",
528 pdwArray[i], pdwArray[i+1], pdwArray[i+2]);
529 rtl8192_setBBreg(dev, pdwArray[i], pdwArray[i+1], pdwArray[i+2]);
535 /******************************************************************************
536 *function: This function does dirty work
540 * notice: BB parameters may change all the time, so please make
541 * sure it has been synced with the newest.
542 * ***************************************************************************/
544 void rtl8192_phyConfigBB(struct net_device *dev, u8 ConfigType)
549 u32 *rtl8192PhyRegArrayTable = NULL, *rtl8192AgcTabArrayTable = NULL;
550 if(Adapter->bInHctTest)
552 PHY_REGArrayLen = PHY_REGArrayLengthDTM;
553 AGCTAB_ArrayLen = AGCTAB_ArrayLengthDTM;
554 Rtl8190PHY_REGArray_Table = Rtl819XPHY_REGArrayDTM;
555 Rtl8190AGCTAB_Array_Table = Rtl819XAGCTAB_ArrayDTM;
558 if (ConfigType == BaseBand_Config_PHY_REG)
560 for (i=0; i<PHY_REG_1T2RArrayLength; i+=2)
562 rtl8192_setBBreg(dev, rtl819XPHY_REG_1T2RArray[i], bMaskDWord, rtl819XPHY_REG_1T2RArray[i+1]);
563 RT_TRACE(COMP_DBG, "i: %x, The Rtl819xUsbPHY_REGArray[0] is %x Rtl819xUsbPHY_REGArray[1] is %x \n",i, rtl819XPHY_REG_1T2RArray[i], rtl819XPHY_REG_1T2RArray[i+1]);
566 else if (ConfigType == BaseBand_Config_AGC_TAB)
568 for (i=0; i<AGCTAB_ArrayLength; i+=2)
570 rtl8192_setBBreg(dev, rtl819XAGCTAB_Array[i], bMaskDWord, rtl819XAGCTAB_Array[i+1]);
571 RT_TRACE(COMP_DBG, "i:%x, The rtl819XAGCTAB_Array[0] is %x rtl819XAGCTAB_Array[1] is %x \n",i, rtl819XAGCTAB_Array[i], rtl819XAGCTAB_Array[i+1]);
578 /******************************************************************************
579 *function: This function initialize Register definition offset for Radio Path
581 * input: net_device dev
584 * notice: Initialization value here is constant and it should never be changed
585 * ***************************************************************************/
586 void rtl8192_InitBBRFRegDef(struct net_device *dev)
588 struct r8192_priv *priv = ieee80211_priv(dev);
589 // RF Interface Software Control
590 priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 LSBs if read 32-bit from 0x870
591 priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872)
592 priv->PHYRegDef[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 LSBs if read 32-bit from 0x874
593 priv->PHYRegDef[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876)
595 // RF Interface Readback Value
596 priv->PHYRegDef[RF90_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB; // 16 LSBs if read 32-bit from 0x8E0
597 priv->PHYRegDef[RF90_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB;// 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2)
598 priv->PHYRegDef[RF90_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB;// 16 LSBs if read 32-bit from 0x8E4
599 priv->PHYRegDef[RF90_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB;// 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6)
601 // RF Interface Output (and Enable)
602 priv->PHYRegDef[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x860
603 priv->PHYRegDef[RF90_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x864
604 priv->PHYRegDef[RF90_PATH_C].rfintfo = rFPGA0_XC_RFInterfaceOE;// 16 LSBs if read 32-bit from 0x868
605 priv->PHYRegDef[RF90_PATH_D].rfintfo = rFPGA0_XD_RFInterfaceOE;// 16 LSBs if read 32-bit from 0x86C
607 // RF Interface (Output and) Enable
608 priv->PHYRegDef[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862)
609 priv->PHYRegDef[RF90_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866)
610 priv->PHYRegDef[RF90_PATH_C].rfintfe = rFPGA0_XC_RFInterfaceOE;// 16 MSBs if read 32-bit from 0x86A (16-bit for 0x86A)
611 priv->PHYRegDef[RF90_PATH_D].rfintfe = rFPGA0_XD_RFInterfaceOE;// 16 MSBs if read 32-bit from 0x86C (16-bit for 0x86E)
613 //Addr of LSSI. Write RF register by driver
614 priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; //LSSI Parameter
615 priv->PHYRegDef[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter;
616 priv->PHYRegDef[RF90_PATH_C].rf3wireOffset = rFPGA0_XC_LSSIParameter;
617 priv->PHYRegDef[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter;
620 priv->PHYRegDef[RF90_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter; //BB Band Select
621 priv->PHYRegDef[RF90_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter;
622 priv->PHYRegDef[RF90_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter;
623 priv->PHYRegDef[RF90_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter;
625 // Tx AGC Gain Stage (same for all path. Should we remove this?)
626 priv->PHYRegDef[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
627 priv->PHYRegDef[RF90_PATH_B].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
628 priv->PHYRegDef[RF90_PATH_C].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
629 priv->PHYRegDef[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
631 // Tranceiver A~D HSSI Parameter-1
632 priv->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1; //wire control parameter1
633 priv->PHYRegDef[RF90_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1; //wire control parameter1
634 priv->PHYRegDef[RF90_PATH_C].rfHSSIPara1 = rFPGA0_XC_HSSIParameter1; //wire control parameter1
635 priv->PHYRegDef[RF90_PATH_D].rfHSSIPara1 = rFPGA0_XD_HSSIParameter1; //wire control parameter1
637 // Tranceiver A~D HSSI Parameter-2
638 priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2; //wire control parameter2
639 priv->PHYRegDef[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2; //wire control parameter2
640 priv->PHYRegDef[RF90_PATH_C].rfHSSIPara2 = rFPGA0_XC_HSSIParameter2; //wire control parameter2
641 priv->PHYRegDef[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2; //wire control parameter1
644 priv->PHYRegDef[RF90_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl; //TR/Ant switch control
645 priv->PHYRegDef[RF90_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl;
646 priv->PHYRegDef[RF90_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl;
647 priv->PHYRegDef[RF90_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl;
650 priv->PHYRegDef[RF90_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1;
651 priv->PHYRegDef[RF90_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1;
652 priv->PHYRegDef[RF90_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1;
653 priv->PHYRegDef[RF90_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1;
656 priv->PHYRegDef[RF90_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2;
657 priv->PHYRegDef[RF90_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2;
658 priv->PHYRegDef[RF90_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2;
659 priv->PHYRegDef[RF90_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2;
662 priv->PHYRegDef[RF90_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance;
663 priv->PHYRegDef[RF90_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance;
664 priv->PHYRegDef[RF90_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance;
665 priv->PHYRegDef[RF90_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance;
668 priv->PHYRegDef[RF90_PATH_A].rfRxAFE = rOFDM0_XARxAFE;
669 priv->PHYRegDef[RF90_PATH_B].rfRxAFE = rOFDM0_XBRxAFE;
670 priv->PHYRegDef[RF90_PATH_C].rfRxAFE = rOFDM0_XCRxAFE;
671 priv->PHYRegDef[RF90_PATH_D].rfRxAFE = rOFDM0_XDRxAFE;
674 priv->PHYRegDef[RF90_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance;
675 priv->PHYRegDef[RF90_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance;
676 priv->PHYRegDef[RF90_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance;
677 priv->PHYRegDef[RF90_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance;
680 priv->PHYRegDef[RF90_PATH_A].rfTxAFE = rOFDM0_XATxAFE;
681 priv->PHYRegDef[RF90_PATH_B].rfTxAFE = rOFDM0_XBTxAFE;
682 priv->PHYRegDef[RF90_PATH_C].rfTxAFE = rOFDM0_XCTxAFE;
683 priv->PHYRegDef[RF90_PATH_D].rfTxAFE = rOFDM0_XDTxAFE;
685 // Tranceiver LSSI Readback
686 priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;
687 priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;
688 priv->PHYRegDef[RF90_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack;
689 priv->PHYRegDef[RF90_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack;
692 /******************************************************************************
693 *function: This function is to write register and then readback to make sure whether BB and RF is OK
694 * input: net_device dev
695 * HW90_BLOCK_E CheckBlock
696 * RF90_RADIO_PATH_E eRFPath //only used when checkblock is HW90_BLOCK_RF
698 * return: return whether BB and RF is ok(0:OK; 1:Fail)
699 * notice: This function may be removed in the ASIC
700 * ***************************************************************************/
701 u8 rtl8192_phy_checkBBAndRF(struct net_device *dev, HW90_BLOCK_E CheckBlock, RF90_RADIO_PATH_E eRFPath)
703 // struct r8192_priv *priv = ieee80211_priv(dev);
704 // BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath];
706 u32 i, CheckTimes = 4, dwRegRead = 0;
708 u32 WriteData[] = {0xfffff027, 0xaa55a02f, 0x00000027, 0x55aa502f};
709 // Initialize register address offset to be checked
710 WriteAddr[HW90_BLOCK_MAC] = 0x100;
711 WriteAddr[HW90_BLOCK_PHY0] = 0x900;
712 WriteAddr[HW90_BLOCK_PHY1] = 0x800;
713 WriteAddr[HW90_BLOCK_RF] = 0x3;
714 RT_TRACE(COMP_PHY, "=======>%s(), CheckBlock:%d\n", __FUNCTION__, CheckBlock);
715 for(i=0 ; i < CheckTimes ; i++)
719 // Write Data to register and readback
724 RT_TRACE(COMP_ERR, "PHY_CheckBBRFOK(): Never Write 0x100 here!");
727 case HW90_BLOCK_PHY0:
728 case HW90_BLOCK_PHY1:
729 write_nic_dword(dev, WriteAddr[CheckBlock], WriteData[i]);
730 read_nic_dword(dev, WriteAddr[CheckBlock], &dwRegRead);
734 WriteData[i] &= 0xfff;
735 rtl8192_phy_SetRFReg(dev, eRFPath, WriteAddr[HW90_BLOCK_RF], bMask12Bits, WriteData[i]);
736 // TODO: we should not delay for such a long time. Ask SD3
738 dwRegRead = rtl8192_phy_QueryRFReg(dev, eRFPath, WriteAddr[HW90_BLOCK_RF], bMask12Bits);
749 // Check whether readback data is correct
751 if(dwRegRead != WriteData[i])
753 RT_TRACE((COMP_PHY|COMP_ERR), "====>error=====dwRegRead: %x, WriteData: %x \n", dwRegRead, WriteData[i]);
763 /******************************************************************************
764 *function: This function initialize BB&RF
765 * input: net_device dev
768 * notice: Initialization value may change all the time, so please make
769 * sure it has been synced with the newest.
770 * ***************************************************************************/
771 void rtl8192_BB_Config_ParaFile(struct net_device *dev)
773 struct r8192_priv *priv = ieee80211_priv(dev);
774 u8 bRegValue = 0, eCheckItem = 0, rtStatus = 0;
776 /**************************************
777 //<1>Initialize BaseBand
778 **************************************/
780 /*--set BB Global Reset--*/
781 read_nic_byte(dev, BB_GLOBAL_RESET, &bRegValue);
782 write_nic_byte(dev, BB_GLOBAL_RESET,(bRegValue|BB_GLOBAL_RESET_BIT));
784 /*---set BB reset Active---*/
785 read_nic_dword(dev, CPU_GEN, &dwRegValue);
786 write_nic_dword(dev, CPU_GEN, (dwRegValue&(~CPU_GEN_BB_RST)));
788 /*----Ckeck FPGAPHY0 and PHY1 board is OK----*/
789 // TODO: this function should be removed on ASIC , Emily 2007.2.2
790 for(eCheckItem=(HW90_BLOCK_E)HW90_BLOCK_PHY0; eCheckItem<=HW90_BLOCK_PHY1; eCheckItem++)
792 rtStatus = rtl8192_phy_checkBBAndRF(dev, (HW90_BLOCK_E)eCheckItem, (RF90_RADIO_PATH_E)0); //don't care RF path
795 RT_TRACE((COMP_ERR | COMP_PHY), "PHY_RF8256_Config():Check PHY%d Fail!!\n", eCheckItem-1);
799 /*---- Set CCK and OFDM Block "OFF"----*/
800 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x0);
801 /*----BB Register Initilazation----*/
802 //==m==>Set PHY REG From Header<==m==
803 rtl8192_phyConfigBB(dev, BaseBand_Config_PHY_REG);
805 /*----Set BB reset de-Active----*/
806 read_nic_dword(dev, CPU_GEN, &dwRegValue);
807 write_nic_dword(dev, CPU_GEN, (dwRegValue|CPU_GEN_BB_RST));
809 /*----BB AGC table Initialization----*/
810 //==m==>Set PHY REG From Header<==m==
811 rtl8192_phyConfigBB(dev, BaseBand_Config_AGC_TAB);
813 /*----Enable XSTAL ----*/
814 write_nic_byte_E(dev, 0x5e, 0x00);
815 if (priv->card_8192_version == (u8)VERSION_819xU_A)
817 //Antenna gain offset from B/C/D to A
818 dwRegValue = (priv->AntennaTxPwDiff[1]<<4 | priv->AntennaTxPwDiff[0]);
819 rtl8192_setBBreg(dev, rFPGA0_TxGainStage, (bXBTxAGC|bXCTxAGC), dwRegValue);
822 dwRegValue = priv->CrystalCap & 0xf;
823 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bXtalCap, dwRegValue);
826 // Check if the CCK HighPower is turned ON.
827 // This is used to calculate PWDB.
828 priv->bCckHighPower = (u8)(rtl8192_QueryBBReg(dev, rFPGA0_XA_HSSIParameter2, 0x200));
831 /******************************************************************************
832 *function: This function initialize BB&RF
833 * input: net_device dev
836 * notice: Initialization value may change all the time, so please make
837 * sure it has been synced with the newest.
838 * ***************************************************************************/
839 void rtl8192_BBConfig(struct net_device *dev)
841 rtl8192_InitBBRFRegDef(dev);
842 //config BB&RF. As hardCode based initialization has not been well
843 //implemented, so use file first.FIXME:should implement it for hardcode?
844 rtl8192_BB_Config_ParaFile(dev);
848 /******************************************************************************
849 *function: This function obtains the initialization value of Tx power Level offset
850 * input: net_device dev
853 * ***************************************************************************/
854 void rtl8192_phy_getTxPower(struct net_device *dev)
856 struct r8192_priv *priv = ieee80211_priv(dev);
858 read_nic_dword(dev, rTxAGC_Rate18_06, &priv->MCSTxPowerLevelOriginalOffset[0]);
859 read_nic_dword(dev, rTxAGC_Rate54_24, &priv->MCSTxPowerLevelOriginalOffset[1]);
860 read_nic_dword(dev, rTxAGC_Mcs03_Mcs00, &priv->MCSTxPowerLevelOriginalOffset[2]);
861 read_nic_dword(dev, rTxAGC_Mcs07_Mcs04, &priv->MCSTxPowerLevelOriginalOffset[3]);
862 read_nic_dword(dev, rTxAGC_Mcs11_Mcs08, &priv->MCSTxPowerLevelOriginalOffset[4]);
863 read_nic_dword(dev, rTxAGC_Mcs15_Mcs12, &priv->MCSTxPowerLevelOriginalOffset[5]);
865 // read rx initial gain
866 read_nic_byte(dev, rOFDM0_XAAGCCore1, &priv->DefaultInitialGain[0]);
867 read_nic_byte(dev, rOFDM0_XBAGCCore1, &priv->DefaultInitialGain[1]);
868 read_nic_byte(dev, rOFDM0_XCAGCCore1, &priv->DefaultInitialGain[2]);
869 read_nic_byte(dev, rOFDM0_XDAGCCore1, &priv->DefaultInitialGain[3]);
870 RT_TRACE(COMP_INIT, "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x) \n",
871 priv->DefaultInitialGain[0], priv->DefaultInitialGain[1],
872 priv->DefaultInitialGain[2], priv->DefaultInitialGain[3]);
875 read_nic_byte(dev, rOFDM0_RxDetector3, &priv->framesync);
876 read_nic_byte(dev, rOFDM0_RxDetector2, &tmp);
877 priv->framesyncC34 = tmp;
878 RT_TRACE(COMP_INIT, "Default framesync (0x%x) = 0x%x \n",
879 rOFDM0_RxDetector3, priv->framesync);
881 // read SIFS (save the value read fome MACPHY_REG.txt)
882 read_nic_word(dev, SIFS, &priv->SifsTime);
887 /******************************************************************************
888 *function: This function obtains the initialization value of Tx power Level offset
889 * input: net_device dev
892 * ***************************************************************************/
893 void rtl8192_phy_setTxPower(struct net_device *dev, u8 channel)
895 struct r8192_priv *priv = ieee80211_priv(dev);
896 u8 powerlevel = priv->TxPowerLevelCCK[channel-1];
897 u8 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1];
899 switch (priv->rf_chip)
902 PHY_SetRF8256CCKTxPower(dev, powerlevel); //need further implement
903 PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G);
908 RT_TRACE((COMP_PHY|COMP_ERR), "error RF chipID(8225 or 8258) in function %s()\n", __FUNCTION__);
914 /******************************************************************************
915 *function: This function check Rf chip to do RF config
916 * input: net_device dev
918 * return: only 8256 is supported
919 * ***************************************************************************/
920 void rtl8192_phy_RFConfig(struct net_device *dev)
922 struct r8192_priv *priv = ieee80211_priv(dev);
924 switch (priv->rf_chip)
927 PHY_RF8256_Config(dev);
932 RT_TRACE(COMP_ERR, "error chip id\n");
938 /******************************************************************************
939 *function: This function update Initial gain
940 * input: net_device dev
942 * return: As Windows has not implemented this, wait for complement
943 * ***************************************************************************/
944 void rtl8192_phy_updateInitGain(struct net_device *dev)
949 /******************************************************************************
950 *function: This function read RF parameters from general head file, and do RF 3-wire
951 * input: net_device dev
953 * return: return code show if RF configuration is successful(0:pass, 1:fail)
954 * Note: Delay may be required for RF configuration
955 * ***************************************************************************/
956 u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device *dev, RF90_RADIO_PATH_E eRFPath)
965 for(i = 0;i<RadioA_ArrayLength; i=i+2){
967 if(rtl819XRadioA_Array[i] == 0xfe){
971 rtl8192_phy_SetRFReg(dev, eRFPath, rtl819XRadioA_Array[i], bMask12Bits, rtl819XRadioA_Array[i+1]);
977 for(i = 0;i<RadioB_ArrayLength; i=i+2){
979 if(rtl819XRadioB_Array[i] == 0xfe){
983 rtl8192_phy_SetRFReg(dev, eRFPath, rtl819XRadioB_Array[i], bMask12Bits, rtl819XRadioB_Array[i+1]);
989 for(i = 0;i<RadioC_ArrayLength; i=i+2){
991 if(rtl819XRadioC_Array[i] == 0xfe){
995 rtl8192_phy_SetRFReg(dev, eRFPath, rtl819XRadioC_Array[i], bMask12Bits, rtl819XRadioC_Array[i+1]);
1001 for(i = 0;i<RadioD_ArrayLength; i=i+2){
1003 if(rtl819XRadioD_Array[i] == 0xfe){
1007 rtl8192_phy_SetRFReg(dev, eRFPath, rtl819XRadioD_Array[i], bMask12Bits, rtl819XRadioD_Array[i+1]);
1019 /******************************************************************************
1020 *function: This function set Tx Power of the channel
1021 * input: struct net_device *dev
1026 * ***************************************************************************/
1027 void rtl8192_SetTxPowerLevel(struct net_device *dev, u8 channel)
1029 struct r8192_priv *priv = ieee80211_priv(dev);
1030 u8 powerlevel = priv->TxPowerLevelCCK[channel-1];
1031 u8 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1];
1033 switch (priv->rf_chip)
1037 PHY_SetRF8225CckTxPower(Adapter, powerlevel);
1038 PHY_SetRF8225OfdmTxPower(Adapter, powerlevelOFDM24G);
1043 PHY_SetRF8256CCKTxPower(dev, powerlevel);
1044 PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G);
1050 RT_TRACE(COMP_ERR, "unknown rf chip ID in rtl8192_SetTxPowerLevel()\n");
1056 /******************************************************************************
1057 *function: This function set RF state on or off
1058 * input: struct net_device *dev
1059 * RT_RF_POWER_STATE eRFPowerState //Power State to set
1063 * ***************************************************************************/
1064 bool rtl8192_SetRFPowerState(struct net_device *dev, RT_RF_POWER_STATE eRFPowerState)
1066 bool bResult = true;
1068 struct r8192_priv *priv = ieee80211_priv(dev);
1070 if(eRFPowerState == priv->ieee80211->eRFPowerState)
1073 if(priv->SetRFPowerStateInProgress == true)
1076 priv->SetRFPowerStateInProgress = true;
1078 switch (priv->rf_chip)
1081 switch ( eRFPowerState )
1085 //enable RF-Chip A/B
1086 rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x1); // 0x860[4]
1087 //analog to digital on
1088 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3);// 0x88c[9:8]
1089 //digital to analog on
1090 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18, 0x3); // 0x880[4:3]
1092 rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x3, 0x3);// 0xc04[1:0]
1094 rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x3, 0x3);// 0xd04[1:0]
1095 //analog to digital part2 on
1096 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 0x3); // 0x880[6:5]
1106 //disable RF-Chip A/B
1107 rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x0); // 0x860[4]
1108 //analog to digital off, for power save
1109 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);// 0x88c[11:8]
1110 //digital to analog off, for power save
1111 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18, 0x0); // 0x880[4:3]
1113 rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0xf, 0x0);// 0xc04[3:0]
1115 rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x0);// 0xd04[3:0]
1116 //analog to digital part2 off, for power save
1117 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 0x0); // 0x880[6:5]
1123 RT_TRACE(COMP_ERR, "SetRFPowerState819xUsb(): unknow state to set: 0x%X!!!\n", eRFPowerState);
1128 RT_TRACE(COMP_ERR, "Not support rf_chip(%x)\n", priv->rf_chip);
1134 // Update current RF state variable.
1135 pHalData->eRFPowerState = eRFPowerState;
1136 switch (pHalData->RFChipID )
1139 switch (pHalData->eRFPowerState)
1143 //If Rf off reason is from IPS, Led should blink with no link, by Maddest 071015
1145 if(pMgntInfo->RfOffReason==RF_CHANGE_BY_IPS )
1147 Adapter->HalFunc.LedControlHandler(Adapter,LED_CTL_NO_LINK);
1151 // Turn off LED if RF is not ON.
1152 Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_POWER_OFF);
1157 // Turn on RF we are still linked, which might happen when
1158 // we quickly turn off and on HW RF. 2006.05.12, by rcnjko.
1159 if( pMgntInfo->bMediaConnect == TRUE )
1161 Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_LINK);
1165 // Turn off LED if RF is not ON.
1166 Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_NO_LINK);
1177 RT_TRACE(COMP_RF, DBG_LOUD, ("SetRFPowerState8190(): Unknown RF type\n"));
1183 priv->SetRFPowerStateInProgress = false;
1188 /****************************************************************************************
1189 *function: This function set command table variable(struct SwChnlCmd).
1190 * input: SwChnlCmd* CmdTable //table to be set.
1191 * u32 CmdTableIdx //variable index in table to be set
1192 * u32 CmdTableSz //table size.
1193 * SwChnlCmdID CmdID //command ID to set.
1198 * return: true if finished, false otherwise
1200 * ************************************************************************************/
1201 u8 rtl8192_phy_SetSwChnlCmdArray(
1202 SwChnlCmd *CmdTable,
1213 if(CmdTable == NULL)
1215 RT_TRACE(COMP_ERR, "phy_SetSwChnlCmdArray(): CmdTable cannot be NULL.\n");
1218 if(CmdTableIdx >= CmdTableSz)
1220 RT_TRACE(COMP_ERR, "phy_SetSwChnlCmdArray(): Access invalid index, please check size of the table, CmdTableIdx:%d, CmdTableSz:%d\n",
1221 CmdTableIdx, CmdTableSz);
1225 pCmd = CmdTable + CmdTableIdx;
1226 pCmd->CmdID = CmdID;
1227 pCmd->Para1 = Para1;
1228 pCmd->Para2 = Para2;
1229 pCmd->msDelay = msDelay;
1233 /******************************************************************************
1234 *function: This function set channel step by step
1235 * input: struct net_device *dev
1237 * u8* stage //3 stages
1239 * u32* delay //whether need to delay
1240 * output: store new stage, step and delay for next step(combine with function above)
1241 * return: true if finished, false otherwise
1242 * Note: Wait for simpler function to replace it //wb
1243 * ***************************************************************************/
1244 u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel, u8 *stage, u8 *step, u32 *delay)
1246 struct r8192_priv *priv = ieee80211_priv(dev);
1247 // PCHANNEL_ACCESS_SETTING pChnlAccessSetting;
1248 SwChnlCmd PreCommonCmd[MAX_PRECMD_CNT];
1249 u32 PreCommonCmdCnt;
1250 SwChnlCmd PostCommonCmd[MAX_POSTCMD_CNT];
1251 u32 PostCommonCmdCnt;
1252 SwChnlCmd RfDependCmd[MAX_RFDEPENDCMD_CNT];
1254 SwChnlCmd *CurrentCmd = NULL;
1255 //RF90_RADIO_PATH_E eRFPath;
1260 RT_TRACE(COMP_CH, "====>%s()====stage:%d, step:%d, channel:%d\n", __FUNCTION__, *stage, *step, channel);
1261 // RT_ASSERT(IsLegalChannel(Adapter, channel), ("illegal channel: %d\n", channel));
1262 if (!IsLegalChannel(priv->ieee80211, channel))
1264 RT_TRACE(COMP_ERR, "=============>set to illegal channel:%d\n", channel);
1265 return true; //return true to tell upper caller function this channel setting is finished! Or it will in while loop.
1267 //FIXME:need to check whether channel is legal or not here.WB
1270 //for(eRFPath = RF90_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
1271 // for(eRFPath = 0; eRFPath <RF90_PATH_MAX; eRFPath++)
1273 // if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
1275 // <1> Fill up pre common command.
1276 PreCommonCmdCnt = 0;
1277 rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT,
1278 CmdID_SetTxPowerLevel, 0, 0, 0);
1279 rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT,
1280 CmdID_End, 0, 0, 0);
1282 // <2> Fill up post common command.
1283 PostCommonCmdCnt = 0;
1285 rtl8192_phy_SetSwChnlCmdArray(PostCommonCmd, PostCommonCmdCnt++, MAX_POSTCMD_CNT,
1286 CmdID_End, 0, 0, 0);
1288 // <3> Fill up RF dependent command.
1290 switch ( priv->rf_chip )
1293 if (!(channel >= 1 && channel <= 14))
1295 RT_TRACE(COMP_ERR, "illegal channel for Zebra 8225: %d\n", channel);
1298 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
1299 CmdID_RF_WriteReg, rZebra1_Channel, RF_CHANNEL_TABLE_ZEBRA[channel], 10);
1300 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
1301 CmdID_End, 0, 0, 0);
1305 // TEST!! This is not the table for 8256!!
1306 if (!(channel >= 1 && channel <= 14))
1308 RT_TRACE(COMP_ERR, "illegal channel for Zebra 8256: %d\n", channel);
1311 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
1312 CmdID_RF_WriteReg, rZebra1_Channel, channel, 10);
1313 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
1314 CmdID_End, 0, 0, 0);
1321 RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip);
1331 CurrentCmd=&PreCommonCmd[*step];
1334 CurrentCmd=&RfDependCmd[*step];
1337 CurrentCmd=&PostCommonCmd[*step];
1341 if(CurrentCmd->CmdID==CmdID_End)
1345 (*delay)=CurrentCmd->msDelay;
1356 switch (CurrentCmd->CmdID)
1358 case CmdID_SetTxPowerLevel:
1359 if(priv->card_8192_version == (u8)VERSION_819xU_A) //xiong: consider it later!
1360 rtl8192_SetTxPowerLevel(dev,channel);
1362 case CmdID_WritePortUlong:
1363 write_nic_dword(dev, CurrentCmd->Para1, CurrentCmd->Para2);
1365 case CmdID_WritePortUshort:
1366 write_nic_word(dev, CurrentCmd->Para1, (u16)CurrentCmd->Para2);
1368 case CmdID_WritePortUchar:
1369 write_nic_byte(dev, CurrentCmd->Para1, (u8)CurrentCmd->Para2);
1371 case CmdID_RF_WriteReg:
1372 for(eRFPath = 0; eRFPath < RF90_PATH_MAX; eRFPath++)
1374 rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, bZebra1_ChannelNum, CurrentCmd->Para2);
1383 // }/*for(Number of RF paths)*/
1385 (*delay)=CurrentCmd->msDelay;
1390 /******************************************************************************
1391 *function: This function does actually set channel work
1392 * input: struct net_device *dev
1396 * Note: We should not call this function directly
1397 * ***************************************************************************/
1398 void rtl8192_phy_FinishSwChnlNow(struct net_device *dev, u8 channel)
1400 struct r8192_priv *priv = ieee80211_priv(dev);
1403 while(!rtl8192_phy_SwChnlStepByStep(dev,channel,&priv->SwChnlStage,&priv->SwChnlStep,&delay))
1406 // msleep(delay);//or mdelay? need further consideration
1411 /******************************************************************************
1412 *function: Callback routine of the work item for switch channel.
1417 * ***************************************************************************/
1418 void rtl8192_SwChnl_WorkItem(struct net_device *dev)
1421 struct r8192_priv *priv = ieee80211_priv(dev);
1423 RT_TRACE(COMP_CH, "==> SwChnlCallback819xUsbWorkItem(), chan:%d\n", priv->chan);
1426 rtl8192_phy_FinishSwChnlNow(dev , priv->chan);
1428 RT_TRACE(COMP_CH, "<== SwChnlCallback819xUsbWorkItem()\n");
1431 /******************************************************************************
1432 *function: This function scheduled actual work item to set channel
1433 * input: net_device dev
1434 * u8 channel //channel to set
1436 * return: return code show if workitem is scheduled(1:pass, 0:fail)
1437 * Note: Delay may be required for RF configuration
1438 * ***************************************************************************/
1439 u8 rtl8192_phy_SwChnl(struct net_device *dev, u8 channel)
1441 struct r8192_priv *priv = ieee80211_priv(dev);
1442 RT_TRACE(COMP_CH, "=====>%s(), SwChnlInProgress:%d\n", __FUNCTION__, priv->SwChnlInProgress);
1445 if(priv->SwChnlInProgress)
1448 // if(pHalData->SetBWModeInProgress)
1450 if (0) //to test current channel from RF reg 0x7.
1453 for(eRFPath = 0; eRFPath < 2; eRFPath++){
1454 printk("====>set channel:%x\n",rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x7, bZebra1_ChannelNum));
1458 //--------------------------------------------
1459 switch (priv->ieee80211->mode)
1461 case WIRELESS_MODE_A:
1462 case WIRELESS_MODE_N_5G:
1464 RT_TRACE(COMP_ERR, "WIRELESS_MODE_A but channel<=14");
1468 case WIRELESS_MODE_B:
1470 RT_TRACE(COMP_ERR, "WIRELESS_MODE_B but channel>14");
1474 case WIRELESS_MODE_G:
1475 case WIRELESS_MODE_N_24G:
1477 RT_TRACE(COMP_ERR, "WIRELESS_MODE_G but channel>14");
1482 //--------------------------------------------
1484 priv->SwChnlInProgress = true;
1490 priv->SwChnlStage=0;
1492 // schedule_work(&(priv->SwChnlWorkItem));
1493 // rtl8192_SwChnl_WorkItem(dev);
1495 // queue_work(priv->priv_wq,&(priv->SwChnlWorkItem));
1496 rtl8192_SwChnl_WorkItem(dev);
1499 priv->SwChnlInProgress = false;
1505 /******************************************************************************
1506 *function: Callback routine of the work item for set bandwidth mode.
1507 * input: struct net_device *dev
1508 * HT_CHANNEL_WIDTH Bandwidth //20M or 40M
1509 * HT_EXTCHNL_OFFSET Offset //Upper, Lower, or Don't care
1512 * Note: I doubt whether SetBWModeInProgress flag is necessary as we can
1513 * test whether current work in the queue or not.//do I?
1514 * ***************************************************************************/
1515 void rtl8192_SetBWModeWorkItem(struct net_device *dev)
1518 struct r8192_priv *priv = ieee80211_priv(dev);
1521 RT_TRACE(COMP_SWBW, "==>rtl8192_SetBWModeWorkItem() Switch to %s bandwidth\n", \
1522 priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz")
1525 if(priv->rf_chip == RF_PSEUDO_11N)
1527 priv->SetBWModeInProgress= false;
1531 //<1>Set MAC register
1532 read_nic_byte(dev, BW_OPMODE, ®BwOpMode);
1534 switch (priv->CurrentChannelBW)
1536 case HT_CHANNEL_WIDTH_20:
1537 regBwOpMode |= BW_OPMODE_20MHZ;
1538 // 2007/02/07 Mark by Emily because we have not verify whether this register works
1539 write_nic_byte(dev, BW_OPMODE, regBwOpMode);
1542 case HT_CHANNEL_WIDTH_20_40:
1543 regBwOpMode &= ~BW_OPMODE_20MHZ;
1544 // 2007/02/07 Mark by Emily because we have not verify whether this register works
1545 write_nic_byte(dev, BW_OPMODE, regBwOpMode);
1549 RT_TRACE(COMP_ERR, "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n",priv->CurrentChannelBW);
1553 //<2>Set PHY related register
1554 switch (priv->CurrentChannelBW)
1556 case HT_CHANNEL_WIDTH_20:
1557 // Add by Vivi 20071119
1558 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0);
1559 rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0);
1560 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 1);
1562 // Correct the tx power for CCK rate in 20M. Suggest by YN, 20071207
1563 priv->cck_present_attentuation =
1564 priv->cck_present_attentuation_20Mdefault + priv->cck_present_attentuation_difference;
1566 if(priv->cck_present_attentuation > 22)
1567 priv->cck_present_attentuation= 22;
1568 if(priv->cck_present_attentuation< 0)
1569 priv->cck_present_attentuation = 0;
1570 RT_TRACE(COMP_INIT, "20M, pHalData->CCKPresentAttentuation = %d\n", priv->cck_present_attentuation);
1572 if(priv->chan == 14 && !priv->bcck_in_ch14)
1574 priv->bcck_in_ch14 = TRUE;
1575 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
1577 else if(priv->chan != 14 && priv->bcck_in_ch14)
1579 priv->bcck_in_ch14 = FALSE;
1580 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
1583 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
1586 case HT_CHANNEL_WIDTH_20_40:
1587 // Add by Vivi 20071119
1588 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1);
1589 rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1);
1590 rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1));
1591 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0);
1592 rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC);
1593 priv->cck_present_attentuation =
1594 priv->cck_present_attentuation_40Mdefault + priv->cck_present_attentuation_difference;
1596 if(priv->cck_present_attentuation > 22)
1597 priv->cck_present_attentuation = 22;
1598 if(priv->cck_present_attentuation < 0)
1599 priv->cck_present_attentuation = 0;
1601 RT_TRACE(COMP_INIT, "40M, pHalData->CCKPresentAttentuation = %d\n", priv->cck_present_attentuation);
1602 if(priv->chan == 14 && !priv->bcck_in_ch14)
1604 priv->bcck_in_ch14 = true;
1605 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
1607 else if(priv->chan!= 14 && priv->bcck_in_ch14)
1609 priv->bcck_in_ch14 = false;
1610 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
1613 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
1617 RT_TRACE(COMP_ERR, "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n" ,priv->CurrentChannelBW);
1621 //Skip over setting of J-mode in BB register here. Default value is "None J mode". Emily 20070315
1623 //<3>Set RF related register
1624 switch ( priv->rf_chip )
1628 PHY_SetRF8225Bandwidth(Adapter, pHalData->CurrentChannelBW);
1633 PHY_SetRF8256Bandwidth(dev, priv->CurrentChannelBW);
1637 // PHY_SetRF8258Bandwidth();
1645 RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip);
1648 priv->SetBWModeInProgress= false;
1650 RT_TRACE(COMP_SWBW, "<==SetBWMode819xUsb(), %d", atomic_read(&(priv->ieee80211->atm_swbw)) );
1653 /******************************************************************************
1654 *function: This function schedules bandwidth switch work.
1655 * input: struct net_device *dev
1656 * HT_CHANNEL_WIDTH Bandwidth //20M or 40M
1657 * HT_EXTCHNL_OFFSET Offset //Upper, Lower, or Don't care
1660 * Note: I doubt whether SetBWModeInProgress flag is necessary as we can
1661 * test whether current work in the queue or not.//do I?
1662 * ***************************************************************************/
1663 void rtl8192_SetBWMode(struct net_device *dev, HT_CHANNEL_WIDTH Bandwidth, HT_EXTCHNL_OFFSET Offset)
1665 struct r8192_priv *priv = ieee80211_priv(dev);
1667 if(priv->SetBWModeInProgress)
1669 priv->SetBWModeInProgress= true;
1671 priv->CurrentChannelBW = Bandwidth;
1673 if(Offset==HT_EXTCHNL_OFFSET_LOWER)
1674 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER;
1675 else if(Offset==HT_EXTCHNL_OFFSET_UPPER)
1676 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER;
1678 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
1680 //queue_work(priv->priv_wq, &(priv->SetBWModeWorkItem));
1681 // schedule_work(&(priv->SetBWModeWorkItem));
1682 rtl8192_SetBWModeWorkItem(dev);
1686 void InitialGain819xUsb(struct net_device *dev, u8 Operation)
1688 struct r8192_priv *priv = ieee80211_priv(dev);
1690 priv->InitialGainOperateType = Operation;
1694 queue_delayed_work(priv->priv_wq,&priv->initialgain_operate_wq,0);
1698 extern void InitialGainOperateWorkItemCallBack(struct work_struct *work)
1700 struct delayed_work *dwork = container_of(work,struct delayed_work,work);
1701 struct r8192_priv *priv = container_of(dwork,struct r8192_priv,initialgain_operate_wq);
1702 struct net_device *dev = priv->ieee80211->dev;
1703 #define SCAN_RX_INITIAL_GAIN 0x17
1704 #define POWER_DETECTION_TH 0x08
1709 Operation = priv->InitialGainOperateType;
1714 RT_TRACE(COMP_SCAN, "IG_Backup, backup the initial gain.\n");
1715 initial_gain = SCAN_RX_INITIAL_GAIN;//priv->DefaultInitialGain[0];//
1716 BitMask = bMaskByte0;
1717 if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
1718 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // FW DIG OFF
1719 priv->initgain_backup.xaagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, BitMask);
1720 priv->initgain_backup.xbagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, BitMask);
1721 priv->initgain_backup.xcagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, BitMask);
1722 priv->initgain_backup.xdagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, BitMask);
1723 BitMask = bMaskByte2;
1724 priv->initgain_backup.cca = (u8)rtl8192_QueryBBReg(dev, rCCK0_CCA, BitMask);
1726 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc50 is %x\n",priv->initgain_backup.xaagccore1);
1727 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc58 is %x\n",priv->initgain_backup.xbagccore1);
1728 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc60 is %x\n",priv->initgain_backup.xcagccore1);
1729 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc68 is %x\n",priv->initgain_backup.xdagccore1);
1730 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xa0a is %x\n",priv->initgain_backup.cca);
1732 RT_TRACE(COMP_SCAN, "Write scan initial gain = 0x%x \n", initial_gain);
1733 write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain);
1734 write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain);
1735 write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain);
1736 write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain);
1737 RT_TRACE(COMP_SCAN, "Write scan 0xa0a = 0x%x \n", POWER_DETECTION_TH);
1738 write_nic_byte(dev, 0xa0a, POWER_DETECTION_TH);
1741 RT_TRACE(COMP_SCAN, "IG_Restore, restore the initial gain.\n");
1742 BitMask = 0x7f; //Bit0~ Bit6
1743 if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
1744 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // FW DIG OFF
1746 rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, BitMask, (u32)priv->initgain_backup.xaagccore1);
1747 rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, BitMask, (u32)priv->initgain_backup.xbagccore1);
1748 rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, BitMask, (u32)priv->initgain_backup.xcagccore1);
1749 rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, BitMask, (u32)priv->initgain_backup.xdagccore1);
1750 BitMask = bMaskByte2;
1751 rtl8192_setBBreg(dev, rCCK0_CCA, BitMask, (u32)priv->initgain_backup.cca);
1753 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc50 is %x\n",priv->initgain_backup.xaagccore1);
1754 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc58 is %x\n",priv->initgain_backup.xbagccore1);
1755 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc60 is %x\n",priv->initgain_backup.xcagccore1);
1756 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc68 is %x\n",priv->initgain_backup.xdagccore1);
1757 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xa0a is %x\n",priv->initgain_backup.cca);
1760 SetTxPowerLevel8190(Adapter,priv->CurrentChannel);
1763 SetTxPowerLevel8190(Adapter,priv->CurrentChannel);
1766 rtl8192_phy_setTxPower(dev,priv->ieee80211->current_network.channel);
1769 if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
1770 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); // FW DIG ON
1773 RT_TRACE(COMP_SCAN, "Unknown IG Operation. \n");