Pileus Git - ~andy/linux/blob - drivers/staging/rtl8192e/r819xE_phy.c

   1 #include "r8192E.h"
   2 #include "r8192E_hw.h"
   3 #include "r819xE_phyreg.h"
   4 #include "r8190_rtl8256.h"
   5 #include "r819xE_phy.h"
   6 #include "r8192E_dm.h"
   7 #ifdef ENABLE_DOT11D
   8 #include "ieee80211/dot11d.h"
   9 #endif
  10 static const u32 RF_CHANNEL_TABLE_ZEBRA[] = {
  11         0,
  12         0x085c, //2412 1
  13         0x08dc, //2417 2
  14         0x095c, //2422 3
  15         0x09dc, //2427 4
  16         0x0a5c, //2432 5
  17         0x0adc, //2437 6
  18         0x0b5c, //2442 7
  19         0x0bdc, //2447 8
  20         0x0c5c, //2452 9
  21         0x0cdc, //2457 10
  22         0x0d5c, //2462 11
  23         0x0ddc, //2467 12
  24         0x0e5c, //2472 13
  25         0x0f72, //2484
  26 };
  27
  28 static u32 Rtl8192PciEMACPHY_Array[] = {
  29 0x03c,0xffff0000,0x00000f0f,
  30 0x340,0xffffffff,0x161a1a1a,
  31 0x344,0xffffffff,0x12121416,
  32 0x348,0x0000ffff,0x00001818,
  33 0x12c,0xffffffff,0x04000802,
  34 0x318,0x00000fff,0x00000100,
  35 };
  36 static u32 Rtl8192PciEMACPHY_Array_PG[] = {
  37 0x03c,0xffff0000,0x00000f0f,
  38 0xe00,0xffffffff,0x06090909,
  39 0xe04,0xffffffff,0x00030306,
  40 0xe08,0x0000ff00,0x00000000,
  41 0xe10,0xffffffff,0x0a0c0d0f,
  42 0xe14,0xffffffff,0x06070809,
  43 0xe18,0xffffffff,0x0a0c0d0f,
  44 0xe1c,0xffffffff,0x06070809,
  45 0x12c,0xffffffff,0x04000802,
  46 0x318,0x00000fff,0x00000800,
  47 };
  48 static u32 Rtl8192PciEAGCTAB_Array[AGCTAB_ArrayLength] = {
  49 0xc78,0x7d000001,
  50 0xc78,0x7d010001,
  51 0xc78,0x7d020001,
  52 0xc78,0x7d030001,
  53 0xc78,0x7d040001,
  54 0xc78,0x7d050001,
  55 0xc78,0x7c060001,
  56 0xc78,0x7b070001,
  57 0xc78,0x7a080001,
  58 0xc78,0x79090001,
  59 0xc78,0x780a0001,
  60 0xc78,0x770b0001,
  61 0xc78,0x760c0001,
  62 0xc78,0x750d0001,
  63 0xc78,0x740e0001,
  64 0xc78,0x730f0001,
  65 0xc78,0x72100001,
  66 0xc78,0x71110001,
  67 0xc78,0x70120001,
  68 0xc78,0x6f130001,
  69 0xc78,0x6e140001,
  70 0xc78,0x6d150001,
  71 0xc78,0x6c160001,
  72 0xc78,0x6b170001,
  73 0xc78,0x6a180001,
  74 0xc78,0x69190001,
  75 0xc78,0x681a0001,
  76 0xc78,0x671b0001,
  77 0xc78,0x661c0001,
  78 0xc78,0x651d0001,
  79 0xc78,0x641e0001,
  80 0xc78,0x491f0001,
  81 0xc78,0x48200001,
  82 0xc78,0x47210001,
  83 0xc78,0x46220001,
  84 0xc78,0x45230001,
  85 0xc78,0x44240001,
  86 0xc78,0x43250001,
  87 0xc78,0x28260001,
  88 0xc78,0x27270001,
  89 0xc78,0x26280001,
  90 0xc78,0x25290001,
  91 0xc78,0x242a0001,
  92 0xc78,0x232b0001,
  93 0xc78,0x222c0001,
  94 0xc78,0x212d0001,
  95 0xc78,0x202e0001,
  96 0xc78,0x0a2f0001,
  97 0xc78,0x08300001,
  98 0xc78,0x06310001,
  99 0xc78,0x05320001,
 100 0xc78,0x04330001,
 101 0xc78,0x03340001,
 102 0xc78,0x02350001,
 103 0xc78,0x01360001,
 104 0xc78,0x00370001,
 105 0xc78,0x00380001,
 106 0xc78,0x00390001,
 107 0xc78,0x003a0001,
 108 0xc78,0x003b0001,
 109 0xc78,0x003c0001,
 110 0xc78,0x003d0001,
 111 0xc78,0x003e0001,
 112 0xc78,0x003f0001,
 113 0xc78,0x7d400001,
 114 0xc78,0x7d410001,
 115 0xc78,0x7d420001,
 116 0xc78,0x7d430001,
 117 0xc78,0x7d440001,
 118 0xc78,0x7d450001,
 119 0xc78,0x7c460001,
 120 0xc78,0x7b470001,
 121 0xc78,0x7a480001,
 122 0xc78,0x79490001,
 123 0xc78,0x784a0001,
 124 0xc78,0x774b0001,
 125 0xc78,0x764c0001,
 126 0xc78,0x754d0001,
 127 0xc78,0x744e0001,
 128 0xc78,0x734f0001,
 129 0xc78,0x72500001,
 130 0xc78,0x71510001,
 131 0xc78,0x70520001,
 132 0xc78,0x6f530001,
 133 0xc78,0x6e540001,
 134 0xc78,0x6d550001,
 135 0xc78,0x6c560001,
 136 0xc78,0x6b570001,
 137 0xc78,0x6a580001,
 138 0xc78,0x69590001,
 139 0xc78,0x685a0001,
 140 0xc78,0x675b0001,
 141 0xc78,0x665c0001,
 142 0xc78,0x655d0001,
 143 0xc78,0x645e0001,
 144 0xc78,0x495f0001,
 145 0xc78,0x48600001,
 146 0xc78,0x47610001,
 147 0xc78,0x46620001,
 148 0xc78,0x45630001,
 149 0xc78,0x44640001,
 150 0xc78,0x43650001,
 151 0xc78,0x28660001,
 152 0xc78,0x27670001,
 153 0xc78,0x26680001,
 154 0xc78,0x25690001,
 155 0xc78,0x246a0001,
 156 0xc78,0x236b0001,
 157 0xc78,0x226c0001,
 158 0xc78,0x216d0001,
 159 0xc78,0x206e0001,
 160 0xc78,0x0a6f0001,
 161 0xc78,0x08700001,
 162 0xc78,0x06710001,
 163 0xc78,0x05720001,
 164 0xc78,0x04730001,
 165 0xc78,0x03740001,
 166 0xc78,0x02750001,
 167 0xc78,0x01760001,
 168 0xc78,0x00770001,
 169 0xc78,0x00780001,
 170 0xc78,0x00790001,
 171 0xc78,0x007a0001,
 172 0xc78,0x007b0001,
 173 0xc78,0x007c0001,
 174 0xc78,0x007d0001,
 175 0xc78,0x007e0001,
 176 0xc78,0x007f0001,
 177 0xc78,0x2e00001e,
 178 0xc78,0x2e01001e,
 179 0xc78,0x2e02001e,
 180 0xc78,0x2e03001e,
 181 0xc78,0x2e04001e,
 182 0xc78,0x2e05001e,
 183 0xc78,0x3006001e,
 184 0xc78,0x3407001e,
 185 0xc78,0x3908001e,
 186 0xc78,0x3c09001e,
 187 0xc78,0x3f0a001e,
 188 0xc78,0x420b001e,
 189 0xc78,0x440c001e,
 190 0xc78,0x450d001e,
 191 0xc78,0x460e001e,
 192 0xc78,0x460f001e,
 193 0xc78,0x4710001e,
 194 0xc78,0x4811001e,
 195 0xc78,0x4912001e,
 196 0xc78,0x4a13001e,
 197 0xc78,0x4b14001e,
 198 0xc78,0x4b15001e,
 199 0xc78,0x4c16001e,
 200 0xc78,0x4d17001e,
 201 0xc78,0x4e18001e,
 202 0xc78,0x4f19001e,
 203 0xc78,0x4f1a001e,
 204 0xc78,0x501b001e,
 205 0xc78,0x511c001e,
 206 0xc78,0x521d001e,
 207 0xc78,0x521e001e,
 208 0xc78,0x531f001e,
 209 0xc78,0x5320001e,
 210 0xc78,0x5421001e,
 211 0xc78,0x5522001e,
 212 0xc78,0x5523001e,
 213 0xc78,0x5624001e,
 214 0xc78,0x5725001e,
 215 0xc78,0x5726001e,
 216 0xc78,0x5827001e,
 217 0xc78,0x5828001e,
 218 0xc78,0x5929001e,
 219 0xc78,0x592a001e,
 220 0xc78,0x5a2b001e,
 221 0xc78,0x5b2c001e,
 222 0xc78,0x5c2d001e,
 223 0xc78,0x5c2e001e,
 224 0xc78,0x5d2f001e,
 225 0xc78,0x5e30001e,
 226 0xc78,0x5f31001e,
 227 0xc78,0x6032001e,
 228 0xc78,0x6033001e,
 229 0xc78,0x6134001e,
 230 0xc78,0x6235001e,
 231 0xc78,0x6336001e,
 232 0xc78,0x6437001e,
 233 0xc78,0x6438001e,
 234 0xc78,0x6539001e,
 235 0xc78,0x663a001e,
 236 0xc78,0x673b001e,
 237 0xc78,0x673c001e,
 238 0xc78,0x683d001e,
 239 0xc78,0x693e001e,
 240 0xc78,0x6a3f001e,
 241 };
 242 static u32 Rtl8192PciEPHY_REGArray[PHY_REGArrayLength] = {
 243 0x0, };
 244 static u32 Rtl8192PciEPHY_REG_1T2RArray[PHY_REG_1T2RArrayLength] = {
 245 0x800,0x00000000,
 246 0x804,0x00000001,
 247 0x808,0x0000fc00,
 248 0x80c,0x0000001c,
 249 0x810,0x801010aa,
 250 0x814,0x008514d0,
 251 0x818,0x00000040,
 252 0x81c,0x00000000,
 253 0x820,0x00000004,
 254 0x824,0x00690000,
 255 0x828,0x00000004,
 256 0x82c,0x00e90000,
 257 0x830,0x00000004,
 258 0x834,0x00690000,
 259 0x838,0x00000004,
 260 0x83c,0x00e90000,
 261 0x840,0x00000000,
 262 0x844,0x00000000,
 263 0x848,0x00000000,
 264 0x84c,0x00000000,
 265 0x850,0x00000000,
 266 0x854,0x00000000,
 267 0x858,0x65a965a9,
 268 0x85c,0x65a965a9,
 269 0x860,0x001f0010,
 270 0x864,0x007f0010,
 271 0x868,0x001f0010,
 272 0x86c,0x007f0010,
 273 0x870,0x0f100f70,
 274 0x874,0x0f100f70,
 275 0x878,0x00000000,
 276 0x87c,0x00000000,
 277 0x880,0x6870e36c,
 278 0x884,0xe3573600,
 279 0x888,0x4260c340,
 280 0x88c,0x0000ff00,
 281 0x890,0x00000000,
 282 0x894,0xfffffffe,
 283 0x898,0x4c42382f,
 284 0x89c,0x00656056,
 285 0x8b0,0x00000000,
 286 0x8e0,0x00000000,
 287 0x8e4,0x00000000,
 288 0x900,0x00000000,
 289 0x904,0x00000023,
 290 0x908,0x00000000,
 291 0x90c,0x31121311,
 292 0xa00,0x00d0c7d8,
 293 0xa04,0x811f0008,
 294 0xa08,0x80cd8300,
 295 0xa0c,0x2e62740f,
 296 0xa10,0x95009b78,
 297 0xa14,0x11145008,
 298 0xa18,0x00881117,
 299 0xa1c,0x89140fa0,
 300 0xa20,0x1a1b0000,
 301 0xa24,0x090e1317,
 302 0xa28,0x00000204,
 303 0xa2c,0x00000000,
 304 0xc00,0x00000040,
 305 0xc04,0x00005433,
 306 0xc08,0x000000e4,
 307 0xc0c,0x6c6c6c6c,
 308 0xc10,0x08800000,
 309 0xc14,0x40000100,
 310 0xc18,0x08000000,
 311 0xc1c,0x40000100,
 312 0xc20,0x08000000,
 313 0xc24,0x40000100,
 314 0xc28,0x08000000,
 315 0xc2c,0x40000100,
 316 0xc30,0x6de9ac44,
 317 0xc34,0x465c52cd,
 318 0xc38,0x497f5994,
 319 0xc3c,0x0a969764,
 320 0xc40,0x1f7c403f,
 321 0xc44,0x000100b7,
 322 0xc48,0xec020000,
 323 0xc4c,0x00000300,
 324 0xc50,0x69543420,
 325 0xc54,0x433c0094,
 326 0xc58,0x69543420,
 327 0xc5c,0x433c0094,
 328 0xc60,0x69543420,
 329 0xc64,0x433c0094,
 330 0xc68,0x69543420,
 331 0xc6c,0x433c0094,
 332 0xc70,0x2c7f000d,
 333 0xc74,0x0186175b,
 334 0xc78,0x0000001f,
 335 0xc7c,0x00b91612,
 336 0xc80,0x40000100,
 337 0xc84,0x20000000,
 338 0xc88,0x40000100,
 339 0xc8c,0x20200000,
 340 0xc90,0x40000100,
 341 0xc94,0x00000000,
 342 0xc98,0x40000100,
 343 0xc9c,0x00000000,
 344 0xca0,0x00492492,
 345 0xca4,0x00000000,
 346 0xca8,0x00000000,
 347 0xcac,0x00000000,
 348 0xcb0,0x00000000,
 349 0xcb4,0x00000000,
 350 0xcb8,0x00000000,
 351 0xcbc,0x00492492,
 352 0xcc0,0x00000000,
 353 0xcc4,0x00000000,
 354 0xcc8,0x00000000,
 355 0xccc,0x00000000,
 356 0xcd0,0x00000000,
 357 0xcd4,0x00000000,
 358 0xcd8,0x64b22427,
 359 0xcdc,0x00766932,
 360 0xce0,0x00222222,
 361 0xd00,0x00000750,
 362 0xd04,0x00000403,
 363 0xd08,0x0000907f,
 364 0xd0c,0x00000001,
 365 0xd10,0xa0633333,
 366 0xd14,0x33333c63,
 367 0xd18,0x6a8f5b6b,
 368 0xd1c,0x00000000,
 369 0xd20,0x00000000,
 370 0xd24,0x00000000,
 371 0xd28,0x00000000,
 372 0xd2c,0xcc979975,
 373 0xd30,0x00000000,
 374 0xd34,0x00000000,
 375 0xd38,0x00000000,
 376 0xd3c,0x00027293,
 377 0xd40,0x00000000,
 378 0xd44,0x00000000,
 379 0xd48,0x00000000,
 380 0xd4c,0x00000000,
 381 0xd50,0x6437140a,
 382 0xd54,0x024dbd02,
 383 0xd58,0x00000000,
 384 0xd5c,0x04032064,
 385 0xe00,0x161a1a1a,
 386 0xe04,0x12121416,
 387 0xe08,0x00001800,
 388 0xe0c,0x00000000,
 389 0xe10,0x161a1a1a,
 390 0xe14,0x12121416,
 391 0xe18,0x161a1a1a,
 392 0xe1c,0x12121416,
 393 };
 394 static u32 Rtl8192PciERadioA_Array[RadioA_ArrayLength] = {
 395 0x019,0x00000003,
 396 0x000,0x000000bf,
 397 0x001,0x00000ee0,
 398 0x002,0x0000004c,
 399 0x003,0x000007f1,
 400 0x004,0x00000975,
 401 0x005,0x00000c58,
 402 0x006,0x00000ae6,
 403 0x007,0x000000ca,
 404 0x008,0x00000e1c,
 405 0x009,0x000007f0,
 406 0x00a,0x000009d0,
 407 0x00b,0x000001ba,
 408 0x00c,0x00000240,
 409 0x00e,0x00000020,
 410 0x00f,0x00000990,
 411 0x012,0x00000806,
 412 0x014,0x000005ab,
 413 0x015,0x00000f80,
 414 0x016,0x00000020,
 415 0x017,0x00000597,
 416 0x018,0x0000050a,
 417 0x01a,0x00000f80,
 418 0x01b,0x00000f5e,
 419 0x01c,0x00000008,
 420 0x01d,0x00000607,
 421 0x01e,0x000006cc,
 422 0x01f,0x00000000,
 423 0x020,0x000001a5,
 424 0x01f,0x00000001,
 425 0x020,0x00000165,
 426 0x01f,0x00000002,
 427 0x020,0x000000c6,
 428 0x01f,0x00000003,
 429 0x020,0x00000086,
 430 0x01f,0x00000004,
 431 0x020,0x00000046,
 432 0x01f,0x00000005,
 433 0x020,0x000001e6,
 434 0x01f,0x00000006,
 435 0x020,0x000001a6,
 436 0x01f,0x00000007,
 437 0x020,0x00000166,
 438 0x01f,0x00000008,
 439 0x020,0x000000c7,
 440 0x01f,0x00000009,
 441 0x020,0x00000087,
 442 0x01f,0x0000000a,
 443 0x020,0x000000f7,
 444 0x01f,0x0000000b,
 445 0x020,0x000000d7,
 446 0x01f,0x0000000c,
 447 0x020,0x000000b7,
 448 0x01f,0x0000000d,
 449 0x020,0x00000097,
 450 0x01f,0x0000000e,
 451 0x020,0x00000077,
 452 0x01f,0x0000000f,
 453 0x020,0x00000057,
 454 0x01f,0x00000010,
 455 0x020,0x00000037,
 456 0x01f,0x00000011,
 457 0x020,0x000000fb,
 458 0x01f,0x00000012,
 459 0x020,0x000000db,
 460 0x01f,0x00000013,
 461 0x020,0x000000bb,
 462 0x01f,0x00000014,
 463 0x020,0x000000ff,
 464 0x01f,0x00000015,
 465 0x020,0x000000e3,
 466 0x01f,0x00000016,
 467 0x020,0x000000c3,
 468 0x01f,0x00000017,
 469 0x020,0x000000a3,
 470 0x01f,0x00000018,
 471 0x020,0x00000083,
 472 0x01f,0x00000019,
 473 0x020,0x00000063,
 474 0x01f,0x0000001a,
 475 0x020,0x00000043,
 476 0x01f,0x0000001b,
 477 0x020,0x00000023,
 478 0x01f,0x0000001c,
 479 0x020,0x00000003,
 480 0x01f,0x0000001d,
 481 0x020,0x000001e3,
 482 0x01f,0x0000001e,
 483 0x020,0x000001c3,
 484 0x01f,0x0000001f,
 485 0x020,0x000001a3,
 486 0x01f,0x00000020,
 487 0x020,0x00000183,
 488 0x01f,0x00000021,
 489 0x020,0x00000163,
 490 0x01f,0x00000022,
 491 0x020,0x00000143,
 492 0x01f,0x00000023,
 493 0x020,0x00000123,
 494 0x01f,0x00000024,
 495 0x020,0x00000103,
 496 0x023,0x00000203,
 497 0x024,0x00000100,
 498 0x00b,0x000001ba,
 499 0x02c,0x000003d7,
 500 0x02d,0x00000ff0,
 501 0x000,0x00000037,
 502 0x004,0x00000160,
 503 0x007,0x00000080,
 504 0x002,0x0000088d,
 505 0x0fe,0x00000000,
 506 0x0fe,0x00000000,
 507 0x016,0x00000200,
 508 0x016,0x00000380,
 509 0x016,0x00000020,
 510 0x016,0x000001a0,
 511 0x000,0x000000bf,
 512 0x00d,0x0000001f,
 513 0x00d,0x00000c9f,
 514 0x002,0x0000004d,
 515 0x000,0x00000cbf,
 516 0x004,0x00000975,
 517 0x007,0x00000700,
 518 };
 519 static u32 Rtl8192PciERadioB_Array[RadioB_ArrayLength] = {
 520 0x019,0x00000003,
 521 0x000,0x000000bf,
 522 0x001,0x000006e0,
 523 0x002,0x0000004c,
 524 0x003,0x000007f1,
 525 0x004,0x00000975,
 526 0x005,0x00000c58,
 527 0x006,0x00000ae6,
 528 0x007,0x000000ca,
 529 0x008,0x00000e1c,
 530 0x000,0x000000b7,
 531 0x00a,0x00000850,
 532 0x000,0x000000bf,
 533 0x00b,0x000001ba,
 534 0x00c,0x00000240,
 535 0x00e,0x00000020,
 536 0x015,0x00000f80,
 537 0x016,0x00000020,
 538 0x017,0x00000597,
 539 0x018,0x0000050a,
 540 0x01a,0x00000e00,
 541 0x01b,0x00000f5e,
 542 0x01d,0x00000607,
 543 0x01e,0x000006cc,
 544 0x00b,0x000001ba,
 545 0x023,0x00000203,
 546 0x024,0x00000100,
 547 0x000,0x00000037,
 548 0x004,0x00000160,
 549 0x016,0x00000200,
 550 0x016,0x00000380,
 551 0x016,0x00000020,
 552 0x016,0x000001a0,
 553 0x00d,0x00000ccc,
 554 0x000,0x000000bf,
 555 0x002,0x0000004d,
 556 0x000,0x00000cbf,
 557 0x004,0x00000975,
 558 0x007,0x00000700,
 559 };
 560 static u32 Rtl8192PciERadioC_Array[RadioC_ArrayLength] = {
 561 0x0,  };
 562 static u32 Rtl8192PciERadioD_Array[RadioD_ArrayLength] = {
 563 0x0, };
 564
 565 /*************************Define local function prototype**********************/
 566
 567 static u32 phy_FwRFSerialRead(struct r8192_priv *priv, RF90_RADIO_PATH_E eRFPath, u32 Offset);
 568 static void phy_FwRFSerialWrite(struct r8192_priv *priv, RF90_RADIO_PATH_E eRFPath, u32 Offset, u32 Data);
 569
 570 /*************************Define local function prototype**********************/
 571 /******************************************************************************
 572  *function:  This function read BB parameters from Header file we gen,
 573  *           and do register read/write
 574  *   input:  u32        dwBitMask  //taget bit pos in the addr to be modified
 575  *  output:  none
 576  *  return:  u32        return the shift bit bit position of the mask
 577  * ****************************************************************************/
 578 static u32 rtl8192_CalculateBitShift(u32 dwBitMask)
 579 {
 580         u32 i;
 581         for (i=0; i<=31; i++)
 582         {
 583                 if (((dwBitMask>>i)&0x1) == 1)
 584                         break;
 585         }
 586         return i;
 587 }
 588 /******************************************************************************
 589  *function:  This function check different RF type to execute legal judgement. If RF Path is illegal, we will return false.
 590  *   input:  none
 591  *  output:  none
 592  *  return:  0(illegal, false), 1(legal,true)
 593  * ***************************************************************************/
 594 u8 rtl8192_phy_CheckIsLegalRFPath(struct r8192_priv *priv, u32 eRFPath)
 595 {
 596         u8 ret = 1;
 597
 598         if (priv->rf_type == RF_2T4R)
 599                 ret = 0;
 600         else if (priv->rf_type == RF_1T2R)
 601         {
 602                 if (eRFPath == RF90_PATH_A || eRFPath == RF90_PATH_B)
 603                         ret = 1;
 604                 else if (eRFPath == RF90_PATH_C || eRFPath == RF90_PATH_D)
 605                         ret = 0;
 606         }
 607
 608         return ret;
 609 }
 610 /******************************************************************************
 611  *function:  This function set specific bits to BB register
 612  *   input:  net_device dev
 613  *           u32        dwRegAddr  //target addr to be modified
 614  *           u32        dwBitMask  //taget bit pos in the addr to be modified
 615  *           u32        dwData     //value to be write
 616  *  output:  none
 617  *  return:  none
 618  *  notice:
 619  * ****************************************************************************/
 620 void rtl8192_setBBreg(struct r8192_priv *priv, u32 dwRegAddr, u32 dwBitMask, u32 dwData)
 621 {
 622         u32 OriginalValue, BitShift, NewValue;
 623
 624         if(dwBitMask!= bMaskDWord)
 625         {//if not "double word" write
 626                 OriginalValue = read_nic_dword(priv, dwRegAddr);
 627                 BitShift = rtl8192_CalculateBitShift(dwBitMask);
 628                 NewValue = (((OriginalValue) & (~dwBitMask)) | (dwData << BitShift));
 629                 write_nic_dword(priv, dwRegAddr, NewValue);
 630         }else
 631                 write_nic_dword(priv, dwRegAddr, dwData);
 632 }
 633 /******************************************************************************
 634  *function:  This function reads specific bits from BB register
 635  *   input:  net_device dev
 636  *           u32        dwRegAddr  //target addr to be readback
 637  *           u32        dwBitMask  //taget bit pos in the addr to be readback
 638  *  output:  none
 639  *  return:  u32        Data    //the readback register value
 640  *  notice:
 641  * ****************************************************************************/
 642 u32 rtl8192_QueryBBReg(struct r8192_priv *priv, u32 dwRegAddr, u32 dwBitMask)
 643 {
 644         u32 OriginalValue, BitShift;
 645
 646         OriginalValue = read_nic_dword(priv, dwRegAddr);
 647         BitShift = rtl8192_CalculateBitShift(dwBitMask);
 648         return (OriginalValue & dwBitMask) >> BitShift;
 649 }
 650 /******************************************************************************
 651  *function:  This function read register from RF chip
 652  *   input:  net_device dev
 653  *           RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D
 654  *           u32        Offset     //target address to be read
 655  *  output:  none
 656  *  return:  u32        readback value
 657  *  notice:  There are three types of serial operations:(1) Software serial write.(2)Hardware LSSI-Low Speed Serial Interface.(3)Hardware HSSI-High speed serial write. Driver here need to implement (1) and (2)---need more spec for this information.
 658  * ****************************************************************************/
 659 static u32 rtl8192_phy_RFSerialRead(struct r8192_priv *priv,
 660                                     RF90_RADIO_PATH_E eRFPath, u32 Offset)
 661 {
 662         u32 ret = 0;
 663         u32 NewOffset = 0;
 664         BB_REGISTER_DEFINITION_T* pPhyReg = &priv->PHYRegDef[eRFPath];
 665         //rtl8192_setBBreg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData, 0);
 666         //make sure RF register offset is correct
 667         Offset &= 0x3f;
 668
 669         //switch page for 8256 RF IC
 670         //analog to digital off, for protection
 671         rtl8192_setBBreg(priv, rFPGA0_AnalogParameter4, 0xf00, 0x0);// 0x88c[11:8]
 672         if (Offset >= 31)
 673         {
 674                 priv->RfReg0Value[eRFPath] |= 0x140;
 675                 //Switch to Reg_Mode2 for Reg 31-45
 676                 rtl8192_setBBreg(priv, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16) );
 677                 //modify offset
 678                 NewOffset = Offset -30;
 679         }
 680         else if (Offset >= 16)
 681         {
 682                 priv->RfReg0Value[eRFPath] |= 0x100;
 683                 priv->RfReg0Value[eRFPath] &= (~0x40);
 684                 //Switch to Reg_Mode 1 for Reg16-30
 685                 rtl8192_setBBreg(priv, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16) );
 686
 687                 NewOffset = Offset - 15;
 688         }
 689         else
 690                 NewOffset = Offset;
 691
 692         //put desired read addr to LSSI control Register
 693         rtl8192_setBBreg(priv, pPhyReg->rfHSSIPara2, bLSSIReadAddress, NewOffset);
 694         //Issue a posedge trigger
 695         //
 696         rtl8192_setBBreg(priv, pPhyReg->rfHSSIPara2,  bLSSIReadEdge, 0x0);
 697         rtl8192_setBBreg(priv, pPhyReg->rfHSSIPara2,  bLSSIReadEdge, 0x1);
 698
 699
 700         // TODO: we should not delay such a  long time. Ask help from SD3
 701         msleep(1);
 702
 703         ret = rtl8192_QueryBBReg(priv, pPhyReg->rfLSSIReadBack, bLSSIReadBackData);
 704
 705
 706         // Switch back to Reg_Mode0;
 707         priv->RfReg0Value[eRFPath] &= 0xebf;
 708
 709         rtl8192_setBBreg(
 710                 priv,
 711                 pPhyReg->rf3wireOffset,
 712                 bMaskDWord,
 713                 (priv->RfReg0Value[eRFPath] << 16));
 714
 715         //analog to digital on
 716         rtl8192_setBBreg(priv, rFPGA0_AnalogParameter4, 0x300, 0x3);// 0x88c[9:8]
 717
 718         return ret;
 719 }
 720
 721 /******************************************************************************
 722  *function:  This function write data to RF register
 723  *   input:  net_device dev
 724  *           RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D
 725  *           u32        Offset     //target address to be written
 726  *           u32        Data    //The new register data to be written
 727  *  output:  none
 728  *  return:  none
 729  *  notice:  For RF8256 only.
 730   ===========================================================
 731  *Reg Mode      RegCTL[1]       RegCTL[0]               Note
 732  *              (Reg00[12])     (Reg00[10])
 733  *===========================================================
 734  *Reg_Mode0     0               x                       Reg 0 ~15(0x0 ~ 0xf)
 735  *------------------------------------------------------------------
 736  *Reg_Mode1     1               0                       Reg 16 ~30(0x1 ~ 0xf)
 737  *------------------------------------------------------------------
 738  * Reg_Mode2    1               1                       Reg 31 ~ 45(0x1 ~ 0xf)
 739  *------------------------------------------------------------------
 740  * ****************************************************************************/
 741 static void rtl8192_phy_RFSerialWrite(struct r8192_priv *priv,
 742                                       RF90_RADIO_PATH_E eRFPath, u32 Offset,
 743                                       u32 Data)
 744 {
 745         u32 DataAndAddr = 0, NewOffset = 0;
 746         BB_REGISTER_DEFINITION_T        *pPhyReg = &priv->PHYRegDef[eRFPath];
 747
 748         Offset &= 0x3f;
 749
 750         //analog to digital off, for protection
 751         rtl8192_setBBreg(priv, rFPGA0_AnalogParameter4, 0xf00, 0x0);// 0x88c[11:8]
 752
 753         if (Offset >= 31)
 754         {
 755                 priv->RfReg0Value[eRFPath] |= 0x140;
 756                 rtl8192_setBBreg(priv, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath] << 16));
 757                 NewOffset = Offset - 30;
 758         }
 759         else if (Offset >= 16)
 760         {
 761                 priv->RfReg0Value[eRFPath] |= 0x100;
 762                 priv->RfReg0Value[eRFPath] &= (~0x40);
 763                 rtl8192_setBBreg(priv, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16));
 764                 NewOffset = Offset - 15;
 765         }
 766         else
 767                 NewOffset = Offset;
 768
 769         // Put write addr in [5:0]  and write data in [31:16]
 770         DataAndAddr = (Data<<16) | (NewOffset&0x3f);
 771
 772         // Write Operation
 773         rtl8192_setBBreg(priv, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
 774
 775
 776         if(Offset==0x0)
 777                 priv->RfReg0Value[eRFPath] = Data;
 778
 779         // Switch back to Reg_Mode0;
 780         if(Offset != 0)
 781         {
 782                 priv->RfReg0Value[eRFPath] &= 0xebf;
 783                 rtl8192_setBBreg(
 784                         priv,
 785                         pPhyReg->rf3wireOffset,
 786                         bMaskDWord,
 787                         (priv->RfReg0Value[eRFPath] << 16));
 788         }
 789         //analog to digital on
 790         rtl8192_setBBreg(priv, rFPGA0_AnalogParameter4, 0x300, 0x3);// 0x88c[9:8]
 791 }
 792
 793 /******************************************************************************
 794  *function:  This function set specific bits to RF register
 795  *   input:  RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D
 796  *           u32        RegAddr  //target addr to be modified
 797  *           u32        BitMask  //taget bit pos in the addr to be modified
 798  *           u32        Data     //value to be write
 799  *  output:  none
 800  *  return:  none
 801  *  notice:
 802  * ****************************************************************************/
 803 void rtl8192_phy_SetRFReg(struct r8192_priv *priv, RF90_RADIO_PATH_E eRFPath,
 804                           u32 RegAddr, u32 BitMask, u32 Data)
 805 {
 806         u32 Original_Value, BitShift, New_Value;
 807 //      u8      time = 0;
 808
 809         if (!rtl8192_phy_CheckIsLegalRFPath(priv, eRFPath))
 810                 return;
 811         if (priv->eRFPowerState != eRfOn && !priv->being_init_adapter)
 812                 return;
 813         //down(&priv->rf_sem);
 814
 815         RT_TRACE(COMP_PHY, "FW RF CTRL is not ready now\n");
 816         if (priv->Rf_Mode == RF_OP_By_FW)
 817         {
 818                 if (BitMask != bMask12Bits) // RF data is 12 bits only
 819                 {
 820                         Original_Value = phy_FwRFSerialRead(priv, eRFPath, RegAddr);
 821                         BitShift =  rtl8192_CalculateBitShift(BitMask);
 822                         New_Value = (((Original_Value) & (~BitMask)) | (Data<< BitShift));
 823
 824                         phy_FwRFSerialWrite(priv, eRFPath, RegAddr, New_Value);
 825                 }else
 826                         phy_FwRFSerialWrite(priv, eRFPath, RegAddr, Data);
 827                 udelay(200);
 828
 829         }
 830         else
 831         {
 832                 if (BitMask != bMask12Bits) // RF data is 12 bits only
 833                 {
 834                         Original_Value = rtl8192_phy_RFSerialRead(priv, eRFPath, RegAddr);
 835                         BitShift =  rtl8192_CalculateBitShift(BitMask);
 836                         New_Value = (((Original_Value) & (~BitMask)) | (Data<< BitShift));
 837
 838                         rtl8192_phy_RFSerialWrite(priv, eRFPath, RegAddr, New_Value);
 839                 }else
 840                         rtl8192_phy_RFSerialWrite(priv, eRFPath, RegAddr, Data);
 841         }
 842         //up(&priv->rf_sem);
 843 }
 844
 845 /******************************************************************************
 846  *function:  This function reads specific bits from RF register
 847  *   input:  net_device dev
 848  *           u32        RegAddr  //target addr to be readback
 849  *           u32        BitMask  //taget bit pos in the addr to be readback
 850  *  output:  none
 851  *  return:  u32        Data    //the readback register value
 852  *  notice:
 853  * ****************************************************************************/
 854 u32 rtl8192_phy_QueryRFReg(struct r8192_priv *priv, RF90_RADIO_PATH_E eRFPath,
 855                            u32 RegAddr, u32 BitMask)
 856 {
 857         u32 Original_Value, Readback_Value, BitShift;
 858
 859         if (!rtl8192_phy_CheckIsLegalRFPath(priv, eRFPath))
 860                 return 0;
 861         if (priv->eRFPowerState != eRfOn && !priv->being_init_adapter)
 862                 return  0;
 863         down(&priv->rf_sem);
 864         if (priv->Rf_Mode == RF_OP_By_FW)
 865         {
 866                 Original_Value = phy_FwRFSerialRead(priv, eRFPath, RegAddr);
 867                 udelay(200);
 868         }
 869         else
 870         {
 871                 Original_Value = rtl8192_phy_RFSerialRead(priv, eRFPath, RegAddr);
 872
 873         }
 874         BitShift =  rtl8192_CalculateBitShift(BitMask);
 875         Readback_Value = (Original_Value & BitMask) >> BitShift;
 876         up(&priv->rf_sem);
 877 //      udelay(200);
 878         return Readback_Value;
 879 }
 880
 881 /******************************************************************************
 882  *function:  We support firmware to execute RF-R/W.
 883  *   input:  dev
 884  *  output:  none
 885  *  return:  none
 886  *  notice:
 887  * ***************************************************************************/
 888 static u32 phy_FwRFSerialRead(struct r8192_priv *priv,
 889                               RF90_RADIO_PATH_E eRFPath, u32 Offset)
 890 {
 891         u32             Data = 0;
 892         u8              time = 0;
 893         //DbgPrint("FW RF CTRL\n\r");
 894         /* 2007/11/02 MH Firmware RF Write control. By Francis' suggestion, we can
 895            not execute the scheme in the initial step. Otherwise, RF-R/W will waste
 896            much time. This is only for site survey. */
 897         // 1. Read operation need not insert data. bit 0-11
 898         //Data &= bMask12Bits;
 899         // 2. Write RF register address. Bit 12-19
 900         Data |= ((Offset&0xFF)<<12);
 901         // 3. Write RF path.  bit 20-21
 902         Data |= ((eRFPath&0x3)<<20);
 903         // 4. Set RF read indicator. bit 22=0
 904         //Data |= 0x00000;
 905         // 5. Trigger Fw to operate the command. bit 31
 906         Data |= 0x80000000;
 907         // 6. We can not execute read operation if bit 31 is 1.
 908         while (read_nic_dword(priv, QPNR)&0x80000000)
 909         {
 910                 // If FW can not finish RF-R/W for more than ?? times. We must reset FW.
 911                 if (time++ < 100)
 912                 {
 913                         //DbgPrint("FW not finish RF-R Time=%d\n\r", time);
 914                         udelay(10);
 915                 }
 916                 else
 917                         break;
 918         }
 919         // 7. Execute read operation.
 920         write_nic_dword(priv, QPNR, Data);
 921         // 8. Check if firmawre send back RF content.
 922         while (read_nic_dword(priv, QPNR)&0x80000000)
 923         {
 924                 // If FW can not finish RF-R/W for more than ?? times. We must reset FW.
 925                 if (time++ < 100)
 926                 {
 927                         //DbgPrint("FW not finish RF-W Time=%d\n\r", time);
 928                         udelay(10);
 929                 }
 930                 else
 931                         return 0;
 932         }
 933         return read_nic_dword(priv, RF_DATA);
 934 }
 935
 936 /******************************************************************************
 937  *function:  We support firmware to execute RF-R/W.
 938  *   input:  dev
 939  *  output:  none
 940  *  return:  none
 941  *  notice:
 942  * ***************************************************************************/
 943 static void phy_FwRFSerialWrite(struct r8192_priv *priv,
 944                                 RF90_RADIO_PATH_E eRFPath, u32 Offset, u32 Data)
 945 {
 946         u8      time = 0;
 947
 948         //DbgPrint("N FW RF CTRL RF-%d OF%02x DATA=%03x\n\r", eRFPath, Offset, Data);
 949         /* 2007/11/02 MH Firmware RF Write control. By Francis' suggestion, we can
 950            not execute the scheme in the initial step. Otherwise, RF-R/W will waste
 951            much time. This is only for site survey. */
 952
 953         // 1. Set driver write bit and 12 bit data. bit 0-11
 954         //Data &= bMask12Bits;  // Done by uper layer.
 955         // 2. Write RF register address. bit 12-19
 956         Data |= ((Offset&0xFF)<<12);
 957         // 3. Write RF path.  bit 20-21
 958         Data |= ((eRFPath&0x3)<<20);
 959         // 4. Set RF write indicator. bit 22=1
 960         Data |= 0x400000;
 961         // 5. Trigger Fw to operate the command. bit 31=1
 962         Data |= 0x80000000;
 963
 964         // 6. Write operation. We can not write if bit 31 is 1.
 965         while (read_nic_dword(priv, QPNR)&0x80000000)
 966         {
 967                 // If FW can not finish RF-R/W for more than ?? times. We must reset FW.
 968                 if (time++ < 100)
 969                 {
 970                         //DbgPrint("FW not finish RF-W Time=%d\n\r", time);
 971                         udelay(10);
 972                 }
 973                 else
 974                         break;
 975         }
 976         // 7. No matter check bit. We always force the write. Because FW will
 977         //    not accept the command.
 978         write_nic_dword(priv, QPNR, Data);
 979         /* 2007/11/02 MH Acoording to test, we must delay 20us to wait firmware
 980            to finish RF write operation. */
 981         /* 2008/01/17 MH We support delay in firmware side now. */
 982         //delay_us(20);
 983
 984 }
 985
 986
 987 /******************************************************************************
 988  *function:  This function read BB parameters from Header file we gen,
 989  *           and do register read/write
 990  *   input:  dev
 991  *  output:  none
 992  *  return:  none
 993  *  notice:  BB parameters may change all the time, so please make
 994  *           sure it has been synced with the newest.
 995  * ***************************************************************************/
 996 void rtl8192_phy_configmac(struct r8192_priv *priv)
 997 {
 998         u32 dwArrayLen = 0, i = 0;
 999         u32* pdwArray = NULL;
1000 #ifdef TO_DO_LIST
1001 if(Adapter->bInHctTest)
1002         {
1003                 RT_TRACE(COMP_PHY, "Rtl819XMACPHY_ArrayDTM\n");
1004                 dwArrayLen = MACPHY_ArrayLengthDTM;
1005                 pdwArray = Rtl819XMACPHY_ArrayDTM;
1006         }
1007         else if(priv->bTXPowerDataReadFromEEPORM)
1008 #endif
1009          if(priv->bTXPowerDataReadFromEEPORM)
1010         {
1011                 RT_TRACE(COMP_PHY, "Rtl819XMACPHY_Array_PG\n");
1012                 dwArrayLen = MACPHY_Array_PGLength;
1013                 pdwArray = Rtl819XMACPHY_Array_PG;
1014
1015         }
1016         else
1017         {
1018                 RT_TRACE(COMP_PHY,"Read rtl819XMACPHY_Array\n");
1019                 dwArrayLen = MACPHY_ArrayLength;
1020                 pdwArray = Rtl819XMACPHY_Array;
1021         }
1022         for(i = 0; i<dwArrayLen; i=i+3){
1023                 RT_TRACE(COMP_DBG, "The Rtl8190MACPHY_Array[0] is %x Rtl8190MACPHY_Array[1] is %x Rtl8190MACPHY_Array[2] is %x\n",
1024                                 pdwArray[i], pdwArray[i+1], pdwArray[i+2]);
1025                 if(pdwArray[i] == 0x318)
1026                 {
1027                         pdwArray[i+2] = 0x00000800;
1028                         //DbgPrint("ptrArray[i], ptrArray[i+1], ptrArray[i+2] = %x, %x, %x\n",
1029                         //      ptrArray[i], ptrArray[i+1], ptrArray[i+2]);
1030                 }
1031                 rtl8192_setBBreg(priv, pdwArray[i], pdwArray[i+1], pdwArray[i+2]);
1032         }
1033 }
1034
1035 /******************************************************************************
1036  *function:  This function do dirty work
1037  *   input:  dev
1038  *  output:  none
1039  *  return:  none
1040  *  notice:  BB parameters may change all the time, so please make
1041  *           sure it has been synced with the newest.
1042  * ***************************************************************************/
1043
1044 void rtl8192_phyConfigBB(struct r8192_priv *priv, u8 ConfigType)
1045 {
1046         int i;
1047         //u8 ArrayLength;
1048         u32*    Rtl819XPHY_REGArray_Table = NULL;
1049         u32*    Rtl819XAGCTAB_Array_Table = NULL;
1050         u16     AGCTAB_ArrayLen, PHY_REGArrayLen = 0;
1051 #ifdef TO_DO_LIST
1052         u32 *rtl8192PhyRegArrayTable = NULL, *rtl8192AgcTabArrayTable = NULL;
1053         if(Adapter->bInHctTest)
1054         {
1055                 AGCTAB_ArrayLen = AGCTAB_ArrayLengthDTM;
1056                 Rtl819XAGCTAB_Array_Table = Rtl819XAGCTAB_ArrayDTM;
1057
1058                 if(priv->RF_Type == RF_2T4R)
1059                 {
1060                         PHY_REGArrayLen = PHY_REGArrayLengthDTM;
1061                         Rtl819XPHY_REGArray_Table = Rtl819XPHY_REGArrayDTM;
1062                 }
1063                 else if (priv->RF_Type == RF_1T2R)
1064                 {
1065                         PHY_REGArrayLen = PHY_REG_1T2RArrayLengthDTM;
1066                         Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_1T2RArrayDTM;
1067                 }
1068         }
1069         else
1070 #endif
1071         {
1072                 AGCTAB_ArrayLen = AGCTAB_ArrayLength;
1073                 Rtl819XAGCTAB_Array_Table = Rtl819XAGCTAB_Array;
1074                 if(priv->rf_type == RF_2T4R)
1075                 {
1076                         PHY_REGArrayLen = PHY_REGArrayLength;
1077                         Rtl819XPHY_REGArray_Table = Rtl819XPHY_REGArray;
1078                 }
1079                 else if (priv->rf_type == RF_1T2R)
1080                 {
1081                         PHY_REGArrayLen = PHY_REG_1T2RArrayLength;
1082                         Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_1T2RArray;
1083                 }
1084         }
1085
1086         if (ConfigType == BaseBand_Config_PHY_REG)
1087         {
1088                 for (i=0; i<PHY_REGArrayLen; i+=2)
1089                 {
1090                         rtl8192_setBBreg(priv, Rtl819XPHY_REGArray_Table[i], bMaskDWord, Rtl819XPHY_REGArray_Table[i+1]);
1091                         RT_TRACE(COMP_DBG, "i: %x, The Rtl819xUsbPHY_REGArray[0] is %x Rtl819xUsbPHY_REGArray[1] is %x\n",i, Rtl819XPHY_REGArray_Table[i], Rtl819XPHY_REGArray_Table[i+1]);
1092                 }
1093         }
1094         else if (ConfigType == BaseBand_Config_AGC_TAB)
1095         {
1096                 for (i=0; i<AGCTAB_ArrayLen; i+=2)
1097                 {
1098                         rtl8192_setBBreg(priv, Rtl819XAGCTAB_Array_Table[i], bMaskDWord, Rtl819XAGCTAB_Array_Table[i+1]);
1099                         RT_TRACE(COMP_DBG, "i:%x, The rtl819XAGCTAB_Array[0] is %x rtl819XAGCTAB_Array[1] is %x\n",i, Rtl819XAGCTAB_Array_Table[i], Rtl819XAGCTAB_Array_Table[i+1]);
1100                 }
1101         }
1102 }
1103 /******************************************************************************
1104  *function:  This function initialize Register definition offset for Radio Path
1105  *           A/B/C/D
1106  *   input:  net_device dev
1107  *  output:  none
1108  *  return:  none
1109  *  notice:  Initialization value here is constant and it should never be changed
1110  * ***************************************************************************/
1111 static void rtl8192_InitBBRFRegDef(struct r8192_priv *priv)
1112 {
1113 // RF Interface Sowrtware Control
1114         priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 LSBs if read 32-bit from 0x870
1115         priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872)
1116         priv->PHYRegDef[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 LSBs if read 32-bit from 0x874
1117         priv->PHYRegDef[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876)
1118
1119         // RF Interface Readback Value
1120         priv->PHYRegDef[RF90_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB; // 16 LSBs if read 32-bit from 0x8E0
1121         priv->PHYRegDef[RF90_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB;// 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2)
1122         priv->PHYRegDef[RF90_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB;// 16 LSBs if read 32-bit from 0x8E4
1123         priv->PHYRegDef[RF90_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB;// 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6)
1124
1125         // RF Interface Output (and Enable)
1126         priv->PHYRegDef[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x860
1127         priv->PHYRegDef[RF90_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x864
1128         priv->PHYRegDef[RF90_PATH_C].rfintfo = rFPGA0_XC_RFInterfaceOE;// 16 LSBs if read 32-bit from 0x868
1129         priv->PHYRegDef[RF90_PATH_D].rfintfo = rFPGA0_XD_RFInterfaceOE;// 16 LSBs if read 32-bit from 0x86C
1130
1131         // RF Interface (Output and)  Enable
1132         priv->PHYRegDef[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862)
1133         priv->PHYRegDef[RF90_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866)
1134         priv->PHYRegDef[RF90_PATH_C].rfintfe = rFPGA0_XC_RFInterfaceOE;// 16 MSBs if read 32-bit from 0x86A (16-bit for 0x86A)
1135         priv->PHYRegDef[RF90_PATH_D].rfintfe = rFPGA0_XD_RFInterfaceOE;// 16 MSBs if read 32-bit from 0x86C (16-bit for 0x86E)
1136
1137         //Addr of LSSI. Wirte RF register by driver
1138         priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; //LSSI Parameter
1139         priv->PHYRegDef[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter;
1140         priv->PHYRegDef[RF90_PATH_C].rf3wireOffset = rFPGA0_XC_LSSIParameter;
1141         priv->PHYRegDef[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter;
1142
1143         // RF parameter
1144         priv->PHYRegDef[RF90_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter;  //BB Band Select
1145         priv->PHYRegDef[RF90_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter;
1146         priv->PHYRegDef[RF90_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter;
1147         priv->PHYRegDef[RF90_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter;
1148
1149         // Tx AGC Gain Stage (same for all path. Should we remove this?)
1150         priv->PHYRegDef[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
1151         priv->PHYRegDef[RF90_PATH_B].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
1152         priv->PHYRegDef[RF90_PATH_C].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
1153         priv->PHYRegDef[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
1154
1155         // Tranceiver A~D HSSI Parameter-1
1156         priv->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1;  //wire control parameter1
1157         priv->PHYRegDef[RF90_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1;  //wire control parameter1
1158         priv->PHYRegDef[RF90_PATH_C].rfHSSIPara1 = rFPGA0_XC_HSSIParameter1;  //wire control parameter1
1159         priv->PHYRegDef[RF90_PATH_D].rfHSSIPara1 = rFPGA0_XD_HSSIParameter1;  //wire control parameter1
1160
1161         // Tranceiver A~D HSSI Parameter-2
1162         priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2;  //wire control parameter2
1163         priv->PHYRegDef[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2;  //wire control parameter2
1164         priv->PHYRegDef[RF90_PATH_C].rfHSSIPara2 = rFPGA0_XC_HSSIParameter2;  //wire control parameter2
1165         priv->PHYRegDef[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2;  //wire control parameter1
1166
1167         // RF switch Control
1168         priv->PHYRegDef[RF90_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl; //TR/Ant switch control
1169         priv->PHYRegDef[RF90_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl;
1170         priv->PHYRegDef[RF90_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl;
1171         priv->PHYRegDef[RF90_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl;
1172
1173         // AGC control 1
1174         priv->PHYRegDef[RF90_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1;
1175         priv->PHYRegDef[RF90_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1;
1176         priv->PHYRegDef[RF90_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1;
1177         priv->PHYRegDef[RF90_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1;
1178
1179         // AGC control 2
1180         priv->PHYRegDef[RF90_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2;
1181         priv->PHYRegDef[RF90_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2;
1182         priv->PHYRegDef[RF90_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2;
1183         priv->PHYRegDef[RF90_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2;
1184
1185         // RX AFE control 1
1186         priv->PHYRegDef[RF90_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance;
1187         priv->PHYRegDef[RF90_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance;
1188         priv->PHYRegDef[RF90_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance;
1189         priv->PHYRegDef[RF90_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance;
1190
1191         // RX AFE control 1
1192         priv->PHYRegDef[RF90_PATH_A].rfRxAFE = rOFDM0_XARxAFE;
1193         priv->PHYRegDef[RF90_PATH_B].rfRxAFE = rOFDM0_XBRxAFE;
1194         priv->PHYRegDef[RF90_PATH_C].rfRxAFE = rOFDM0_XCRxAFE;
1195         priv->PHYRegDef[RF90_PATH_D].rfRxAFE = rOFDM0_XDRxAFE;
1196
1197         // Tx AFE control 1
1198         priv->PHYRegDef[RF90_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance;
1199         priv->PHYRegDef[RF90_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance;
1200         priv->PHYRegDef[RF90_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance;
1201         priv->PHYRegDef[RF90_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance;
1202
1203         // Tx AFE control 2
1204         priv->PHYRegDef[RF90_PATH_A].rfTxAFE = rOFDM0_XATxAFE;
1205         priv->PHYRegDef[RF90_PATH_B].rfTxAFE = rOFDM0_XBTxAFE;
1206         priv->PHYRegDef[RF90_PATH_C].rfTxAFE = rOFDM0_XCTxAFE;
1207         priv->PHYRegDef[RF90_PATH_D].rfTxAFE = rOFDM0_XDTxAFE;
1208
1209         // Tranceiver LSSI Readback
1210         priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;
1211         priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;
1212         priv->PHYRegDef[RF90_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack;
1213         priv->PHYRegDef[RF90_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack;
1214
1215 }
1216 /******************************************************************************
1217  *function:  This function is to write register and then readback to make sure whether BB and RF is OK
1218  *   input:  net_device dev
1219  *           HW90_BLOCK_E CheckBlock
1220  *           RF90_RADIO_PATH_E eRFPath  //only used when checkblock is HW90_BLOCK_RF
1221  *  output:  none
1222  *  return:  return whether BB and RF is ok(0:OK; 1:Fail)
1223  *  notice:  This function may be removed in the ASIC
1224  * ***************************************************************************/
1225 RT_STATUS rtl8192_phy_checkBBAndRF(struct r8192_priv *priv,
1226                                    HW90_BLOCK_E CheckBlock,
1227                                    RF90_RADIO_PATH_E eRFPath)
1228 {
1229 //      BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath];
1230         RT_STATUS ret = RT_STATUS_SUCCESS;
1231         u32 i, CheckTimes = 4, dwRegRead = 0;
1232         u32 WriteAddr[4];
1233         u32 WriteData[] = {0xfffff027, 0xaa55a02f, 0x00000027, 0x55aa502f};
1234         // Initialize register address offset to be checked
1235         WriteAddr[HW90_BLOCK_MAC] = 0x100;
1236         WriteAddr[HW90_BLOCK_PHY0] = 0x900;
1237         WriteAddr[HW90_BLOCK_PHY1] = 0x800;
1238         WriteAddr[HW90_BLOCK_RF] = 0x3;
1239         RT_TRACE(COMP_PHY, "=======>%s(), CheckBlock:%d\n", __FUNCTION__, CheckBlock);
1240         for(i=0 ; i < CheckTimes ; i++)
1241         {
1242
1243                 //
1244                 // Write Data to register and readback
1245                 //
1246                 switch(CheckBlock)
1247                 {
1248                 case HW90_BLOCK_MAC:
1249                         RT_TRACE(COMP_ERR, "PHY_CheckBBRFOK(): Never Write 0x100 here!\n");
1250                         break;
1251
1252                 case HW90_BLOCK_PHY0:
1253                 case HW90_BLOCK_PHY1:
1254                         write_nic_dword(priv, WriteAddr[CheckBlock], WriteData[i]);
1255                         dwRegRead = read_nic_dword(priv, WriteAddr[CheckBlock]);
1256                         break;
1257
1258                 case HW90_BLOCK_RF:
1259                         WriteData[i] &= 0xfff;
1260                         rtl8192_phy_SetRFReg(priv, eRFPath, WriteAddr[HW90_BLOCK_RF], bMask12Bits, WriteData[i]);
1261                         // TODO: we should not delay for such a long time. Ask SD3
1262                         mdelay(10);
1263                         dwRegRead = rtl8192_phy_QueryRFReg(priv, eRFPath, WriteAddr[HW90_BLOCK_RF], bMaskDWord);
1264                         mdelay(10);
1265                         break;
1266
1267                 default:
1268                         ret = RT_STATUS_FAILURE;
1269                         break;
1270                 }
1271
1272
1273                 //
1274                 // Check whether readback data is correct
1275                 //
1276                 if(dwRegRead != WriteData[i])
1277                 {
1278                         RT_TRACE(COMP_ERR, "====>error=====dwRegRead: %x, WriteData: %x\n", dwRegRead, WriteData[i]);
1279                         ret = RT_STATUS_FAILURE;
1280                         break;
1281                 }
1282         }
1283
1284         return ret;
1285 }
1286
1287
1288 /******************************************************************************
1289  *function:  This function initialize BB&RF
1290  *   input:  net_device dev
1291  *  output:  none
1292  *  return:  none
1293  *  notice:  Initialization value may change all the time, so please make
1294  *           sure it has been synced with the newest.
1295  * ***************************************************************************/
1296 static RT_STATUS rtl8192_BB_Config_ParaFile(struct r8192_priv *priv)
1297 {
1298         RT_STATUS rtStatus = RT_STATUS_SUCCESS;
1299
1300         u8 bRegValue = 0, eCheckItem = 0;
1301         u32 dwRegValue = 0;
1302         /**************************************
1303         //<1>Initialize BaseBand
1304         **************************************/
1305
1306         /*--set BB Global Reset--*/
1307         bRegValue = read_nic_byte(priv, BB_GLOBAL_RESET);
1308         write_nic_byte(priv, BB_GLOBAL_RESET,(bRegValue|BB_GLOBAL_RESET_BIT));
1309
1310         /*---set BB reset Active---*/
1311         dwRegValue = read_nic_dword(priv, CPU_GEN);
1312         write_nic_dword(priv, CPU_GEN, (dwRegValue&(~CPU_GEN_BB_RST)));
1313
1314         /*----Ckeck FPGAPHY0 and PHY1 board is OK----*/
1315         // TODO: this function should be removed on ASIC , Emily 2007.2.2
1316         for(eCheckItem=(HW90_BLOCK_E)HW90_BLOCK_PHY0; eCheckItem<=HW90_BLOCK_PHY1; eCheckItem++)
1317         {
1318                 rtStatus  = rtl8192_phy_checkBBAndRF(priv, (HW90_BLOCK_E)eCheckItem, (RF90_RADIO_PATH_E)0); //don't care RF path
1319                 if(rtStatus != RT_STATUS_SUCCESS)
1320                 {
1321                         RT_TRACE((COMP_ERR | COMP_PHY), "PHY_RF8256_Config():Check PHY%d Fail!!\n", eCheckItem-1);
1322                         return rtStatus;
1323                 }
1324         }
1325         /*---- Set CCK and OFDM Block "OFF"----*/
1326         rtl8192_setBBreg(priv, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x0);
1327         /*----BB Register Initilazation----*/
1328         //==m==>Set PHY REG From Header<==m==
1329         rtl8192_phyConfigBB(priv, BaseBand_Config_PHY_REG);
1330
1331         /*----Set BB reset de-Active----*/
1332         dwRegValue = read_nic_dword(priv, CPU_GEN);
1333         write_nic_dword(priv, CPU_GEN, (dwRegValue|CPU_GEN_BB_RST));
1334
1335         /*----BB AGC table Initialization----*/
1336         //==m==>Set PHY REG From Header<==m==
1337         rtl8192_phyConfigBB(priv, BaseBand_Config_AGC_TAB);
1338
1339         if (priv->card_8192_version  > VERSION_8190_BD)
1340         {
1341                 if(priv->rf_type == RF_2T4R)
1342                 {
1343                 // Antenna gain offset from B/C/D to A
1344                 dwRegValue = (  priv->AntennaTxPwDiff[2]<<8 |
1345                                                 priv->AntennaTxPwDiff[1]<<4 |
1346                                                 priv->AntennaTxPwDiff[0]);
1347                 }
1348                 else
1349                         dwRegValue = 0x0;       //Antenna gain offset doesn't make sense in RF 1T2R.
1350                 rtl8192_setBBreg(priv, rFPGA0_TxGainStage,
1351                         (bXBTxAGC|bXCTxAGC|bXDTxAGC), dwRegValue);
1352
1353
1354                 //XSTALLCap
1355                 dwRegValue = priv->CrystalCap;
1356                 rtl8192_setBBreg(priv, rFPGA0_AnalogParameter1, bXtalCap92x, dwRegValue);
1357         }
1358
1359         // Check if the CCK HighPower is turned ON.
1360         // This is used to calculate PWDB.
1361 //      priv->bCckHighPower = (u8)(rtl8192_QueryBBReg(dev, rFPGA0_XA_HSSIParameter2, 0x200));
1362         return rtStatus;
1363 }
1364 /******************************************************************************
1365  *function:  This function initialize BB&RF
1366  *   input:  net_device dev
1367  *  output:  none
1368  *  return:  none
1369  *  notice:  Initialization value may change all the time, so please make
1370  *           sure it has been synced with the newest.
1371  * ***************************************************************************/
1372 RT_STATUS rtl8192_BBConfig(struct r8192_priv *priv)
1373 {
1374         rtl8192_InitBBRFRegDef(priv);
1375         //config BB&RF. As hardCode based initialization has not been well
1376         //implemented, so use file first.FIXME:should implement it for hardcode?
1377         return rtl8192_BB_Config_ParaFile(priv);
1378 }
1379
1380 /******************************************************************************
1381  *function:  This function obtains the initialization value of Tx power Level offset
1382  *   input:  net_device dev
1383  *  output:  none
1384  *  return:  none
1385  * ***************************************************************************/
1386 void rtl8192_phy_getTxPower(struct r8192_priv *priv)
1387 {
1388         priv->MCSTxPowerLevelOriginalOffset[0] =
1389                 read_nic_dword(priv, rTxAGC_Rate18_06);
1390         priv->MCSTxPowerLevelOriginalOffset[1] =
1391                 read_nic_dword(priv, rTxAGC_Rate54_24);
1392         priv->MCSTxPowerLevelOriginalOffset[2] =
1393                 read_nic_dword(priv, rTxAGC_Mcs03_Mcs00);
1394         priv->MCSTxPowerLevelOriginalOffset[3] =
1395                 read_nic_dword(priv, rTxAGC_Mcs07_Mcs04);
1396         priv->MCSTxPowerLevelOriginalOffset[4] =
1397                 read_nic_dword(priv, rTxAGC_Mcs11_Mcs08);
1398         priv->MCSTxPowerLevelOriginalOffset[5] =
1399                 read_nic_dword(priv, rTxAGC_Mcs15_Mcs12);
1400
1401         // read rx initial gain
1402         priv->DefaultInitialGain[0] = read_nic_byte(priv, rOFDM0_XAAGCCore1);
1403         priv->DefaultInitialGain[1] = read_nic_byte(priv, rOFDM0_XBAGCCore1);
1404         priv->DefaultInitialGain[2] = read_nic_byte(priv, rOFDM0_XCAGCCore1);
1405         priv->DefaultInitialGain[3] = read_nic_byte(priv, rOFDM0_XDAGCCore1);
1406         RT_TRACE(COMP_INIT, "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x)\n",
1407                 priv->DefaultInitialGain[0], priv->DefaultInitialGain[1],
1408                 priv->DefaultInitialGain[2], priv->DefaultInitialGain[3]);
1409
1410         // read framesync
1411         priv->framesync = read_nic_byte(priv, rOFDM0_RxDetector3);
1412         priv->framesyncC34 = read_nic_dword(priv, rOFDM0_RxDetector2);
1413         RT_TRACE(COMP_INIT, "Default framesync (0x%x) = 0x%x\n",
1414                 rOFDM0_RxDetector3, priv->framesync);
1415         // read SIFS (save the value read fome MACPHY_REG.txt)
1416         priv->SifsTime = read_nic_word(priv, SIFS);
1417 }
1418
1419 /******************************************************************************
1420  *function:  This function obtains the initialization value of Tx power Level offset
1421  *   input:  net_device dev
1422  *  output:  none
1423  *  return:  none
1424  * ***************************************************************************/
1425 void rtl8192_phy_setTxPower(struct r8192_priv *priv, u8 channel)
1426 {
1427         u8      powerlevel = 0,powerlevelOFDM24G = 0;
1428         char ant_pwr_diff;
1429         u32     u4RegValue;
1430
1431         if(priv->epromtype == EPROM_93c46)
1432         {
1433                 powerlevel = priv->TxPowerLevelCCK[channel-1];
1434                 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1];
1435         }
1436         else if(priv->epromtype == EPROM_93c56)
1437         {
1438                 if(priv->rf_type == RF_1T2R)
1439                 {
1440                         powerlevel = priv->TxPowerLevelCCK_C[channel-1];
1441                         powerlevelOFDM24G = priv->TxPowerLevelOFDM24G_C[channel-1];
1442                 }
1443                 else if(priv->rf_type == RF_2T4R)
1444                 {
1445                         // Mainly we use RF-A Tx Power to write the Tx Power registers, but the RF-C Tx
1446                         // Power must be calculated by the antenna diff.
1447                         // So we have to rewrite Antenna gain offset register here.
1448                         powerlevel = priv->TxPowerLevelCCK_A[channel-1];
1449                         powerlevelOFDM24G = priv->TxPowerLevelOFDM24G_A[channel-1];
1450
1451                         ant_pwr_diff = priv->TxPowerLevelOFDM24G_C[channel-1]
1452                                                 -priv->TxPowerLevelOFDM24G_A[channel-1];
1453                         ant_pwr_diff &= 0xf;
1454                         //DbgPrint(" ant_pwr_diff = 0x%x", (u8)(ant_pwr_diff));
1455                         priv->RF_C_TxPwDiff = ant_pwr_diff;
1456
1457                         priv->AntennaTxPwDiff[2] = 0;// RF-D, don't care
1458                         priv->AntennaTxPwDiff[1] = (u8)(ant_pwr_diff);// RF-C
1459                         priv->AntennaTxPwDiff[0] = 0;// RF-B, don't care
1460
1461                         // Antenna gain offset from B/C/D to A
1462                         u4RegValue = (  priv->AntennaTxPwDiff[2]<<8 |
1463                                                 priv->AntennaTxPwDiff[1]<<4 |
1464                                                 priv->AntennaTxPwDiff[0]);
1465
1466                         rtl8192_setBBreg(priv, rFPGA0_TxGainStage,
1467                         (bXBTxAGC|bXCTxAGC|bXDTxAGC), u4RegValue);
1468                 }
1469         }
1470 #ifdef TODO
1471         //
1472         // CCX 2 S31, AP control of client transmit power:
1473         // 1. We shall not exceed Cell Power Limit as possible as we can.
1474         // 2. Tolerance is +/- 5dB.
1475         // 3. 802.11h Power Contraint takes higher precedence over CCX Cell Power Limit.
1476         //
1477         // TODO:
1478         // 1. 802.11h power contraint
1479         //
1480         // 071011, by rcnjko.
1481         //
1482         if(     pMgntInfo->OpMode == RT_OP_MODE_INFRASTRUCTURE &&
1483                 pMgntInfo->bWithCcxCellPwr &&
1484                 channel == pMgntInfo->dot11CurrentChannelNumber)
1485         {
1486                 u8      CckCellPwrIdx = DbmToTxPwrIdx(Adapter, WIRELESS_MODE_B, pMgntInfo->CcxCellPwr);
1487                 u8      LegacyOfdmCellPwrIdx = DbmToTxPwrIdx(Adapter, WIRELESS_MODE_G, pMgntInfo->CcxCellPwr);
1488                 u8      OfdmCellPwrIdx = DbmToTxPwrIdx(Adapter, WIRELESS_MODE_N_24G, pMgntInfo->CcxCellPwr);
1489
1490                 RT_TRACE(COMP_TXAGC, DBG_LOUD,
1491                         ("CCX Cell Limit: %d dbm => CCK Tx power index : %d, Legacy OFDM Tx power index : %d, OFDM Tx power index: %d\n",
1492                         pMgntInfo->CcxCellPwr, CckCellPwrIdx, LegacyOfdmCellPwrIdx, OfdmCellPwrIdx));
1493                 RT_TRACE(COMP_TXAGC, DBG_LOUD,
1494                         ("EEPROM channel(%d) => CCK Tx power index: %d, Legacy OFDM Tx power index : %d, OFDM Tx power index: %d\n",
1495                         channel, powerlevel, powerlevelOFDM24G + pHalData->LegacyHTTxPowerDiff, powerlevelOFDM24G));
1496
1497                 // CCK
1498                 if(powerlevel > CckCellPwrIdx)
1499                         powerlevel = CckCellPwrIdx;
1500                 // Legacy OFDM, HT OFDM
1501                 if(powerlevelOFDM24G + pHalData->LegacyHTTxPowerDiff > OfdmCellPwrIdx)
1502                 {
1503                         if((OfdmCellPwrIdx - pHalData->LegacyHTTxPowerDiff) > 0)
1504                         {
1505                                 powerlevelOFDM24G = OfdmCellPwrIdx - pHalData->LegacyHTTxPowerDiff;
1506                         }
1507                         else
1508                         {
1509                                 LegacyOfdmCellPwrIdx = 0;
1510                         }
1511                 }
1512
1513                 RT_TRACE(COMP_TXAGC, DBG_LOUD,
1514                         ("Altered CCK Tx power index : %d, Legacy OFDM Tx power index: %d, OFDM Tx power index: %d\n",
1515                         powerlevel, powerlevelOFDM24G + pHalData->LegacyHTTxPowerDiff, powerlevelOFDM24G));
1516         }
1517
1518         pHalData->CurrentCckTxPwrIdx = powerlevel;
1519         pHalData->CurrentOfdm24GTxPwrIdx = powerlevelOFDM24G;
1520 #endif
1521         PHY_SetRF8256CCKTxPower(priv, powerlevel); //need further implement
1522         PHY_SetRF8256OFDMTxPower(priv, powerlevelOFDM24G);
1523 }
1524
1525 /******************************************************************************
1526  *function:  This function check Rf chip to do RF config
1527  *   input:  net_device dev
1528  *  output:  none
1529  *  return:  only 8256 is supported
1530  * ***************************************************************************/
1531 RT_STATUS rtl8192_phy_RFConfig(struct r8192_priv *priv)
1532 {
1533         return PHY_RF8256_Config(priv);
1534 }
1535
1536 /******************************************************************************
1537  *function:  This function update Initial gain
1538  *   input:  net_device dev
1539  *  output:  none
1540  *  return:  As Windows has not implemented this, wait for complement
1541  * ***************************************************************************/
1542 void rtl8192_phy_updateInitGain(struct r8192_priv *priv)
1543 {
1544 }
1545
1546 /******************************************************************************
1547  *function:  This function read RF parameters from general head file, and do RF 3-wire
1548  *   input:  net_device dev
1549  *  output:  none
1550  *  return:  return code show if RF configuration is successful(0:pass, 1:fail)
1551  *    Note:  Delay may be required for RF configuration
1552  * ***************************************************************************/
1553 u8 rtl8192_phy_ConfigRFWithHeaderFile(struct r8192_priv *priv,
1554                                       RF90_RADIO_PATH_E eRFPath)
1555 {
1556
1557         int i;
1558         //u32* pRFArray;
1559         u8 ret = 0;
1560
1561         switch(eRFPath){
1562                 case RF90_PATH_A:
1563                         for(i = 0;i<RadioA_ArrayLength; i=i+2){
1564
1565                                 if(Rtl819XRadioA_Array[i] == 0xfe){
1566                                                 msleep(100);
1567                                                 continue;
1568                                 }
1569                                 rtl8192_phy_SetRFReg(priv, eRFPath, Rtl819XRadioA_Array[i], bMask12Bits, Rtl819XRadioA_Array[i+1]);
1570                                 //msleep(1);
1571
1572                         }
1573                         break;
1574                 case RF90_PATH_B:
1575                         for(i = 0;i<RadioB_ArrayLength; i=i+2){
1576
1577                                 if(Rtl819XRadioB_Array[i] == 0xfe){
1578                                                 msleep(100);
1579                                                 continue;
1580                                 }
1581                                 rtl8192_phy_SetRFReg(priv, eRFPath, Rtl819XRadioB_Array[i], bMask12Bits, Rtl819XRadioB_Array[i+1]);
1582                                 //msleep(1);
1583
1584                         }
1585                         break;
1586                 case RF90_PATH_C:
1587                         for(i = 0;i<RadioC_ArrayLength; i=i+2){
1588
1589                                 if(Rtl819XRadioC_Array[i] == 0xfe){
1590                                                 msleep(100);
1591                                                 continue;
1592                                 }
1593                                 rtl8192_phy_SetRFReg(priv, eRFPath, Rtl819XRadioC_Array[i], bMask12Bits, Rtl819XRadioC_Array[i+1]);
1594                                 //msleep(1);
1595
1596                         }
1597                         break;
1598                 case RF90_PATH_D:
1599                         for(i = 0;i<RadioD_ArrayLength; i=i+2){
1600
1601                                 if(Rtl819XRadioD_Array[i] == 0xfe){
1602                                                 msleep(100);
1603                                                 continue;
1604                                 }
1605                                 rtl8192_phy_SetRFReg(priv, eRFPath, Rtl819XRadioD_Array[i], bMask12Bits, Rtl819XRadioD_Array[i+1]);
1606                                 //msleep(1);
1607
1608                         }
1609                         break;
1610                 default:
1611                         break;
1612         }
1613
1614         return ret;
1615
1616 }
1617 /******************************************************************************
1618  *function:  This function set Tx Power of the channel
1619  *   input:  struct net_device *dev
1620  *           u8                 channel
1621  *  output:  none
1622  *  return:  none
1623  *    Note:
1624  * ***************************************************************************/
1625 static void rtl8192_SetTxPowerLevel(struct r8192_priv *priv, u8 channel)
1626 {
1627         u8      powerlevel = priv->TxPowerLevelCCK[channel-1];
1628         u8      powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1];
1629
1630         PHY_SetRF8256CCKTxPower(priv, powerlevel);
1631         PHY_SetRF8256OFDMTxPower(priv, powerlevelOFDM24G);
1632 }
1633
1634 /****************************************************************************************
1635  *function:  This function set command table variable(struct SwChnlCmd).
1636  *   input:  SwChnlCmd*         CmdTable        //table to be set.
1637  *           u32                CmdTableIdx     //variable index in table to be set
1638  *           u32                CmdTableSz      //table size.
1639  *           SwChnlCmdID        CmdID           //command ID to set.
1640  *           u32                Para1
1641  *           u32                Para2
1642  *           u32                msDelay
1643  *  output:
1644  *  return:  true if finished, false otherwise
1645  *    Note:
1646  * ************************************************************************************/
1647 static u8 rtl8192_phy_SetSwChnlCmdArray(
1648         SwChnlCmd*              CmdTable,
1649         u32                     CmdTableIdx,
1650         u32                     CmdTableSz,
1651         SwChnlCmdID             CmdID,
1652         u32                     Para1,
1653         u32                     Para2,
1654         u32                     msDelay
1655         )
1656 {
1657         SwChnlCmd* pCmd;
1658
1659         if(CmdTable == NULL)
1660         {
1661                 RT_TRACE(COMP_ERR, "phy_SetSwChnlCmdArray(): CmdTable cannot be NULL.\n");
1662                 return false;
1663         }
1664         if(CmdTableIdx >= CmdTableSz)
1665         {
1666                 RT_TRACE(COMP_ERR, "phy_SetSwChnlCmdArray(): Access invalid index, please check size of the table, CmdTableIdx:%d, CmdTableSz:%d\n",
1667                                 CmdTableIdx, CmdTableSz);
1668                 return false;
1669         }
1670
1671         pCmd = CmdTable + CmdTableIdx;
1672         pCmd->CmdID = CmdID;
1673         pCmd->Para1 = Para1;
1674         pCmd->Para2 = Para2;
1675         pCmd->msDelay = msDelay;
1676
1677         return true;
1678 }
1679 /******************************************************************************
1680  *function:  This function set channel step by step
1681  *   input:  struct net_device *dev
1682  *           u8                 channel
1683  *           u8*                stage //3 stages
1684  *           u8*                step  //
1685  *           u32*               delay //whether need to delay
1686  *  output:  store new stage, step and delay for next step(combine with function above)
1687  *  return:  true if finished, false otherwise
1688  *    Note:  Wait for simpler function to replace it //wb
1689  * ***************************************************************************/
1690 static u8 rtl8192_phy_SwChnlStepByStep(struct r8192_priv *priv, u8 channel,
1691                                        u8* stage, u8* step, u32* delay)
1692 {
1693 //      PCHANNEL_ACCESS_SETTING pChnlAccessSetting;
1694         SwChnlCmd                               PreCommonCmd[MAX_PRECMD_CNT];
1695         u32                                     PreCommonCmdCnt;
1696         SwChnlCmd                               PostCommonCmd[MAX_POSTCMD_CNT];
1697         u32                                     PostCommonCmdCnt;
1698         SwChnlCmd                               RfDependCmd[MAX_RFDEPENDCMD_CNT];
1699         u32                                     RfDependCmdCnt;
1700         SwChnlCmd                               *CurrentCmd = NULL;
1701         //RF90_RADIO_PATH_E             eRFPath;
1702         u8              eRFPath;
1703 //      u32             RfRetVal;
1704 //      u8              RetryCnt;
1705
1706         RT_TRACE(COMP_TRACE, "====>%s()====stage:%d, step:%d, channel:%d\n", __FUNCTION__, *stage, *step, channel);
1707 //      RT_ASSERT(IsLegalChannel(Adapter, channel), ("illegal channel: %d\n", channel));
1708
1709 #ifdef ENABLE_DOT11D
1710         if (!IsLegalChannel(priv->ieee80211, channel))
1711         {
1712                 RT_TRACE(COMP_ERR, "=============>set to illegal channel:%d\n", channel);
1713                 return true; //return true to tell upper caller function this channel setting is finished! Or it will in while loop.
1714         }
1715 #endif
1716
1717         //for(eRFPath = RF90_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
1718         //for(eRFPath = 0; eRFPath <RF90_PATH_MAX; eRFPath++)
1719         {
1720                 //if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
1721                 //      return false;
1722                 // <1> Fill up pre common command.
1723                 PreCommonCmdCnt = 0;
1724                 rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT,
1725                                         CmdID_SetTxPowerLevel, 0, 0, 0);
1726                 rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT,
1727                                         CmdID_End, 0, 0, 0);
1728
1729                 // <2> Fill up post common command.
1730                 PostCommonCmdCnt = 0;
1731
1732                 rtl8192_phy_SetSwChnlCmdArray(PostCommonCmd, PostCommonCmdCnt++, MAX_POSTCMD_CNT,
1733                                         CmdID_End, 0, 0, 0);
1734
1735                 // <3> Fill up RF dependent command.
1736                 RfDependCmdCnt = 0;
1737
1738                 // TEST!! This is not the table for 8256!!
1739                 if (!(channel >= 1 && channel <= 14))
1740                 {
1741                         RT_TRACE(COMP_ERR, "illegal channel for Zebra 8256: %d\n", channel);
1742                         return false;
1743                 }
1744                 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
1745                         CmdID_RF_WriteReg, rZebra1_Channel, channel, 10);
1746                 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
1747                 CmdID_End, 0, 0, 0);
1748
1749                 do{
1750                         switch(*stage)
1751                         {
1752                         case 0:
1753                                 CurrentCmd=&PreCommonCmd[*step];
1754                                 break;
1755                         case 1:
1756                                 CurrentCmd=&RfDependCmd[*step];
1757                                 break;
1758                         case 2:
1759                                 CurrentCmd=&PostCommonCmd[*step];
1760                                 break;
1761                         }
1762
1763                         if(CurrentCmd->CmdID==CmdID_End)
1764                         {
1765                                 if((*stage)==2)
1766                                 {
1767                                         return true;
1768                                 }
1769                                 else
1770                                 {
1771                                         (*stage)++;
1772                                         (*step)=0;
1773                                         continue;
1774                                 }
1775                         }
1776
1777                         switch(CurrentCmd->CmdID)
1778                         {
1779                         case CmdID_SetTxPowerLevel:
1780                                 if(priv->card_8192_version > (u8)VERSION_8190_BD) //xiong: consider it later!
1781                                         rtl8192_SetTxPowerLevel(priv, channel);
1782                                 break;
1783                         case CmdID_WritePortUlong:
1784                                 write_nic_dword(priv, CurrentCmd->Para1, CurrentCmd->Para2);
1785                                 break;
1786                         case CmdID_WritePortUshort:
1787                                 write_nic_word(priv, CurrentCmd->Para1, (u16)CurrentCmd->Para2);
1788                                 break;
1789                         case CmdID_WritePortUchar:
1790                                 write_nic_byte(priv, CurrentCmd->Para1, (u8)CurrentCmd->Para2);
1791                                 break;
1792                         case CmdID_RF_WriteReg:
1793                                 for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++)
1794                                         rtl8192_phy_SetRFReg(priv, (RF90_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, bMask12Bits, CurrentCmd->Para2<<7);
1795                                 break;
1796                         default:
1797                                 break;
1798                         }
1799
1800                         break;
1801                 }while(true);
1802         }/*for(Number of RF paths)*/
1803
1804         (*delay)=CurrentCmd->msDelay;
1805         (*step)++;
1806         return false;
1807 }
1808
1809 /******************************************************************************
1810  *function:  This function does acturally set channel work
1811  *   input:  struct net_device *dev
1812  *           u8                 channel
1813  *  output:  none
1814  *  return:  noin
1815  *    Note:  We should not call this function directly
1816  * ***************************************************************************/
1817 static void rtl8192_phy_FinishSwChnlNow(struct r8192_priv *priv, u8 channel)
1818 {
1819         u32     delay = 0;
1820
1821         while (!rtl8192_phy_SwChnlStepByStep(priv, channel, &priv->SwChnlStage, &priv->SwChnlStep, &delay))
1822         {
1823                 if(delay>0)
1824                         msleep(delay);//or mdelay? need further consideration
1825                 if(!priv->up)
1826                         break;
1827         }
1828 }
1829 /******************************************************************************
1830  *function:  Callback routine of the work item for switch channel.
1831  *   input:
1832  *
1833  *  output:  none
1834  *  return:  noin
1835  * ***************************************************************************/
1836 void rtl8192_SwChnl_WorkItem(struct r8192_priv *priv)
1837 {
1838         RT_TRACE(COMP_TRACE, "==> SwChnlCallback819xUsbWorkItem()\n");
1839
1840         RT_TRACE(COMP_TRACE, "=====>--%s(), set chan:%d, priv:%p\n", __FUNCTION__, priv->chan, priv);
1841
1842         rtl8192_phy_FinishSwChnlNow(priv, priv->chan);
1843
1844         RT_TRACE(COMP_TRACE, "<== SwChnlCallback819xUsbWorkItem()\n");
1845 }
1846
1847 /******************************************************************************
1848  *function:  This function scheduled actural workitem to set channel
1849  *   input:  net_device dev
1850  *           u8         channel //channel to set
1851  *  output:  none
1852  *  return:  return code show if workitem is scheduled(1:pass, 0:fail)
1853  *    Note:  Delay may be required for RF configuration
1854  * ***************************************************************************/
1855 u8 rtl8192_phy_SwChnl(struct net_device* dev, u8 channel)
1856 {
1857         struct r8192_priv *priv = ieee80211_priv(dev);
1858         RT_TRACE(COMP_PHY, "=====>%s()\n", __FUNCTION__);
1859         if(!priv->up)
1860                 return false;
1861         if(priv->SwChnlInProgress)
1862                 return false;
1863
1864 //      if(pHalData->SetBWModeInProgress)
1865 //              return;
1866
1867         //--------------------------------------------
1868         switch(priv->ieee80211->mode)
1869         {
1870         case WIRELESS_MODE_A:
1871         case WIRELESS_MODE_N_5G:
1872                 if (channel<=14){
1873                         RT_TRACE(COMP_ERR, "WIRELESS_MODE_A but channel<=14\n");
1874                         return false;
1875                 }
1876                 break;
1877         case WIRELESS_MODE_B:
1878                 if (channel>14){
1879                         RT_TRACE(COMP_ERR, "WIRELESS_MODE_B but channel>14\n");
1880                         return false;
1881                 }
1882                 break;
1883         case WIRELESS_MODE_G:
1884         case WIRELESS_MODE_N_24G:
1885                 if (channel>14){
1886                         RT_TRACE(COMP_ERR, "WIRELESS_MODE_G but channel>14\n");
1887                         return false;
1888                 }
1889                 break;
1890         }
1891         //--------------------------------------------
1892
1893         priv->SwChnlInProgress = true;
1894         if(channel == 0)
1895                 channel = 1;
1896
1897         priv->chan=channel;
1898
1899         priv->SwChnlStage=0;
1900         priv->SwChnlStep=0;
1901         if (priv->up)
1902                 rtl8192_SwChnl_WorkItem(priv);
1903
1904         priv->SwChnlInProgress = false;
1905         return true;
1906 }
1907
1908 static void CCK_Tx_Power_Track_BW_Switch_TSSI(struct r8192_priv *priv)
1909 {
1910         switch(priv->CurrentChannelBW)
1911         {
1912                 /* 20 MHz channel*/
1913                 case HT_CHANNEL_WIDTH_20:
1914         //added by vivi, cck,tx power track, 20080703
1915                         priv->CCKPresentAttentuation =
1916                                 priv->CCKPresentAttentuation_20Mdefault + priv->CCKPresentAttentuation_difference;
1917
1918                         if(priv->CCKPresentAttentuation > (CCKTxBBGainTableLength-1))
1919                                 priv->CCKPresentAttentuation = CCKTxBBGainTableLength-1;
1920                         if(priv->CCKPresentAttentuation < 0)
1921                                 priv->CCKPresentAttentuation = 0;
1922
1923                         RT_TRACE(COMP_POWER_TRACKING, "20M, priv->CCKPresentAttentuation = %d\n", priv->CCKPresentAttentuation);
1924
1925                         if(priv->ieee80211->current_network.channel== 14 && !priv->bcck_in_ch14)
1926                         {
1927                                 priv->bcck_in_ch14 = TRUE;
1928                                 dm_cck_txpower_adjust(priv, priv->bcck_in_ch14);
1929                         }
1930                         else if(priv->ieee80211->current_network.channel != 14 && priv->bcck_in_ch14)
1931                         {
1932                                 priv->bcck_in_ch14 = FALSE;
1933                                 dm_cck_txpower_adjust(priv, priv->bcck_in_ch14);
1934                         }
1935                         else
1936                                 dm_cck_txpower_adjust(priv, priv->bcck_in_ch14);
1937                 break;
1938
1939                 /* 40 MHz channel*/
1940                 case HT_CHANNEL_WIDTH_20_40:
1941                         //added by vivi, cck,tx power track, 20080703
1942                         priv->CCKPresentAttentuation =
1943                                 priv->CCKPresentAttentuation_40Mdefault + priv->CCKPresentAttentuation_difference;
1944
1945                         RT_TRACE(COMP_POWER_TRACKING, "40M, priv->CCKPresentAttentuation = %d\n", priv->CCKPresentAttentuation);
1946                         if(priv->CCKPresentAttentuation > (CCKTxBBGainTableLength-1))
1947                                 priv->CCKPresentAttentuation = CCKTxBBGainTableLength-1;
1948                         if(priv->CCKPresentAttentuation < 0)
1949                                 priv->CCKPresentAttentuation = 0;
1950
1951                         if(priv->ieee80211->current_network.channel == 14 && !priv->bcck_in_ch14)
1952                         {
1953                                 priv->bcck_in_ch14 = TRUE;
1954                                 dm_cck_txpower_adjust(priv, priv->bcck_in_ch14);
1955                         }
1956                         else if(priv->ieee80211->current_network.channel != 14 && priv->bcck_in_ch14)
1957                         {
1958                                 priv->bcck_in_ch14 = FALSE;
1959                                 dm_cck_txpower_adjust(priv, priv->bcck_in_ch14);
1960                         }
1961                         else
1962                                 dm_cck_txpower_adjust(priv, priv->bcck_in_ch14);
1963                 break;
1964         }
1965 }
1966
1967 static void CCK_Tx_Power_Track_BW_Switch_ThermalMeter(struct r8192_priv *priv)
1968 {
1969         if(priv->ieee80211->current_network.channel == 14 && !priv->bcck_in_ch14)
1970                 priv->bcck_in_ch14 = TRUE;
1971         else if(priv->ieee80211->current_network.channel != 14 && priv->bcck_in_ch14)
1972                 priv->bcck_in_ch14 = FALSE;
1973
1974         //write to default index and tx power track will be done in dm.
1975         switch(priv->CurrentChannelBW)
1976         {
1977                 /* 20 MHz channel*/
1978                 case HT_CHANNEL_WIDTH_20:
1979                         if(priv->Record_CCK_20Mindex == 0)
1980                                 priv->Record_CCK_20Mindex = 6;  //set default value.
1981                         priv->CCK_index = priv->Record_CCK_20Mindex;//6;
1982                         RT_TRACE(COMP_POWER_TRACKING, "20MHz, CCK_Tx_Power_Track_BW_Switch_ThermalMeter(),CCK_index = %d\n", priv->CCK_index);
1983                 break;
1984
1985                 /* 40 MHz channel*/
1986                 case HT_CHANNEL_WIDTH_20_40:
1987                         priv->CCK_index = priv->Record_CCK_40Mindex;//0;
1988                         RT_TRACE(COMP_POWER_TRACKING, "40MHz, CCK_Tx_Power_Track_BW_Switch_ThermalMeter(), CCK_index = %d\n", priv->CCK_index);
1989                 break;
1990         }
1991         dm_cck_txpower_adjust(priv, priv->bcck_in_ch14);
1992 }
1993
1994 static void CCK_Tx_Power_Track_BW_Switch(struct r8192_priv *priv)
1995 {
1996
1997         //if(pHalData->bDcut == TRUE)
1998         if(priv->IC_Cut >= IC_VersionCut_D)
1999                 CCK_Tx_Power_Track_BW_Switch_TSSI(priv);
2000         else
2001                 CCK_Tx_Power_Track_BW_Switch_ThermalMeter(priv);
2002 }
2003
2004
2005 //
2006 /******************************************************************************
2007  *function:  Callback routine of the work item for set bandwidth mode.
2008  *   input:  struct net_device *dev
2009  *           HT_CHANNEL_WIDTH   Bandwidth  //20M or 40M
2010  *           HT_EXTCHNL_OFFSET Offset      //Upper, Lower, or Don't care
2011  *  output:  none
2012  *  return:  none
2013  *    Note:  I doubt whether SetBWModeInProgress flag is necessary as we can
2014  *           test whether current work in the queue or not.//do I?
2015  * ***************************************************************************/
2016 void rtl8192_SetBWModeWorkItem(struct r8192_priv *priv)
2017 {
2018         u8 regBwOpMode;
2019
2020         RT_TRACE(COMP_SWBW, "==>rtl8192_SetBWModeWorkItem()  Switch to %s bandwidth\n",
2021                                         priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz")
2022
2023
2024         if(!priv->up)
2025         {
2026                 priv->SetBWModeInProgress= false;
2027                 return;
2028         }
2029         //<1>Set MAC register
2030         regBwOpMode = read_nic_byte(priv, BW_OPMODE);
2031
2032         switch(priv->CurrentChannelBW)
2033         {
2034                 case HT_CHANNEL_WIDTH_20:
2035                         regBwOpMode |= BW_OPMODE_20MHZ;
2036                        // 2007/02/07 Mark by Emily becasue we have not verify whether this register works
2037                         write_nic_byte(priv, BW_OPMODE, regBwOpMode);
2038                         break;
2039
2040                 case HT_CHANNEL_WIDTH_20_40:
2041                         regBwOpMode &= ~BW_OPMODE_20MHZ;
2042                         // 2007/02/07 Mark by Emily becasue we have not verify whether this register works
2043                         write_nic_byte(priv, BW_OPMODE, regBwOpMode);
2044                         break;
2045
2046                 default:
2047                         RT_TRACE(COMP_ERR, "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n",priv->CurrentChannelBW);
2048                         break;
2049         }
2050
2051         //<2>Set PHY related register
2052         switch(priv->CurrentChannelBW)
2053         {
2054                 case HT_CHANNEL_WIDTH_20:
2055                         // Add by Vivi 20071119
2056                         rtl8192_setBBreg(priv, rFPGA0_RFMOD, bRFMOD, 0x0);
2057                         rtl8192_setBBreg(priv, rFPGA1_RFMOD, bRFMOD, 0x0);
2058 //                      rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 1);
2059
2060                         // Correct the tx power for CCK rate in 20M. Suggest by YN, 20071207
2061 //                      write_nic_dword(dev, rCCK0_TxFilter1, 0x1a1b0000);
2062 //                      write_nic_dword(dev, rCCK0_TxFilter2, 0x090e1317);
2063 //                      write_nic_dword(dev, rCCK0_DebugPort, 0x00000204);
2064                         if(!priv->btxpower_tracking)
2065                         {
2066                                 write_nic_dword(priv, rCCK0_TxFilter1, 0x1a1b0000);
2067                                 write_nic_dword(priv, rCCK0_TxFilter2, 0x090e1317);
2068                                 write_nic_dword(priv, rCCK0_DebugPort, 0x00000204);
2069                         }
2070                         else
2071                                 CCK_Tx_Power_Track_BW_Switch(priv);
2072
2073                         rtl8192_setBBreg(priv, rFPGA0_AnalogParameter1, 0x00100000, 1);
2074                         break;
2075                 case HT_CHANNEL_WIDTH_20_40:
2076                         // Add by Vivi 20071119
2077                         rtl8192_setBBreg(priv, rFPGA0_RFMOD, bRFMOD, 0x1);
2078                         rtl8192_setBBreg(priv, rFPGA1_RFMOD, bRFMOD, 0x1);
2079                         //rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1));
2080                     //rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0);
2081                         //rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC);
2082
2083                         // Correct the tx power for CCK rate in 40M. Suggest by YN, 20071207
2084                         //write_nic_dword(dev, rCCK0_TxFilter1, 0x35360000);
2085                         //write_nic_dword(dev, rCCK0_TxFilter2, 0x121c252e);
2086                         //write_nic_dword(dev, rCCK0_DebugPort, 0x00000409);
2087                         if(!priv->btxpower_tracking)
2088                         {
2089                                 write_nic_dword(priv, rCCK0_TxFilter1, 0x35360000);
2090                                 write_nic_dword(priv, rCCK0_TxFilter2, 0x121c252e);
2091                                 write_nic_dword(priv, rCCK0_DebugPort, 0x00000409);
2092                         }
2093                         else
2094                                 CCK_Tx_Power_Track_BW_Switch(priv);
2095
2096                         // Set Control channel to upper or lower. These settings are required only for 40MHz
2097                         rtl8192_setBBreg(priv, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1));
2098                         rtl8192_setBBreg(priv, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC);
2099
2100
2101                         rtl8192_setBBreg(priv, rFPGA0_AnalogParameter1, 0x00100000, 0);
2102                         break;
2103                 default:
2104                         RT_TRACE(COMP_ERR, "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n" ,priv->CurrentChannelBW);
2105                         break;
2106
2107         }
2108         //Skip over setting of J-mode in BB register here. Default value is "None J mode". Emily 20070315
2109
2110         //<3>Set RF related register
2111         PHY_SetRF8256Bandwidth(priv, priv->CurrentChannelBW);
2112
2113         atomic_dec(&(priv->ieee80211->atm_swbw));
2114         priv->SetBWModeInProgress= false;
2115
2116         RT_TRACE(COMP_SWBW, "<==SetBWMode819xUsb()\n");
2117 }
2118
2119 /******************************************************************************
2120  *function:  This function schedules bandwith switch work.
2121  *   input:  struct net_device *dev
2122  *           HT_CHANNEL_WIDTH   Bandwidth  //20M or 40M
2123  *           HT_EXTCHNL_OFFSET Offset      //Upper, Lower, or Don't care
2124  *  output:  none
2125  *  return:  none
2126  *    Note:  I doubt whether SetBWModeInProgress flag is necessary as we can
2127  *           test whether current work in the queue or not.//do I?
2128  * ***************************************************************************/
2129 void rtl8192_SetBWMode(struct net_device *dev, HT_CHANNEL_WIDTH Bandwidth, HT_EXTCHNL_OFFSET Offset)
2130 {
2131         struct r8192_priv *priv = ieee80211_priv(dev);
2132
2133
2134         if(priv->SetBWModeInProgress)
2135                 return;
2136
2137          atomic_inc(&(priv->ieee80211->atm_swbw));
2138         priv->SetBWModeInProgress= true;
2139
2140         priv->CurrentChannelBW = Bandwidth;
2141
2142         if(Offset==HT_EXTCHNL_OFFSET_LOWER)
2143                 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER;
2144         else if(Offset==HT_EXTCHNL_OFFSET_UPPER)
2145                 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER;
2146         else
2147                 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
2148
2149         //queue_work(priv->priv_wq, &(priv->SetBWModeWorkItem));
2150         //      schedule_work(&(priv->SetBWModeWorkItem));
2151         rtl8192_SetBWModeWorkItem(priv);
2152
2153 }
2154
2155
2156 void InitialGain819xPci(struct net_device *dev, u8 Operation)
2157 {
2158 #define SCAN_RX_INITIAL_GAIN    0x17
2159 #define POWER_DETECTION_TH      0x08
2160         struct r8192_priv *priv = ieee80211_priv(dev);
2161         u32                                     BitMask;
2162         u8                                      initial_gain;
2163
2164         if(priv->up)
2165         {
2166                 switch(Operation)
2167                 {
2168                         case IG_Backup:
2169                         RT_TRACE(COMP_SCAN, "IG_Backup, backup the initial gain.\n");
2170                                 initial_gain = SCAN_RX_INITIAL_GAIN;//pHalData->DefaultInitialGain[0];//
2171                                 BitMask = bMaskByte0;
2172                                 if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
2173                                         rtl8192_setBBreg(priv, UFWP, bMaskByte1, 0x8);  // FW DIG OFF
2174                                 priv->initgain_backup.xaagccore1 = (u8)rtl8192_QueryBBReg(priv, rOFDM0_XAAGCCore1, BitMask);
2175                                 priv->initgain_backup.xbagccore1 = (u8)rtl8192_QueryBBReg(priv, rOFDM0_XBAGCCore1, BitMask);
2176                                 priv->initgain_backup.xcagccore1 = (u8)rtl8192_QueryBBReg(priv, rOFDM0_XCAGCCore1, BitMask);
2177                                 priv->initgain_backup.xdagccore1 = (u8)rtl8192_QueryBBReg(priv, rOFDM0_XDAGCCore1, BitMask);
2178                                 BitMask  = bMaskByte2;
2179                                 priv->initgain_backup.cca = (u8)rtl8192_QueryBBReg(priv, rCCK0_CCA, BitMask);
2180
2181                         RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc50 is %x\n",priv->initgain_backup.xaagccore1);
2182                         RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc58 is %x\n",priv->initgain_backup.xbagccore1);
2183                         RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc60 is %x\n",priv->initgain_backup.xcagccore1);
2184                         RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc68 is %x\n",priv->initgain_backup.xdagccore1);
2185                         RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xa0a is %x\n",priv->initgain_backup.cca);
2186
2187                         RT_TRACE(COMP_SCAN, "Write scan initial gain = 0x%x \n", initial_gain);
2188                                 write_nic_byte(priv, rOFDM0_XAAGCCore1, initial_gain);
2189                                 write_nic_byte(priv, rOFDM0_XBAGCCore1, initial_gain);
2190                                 write_nic_byte(priv, rOFDM0_XCAGCCore1, initial_gain);
2191                                 write_nic_byte(priv, rOFDM0_XDAGCCore1, initial_gain);
2192                                 RT_TRACE(COMP_SCAN, "Write scan 0xa0a = 0x%x \n", POWER_DETECTION_TH);
2193                                 write_nic_byte(priv, 0xa0a, POWER_DETECTION_TH);
2194                                 break;
2195                         case IG_Restore:
2196                         RT_TRACE(COMP_SCAN, "IG_Restore, restore the initial gain.\n");
2197                                 BitMask = 0x7f; //Bit0~ Bit6
2198                                 if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
2199                                         rtl8192_setBBreg(priv, UFWP, bMaskByte1, 0x8);  // FW DIG OFF
2200
2201                                 rtl8192_setBBreg(priv, rOFDM0_XAAGCCore1, BitMask, (u32)priv->initgain_backup.xaagccore1);
2202                                 rtl8192_setBBreg(priv, rOFDM0_XBAGCCore1, BitMask, (u32)priv->initgain_backup.xbagccore1);
2203                                 rtl8192_setBBreg(priv, rOFDM0_XCAGCCore1, BitMask, (u32)priv->initgain_backup.xcagccore1);
2204                                 rtl8192_setBBreg(priv, rOFDM0_XDAGCCore1, BitMask, (u32)priv->initgain_backup.xdagccore1);
2205                                 BitMask  = bMaskByte2;
2206                                 rtl8192_setBBreg(priv, rCCK0_CCA, BitMask, (u32)priv->initgain_backup.cca);
2207
2208                         RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc50 is %x\n",priv->initgain_backup.xaagccore1);
2209                         RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc58 is %x\n",priv->initgain_backup.xbagccore1);
2210                         RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc60 is %x\n",priv->initgain_backup.xcagccore1);
2211                         RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc68 is %x\n",priv->initgain_backup.xdagccore1);
2212                         RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xa0a is %x\n",priv->initgain_backup.cca);
2213
2214                                 rtl8192_phy_setTxPower(priv, priv->ieee80211->current_network.channel);
2215
2216
2217                                 if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
2218                                         rtl8192_setBBreg(priv, UFWP, bMaskByte1, 0x1);  // FW DIG ON
2219                                 break;
2220                         default:
2221                         RT_TRACE(COMP_SCAN, "Unknown IG Operation.\n");
2222                                 break;
2223                 }
2224         }
2225 }
2226