Pileus Git - ~andy/linux/blob - drivers/staging/rtl8192e/r8192E.h

   1 /*
   2    This is part of rtl8187 OpenSource driver.
   3    Copyright (C) Andrea Merello 2004-2005  <andreamrl@tiscali.it>
   4    Released under the terms of GPL (General Public Licence)
   5
   6    Parts of this driver are based on the GPL part of the
   7    official realtek driver
   8
   9    Parts of this driver are based on the rtl8192 driver skeleton
  10    from Patric Schenke & Andres Salomon
  11
  12    Parts of this driver are based on the Intel Pro Wireless 2100 GPL driver
  13
  14    We want to tanks the Authors of those projects and the Ndiswrapper
  15    project Authors.
  16 */
  17
  18 #ifndef R819xU_H
  19 #define R819xU_H
  20
  21 #include <linux/module.h>
  22 #include <linux/kernel.h>
  23 #include <linux/init.h>
  24 #include <linux/ioport.h>
  25 #include <linux/sched.h>
  26 #include <linux/types.h>
  27 #include <linux/slab.h>
  28 #include <linux/netdevice.h>
  29 #include <linux/pci.h>
  30 #include <linux/etherdevice.h>
  31 #include <linux/delay.h>
  32 #include <linux/rtnetlink.h>    //for rtnl_lock()
  33 #include <linux/wireless.h>
  34 #include <linux/timer.h>
  35 #include <linux/proc_fs.h>      // Necessary because we use the proc fs
  36 #include <linux/if_arp.h>
  37 #include <linux/random.h>
  38 #include <linux/version.h>
  39 #include <asm/io.h>
  40 #include "ieee80211/rtl819x_HT.h"
  41 #include "ieee80211/ieee80211.h"
  42
  43
  44
  45
  46 #define RTL819xE_MODULE_NAME "rtl819xE"
  47
  48 #define FALSE 0
  49 #define TRUE 1
  50 #define MAX_KEY_LEN     61
  51 #define KEY_BUF_SIZE    5
  52
  53 #define BIT0            0x00000001
  54 #define BIT1            0x00000002
  55 #define BIT2            0x00000004
  56 #define BIT3            0x00000008
  57 #define BIT4            0x00000010
  58 #define BIT5            0x00000020
  59 #define BIT6            0x00000040
  60 #define BIT7            0x00000080
  61 #define BIT8            0x00000100
  62 #define BIT9            0x00000200
  63 #define BIT10           0x00000400
  64 #define BIT11           0x00000800
  65 #define BIT12           0x00001000
  66 #define BIT13           0x00002000
  67 #define BIT14           0x00004000
  68 #define BIT15           0x00008000
  69 #define BIT16           0x00010000
  70 #define BIT17           0x00020000
  71 #define BIT18           0x00040000
  72 #define BIT19           0x00080000
  73 #define BIT20           0x00100000
  74 #define BIT21           0x00200000
  75 #define BIT22           0x00400000
  76 #define BIT23           0x00800000
  77 #define BIT24           0x01000000
  78 #define BIT25           0x02000000
  79 #define BIT26           0x04000000
  80 #define BIT27           0x08000000
  81 #define BIT28           0x10000000
  82 #define BIT29           0x20000000
  83 #define BIT30           0x40000000
  84 #define BIT31           0x80000000
  85 // Rx smooth factor
  86 #define Rx_Smooth_Factor                20
  87 /* 2007/06/04 MH Define sliding window for RSSI history. */
  88 #define         PHY_RSSI_SLID_WIN_MAX                           100
  89 #define         PHY_Beacon_RSSI_SLID_WIN_MAX            10
  90
  91 #define IC_VersionCut_D 0x3
  92 #define IC_VersionCut_E 0x4
  93
  94 #if 0 //we need to use RT_TRACE instead DMESG as RT_TRACE will clearly show debug level wb.
  95 #define DMESG(x,a...) printk(KERN_INFO RTL819xE_MODULE_NAME ": " x "\n", ## a)
  96 #else
  97 #define DMESG(x,a...)
  98 extern u32 rt_global_debug_component;
  99 #define RT_TRACE(component, x, args...) \
 100 do { if(rt_global_debug_component & component) \
 101         printk(KERN_DEBUG RTL819xE_MODULE_NAME ":" x , \
 102                ##args);\
 103 }while(0);
 104
 105 #define COMP_TRACE                              BIT0            // For function call tracing.
 106 #define COMP_DBG                                BIT1            // Only for temporary debug message.
 107 #define COMP_INIT                               BIT2            // during driver initialization / halt / reset.
 108
 109
 110 #define COMP_RECV                               BIT3            // Reveive part data path.
 111 #define COMP_SEND                               BIT4            // Send part path.
 112 #define COMP_IO                                 BIT5            // I/O Related. Added by Annie, 2006-03-02.
 113 #define COMP_POWER                              BIT6            // 802.11 Power Save mode or System/Device Power state related.
 114 #define COMP_EPROM                              BIT7            // 802.11 link related: join/start BSS, leave BSS.
 115 #define COMP_SWBW                               BIT8    // For bandwidth switch.
 116 #define COMP_SEC                                BIT9// For Security.
 117
 118
 119 #define COMP_TURBO                              BIT10   // For Turbo Mode related. By Annie, 2005-10-21.
 120 #define COMP_QOS                                BIT11   // For QoS.
 121
 122 #define COMP_RATE                               BIT12   // For Rate Adaptive mechanism, 2006.07.02, by rcnjko. #define COMP_EVENTS                              0x00000080      // Event handling
 123 #define COMP_RXDESC                             BIT13   // Show Rx desc information for SD3 debug. Added by Annie, 2006-07-15.
 124 #define COMP_PHY                                BIT14
 125 #define COMP_DIG                                BIT15   // For DIG, 2006.09.25, by rcnjko.
 126 #define COMP_TXAGC                              BIT16   // For Tx power, 060928, by rcnjko.
 127 #define COMP_HALDM                              BIT17   // For HW Dynamic Mechanism, 061010, by rcnjko.
 128 #define COMP_POWER_TRACKING                     BIT18   //FOR 8190 TX POWER TRACKING
 129 #define COMP_EVENTS                             BIT19   // Event handling
 130
 131 #define COMP_RF                                 BIT20   // For RF.
 132
 133 /* 11n or 8190 specific code should be put below this line */
 134
 135
 136 #define COMP_FIRMWARE                           BIT21   //for firmware downloading
 137 #define COMP_HT                                 BIT22   // For 802.11n HT related information. by Emily 2006-8-11
 138
 139 #define COMP_RESET                              BIT23
 140 #define COMP_CMDPKT                             BIT24
 141 #define COMP_SCAN                               BIT25
 142 #define COMP_IPS                                BIT26
 143 #define COMP_DOWN                               BIT27  // for rm driver module
 144 #define COMP_INTR                               BIT28  // for interrupt
 145 #define COMP_ERR                                BIT31  // for error out, always on
 146 #endif
 147
 148
 149 //
 150 // Queue Select Value in TxDesc
 151 //
 152 #define QSLT_BK                                 0x1
 153 #define QSLT_BE                                 0x0
 154 #define QSLT_VI                                 0x4
 155 #define QSLT_VO                                 0x6
 156 #define QSLT_BEACON                             0x10
 157 #define QSLT_HIGH                               0x11
 158 #define QSLT_MGNT                               0x12
 159 #define QSLT_CMD                                0x13
 160
 161 #define DESC90_RATE1M                           0x00
 162 #define DESC90_RATE2M                           0x01
 163 #define DESC90_RATE5_5M                         0x02
 164 #define DESC90_RATE11M                          0x03
 165 #define DESC90_RATE6M                           0x04
 166 #define DESC90_RATE9M                           0x05
 167 #define DESC90_RATE12M                          0x06
 168 #define DESC90_RATE18M                          0x07
 169 #define DESC90_RATE24M                          0x08
 170 #define DESC90_RATE36M                          0x09
 171 #define DESC90_RATE48M                          0x0a
 172 #define DESC90_RATE54M                          0x0b
 173 #define DESC90_RATEMCS0                         0x00
 174 #define DESC90_RATEMCS1                         0x01
 175 #define DESC90_RATEMCS2                         0x02
 176 #define DESC90_RATEMCS3                         0x03
 177 #define DESC90_RATEMCS4                         0x04
 178 #define DESC90_RATEMCS5                         0x05
 179 #define DESC90_RATEMCS6                         0x06
 180 #define DESC90_RATEMCS7                         0x07
 181 #define DESC90_RATEMCS8                         0x08
 182 #define DESC90_RATEMCS9                         0x09
 183 #define DESC90_RATEMCS10                        0x0a
 184 #define DESC90_RATEMCS11                        0x0b
 185 #define DESC90_RATEMCS12                        0x0c
 186 #define DESC90_RATEMCS13                        0x0d
 187 #define DESC90_RATEMCS14                        0x0e
 188 #define DESC90_RATEMCS15                        0x0f
 189 #define DESC90_RATEMCS32                        0x20
 190
 191 #define RTL819X_DEFAULT_RF_TYPE RF_1T2R
 192 #define EEPROM_Default_LegacyHTTxPowerDiff      0x4
 193 #define IEEE80211_WATCH_DOG_TIME    2000
 194
 195 typedef u32 RT_RF_CHANGE_SOURCE;
 196 #define RF_CHANGE_BY_SW BIT31
 197 #define RF_CHANGE_BY_HW BIT30
 198 #define RF_CHANGE_BY_PS BIT29
 199 #define RF_CHANGE_BY_IPS BIT28
 200 #define RF_CHANGE_BY_INIT       0       // Do not change the RFOff reason. Defined by Bruce, 2008-01-17.
 201
 202 /* For rtl819x */
 203 typedef struct _tx_desc_819x_pci {
 204         //DWORD 0
 205         u16     PktSize;
 206         u8      Offset;
 207         u8      Reserved1:3;
 208         u8      CmdInit:1;
 209         u8      LastSeg:1;
 210         u8      FirstSeg:1;
 211         u8      LINIP:1;
 212         u8      OWN:1;
 213
 214         //DWORD 1
 215         u8      TxFWInfoSize;
 216         u8      RATid:3;
 217         u8      DISFB:1;
 218         u8      USERATE:1;
 219         u8      MOREFRAG:1;
 220         u8      NoEnc:1;
 221         u8      PIFS:1;
 222         u8      QueueSelect:5;
 223         u8      NoACM:1;
 224         u8      Resv:2;
 225         u8      SecCAMID:5;
 226         u8      SecDescAssign:1;
 227         u8      SecType:2;
 228
 229         //DWORD 2
 230         u16     TxBufferSize;
 231         u8      PktId:7;
 232         u8      Resv1:1;
 233         u8      Reserved2;
 234
 235         //DWORD 3
 236         u32     TxBuffAddr;
 237
 238         //DWORD 4
 239         u32     NextDescAddress;
 240
 241         //DWORD 5,6,7
 242         u32     Reserved5;
 243         u32     Reserved6;
 244         u32     Reserved7;
 245 }tx_desc_819x_pci, *ptx_desc_819x_pci;
 246
 247
 248 typedef struct _tx_desc_cmd_819x_pci {
 249         //DWORD 0
 250         u16     PktSize;
 251         u8      Reserved1;
 252         u8      CmdType:3;
 253         u8      CmdInit:1;
 254         u8      LastSeg:1;
 255         u8      FirstSeg:1;
 256         u8      LINIP:1;
 257         u8      OWN:1;
 258
 259         //DOWRD 1
 260         u16     ElementReport;
 261         u16     Reserved2;
 262
 263         //DOWRD 2
 264         u16     TxBufferSize;
 265         u16     Reserved3;
 266
 267        //DWORD 3,4,5
 268         u32     TxBufferAddr;
 269         u32     NextDescAddress;
 270         u32     Reserved4;
 271         u32     Reserved5;
 272         u32     Reserved6;
 273 }tx_desc_cmd_819x_pci, *ptx_desc_cmd_819x_pci;
 274
 275
 276 typedef struct _tx_fwinfo_819x_pci {
 277         //DOWRD 0
 278         u8              TxRate:7;
 279         u8              CtsEnable:1;
 280         u8              RtsRate:7;
 281         u8              RtsEnable:1;
 282         u8              TxHT:1;
 283         u8              Short:1;                //Short PLCP for CCK, or short GI for 11n MCS
 284         u8              TxBandwidth:1;          // This is used for HT MCS rate only.
 285         u8              TxSubCarrier:2;         // This is used for legacy OFDM rate only.
 286         u8              STBC:2;
 287         u8              AllowAggregation:1;
 288         u8              RtsHT:1;                //Interpre RtsRate field as high throughput data rate
 289         u8              RtsShort:1;             //Short PLCP for CCK, or short GI for 11n MCS
 290         u8              RtsBandwidth:1;         // This is used for HT MCS rate only.
 291         u8              RtsSubcarrier:2;        // This is used for legacy OFDM rate only.
 292         u8              RtsSTBC:2;
 293         u8              EnableCPUDur:1;         //Enable firmware to recalculate and assign packet duration
 294
 295         //DWORD 1
 296         u8              RxMF:2;
 297         u8              RxAMD:3;
 298         u8              Reserved1:3;
 299         u8              Reserved2;
 300         u8              Reserved3;
 301         u8              Reserved4;
 302
 303         //u32                Reserved;
 304 }tx_fwinfo_819x_pci, *ptx_fwinfo_819x_pci;
 305
 306 typedef struct _rx_desc_819x_pci{
 307         //DOWRD 0
 308         u16                     Length:14;
 309         u16                     CRC32:1;
 310         u16                     ICV:1;
 311         u8                      RxDrvInfoSize;
 312         u8                      Shift:2;
 313         u8                      PHYStatus:1;
 314         u8                      SWDec:1;
 315         u8                                      LastSeg:1;
 316         u8                                      FirstSeg:1;
 317         u8                                      EOR:1;
 318         u8                                      OWN:1;
 319
 320         //DWORD 1
 321         u32                     Reserved2;
 322
 323         //DWORD 2
 324         u32                     Reserved3;
 325
 326         //DWORD 3
 327         u32     BufferAddress;
 328
 329 }rx_desc_819x_pci, *prx_desc_819x_pci;
 330
 331 typedef struct _rx_fwinfo_819x_pci{
 332         //DWORD 0
 333         u16                     Reserved1:12;
 334         u16                     PartAggr:1;
 335         u16                     FirstAGGR:1;
 336         u16                     Reserved2:2;
 337
 338         u8                      RxRate:7;
 339         u8                      RxHT:1;
 340
 341         u8                      BW:1;
 342         u8                      SPLCP:1;
 343         u8                      Reserved3:2;
 344         u8                      PAM:1;
 345         u8                      Mcast:1;
 346         u8                      Bcast:1;
 347         u8                      Reserved4:1;
 348
 349         //DWORD 1
 350         u32                     TSFL;
 351
 352 }rx_fwinfo_819x_pci, *prx_fwinfo_819x_pci;
 353
 354 #define MAX_DEV_ADDR_SIZE               8  /* support till 64 bit bus width OS */
 355 #define MAX_FIRMWARE_INFORMATION_SIZE   32 /*2006/04/30 by Emily forRTL8190*/
 356 #define MAX_802_11_HEADER_LENGTH        (40 + MAX_FIRMWARE_INFORMATION_SIZE)
 357 #define ENCRYPTION_MAX_OVERHEAD         128
 358 #define MAX_FRAGMENT_COUNT              8
 359 #define MAX_TRANSMIT_BUFFER_SIZE        (1600+(MAX_802_11_HEADER_LENGTH+ENCRYPTION_MAX_OVERHEAD)*MAX_FRAGMENT_COUNT)
 360
 361 #define scrclng                                 4               // octets for crc32 (FCS, ICV)
 362 /* 8190 Loopback Mode definition */
 363 typedef enum _rtl819x_loopback{
 364         RTL819X_NO_LOOPBACK = 0,
 365         RTL819X_MAC_LOOPBACK = 1,
 366         RTL819X_DMA_LOOPBACK = 2,
 367         RTL819X_CCK_LOOPBACK = 3,
 368 }rtl819x_loopback_e;
 369
 370 /* due to rtl8192 firmware */
 371 typedef enum _desc_packet_type_e{
 372         DESC_PACKET_TYPE_INIT = 0,
 373         DESC_PACKET_TYPE_NORMAL = 1,
 374 }desc_packet_type_e;
 375
 376 typedef enum _firmware_status{
 377         FW_STATUS_0_INIT = 0,
 378         FW_STATUS_1_MOVE_BOOT_CODE = 1,
 379         FW_STATUS_2_MOVE_MAIN_CODE = 2,
 380         FW_STATUS_3_TURNON_CPU = 3,
 381         FW_STATUS_4_MOVE_DATA_CODE = 4,
 382         FW_STATUS_5_READY = 5,
 383 }firmware_status_e;
 384
 385 typedef struct _rt_firmware{
 386         firmware_status_e firmware_status;
 387         u16               cmdpacket_frag_thresold;
 388 #define RTL8190_MAX_FIRMWARE_CODE_SIZE  64000   //64k
 389 #define MAX_FW_INIT_STEP                3
 390         u8                firmware_buf[MAX_FW_INIT_STEP][RTL8190_MAX_FIRMWARE_CODE_SIZE];
 391         u16               firmware_buf_size[MAX_FW_INIT_STEP];
 392 }rt_firmware, *prt_firmware;
 393
 394 #define MAX_RECEIVE_BUFFER_SIZE 9100    // Add this to 9100 bytes to receive A-MSDU from RT-AP
 395
 396 /* Firmware Queue Layout */
 397 #define NUM_OF_FIRMWARE_QUEUE           10
 398 #define NUM_OF_PAGES_IN_FW              0x100
 399 #define NUM_OF_PAGE_IN_FW_QUEUE_BE      0x0aa
 400 #define NUM_OF_PAGE_IN_FW_QUEUE_BK      0x007
 401 #define NUM_OF_PAGE_IN_FW_QUEUE_VI      0x024
 402 #define NUM_OF_PAGE_IN_FW_QUEUE_VO      0x007
 403 #define NUM_OF_PAGE_IN_FW_QUEUE_HCCA    0
 404 #define NUM_OF_PAGE_IN_FW_QUEUE_CMD     0x2
 405 #define NUM_OF_PAGE_IN_FW_QUEUE_MGNT    0x10
 406 #define NUM_OF_PAGE_IN_FW_QUEUE_HIGH    0
 407 #define NUM_OF_PAGE_IN_FW_QUEUE_BCN     0x4
 408 #define NUM_OF_PAGE_IN_FW_QUEUE_PUB     0xd
 409 #define APPLIED_RESERVED_QUEUE_IN_FW    0x80000000
 410 #define RSVD_FW_QUEUE_PAGE_BK_SHIFT     0x00
 411 #define RSVD_FW_QUEUE_PAGE_BE_SHIFT     0x08
 412 #define RSVD_FW_QUEUE_PAGE_VI_SHIFT     0x10
 413 #define RSVD_FW_QUEUE_PAGE_VO_SHIFT     0x18
 414 #define RSVD_FW_QUEUE_PAGE_MGNT_SHIFT   0x10
 415 #define RSVD_FW_QUEUE_PAGE_CMD_SHIFT    0x08
 416 #define RSVD_FW_QUEUE_PAGE_BCN_SHIFT    0x00
 417 #define RSVD_FW_QUEUE_PAGE_PUB_SHIFT    0x08
 418
 419 #define DCAM                    0xAC                    // Debug CAM Interface
 420 #define AESMSK_FC               0xB2    // AES Mask register for frame control (0xB2~0xB3). Added by Annie, 2006-03-06.
 421
 422
 423 #define CAM_CONTENT_COUNT       8
 424 #define CFG_VALID               BIT15
 425 #define EPROM_93c46 0
 426 #define EPROM_93c56 1
 427
 428 #define DEFAULT_FRAG_THRESHOLD 2342U
 429 #define MIN_FRAG_THRESHOLD     256U
 430 #define DEFAULT_BEACONINTERVAL 0x64U
 431
 432 #define DEFAULT_RETRY_RTS 7
 433 #define DEFAULT_RETRY_DATA 7
 434
 435 #define         PHY_RSSI_SLID_WIN_MAX                           100
 436
 437
 438 typedef enum _WIRELESS_MODE {
 439         WIRELESS_MODE_UNKNOWN = 0x00,
 440         WIRELESS_MODE_A = 0x01,
 441         WIRELESS_MODE_B = 0x02,
 442         WIRELESS_MODE_G = 0x04,
 443         WIRELESS_MODE_AUTO = 0x08,
 444         WIRELESS_MODE_N_24G = 0x10,
 445         WIRELESS_MODE_N_5G = 0x20
 446 } WIRELESS_MODE;
 447
 448 #define RTL_IOCTL_WPA_SUPPLICANT                SIOCIWFIRSTPRIV+30
 449
 450 typedef struct buffer
 451 {
 452         struct buffer *next;
 453         u32 *buf;
 454         dma_addr_t dma;
 455
 456 } buffer;
 457
 458 typedef struct _rt_9x_tx_rate_history {
 459         u32             cck[4];
 460         u32             ofdm[8];
 461         // HT_MCS[0][]: BW=0 SG=0
 462         // HT_MCS[1][]: BW=1 SG=0
 463         // HT_MCS[2][]: BW=0 SG=1
 464         // HT_MCS[3][]: BW=1 SG=1
 465         u32             ht_mcs[4][16];
 466 }rt_tx_rahis_t, *prt_tx_rahis_t;
 467
 468 typedef struct _RT_SMOOTH_DATA_4RF {
 469         char    elements[4][100];//array to store values
 470         u32     index;                  //index to current array to store
 471         u32     TotalNum;               //num of valid elements
 472         u32     TotalVal[4];            //sum of valid elements
 473 }RT_SMOOTH_DATA_4RF, *PRT_SMOOTH_DATA_4RF;
 474
 475 typedef enum _tag_TxCmd_Config_Index{
 476         TXCMD_TXRA_HISTORY_CTRL                         = 0xFF900000,
 477         TXCMD_RESET_TX_PKT_BUFF                         = 0xFF900001,
 478         TXCMD_RESET_RX_PKT_BUFF                         = 0xFF900002,
 479         TXCMD_SET_TX_DURATION                           = 0xFF900003,
 480         TXCMD_SET_RX_RSSI                                               = 0xFF900004,
 481         TXCMD_SET_TX_PWR_TRACKING                       = 0xFF900005,
 482         TXCMD_XXXX_CTRL,
 483 }DCMD_TXCMD_OP;
 484
 485 typedef struct Stats
 486 {
 487         unsigned long rxrdu;
 488         unsigned long rxok;
 489         unsigned long received_rate_histogram[4][32];   //0: Total, 1:OK, 2:CRC, 3:ICV
 490         unsigned long rxoverflow;
 491         unsigned long rxint;
 492         unsigned long txoverflow;
 493         unsigned long txbeokint;
 494         unsigned long txbkokint;
 495         unsigned long txviokint;
 496         unsigned long txvookint;
 497         unsigned long txbeaconokint;
 498         unsigned long txbeaconerr;
 499         unsigned long txmanageokint;
 500         unsigned long txcmdpktokint;
 501         unsigned long txfeedback;
 502         unsigned long txfeedbackok;
 503         unsigned long txoktotal;
 504         unsigned long txbytesunicast;
 505         unsigned long rxbytesunicast;
 506
 507         unsigned long slide_signal_strength[100];
 508         unsigned long slide_evm[100];
 509         unsigned long   slide_rssi_total;       // For recording sliding window's RSSI value
 510         unsigned long slide_evm_total;  // For recording sliding window's EVM value
 511         long signal_strength; // Transformed, in dbm. Beautified signal strength for UI, not correct.
 512         u8 rx_rssi_percentage[4];
 513         u8 rx_evm_percentage[2];
 514         u32 Slide_Beacon_pwdb[100];
 515         u32 Slide_Beacon_Total;
 516         RT_SMOOTH_DATA_4RF              cck_adc_pwdb;
 517 } Stats;
 518
 519
 520 // Bandwidth Offset
 521 #define HAL_PRIME_CHNL_OFFSET_DONT_CARE         0
 522 #define HAL_PRIME_CHNL_OFFSET_LOWER                     1
 523 #define HAL_PRIME_CHNL_OFFSET_UPPER                     2
 524
 525 typedef struct  ChnlAccessSetting {
 526         u16 SIFS_Timer;
 527         u16 DIFS_Timer;
 528         u16 SlotTimeTimer;
 529         u16 EIFS_Timer;
 530         u16 CWminIndex;
 531         u16 CWmaxIndex;
 532 }*PCHANNEL_ACCESS_SETTING,CHANNEL_ACCESS_SETTING;
 533
 534 typedef struct _BB_REGISTER_DEFINITION{
 535         u32 rfintfs;                    // set software control: //             0x870~0x877[8 bytes]
 536         u32 rfintfi;                    // readback data: //            0x8e0~0x8e7[8 bytes]
 537         u32 rfintfo;                    // output data: //              0x860~0x86f [16 bytes]
 538         u32 rfintfe;                    // output enable: //            0x860~0x86f [16 bytes]
 539         u32 rf3wireOffset;              // LSSI data: //                0x840~0x84f [16 bytes]
 540         u32 rfLSSI_Select;              // BB Band Select: //           0x878~0x87f [8 bytes]
 541         u32 rfTxGainStage;              // Tx gain stage: //            0x80c~0x80f [4 bytes]
 542         u32 rfHSSIPara1;                // wire parameter control1 : //         0x820~0x823,0x828~0x82b, 0x830~0x833, 0x838~0x83b [16 bytes]
 543         u32 rfHSSIPara2;                // wire parameter control2 : //         0x824~0x827,0x82c~0x82f, 0x834~0x837, 0x83c~0x83f [16 bytes]
 544         u32 rfSwitchControl;    //Tx Rx antenna control : //            0x858~0x85f [16 bytes]
 545         u32 rfAGCControl1;      //AGC parameter control1 : //           0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63, 0xc68~0xc6b [16 bytes]
 546         u32 rfAGCControl2;      //AGC parameter control2 : //           0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67, 0xc6c~0xc6f [16 bytes]
 547         u32 rfRxIQImbalance;    //OFDM Rx IQ imbalance matrix : //              0xc14~0xc17,0xc1c~0xc1f, 0xc24~0xc27, 0xc2c~0xc2f [16 bytes]
 548         u32 rfRxAFE;                    //Rx IQ DC ofset and Rx digital filter, Rx DC notch filter : //         0xc10~0xc13,0xc18~0xc1b, 0xc20~0xc23, 0xc28~0xc2b [16 bytes]
 549         u32 rfTxIQImbalance;    //OFDM Tx IQ imbalance matrix //                0xc80~0xc83,0xc88~0xc8b, 0xc90~0xc93, 0xc98~0xc9b [16 bytes]
 550         u32 rfTxAFE;                    //Tx IQ DC Offset and Tx DFIR type //           0xc84~0xc87,0xc8c~0xc8f, 0xc94~0xc97, 0xc9c~0xc9f [16 bytes]
 551         u32 rfLSSIReadBack;     //LSSI RF readback data //              0x8a0~0x8af [16 bytes]
 552 }BB_REGISTER_DEFINITION_T, *PBB_REGISTER_DEFINITION_T;
 553
 554 typedef struct _rate_adaptive
 555 {
 556         u8                              rate_adaptive_disabled;
 557         u8                              ratr_state;
 558         u16                             reserve;
 559
 560         u32                             high_rssi_thresh_for_ra;
 561         u32                             high2low_rssi_thresh_for_ra;
 562         u8                              low2high_rssi_thresh_for_ra40M;
 563         u32                             low_rssi_thresh_for_ra40M;
 564         u8                              low2high_rssi_thresh_for_ra20M;
 565         u32                             low_rssi_thresh_for_ra20M;
 566         u32                             upper_rssi_threshold_ratr;
 567         u32                             middle_rssi_threshold_ratr;
 568         u32                             low_rssi_threshold_ratr;
 569         u32                             low_rssi_threshold_ratr_40M;
 570         u32                             low_rssi_threshold_ratr_20M;
 571         u8                              ping_rssi_enable;       //cosa add for test
 572         u32                             ping_rssi_ratr; //cosa add for test
 573         u32                             ping_rssi_thresh_for_ra;//cosa add for test
 574         u32                             last_ratr;
 575
 576 } rate_adaptive, *prate_adaptive;
 577 #define TxBBGainTableLength 37
 578 #define CCKTxBBGainTableLength 23
 579 typedef struct _txbbgain_struct
 580 {
 581         long    txbb_iq_amplifygain;
 582         u32     txbbgain_value;
 583 } txbbgain_struct, *ptxbbgain_struct;
 584
 585 typedef struct _ccktxbbgain_struct
 586 {
 587         //The Value is from a22 to a29 one Byte one time is much Safer
 588         u8      ccktxbb_valuearray[8];
 589 } ccktxbbgain_struct,*pccktxbbgain_struct;
 590
 591
 592 typedef struct _init_gain
 593 {
 594         u8                              xaagccore1;
 595         u8                              xbagccore1;
 596         u8                              xcagccore1;
 597         u8                              xdagccore1;
 598         u8                              cca;
 599
 600 } init_gain, *pinit_gain;
 601
 602 /* 2007/11/02 MH Define RF mode temporarily for test. */
 603 typedef enum tag_Rf_Operatetion_State
 604 {
 605     RF_STEP_INIT = 0,
 606     RF_STEP_NORMAL,
 607     RF_STEP_MAX
 608 }RF_STEP_E;
 609
 610 typedef enum _RT_STATUS{
 611         RT_STATUS_SUCCESS,
 612         RT_STATUS_FAILURE,
 613         RT_STATUS_PENDING,
 614         RT_STATUS_RESOURCE
 615 }RT_STATUS,*PRT_STATUS;
 616
 617 typedef enum _RT_CUSTOMER_ID
 618 {
 619         RT_CID_DEFAULT = 0,
 620         RT_CID_8187_ALPHA0 = 1,
 621         RT_CID_8187_SERCOMM_PS = 2,
 622         RT_CID_8187_HW_LED = 3,
 623         RT_CID_8187_NETGEAR = 4,
 624         RT_CID_WHQL = 5,
 625         RT_CID_819x_CAMEO  = 6,
 626         RT_CID_819x_RUNTOP = 7,
 627         RT_CID_819x_Senao = 8,
 628         RT_CID_TOSHIBA = 9,     // Merge by Jacken, 2008/01/31.
 629         RT_CID_819x_Netcore = 10,
 630         RT_CID_Nettronix = 11,
 631         RT_CID_DLINK = 12,
 632         RT_CID_PRONET = 13,
 633         RT_CID_COREGA = 14,
 634 }RT_CUSTOMER_ID, *PRT_CUSTOMER_ID;
 635
 636 /* LED customization. */
 637
 638 typedef enum _LED_STRATEGY_8190{
 639         SW_LED_MODE0, // SW control 1 LED via GPIO0. It is default option.
 640         SW_LED_MODE1, // SW control for PCI Express
 641         SW_LED_MODE2, // SW control for Cameo.
 642         SW_LED_MODE3, // SW contorl for RunTop.
 643         SW_LED_MODE4, // SW control for Netcore
 644         SW_LED_MODE5, //added by vivi, for led new mode, DLINK
 645         SW_LED_MODE6, //added by vivi, for led new mode, PRONET
 646         HW_LED, // HW control 2 LEDs, LED0 and LED1 (there are 4 different control modes)
 647 }LED_STRATEGY_8190, *PLED_STRATEGY_8190;
 648
 649 #define CHANNEL_PLAN_LEN                                10
 650
 651 #define sCrcLng                 4
 652
 653 typedef struct _TX_FWINFO_STRUCUTRE{
 654         //DOWRD 0
 655         u8                      TxRate:7;
 656         u8                      CtsEnable:1;
 657         u8                      RtsRate:7;
 658         u8                      RtsEnable:1;
 659         u8                      TxHT:1;
 660         u8                      Short:1;
 661         u8                      TxBandwidth:1;
 662         u8                      TxSubCarrier:2;
 663         u8                      STBC:2;
 664         u8                      AllowAggregation:1;
 665         u8                      RtsHT:1;
 666         u8                      RtsShort:1;
 667         u8                      RtsBandwidth:1;
 668         u8                      RtsSubcarrier:2;
 669         u8                      RtsSTBC:2;
 670         u8                      EnableCPUDur:1;
 671
 672         //DWORD 1
 673         u32                     RxMF:2;
 674         u32                     RxAMD:3;
 675         u32                     Reserved1:3;
 676         u32                     TxAGCOffset:4;
 677         u32                     TxAGCSign:1;
 678         u32                     Tx_INFO_RSVD:6;
 679         u32                     PacketID:13;
 680 }TX_FWINFO_T;
 681
 682
 683 typedef struct _TX_FWINFO_8190PCI{
 684         //DOWRD 0
 685         u8                      TxRate:7;
 686         u8                      CtsEnable:1;
 687         u8                      RtsRate:7;
 688         u8                      RtsEnable:1;
 689         u8                      TxHT:1;
 690         u8                      Short:1;                                                //Short PLCP for CCK, or short GI for 11n MCS
 691         u8                      TxBandwidth:1;                          // This is used for HT MCS rate only.
 692         u8                      TxSubCarrier:2;                         // This is used for legacy OFDM rate only.
 693         u8                      STBC:2;
 694         u8                      AllowAggregation:1;
 695         u8                      RtsHT:1;                                                //Interpre RtsRate field as high throughput data rate
 696         u8                      RtsShort:1;                             //Short PLCP for CCK, or short GI for 11n MCS
 697         u8                      RtsBandwidth:1;                         // This is used for HT MCS rate only.
 698         u8                      RtsSubcarrier:2;                                // This is used for legacy OFDM rate only.
 699         u8                      RtsSTBC:2;
 700         u8                      EnableCPUDur:1;                         //Enable firmware to recalculate and assign packet duration
 701
 702         //DWORD 1
 703         u32                     RxMF:2;
 704         u32                     RxAMD:3;
 705         u32                     TxPerPktInfoFeedback:1;         // 1: indicate that the transimission info of this packet should be gathered by Firmware and retured by Rx Cmd.
 706         u32                     Reserved1:2;
 707         u32                     TxAGCOffset:4;          // Only 90 support
 708         u32                     TxAGCSign:1;            // Only 90 support
 709         u32                     RAW_TXD:1;                      // MAC will send data in txpktbuffer without any processing,such as CRC check
 710         u32                     Retry_Limit:4;          // CCX Support relative retry limit FW page only support 4 bits now.
 711         u32                     Reserved2:1;
 712         u32                     PacketID:13;
 713
 714         // DW 2
 715
 716 }TX_FWINFO_8190PCI, *PTX_FWINFO_8190PCI;
 717
 718 typedef struct _phy_ofdm_rx_status_report_819xpci
 719 {
 720         u8      trsw_gain_X[4];
 721         u8      pwdb_all;
 722         u8      cfosho_X[4];
 723         u8      cfotail_X[4];
 724         u8      rxevm_X[2];
 725         u8      rxsnr_X[4];
 726         u8      pdsnr_X[2];
 727         u8      csi_current_X[2];
 728         u8      csi_target_X[2];
 729         u8      sigevm;
 730         u8      max_ex_pwr;
 731         u8      sgi_en;
 732         u8      rxsc_sgien_exflg;
 733 }phy_sts_ofdm_819xpci_t;
 734
 735 typedef struct _phy_cck_rx_status_report_819xpci
 736 {
 737         /* For CCK rate descriptor. This is a unsigned 8:1 variable. LSB bit presend
 738            0.5. And MSB 7 bts presend a signed value. Range from -64~+63.5. */
 739         u8      adc_pwdb_X[4];
 740         u8      sq_rpt;
 741         u8      cck_agc_rpt;
 742 }phy_sts_cck_819xpci_t;
 743
 744 typedef struct _phy_ofdm_rx_status_rxsc_sgien_exintfflag{
 745         u8                      reserved:4;
 746         u8                      rxsc:2;
 747         u8                      sgi_en:1;
 748         u8                      ex_intf_flag:1;
 749 }phy_ofdm_rx_status_rxsc_sgien_exintfflag;
 750
 751 typedef enum _RT_OP_MODE{
 752         RT_OP_MODE_AP,
 753         RT_OP_MODE_INFRASTRUCTURE,
 754         RT_OP_MODE_IBSS,
 755         RT_OP_MODE_NO_LINK,
 756 }RT_OP_MODE, *PRT_OP_MODE;
 757
 758
 759 /* 2007/11/02 MH Define RF mode temporarily for test. */
 760 typedef enum tag_Rf_OpType
 761 {
 762     RF_OP_By_SW_3wire = 0,
 763     RF_OP_By_FW,
 764     RF_OP_MAX
 765 }RF_OpType_E;
 766
 767 typedef enum _RESET_TYPE {
 768         RESET_TYPE_NORESET = 0x00,
 769         RESET_TYPE_NORMAL = 0x01,
 770         RESET_TYPE_SILENT = 0x02
 771 } RESET_TYPE;
 772
 773 typedef struct _tx_ring{
 774         u32 * desc;
 775         u8 nStuckCount;
 776         struct _tx_ring * next;
 777 }__attribute__ ((packed)) tx_ring, * ptx_ring;
 778
 779 struct rtl8192_tx_ring {
 780     tx_desc_819x_pci *desc;
 781     dma_addr_t dma;
 782     unsigned int idx;
 783     unsigned int entries;
 784     struct sk_buff_head queue;
 785 };
 786
 787 #define NIC_SEND_HANG_THRESHOLD_NORMAL          4
 788 #define NIC_SEND_HANG_THRESHOLD_POWERSAVE       8
 789 #define MAX_TX_QUEUE                            9       // BK, BE, VI, VO, HCCA, MANAGEMENT, COMMAND, HIGH, BEACON.
 790
 791 #define MAX_RX_COUNT                            64
 792 #define MAX_TX_QUEUE_COUNT                      9
 793
 794 typedef struct r8192_priv
 795 {
 796         struct pci_dev *pdev;
 797         /* maintain info from eeprom */
 798         short epromtype;
 799         u16 eeprom_vid;
 800         u16 eeprom_did;
 801         u8  eeprom_CustomerID;
 802         u16  eeprom_ChannelPlan;
 803         RT_CUSTOMER_ID CustomerID;
 804         LED_STRATEGY_8190       LedStrategy;
 805         u8      IC_Cut;
 806         int irq;
 807         struct ieee80211_device *ieee80211;
 808 #ifdef ENABLE_LPS
 809         bool ps_force;
 810         bool force_lps;
 811         bool bdisable_nic;
 812 #endif
 813         bool being_init_adapter;
 814         u8 Rf_Mode;
 815         u8 card_8192_version; /* if TCR reports card V B/C this discriminates */
 816         spinlock_t irq_th_lock;
 817         spinlock_t rf_ps_lock;
 818         struct mutex mutex;
 819
 820         short chan;
 821         short sens;
 822         /* RX stuff */
 823         rx_desc_819x_pci *rx_ring;
 824         dma_addr_t rx_ring_dma;
 825         unsigned int rx_idx;
 826         struct sk_buff *rx_buf[MAX_RX_COUNT];
 827         int rxringcount;
 828         u16 rxbuffersize;
 829
 830         struct sk_buff *rx_skb;
 831         u32 *rxring;
 832         u32 *rxringtail;
 833         dma_addr_t rxringdma;
 834         struct buffer *rxbuffer;
 835         struct buffer *rxbufferhead;
 836         short rx_skb_complete;
 837         /* TX stuff */
 838         struct rtl8192_tx_ring tx_ring[MAX_TX_QUEUE_COUNT];
 839         int txringcount;
 840
 841         struct tasklet_struct irq_rx_tasklet;
 842         struct tasklet_struct irq_tx_tasklet;
 843         struct tasklet_struct irq_prepare_beacon_tasklet;
 844
 845         short up;
 846         short crcmon; //if 1 allow bad crc frame reception in monitor mode
 847         struct semaphore wx_sem;
 848         struct semaphore rf_sem; //used to lock rf write operation added by wb, modified by david
 849         u8 rf_type; /* 0 means 1T2R, 1 means 2T4R */
 850
 851         short (*rf_set_sens)(struct net_device *dev,short sens);
 852         u8 (*rf_set_chan)(struct net_device *dev,u8 ch);
 853         void (*rf_close)(struct net_device *dev);
 854         void (*rf_init)(struct net_device *dev);
 855         short promisc;
 856         /* stats */
 857         struct Stats stats;
 858         struct iw_statistics wstats;
 859         struct proc_dir_entry *dir_dev;
 860         struct ieee80211_rx_stats previous_stats;
 861
 862         /* RX stuff */
 863         struct sk_buff_head skb_queue;
 864         struct work_struct qos_activate;
 865
 866         //2 Tx Related variables
 867         u16     ShortRetryLimit;
 868         u16     LongRetryLimit;
 869
 870         u32     LastRxDescTSFHigh;
 871         u32     LastRxDescTSFLow;
 872
 873
 874         //2 Rx Related variables
 875         u32     ReceiveConfig;
 876
 877         u8 retry_data;
 878         u8 retry_rts;
 879
 880         struct work_struct reset_wq;
 881         u8      rx_chk_cnt;
 882
 883 //for rtl819xPci
 884         // Data Rate Config. Added by Annie, 2006-04-13.
 885         u16     basic_rate;
 886         u8      short_preamble;
 887         u8      slot_time;
 888         u16 SifsTime;
 889 /* WirelessMode*/
 890         u8 RegWirelessMode;
 891 /*Firmware*/
 892         prt_firmware            pFirmware;
 893         rtl819x_loopback_e      LoopbackMode;
 894         bool AutoloadFailFlag;
 895         u16 EEPROMAntPwDiff;            // Antenna gain offset from B/C/D to A
 896         u8 EEPROMThermalMeter;
 897         u8 EEPROMCrystalCap;
 898         u8 EEPROMTxPowerLevelCCK[14];// CCK channel 1~14
 899         // The following definition is for eeprom 93c56
 900         u8 EEPROMRfACCKChnl1TxPwLevel[3];       //RF-A CCK Tx Power Level at channel 7
 901         u8 EEPROMRfAOfdmChnlTxPwLevel[3];//RF-A CCK Tx Power Level at [0],[1],[2] = channel 1,7,13
 902         u8 EEPROMRfCCCKChnl1TxPwLevel[3];       //RF-C CCK Tx Power Level at channel 7
 903         u8 EEPROMRfCOfdmChnlTxPwLevel[3];//RF-C CCK Tx Power Level at [0],[1],[2] = channel 1,7,13
 904         u8 EEPROMTxPowerLevelOFDM24G[14]; // OFDM 2.4G channel 1~14
 905         u8 EEPROMLegacyHTTxPowerDiff;   // Legacy to HT rate power diff
 906         bool bTXPowerDataReadFromEEPORM;
 907 /*channel plan*/
 908         u16 RegChannelPlan; // Channel Plan specifed by user, 15: following setting of EEPROM, 0-14: default channel plan index specified by user.
 909         u16 ChannelPlan;
 910 /*PS related*/
 911         // Rf off action for power save
 912         u8      bHwRfOffAction; //0:No action, 1:By GPIO, 2:By Disable
 913 /*PHY related*/
 914         BB_REGISTER_DEFINITION_T        PHYRegDef[4];   //Radio A/B/C/D
 915         // Read/write are allow for following hardware information variables
 916         u32     MCSTxPowerLevelOriginalOffset[6];
 917         u32     CCKTxPowerLevelOriginalOffset;
 918         u8      TxPowerLevelCCK[14];                    // CCK channel 1~14
 919         u8      TxPowerLevelCCK_A[14];                  // RF-A, CCK channel 1~14
 920         u8      TxPowerLevelCCK_C[14];
 921         u8      TxPowerLevelOFDM24G[14];                // OFDM 2.4G channel 1~14
 922         u8      TxPowerLevelOFDM5G[14];                 // OFDM 5G
 923         u8      TxPowerLevelOFDM24G_A[14];      // RF-A, OFDM 2.4G channel 1~14
 924         u8      TxPowerLevelOFDM24G_C[14];      // RF-C, OFDM 2.4G channel 1~14
 925         u8      LegacyHTTxPowerDiff;                    // Legacy to HT rate power diff
 926         u8      TxPowerDiff;
 927         char    RF_C_TxPwDiff;                                  // Antenna gain offset, rf-c to rf-a
 928         u8      AntennaTxPwDiff[3];                             // Antenna gain offset, index 0 for B, 1 for C, and 2 for D
 929         u8      CrystalCap;                                             // CrystalCap.
 930         u8      ThermalMeter[2];                                // ThermalMeter, index 0 for RFIC0, and 1 for RFIC1
 931         //05/27/2008 cck power enlarge
 932         u8      CckPwEnl;
 933         u16     TSSI_13dBm;
 934         u32     Pwr_Track;
 935         u8                              CCKPresentAttentuation_20Mdefault;
 936         u8                              CCKPresentAttentuation_40Mdefault;
 937         char                            CCKPresentAttentuation_difference;
 938         char                            CCKPresentAttentuation;
 939         // Use to calculate PWBD.
 940         RT_RF_POWER_STATE               eRFPowerState;
 941         RT_RF_CHANGE_SOURCE     RfOffReason;
 942         RT_POWER_SAVE_CONTROL   PowerSaveControl;
 943         u8      bCckHighPower;
 944         long    undecorated_smoothed_pwdb;
 945         long    undecorated_smoothed_cck_adc_pwdb[4];
 946         //for set channel
 947         u8      SwChnlInProgress;
 948         u8      SwChnlStage;
 949         u8      SwChnlStep;
 950         u8      SetBWModeInProgress;
 951         HT_CHANNEL_WIDTH                CurrentChannelBW;
 952
 953         // 8190 40MHz mode
 954         //
 955         u8      nCur40MhzPrimeSC;       // Control channel sub-carrier
 956         // Joseph test for shorten RF configuration time.
 957         // We save RF reg0 in this variable to reduce RF reading.
 958         //
 959         u32                                     RfReg0Value[4];
 960         u8                                      NumTotalRFPath;
 961         bool                            brfpath_rxenable[4];
 962 //+by amy 080507
 963         struct timer_list watch_dog_timer;
 964         u8 watchdog_last_time;
 965         u8 watchdog_check_reset_cnt;
 966
 967 //+by amy 080515 for dynamic mechenism
 968         //Add by amy Tx Power Control for Near/Far Range 2008/05/15
 969         bool    bdynamic_txpower;  //bDynamicTxPower
 970         bool    bDynamicTxHighPower;  // Tx high power state
 971         bool    bDynamicTxLowPower;  // Tx low power state
 972         bool    bLastDTPFlag_High;
 973         bool    bLastDTPFlag_Low;
 974
 975         /* OFDM RSSI. For high power or not */
 976         u8      phy_check_reg824;
 977         u32     phy_reg824_bit9;
 978
 979         //Add by amy for Rate Adaptive
 980         rate_adaptive rate_adaptive;
 981         //Add by amy for TX power tracking
 982         //2008/05/15  Mars OPEN/CLOSE TX POWER TRACKING
 983         const txbbgain_struct * txbbgain_table;
 984         u8                         txpower_count;//For 6 sec do tracking again
 985         bool                       btxpower_trackingInit;
 986         u8                         OFDM_index;
 987         u8                         CCK_index;
 988         u8                         Record_CCK_20Mindex;
 989         u8                         Record_CCK_40Mindex;
 990         //2007/09/10 Mars Add CCK TX Power Tracking
 991         const ccktxbbgain_struct *cck_txbbgain_table;
 992         const ccktxbbgain_struct *cck_txbbgain_ch14_table;
 993         u8 rfa_txpowertrackingindex;
 994         u8 rfa_txpowertrackingindex_real;
 995         u8 rfa_txpowertracking_default;
 996         u8 rfc_txpowertrackingindex;
 997         u8 rfc_txpowertrackingindex_real;
 998         u8 rfc_txpowertracking_default;
 999         bool btxpower_tracking;
1000         bool bcck_in_ch14;
1001
1002         //For Backup Initial Gain
1003         init_gain initgain_backup;
1004         u8              DefaultInitialGain[4];
1005         // For EDCA Turbo mode, Added by amy 080515.
1006         bool            bis_any_nonbepkts;
1007         bool            bcurrent_turbo_EDCA;
1008
1009         bool            bis_cur_rdlstate;
1010         struct timer_list fsync_timer;
1011         u32     rate_record;
1012         u32     rateCountDiffRecord;
1013         u32     ContiuneDiffCount;
1014         bool bswitch_fsync;
1015
1016         u8      framesync;
1017         u32     framesyncC34;
1018         u8      framesyncMonitor;
1019
1020         //by amy for gpio
1021         bool bHwRadioOff;
1022         //by amy for ps
1023         RT_OP_MODE OpMode;
1024         //by amy for reset_count
1025         u32 reset_count;
1026
1027         //by amy for silent reset
1028         RESET_TYPE      ResetProgress;
1029         bool            bForcedSilentReset;
1030         bool            bDisableNormalResetCheck;
1031         u16             TxCounter;
1032         u16             RxCounter;
1033         int             IrpPendingCount;
1034         bool            bResetInProgress;
1035         bool            force_reset;
1036         u8              InitialGainOperateType;
1037
1038         //define work item by amy 080526
1039         struct delayed_work update_beacon_wq;
1040         struct delayed_work watch_dog_wq;
1041         struct delayed_work txpower_tracking_wq;
1042         struct delayed_work rfpath_check_wq;
1043         struct delayed_work gpio_change_rf_wq;
1044         struct delayed_work initialgain_operate_wq;
1045         struct workqueue_struct *priv_wq;
1046 }r8192_priv;
1047
1048 bool init_firmware(struct net_device *dev);
1049 u32 read_cam(struct r8192_priv *priv, u8 addr);
1050 void write_cam(struct r8192_priv *priv, u8 addr, u32 data);
1051 u8 read_nic_byte(struct r8192_priv *priv, int x);
1052 u32 read_nic_dword(struct r8192_priv *priv, int x);
1053 u16 read_nic_word(struct r8192_priv *priv, int x) ;
1054 void write_nic_byte(struct r8192_priv *priv, int x,u8 y);
1055 void write_nic_word(struct r8192_priv *priv, int x,u16 y);
1056 void write_nic_dword(struct r8192_priv *priv, int x,u32 y);
1057
1058 int rtl8192_down(struct net_device *dev);
1059 int rtl8192_up(struct net_device *dev);
1060 void rtl8192_commit(struct r8192_priv *priv);
1061 void write_phy(struct net_device *dev, u8 adr, u8 data);
1062 void CamResetAllEntry(struct r8192_priv *priv);
1063 void EnableHWSecurityConfig8192(struct net_device *dev);
1064 void setKey(struct net_device *dev, u8 EntryNo, u8 KeyIndex, u16 KeyType, const u8 *MacAddr, u8 DefaultKey, u32 *KeyContent );
1065 void dm_cck_txpower_adjust(struct net_device *dev, bool binch14);
1066 void firmware_init_param(struct net_device *dev);
1067 RT_STATUS cmpk_message_handle_tx(struct net_device *dev, u8* codevirtualaddress, u32 packettype, u32 buffer_len);
1068
1069 #ifdef ENABLE_IPS
1070 void IPSEnter(struct net_device *dev);
1071 void IPSLeave(struct net_device *dev);
1072 void IPSLeave_wq(struct work_struct *work);
1073 void ieee80211_ips_leave_wq(struct net_device *dev);
1074 void ieee80211_ips_leave(struct net_device *dev);
1075 #endif
1076 #ifdef ENABLE_LPS
1077 void LeisurePSEnter(struct net_device *dev);
1078 void LeisurePSLeave(struct net_device *dev);
1079 #endif
1080
1081 bool NicIFEnableNIC(struct r8192_priv *priv);
1082 bool NicIFDisableNIC(struct r8192_priv *priv);
1083
1084 void PHY_SetRtl8192eRfOff(struct r8192_priv *priv);
1085 #endif