Pileus Git - ~andy/linux/blob - drivers/staging/rtl8192e/r8192E.h

   1 /*
   2    This is part of rtl8187 OpenSource driver.
   3    Copyright (C) Andrea Merello 2004-2005  <andreamrl@tiscali.it>
   4    Released under the terms of GPL (General Public Licence)
   5
   6    Parts of this driver are based on the GPL part of the
   7    official realtek driver
   8
   9    Parts of this driver are based on the rtl8192 driver skeleton
  10    from Patric Schenke & Andres Salomon
  11
  12    Parts of this driver are based on the Intel Pro Wireless 2100 GPL driver
  13
  14    We want to tanks the Authors of those projects and the Ndiswrapper
  15    project Authors.
  16 */
  17
  18 #ifndef R819xU_H
  19 #define R819xU_H
  20
  21 #include <linux/module.h>
  22 #include <linux/kernel.h>
  23 #include <linux/init.h>
  24 #include <linux/ioport.h>
  25 #include <linux/sched.h>
  26 #include <linux/types.h>
  27 #include <linux/slab.h>
  28 #include <linux/netdevice.h>
  29 #include <linux/pci.h>
  30 #include <linux/etherdevice.h>
  31 #include <linux/delay.h>
  32 #include <linux/rtnetlink.h>    //for rtnl_lock()
  33 #include <linux/wireless.h>
  34 #include <linux/timer.h>
  35 #include <linux/proc_fs.h>      // Necessary because we use the proc fs
  36 #include <linux/if_arp.h>
  37 #include <linux/random.h>
  38 #include <linux/version.h>
  39 #include <asm/io.h>
  40 #include "ieee80211/ieee80211.h"
  41
  42
  43
  44
  45 #define RTL819xE_MODULE_NAME "rtl819xE"
  46
  47 #define FALSE 0
  48 #define TRUE 1
  49 #define MAX_KEY_LEN     61
  50 #define KEY_BUF_SIZE    5
  51
  52 #define BIT0            0x00000001
  53 #define BIT1            0x00000002
  54 #define BIT2            0x00000004
  55 #define BIT3            0x00000008
  56 #define BIT4            0x00000010
  57 #define BIT5            0x00000020
  58 #define BIT6            0x00000040
  59 #define BIT7            0x00000080
  60 #define BIT8            0x00000100
  61 #define BIT9            0x00000200
  62 #define BIT10           0x00000400
  63 #define BIT11           0x00000800
  64 #define BIT12           0x00001000
  65 #define BIT13           0x00002000
  66 #define BIT14           0x00004000
  67 #define BIT15           0x00008000
  68 #define BIT16           0x00010000
  69 #define BIT17           0x00020000
  70 #define BIT18           0x00040000
  71 #define BIT19           0x00080000
  72 #define BIT20           0x00100000
  73 #define BIT21           0x00200000
  74 #define BIT22           0x00400000
  75 #define BIT23           0x00800000
  76 #define BIT24           0x01000000
  77 #define BIT25           0x02000000
  78 #define BIT26           0x04000000
  79 #define BIT27           0x08000000
  80 #define BIT28           0x10000000
  81 #define BIT29           0x20000000
  82 #define BIT30           0x40000000
  83 #define BIT31           0x80000000
  84 // Rx smooth factor
  85 #define Rx_Smooth_Factor                20
  86 /* 2007/06/04 MH Define sliding window for RSSI history. */
  87 #define         PHY_RSSI_SLID_WIN_MAX                           100
  88 #define         PHY_Beacon_RSSI_SLID_WIN_MAX            10
  89
  90 #define IC_VersionCut_D 0x3
  91 #define IC_VersionCut_E 0x4
  92
  93 #if 0 //we need to use RT_TRACE instead DMESG as RT_TRACE will clearly show debug level wb.
  94 #define DMESG(x,a...) printk(KERN_INFO RTL819xE_MODULE_NAME ": " x "\n", ## a)
  95 #else
  96 #define DMESG(x,a...)
  97 extern u32 rt_global_debug_component;
  98 #define RT_TRACE(component, x, args...) \
  99 do { if(rt_global_debug_component & component) \
 100         printk(KERN_DEBUG RTL819xE_MODULE_NAME ":" x "\n" , \
 101                ##args);\
 102 }while(0);
 103
 104 #define COMP_TRACE                              BIT0            // For function call tracing.
 105 #define COMP_DBG                                BIT1            // Only for temporary debug message.
 106 #define COMP_INIT                               BIT2            // during driver initialization / halt / reset.
 107
 108
 109 #define COMP_RECV                               BIT3            // Reveive part data path.
 110 #define COMP_SEND                               BIT4            // Send part path.
 111 #define COMP_IO                                 BIT5            // I/O Related. Added by Annie, 2006-03-02.
 112 #define COMP_POWER                              BIT6            // 802.11 Power Save mode or System/Device Power state related.
 113 #define COMP_EPROM                              BIT7            // 802.11 link related: join/start BSS, leave BSS.
 114 #define COMP_SWBW                               BIT8    // For bandwidth switch.
 115 #define COMP_SEC                                BIT9// For Security.
 116
 117
 118 #define COMP_TURBO                              BIT10   // For Turbo Mode related. By Annie, 2005-10-21.
 119 #define COMP_QOS                                BIT11   // For QoS.
 120
 121 #define COMP_RATE                               BIT12   // For Rate Adaptive mechanism, 2006.07.02, by rcnjko. #define COMP_EVENTS                              0x00000080      // Event handling
 122 #define COMP_RXDESC                             BIT13   // Show Rx desc information for SD3 debug. Added by Annie, 2006-07-15.
 123 #define COMP_PHY                                BIT14
 124 #define COMP_DIG                                BIT15   // For DIG, 2006.09.25, by rcnjko.
 125 #define COMP_TXAGC                              BIT16   // For Tx power, 060928, by rcnjko.
 126 #define COMP_HALDM                              BIT17   // For HW Dynamic Mechanism, 061010, by rcnjko.
 127 #define COMP_POWER_TRACKING                     BIT18   //FOR 8190 TX POWER TRACKING
 128 #define COMP_EVENTS                             BIT19   // Event handling
 129
 130 #define COMP_RF                                 BIT20   // For RF.
 131
 132 /* 11n or 8190 specific code should be put below this line */
 133
 134
 135 #define COMP_FIRMWARE                           BIT21   //for firmware downloading
 136 #define COMP_HT                                 BIT22   // For 802.11n HT related information. by Emily 2006-8-11
 137
 138 #define COMP_RESET                              BIT23
 139 #define COMP_CMDPKT                             BIT24
 140 #define COMP_SCAN                               BIT25
 141 #define COMP_IPS                                BIT26
 142 #define COMP_DOWN                               BIT27  // for rm driver module
 143 #define COMP_INTR                               BIT28  // for interrupt
 144 #define COMP_ERR                                BIT31  // for error out, always on
 145 #endif
 146
 147
 148 //
 149 // Queue Select Value in TxDesc
 150 //
 151 #define QSLT_BK                                 0x1
 152 #define QSLT_BE                                 0x0
 153 #define QSLT_VI                                 0x4
 154 #define QSLT_VO                                 0x6
 155 #define QSLT_BEACON                             0x10
 156 #define QSLT_HIGH                               0x11
 157 #define QSLT_MGNT                               0x12
 158 #define QSLT_CMD                                0x13
 159
 160 #define DESC90_RATE1M                           0x00
 161 #define DESC90_RATE2M                           0x01
 162 #define DESC90_RATE5_5M                         0x02
 163 #define DESC90_RATE11M                          0x03
 164 #define DESC90_RATE6M                           0x04
 165 #define DESC90_RATE9M                           0x05
 166 #define DESC90_RATE12M                          0x06
 167 #define DESC90_RATE18M                          0x07
 168 #define DESC90_RATE24M                          0x08
 169 #define DESC90_RATE36M                          0x09
 170 #define DESC90_RATE48M                          0x0a
 171 #define DESC90_RATE54M                          0x0b
 172 #define DESC90_RATEMCS0                         0x00
 173 #define DESC90_RATEMCS1                         0x01
 174 #define DESC90_RATEMCS2                         0x02
 175 #define DESC90_RATEMCS3                         0x03
 176 #define DESC90_RATEMCS4                         0x04
 177 #define DESC90_RATEMCS5                         0x05
 178 #define DESC90_RATEMCS6                         0x06
 179 #define DESC90_RATEMCS7                         0x07
 180 #define DESC90_RATEMCS8                         0x08
 181 #define DESC90_RATEMCS9                         0x09
 182 #define DESC90_RATEMCS10                        0x0a
 183 #define DESC90_RATEMCS11                        0x0b
 184 #define DESC90_RATEMCS12                        0x0c
 185 #define DESC90_RATEMCS13                        0x0d
 186 #define DESC90_RATEMCS14                        0x0e
 187 #define DESC90_RATEMCS15                        0x0f
 188 #define DESC90_RATEMCS32                        0x20
 189
 190 #define RTL819X_DEFAULT_RF_TYPE RF_1T2R
 191 #define EEPROM_Default_LegacyHTTxPowerDiff      0x4
 192 #define IEEE80211_WATCH_DOG_TIME    2000
 193
 194 /* For rtl819x */
 195 typedef struct _tx_desc_819x_pci {
 196         //DWORD 0
 197         u16     PktSize;
 198         u8      Offset;
 199         u8      Reserved1:3;
 200         u8      CmdInit:1;
 201         u8      LastSeg:1;
 202         u8      FirstSeg:1;
 203         u8      LINIP:1;
 204         u8      OWN:1;
 205
 206         //DWORD 1
 207         u8      TxFWInfoSize;
 208         u8      RATid:3;
 209         u8      DISFB:1;
 210         u8      USERATE:1;
 211         u8      MOREFRAG:1;
 212         u8      NoEnc:1;
 213         u8      PIFS:1;
 214         u8      QueueSelect:5;
 215         u8      NoACM:1;
 216         u8      Resv:2;
 217         u8      SecCAMID:5;
 218         u8      SecDescAssign:1;
 219         u8      SecType:2;
 220
 221         //DWORD 2
 222         u16     TxBufferSize;
 223         u8      PktId:7;
 224         u8      Resv1:1;
 225         u8      Reserved2;
 226
 227         //DWORD 3
 228         u32     TxBuffAddr;
 229
 230         //DWORD 4
 231         u32     NextDescAddress;
 232
 233         //DWORD 5,6,7
 234         u32     Reserved5;
 235         u32     Reserved6;
 236         u32     Reserved7;
 237 }tx_desc_819x_pci, *ptx_desc_819x_pci;
 238
 239
 240 typedef struct _tx_desc_cmd_819x_pci {
 241         //DWORD 0
 242         u16     PktSize;
 243         u8      Reserved1;
 244         u8      CmdType:3;
 245         u8      CmdInit:1;
 246         u8      LastSeg:1;
 247         u8      FirstSeg:1;
 248         u8      LINIP:1;
 249         u8      OWN:1;
 250
 251         //DOWRD 1
 252         u16     ElementReport;
 253         u16     Reserved2;
 254
 255         //DOWRD 2
 256         u16     TxBufferSize;
 257         u16     Reserved3;
 258
 259        //DWORD 3,4,5
 260         u32     TxBufferAddr;
 261         u32     NextDescAddress;
 262         u32     Reserved4;
 263         u32     Reserved5;
 264         u32     Reserved6;
 265 }tx_desc_cmd_819x_pci, *ptx_desc_cmd_819x_pci;
 266
 267
 268 typedef struct _tx_fwinfo_819x_pci {
 269         //DOWRD 0
 270         u8              TxRate:7;
 271         u8              CtsEnable:1;
 272         u8              RtsRate:7;
 273         u8              RtsEnable:1;
 274         u8              TxHT:1;
 275         u8              Short:1;                //Short PLCP for CCK, or short GI for 11n MCS
 276         u8              TxBandwidth:1;          // This is used for HT MCS rate only.
 277         u8              TxSubCarrier:2;         // This is used for legacy OFDM rate only.
 278         u8              STBC:2;
 279         u8              AllowAggregation:1;
 280         u8              RtsHT:1;                //Interpre RtsRate field as high throughput data rate
 281         u8              RtsShort:1;             //Short PLCP for CCK, or short GI for 11n MCS
 282         u8              RtsBandwidth:1;         // This is used for HT MCS rate only.
 283         u8              RtsSubcarrier:2;        // This is used for legacy OFDM rate only.
 284         u8              RtsSTBC:2;
 285         u8              EnableCPUDur:1;         //Enable firmware to recalculate and assign packet duration
 286
 287         //DWORD 1
 288         u8              RxMF:2;
 289         u8              RxAMD:3;
 290         u8              Reserved1:3;
 291         u8              Reserved2;
 292         u8              Reserved3;
 293         u8              Reserved4;
 294
 295         //u32                Reserved;
 296 }tx_fwinfo_819x_pci, *ptx_fwinfo_819x_pci;
 297
 298 typedef struct _rx_desc_819x_pci{
 299         //DOWRD 0
 300         u16                     Length:14;
 301         u16                     CRC32:1;
 302         u16                     ICV:1;
 303         u8                      RxDrvInfoSize;
 304         u8                      Shift:2;
 305         u8                      PHYStatus:1;
 306         u8                      SWDec:1;
 307         u8                                      LastSeg:1;
 308         u8                                      FirstSeg:1;
 309         u8                                      EOR:1;
 310         u8                                      OWN:1;
 311
 312         //DWORD 1
 313         u32                     Reserved2;
 314
 315         //DWORD 2
 316         u32                     Reserved3;
 317
 318         //DWORD 3
 319         u32     BufferAddress;
 320
 321 }rx_desc_819x_pci, *prx_desc_819x_pci;
 322
 323 typedef struct _rx_fwinfo_819x_pci{
 324         //DWORD 0
 325         u16                     Reserved1:12;
 326         u16                     PartAggr:1;
 327         u16                     FirstAGGR:1;
 328         u16                     Reserved2:2;
 329
 330         u8                      RxRate:7;
 331         u8                      RxHT:1;
 332
 333         u8                      BW:1;
 334         u8                      SPLCP:1;
 335         u8                      Reserved3:2;
 336         u8                      PAM:1;
 337         u8                      Mcast:1;
 338         u8                      Bcast:1;
 339         u8                      Reserved4:1;
 340
 341         //DWORD 1
 342         u32                     TSFL;
 343
 344 }rx_fwinfo_819x_pci, *prx_fwinfo_819x_pci;
 345
 346 #define MAX_DEV_ADDR_SIZE               8  /* support till 64 bit bus width OS */
 347 #define MAX_FIRMWARE_INFORMATION_SIZE   32 /*2006/04/30 by Emily forRTL8190*/
 348 #define MAX_802_11_HEADER_LENGTH        (40 + MAX_FIRMWARE_INFORMATION_SIZE)
 349 #define ENCRYPTION_MAX_OVERHEAD         128
 350 #define MAX_FRAGMENT_COUNT              8
 351 #define MAX_TRANSMIT_BUFFER_SIZE        (1600+(MAX_802_11_HEADER_LENGTH+ENCRYPTION_MAX_OVERHEAD)*MAX_FRAGMENT_COUNT)
 352
 353 #define scrclng                                 4               // octets for crc32 (FCS, ICV)
 354 /* 8190 Loopback Mode definition */
 355 typedef enum _rtl819x_loopback{
 356         RTL819X_NO_LOOPBACK = 0,
 357         RTL819X_MAC_LOOPBACK = 1,
 358         RTL819X_DMA_LOOPBACK = 2,
 359         RTL819X_CCK_LOOPBACK = 3,
 360 }rtl819x_loopback_e;
 361
 362 /* due to rtl8192 firmware */
 363 typedef enum _desc_packet_type_e{
 364         DESC_PACKET_TYPE_INIT = 0,
 365         DESC_PACKET_TYPE_NORMAL = 1,
 366 }desc_packet_type_e;
 367
 368 typedef enum _firmware_status{
 369         FW_STATUS_0_INIT = 0,
 370         FW_STATUS_1_MOVE_BOOT_CODE = 1,
 371         FW_STATUS_2_MOVE_MAIN_CODE = 2,
 372         FW_STATUS_3_TURNON_CPU = 3,
 373         FW_STATUS_4_MOVE_DATA_CODE = 4,
 374         FW_STATUS_5_READY = 5,
 375 }firmware_status_e;
 376
 377 typedef struct _rt_firmware{
 378         firmware_status_e firmware_status;
 379         u16               cmdpacket_frag_thresold;
 380 #define RTL8190_MAX_FIRMWARE_CODE_SIZE  64000   //64k
 381 #define MAX_FW_INIT_STEP                3
 382         u8                firmware_buf[MAX_FW_INIT_STEP][RTL8190_MAX_FIRMWARE_CODE_SIZE];
 383         u16               firmware_buf_size[MAX_FW_INIT_STEP];
 384 }rt_firmware, *prt_firmware;
 385
 386 #define MAX_RECEIVE_BUFFER_SIZE 9100    // Add this to 9100 bytes to receive A-MSDU from RT-AP
 387
 388 /* Firmware Queue Layout */
 389 #define NUM_OF_FIRMWARE_QUEUE           10
 390 #define NUM_OF_PAGES_IN_FW              0x100
 391 #define NUM_OF_PAGE_IN_FW_QUEUE_BE      0x0aa
 392 #define NUM_OF_PAGE_IN_FW_QUEUE_BK      0x007
 393 #define NUM_OF_PAGE_IN_FW_QUEUE_VI      0x024
 394 #define NUM_OF_PAGE_IN_FW_QUEUE_VO      0x007
 395 #define NUM_OF_PAGE_IN_FW_QUEUE_HCCA    0
 396 #define NUM_OF_PAGE_IN_FW_QUEUE_CMD     0x2
 397 #define NUM_OF_PAGE_IN_FW_QUEUE_MGNT    0x10
 398 #define NUM_OF_PAGE_IN_FW_QUEUE_HIGH    0
 399 #define NUM_OF_PAGE_IN_FW_QUEUE_BCN     0x4
 400 #define NUM_OF_PAGE_IN_FW_QUEUE_PUB     0xd
 401 #define APPLIED_RESERVED_QUEUE_IN_FW    0x80000000
 402 #define RSVD_FW_QUEUE_PAGE_BK_SHIFT     0x00
 403 #define RSVD_FW_QUEUE_PAGE_BE_SHIFT     0x08
 404 #define RSVD_FW_QUEUE_PAGE_VI_SHIFT     0x10
 405 #define RSVD_FW_QUEUE_PAGE_VO_SHIFT     0x18
 406 #define RSVD_FW_QUEUE_PAGE_MGNT_SHIFT   0x10
 407 #define RSVD_FW_QUEUE_PAGE_CMD_SHIFT    0x08
 408 #define RSVD_FW_QUEUE_PAGE_BCN_SHIFT    0x00
 409 #define RSVD_FW_QUEUE_PAGE_PUB_SHIFT    0x08
 410
 411 #define DCAM                    0xAC                    // Debug CAM Interface
 412 #define AESMSK_FC               0xB2    // AES Mask register for frame control (0xB2~0xB3). Added by Annie, 2006-03-06.
 413
 414
 415 #define CAM_CONTENT_COUNT       8
 416 #define CFG_VALID               BIT15
 417 #define EPROM_93c46 0
 418 #define EPROM_93c56 1
 419
 420 #define DEFAULT_FRAG_THRESHOLD 2342U
 421 #define MIN_FRAG_THRESHOLD     256U
 422 #define DEFAULT_BEACONINTERVAL 0x64U
 423
 424 #define DEFAULT_RETRY_RTS 7
 425 #define DEFAULT_RETRY_DATA 7
 426
 427 #define         PHY_RSSI_SLID_WIN_MAX                           100
 428
 429
 430 typedef enum _WIRELESS_MODE {
 431         WIRELESS_MODE_UNKNOWN = 0x00,
 432         WIRELESS_MODE_A = 0x01,
 433         WIRELESS_MODE_B = 0x02,
 434         WIRELESS_MODE_G = 0x04,
 435         WIRELESS_MODE_AUTO = 0x08,
 436         WIRELESS_MODE_N_24G = 0x10,
 437         WIRELESS_MODE_N_5G = 0x20
 438 } WIRELESS_MODE;
 439
 440 #define RTL_IOCTL_WPA_SUPPLICANT                SIOCIWFIRSTPRIV+30
 441
 442 typedef struct buffer
 443 {
 444         struct buffer *next;
 445         u32 *buf;
 446         dma_addr_t dma;
 447
 448 } buffer;
 449
 450 typedef struct _rt_9x_tx_rate_history {
 451         u32             cck[4];
 452         u32             ofdm[8];
 453         // HT_MCS[0][]: BW=0 SG=0
 454         // HT_MCS[1][]: BW=1 SG=0
 455         // HT_MCS[2][]: BW=0 SG=1
 456         // HT_MCS[3][]: BW=1 SG=1
 457         u32             ht_mcs[4][16];
 458 }rt_tx_rahis_t, *prt_tx_rahis_t;
 459
 460 typedef struct _RT_SMOOTH_DATA_4RF {
 461         char    elements[4][100];//array to store values
 462         u32     index;                  //index to current array to store
 463         u32     TotalNum;               //num of valid elements
 464         u32     TotalVal[4];            //sum of valid elements
 465 }RT_SMOOTH_DATA_4RF, *PRT_SMOOTH_DATA_4RF;
 466
 467 typedef enum _tag_TxCmd_Config_Index{
 468         TXCMD_TXRA_HISTORY_CTRL                         = 0xFF900000,
 469         TXCMD_RESET_TX_PKT_BUFF                         = 0xFF900001,
 470         TXCMD_RESET_RX_PKT_BUFF                         = 0xFF900002,
 471         TXCMD_SET_TX_DURATION                           = 0xFF900003,
 472         TXCMD_SET_RX_RSSI                                               = 0xFF900004,
 473         TXCMD_SET_TX_PWR_TRACKING                       = 0xFF900005,
 474         TXCMD_XXXX_CTRL,
 475 }DCMD_TXCMD_OP;
 476
 477 typedef struct Stats
 478 {
 479         unsigned long rxrdu;
 480         unsigned long rxok;
 481         unsigned long received_rate_histogram[4][32];   //0: Total, 1:OK, 2:CRC, 3:ICV
 482         unsigned long rxoverflow;
 483         unsigned long rxint;
 484         unsigned long txoverflow;
 485         unsigned long txbeokint;
 486         unsigned long txbkokint;
 487         unsigned long txviokint;
 488         unsigned long txvookint;
 489         unsigned long txbeaconokint;
 490         unsigned long txbeaconerr;
 491         unsigned long txmanageokint;
 492         unsigned long txcmdpktokint;
 493         unsigned long txfeedback;
 494         unsigned long txfeedbackok;
 495         unsigned long txoktotal;
 496         unsigned long txbytesunicast;
 497         unsigned long rxbytesunicast;
 498
 499         unsigned long slide_signal_strength[100];
 500         unsigned long slide_evm[100];
 501         unsigned long   slide_rssi_total;       // For recording sliding window's RSSI value
 502         unsigned long slide_evm_total;  // For recording sliding window's EVM value
 503         long signal_strength; // Transformed, in dbm. Beautified signal strength for UI, not correct.
 504         u8 rx_rssi_percentage[4];
 505         u8 rx_evm_percentage[2];
 506         u32 Slide_Beacon_pwdb[100];
 507         u32 Slide_Beacon_Total;
 508         RT_SMOOTH_DATA_4RF              cck_adc_pwdb;
 509 } Stats;
 510
 511
 512 // Bandwidth Offset
 513 #define HAL_PRIME_CHNL_OFFSET_DONT_CARE         0
 514 #define HAL_PRIME_CHNL_OFFSET_LOWER                     1
 515 #define HAL_PRIME_CHNL_OFFSET_UPPER                     2
 516
 517 typedef struct  ChnlAccessSetting {
 518         u16 SIFS_Timer;
 519         u16 DIFS_Timer;
 520         u16 SlotTimeTimer;
 521         u16 EIFS_Timer;
 522         u16 CWminIndex;
 523         u16 CWmaxIndex;
 524 }*PCHANNEL_ACCESS_SETTING,CHANNEL_ACCESS_SETTING;
 525
 526 typedef struct _BB_REGISTER_DEFINITION{
 527         u32 rfintfs;                    // set software control: //             0x870~0x877[8 bytes]
 528         u32 rfintfi;                    // readback data: //            0x8e0~0x8e7[8 bytes]
 529         u32 rfintfo;                    // output data: //              0x860~0x86f [16 bytes]
 530         u32 rfintfe;                    // output enable: //            0x860~0x86f [16 bytes]
 531         u32 rf3wireOffset;              // LSSI data: //                0x840~0x84f [16 bytes]
 532         u32 rfLSSI_Select;              // BB Band Select: //           0x878~0x87f [8 bytes]
 533         u32 rfTxGainStage;              // Tx gain stage: //            0x80c~0x80f [4 bytes]
 534         u32 rfHSSIPara1;                // wire parameter control1 : //         0x820~0x823,0x828~0x82b, 0x830~0x833, 0x838~0x83b [16 bytes]
 535         u32 rfHSSIPara2;                // wire parameter control2 : //         0x824~0x827,0x82c~0x82f, 0x834~0x837, 0x83c~0x83f [16 bytes]
 536         u32 rfSwitchControl;    //Tx Rx antenna control : //            0x858~0x85f [16 bytes]
 537         u32 rfAGCControl1;      //AGC parameter control1 : //           0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63, 0xc68~0xc6b [16 bytes]
 538         u32 rfAGCControl2;      //AGC parameter control2 : //           0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67, 0xc6c~0xc6f [16 bytes]
 539         u32 rfRxIQImbalance;    //OFDM Rx IQ imbalance matrix : //              0xc14~0xc17,0xc1c~0xc1f, 0xc24~0xc27, 0xc2c~0xc2f [16 bytes]
 540         u32 rfRxAFE;                    //Rx IQ DC ofset and Rx digital filter, Rx DC notch filter : //         0xc10~0xc13,0xc18~0xc1b, 0xc20~0xc23, 0xc28~0xc2b [16 bytes]
 541         u32 rfTxIQImbalance;    //OFDM Tx IQ imbalance matrix //                0xc80~0xc83,0xc88~0xc8b, 0xc90~0xc93, 0xc98~0xc9b [16 bytes]
 542         u32 rfTxAFE;                    //Tx IQ DC Offset and Tx DFIR type //           0xc84~0xc87,0xc8c~0xc8f, 0xc94~0xc97, 0xc9c~0xc9f [16 bytes]
 543         u32 rfLSSIReadBack;     //LSSI RF readback data //              0x8a0~0x8af [16 bytes]
 544 }BB_REGISTER_DEFINITION_T, *PBB_REGISTER_DEFINITION_T;
 545
 546 typedef struct _rate_adaptive
 547 {
 548         u8                              rate_adaptive_disabled;
 549         u8                              ratr_state;
 550         u16                             reserve;
 551
 552         u32                             high_rssi_thresh_for_ra;
 553         u32                             high2low_rssi_thresh_for_ra;
 554         u8                              low2high_rssi_thresh_for_ra40M;
 555         u32                             low_rssi_thresh_for_ra40M;
 556         u8                              low2high_rssi_thresh_for_ra20M;
 557         u32                             low_rssi_thresh_for_ra20M;
 558         u32                             upper_rssi_threshold_ratr;
 559         u32                             middle_rssi_threshold_ratr;
 560         u32                             low_rssi_threshold_ratr;
 561         u32                             low_rssi_threshold_ratr_40M;
 562         u32                             low_rssi_threshold_ratr_20M;
 563         u8                              ping_rssi_enable;       //cosa add for test
 564         u32                             ping_rssi_ratr; //cosa add for test
 565         u32                             ping_rssi_thresh_for_ra;//cosa add for test
 566         u32                             last_ratr;
 567
 568 } rate_adaptive, *prate_adaptive;
 569 #define TxBBGainTableLength 37
 570 #define CCKTxBBGainTableLength 23
 571 typedef struct _txbbgain_struct
 572 {
 573         long    txbb_iq_amplifygain;
 574         u32     txbbgain_value;
 575 } txbbgain_struct, *ptxbbgain_struct;
 576
 577 typedef struct _ccktxbbgain_struct
 578 {
 579         //The Value is from a22 to a29 one Byte one time is much Safer
 580         u8      ccktxbb_valuearray[8];
 581 } ccktxbbgain_struct,*pccktxbbgain_struct;
 582
 583
 584 typedef struct _init_gain
 585 {
 586         u8                              xaagccore1;
 587         u8                              xbagccore1;
 588         u8                              xcagccore1;
 589         u8                              xdagccore1;
 590         u8                              cca;
 591
 592 } init_gain, *pinit_gain;
 593
 594 /* 2007/11/02 MH Define RF mode temporarily for test. */
 595 typedef enum tag_Rf_Operatetion_State
 596 {
 597     RF_STEP_INIT = 0,
 598     RF_STEP_NORMAL,
 599     RF_STEP_MAX
 600 }RF_STEP_E;
 601
 602 typedef enum _RT_STATUS{
 603         RT_STATUS_SUCCESS,
 604         RT_STATUS_FAILURE,
 605         RT_STATUS_PENDING,
 606         RT_STATUS_RESOURCE
 607 }RT_STATUS,*PRT_STATUS;
 608
 609 typedef enum _RT_CUSTOMER_ID
 610 {
 611         RT_CID_DEFAULT = 0,
 612         RT_CID_8187_ALPHA0 = 1,
 613         RT_CID_8187_SERCOMM_PS = 2,
 614         RT_CID_8187_HW_LED = 3,
 615         RT_CID_8187_NETGEAR = 4,
 616         RT_CID_WHQL = 5,
 617         RT_CID_819x_CAMEO  = 6,
 618         RT_CID_819x_RUNTOP = 7,
 619         RT_CID_819x_Senao = 8,
 620         RT_CID_TOSHIBA = 9,     // Merge by Jacken, 2008/01/31.
 621         RT_CID_819x_Netcore = 10,
 622         RT_CID_Nettronix = 11,
 623         RT_CID_DLINK = 12,
 624         RT_CID_PRONET = 13,
 625         RT_CID_COREGA = 14,
 626 }RT_CUSTOMER_ID, *PRT_CUSTOMER_ID;
 627
 628 /* LED customization. */
 629
 630 typedef enum _LED_STRATEGY_8190{
 631         SW_LED_MODE0, // SW control 1 LED via GPIO0. It is default option.
 632         SW_LED_MODE1, // SW control for PCI Express
 633         SW_LED_MODE2, // SW control for Cameo.
 634         SW_LED_MODE3, // SW contorl for RunTop.
 635         SW_LED_MODE4, // SW control for Netcore
 636         SW_LED_MODE5, //added by vivi, for led new mode, DLINK
 637         SW_LED_MODE6, //added by vivi, for led new mode, PRONET
 638         HW_LED, // HW control 2 LEDs, LED0 and LED1 (there are 4 different control modes)
 639 }LED_STRATEGY_8190, *PLED_STRATEGY_8190;
 640
 641 #define CHANNEL_PLAN_LEN                                10
 642
 643 #define sCrcLng                 4
 644
 645 typedef struct _TX_FWINFO_STRUCUTRE{
 646         //DOWRD 0
 647         u8                      TxRate:7;
 648         u8                      CtsEnable:1;
 649         u8                      RtsRate:7;
 650         u8                      RtsEnable:1;
 651         u8                      TxHT:1;
 652         u8                      Short:1;
 653         u8                      TxBandwidth:1;
 654         u8                      TxSubCarrier:2;
 655         u8                      STBC:2;
 656         u8                      AllowAggregation:1;
 657         u8                      RtsHT:1;
 658         u8                      RtsShort:1;
 659         u8                      RtsBandwidth:1;
 660         u8                      RtsSubcarrier:2;
 661         u8                      RtsSTBC:2;
 662         u8                      EnableCPUDur:1;
 663
 664         //DWORD 1
 665         u32                     RxMF:2;
 666         u32                     RxAMD:3;
 667         u32                     Reserved1:3;
 668         u32                     TxAGCOffset:4;
 669         u32                     TxAGCSign:1;
 670         u32                     Tx_INFO_RSVD:6;
 671         u32                     PacketID:13;
 672 }TX_FWINFO_T;
 673
 674
 675 typedef struct _TX_FWINFO_8190PCI{
 676         //DOWRD 0
 677         u8                      TxRate:7;
 678         u8                      CtsEnable:1;
 679         u8                      RtsRate:7;
 680         u8                      RtsEnable:1;
 681         u8                      TxHT:1;
 682         u8                      Short:1;                                                //Short PLCP for CCK, or short GI for 11n MCS
 683         u8                      TxBandwidth:1;                          // This is used for HT MCS rate only.
 684         u8                      TxSubCarrier:2;                         // This is used for legacy OFDM rate only.
 685         u8                      STBC:2;
 686         u8                      AllowAggregation:1;
 687         u8                      RtsHT:1;                                                //Interpre RtsRate field as high throughput data rate
 688         u8                      RtsShort:1;                             //Short PLCP for CCK, or short GI for 11n MCS
 689         u8                      RtsBandwidth:1;                         // This is used for HT MCS rate only.
 690         u8                      RtsSubcarrier:2;                                // This is used for legacy OFDM rate only.
 691         u8                      RtsSTBC:2;
 692         u8                      EnableCPUDur:1;                         //Enable firmware to recalculate and assign packet duration
 693
 694         //DWORD 1
 695         u32                     RxMF:2;
 696         u32                     RxAMD:3;
 697         u32                     TxPerPktInfoFeedback:1;         // 1: indicate that the transimission info of this packet should be gathered by Firmware and retured by Rx Cmd.
 698         u32                     Reserved1:2;
 699         u32                     TxAGCOffset:4;          // Only 90 support
 700         u32                     TxAGCSign:1;            // Only 90 support
 701         u32                     RAW_TXD:1;                      // MAC will send data in txpktbuffer without any processing,such as CRC check
 702         u32                     Retry_Limit:4;          // CCX Support relative retry limit FW page only support 4 bits now.
 703         u32                     Reserved2:1;
 704         u32                     PacketID:13;
 705
 706         // DW 2
 707
 708 }TX_FWINFO_8190PCI, *PTX_FWINFO_8190PCI;
 709
 710 typedef struct _phy_ofdm_rx_status_report_819xpci
 711 {
 712         u8      trsw_gain_X[4];
 713         u8      pwdb_all;
 714         u8      cfosho_X[4];
 715         u8      cfotail_X[4];
 716         u8      rxevm_X[2];
 717         u8      rxsnr_X[4];
 718         u8      pdsnr_X[2];
 719         u8      csi_current_X[2];
 720         u8      csi_target_X[2];
 721         u8      sigevm;
 722         u8      max_ex_pwr;
 723         u8      sgi_en;
 724         u8      rxsc_sgien_exflg;
 725 }phy_sts_ofdm_819xpci_t;
 726
 727 typedef struct _phy_cck_rx_status_report_819xpci
 728 {
 729         /* For CCK rate descriptor. This is a unsigned 8:1 variable. LSB bit presend
 730            0.5. And MSB 7 bts presend a signed value. Range from -64~+63.5. */
 731         u8      adc_pwdb_X[4];
 732         u8      sq_rpt;
 733         u8      cck_agc_rpt;
 734 }phy_sts_cck_819xpci_t;
 735
 736 typedef struct _phy_ofdm_rx_status_rxsc_sgien_exintfflag{
 737         u8                      reserved:4;
 738         u8                      rxsc:2;
 739         u8                      sgi_en:1;
 740         u8                      ex_intf_flag:1;
 741 }phy_ofdm_rx_status_rxsc_sgien_exintfflag;
 742
 743 typedef enum _RT_OP_MODE{
 744         RT_OP_MODE_AP,
 745         RT_OP_MODE_INFRASTRUCTURE,
 746         RT_OP_MODE_IBSS,
 747         RT_OP_MODE_NO_LINK,
 748 }RT_OP_MODE, *PRT_OP_MODE;
 749
 750
 751 /* 2007/11/02 MH Define RF mode temporarily for test. */
 752 typedef enum tag_Rf_OpType
 753 {
 754     RF_OP_By_SW_3wire = 0,
 755     RF_OP_By_FW,
 756     RF_OP_MAX
 757 }RF_OpType_E;
 758
 759 typedef enum _RESET_TYPE {
 760         RESET_TYPE_NORESET = 0x00,
 761         RESET_TYPE_NORMAL = 0x01,
 762         RESET_TYPE_SILENT = 0x02
 763 } RESET_TYPE;
 764
 765 typedef struct _tx_ring{
 766         u32 * desc;
 767         u8 nStuckCount;
 768         struct _tx_ring * next;
 769 }__attribute__ ((packed)) tx_ring, * ptx_ring;
 770
 771 struct rtl8192_tx_ring {
 772     tx_desc_819x_pci *desc;
 773     dma_addr_t dma;
 774     unsigned int idx;
 775     unsigned int entries;
 776     struct sk_buff_head queue;
 777 };
 778
 779 #define NIC_SEND_HANG_THRESHOLD_NORMAL          4
 780 #define NIC_SEND_HANG_THRESHOLD_POWERSAVE       8
 781 #define MAX_TX_QUEUE                            9       // BK, BE, VI, VO, HCCA, MANAGEMENT, COMMAND, HIGH, BEACON.
 782
 783 #define MAX_RX_COUNT                            64
 784 #define MAX_TX_QUEUE_COUNT                      9
 785
 786 typedef struct r8192_priv
 787 {
 788         struct pci_dev *pdev;
 789         /* maintain info from eeprom */
 790         short epromtype;
 791         u16 eeprom_vid;
 792         u16 eeprom_did;
 793         u8  eeprom_CustomerID;
 794         u16  eeprom_ChannelPlan;
 795         RT_CUSTOMER_ID CustomerID;
 796         LED_STRATEGY_8190       LedStrategy;
 797         u8      IC_Cut;
 798         int irq;
 799         short irq_enabled;
 800         struct ieee80211_device *ieee80211;
 801 #ifdef ENABLE_LPS
 802         bool ps_force;
 803         bool force_lps;
 804         bool bdisable_nic;
 805 #endif
 806         bool being_init_adapter;
 807         u8 Rf_Mode;
 808         u8 card_8192_version; /* if TCR reports card V B/C this discriminates */
 809         spinlock_t irq_th_lock;
 810         spinlock_t tx_lock;
 811         spinlock_t rf_ps_lock;
 812         struct mutex mutex;
 813         spinlock_t ps_lock;
 814
 815         u32 irq_mask;
 816         short chan;
 817         short sens;
 818         /* RX stuff */
 819         rx_desc_819x_pci *rx_ring;
 820         dma_addr_t rx_ring_dma;
 821         unsigned int rx_idx;
 822         struct sk_buff *rx_buf[MAX_RX_COUNT];
 823         int rxringcount;
 824         u16 rxbuffersize;
 825
 826         struct sk_buff *rx_skb;
 827         u32 *rxring;
 828         u32 *rxringtail;
 829         dma_addr_t rxringdma;
 830         struct buffer *rxbuffer;
 831         struct buffer *rxbufferhead;
 832         short rx_skb_complete;
 833         /* TX stuff */
 834         struct rtl8192_tx_ring tx_ring[MAX_TX_QUEUE_COUNT];
 835         int txringcount;
 836
 837         struct tasklet_struct irq_rx_tasklet;
 838         struct tasklet_struct irq_tx_tasklet;
 839         struct tasklet_struct irq_prepare_beacon_tasklet;
 840
 841         short up;
 842         short crcmon; //if 1 allow bad crc frame reception in monitor mode
 843         struct semaphore wx_sem;
 844         struct semaphore rf_sem; //used to lock rf write operation added by wb, modified by david
 845         u8 rf_type; /* 0 means 1T2R, 1 means 2T4R */
 846
 847         short (*rf_set_sens)(struct net_device *dev,short sens);
 848         u8 (*rf_set_chan)(struct net_device *dev,u8 ch);
 849         void (*rf_close)(struct net_device *dev);
 850         void (*rf_init)(struct net_device *dev);
 851         short promisc;
 852         /* stats */
 853         struct Stats stats;
 854         struct iw_statistics wstats;
 855         struct proc_dir_entry *dir_dev;
 856         struct ieee80211_rx_stats previous_stats;
 857
 858         /* RX stuff */
 859         struct sk_buff_head skb_queue;
 860         struct work_struct qos_activate;
 861
 862         //2 Tx Related variables
 863         u16     ShortRetryLimit;
 864         u16     LongRetryLimit;
 865
 866         u32     LastRxDescTSFHigh;
 867         u32     LastRxDescTSFLow;
 868
 869
 870         //2 Rx Related variables
 871         u32     ReceiveConfig;
 872
 873         u8 retry_data;
 874         u8 retry_rts;
 875
 876         struct work_struct reset_wq;
 877         u8      rx_chk_cnt;
 878
 879 //for rtl819xPci
 880         // Data Rate Config. Added by Annie, 2006-04-13.
 881         u16     basic_rate;
 882         u8      short_preamble;
 883         u8      slot_time;
 884         u16 SifsTime;
 885 /* WirelessMode*/
 886         u8 RegWirelessMode;
 887 /*Firmware*/
 888         prt_firmware            pFirmware;
 889         rtl819x_loopback_e      LoopbackMode;
 890         bool AutoloadFailFlag;
 891         u16 EEPROMAntPwDiff;            // Antenna gain offset from B/C/D to A
 892         u8 EEPROMThermalMeter;
 893         u8 EEPROMCrystalCap;
 894         u8 EEPROMTxPowerLevelCCK[14];// CCK channel 1~14
 895         // The following definition is for eeprom 93c56
 896         u8 EEPROMRfACCKChnl1TxPwLevel[3];       //RF-A CCK Tx Power Level at channel 7
 897         u8 EEPROMRfAOfdmChnlTxPwLevel[3];//RF-A CCK Tx Power Level at [0],[1],[2] = channel 1,7,13
 898         u8 EEPROMRfCCCKChnl1TxPwLevel[3];       //RF-C CCK Tx Power Level at channel 7
 899         u8 EEPROMRfCOfdmChnlTxPwLevel[3];//RF-C CCK Tx Power Level at [0],[1],[2] = channel 1,7,13
 900         u8 EEPROMTxPowerLevelOFDM24G[14]; // OFDM 2.4G channel 1~14
 901         u8 EEPROMLegacyHTTxPowerDiff;   // Legacy to HT rate power diff
 902         bool bTXPowerDataReadFromEEPORM;
 903 /*channel plan*/
 904         u16 RegChannelPlan; // Channel Plan specifed by user, 15: following setting of EEPROM, 0-14: default channel plan index specified by user.
 905         u16 ChannelPlan;
 906 /*PS related*/
 907         // Rf off action for power save
 908         u8      bHwRfOffAction; //0:No action, 1:By GPIO, 2:By Disable
 909 /*PHY related*/
 910         BB_REGISTER_DEFINITION_T        PHYRegDef[4];   //Radio A/B/C/D
 911         // Read/write are allow for following hardware information variables
 912         u32     MCSTxPowerLevelOriginalOffset[6];
 913         u32     CCKTxPowerLevelOriginalOffset;
 914         u8      TxPowerLevelCCK[14];                    // CCK channel 1~14
 915         u8      TxPowerLevelCCK_A[14];                  // RF-A, CCK channel 1~14
 916         u8      TxPowerLevelCCK_C[14];
 917         u8      TxPowerLevelOFDM24G[14];                // OFDM 2.4G channel 1~14
 918         u8      TxPowerLevelOFDM5G[14];                 // OFDM 5G
 919         u8      TxPowerLevelOFDM24G_A[14];      // RF-A, OFDM 2.4G channel 1~14
 920         u8      TxPowerLevelOFDM24G_C[14];      // RF-C, OFDM 2.4G channel 1~14
 921         u8      LegacyHTTxPowerDiff;                    // Legacy to HT rate power diff
 922         u8      TxPowerDiff;
 923         char    RF_C_TxPwDiff;                                  // Antenna gain offset, rf-c to rf-a
 924         u8      AntennaTxPwDiff[3];                             // Antenna gain offset, index 0 for B, 1 for C, and 2 for D
 925         u8      CrystalCap;                                             // CrystalCap.
 926         u8      ThermalMeter[2];                                // ThermalMeter, index 0 for RFIC0, and 1 for RFIC1
 927         //05/27/2008 cck power enlarge
 928         u8      CckPwEnl;
 929         u16     TSSI_13dBm;
 930         u32     Pwr_Track;
 931         u8                              CCKPresentAttentuation_20Mdefault;
 932         u8                              CCKPresentAttentuation_40Mdefault;
 933         char                            CCKPresentAttentuation_difference;
 934         char                            CCKPresentAttentuation;
 935         // Use to calculate PWBD.
 936         u8      bCckHighPower;
 937         long    undecorated_smoothed_pwdb;
 938         long    undecorated_smoothed_cck_adc_pwdb[4];
 939         //for set channel
 940         u8      SwChnlInProgress;
 941         u8      SwChnlStage;
 942         u8      SwChnlStep;
 943         u8      SetBWModeInProgress;
 944         HT_CHANNEL_WIDTH                CurrentChannelBW;
 945
 946         // 8190 40MHz mode
 947         //
 948         u8      nCur40MhzPrimeSC;       // Control channel sub-carrier
 949         // Joseph test for shorten RF configuration time.
 950         // We save RF reg0 in this variable to reduce RF reading.
 951         //
 952         u32                                     RfReg0Value[4];
 953         u8                                      NumTotalRFPath;
 954         bool                            brfpath_rxenable[4];
 955 //+by amy 080507
 956         struct timer_list watch_dog_timer;
 957         u8 watchdog_last_time;
 958         u8 watchdog_check_reset_cnt;
 959
 960 //+by amy 080515 for dynamic mechenism
 961         //Add by amy Tx Power Control for Near/Far Range 2008/05/15
 962         bool    bdynamic_txpower;  //bDynamicTxPower
 963         bool    bDynamicTxHighPower;  // Tx high power state
 964         bool    bDynamicTxLowPower;  // Tx low power state
 965         bool    bLastDTPFlag_High;
 966         bool    bLastDTPFlag_Low;
 967
 968         /* OFDM RSSI. For high power or not */
 969         u8      phy_check_reg824;
 970         u32     phy_reg824_bit9;
 971
 972         //Add by amy for Rate Adaptive
 973         rate_adaptive rate_adaptive;
 974         //Add by amy for TX power tracking
 975         //2008/05/15  Mars OPEN/CLOSE TX POWER TRACKING
 976         const txbbgain_struct * txbbgain_table;
 977         u8                         txpower_count;//For 6 sec do tracking again
 978         bool                       btxpower_trackingInit;
 979         u8                         OFDM_index;
 980         u8                         CCK_index;
 981         u8                         Record_CCK_20Mindex;
 982         u8                         Record_CCK_40Mindex;
 983         //2007/09/10 Mars Add CCK TX Power Tracking
 984         const ccktxbbgain_struct *cck_txbbgain_table;
 985         const ccktxbbgain_struct *cck_txbbgain_ch14_table;
 986         u8 rfa_txpowertrackingindex;
 987         u8 rfa_txpowertrackingindex_real;
 988         u8 rfa_txpowertracking_default;
 989         u8 rfc_txpowertrackingindex;
 990         u8 rfc_txpowertrackingindex_real;
 991         u8 rfc_txpowertracking_default;
 992         bool btxpower_tracking;
 993         bool bcck_in_ch14;
 994
 995         //For Backup Initial Gain
 996         init_gain initgain_backup;
 997         u8              DefaultInitialGain[4];
 998         // For EDCA Turbo mode, Added by amy 080515.
 999         bool            bis_any_nonbepkts;
1000         bool            bcurrent_turbo_EDCA;
1001
1002         bool            bis_cur_rdlstate;
1003         struct timer_list fsync_timer;
1004         u32     rate_record;
1005         u32     rateCountDiffRecord;
1006         u32     ContiuneDiffCount;
1007         bool bswitch_fsync;
1008
1009         u8      framesync;
1010         u32     framesyncC34;
1011         u8      framesyncMonitor;
1012
1013         //by amy for gpio
1014         bool bHwRadioOff;
1015         //by amy for ps
1016         bool RFChangeInProgress; // RF Chnage in progress, by Bruce, 2007-10-30
1017         bool SetRFPowerStateInProgress;
1018         RT_OP_MODE OpMode;
1019         //by amy for reset_count
1020         u32 reset_count;
1021
1022         //by amy for silent reset
1023         RESET_TYPE      ResetProgress;
1024         bool            bForcedSilentReset;
1025         bool            bDisableNormalResetCheck;
1026         u16             TxCounter;
1027         u16             RxCounter;
1028         int             IrpPendingCount;
1029         bool            bResetInProgress;
1030         bool            force_reset;
1031         u8              InitialGainOperateType;
1032
1033         //define work item by amy 080526
1034         struct delayed_work update_beacon_wq;
1035         struct delayed_work watch_dog_wq;
1036         struct delayed_work txpower_tracking_wq;
1037         struct delayed_work rfpath_check_wq;
1038         struct delayed_work gpio_change_rf_wq;
1039         struct delayed_work initialgain_operate_wq;
1040         struct workqueue_struct *priv_wq;
1041 }r8192_priv;
1042
1043 bool init_firmware(struct net_device *dev);
1044 short rtl8192_tx(struct net_device *dev, struct sk_buff* skb);
1045 u32 read_cam(struct r8192_priv *priv, u8 addr);
1046 void write_cam(struct r8192_priv *priv, u8 addr, u32 data);
1047 u8 read_nic_byte(struct r8192_priv *priv, int x);
1048 u32 read_nic_dword(struct r8192_priv *priv, int x);
1049 u16 read_nic_word(struct r8192_priv *priv, int x) ;
1050 void write_nic_byte(struct r8192_priv *priv, int x,u8 y);
1051 void write_nic_word(struct r8192_priv *priv, int x,u16 y);
1052 void write_nic_dword(struct r8192_priv *priv, int x,u32 y);
1053
1054 void rtl8192_halt_adapter(struct net_device *dev, bool reset);
1055 void rtl8192_rx_enable(struct net_device *);
1056 void rtl8192_tx_enable(struct net_device *);
1057
1058 void rtl8192_update_msr(struct net_device *dev);
1059 int rtl8192_down(struct net_device *dev);
1060 int rtl8192_up(struct net_device *dev);
1061 void rtl8192_commit(struct net_device *dev);
1062 void rtl8192_set_chan(struct net_device *dev,short ch);
1063 void write_phy(struct net_device *dev, u8 adr, u8 data);
1064 void write_phy_cck(struct net_device *dev, u8 adr, u32 data);
1065 void write_phy_ofdm(struct net_device *dev, u8 adr, u32 data);
1066 void CamResetAllEntry(struct net_device* dev);
1067 void EnableHWSecurityConfig8192(struct net_device *dev);
1068 void setKey(struct net_device *dev, u8 EntryNo, u8 KeyIndex, u16 KeyType, const u8 *MacAddr, u8 DefaultKey, u32 *KeyContent );
1069 void dm_cck_txpower_adjust(struct net_device *dev, bool binch14);
1070 void firmware_init_param(struct net_device *dev);
1071 RT_STATUS cmpk_message_handle_tx(struct net_device *dev, u8* codevirtualaddress, u32 packettype, u32 buffer_len);
1072 void rtl8192_hw_wakeup_wq (struct work_struct *work);
1073
1074 short rtl8192_is_tx_queue_empty(struct net_device *dev);
1075 #ifdef ENABLE_IPS
1076 void IPSEnter(struct net_device *dev);
1077 void IPSLeave(struct net_device *dev);
1078 void InactivePsWorkItemCallback(struct net_device *dev);
1079 void IPSLeave_wq(struct work_struct *work);
1080 void ieee80211_ips_leave_wq(struct net_device *dev);
1081 void ieee80211_ips_leave(struct net_device *dev);
1082 #endif
1083 #ifdef ENABLE_LPS
1084 void LeisurePSEnter(struct net_device *dev);
1085 void LeisurePSLeave(struct net_device *dev);
1086 #endif
1087
1088 bool NicIFEnableNIC(struct net_device* dev);
1089 bool NicIFDisableNIC(struct net_device* dev);
1090
1091 void rtl8192_irq_disable(struct net_device *dev);
1092 void PHY_SetRtl8192eRfOff(struct net_device* dev);
1093 #endif