Pileus Git - ~andy/linux/blob - drivers/staging/rtl8192e/r8192E.h

   1 /*
   2    This is part of rtl8187 OpenSource driver.
   3    Copyright (C) Andrea Merello 2004-2005  <andreamrl@tiscali.it>
   4    Released under the terms of GPL (General Public Licence)
   5
   6    Parts of this driver are based on the GPL part of the
   7    official realtek driver
   8
   9    Parts of this driver are based on the rtl8192 driver skeleton
  10    from Patric Schenke & Andres Salomon
  11
  12    Parts of this driver are based on the Intel Pro Wireless 2100 GPL driver
  13
  14    We want to tanks the Authors of those projects and the Ndiswrapper
  15    project Authors.
  16 */
  17
  18 #ifndef R819xU_H
  19 #define R819xU_H
  20
  21 #include <linux/module.h>
  22 #include <linux/kernel.h>
  23 #include <linux/init.h>
  24 #include <linux/ioport.h>
  25 #include <linux/sched.h>
  26 #include <linux/types.h>
  27 #include <linux/slab.h>
  28 #include <linux/netdevice.h>
  29 #include <linux/pci.h>
  30 #include <linux/etherdevice.h>
  31 #include <linux/delay.h>
  32 #include <linux/rtnetlink.h>    //for rtnl_lock()
  33 #include <linux/wireless.h>
  34 #include <linux/timer.h>
  35 #include <linux/proc_fs.h>      // Necessary because we use the proc fs
  36 #include <linux/if_arp.h>
  37 #include <linux/random.h>
  38 #include <linux/version.h>
  39 #include <asm/io.h>
  40 #include "ieee80211/rtl819x_HT.h"
  41 #include "ieee80211/ieee80211.h"
  42
  43
  44
  45
  46 #define RTL819xE_MODULE_NAME "rtl819xE"
  47
  48 #define FALSE 0
  49 #define TRUE 1
  50 #define MAX_KEY_LEN     61
  51 #define KEY_BUF_SIZE    5
  52
  53 #define BIT0            0x00000001
  54 #define BIT1            0x00000002
  55 #define BIT2            0x00000004
  56 #define BIT3            0x00000008
  57 #define BIT4            0x00000010
  58 #define BIT5            0x00000020
  59 #define BIT6            0x00000040
  60 #define BIT7            0x00000080
  61 #define BIT8            0x00000100
  62 #define BIT9            0x00000200
  63 #define BIT10           0x00000400
  64 #define BIT11           0x00000800
  65 #define BIT12           0x00001000
  66 #define BIT13           0x00002000
  67 #define BIT14           0x00004000
  68 #define BIT15           0x00008000
  69 #define BIT16           0x00010000
  70 #define BIT17           0x00020000
  71 #define BIT18           0x00040000
  72 #define BIT19           0x00080000
  73 #define BIT20           0x00100000
  74 #define BIT21           0x00200000
  75 #define BIT22           0x00400000
  76 #define BIT23           0x00800000
  77 #define BIT24           0x01000000
  78 #define BIT25           0x02000000
  79 #define BIT26           0x04000000
  80 #define BIT27           0x08000000
  81 #define BIT28           0x10000000
  82 #define BIT29           0x20000000
  83 #define BIT30           0x40000000
  84 #define BIT31           0x80000000
  85 // Rx smooth factor
  86 #define Rx_Smooth_Factor                20
  87 /* 2007/06/04 MH Define sliding window for RSSI history. */
  88 #define         PHY_RSSI_SLID_WIN_MAX                           100
  89 #define         PHY_Beacon_RSSI_SLID_WIN_MAX            10
  90
  91 #define IC_VersionCut_D 0x3
  92 #define IC_VersionCut_E 0x4
  93
  94 #if 0 //we need to use RT_TRACE instead DMESG as RT_TRACE will clearly show debug level wb.
  95 #define DMESG(x,a...) printk(KERN_INFO RTL819xE_MODULE_NAME ": " x "\n", ## a)
  96 #else
  97 #define DMESG(x,a...)
  98 extern u32 rt_global_debug_component;
  99 #define RT_TRACE(component, x, args...) \
 100 do { if(rt_global_debug_component & component) \
 101         printk(KERN_DEBUG RTL819xE_MODULE_NAME ":" x , \
 102                ##args);\
 103 }while(0);
 104
 105 #define COMP_TRACE                              BIT0            // For function call tracing.
 106 #define COMP_DBG                                BIT1            // Only for temporary debug message.
 107 #define COMP_INIT                               BIT2            // during driver initialization / halt / reset.
 108
 109
 110 #define COMP_RECV                               BIT3            // Reveive part data path.
 111 #define COMP_SEND                               BIT4            // Send part path.
 112 #define COMP_IO                                 BIT5            // I/O Related. Added by Annie, 2006-03-02.
 113 #define COMP_POWER                              BIT6            // 802.11 Power Save mode or System/Device Power state related.
 114 #define COMP_EPROM                              BIT7            // 802.11 link related: join/start BSS, leave BSS.
 115 #define COMP_SWBW                               BIT8    // For bandwidth switch.
 116 #define COMP_SEC                                BIT9// For Security.
 117
 118
 119 #define COMP_TURBO                              BIT10   // For Turbo Mode related. By Annie, 2005-10-21.
 120 #define COMP_QOS                                BIT11   // For QoS.
 121
 122 #define COMP_RATE                               BIT12   // For Rate Adaptive mechanism, 2006.07.02, by rcnjko. #define COMP_EVENTS                              0x00000080      // Event handling
 123 #define COMP_RXDESC                             BIT13   // Show Rx desc information for SD3 debug. Added by Annie, 2006-07-15.
 124 #define COMP_PHY                                BIT14
 125 #define COMP_DIG                                BIT15   // For DIG, 2006.09.25, by rcnjko.
 126 #define COMP_TXAGC                              BIT16   // For Tx power, 060928, by rcnjko.
 127 #define COMP_HALDM                              BIT17   // For HW Dynamic Mechanism, 061010, by rcnjko.
 128 #define COMP_POWER_TRACKING                     BIT18   //FOR 8190 TX POWER TRACKING
 129 #define COMP_EVENTS                             BIT19   // Event handling
 130
 131 #define COMP_RF                                 BIT20   // For RF.
 132
 133 /* 11n or 8190 specific code should be put below this line */
 134
 135
 136 #define COMP_FIRMWARE                           BIT21   //for firmware downloading
 137 #define COMP_HT                                 BIT22   // For 802.11n HT related information. by Emily 2006-8-11
 138
 139 #define COMP_RESET                              BIT23
 140 #define COMP_CMDPKT                             BIT24
 141 #define COMP_SCAN                               BIT25
 142 #define COMP_IPS                                BIT26
 143 #define COMP_DOWN                               BIT27  // for rm driver module
 144 #define COMP_INTR                               BIT28  // for interrupt
 145 #define COMP_ERR                                BIT31  // for error out, always on
 146 #endif
 147
 148
 149 //
 150 // Queue Select Value in TxDesc
 151 //
 152 #define QSLT_BK                                 0x1
 153 #define QSLT_BE                                 0x0
 154 #define QSLT_VI                                 0x4
 155 #define QSLT_VO                                 0x6
 156 #define QSLT_BEACON                             0x10
 157 #define QSLT_HIGH                               0x11
 158 #define QSLT_MGNT                               0x12
 159 #define QSLT_CMD                                0x13
 160
 161 #define DESC90_RATE1M                           0x00
 162 #define DESC90_RATE2M                           0x01
 163 #define DESC90_RATE5_5M                         0x02
 164 #define DESC90_RATE11M                          0x03
 165 #define DESC90_RATE6M                           0x04
 166 #define DESC90_RATE9M                           0x05
 167 #define DESC90_RATE12M                          0x06
 168 #define DESC90_RATE18M                          0x07
 169 #define DESC90_RATE24M                          0x08
 170 #define DESC90_RATE36M                          0x09
 171 #define DESC90_RATE48M                          0x0a
 172 #define DESC90_RATE54M                          0x0b
 173 #define DESC90_RATEMCS0                         0x00
 174 #define DESC90_RATEMCS1                         0x01
 175 #define DESC90_RATEMCS2                         0x02
 176 #define DESC90_RATEMCS3                         0x03
 177 #define DESC90_RATEMCS4                         0x04
 178 #define DESC90_RATEMCS5                         0x05
 179 #define DESC90_RATEMCS6                         0x06
 180 #define DESC90_RATEMCS7                         0x07
 181 #define DESC90_RATEMCS8                         0x08
 182 #define DESC90_RATEMCS9                         0x09
 183 #define DESC90_RATEMCS10                        0x0a
 184 #define DESC90_RATEMCS11                        0x0b
 185 #define DESC90_RATEMCS12                        0x0c
 186 #define DESC90_RATEMCS13                        0x0d
 187 #define DESC90_RATEMCS14                        0x0e
 188 #define DESC90_RATEMCS15                        0x0f
 189 #define DESC90_RATEMCS32                        0x20
 190
 191 #define RTL819X_DEFAULT_RF_TYPE RF_1T2R
 192 #define EEPROM_Default_LegacyHTTxPowerDiff      0x4
 193 #define IEEE80211_WATCH_DOG_TIME    2000
 194
 195 /* For rtl819x */
 196 typedef struct _tx_desc_819x_pci {
 197         //DWORD 0
 198         u16     PktSize;
 199         u8      Offset;
 200         u8      Reserved1:3;
 201         u8      CmdInit:1;
 202         u8      LastSeg:1;
 203         u8      FirstSeg:1;
 204         u8      LINIP:1;
 205         u8      OWN:1;
 206
 207         //DWORD 1
 208         u8      TxFWInfoSize;
 209         u8      RATid:3;
 210         u8      DISFB:1;
 211         u8      USERATE:1;
 212         u8      MOREFRAG:1;
 213         u8      NoEnc:1;
 214         u8      PIFS:1;
 215         u8      QueueSelect:5;
 216         u8      NoACM:1;
 217         u8      Resv:2;
 218         u8      SecCAMID:5;
 219         u8      SecDescAssign:1;
 220         u8      SecType:2;
 221
 222         //DWORD 2
 223         u16     TxBufferSize;
 224         u8      PktId:7;
 225         u8      Resv1:1;
 226         u8      Reserved2;
 227
 228         //DWORD 3
 229         u32     TxBuffAddr;
 230
 231         //DWORD 4
 232         u32     NextDescAddress;
 233
 234         //DWORD 5,6,7
 235         u32     Reserved5;
 236         u32     Reserved6;
 237         u32     Reserved7;
 238 }tx_desc_819x_pci, *ptx_desc_819x_pci;
 239
 240
 241 typedef struct _tx_desc_cmd_819x_pci {
 242         //DWORD 0
 243         u16     PktSize;
 244         u8      Reserved1;
 245         u8      CmdType:3;
 246         u8      CmdInit:1;
 247         u8      LastSeg:1;
 248         u8      FirstSeg:1;
 249         u8      LINIP:1;
 250         u8      OWN:1;
 251
 252         //DOWRD 1
 253         u16     ElementReport;
 254         u16     Reserved2;
 255
 256         //DOWRD 2
 257         u16     TxBufferSize;
 258         u16     Reserved3;
 259
 260        //DWORD 3,4,5
 261         u32     TxBufferAddr;
 262         u32     NextDescAddress;
 263         u32     Reserved4;
 264         u32     Reserved5;
 265         u32     Reserved6;
 266 }tx_desc_cmd_819x_pci, *ptx_desc_cmd_819x_pci;
 267
 268
 269 typedef struct _tx_fwinfo_819x_pci {
 270         //DOWRD 0
 271         u8              TxRate:7;
 272         u8              CtsEnable:1;
 273         u8              RtsRate:7;
 274         u8              RtsEnable:1;
 275         u8              TxHT:1;
 276         u8              Short:1;                //Short PLCP for CCK, or short GI for 11n MCS
 277         u8              TxBandwidth:1;          // This is used for HT MCS rate only.
 278         u8              TxSubCarrier:2;         // This is used for legacy OFDM rate only.
 279         u8              STBC:2;
 280         u8              AllowAggregation:1;
 281         u8              RtsHT:1;                //Interpre RtsRate field as high throughput data rate
 282         u8              RtsShort:1;             //Short PLCP for CCK, or short GI for 11n MCS
 283         u8              RtsBandwidth:1;         // This is used for HT MCS rate only.
 284         u8              RtsSubcarrier:2;        // This is used for legacy OFDM rate only.
 285         u8              RtsSTBC:2;
 286         u8              EnableCPUDur:1;         //Enable firmware to recalculate and assign packet duration
 287
 288         //DWORD 1
 289         u8              RxMF:2;
 290         u8              RxAMD:3;
 291         u8              Reserved1:3;
 292         u8              Reserved2;
 293         u8              Reserved3;
 294         u8              Reserved4;
 295
 296         //u32                Reserved;
 297 }tx_fwinfo_819x_pci, *ptx_fwinfo_819x_pci;
 298
 299 typedef struct _rx_desc_819x_pci{
 300         //DOWRD 0
 301         u16                     Length:14;
 302         u16                     CRC32:1;
 303         u16                     ICV:1;
 304         u8                      RxDrvInfoSize;
 305         u8                      Shift:2;
 306         u8                      PHYStatus:1;
 307         u8                      SWDec:1;
 308         u8                                      LastSeg:1;
 309         u8                                      FirstSeg:1;
 310         u8                                      EOR:1;
 311         u8                                      OWN:1;
 312
 313         //DWORD 1
 314         u32                     Reserved2;
 315
 316         //DWORD 2
 317         u32                     Reserved3;
 318
 319         //DWORD 3
 320         u32     BufferAddress;
 321
 322 }rx_desc_819x_pci, *prx_desc_819x_pci;
 323
 324 typedef struct _rx_fwinfo_819x_pci{
 325         //DWORD 0
 326         u16                     Reserved1:12;
 327         u16                     PartAggr:1;
 328         u16                     FirstAGGR:1;
 329         u16                     Reserved2:2;
 330
 331         u8                      RxRate:7;
 332         u8                      RxHT:1;
 333
 334         u8                      BW:1;
 335         u8                      SPLCP:1;
 336         u8                      Reserved3:2;
 337         u8                      PAM:1;
 338         u8                      Mcast:1;
 339         u8                      Bcast:1;
 340         u8                      Reserved4:1;
 341
 342         //DWORD 1
 343         u32                     TSFL;
 344
 345 }rx_fwinfo_819x_pci, *prx_fwinfo_819x_pci;
 346
 347 #define MAX_DEV_ADDR_SIZE               8  /* support till 64 bit bus width OS */
 348 #define MAX_FIRMWARE_INFORMATION_SIZE   32 /*2006/04/30 by Emily forRTL8190*/
 349 #define MAX_802_11_HEADER_LENGTH        (40 + MAX_FIRMWARE_INFORMATION_SIZE)
 350 #define ENCRYPTION_MAX_OVERHEAD         128
 351 #define MAX_FRAGMENT_COUNT              8
 352 #define MAX_TRANSMIT_BUFFER_SIZE        (1600+(MAX_802_11_HEADER_LENGTH+ENCRYPTION_MAX_OVERHEAD)*MAX_FRAGMENT_COUNT)
 353
 354 #define scrclng                                 4               // octets for crc32 (FCS, ICV)
 355 /* 8190 Loopback Mode definition */
 356 typedef enum _rtl819x_loopback{
 357         RTL819X_NO_LOOPBACK = 0,
 358         RTL819X_MAC_LOOPBACK = 1,
 359         RTL819X_DMA_LOOPBACK = 2,
 360         RTL819X_CCK_LOOPBACK = 3,
 361 }rtl819x_loopback_e;
 362
 363 /* due to rtl8192 firmware */
 364 typedef enum _desc_packet_type_e{
 365         DESC_PACKET_TYPE_INIT = 0,
 366         DESC_PACKET_TYPE_NORMAL = 1,
 367 }desc_packet_type_e;
 368
 369 typedef enum _firmware_status{
 370         FW_STATUS_0_INIT = 0,
 371         FW_STATUS_1_MOVE_BOOT_CODE = 1,
 372         FW_STATUS_2_MOVE_MAIN_CODE = 2,
 373         FW_STATUS_3_TURNON_CPU = 3,
 374         FW_STATUS_4_MOVE_DATA_CODE = 4,
 375         FW_STATUS_5_READY = 5,
 376 }firmware_status_e;
 377
 378 typedef struct _rt_firmware{
 379         firmware_status_e firmware_status;
 380         u16               cmdpacket_frag_thresold;
 381 #define RTL8190_MAX_FIRMWARE_CODE_SIZE  64000   //64k
 382 #define MAX_FW_INIT_STEP                3
 383         u8                firmware_buf[MAX_FW_INIT_STEP][RTL8190_MAX_FIRMWARE_CODE_SIZE];
 384         u16               firmware_buf_size[MAX_FW_INIT_STEP];
 385 }rt_firmware, *prt_firmware;
 386
 387 #define MAX_RECEIVE_BUFFER_SIZE 9100    // Add this to 9100 bytes to receive A-MSDU from RT-AP
 388
 389 /* Firmware Queue Layout */
 390 #define NUM_OF_FIRMWARE_QUEUE           10
 391 #define NUM_OF_PAGES_IN_FW              0x100
 392 #define NUM_OF_PAGE_IN_FW_QUEUE_BE      0x0aa
 393 #define NUM_OF_PAGE_IN_FW_QUEUE_BK      0x007
 394 #define NUM_OF_PAGE_IN_FW_QUEUE_VI      0x024
 395 #define NUM_OF_PAGE_IN_FW_QUEUE_VO      0x007
 396 #define NUM_OF_PAGE_IN_FW_QUEUE_HCCA    0
 397 #define NUM_OF_PAGE_IN_FW_QUEUE_CMD     0x2
 398 #define NUM_OF_PAGE_IN_FW_QUEUE_MGNT    0x10
 399 #define NUM_OF_PAGE_IN_FW_QUEUE_HIGH    0
 400 #define NUM_OF_PAGE_IN_FW_QUEUE_BCN     0x4
 401 #define NUM_OF_PAGE_IN_FW_QUEUE_PUB     0xd
 402 #define APPLIED_RESERVED_QUEUE_IN_FW    0x80000000
 403 #define RSVD_FW_QUEUE_PAGE_BK_SHIFT     0x00
 404 #define RSVD_FW_QUEUE_PAGE_BE_SHIFT     0x08
 405 #define RSVD_FW_QUEUE_PAGE_VI_SHIFT     0x10
 406 #define RSVD_FW_QUEUE_PAGE_VO_SHIFT     0x18
 407 #define RSVD_FW_QUEUE_PAGE_MGNT_SHIFT   0x10
 408 #define RSVD_FW_QUEUE_PAGE_CMD_SHIFT    0x08
 409 #define RSVD_FW_QUEUE_PAGE_BCN_SHIFT    0x00
 410 #define RSVD_FW_QUEUE_PAGE_PUB_SHIFT    0x08
 411
 412 #define DCAM                    0xAC                    // Debug CAM Interface
 413 #define AESMSK_FC               0xB2    // AES Mask register for frame control (0xB2~0xB3). Added by Annie, 2006-03-06.
 414
 415
 416 #define CAM_CONTENT_COUNT       8
 417 #define CFG_VALID               BIT15
 418 #define EPROM_93c46 0
 419 #define EPROM_93c56 1
 420
 421 #define DEFAULT_FRAG_THRESHOLD 2342U
 422 #define MIN_FRAG_THRESHOLD     256U
 423 #define DEFAULT_BEACONINTERVAL 0x64U
 424
 425 #define DEFAULT_RETRY_RTS 7
 426 #define DEFAULT_RETRY_DATA 7
 427
 428 #define         PHY_RSSI_SLID_WIN_MAX                           100
 429
 430
 431 typedef enum _WIRELESS_MODE {
 432         WIRELESS_MODE_UNKNOWN = 0x00,
 433         WIRELESS_MODE_A = 0x01,
 434         WIRELESS_MODE_B = 0x02,
 435         WIRELESS_MODE_G = 0x04,
 436         WIRELESS_MODE_AUTO = 0x08,
 437         WIRELESS_MODE_N_24G = 0x10,
 438         WIRELESS_MODE_N_5G = 0x20
 439 } WIRELESS_MODE;
 440
 441 #define RTL_IOCTL_WPA_SUPPLICANT                SIOCIWFIRSTPRIV+30
 442
 443 typedef struct buffer
 444 {
 445         struct buffer *next;
 446         u32 *buf;
 447         dma_addr_t dma;
 448
 449 } buffer;
 450
 451 typedef struct _rt_9x_tx_rate_history {
 452         u32             cck[4];
 453         u32             ofdm[8];
 454         // HT_MCS[0][]: BW=0 SG=0
 455         // HT_MCS[1][]: BW=1 SG=0
 456         // HT_MCS[2][]: BW=0 SG=1
 457         // HT_MCS[3][]: BW=1 SG=1
 458         u32             ht_mcs[4][16];
 459 }rt_tx_rahis_t, *prt_tx_rahis_t;
 460
 461 typedef struct _RT_SMOOTH_DATA_4RF {
 462         char    elements[4][100];//array to store values
 463         u32     index;                  //index to current array to store
 464         u32     TotalNum;               //num of valid elements
 465         u32     TotalVal[4];            //sum of valid elements
 466 }RT_SMOOTH_DATA_4RF, *PRT_SMOOTH_DATA_4RF;
 467
 468 typedef enum _tag_TxCmd_Config_Index{
 469         TXCMD_TXRA_HISTORY_CTRL                         = 0xFF900000,
 470         TXCMD_RESET_TX_PKT_BUFF                         = 0xFF900001,
 471         TXCMD_RESET_RX_PKT_BUFF                         = 0xFF900002,
 472         TXCMD_SET_TX_DURATION                           = 0xFF900003,
 473         TXCMD_SET_RX_RSSI                                               = 0xFF900004,
 474         TXCMD_SET_TX_PWR_TRACKING                       = 0xFF900005,
 475         TXCMD_XXXX_CTRL,
 476 }DCMD_TXCMD_OP;
 477
 478 typedef struct Stats
 479 {
 480         unsigned long rxrdu;
 481         unsigned long rxok;
 482         unsigned long received_rate_histogram[4][32];   //0: Total, 1:OK, 2:CRC, 3:ICV
 483         unsigned long rxoverflow;
 484         unsigned long rxint;
 485         unsigned long txoverflow;
 486         unsigned long txbeokint;
 487         unsigned long txbkokint;
 488         unsigned long txviokint;
 489         unsigned long txvookint;
 490         unsigned long txbeaconokint;
 491         unsigned long txbeaconerr;
 492         unsigned long txmanageokint;
 493         unsigned long txcmdpktokint;
 494         unsigned long txfeedback;
 495         unsigned long txfeedbackok;
 496         unsigned long txoktotal;
 497         unsigned long txbytesunicast;
 498         unsigned long rxbytesunicast;
 499
 500         unsigned long slide_signal_strength[100];
 501         unsigned long slide_evm[100];
 502         unsigned long   slide_rssi_total;       // For recording sliding window's RSSI value
 503         unsigned long slide_evm_total;  // For recording sliding window's EVM value
 504         long signal_strength; // Transformed, in dbm. Beautified signal strength for UI, not correct.
 505         u8 rx_rssi_percentage[4];
 506         u8 rx_evm_percentage[2];
 507         u32 Slide_Beacon_pwdb[100];
 508         u32 Slide_Beacon_Total;
 509         RT_SMOOTH_DATA_4RF              cck_adc_pwdb;
 510 } Stats;
 511
 512
 513 // Bandwidth Offset
 514 #define HAL_PRIME_CHNL_OFFSET_DONT_CARE         0
 515 #define HAL_PRIME_CHNL_OFFSET_LOWER                     1
 516 #define HAL_PRIME_CHNL_OFFSET_UPPER                     2
 517
 518 typedef struct  ChnlAccessSetting {
 519         u16 SIFS_Timer;
 520         u16 DIFS_Timer;
 521         u16 SlotTimeTimer;
 522         u16 EIFS_Timer;
 523         u16 CWminIndex;
 524         u16 CWmaxIndex;
 525 }*PCHANNEL_ACCESS_SETTING,CHANNEL_ACCESS_SETTING;
 526
 527 typedef struct _BB_REGISTER_DEFINITION{
 528         u32 rfintfs;                    // set software control: //             0x870~0x877[8 bytes]
 529         u32 rfintfi;                    // readback data: //            0x8e0~0x8e7[8 bytes]
 530         u32 rfintfo;                    // output data: //              0x860~0x86f [16 bytes]
 531         u32 rfintfe;                    // output enable: //            0x860~0x86f [16 bytes]
 532         u32 rf3wireOffset;              // LSSI data: //                0x840~0x84f [16 bytes]
 533         u32 rfLSSI_Select;              // BB Band Select: //           0x878~0x87f [8 bytes]
 534         u32 rfTxGainStage;              // Tx gain stage: //            0x80c~0x80f [4 bytes]
 535         u32 rfHSSIPara1;                // wire parameter control1 : //         0x820~0x823,0x828~0x82b, 0x830~0x833, 0x838~0x83b [16 bytes]
 536         u32 rfHSSIPara2;                // wire parameter control2 : //         0x824~0x827,0x82c~0x82f, 0x834~0x837, 0x83c~0x83f [16 bytes]
 537         u32 rfSwitchControl;    //Tx Rx antenna control : //            0x858~0x85f [16 bytes]
 538         u32 rfAGCControl1;      //AGC parameter control1 : //           0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63, 0xc68~0xc6b [16 bytes]
 539         u32 rfAGCControl2;      //AGC parameter control2 : //           0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67, 0xc6c~0xc6f [16 bytes]
 540         u32 rfRxIQImbalance;    //OFDM Rx IQ imbalance matrix : //              0xc14~0xc17,0xc1c~0xc1f, 0xc24~0xc27, 0xc2c~0xc2f [16 bytes]
 541         u32 rfRxAFE;                    //Rx IQ DC ofset and Rx digital filter, Rx DC notch filter : //         0xc10~0xc13,0xc18~0xc1b, 0xc20~0xc23, 0xc28~0xc2b [16 bytes]
 542         u32 rfTxIQImbalance;    //OFDM Tx IQ imbalance matrix //                0xc80~0xc83,0xc88~0xc8b, 0xc90~0xc93, 0xc98~0xc9b [16 bytes]
 543         u32 rfTxAFE;                    //Tx IQ DC Offset and Tx DFIR type //           0xc84~0xc87,0xc8c~0xc8f, 0xc94~0xc97, 0xc9c~0xc9f [16 bytes]
 544         u32 rfLSSIReadBack;     //LSSI RF readback data //              0x8a0~0x8af [16 bytes]
 545 }BB_REGISTER_DEFINITION_T, *PBB_REGISTER_DEFINITION_T;
 546
 547 typedef struct _rate_adaptive
 548 {
 549         u8                              rate_adaptive_disabled;
 550         u8                              ratr_state;
 551         u16                             reserve;
 552
 553         u32                             high_rssi_thresh_for_ra;
 554         u32                             high2low_rssi_thresh_for_ra;
 555         u8                              low2high_rssi_thresh_for_ra40M;
 556         u32                             low_rssi_thresh_for_ra40M;
 557         u8                              low2high_rssi_thresh_for_ra20M;
 558         u32                             low_rssi_thresh_for_ra20M;
 559         u32                             upper_rssi_threshold_ratr;
 560         u32                             middle_rssi_threshold_ratr;
 561         u32                             low_rssi_threshold_ratr;
 562         u32                             low_rssi_threshold_ratr_40M;
 563         u32                             low_rssi_threshold_ratr_20M;
 564         u8                              ping_rssi_enable;       //cosa add for test
 565         u32                             ping_rssi_ratr; //cosa add for test
 566         u32                             ping_rssi_thresh_for_ra;//cosa add for test
 567         u32                             last_ratr;
 568
 569 } rate_adaptive, *prate_adaptive;
 570 #define TxBBGainTableLength 37
 571 #define CCKTxBBGainTableLength 23
 572 typedef struct _txbbgain_struct
 573 {
 574         long    txbb_iq_amplifygain;
 575         u32     txbbgain_value;
 576 } txbbgain_struct, *ptxbbgain_struct;
 577
 578 typedef struct _ccktxbbgain_struct
 579 {
 580         //The Value is from a22 to a29 one Byte one time is much Safer
 581         u8      ccktxbb_valuearray[8];
 582 } ccktxbbgain_struct,*pccktxbbgain_struct;
 583
 584
 585 typedef struct _init_gain
 586 {
 587         u8                              xaagccore1;
 588         u8                              xbagccore1;
 589         u8                              xcagccore1;
 590         u8                              xdagccore1;
 591         u8                              cca;
 592
 593 } init_gain, *pinit_gain;
 594
 595 /* 2007/11/02 MH Define RF mode temporarily for test. */
 596 typedef enum tag_Rf_Operatetion_State
 597 {
 598     RF_STEP_INIT = 0,
 599     RF_STEP_NORMAL,
 600     RF_STEP_MAX
 601 }RF_STEP_E;
 602
 603 typedef enum _RT_STATUS{
 604         RT_STATUS_SUCCESS,
 605         RT_STATUS_FAILURE,
 606         RT_STATUS_PENDING,
 607         RT_STATUS_RESOURCE
 608 }RT_STATUS,*PRT_STATUS;
 609
 610 typedef enum _RT_CUSTOMER_ID
 611 {
 612         RT_CID_DEFAULT = 0,
 613         RT_CID_8187_ALPHA0 = 1,
 614         RT_CID_8187_SERCOMM_PS = 2,
 615         RT_CID_8187_HW_LED = 3,
 616         RT_CID_8187_NETGEAR = 4,
 617         RT_CID_WHQL = 5,
 618         RT_CID_819x_CAMEO  = 6,
 619         RT_CID_819x_RUNTOP = 7,
 620         RT_CID_819x_Senao = 8,
 621         RT_CID_TOSHIBA = 9,     // Merge by Jacken, 2008/01/31.
 622         RT_CID_819x_Netcore = 10,
 623         RT_CID_Nettronix = 11,
 624         RT_CID_DLINK = 12,
 625         RT_CID_PRONET = 13,
 626         RT_CID_COREGA = 14,
 627 }RT_CUSTOMER_ID, *PRT_CUSTOMER_ID;
 628
 629 /* LED customization. */
 630
 631 typedef enum _LED_STRATEGY_8190{
 632         SW_LED_MODE0, // SW control 1 LED via GPIO0. It is default option.
 633         SW_LED_MODE1, // SW control for PCI Express
 634         SW_LED_MODE2, // SW control for Cameo.
 635         SW_LED_MODE3, // SW contorl for RunTop.
 636         SW_LED_MODE4, // SW control for Netcore
 637         SW_LED_MODE5, //added by vivi, for led new mode, DLINK
 638         SW_LED_MODE6, //added by vivi, for led new mode, PRONET
 639         HW_LED, // HW control 2 LEDs, LED0 and LED1 (there are 4 different control modes)
 640 }LED_STRATEGY_8190, *PLED_STRATEGY_8190;
 641
 642 #define CHANNEL_PLAN_LEN                                10
 643
 644 #define sCrcLng                 4
 645
 646 typedef struct _TX_FWINFO_STRUCUTRE{
 647         //DOWRD 0
 648         u8                      TxRate:7;
 649         u8                      CtsEnable:1;
 650         u8                      RtsRate:7;
 651         u8                      RtsEnable:1;
 652         u8                      TxHT:1;
 653         u8                      Short:1;
 654         u8                      TxBandwidth:1;
 655         u8                      TxSubCarrier:2;
 656         u8                      STBC:2;
 657         u8                      AllowAggregation:1;
 658         u8                      RtsHT:1;
 659         u8                      RtsShort:1;
 660         u8                      RtsBandwidth:1;
 661         u8                      RtsSubcarrier:2;
 662         u8                      RtsSTBC:2;
 663         u8                      EnableCPUDur:1;
 664
 665         //DWORD 1
 666         u32                     RxMF:2;
 667         u32                     RxAMD:3;
 668         u32                     Reserved1:3;
 669         u32                     TxAGCOffset:4;
 670         u32                     TxAGCSign:1;
 671         u32                     Tx_INFO_RSVD:6;
 672         u32                     PacketID:13;
 673 }TX_FWINFO_T;
 674
 675
 676 typedef struct _TX_FWINFO_8190PCI{
 677         //DOWRD 0
 678         u8                      TxRate:7;
 679         u8                      CtsEnable:1;
 680         u8                      RtsRate:7;
 681         u8                      RtsEnable:1;
 682         u8                      TxHT:1;
 683         u8                      Short:1;                                                //Short PLCP for CCK, or short GI for 11n MCS
 684         u8                      TxBandwidth:1;                          // This is used for HT MCS rate only.
 685         u8                      TxSubCarrier:2;                         // This is used for legacy OFDM rate only.
 686         u8                      STBC:2;
 687         u8                      AllowAggregation:1;
 688         u8                      RtsHT:1;                                                //Interpre RtsRate field as high throughput data rate
 689         u8                      RtsShort:1;                             //Short PLCP for CCK, or short GI for 11n MCS
 690         u8                      RtsBandwidth:1;                         // This is used for HT MCS rate only.
 691         u8                      RtsSubcarrier:2;                                // This is used for legacy OFDM rate only.
 692         u8                      RtsSTBC:2;
 693         u8                      EnableCPUDur:1;                         //Enable firmware to recalculate and assign packet duration
 694
 695         //DWORD 1
 696         u32                     RxMF:2;
 697         u32                     RxAMD:3;
 698         u32                     TxPerPktInfoFeedback:1;         // 1: indicate that the transimission info of this packet should be gathered by Firmware and retured by Rx Cmd.
 699         u32                     Reserved1:2;
 700         u32                     TxAGCOffset:4;          // Only 90 support
 701         u32                     TxAGCSign:1;            // Only 90 support
 702         u32                     RAW_TXD:1;                      // MAC will send data in txpktbuffer without any processing,such as CRC check
 703         u32                     Retry_Limit:4;          // CCX Support relative retry limit FW page only support 4 bits now.
 704         u32                     Reserved2:1;
 705         u32                     PacketID:13;
 706
 707         // DW 2
 708
 709 }TX_FWINFO_8190PCI, *PTX_FWINFO_8190PCI;
 710
 711 typedef struct _phy_ofdm_rx_status_report_819xpci
 712 {
 713         u8      trsw_gain_X[4];
 714         u8      pwdb_all;
 715         u8      cfosho_X[4];
 716         u8      cfotail_X[4];
 717         u8      rxevm_X[2];
 718         u8      rxsnr_X[4];
 719         u8      pdsnr_X[2];
 720         u8      csi_current_X[2];
 721         u8      csi_target_X[2];
 722         u8      sigevm;
 723         u8      max_ex_pwr;
 724         u8      sgi_en;
 725         u8      rxsc_sgien_exflg;
 726 }phy_sts_ofdm_819xpci_t;
 727
 728 typedef struct _phy_cck_rx_status_report_819xpci
 729 {
 730         /* For CCK rate descriptor. This is a unsigned 8:1 variable. LSB bit presend
 731            0.5. And MSB 7 bts presend a signed value. Range from -64~+63.5. */
 732         u8      adc_pwdb_X[4];
 733         u8      sq_rpt;
 734         u8      cck_agc_rpt;
 735 }phy_sts_cck_819xpci_t;
 736
 737 typedef struct _phy_ofdm_rx_status_rxsc_sgien_exintfflag{
 738         u8                      reserved:4;
 739         u8                      rxsc:2;
 740         u8                      sgi_en:1;
 741         u8                      ex_intf_flag:1;
 742 }phy_ofdm_rx_status_rxsc_sgien_exintfflag;
 743
 744 typedef enum _RT_OP_MODE{
 745         RT_OP_MODE_AP,
 746         RT_OP_MODE_INFRASTRUCTURE,
 747         RT_OP_MODE_IBSS,
 748         RT_OP_MODE_NO_LINK,
 749 }RT_OP_MODE, *PRT_OP_MODE;
 750
 751
 752 /* 2007/11/02 MH Define RF mode temporarily for test. */
 753 typedef enum tag_Rf_OpType
 754 {
 755     RF_OP_By_SW_3wire = 0,
 756     RF_OP_By_FW,
 757     RF_OP_MAX
 758 }RF_OpType_E;
 759
 760 typedef enum _RESET_TYPE {
 761         RESET_TYPE_NORESET = 0x00,
 762         RESET_TYPE_NORMAL = 0x01,
 763         RESET_TYPE_SILENT = 0x02
 764 } RESET_TYPE;
 765
 766 typedef struct _tx_ring{
 767         u32 * desc;
 768         u8 nStuckCount;
 769         struct _tx_ring * next;
 770 }__attribute__ ((packed)) tx_ring, * ptx_ring;
 771
 772 struct rtl8192_tx_ring {
 773     tx_desc_819x_pci *desc;
 774     dma_addr_t dma;
 775     unsigned int idx;
 776     unsigned int entries;
 777     struct sk_buff_head queue;
 778 };
 779
 780 #define NIC_SEND_HANG_THRESHOLD_NORMAL          4
 781 #define NIC_SEND_HANG_THRESHOLD_POWERSAVE       8
 782 #define MAX_TX_QUEUE                            9       // BK, BE, VI, VO, HCCA, MANAGEMENT, COMMAND, HIGH, BEACON.
 783
 784 #define MAX_RX_COUNT                            64
 785 #define MAX_TX_QUEUE_COUNT                      9
 786
 787 typedef struct r8192_priv
 788 {
 789         struct pci_dev *pdev;
 790         /* maintain info from eeprom */
 791         short epromtype;
 792         u16 eeprom_vid;
 793         u16 eeprom_did;
 794         u8  eeprom_CustomerID;
 795         u16  eeprom_ChannelPlan;
 796         RT_CUSTOMER_ID CustomerID;
 797         LED_STRATEGY_8190       LedStrategy;
 798         u8      IC_Cut;
 799         int irq;
 800         struct ieee80211_device *ieee80211;
 801 #ifdef ENABLE_LPS
 802         bool ps_force;
 803         bool force_lps;
 804         bool bdisable_nic;
 805 #endif
 806         bool being_init_adapter;
 807         u8 Rf_Mode;
 808         u8 card_8192_version; /* if TCR reports card V B/C this discriminates */
 809         spinlock_t irq_th_lock;
 810         spinlock_t rf_ps_lock;
 811         struct mutex mutex;
 812
 813         short chan;
 814         short sens;
 815         /* RX stuff */
 816         rx_desc_819x_pci *rx_ring;
 817         dma_addr_t rx_ring_dma;
 818         unsigned int rx_idx;
 819         struct sk_buff *rx_buf[MAX_RX_COUNT];
 820         int rxringcount;
 821         u16 rxbuffersize;
 822
 823         struct sk_buff *rx_skb;
 824         u32 *rxring;
 825         u32 *rxringtail;
 826         dma_addr_t rxringdma;
 827         struct buffer *rxbuffer;
 828         struct buffer *rxbufferhead;
 829         short rx_skb_complete;
 830         /* TX stuff */
 831         struct rtl8192_tx_ring tx_ring[MAX_TX_QUEUE_COUNT];
 832         int txringcount;
 833
 834         struct tasklet_struct irq_rx_tasklet;
 835         struct tasklet_struct irq_tx_tasklet;
 836         struct tasklet_struct irq_prepare_beacon_tasklet;
 837
 838         short up;
 839         short crcmon; //if 1 allow bad crc frame reception in monitor mode
 840         struct semaphore wx_sem;
 841         struct semaphore rf_sem; //used to lock rf write operation added by wb, modified by david
 842         u8 rf_type; /* 0 means 1T2R, 1 means 2T4R */
 843
 844         short (*rf_set_sens)(struct net_device *dev,short sens);
 845         u8 (*rf_set_chan)(struct net_device *dev,u8 ch);
 846         void (*rf_close)(struct net_device *dev);
 847         void (*rf_init)(struct net_device *dev);
 848         short promisc;
 849         /* stats */
 850         struct Stats stats;
 851         struct iw_statistics wstats;
 852         struct proc_dir_entry *dir_dev;
 853         struct ieee80211_rx_stats previous_stats;
 854
 855         /* RX stuff */
 856         struct sk_buff_head skb_queue;
 857         struct work_struct qos_activate;
 858
 859         //2 Tx Related variables
 860         u16     ShortRetryLimit;
 861         u16     LongRetryLimit;
 862
 863         u32     LastRxDescTSFHigh;
 864         u32     LastRxDescTSFLow;
 865
 866
 867         //2 Rx Related variables
 868         u32     ReceiveConfig;
 869
 870         u8 retry_data;
 871         u8 retry_rts;
 872
 873         struct work_struct reset_wq;
 874         u8      rx_chk_cnt;
 875
 876 //for rtl819xPci
 877         // Data Rate Config. Added by Annie, 2006-04-13.
 878         u16     basic_rate;
 879         u8      short_preamble;
 880         u8      slot_time;
 881         u16 SifsTime;
 882 /* WirelessMode*/
 883         u8 RegWirelessMode;
 884 /*Firmware*/
 885         prt_firmware            pFirmware;
 886         rtl819x_loopback_e      LoopbackMode;
 887         bool AutoloadFailFlag;
 888         u16 EEPROMAntPwDiff;            // Antenna gain offset from B/C/D to A
 889         u8 EEPROMThermalMeter;
 890         u8 EEPROMCrystalCap;
 891         u8 EEPROMTxPowerLevelCCK[14];// CCK channel 1~14
 892         // The following definition is for eeprom 93c56
 893         u8 EEPROMRfACCKChnl1TxPwLevel[3];       //RF-A CCK Tx Power Level at channel 7
 894         u8 EEPROMRfAOfdmChnlTxPwLevel[3];//RF-A CCK Tx Power Level at [0],[1],[2] = channel 1,7,13
 895         u8 EEPROMRfCCCKChnl1TxPwLevel[3];       //RF-C CCK Tx Power Level at channel 7
 896         u8 EEPROMRfCOfdmChnlTxPwLevel[3];//RF-C CCK Tx Power Level at [0],[1],[2] = channel 1,7,13
 897         u8 EEPROMTxPowerLevelOFDM24G[14]; // OFDM 2.4G channel 1~14
 898         u8 EEPROMLegacyHTTxPowerDiff;   // Legacy to HT rate power diff
 899         bool bTXPowerDataReadFromEEPORM;
 900 /*channel plan*/
 901         u16 RegChannelPlan; // Channel Plan specifed by user, 15: following setting of EEPROM, 0-14: default channel plan index specified by user.
 902         u16 ChannelPlan;
 903 /*PS related*/
 904         // Rf off action for power save
 905         u8      bHwRfOffAction; //0:No action, 1:By GPIO, 2:By Disable
 906 /*PHY related*/
 907         BB_REGISTER_DEFINITION_T        PHYRegDef[4];   //Radio A/B/C/D
 908         // Read/write are allow for following hardware information variables
 909         u32     MCSTxPowerLevelOriginalOffset[6];
 910         u32     CCKTxPowerLevelOriginalOffset;
 911         u8      TxPowerLevelCCK[14];                    // CCK channel 1~14
 912         u8      TxPowerLevelCCK_A[14];                  // RF-A, CCK channel 1~14
 913         u8      TxPowerLevelCCK_C[14];
 914         u8      TxPowerLevelOFDM24G[14];                // OFDM 2.4G channel 1~14
 915         u8      TxPowerLevelOFDM5G[14];                 // OFDM 5G
 916         u8      TxPowerLevelOFDM24G_A[14];      // RF-A, OFDM 2.4G channel 1~14
 917         u8      TxPowerLevelOFDM24G_C[14];      // RF-C, OFDM 2.4G channel 1~14
 918         u8      LegacyHTTxPowerDiff;                    // Legacy to HT rate power diff
 919         u8      TxPowerDiff;
 920         char    RF_C_TxPwDiff;                                  // Antenna gain offset, rf-c to rf-a
 921         u8      AntennaTxPwDiff[3];                             // Antenna gain offset, index 0 for B, 1 for C, and 2 for D
 922         u8      CrystalCap;                                             // CrystalCap.
 923         u8      ThermalMeter[2];                                // ThermalMeter, index 0 for RFIC0, and 1 for RFIC1
 924         //05/27/2008 cck power enlarge
 925         u8      CckPwEnl;
 926         u16     TSSI_13dBm;
 927         u32     Pwr_Track;
 928         u8                              CCKPresentAttentuation_20Mdefault;
 929         u8                              CCKPresentAttentuation_40Mdefault;
 930         char                            CCKPresentAttentuation_difference;
 931         char                            CCKPresentAttentuation;
 932         // Use to calculate PWBD.
 933         RT_RF_POWER_STATE               eRFPowerState;
 934         u8      bCckHighPower;
 935         long    undecorated_smoothed_pwdb;
 936         long    undecorated_smoothed_cck_adc_pwdb[4];
 937         //for set channel
 938         u8      SwChnlInProgress;
 939         u8      SwChnlStage;
 940         u8      SwChnlStep;
 941         u8      SetBWModeInProgress;
 942         HT_CHANNEL_WIDTH                CurrentChannelBW;
 943
 944         // 8190 40MHz mode
 945         //
 946         u8      nCur40MhzPrimeSC;       // Control channel sub-carrier
 947         // Joseph test for shorten RF configuration time.
 948         // We save RF reg0 in this variable to reduce RF reading.
 949         //
 950         u32                                     RfReg0Value[4];
 951         u8                                      NumTotalRFPath;
 952         bool                            brfpath_rxenable[4];
 953 //+by amy 080507
 954         struct timer_list watch_dog_timer;
 955         u8 watchdog_last_time;
 956         u8 watchdog_check_reset_cnt;
 957
 958 //+by amy 080515 for dynamic mechenism
 959         //Add by amy Tx Power Control for Near/Far Range 2008/05/15
 960         bool    bdynamic_txpower;  //bDynamicTxPower
 961         bool    bDynamicTxHighPower;  // Tx high power state
 962         bool    bDynamicTxLowPower;  // Tx low power state
 963         bool    bLastDTPFlag_High;
 964         bool    bLastDTPFlag_Low;
 965
 966         /* OFDM RSSI. For high power or not */
 967         u8      phy_check_reg824;
 968         u32     phy_reg824_bit9;
 969
 970         //Add by amy for Rate Adaptive
 971         rate_adaptive rate_adaptive;
 972         //Add by amy for TX power tracking
 973         //2008/05/15  Mars OPEN/CLOSE TX POWER TRACKING
 974         const txbbgain_struct * txbbgain_table;
 975         u8                         txpower_count;//For 6 sec do tracking again
 976         bool                       btxpower_trackingInit;
 977         u8                         OFDM_index;
 978         u8                         CCK_index;
 979         u8                         Record_CCK_20Mindex;
 980         u8                         Record_CCK_40Mindex;
 981         //2007/09/10 Mars Add CCK TX Power Tracking
 982         const ccktxbbgain_struct *cck_txbbgain_table;
 983         const ccktxbbgain_struct *cck_txbbgain_ch14_table;
 984         u8 rfa_txpowertrackingindex;
 985         u8 rfa_txpowertrackingindex_real;
 986         u8 rfa_txpowertracking_default;
 987         u8 rfc_txpowertrackingindex;
 988         u8 rfc_txpowertrackingindex_real;
 989         u8 rfc_txpowertracking_default;
 990         bool btxpower_tracking;
 991         bool bcck_in_ch14;
 992
 993         //For Backup Initial Gain
 994         init_gain initgain_backup;
 995         u8              DefaultInitialGain[4];
 996         // For EDCA Turbo mode, Added by amy 080515.
 997         bool            bis_any_nonbepkts;
 998         bool            bcurrent_turbo_EDCA;
 999
1000         bool            bis_cur_rdlstate;
1001         struct timer_list fsync_timer;
1002         u32     rate_record;
1003         u32     rateCountDiffRecord;
1004         u32     ContiuneDiffCount;
1005         bool bswitch_fsync;
1006
1007         u8      framesync;
1008         u32     framesyncC34;
1009         u8      framesyncMonitor;
1010
1011         //by amy for gpio
1012         bool bHwRadioOff;
1013         //by amy for ps
1014         RT_OP_MODE OpMode;
1015         //by amy for reset_count
1016         u32 reset_count;
1017
1018         //by amy for silent reset
1019         RESET_TYPE      ResetProgress;
1020         bool            bForcedSilentReset;
1021         bool            bDisableNormalResetCheck;
1022         u16             TxCounter;
1023         u16             RxCounter;
1024         int             IrpPendingCount;
1025         bool            bResetInProgress;
1026         bool            force_reset;
1027         u8              InitialGainOperateType;
1028
1029         //define work item by amy 080526
1030         struct delayed_work update_beacon_wq;
1031         struct delayed_work watch_dog_wq;
1032         struct delayed_work txpower_tracking_wq;
1033         struct delayed_work rfpath_check_wq;
1034         struct delayed_work gpio_change_rf_wq;
1035         struct delayed_work initialgain_operate_wq;
1036         struct workqueue_struct *priv_wq;
1037 }r8192_priv;
1038
1039 bool init_firmware(struct net_device *dev);
1040 u32 read_cam(struct r8192_priv *priv, u8 addr);
1041 void write_cam(struct r8192_priv *priv, u8 addr, u32 data);
1042 u8 read_nic_byte(struct r8192_priv *priv, int x);
1043 u32 read_nic_dword(struct r8192_priv *priv, int x);
1044 u16 read_nic_word(struct r8192_priv *priv, int x) ;
1045 void write_nic_byte(struct r8192_priv *priv, int x,u8 y);
1046 void write_nic_word(struct r8192_priv *priv, int x,u16 y);
1047 void write_nic_dword(struct r8192_priv *priv, int x,u32 y);
1048
1049 int rtl8192_down(struct net_device *dev);
1050 int rtl8192_up(struct net_device *dev);
1051 void rtl8192_commit(struct net_device *dev);
1052 void write_phy(struct net_device *dev, u8 adr, u8 data);
1053 void CamResetAllEntry(struct net_device* dev);
1054 void EnableHWSecurityConfig8192(struct net_device *dev);
1055 void setKey(struct net_device *dev, u8 EntryNo, u8 KeyIndex, u16 KeyType, const u8 *MacAddr, u8 DefaultKey, u32 *KeyContent );
1056 void dm_cck_txpower_adjust(struct net_device *dev, bool binch14);
1057 void firmware_init_param(struct net_device *dev);
1058 RT_STATUS cmpk_message_handle_tx(struct net_device *dev, u8* codevirtualaddress, u32 packettype, u32 buffer_len);
1059
1060 #ifdef ENABLE_IPS
1061 void IPSEnter(struct net_device *dev);
1062 void IPSLeave(struct net_device *dev);
1063 void InactivePsWorkItemCallback(struct net_device *dev);
1064 void IPSLeave_wq(struct work_struct *work);
1065 void ieee80211_ips_leave_wq(struct net_device *dev);
1066 void ieee80211_ips_leave(struct net_device *dev);
1067 #endif
1068 #ifdef ENABLE_LPS
1069 void LeisurePSEnter(struct net_device *dev);
1070 void LeisurePSLeave(struct net_device *dev);
1071 #endif
1072
1073 bool NicIFEnableNIC(struct net_device* dev);
1074 bool NicIFDisableNIC(struct net_device* dev);
1075
1076 void PHY_SetRtl8192eRfOff(struct net_device* dev);
1077 #endif