2 *************************************************************************
4 * 5F., No.36, Taiyuan St., Jhubei City,
8 * (c) Copyright 2002-2007, Ralink Technology, Inc.
10 * This program is free software; you can redistribute it and/or modify *
11 * it under the terms of the GNU General Public License as published by *
12 * the Free Software Foundation; either version 2 of the License, or *
13 * (at your option) any later version. *
15 * This program is distributed in the hope that it will be useful, *
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
18 * GNU General Public License for more details. *
20 * You should have received a copy of the GNU General Public License *
21 * along with this program; if not, write to the *
22 * Free Software Foundation, Inc., *
23 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 *************************************************************************
31 RT28xx ASIC related definition & structures
35 -------- ---------- ----------------------------------------------
36 Jan Lee Jan-3-2006 created for RT2860c
44 // PCI registers - base address 0x0000
46 #define PCI_CFG 0x0000
47 #define PCI_EECTRL 0x0004
48 #define PCI_MCUCTRL 0x0008
51 // SCH/DMA registers - base address 0x0200
53 // INT_SOURCE_CSR: Interrupt source register. Write one to clear corresponding bit
55 #define DMA_CSR0 0x200
56 #define INT_SOURCE_CSR 0x200
57 typedef union _INT_SOURCE_CSR_STRUC {
62 UINT32 Ac0DmaDone:1;//4
66 UINT32 HccaDmaDone:1; // bit7
68 UINT32 MCUCommandINT:1;//bit 9
69 UINT32 RxTxCoherent:1;
72 UINT32 TXFifoStatusInt:1;//FIFO Statistics is full, sw should read 0x171c
73 UINT32 AutoWakeup:1;//bit14
75 UINT32 RxCoherent:1;//bit16
80 } INT_SOURCE_CSR_STRUC, *PINT_SOURCE_CSR_STRUC;
83 // INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF
85 #define INT_MASK_CSR 0x204
86 typedef union _INT_MASK_CSR_STRUC {
88 UINT32 RXDelay_INT_MSK:1;
97 UINT32 MCUCommandINT:1;
103 } INT_MASK_CSR_STRUC, *PINT_MASK_CSR_STRUC;
105 #define WPDMA_GLO_CFG 0x208
106 typedef union _WPDMA_GLO_CFG_STRUC {
108 UINT32 EnableTxDMA:1;
110 UINT32 EnableRxDMA:1;
112 UINT32 WPDMABurstSIZE:2;
113 UINT32 EnTXWriteBackDDONE:1;
115 UINT32 RXHdrScater:8;
116 UINT32 HDR_SEG_LEN:16;
119 } WPDMA_GLO_CFG_STRUC, *PWPDMA_GLO_CFG_STRUC;
121 #define WPDMA_RST_IDX 0x20c
122 typedef union _WPDMA_RST_IDX_STRUC {
124 UINT32 RST_DTX_IDX0:1;
125 UINT32 RST_DTX_IDX1:1;
126 UINT32 RST_DTX_IDX2:1;
127 UINT32 RST_DTX_IDX3:1;
128 UINT32 RST_DTX_IDX4:1;
129 UINT32 RST_DTX_IDX5:1;
131 UINT32 RST_DRX_IDX0:1;
135 } WPDMA_RST_IDX_STRUC, *PWPDMA_RST_IDX_STRUC;
137 #define DELAY_INT_CFG 0x0210
138 typedef union _DELAY_INT_CFG_STRUC {
140 UINT32 RXMAX_PTIME:8;
142 UINT32 RXDLY_INT_EN:1;
143 UINT32 TXMAX_PTIME:8;
145 UINT32 TXDLY_INT_EN:1;
148 } DELAY_INT_CFG_STRUC, *PDELAY_INT_CFG_STRUC;
150 #define WMM_AIFSN_CFG 0x0214
151 typedef union _AIFSN_CSR_STRUC {
153 UINT32 Aifsn0:4; // for AC_BE
154 UINT32 Aifsn1:4; // for AC_BK
155 UINT32 Aifsn2:4; // for AC_VI
156 UINT32 Aifsn3:4; // for AC_VO
160 } AIFSN_CSR_STRUC, *PAIFSN_CSR_STRUC;
163 // CWMIN_CSR: CWmin for each EDCA AC
165 #define WMM_CWMIN_CFG 0x0218
166 typedef union _CWMIN_CSR_STRUC {
168 UINT32 Cwmin0:4; // for AC_BE
169 UINT32 Cwmin1:4; // for AC_BK
170 UINT32 Cwmin2:4; // for AC_VI
171 UINT32 Cwmin3:4; // for AC_VO
175 } CWMIN_CSR_STRUC, *PCWMIN_CSR_STRUC;
178 // CWMAX_CSR: CWmin for each EDCA AC
180 #define WMM_CWMAX_CFG 0x021c
181 typedef union _CWMAX_CSR_STRUC {
183 UINT32 Cwmax0:4; // for AC_BE
184 UINT32 Cwmax1:4; // for AC_BK
185 UINT32 Cwmax2:4; // for AC_VI
186 UINT32 Cwmax3:4; // for AC_VO
190 } CWMAX_CSR_STRUC, *PCWMAX_CSR_STRUC;
193 // AC_TXOP_CSR0: AC_BK/AC_BE TXOP register
195 #define WMM_TXOP0_CFG 0x0220
196 typedef union _AC_TXOP_CSR0_STRUC {
198 USHORT Ac0Txop; // for AC_BK, in unit of 32us
199 USHORT Ac1Txop; // for AC_BE, in unit of 32us
202 } AC_TXOP_CSR0_STRUC, *PAC_TXOP_CSR0_STRUC;
205 // AC_TXOP_CSR1: AC_VO/AC_VI TXOP register
207 #define WMM_TXOP1_CFG 0x0224
208 typedef union _AC_TXOP_CSR1_STRUC {
210 USHORT Ac2Txop; // for AC_VI, in unit of 32us
211 USHORT Ac3Txop; // for AC_VO, in unit of 32us
214 } AC_TXOP_CSR1_STRUC, *PAC_TXOP_CSR1_STRUC;
216 #define RINGREG_DIFF 0x10
217 #define GPIO_CTRL_CFG 0x0228 //MAC_CSR13
218 #define MCU_CMD_CFG 0x022c
219 #define TX_BASE_PTR0 0x0230 //AC_BK base address
220 #define TX_MAX_CNT0 0x0234
221 #define TX_CTX_IDX0 0x0238
222 #define TX_DTX_IDX0 0x023c
223 #define TX_BASE_PTR1 0x0240 //AC_BE base address
224 #define TX_MAX_CNT1 0x0244
225 #define TX_CTX_IDX1 0x0248
226 #define TX_DTX_IDX1 0x024c
227 #define TX_BASE_PTR2 0x0250 //AC_VI base address
228 #define TX_MAX_CNT2 0x0254
229 #define TX_CTX_IDX2 0x0258
230 #define TX_DTX_IDX2 0x025c
231 #define TX_BASE_PTR3 0x0260 //AC_VO base address
232 #define TX_MAX_CNT3 0x0264
233 #define TX_CTX_IDX3 0x0268
234 #define TX_DTX_IDX3 0x026c
235 #define TX_BASE_PTR4 0x0270 //HCCA base address
236 #define TX_MAX_CNT4 0x0274
237 #define TX_CTX_IDX4 0x0278
238 #define TX_DTX_IDX4 0x027c
239 #define TX_BASE_PTR5 0x0280 //MGMT base address
240 #define TX_MAX_CNT5 0x0284
241 #define TX_CTX_IDX5 0x0288
242 #define TX_DTX_IDX5 0x028c
243 #define TX_MGMTMAX_CNT TX_MAX_CNT5
244 #define TX_MGMTCTX_IDX TX_CTX_IDX5
245 #define TX_MGMTDTX_IDX TX_DTX_IDX5
246 #define RX_BASE_PTR 0x0290 //RX base address
247 #define RX_MAX_CNT 0x0294
248 #define RX_CRX_IDX 0x0298
249 #define RX_DRX_IDX 0x029c
250 #define USB_DMA_CFG 0x02a0
252 typedef union _USB_DMA_CFG_STRUC {
254 UINT32 RxBulkAggTOut:8; //Rx Bulk Aggregation TimeOut in unit of 33ns
255 UINT32 RxBulkAggLmt:8; //Rx Bulk Aggregation Limit in unit of 256 bytes
256 UINT32 phyclear:1; //phy watch dog enable. write 1
258 UINT32 TxClear:1; //Clear USB DMA TX path
259 UINT32 TxopHalt:1; //Halt TXOP count down when TX buffer is full.
260 UINT32 RxBulkAggEn:1; //Enable Rx Bulk Aggregation
261 UINT32 RxBulkEn:1; //Enable USB DMA Rx
262 UINT32 TxBulkEn:1; //Enable USB DMA Tx
263 UINT32 EpoutValid:6; //OUT endpoint data valid
264 UINT32 RxBusy:1; //USB DMA RX FSM busy
265 UINT32 TxBusy:1; //USB DMA TX FSM busy
268 } USB_DMA_CFG_STRUC, *PUSB_DMA_CFG_STRUC;
274 // Most are for debug. Driver doesn't touch PBF register.
275 #define PBF_SYS_CTRL 0x0400
276 #define PBF_CFG 0x0408
277 #define PBF_MAX_PCNT 0x040C
278 #define PBF_CTRL 0x0410
279 #define PBF_INT_STA 0x0414
280 #define PBF_INT_ENA 0x0418
281 #define TXRXQ_PCNT 0x0438
282 #define PBF_DBG 0x043c
283 #define PBF_CAP_CTRL 0x0440
289 // 4.1 MAC SYSTEM configuration registers (offset:0x1000)
291 #define MAC_CSR0 0x1000
292 typedef union _ASIC_VER_ID_STRUC {
294 USHORT ASICRev; // reversion : 0
295 USHORT ASICVer; // version : 2860
298 } ASIC_VER_ID_STRUC, *PASIC_VER_ID_STRUC;
300 #define MAC_SYS_CTRL 0x1004 //MAC_CSR1
301 #define MAC_ADDR_DW0 0x1008 // MAC ADDR DW0
302 #define MAC_ADDR_DW1 0x100c // MAC ADDR DW1
304 // MAC_CSR2: STA MAC register 0
306 typedef union _MAC_DW0_STRUC {
308 UCHAR Byte0; // MAC address byte 0
309 UCHAR Byte1; // MAC address byte 1
310 UCHAR Byte2; // MAC address byte 2
311 UCHAR Byte3; // MAC address byte 3
314 } MAC_DW0_STRUC, *PMAC_DW0_STRUC;
317 // MAC_CSR3: STA MAC register 1
319 typedef union _MAC_DW1_STRUC {
321 UCHAR Byte4; // MAC address byte 4
322 UCHAR Byte5; // MAC address byte 5
327 } MAC_DW1_STRUC, *PMAC_DW1_STRUC;
329 #define MAC_BSSID_DW0 0x1010 // MAC BSSID DW0
330 #define MAC_BSSID_DW1 0x1014 // MAC BSSID DW1
333 // MAC_CSR5: BSSID register 1
335 typedef union _MAC_CSR5_STRUC {
337 UCHAR Byte4; // BSSID byte 4
338 UCHAR Byte5; // BSSID byte 5
339 USHORT BssIdMask:2; // 0: one BSSID, 10: 4 BSSID, 01: 2 BSSID , 11: 8BSSID
344 } MAC_CSR5_STRUC, *PMAC_CSR5_STRUC;
346 #define MAX_LEN_CFG 0x1018 // rt2860b max 16k bytes. bit12:13 Maximum PSDU length (power factor) 0:2^13, 1:2^14, 2:2^15, 3:2^16
347 #define BBP_CSR_CFG 0x101c //
349 // BBP_CSR_CFG: BBP serial control register
351 typedef union _BBP_CSR_CFG_STRUC {
353 UINT32 Value:8; // Register value to program into BBP
354 UINT32 RegNum:8; // Selected BBP register
355 UINT32 fRead:1; // 0: Write BBP, 1: Read BBP
356 UINT32 Busy:1; // 1: ASIC is busy execute BBP programming.
357 UINT32 BBP_PAR_DUR:1; // 0: 4 MAC clock cycles 1: 8 MAC clock cycles
358 UINT32 BBP_RW_MODE:1; // 0: use serial mode 1:parallel
362 } BBP_CSR_CFG_STRUC, *PBBP_CSR_CFG_STRUC;
364 #define RF_CSR_CFG0 0x1020
366 // RF_CSR_CFG: RF control register
368 typedef union _RF_CSR_CFG0_STRUC {
370 UINT32 RegIdAndContent:24; // Register value to program into BBP
371 UINT32 bitwidth:5; // Selected BBP register
372 UINT32 StandbyMode:1; // 0: high when stand by 1: low when standby
373 UINT32 Sel:1; // 0:RF_LE0 activate 1:RF_LE1 activate
374 UINT32 Busy:1; // 0: idle 1: 8busy
377 } RF_CSR_CFG0_STRUC, *PRF_CSR_CFG0_STRUC;
379 #define RF_CSR_CFG1 0x1024
380 typedef union _RF_CSR_CFG1_STRUC {
382 UINT32 RegIdAndContent:24; // Register value to program into BBP
383 UINT32 RFGap:5; // Gap between BB_CONTROL_RF and RF_LE. 0: 3 system clock cycle (37.5usec) 1: 5 system clock cycle (62.5usec)
384 UINT32 rsv:7; // 0: idle 1: 8busy
387 } RF_CSR_CFG1_STRUC, *PRF_CSR_CFG1_STRUC;
389 #define RF_CSR_CFG2 0x1028 //
390 typedef union _RF_CSR_CFG2_STRUC {
392 UINT32 RegIdAndContent:24; // Register value to program into BBP
393 UINT32 rsv:8; // 0: idle 1: 8busy
396 } RF_CSR_CFG2_STRUC, *PRF_CSR_CFG2_STRUC;
398 #define LED_CFG 0x102c // MAC_CSR14
399 typedef union _LED_CFG_STRUC {
401 UINT32 OnPeriod:8; // blinking on period unit 1ms
402 UINT32 OffPeriod:8; // blinking off period unit 1ms
403 UINT32 SlowBlinkPeriod:6; // slow blinking period. unit:1ms
405 UINT32 RLedMode:2; // red Led Mode 0: off1: blinking upon TX2: periodic slow blinking3: always on
406 UINT32 GLedMode:2; // green Led Mode
407 UINT32 YLedMode:2; // yellow Led Mode
408 UINT32 LedPolar:1; // Led Polarity. 0: active low1: active high
412 } LED_CFG_STRUC, *PLED_CFG_STRUC;
415 // 4.2 MAC TIMING configuration registers (offset:0x1100)
417 #define XIFS_TIME_CFG 0x1100 // MAC_CSR8 MAC_CSR9
418 typedef union _IFS_SLOT_CFG_STRUC {
420 UINT32 CckmSifsTime:8; // unit 1us. Applied after CCK RX/TX
421 UINT32 OfdmSifsTime:8; // unit 1us. Applied after OFDM RX/TX
422 UINT32 OfdmXifsTime:4; //OFDM SIFS. unit 1us. Applied after OFDM RX when MAC doesn't reference BBP signal BBRXEND
423 UINT32 EIFS:9; // unit 1us
424 UINT32 BBRxendEnable:1; // reference RXEND signal to begin XIFS defer
428 } IFS_SLOT_CFG_STRUC, *PIFS_SLOT_CFG_STRUC;
430 #define BKOFF_SLOT_CFG 0x1104 // mac_csr9 last 8 bits
431 #define NAV_TIME_CFG 0x1108 // NAV (MAC_CSR15)
432 #define CH_TIME_CFG 0x110C // Count as channel busy
433 #define PBF_LIFE_TIMER 0x1110 //TX/RX MPDU timestamp timer (free run)Unit: 1us
434 #define BCN_TIME_CFG 0x1114 // TXRX_CSR9
436 #define BCN_OFFSET0 0x042C
437 #define BCN_OFFSET1 0x0430
440 // BCN_TIME_CFG : Synchronization control register
442 typedef union _BCN_TIME_CFG_STRUC {
444 UINT32 BeaconInterval:16; // in unit of 1/16 TU
445 UINT32 bTsfTicking:1; // Enable TSF auto counting
446 UINT32 TsfSyncMode:2; // Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode
447 UINT32 bTBTTEnable:1;
448 UINT32 bBeaconGen:1; // Enable beacon generator
450 UINT32 TxTimestampCompensate:8;
453 } BCN_TIME_CFG_STRUC, *PBCN_TIME_CFG_STRUC;
455 #define TBTT_SYNC_CFG 0x1118 // txrx_csr10
456 #define TSF_TIMER_DW0 0x111C // Local TSF timer lsb 32 bits. Read-only
457 #define TSF_TIMER_DW1 0x1120 // msb 32 bits. Read-only.
458 #define TBTT_TIMER 0x1124 // TImer remains till next TBTT. Read-only. TXRX_CSR14
459 #define INT_TIMER_CFG 0x1128 //
460 #define INT_TIMER_EN 0x112c // GP-timer and pre-tbtt Int enable
461 #define CH_IDLE_STA 0x1130 // channel idle time
462 #define CH_BUSY_STA 0x1134 // channle busy time
464 // 4.2 MAC POWER configuration registers (offset:0x1200)
466 #define MAC_STATUS_CFG 0x1200 // old MAC_CSR12
467 #define PWR_PIN_CFG 0x1204 // old MAC_CSR12
468 #define AUTO_WAKEUP_CFG 0x1208 // old MAC_CSR10
470 // AUTO_WAKEUP_CFG: Manual power control / status register
472 typedef union _AUTO_WAKEUP_STRUC {
474 UINT32 AutoLeadTime:8;
475 UINT32 NumofSleepingTbtt:7; // ForceWake has high privilege than PutToSleep when both set
476 UINT32 EnableAutoWakeup:1; // 0:sleep, 1:awake
480 } AUTO_WAKEUP_STRUC, *PAUTO_WAKEUP_STRUC;
483 // 4.3 MAC TX configuration registers (offset:0x1300)
486 #define EDCA_AC0_CFG 0x1300 //AC_TXOP_CSR0 0x3474
487 #define EDCA_AC1_CFG 0x1304
488 #define EDCA_AC2_CFG 0x1308
489 #define EDCA_AC3_CFG 0x130c
490 typedef union _EDCA_AC_CFG_STRUC {
492 UINT32 AcTxop:8; // in unit of 32us
493 UINT32 Aifsn:4; // # of slot time
495 UINT32 Cwmax:4; //unit power of 2
499 } EDCA_AC_CFG_STRUC, *PEDCA_AC_CFG_STRUC;
501 #define EDCA_TID_AC_MAP 0x1310
502 #define TX_PWR_CFG_0 0x1314
503 #define TX_PWR_CFG_1 0x1318
504 #define TX_PWR_CFG_2 0x131C
505 #define TX_PWR_CFG_3 0x1320
506 #define TX_PWR_CFG_4 0x1324
507 #define TX_PIN_CFG 0x1328
508 #define TX_BAND_CFG 0x132c // 0x1 use upper 20MHz. 0 juse lower 20MHz
509 #define TX_SW_CFG0 0x1330
510 #define TX_SW_CFG1 0x1334
511 #define TX_SW_CFG2 0x1338
512 #define TXOP_THRES_CFG 0x133c
513 #define TXOP_CTRL_CFG 0x1340
514 #define TX_RTS_CFG 0x1344
516 typedef union _TX_RTS_CFG_STRUC {
518 UINT32 AutoRtsRetryLimit:8;
519 UINT32 RtsThres:16; // unit:byte
520 UINT32 RtsFbkEn:1; // enable rts rate fallback
521 UINT32 rsv:7; // 1: HT non-STBC control frame enable
524 } TX_RTS_CFG_STRUC, *PTX_RTS_CFG_STRUC;
526 #define TX_TIMEOUT_CFG 0x1348
527 typedef union _TX_TIMEOUT_CFG_STRUC {
530 UINT32 MpduLifeTime:4; // expiration time = 2^(9+MPDU LIFE TIME) us
531 UINT32 RxAckTimeout:8; // unit:slot. Used for TX precedure
532 UINT32 TxopTimeout:8; //TXOP timeout value for TXOP truncation. It is recommended that (SLOT_TIME) > (TX_OP_TIMEOUT) > (RX_ACK_TIMEOUT)
533 UINT32 rsv2:8; // 1: HT non-STBC control frame enable
536 } TX_TIMEOUT_CFG_STRUC, *PTX_TIMEOUT_CFG_STRUC;
538 #define TX_RTY_CFG 0x134c
539 typedef union PACKED _TX_RTY_CFG_STRUC {
541 UINT32 ShortRtyLimit:8; // short retry limit
542 UINT32 LongRtyLimit:8; //long retry limit
543 UINT32 LongRtyThre:12; // Long retry threshoold
544 UINT32 NonAggRtyMode:1; // Non-Aggregate MPDU retry mode. 0:expired by retry limit, 1: expired by mpdu life timer
545 UINT32 AggRtyMode:1; // Aggregate MPDU retry mode. 0:expired by retry limit, 1: expired by mpdu life timer
546 UINT32 TxautoFBEnable:1; // Tx retry PHY rate auto fallback enable
547 UINT32 rsv:1; // 1: HT non-STBC control frame enable
550 } TX_RTY_CFG_STRUC, *PTX_RTY_CFG_STRUC;
552 #define TX_LINK_CFG 0x1350
553 typedef union PACKED _TX_LINK_CFG_STRUC {
555 UINT32 RemoteMFBLifeTime:8; //remote MFB life time. unit : 32us
556 UINT32 MFBEnable:1; // TX apply remote MFB 1:enable
557 UINT32 RemoteUMFSEnable:1; // remote unsolicit MFB enable. 0: not apply remote remote unsolicit (MFS=7)
558 UINT32 TxMRQEn:1; // MCS request TX enable
559 UINT32 TxRDGEn:1; // RDG TX enable
560 UINT32 TxCFAckEn:1; // Piggyback CF-ACK enable
562 UINT32 RemotMFB:8; // remote MCS feedback
563 UINT32 RemotMFS:8; //remote MCS feedback sequence number
566 } TX_LINK_CFG_STRUC, *PTX_LINK_CFG_STRUC;
568 #define HT_FBK_CFG0 0x1354
569 typedef union PACKED _HT_FBK_CFG0_STRUC {
581 } HT_FBK_CFG0_STRUC, *PHT_FBK_CFG0_STRUC;
583 #define HT_FBK_CFG1 0x1358
584 typedef union _HT_FBK_CFG1_STRUC {
596 } HT_FBK_CFG1_STRUC, *PHT_FBK_CFG1_STRUC;
598 #define LG_FBK_CFG0 0x135c
599 typedef union _LG_FBK_CFG0_STRUC {
601 UINT32 OFDMMCS0FBK:4; //initial value is 0
602 UINT32 OFDMMCS1FBK:4; //initial value is 0
603 UINT32 OFDMMCS2FBK:4; //initial value is 1
604 UINT32 OFDMMCS3FBK:4; //initial value is 2
605 UINT32 OFDMMCS4FBK:4; //initial value is 3
606 UINT32 OFDMMCS5FBK:4; //initial value is 4
607 UINT32 OFDMMCS6FBK:4; //initial value is 5
608 UINT32 OFDMMCS7FBK:4; //initial value is 6
611 } LG_FBK_CFG0_STRUC, *PLG_FBK_CFG0_STRUC;
613 #define LG_FBK_CFG1 0x1360
614 typedef union _LG_FBK_CFG1_STRUC {
616 UINT32 CCKMCS0FBK:4; //initial value is 0
617 UINT32 CCKMCS1FBK:4; //initial value is 0
618 UINT32 CCKMCS2FBK:4; //initial value is 1
619 UINT32 CCKMCS3FBK:4; //initial value is 2
623 } LG_FBK_CFG1_STRUC, *PLG_FBK_CFG1_STRUC;
625 //=======================================================
626 //================ Protection Paramater================================
627 //=======================================================
628 #define CCK_PROT_CFG 0x1364 //CCK Protection
629 #define ASIC_SHORTNAV 1
630 #define ASIC_LONGNAV 2
633 typedef union _PROT_CFG_STRUC {
635 UINT32 ProtectRate:16; //Protection control frame rate for CCK TX(RTS/CTS/CFEnd).
636 UINT32 ProtectCtrl:2; //Protection control frame type for CCK TX. 1:RTS/CTS, 2:CTS-to-self, 0:None, 3:rsv
637 UINT32 ProtectNav:2; //TXOP protection type for CCK TX. 0:None, 1:ShortNAVprotect, 2:LongNAVProtect, 3:rsv
638 UINT32 TxopAllowCck:1; //CCK TXOP allowance.0:disallow.
639 UINT32 TxopAllowOfdm:1; //CCK TXOP allowance.0:disallow.
640 UINT32 TxopAllowMM20:1; //CCK TXOP allowance. 0:disallow.
641 UINT32 TxopAllowMM40:1; //CCK TXOP allowance.0:disallow.
642 UINT32 TxopAllowGF20:1; //CCK TXOP allowance.0:disallow.
643 UINT32 TxopAllowGF40:1; //CCK TXOP allowance.0:disallow.
644 UINT32 RTSThEn:1; //RTS threshold enable on CCK TX
648 } PROT_CFG_STRUC, *PPROT_CFG_STRUC;
650 #define OFDM_PROT_CFG 0x1368 //OFDM Protection
651 #define MM20_PROT_CFG 0x136C //MM20 Protection
652 #define MM40_PROT_CFG 0x1370 //MM40 Protection
653 #define GF20_PROT_CFG 0x1374 //GF20 Protection
654 #define GF40_PROT_CFG 0x1378 //GR40 Protection
655 #define EXP_CTS_TIME 0x137C //
656 #define EXP_ACK_TIME 0x1380 //
659 // 4.4 MAC RX configuration registers (offset:0x1400)
661 #define RX_FILTR_CFG 0x1400 //TXRX_CSR0
662 #define AUTO_RSP_CFG 0x1404 //TXRX_CSR4
664 // TXRX_CSR4: Auto-Responder/
666 typedef union _AUTO_RSP_CFG_STRUC {
668 UINT32 AutoResponderEnable:1;
669 UINT32 BACAckPolicyEnable:1; // 0:long, 1:short preamble
670 UINT32 CTS40MMode:1; // Response CTS 40MHz duplicate mode
671 UINT32 CTS40MRef:1; // Response CTS 40MHz duplicate mode
672 UINT32 AutoResponderPreamble:1; // 0:long, 1:short preamble
673 UINT32 rsv:1; // Power bit value in conrtrol frame
674 UINT32 DualCTSEn:1; // Power bit value in conrtrol frame
675 UINT32 AckCtsPsmBit:1; // Power bit value in conrtrol frame
679 } AUTO_RSP_CFG_STRUC, *PAUTO_RSP_CFG_STRUC;
681 #define LEGACY_BASIC_RATE 0x1408 // TXRX_CSR5 0x3054
682 #define HT_BASIC_RATE 0x140c
683 #define HT_CTRL_CFG 0x1410
684 #define SIFS_COST_CFG 0x1414
685 #define RX_PARSER_CFG 0x1418 //Set NAV for all received frames
688 // 4.5 MAC Security configuration (offset:0x1500)
690 #define TX_SEC_CNT0 0x1500 //
691 #define RX_SEC_CNT0 0x1504 //
692 #define CCMP_FC_MUTE 0x1508 //
694 // 4.6 HCCA/PSMP (offset:0x1600)
696 #define TXOP_HLDR_ADDR0 0x1600
697 #define TXOP_HLDR_ADDR1 0x1604
698 #define TXOP_HLDR_ET 0x1608
699 #define QOS_CFPOLL_RA_DW0 0x160c
700 #define QOS_CFPOLL_A1_DW1 0x1610
701 #define QOS_CFPOLL_QC 0x1614
703 // 4.7 MAC Statistis registers (offset:0x1700)
705 #define RX_STA_CNT0 0x1700 //
706 #define RX_STA_CNT1 0x1704 //
707 #define RX_STA_CNT2 0x1708 //
710 // RX_STA_CNT0_STRUC: RX PLCP error count & RX CRC error count
712 typedef union _RX_STA_CNT0_STRUC {
718 } RX_STA_CNT0_STRUC, *PRX_STA_CNT0_STRUC;
721 // RX_STA_CNT1_STRUC: RX False CCA count & RX LONG frame count
723 typedef union _RX_STA_CNT1_STRUC {
729 } RX_STA_CNT1_STRUC, *PRX_STA_CNT1_STRUC;
732 // RX_STA_CNT2_STRUC:
734 typedef union _RX_STA_CNT2_STRUC {
737 USHORT RxFifoOverflowCount;
740 } RX_STA_CNT2_STRUC, *PRX_STA_CNT2_STRUC;
742 #define TX_STA_CNT0 0x170C //
744 // STA_CSR3: TX Beacon count
746 typedef union _TX_STA_CNT0_STRUC {
749 USHORT TxBeaconCount;
752 } TX_STA_CNT0_STRUC, *PTX_STA_CNT0_STRUC;
754 #define TX_STA_CNT1 0x1710 //
756 // TX_STA_CNT1: TX tx count
758 typedef union _TX_STA_CNT1_STRUC {
764 } TX_STA_CNT1_STRUC, *PTX_STA_CNT1_STRUC;
766 #define TX_STA_CNT2 0x1714 //
768 // TX_STA_CNT2: TX tx count
770 typedef union _TX_STA_CNT2_STRUC {
772 USHORT TxZeroLenCount;
773 USHORT TxUnderFlowCount;
776 } TX_STA_CNT2_STRUC, *PTX_STA_CNT2_STRUC;
778 #define TX_STA_FIFO 0x1718 //
780 // TX_STA_FIFO_STRUC: TX Result for specific PID status fifo register
782 typedef union PACKED _TX_STA_FIFO_STRUC {
784 UINT32 bValid:1; // 1:This register contains a valid TX result
786 UINT32 TxSuccess:1; // Tx No retry success
787 UINT32 TxAggre:1; // Tx Retry Success
788 UINT32 TxAckRequired:1; // Tx fail
789 UINT32 wcid:8; //wireless client index
790 // UINT32 SuccessRate:16; //include MCS, mode ,shortGI, BW settingSame format as TXWI Word 0 Bit 31-16.
791 UINT32 SuccessRate:13; //include MCS, mode ,shortGI, BW settingSame format as TXWI Word 0 Bit 31-16.
796 } TX_STA_FIFO_STRUC, *PTX_STA_FIFO_STRUC;
799 #define TX_AGG_CNT 0x171c
800 typedef union _TX_AGG_CNT_STRUC {
802 USHORT NonAggTxCount;
806 } TX_AGG_CNT_STRUC, *PTX_AGG_CNT_STRUC;
809 #define TX_AGG_CNT0 0x1720
810 typedef union _TX_AGG_CNT0_STRUC {
812 USHORT AggSize1Count;
813 USHORT AggSize2Count;
816 } TX_AGG_CNT0_STRUC, *PTX_AGG_CNT0_STRUC;
819 #define TX_AGG_CNT1 0x1724
820 typedef union _TX_AGG_CNT1_STRUC {
822 USHORT AggSize3Count;
823 USHORT AggSize4Count;
826 } TX_AGG_CNT1_STRUC, *PTX_AGG_CNT1_STRUC;
828 #define TX_AGG_CNT2 0x1728
829 typedef union _TX_AGG_CNT2_STRUC {
831 USHORT AggSize5Count;
832 USHORT AggSize6Count;
835 } TX_AGG_CNT2_STRUC, *PTX_AGG_CNT2_STRUC;
838 #define TX_AGG_CNT3 0x172c
839 typedef union _TX_AGG_CNT3_STRUC {
841 USHORT AggSize7Count;
842 USHORT AggSize8Count;
845 } TX_AGG_CNT3_STRUC, *PTX_AGG_CNT3_STRUC;
848 #define TX_AGG_CNT4 0x1730
849 typedef union _TX_AGG_CNT4_STRUC {
851 USHORT AggSize9Count;
852 USHORT AggSize10Count;
855 } TX_AGG_CNT4_STRUC, *PTX_AGG_CNT4_STRUC;
857 #define TX_AGG_CNT5 0x1734
858 typedef union _TX_AGG_CNT5_STRUC {
860 USHORT AggSize11Count;
861 USHORT AggSize12Count;
864 } TX_AGG_CNT5_STRUC, *PTX_AGG_CNT5_STRUC;
866 #define TX_AGG_CNT6 0x1738
867 typedef union _TX_AGG_CNT6_STRUC {
869 USHORT AggSize13Count;
870 USHORT AggSize14Count;
873 } TX_AGG_CNT6_STRUC, *PTX_AGG_CNT6_STRUC;
875 #define TX_AGG_CNT7 0x173c
876 typedef union _TX_AGG_CNT7_STRUC {
878 USHORT AggSize15Count;
879 USHORT AggSize16Count;
882 } TX_AGG_CNT7_STRUC, *PTX_AGG_CNT7_STRUC;
884 #define MPDU_DENSITY_CNT 0x1740
885 typedef union _MPDU_DEN_CNT_STRUC {
887 USHORT TXZeroDelCount; //TX zero length delimiter count
888 USHORT RXZeroDelCount; //RX zero length delimiter count
891 } MPDU_DEN_CNT_STRUC, *PMPDU_DEN_CNT_STRUC;
894 // TXRX control registers - base address 0x3000
896 // rt2860b UNKNOWN reg use R/O Reg Addr 0x77d0 first..
897 #define TXRX_CSR1 0x77d0
900 // Security key table memory, base address = 0x1000
902 #define MAC_WCID_BASE 0x1800 //8-bytes(use only 6-bytes) * 256 entry =
903 #define HW_WCID_ENTRY_SIZE 8
904 #define PAIRWISE_KEY_TABLE_BASE 0x4000 // 32-byte * 256-entry = -byte
905 #define HW_KEY_ENTRY_SIZE 0x20
906 #define PAIRWISE_IVEIV_TABLE_BASE 0x6000 // 8-byte * 256-entry = -byte
907 #define MAC_IVEIV_TABLE_BASE 0x6000 // 8-byte * 256-entry = -byte
908 #define HW_IVEIV_ENTRY_SIZE 8
909 #define MAC_WCID_ATTRIBUTE_BASE 0x6800 // 4-byte * 256-entry = -byte
910 #define HW_WCID_ATTRI_SIZE 4
911 #define WCID_RESERVED 0x6bfc
912 #define SHARED_KEY_TABLE_BASE 0x6c00 // 32-byte * 16-entry = 512-byte
913 #define SHARED_KEY_MODE_BASE 0x7000 // 32-byte * 16-entry = 512-byte
914 #define HW_SHARED_KEY_MODE_SIZE 4
915 #define SHAREDKEYTABLE 0
916 #define PAIRWISEKEYTABLE 1
918 typedef union _SHAREDKEY_MODE_STRUC {
920 UINT32 Bss0Key0CipherAlg:3;
922 UINT32 Bss0Key1CipherAlg:3;
924 UINT32 Bss0Key2CipherAlg:3;
926 UINT32 Bss0Key3CipherAlg:3;
928 UINT32 Bss1Key0CipherAlg:3;
930 UINT32 Bss1Key1CipherAlg:3;
932 UINT32 Bss1Key2CipherAlg:3;
934 UINT32 Bss1Key3CipherAlg:3;
938 } SHAREDKEY_MODE_STRUC, *PSHAREDKEY_MODE_STRUC;
940 // 64-entry for pairwise key table
941 typedef struct _HW_WCID_ENTRY { // 8-byte per entry
944 } HW_WCID_ENTRY, PHW_WCID_ENTRY;
949 // Other on-chip shared memory space, base = 0x2000
952 // CIS space - base address = 0x2000
953 #define HW_CIS_BASE 0x2000
955 // Carrier-sense CTS frame base address. It's where mac stores carrier-sense frame for carrier-sense function.
956 #define HW_CS_CTS_BASE 0x7700
957 // DFS CTS frame base address. It's where mac stores CTS frame for DFS.
958 #define HW_DFS_CTS_BASE 0x7780
959 #define HW_CTS_FRAME_SIZE 0x80
961 // 2004-11-08 john - since NULL frame won't be that long (256 byte). We steal 16 tail bytes
962 // to save debugging settings
963 #define HW_DEBUG_SETTING_BASE 0x77f0 // 0x77f0~0x77ff total 16 bytes
964 #define HW_DEBUG_SETTING_BASE2 0x7770 // 0x77f0~0x77ff total 16 bytes
967 // on-chip BEACON frame space - base address = 0x7800
968 #define HW_BEACON_MAX_SIZE 0x0800 /* unit: byte */
969 #define HW_BEACON_BASE0 0x7800
970 #define HW_BEACON_BASE1 0x7900
971 #define HW_BEACON_BASE2 0x7a00
972 #define HW_BEACON_BASE3 0x7b00
973 #define HW_BEACON_BASE4 0x7c00
974 #define HW_BEACON_BASE5 0x7d00
975 #define HW_BEACON_BASE6 0x7e00
976 #define HW_BEACON_BASE7 0x7f00
977 /* 1. HW_BEACON_OFFSET/64B must be 0;
978 2. BCN_OFFSET0 must also be changed in NICInitializeAsic();
979 3. max 0x0800 for 8 beacon frames; */
981 // In order to support maximum 8 MBSS and its maximum length is 512 for each beacon
982 // Three section discontinue memory segments will be used.
983 // 1. The original region for BCN 0~3
984 // 2. Extract memory from FCE table for BCN 4~5
985 // 3. Extract memory from Pair-wise key table for BCN 6~7
986 // It occupied those memory of wcid 238~253 for BCN 6
987 // and wcid 222~237 for BCN 7
988 #define HW_BEACON_MAX_SIZE 0x1000 /* unit: byte */
989 #define HW_BEACON_BASE0 0x7800
990 #define HW_BEACON_BASE1 0x7A00
991 #define HW_BEACON_BASE2 0x7C00
992 #define HW_BEACON_BASE3 0x7E00
993 #define HW_BEACON_BASE4 0x7200
994 #define HW_BEACON_BASE5 0x7400
995 #define HW_BEACON_BASE6 0x5DC0
996 #define HW_BEACON_BASE7 0x5BC0
999 #define HW_BEACON_MAX_COUNT 8
1000 #define HW_BEACON_OFFSET 0x0200
1001 #define HW_BEACON_CONTENT_LEN (HW_BEACON_OFFSET - TXWI_SIZE)
1003 // HOST-MCU shared memory - base address = 0x2100
1004 #define HOST_CMD_CSR 0x404
1005 #define H2M_MAILBOX_CSR 0x7010
1006 #define H2M_MAILBOX_CID 0x7014
1007 #define H2M_MAILBOX_STATUS 0x701c
1008 #define H2M_INT_SRC 0x7024
1009 #define H2M_BBP_AGENT 0x7028
1010 #define M2H_CMD_DONE_CSR 0x000c
1011 #define MCU_TXOP_ARRAY_BASE 0x000c // TODO: to be provided by Albert
1012 #define MCU_TXOP_ENTRY_SIZE 32 // TODO: to be provided by Albert
1013 #define MAX_NUM_OF_TXOP_ENTRY 16 // TODO: must be same with 8051 firmware
1014 #define MCU_MBOX_VERSION 0x01 // TODO: to be confirmed by Albert
1015 #define MCU_MBOX_VERSION_OFFSET 5 // TODO: to be provided by Albert
1018 // Host DMA registers - base address 0x200 . TX0-3=EDCAQid0-3, TX4=HCCA, TX5=MGMT,
1021 // DMA RING DESCRIPTOR
1023 #define E2PROM_CSR 0x0004
1024 #define IO_CNTL_CSR 0x77d0
1027 // 8051 firmware image for usb - use last-half base address = 0x3000
1028 #define FIRMWARE_IMAGE_BASE 0x3000
1029 #define MAX_FIRMWARE_IMAGE_SIZE 0x1000 // 4kbyte
1032 // TODO: ????? old RT2560 registers. to keep them or remove them?
1033 //#define MCAST0 0x0178 // multicast filter register 0
1034 //#define MCAST1 0x017c // multicast filter register 1
1037 // ================================================================
1038 // Tx / Rx / Mgmt ring descriptor definition
1039 // ================================================================
1041 // the following PID values are used to mark outgoing frame type in TXD->PID so that
1042 // proper TX statistics can be collected based on these categories
1043 // b3-2 of PID field -
1044 #define PID_MGMT 0x05
1045 #define PID_BEACON 0x0c
1046 #define PID_DATA_NORMALUCAST 0x02
1047 #define PID_DATA_AMPDU 0x04
1048 #define PID_DATA_NO_ACK 0x08
1049 #define PID_DATA_NOT_NORM_ACK 0x03
1051 #define PTYPE_DATA_REQUIRE_ACK 0x00 // b7-6:00, b5-0: 0~59 is MAC table index (AID?), 60~63 is WDS index
1052 #define PTYPE_NULL_AT_HIGH_RATE 0x04 // b7-6:01, b5-0: 0~59 is MAC table index (AID?), 60~63 is WDS index
1053 #define PTYPE_RESERVED 0x08 // b7-6:10
1054 #define PTYPE_SPECIAL 0x0c // b7-6:11
1056 // when b3-2=11 (PTYPE_SPECIAL), b1-0 coube be ...
1057 #define PSUBTYPE_DATA_NO_ACK 0x00
1058 #define PSUBTYPE_MGMT 0x01
1059 #define PSUBTYPE_OTHER_CNTL 0x02
1060 #define PSUBTYPE_RTS 0x03
1062 // value domain of pTxD->HostQId (4-bit: 0~15)
1063 #define QID_AC_BK 1 // meet ACI definition in 802.11e
1064 #define QID_AC_BE 0 // meet ACI definition in 802.11e
1068 #define NUM_OF_TX_RING 5
1071 #define QID_OTHER 15
1074 // ------------------------------------------------------
1075 // BBP & RF definition
1076 // ------------------------------------------------------
1113 #define BBP_R0 0 // version
1114 #define BBP_R1 1 // TSSI
1115 #define BBP_R2 2 // TX configure
1120 #define BBP_R14 14 // RX configure
1122 #define BBP_R17 17 // RX sensibility
1128 #define BBP_R49 49 //TSSI
1133 #define BBP_R62 62 // Rx SQ0 Threshold HIGH
1141 #define BBP_R70 70 // Rx AGC SQ CCK Xcorr threshold
1152 #define BBP_R94 94 // Tx Gain Control
1153 #define BBP_R103 103
1154 #define BBP_R105 105
1155 #define BBP_R113 113
1156 #define BBP_R114 114
1157 #define BBP_R115 115
1158 #define BBP_R116 116
1159 #define BBP_R117 117
1160 #define BBP_R118 118
1161 #define BBP_R119 119
1162 #define BBP_R120 120
1163 #define BBP_R121 121
1164 #define BBP_R122 122
1165 #define BBP_R123 123
1168 #define BBPR94_DEFAULT 0x06 // Add 1 value will gain 1db
1170 //#define PHY_TR_SWITCH_TIME 5 // usec
1172 //#define BBP_R17_LOW_SENSIBILITY 0x50
1173 //#define BBP_R17_MID_SENSIBILITY 0x41
1174 //#define BBP_R17_DYNAMIC_UP_BOUND 0x40
1175 #define RSSI_FOR_VERY_LOW_SENSIBILITY -35
1176 #define RSSI_FOR_LOW_SENSIBILITY -58
1177 #define RSSI_FOR_MID_LOW_SENSIBILITY -80
1178 #define RSSI_FOR_MID_SENSIBILITY -90
1180 //-------------------------------------------------------------------------
1181 // EEPROM definition
1182 //-------------------------------------------------------------------------
1189 #define EEPROM_WRITE_OPCODE 0x05
1190 #define EEPROM_READ_OPCODE 0x06
1191 #define EEPROM_EWDS_OPCODE 0x10
1192 #define EEPROM_EWEN_OPCODE 0x13
1194 #define NUM_EEPROM_BBP_PARMS 19 // Include NIC Config 0, 1, CR, TX ALC step, BBPs
1195 #define NUM_EEPROM_TX_G_PARMS 7
1196 #define EEPROM_NIC1_OFFSET 0x34 // The address is from NIC config 0, not BBP register ID
1197 #define EEPROM_NIC2_OFFSET 0x36 // The address is from NIC config 0, not BBP register ID
1198 #define EEPROM_BBP_BASE_OFFSET 0xf0 // The address is from NIC config 0, not BBP register ID
1199 #define EEPROM_G_TX_PWR_OFFSET 0x52
1200 #define EEPROM_G_TX2_PWR_OFFSET 0x60
1201 #define EEPROM_LED1_OFFSET 0x3c
1202 #define EEPROM_LED2_OFFSET 0x3e
1203 #define EEPROM_LED3_OFFSET 0x40
1204 #define EEPROM_LNA_OFFSET 0x44
1205 #define EEPROM_RSSI_BG_OFFSET 0x46
1206 #define EEPROM_RSSI_A_OFFSET 0x4a
1207 #define EEPROM_DEFINE_MAX_TXPWR 0x4e
1208 #define EEPROM_TXPOWER_BYRATE_20MHZ_2_4G 0xde // 20MHZ 2.4G tx power.
1209 #define EEPROM_TXPOWER_BYRATE_40MHZ_2_4G 0xee // 40MHZ 2.4G tx power.
1210 #define EEPROM_TXPOWER_BYRATE_20MHZ_5G 0xfa // 20MHZ 5G tx power.
1211 #define EEPROM_TXPOWER_BYRATE_40MHZ_5G 0x10a // 40MHZ 5G tx power.
1212 #define EEPROM_A_TX_PWR_OFFSET 0x78
1213 #define EEPROM_A_TX2_PWR_OFFSET 0xa6
1214 //#define EEPROM_Japan_TX_PWR_OFFSET 0x90 // 802.11j
1215 //#define EEPROM_Japan_TX2_PWR_OFFSET 0xbe
1216 //#define EEPROM_TSSI_REF_OFFSET 0x54
1217 //#define EEPROM_TSSI_DELTA_OFFSET 0x24
1218 //#define EEPROM_CCK_TX_PWR_OFFSET 0x62
1219 //#define EEPROM_CALIBRATE_OFFSET 0x7c
1220 #define EEPROM_VERSION_OFFSET 0x02
1221 #define EEPROM_FREQ_OFFSET 0x3a
1222 #define EEPROM_TXPOWER_BYRATE 0xde // 20MHZ power.
1223 #define EEPROM_TXPOWER_DELTA 0x50 // 20MHZ AND 40 MHZ use different power. This is delta in 40MHZ.
1224 #define VALID_EEPROM_VERSION 1
1226 // PairKeyMode definition
1227 #define PKMODE_NONE 0
1228 #define PKMODE_WEP64 1
1229 #define PKMODE_WEP128 2
1230 #define PKMODE_TKIP 3
1231 #define PKMODE_AES 4
1232 #define PKMODE_CKIP64 5
1233 #define PKMODE_CKIP128 6
1234 #define PKMODE_TKIP_NO_MIC 7 // MIC appended by driver: not a valid value in hardware key table
1236 // =================================================================================
1238 // =================================================================================
1239 //7.1 WCID ENTRY format : 8bytes
1240 typedef struct _WCID_ENTRY_STRUC {
1241 UCHAR RXBABitmap7; // bit0 for TID8, bit7 for TID 15
1242 UCHAR RXBABitmap0; // bit0 for TID0, bit7 for TID 7
1243 UCHAR MAC[6]; // 0 for shared key table. 1 for pairwise key table
1244 } WCID_ENTRY_STRUC, *PWCID_ENTRY_STRUC;
1246 //8.1.1 SECURITY KEY format : 8DW
1247 // 32-byte per entry, total 16-entry for shared key table, 64-entry for pairwise key table
1248 typedef struct _HW_KEY_ENTRY { // 32-byte per entry
1252 } HW_KEY_ENTRY, *PHW_KEY_ENTRY;
1254 //8.1.2 IV/EIV format : 2DW
1256 //8.1.3 RX attribute entry format : 1DW
1257 typedef struct _MAC_ATTRIBUTE_STRUC {
1258 UINT32 KeyTab:1; // 0 for shared key table. 1 for pairwise key table
1259 UINT32 PairKeyMode:3;
1260 UINT32 BSSIDIdx:3; //multipleBSS index for the WCID
1263 } MAC_ATTRIBUTE_STRUC, *PMAC_ATTRIBUTE_STRUC;
1265 // =================================================================================
1266 // TX / RX ring descriptor format
1267 // =================================================================================
1269 // the first 24-byte in TXD is called TXINFO and will be DMAed to MAC block through TXFIFO.
1270 // MAC block use this TXINFO to control the transmission behavior of this frame.
1276 // TX descriptor format, Tx ring, Mgmt Ring
1278 typedef struct PACKED _TXD_STRUC {
1292 UINT32 WIV:1; // Wireless Info Valid. 1 if Driver already fill WI, o if DMA needs to copy WI to correctposition
1293 UINT32 QSEL:2; // select on-chip FIFO ID for 2nd-stage output scheduler.0:MGMT, 1:HCCA 2:EDCA
1298 } TXD_STRUC, *PTXD_STRUC;
1301 // TXD Wireless Information format for Tx ring and Mgmt Ring
1303 //txop : for txop mode
1304 // 0:txop for the MPDU frame will be handles by ASIC by register
1305 // 1/2/3:the MPDU frame is send after PIFS/backoff/SIFS
1306 typedef struct PACKED _TXWI_STRUC {
1308 UINT32 FRAG:1; // 1 to inform TKIP engine this is a fragment.
1309 UINT32 MIMOps:1; // the remote peer is in dynamic MIMO-PS mode
1314 UINT32 MpduDensity:3;
1315 UINT32 txop:2; //FOR "THIS" frame. 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs only when previous frame exchange is successful.
1319 UINT32 BW:1; //channel bandwidth 20MHz or 40 MHz
1321 UINT32 STBC:2; // 1: STBC support MCS =0-7, 2,3 : RESERVE
1323 // UINT32 rsv2:2; //channel bandwidth 20MHz or 40 MHz
1325 UINT32 TxBF:1; // 3*3
1331 UINT32 WirelessCliID:8;
1332 UINT32 MPDUtotalByteCount:12;
1338 } TXWI_STRUC, *PTXWI_STRUC;
1341 // Rx descriptor format, Rx Ring
1344 // RXWI wireless information format, in PBF. invisible in driver.
1346 typedef struct PACKED _RXWI_STRUC {
1348 UINT32 WirelessCliID:8;
1352 UINT32 MPDUtotalByteCount:12;
1362 UINT32 PHYMODE:2; // 1: this RX frame is unicast to me
1372 } RXWI_STRUC, *PRXWI_STRUC;
1374 // =================================================================================
1375 // HOST-MCU communication data structure
1376 // =================================================================================
1379 // H2M_MAILBOX_CSR: Host-to-MCU Mailbox
1381 typedef union _H2M_MAILBOX_STRUC {
1389 } H2M_MAILBOX_STRUC, *PH2M_MAILBOX_STRUC;
1392 // M2H_CMD_DONE_CSR: MCU-to-Host command complete indication
1394 typedef union _M2H_CMD_DONE_STRUC {
1402 } M2H_CMD_DONE_STRUC, *PM2H_CMD_DONE_STRUC;
1405 // MCU_LEDCS: MCU LED Control Setting.
1407 typedef union _MCU_LEDCS_STRUC {
1413 } MCU_LEDCS_STRUC, *PMCU_LEDCS_STRUC;
1415 // =================================================================================
1417 // =================================================================================
1422 typedef union _NAV_TIME_CFG_STRUC {
1424 UCHAR Sifs; // in unit of 1-us
1425 UCHAR SlotTime; // in unit of 1-us
1426 USHORT Eifs:9; // in unit of 1-us
1427 USHORT ZeroSifs:1; // Applied zero SIFS timer after OFDM RX 0: disable
1431 } NAV_TIME_CFG_STRUC, *PNAV_TIME_CFG_STRUC;
1434 // RX_FILTR_CFG: /RX configuration register
1436 typedef union _RX_FILTR_CFG_STRUC {
1438 UINT32 DropCRCErr:1; // Drop CRC error
1439 UINT32 DropPhyErr:1; // Drop physical error
1440 UINT32 DropNotToMe:1; // Drop not to me unicast frame
1441 UINT32 DropNotMyBSSID:1; // Drop fram ToDs bit is true
1443 UINT32 DropVerErr:1; // Drop version error frame
1444 UINT32 DropMcast:1; // Drop multicast frames
1445 UINT32 DropBcast:1; // Drop broadcast frames
1446 UINT32 DropDuplicate:1; // Drop duplicate frame
1448 UINT32 DropCFEndAck:1; // Drop Ps-Poll
1449 UINT32 DropCFEnd:1; // Drop Ps-Poll
1450 UINT32 DropAck:1; // Drop Ps-Poll
1451 UINT32 DropCts:1; // Drop Ps-Poll
1453 UINT32 DropRts:1; // Drop Ps-Poll
1454 UINT32 DropPsPoll:1; // Drop Ps-Poll
1456 UINT32 DropBAR:1; //
1458 UINT32 DropRsvCntlType:1;
1462 } RX_FILTR_CFG_STRUC, *PRX_FILTR_CFG_STRUC;
1465 // PHY_CSR4: RF serial control register
1467 typedef union _PHY_CSR4_STRUC {
1469 UINT32 RFRegValue:24; // Register value (include register id) serial out to RF/IF chip.
1470 UINT32 NumberOfBits:5; // Number of bits used in RFRegValue (I:20, RFMD:22)
1471 UINT32 IFSelect:1; // 1: select IF to program, 0: select RF to program
1472 UINT32 PLL_LD:1; // RF PLL_LD status
1473 UINT32 Busy:1; // 1: ASIC is busy execute RF programming.
1476 } PHY_CSR4_STRUC, *PPHY_CSR4_STRUC;
1479 // SEC_CSR5: shared key table security mode register
1481 typedef union _SEC_CSR5_STRUC {
1483 UINT32 Bss2Key0CipherAlg:3;
1485 UINT32 Bss2Key1CipherAlg:3;
1487 UINT32 Bss2Key2CipherAlg:3;
1489 UINT32 Bss2Key3CipherAlg:3;
1491 UINT32 Bss3Key0CipherAlg:3;
1493 UINT32 Bss3Key1CipherAlg:3;
1495 UINT32 Bss3Key2CipherAlg:3;
1497 UINT32 Bss3Key3CipherAlg:3;
1501 } SEC_CSR5_STRUC, *PSEC_CSR5_STRUC;
1504 // HOST_CMD_CSR: For HOST to interrupt embedded processor
1506 typedef union _HOST_CMD_CSR_STRUC {
1508 UINT32 HostCommand:8;
1512 } HOST_CMD_CSR_STRUC, *PHOST_CMD_CSR_STRUC;
1515 // AIFSN_CSR: AIFSN for each EDCA AC
1521 // E2PROM_CSR: EEPROM control register
1523 typedef union _E2PROM_CSR_STRUC {
1525 UINT32 Reload:1; // Reload EEPROM content, write one to reload, self-cleared.
1530 UINT32 Type:1; // 1: 93C46, 0:93C66
1531 UINT32 LoadStatus:1; // 1:loading, 0:done
1535 } E2PROM_CSR_STRUC, *PE2PROM_CSR_STRUC;
1537 // -------------------------------------------------------------------
1538 // E2PROM data layout
1539 // -------------------------------------------------------------------
1542 // EEPROM antenna select format
1544 typedef union _EEPROM_ANTENNA_STRUC {
1546 USHORT RxPath:4; // 1: 1R, 2: 2R, 3: 3R
1547 USHORT TxPath:4; // 1: 1T, 2: 2T
1548 USHORT RfIcType:4; // see E2PROM document
1552 } EEPROM_ANTENNA_STRUC, *PEEPROM_ANTENNA_STRUC;
1554 typedef union _EEPROM_NIC_CINFIG2_STRUC {
1556 USHORT HardwareRadioControl:1; // 1:enable, 0:disable
1557 USHORT DynamicTxAgcControl:1; //
1558 USHORT ExternalLNAForG:1; //
1559 USHORT ExternalLNAForA:1; // external LNA enable for 2.4G
1560 USHORT CardbusAcceleration:1; // !!! NOTE: 0 - enable, 1 - disable
1561 USHORT BW40MSidebandForG:1;
1562 USHORT BW40MSidebandForA:1;
1563 USHORT EnableWPSPBC:1; // WPS PBC Control bit
1564 USHORT BW40MAvailForG:1; // 0:enable, 1:disable
1565 USHORT BW40MAvailForA:1; // 0:enable, 1:disable
1566 USHORT Rsv2:6; // must be 0
1569 } EEPROM_NIC_CONFIG2_STRUC, *PEEPROM_NIC_CONFIG2_STRUC;
1572 // TX_PWR Value valid range 0xFA(-6) ~ 0x24(36)
1574 typedef union _EEPROM_TX_PWR_STRUC {
1576 CHAR Byte0; // Low Byte
1577 CHAR Byte1; // High Byte
1580 } EEPROM_TX_PWR_STRUC, *PEEPROM_TX_PWR_STRUC;
1582 typedef union _EEPROM_VERSION_STRUC {
1584 UCHAR FaeReleaseNumber; // Low Byte
1585 UCHAR Version; // High Byte
1588 } EEPROM_VERSION_STRUC, *PEEPROM_VERSION_STRUC;
1590 typedef union _EEPROM_LED_STRUC {
1592 USHORT PolarityRDY_G:1; // Polarity RDY_G setting.
1593 USHORT PolarityRDY_A:1; // Polarity RDY_A setting.
1594 USHORT PolarityACT:1; // Polarity ACT setting.
1595 USHORT PolarityGPIO_0:1; // Polarity GPIO#0 setting.
1596 USHORT PolarityGPIO_1:1; // Polarity GPIO#1 setting.
1597 USHORT PolarityGPIO_2:1; // Polarity GPIO#2 setting.
1598 USHORT PolarityGPIO_3:1; // Polarity GPIO#3 setting.
1599 USHORT PolarityGPIO_4:1; // Polarity GPIO#4 setting.
1600 USHORT LedMode:5; // Led mode.
1601 USHORT Rsvd:3; // Reserved
1604 } EEPROM_LED_STRUC, *PEEPROM_LED_STRUC;
1606 typedef union _EEPROM_TXPOWER_DELTA_STRUC {
1608 UCHAR DeltaValue:6; // Tx Power dalta value (MAX=4)
1609 UCHAR Type:1; // 1: plus the delta value, 0: minus the delta value
1610 UCHAR TxPowerEnable:1;// Enable
1613 } EEPROM_TXPOWER_DELTA_STRUC, *PEEPROM_TXPOWER_DELTA_STRUC;
1616 // QOS_CSR0: TXOP holder address0 register
1618 typedef union _QOS_CSR0_STRUC {
1620 UCHAR Byte0; // MAC address byte 0
1621 UCHAR Byte1; // MAC address byte 1
1622 UCHAR Byte2; // MAC address byte 2
1623 UCHAR Byte3; // MAC address byte 3
1626 } QOS_CSR0_STRUC, *PQOS_CSR0_STRUC;
1629 // QOS_CSR1: TXOP holder address1 register
1631 typedef union _QOS_CSR1_STRUC {
1633 UCHAR Byte4; // MAC address byte 4
1634 UCHAR Byte5; // MAC address byte 5
1639 } QOS_CSR1_STRUC, *PQOS_CSR1_STRUC;
1641 #define RF_CSR_CFG 0x500
1642 typedef union _RF_CSR_CFG_STRUC {
1644 UINT RF_CSR_DATA:8; // DATA
1645 UINT TESTCSR_RFACC_REGNUM:5; // RF register ID
1646 UINT Rsvd2:3; // Reserved
1647 UINT RF_CSR_WR:1; // 0: read 1: write
1648 UINT RF_CSR_KICK:1; // kick RF register read/write
1649 UINT Rsvd1:14; // Reserved
1652 } RF_CSR_CFG_STRUC, *PRF_CSR_CFG_STRUC;
1654 #endif // __RT28XX_H__