2 * DMM IOMMU driver support functions for TI OMAP processors.
4 * Author: Rob Clark <rob@ti.com>
5 * Andy Gross <andy.gross@ti.com>
7 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation version 2.
13 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
14 * kind, whether express or implied; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 #include <linux/init.h>
19 #include <linux/module.h>
20 #include <linux/platform_device.h> /* platform_device() */
21 #include <linux/errno.h>
22 #include <linux/sched.h>
23 #include <linux/wait.h>
24 #include <linux/interrupt.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/slab.h>
27 #include <linux/vmalloc.h>
28 #include <linux/delay.h>
30 #include <linux/time.h>
31 #include <linux/list.h>
32 #include <linux/semaphore.h>
34 #include "omap_dmm_tiler.h"
35 #include "omap_dmm_priv.h"
37 /* mappings for associating views to luts */
38 static struct tcm *containers[TILFMT_NFORMATS];
39 static struct dmm *omap_dmm;
42 #define GEOM(xshift, yshift, bytes_per_pixel) { \
45 .cpp = (bytes_per_pixel), \
46 .slot_w = 1 << (SLOT_WIDTH_BITS - (xshift)), \
47 .slot_h = 1 << (SLOT_HEIGHT_BITS - (yshift)), \
51 uint32_t x_shft; /* unused X-bits (as part of bpp) */
52 uint32_t y_shft; /* unused Y-bits (as part of bpp) */
53 uint32_t cpp; /* bytes/chars per pixel */
54 uint32_t slot_w; /* width of each slot (in pixels) */
55 uint32_t slot_h; /* height of each slot (in pixels) */
56 } geom[TILFMT_NFORMATS] = {
57 [TILFMT_8BIT] = GEOM(0, 0, 1),
58 [TILFMT_16BIT] = GEOM(0, 1, 2),
59 [TILFMT_32BIT] = GEOM(1, 1, 4),
60 [TILFMT_PAGE] = GEOM(SLOT_WIDTH_BITS, SLOT_HEIGHT_BITS, 1),
64 /* lookup table for registers w/ per-engine instances */
65 static const uint32_t reg[][4] = {
66 [PAT_STATUS] = {DMM_PAT_STATUS__0, DMM_PAT_STATUS__1,
67 DMM_PAT_STATUS__2, DMM_PAT_STATUS__3},
68 [PAT_DESCR] = {DMM_PAT_DESCR__0, DMM_PAT_DESCR__1,
69 DMM_PAT_DESCR__2, DMM_PAT_DESCR__3},
72 /* simple allocator to grab next 16 byte aligned memory from txn */
73 static void *alloc_dma(struct dmm_txn *txn, size_t sz, dma_addr_t *pa)
76 struct refill_engine *engine = txn->engine_handle;
78 /* dmm programming requires 16 byte aligned addresses */
79 txn->current_pa = round_up(txn->current_pa, 16);
80 txn->current_va = (void *)round_up((long)txn->current_va, 16);
82 ptr = txn->current_va;
83 *pa = txn->current_pa;
85 txn->current_pa += sz;
86 txn->current_va += sz;
88 BUG_ON((txn->current_va - engine->refill_va) > REFILL_BUFFER_SIZE);
93 /* check status and spin until wait_mask comes true */
94 static int wait_status(struct refill_engine *engine, uint32_t wait_mask)
96 struct dmm *dmm = engine->dmm;
97 uint32_t r = 0, err, i;
99 i = DMM_FIXED_RETRY_COUNT;
101 r = readl(dmm->base + reg[PAT_STATUS][engine->id]);
102 err = r & DMM_PATSTATUS_ERR;
106 if ((r & wait_mask) == wait_mask)
118 irqreturn_t omap_dmm_irq_handler(int irq, void *arg)
120 struct dmm *dmm = arg;
121 uint32_t status = readl(dmm->base + DMM_PAT_IRQSTATUS);
125 writel(status, dmm->base + DMM_PAT_IRQSTATUS);
127 for (i = 0; i < dmm->num_engines; i++) {
128 if (status & DMM_IRQSTAT_LST)
129 wake_up_interruptible(&dmm->engines[i].wait_for_refill);
138 * Get a handle for a DMM transaction
140 static struct dmm_txn *dmm_txn_init(struct dmm *dmm, struct tcm *tcm)
142 struct dmm_txn *txn = NULL;
143 struct refill_engine *engine = NULL;
145 down(&dmm->engine_sem);
147 /* grab an idle engine */
148 spin_lock(&dmm->list_lock);
149 if (!list_empty(&dmm->idle_head)) {
150 engine = list_entry(dmm->idle_head.next, struct refill_engine,
152 list_del(&engine->idle_node);
154 spin_unlock(&dmm->list_lock);
160 txn->engine_handle = engine;
161 txn->last_pat = NULL;
162 txn->current_va = engine->refill_va;
163 txn->current_pa = engine->refill_pa;
169 * Add region to DMM transaction. If pages or pages[i] is NULL, then the
170 * corresponding slot is cleared (ie. dummy_pa is programmed)
172 static int dmm_txn_append(struct dmm_txn *txn, struct pat_area *area,
173 struct page **pages, uint32_t npages, uint32_t roll)
175 dma_addr_t pat_pa = 0;
178 struct refill_engine *engine = txn->engine_handle;
179 int columns = (1 + area->x1 - area->x0);
180 int rows = (1 + area->y1 - area->y0);
181 int i = columns*rows;
182 u32 *lut = omap_dmm->lut + (engine->tcm->lut_id * omap_dmm->lut_width *
183 omap_dmm->lut_height) +
184 (area->y0 * omap_dmm->lut_width) + area->x0;
186 pat = alloc_dma(txn, sizeof(struct pat), &pat_pa);
189 txn->last_pat->next_pa = (uint32_t)pat_pa;
192 pat->ctrl = (struct pat_ctrl){
194 .lut_id = engine->tcm->lut_id,
197 data = alloc_dma(txn, 4*i, &pat->data_pa);
203 data[i] = (pages && pages[n]) ?
204 page_to_phys(pages[n]) : engine->dmm->dummy_pa;
207 /* fill in lut with new addresses */
208 for (i = 0; i < rows; i++, lut += omap_dmm->lut_width)
209 memcpy(lut, &data[i*columns], columns * sizeof(u32));
217 * Commit the DMM transaction.
219 static int dmm_txn_commit(struct dmm_txn *txn, bool wait)
222 struct refill_engine *engine = txn->engine_handle;
223 struct dmm *dmm = engine->dmm;
225 if (!txn->last_pat) {
226 dev_err(engine->dmm->dev, "need at least one txn\n");
231 txn->last_pat->next_pa = 0;
233 /* write to PAT_DESCR to clear out any pending transaction */
234 writel(0x0, dmm->base + reg[PAT_DESCR][engine->id]);
236 /* wait for engine ready: */
237 ret = wait_status(engine, DMM_PATSTATUS_READY);
244 writel(engine->refill_pa,
245 dmm->base + reg[PAT_DESCR][engine->id]);
248 if (wait_event_interruptible_timeout(engine->wait_for_refill,
249 wait_status(engine, DMM_PATSTATUS_READY) == 0,
250 msecs_to_jiffies(1)) <= 0) {
251 dev_err(dmm->dev, "timed out waiting for done\n");
257 spin_lock(&dmm->list_lock);
258 list_add(&engine->idle_node, &dmm->idle_head);
259 spin_unlock(&dmm->list_lock);
261 up(&omap_dmm->engine_sem);
268 static int fill(struct tcm_area *area, struct page **pages,
269 uint32_t npages, uint32_t roll, bool wait)
272 struct tcm_area slice, area_s;
275 txn = dmm_txn_init(omap_dmm, area->tcm);
276 if (IS_ERR_OR_NULL(txn))
279 tcm_for_each_slice(slice, *area, area_s) {
280 struct pat_area p_area = {
281 .x0 = slice.p0.x, .y0 = slice.p0.y,
282 .x1 = slice.p1.x, .y1 = slice.p1.y,
285 ret = dmm_txn_append(txn, &p_area, pages, npages, roll);
289 roll += tcm_sizeof(slice);
292 ret = dmm_txn_commit(txn, wait);
302 /* note: slots for which pages[i] == NULL are filled w/ dummy page
304 int tiler_pin(struct tiler_block *block, struct page **pages,
305 uint32_t npages, uint32_t roll, bool wait)
309 ret = fill(&block->area, pages, npages, roll, wait);
317 int tiler_unpin(struct tiler_block *block)
319 return fill(&block->area, NULL, 0, 0, false);
325 struct tiler_block *tiler_reserve_2d(enum tiler_fmt fmt, uint16_t w,
326 uint16_t h, uint16_t align)
328 struct tiler_block *block = kzalloc(sizeof(*block), GFP_KERNEL);
332 BUG_ON(!validfmt(fmt));
334 /* convert width/height to slots */
335 w = DIV_ROUND_UP(w, geom[fmt].slot_w);
336 h = DIV_ROUND_UP(h, geom[fmt].slot_h);
338 /* convert alignment to slots */
339 min_align = max(min_align, (geom[fmt].slot_w * geom[fmt].cpp));
340 align = ALIGN(align, min_align);
341 align /= geom[fmt].slot_w * geom[fmt].cpp;
345 ret = tcm_reserve_2d(containers[fmt], w, h, align, &block->area);
351 /* add to allocation list */
352 spin_lock(&omap_dmm->list_lock);
353 list_add(&block->alloc_node, &omap_dmm->alloc_head);
354 spin_unlock(&omap_dmm->list_lock);
359 struct tiler_block *tiler_reserve_1d(size_t size)
361 struct tiler_block *block = kzalloc(sizeof(*block), GFP_KERNEL);
362 int num_pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
367 block->fmt = TILFMT_PAGE;
369 if (tcm_reserve_1d(containers[TILFMT_PAGE], num_pages,
375 spin_lock(&omap_dmm->list_lock);
376 list_add(&block->alloc_node, &omap_dmm->alloc_head);
377 spin_unlock(&omap_dmm->list_lock);
382 /* note: if you have pin'd pages, you should have already unpin'd first! */
383 int tiler_release(struct tiler_block *block)
385 int ret = tcm_free(&block->area);
388 dev_err(omap_dmm->dev, "failed to release block\n");
390 spin_lock(&omap_dmm->list_lock);
391 list_del(&block->alloc_node);
392 spin_unlock(&omap_dmm->list_lock);
402 /* calculate the tiler space address of a pixel in a view orientation */
403 static u32 tiler_get_address(u32 orient, enum tiler_fmt fmt, u32 x, u32 y)
405 u32 x_bits, y_bits, tmp, x_mask, y_mask, alignment;
407 x_bits = CONT_WIDTH_BITS - geom[fmt].x_shft;
408 y_bits = CONT_HEIGHT_BITS - geom[fmt].y_shft;
409 alignment = geom[fmt].x_shft + geom[fmt].y_shft;
411 /* validate coordinate */
412 x_mask = MASK(x_bits);
413 y_mask = MASK(y_bits);
415 if (x < 0 || x > x_mask || y < 0 || y > y_mask)
418 /* account for mirroring */
419 if (orient & MASK_X_INVERT)
421 if (orient & MASK_Y_INVERT)
424 /* get coordinate address */
425 if (orient & MASK_XY_FLIP)
426 tmp = ((x << y_bits) + y);
428 tmp = ((y << x_bits) + x);
430 return TIL_ADDR((tmp << alignment), orient, fmt);
433 dma_addr_t tiler_ssptr(struct tiler_block *block)
435 BUG_ON(!validfmt(block->fmt));
437 return TILVIEW_8BIT + tiler_get_address(0, block->fmt,
438 block->area.p0.x * geom[block->fmt].slot_w,
439 block->area.p0.y * geom[block->fmt].slot_h);
442 void tiler_align(enum tiler_fmt fmt, uint16_t *w, uint16_t *h)
444 BUG_ON(!validfmt(fmt));
445 *w = round_up(*w, geom[fmt].slot_w);
446 *h = round_up(*h, geom[fmt].slot_h);
449 uint32_t tiler_stride(enum tiler_fmt fmt)
451 BUG_ON(!validfmt(fmt));
453 return 1 << (CONT_WIDTH_BITS + geom[fmt].y_shft);
456 size_t tiler_size(enum tiler_fmt fmt, uint16_t w, uint16_t h)
458 tiler_align(fmt, &w, &h);
459 return geom[fmt].cpp * w * h;
462 size_t tiler_vsize(enum tiler_fmt fmt, uint16_t w, uint16_t h)
464 BUG_ON(!validfmt(fmt));
465 return round_up(geom[fmt].cpp * w, PAGE_SIZE) * h;
468 int omap_dmm_remove(void)
470 struct tiler_block *block, *_block;
474 /* free all area regions */
475 spin_lock(&omap_dmm->list_lock);
476 list_for_each_entry_safe(block, _block, &omap_dmm->alloc_head,
478 list_del(&block->alloc_node);
481 spin_unlock(&omap_dmm->list_lock);
483 for (i = 0; i < omap_dmm->num_lut; i++)
484 if (omap_dmm->tcm && omap_dmm->tcm[i])
485 omap_dmm->tcm[i]->deinit(omap_dmm->tcm[i]);
486 kfree(omap_dmm->tcm);
488 kfree(omap_dmm->engines);
489 if (omap_dmm->refill_va)
490 dma_free_coherent(omap_dmm->dev,
491 REFILL_BUFFER_SIZE * omap_dmm->num_engines,
493 omap_dmm->refill_pa);
494 if (omap_dmm->dummy_page)
495 __free_page(omap_dmm->dummy_page);
497 vfree(omap_dmm->lut);
499 if (omap_dmm->irq != -1)
500 free_irq(omap_dmm->irq, omap_dmm);
508 int omap_dmm_init(struct drm_device *dev)
510 int ret = -EFAULT, i;
511 struct tcm_area area = {0};
512 u32 hwinfo, pat_geom, lut_table_size;
513 struct omap_drm_platform_data *pdata = dev->dev->platform_data;
515 if (!pdata || !pdata->dmm_pdata) {
516 dev_err(dev->dev, "dmm platform data not present, skipping\n");
520 omap_dmm = kzalloc(sizeof(*omap_dmm), GFP_KERNEL);
522 dev_err(dev->dev, "failed to allocate driver data section\n");
526 /* lookup hwmod data - base address and irq */
527 omap_dmm->base = pdata->dmm_pdata->base;
528 omap_dmm->irq = pdata->dmm_pdata->irq;
529 omap_dmm->dev = dev->dev;
531 if (!omap_dmm->base) {
532 dev_err(dev->dev, "failed to get dmm base address\n");
536 hwinfo = readl(omap_dmm->base + DMM_PAT_HWINFO);
537 omap_dmm->num_engines = (hwinfo >> 24) & 0x1F;
538 omap_dmm->num_lut = (hwinfo >> 16) & 0x1F;
539 omap_dmm->container_width = 256;
540 omap_dmm->container_height = 128;
542 /* read out actual LUT width and height */
543 pat_geom = readl(omap_dmm->base + DMM_PAT_GEOMETRY);
544 omap_dmm->lut_width = ((pat_geom >> 16) & 0xF) << 5;
545 omap_dmm->lut_height = ((pat_geom >> 24) & 0xF) << 5;
547 /* initialize DMM registers */
548 writel(0x88888888, omap_dmm->base + DMM_PAT_VIEW__0);
549 writel(0x88888888, omap_dmm->base + DMM_PAT_VIEW__1);
550 writel(0x80808080, omap_dmm->base + DMM_PAT_VIEW_MAP__0);
551 writel(0x80000000, omap_dmm->base + DMM_PAT_VIEW_MAP_BASE);
552 writel(0x88888888, omap_dmm->base + DMM_TILER_OR__0);
553 writel(0x88888888, omap_dmm->base + DMM_TILER_OR__1);
555 ret = request_irq(omap_dmm->irq, omap_dmm_irq_handler, IRQF_SHARED,
556 "omap_dmm_irq_handler", omap_dmm);
559 dev_err(dev->dev, "couldn't register IRQ %d, error %d\n",
565 /* Enable all interrupts for each refill engine except
566 * ERR_LUT_MISS<n> (which is just advisory, and we don't care
567 * about because we want to be able to refill live scanout
568 * buffers for accelerated pan/scroll) and FILL_DSC<n> which
569 * we just generally don't care about.
571 writel(0x7e7e7e7e, omap_dmm->base + DMM_PAT_IRQENABLE_SET);
573 lut_table_size = omap_dmm->lut_width * omap_dmm->lut_height *
576 omap_dmm->lut = vmalloc(lut_table_size * sizeof(*omap_dmm->lut));
577 if (!omap_dmm->lut) {
578 dev_err(dev->dev, "could not allocate lut table\n");
583 omap_dmm->dummy_page = alloc_page(GFP_KERNEL | __GFP_DMA32);
584 if (!omap_dmm->dummy_page) {
585 dev_err(dev->dev, "could not allocate dummy page\n");
589 omap_dmm->dummy_pa = page_to_phys(omap_dmm->dummy_page);
591 /* alloc refill memory */
592 omap_dmm->refill_va = dma_alloc_coherent(dev->dev,
593 REFILL_BUFFER_SIZE * omap_dmm->num_engines,
594 &omap_dmm->refill_pa, GFP_KERNEL);
595 if (!omap_dmm->refill_va) {
596 dev_err(dev->dev, "could not allocate refill memory\n");
601 omap_dmm->engines = kzalloc(
602 omap_dmm->num_engines * sizeof(struct refill_engine),
604 if (!omap_dmm->engines) {
605 dev_err(dev->dev, "could not allocate engines\n");
610 sema_init(&omap_dmm->engine_sem, omap_dmm->num_engines);
611 INIT_LIST_HEAD(&omap_dmm->idle_head);
612 for (i = 0; i < omap_dmm->num_engines; i++) {
613 omap_dmm->engines[i].id = i;
614 omap_dmm->engines[i].dmm = omap_dmm;
615 omap_dmm->engines[i].refill_va = omap_dmm->refill_va +
616 (REFILL_BUFFER_SIZE * i);
617 omap_dmm->engines[i].refill_pa = omap_dmm->refill_pa +
618 (REFILL_BUFFER_SIZE * i);
619 init_waitqueue_head(&omap_dmm->engines[i].wait_for_refill);
621 list_add(&omap_dmm->engines[i].idle_node, &omap_dmm->idle_head);
624 omap_dmm->tcm = kzalloc(omap_dmm->num_lut * sizeof(*omap_dmm->tcm),
626 if (!omap_dmm->tcm) {
627 dev_err(dev->dev, "failed to allocate lut ptrs\n");
632 /* init containers */
633 for (i = 0; i < omap_dmm->num_lut; i++) {
634 omap_dmm->tcm[i] = sita_init(omap_dmm->container_width,
635 omap_dmm->container_height,
638 if (!omap_dmm->tcm[i]) {
639 dev_err(dev->dev, "failed to allocate container\n");
644 omap_dmm->tcm[i]->lut_id = i;
647 /* assign access mode containers to applicable tcm container */
648 /* OMAP 4 has 1 container for all 4 views */
649 containers[TILFMT_8BIT] = omap_dmm->tcm[0];
650 containers[TILFMT_16BIT] = omap_dmm->tcm[0];
651 containers[TILFMT_32BIT] = omap_dmm->tcm[0];
652 containers[TILFMT_PAGE] = omap_dmm->tcm[0];
654 INIT_LIST_HEAD(&omap_dmm->alloc_head);
655 spin_lock_init(&omap_dmm->list_lock);
657 area = (struct tcm_area) {
660 .p1.x = omap_dmm->container_width - 1,
661 .p1.y = omap_dmm->container_height - 1,
664 for (i = 0; i < lut_table_size; i++)
665 omap_dmm->lut[i] = omap_dmm->dummy_pa;
667 /* initialize all LUTs to dummy page entries */
668 for (i = 0; i < omap_dmm->num_lut; i++) {
669 area.tcm = omap_dmm->tcm[i];
670 if (fill(&area, NULL, 0, 0, true))
671 dev_err(omap_dmm->dev, "refill failed");
674 dev_info(omap_dmm->dev, "initialized all PAT entries\n");
687 #ifdef CONFIG_DEBUG_FS
689 static const char *alphabet = "abcdefghijklmnopqrstuvwxyz"
690 "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789";
691 static const char *special = ".,:;'\"`~!^-+";
693 static void fill_map(char **map, int xdiv, int ydiv, struct tcm_area *a,
697 for (y = a->p0.y / ydiv; y <= a->p1.y / ydiv; y++)
698 for (x = a->p0.x / xdiv; x <= a->p1.x / xdiv; x++)
699 if (map[y][x] == ' ' || ovw)
703 static void fill_map_pt(char **map, int xdiv, int ydiv, struct tcm_pt *p,
706 map[p->y / ydiv][p->x / xdiv] = c;
709 static char read_map_pt(char **map, int xdiv, int ydiv, struct tcm_pt *p)
711 return map[p->y / ydiv][p->x / xdiv];
714 static int map_width(int xdiv, int x0, int x1)
716 return (x1 / xdiv) - (x0 / xdiv) + 1;
719 static void text_map(char **map, int xdiv, char *nice, int yd, int x0, int x1)
721 char *p = map[yd] + (x0 / xdiv);
722 int w = (map_width(xdiv, x0, x1) - strlen(nice)) / 2;
730 static void map_1d_info(char **map, int xdiv, int ydiv, char *nice,
733 sprintf(nice, "%dK", tcm_sizeof(*a) * 4);
734 if (a->p0.y + 1 < a->p1.y) {
735 text_map(map, xdiv, nice, (a->p0.y + a->p1.y) / 2 / ydiv, 0,
737 } else if (a->p0.y < a->p1.y) {
738 if (strlen(nice) < map_width(xdiv, a->p0.x, 256 - 1))
739 text_map(map, xdiv, nice, a->p0.y / ydiv,
740 a->p0.x + xdiv, 256 - 1);
741 else if (strlen(nice) < map_width(xdiv, 0, a->p1.x))
742 text_map(map, xdiv, nice, a->p1.y / ydiv,
744 } else if (strlen(nice) + 1 < map_width(xdiv, a->p0.x, a->p1.x)) {
745 text_map(map, xdiv, nice, a->p0.y / ydiv, a->p0.x, a->p1.x);
749 static void map_2d_info(char **map, int xdiv, int ydiv, char *nice,
752 sprintf(nice, "(%d*%d)", tcm_awidth(*a), tcm_aheight(*a));
753 if (strlen(nice) + 1 < map_width(xdiv, a->p0.x, a->p1.x))
754 text_map(map, xdiv, nice, (a->p0.y + a->p1.y) / 2 / ydiv,
758 int tiler_map_show(struct seq_file *s, void *arg)
760 int xdiv = 2, ydiv = 1;
761 char **map = NULL, *global_map;
762 struct tiler_block *block;
763 struct tcm_area a, p;
765 const char *m2d = alphabet;
766 const char *a2d = special;
767 const char *m2dp = m2d, *a2dp = a2d;
769 int h_adj = omap_dmm->lut_height / ydiv;
770 int w_adj = omap_dmm->lut_width / xdiv;
773 map = kzalloc(h_adj * sizeof(*map), GFP_KERNEL);
774 global_map = kzalloc((w_adj + 1) * h_adj, GFP_KERNEL);
776 if (!map || !global_map)
779 memset(global_map, ' ', (w_adj + 1) * h_adj);
780 for (i = 0; i < omap_dmm->lut_height; i++) {
781 map[i] = global_map + i * (w_adj + 1);
784 spin_lock_irqsave(&omap_dmm->list_lock, flags);
786 list_for_each_entry(block, &omap_dmm->alloc_head, alloc_node) {
787 if (block->fmt != TILFMT_PAGE) {
788 fill_map(map, xdiv, ydiv, &block->area, *m2dp, true);
793 map_2d_info(map, xdiv, ydiv, nice, &block->area);
795 bool start = read_map_pt(map, xdiv, ydiv,
798 bool end = read_map_pt(map, xdiv, ydiv, &block->area.p1)
800 tcm_for_each_slice(a, block->area, p)
801 fill_map(map, xdiv, ydiv, &a, '=', true);
802 fill_map_pt(map, xdiv, ydiv, &block->area.p0,
804 fill_map_pt(map, xdiv, ydiv, &block->area.p1,
806 map_1d_info(map, xdiv, ydiv, nice, &block->area);
810 spin_unlock_irqrestore(&omap_dmm->list_lock, flags);
813 seq_printf(s, "BEGIN DMM TILER MAP\n");
814 for (i = 0; i < 128; i++)
815 seq_printf(s, "%03d:%s\n", i, map[i]);
816 seq_printf(s, "END TILER MAP\n");
818 dev_dbg(omap_dmm->dev, "BEGIN DMM TILER MAP\n");
819 for (i = 0; i < 128; i++)
820 dev_dbg(omap_dmm->dev, "%03d:%s\n", i, map[i]);
821 dev_dbg(omap_dmm->dev, "END TILER MAP\n");