Pileus Git - ~andy/linux/blob - drivers/staging/omapdrm/omap_dmm_tiler.c

   1 /*
   2  * DMM IOMMU driver support functions for TI OMAP processors.
   3  *
   4  * Author: Rob Clark <rob@ti.com>
   5  *         Andy Gross <andy.gross@ti.com>
   6  *
   7  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation version 2.
  12  *
  13  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  14  * kind, whether express or implied; without even the implied warranty
  15  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18 #include <linux/init.h>
  19 #include <linux/module.h>
  20 #include <linux/platform_device.h> /* platform_device() */
  21 #include <linux/errno.h>
  22 #include <linux/sched.h>
  23 #include <linux/wait.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/slab.h>
  27 #include <linux/vmalloc.h>
  28 #include <linux/delay.h>
  29 #include <linux/mm.h>
  30 #include <linux/time.h>
  31 #include <linux/list.h>
  32 #include <linux/semaphore.h>
  33
  34 #include "omap_dmm_tiler.h"
  35 #include "omap_dmm_priv.h"
  36
  37 #define DMM_DRIVER_NAME "dmm"
  38
  39 /* mappings for associating views to luts */
  40 static struct tcm *containers[TILFMT_NFORMATS];
  41 static struct dmm *omap_dmm;
  42
  43 /* Geometry table */
  44 #define GEOM(xshift, yshift, bytes_per_pixel) { \
  45                 .x_shft = (xshift), \
  46                 .y_shft = (yshift), \
  47                 .cpp    = (bytes_per_pixel), \
  48                 .slot_w = 1 << (SLOT_WIDTH_BITS - (xshift)), \
  49                 .slot_h = 1 << (SLOT_HEIGHT_BITS - (yshift)), \
  50         }
  51
  52 static const struct {
  53         uint32_t x_shft;        /* unused X-bits (as part of bpp) */
  54         uint32_t y_shft;        /* unused Y-bits (as part of bpp) */
  55         uint32_t cpp;           /* bytes/chars per pixel */
  56         uint32_t slot_w;        /* width of each slot (in pixels) */
  57         uint32_t slot_h;        /* height of each slot (in pixels) */
  58 } geom[TILFMT_NFORMATS] = {
  59                 [TILFMT_8BIT]  = GEOM(0, 0, 1),
  60                 [TILFMT_16BIT] = GEOM(0, 1, 2),
  61                 [TILFMT_32BIT] = GEOM(1, 1, 4),
  62                 [TILFMT_PAGE]  = GEOM(SLOT_WIDTH_BITS, SLOT_HEIGHT_BITS, 1),
  63 };
  64
  65
  66 /* lookup table for registers w/ per-engine instances */
  67 static const uint32_t reg[][4] = {
  68                 [PAT_STATUS] = {DMM_PAT_STATUS__0, DMM_PAT_STATUS__1,
  69                                 DMM_PAT_STATUS__2, DMM_PAT_STATUS__3},
  70                 [PAT_DESCR]  = {DMM_PAT_DESCR__0, DMM_PAT_DESCR__1,
  71                                 DMM_PAT_DESCR__2, DMM_PAT_DESCR__3},
  72 };
  73
  74 /* simple allocator to grab next 16 byte aligned memory from txn */
  75 static void *alloc_dma(struct dmm_txn *txn, size_t sz, dma_addr_t *pa)
  76 {
  77         void *ptr;
  78         struct refill_engine *engine = txn->engine_handle;
  79
  80         /* dmm programming requires 16 byte aligned addresses */
  81         txn->current_pa = round_up(txn->current_pa, 16);
  82         txn->current_va = (void *)round_up((long)txn->current_va, 16);
  83
  84         ptr = txn->current_va;
  85         *pa = txn->current_pa;
  86
  87         txn->current_pa += sz;
  88         txn->current_va += sz;
  89
  90         BUG_ON((txn->current_va - engine->refill_va) > REFILL_BUFFER_SIZE);
  91
  92         return ptr;
  93 }
  94
  95 /* check status and spin until wait_mask comes true */
  96 static int wait_status(struct refill_engine *engine, uint32_t wait_mask)
  97 {
  98         struct dmm *dmm = engine->dmm;
  99         uint32_t r = 0, err, i;
 100
 101         i = DMM_FIXED_RETRY_COUNT;
 102         while (true) {
 103                 r = readl(dmm->base + reg[PAT_STATUS][engine->id]);
 104                 err = r & DMM_PATSTATUS_ERR;
 105                 if (err)
 106                         return -EFAULT;
 107
 108                 if ((r & wait_mask) == wait_mask)
 109                         break;
 110
 111                 if (--i == 0)
 112                         return -ETIMEDOUT;
 113
 114                 udelay(1);
 115         }
 116
 117         return 0;
 118 }
 119
 120 irqreturn_t omap_dmm_irq_handler(int irq, void *arg)
 121 {
 122         struct dmm *dmm = arg;
 123         uint32_t status = readl(dmm->base + DMM_PAT_IRQSTATUS);
 124         int i;
 125
 126         /* ack IRQ */
 127         writel(status, dmm->base + DMM_PAT_IRQSTATUS);
 128
 129         for (i = 0; i < dmm->num_engines; i++) {
 130                 if (status & DMM_IRQSTAT_LST)
 131                         wake_up_interruptible(&dmm->engines[i].wait_for_refill);
 132
 133                 status >>= 8;
 134         }
 135
 136         return IRQ_HANDLED;
 137 }
 138
 139 /**
 140  * Get a handle for a DMM transaction
 141  */
 142 static struct dmm_txn *dmm_txn_init(struct dmm *dmm, struct tcm *tcm)
 143 {
 144         struct dmm_txn *txn = NULL;
 145         struct refill_engine *engine = NULL;
 146
 147         down(&dmm->engine_sem);
 148
 149         /* grab an idle engine */
 150         spin_lock(&dmm->list_lock);
 151         if (!list_empty(&dmm->idle_head)) {
 152                 engine = list_entry(dmm->idle_head.next, struct refill_engine,
 153                                         idle_node);
 154                 list_del(&engine->idle_node);
 155         }
 156         spin_unlock(&dmm->list_lock);
 157
 158         BUG_ON(!engine);
 159
 160         txn = &engine->txn;
 161         engine->tcm = tcm;
 162         txn->engine_handle = engine;
 163         txn->last_pat = NULL;
 164         txn->current_va = engine->refill_va;
 165         txn->current_pa = engine->refill_pa;
 166
 167         return txn;
 168 }
 169
 170 /**
 171  * Add region to DMM transaction.  If pages or pages[i] is NULL, then the
 172  * corresponding slot is cleared (ie. dummy_pa is programmed)
 173  */
 174 static int dmm_txn_append(struct dmm_txn *txn, struct pat_area *area,
 175                 struct page **pages, uint32_t npages, uint32_t roll)
 176 {
 177         dma_addr_t pat_pa = 0;
 178         uint32_t *data;
 179         struct pat *pat;
 180         struct refill_engine *engine = txn->engine_handle;
 181         int columns = (1 + area->x1 - area->x0);
 182         int rows = (1 + area->y1 - area->y0);
 183         int i = columns*rows;
 184         u32 *lut = omap_dmm->lut + (engine->tcm->lut_id * omap_dmm->lut_width *
 185                         omap_dmm->lut_height) +
 186                         (area->y0 * omap_dmm->lut_width) + area->x0;
 187
 188         pat = alloc_dma(txn, sizeof(struct pat), &pat_pa);
 189
 190         if (txn->last_pat)
 191                 txn->last_pat->next_pa = (uint32_t)pat_pa;
 192
 193         pat->area = *area;
 194         pat->ctrl = (struct pat_ctrl){
 195                         .start = 1,
 196                         .lut_id = engine->tcm->lut_id,
 197                 };
 198
 199         data = alloc_dma(txn, 4*i, &pat->data_pa);
 200
 201         while (i--) {
 202                 int n = i + roll;
 203                 if (n >= npages)
 204                         n -= npages;
 205                 data[i] = (pages && pages[n]) ?
 206                         page_to_phys(pages[n]) : engine->dmm->dummy_pa;
 207         }
 208
 209         /* fill in lut with new addresses */
 210         for (i = 0; i < rows; i++, lut += omap_dmm->lut_width)
 211                 memcpy(lut, &data[i*columns], columns * sizeof(u32));
 212
 213         txn->last_pat = pat;
 214
 215         return 0;
 216 }
 217
 218 /**
 219  * Commit the DMM transaction.
 220  */
 221 static int dmm_txn_commit(struct dmm_txn *txn, bool wait)
 222 {
 223         int ret = 0;
 224         struct refill_engine *engine = txn->engine_handle;
 225         struct dmm *dmm = engine->dmm;
 226
 227         if (!txn->last_pat) {
 228                 dev_err(engine->dmm->dev, "need at least one txn\n");
 229                 ret = -EINVAL;
 230                 goto cleanup;
 231         }
 232
 233         txn->last_pat->next_pa = 0;
 234
 235         /* write to PAT_DESCR to clear out any pending transaction */
 236         writel(0x0, dmm->base + reg[PAT_DESCR][engine->id]);
 237
 238         /* wait for engine ready: */
 239         ret = wait_status(engine, DMM_PATSTATUS_READY);
 240         if (ret) {
 241                 ret = -EFAULT;
 242                 goto cleanup;
 243         }
 244
 245         /* kick reload */
 246         writel(engine->refill_pa,
 247                 dmm->base + reg[PAT_DESCR][engine->id]);
 248
 249         if (wait) {
 250                 if (wait_event_interruptible_timeout(engine->wait_for_refill,
 251                                 wait_status(engine, DMM_PATSTATUS_READY) == 0,
 252                                 msecs_to_jiffies(1)) <= 0) {
 253                         dev_err(dmm->dev, "timed out waiting for done\n");
 254                         ret = -ETIMEDOUT;
 255                 }
 256         }
 257
 258 cleanup:
 259         spin_lock(&dmm->list_lock);
 260         list_add(&engine->idle_node, &dmm->idle_head);
 261         spin_unlock(&dmm->list_lock);
 262
 263         up(&omap_dmm->engine_sem);
 264         return ret;
 265 }
 266
 267 /*
 268  * DMM programming
 269  */
 270 static int fill(struct tcm_area *area, struct page **pages,
 271                 uint32_t npages, uint32_t roll, bool wait)
 272 {
 273         int ret = 0;
 274         struct tcm_area slice, area_s;
 275         struct dmm_txn *txn;
 276
 277         txn = dmm_txn_init(omap_dmm, area->tcm);
 278         if (IS_ERR_OR_NULL(txn))
 279                 return PTR_ERR(txn);
 280
 281         tcm_for_each_slice(slice, *area, area_s) {
 282                 struct pat_area p_area = {
 283                                 .x0 = slice.p0.x,  .y0 = slice.p0.y,
 284                                 .x1 = slice.p1.x,  .y1 = slice.p1.y,
 285                 };
 286
 287                 ret = dmm_txn_append(txn, &p_area, pages, npages, roll);
 288                 if (ret)
 289                         goto fail;
 290
 291                 roll += tcm_sizeof(slice);
 292         }
 293
 294         ret = dmm_txn_commit(txn, wait);
 295
 296 fail:
 297         return ret;
 298 }
 299
 300 /*
 301  * Pin/unpin
 302  */
 303
 304 /* note: slots for which pages[i] == NULL are filled w/ dummy page
 305  */
 306 int tiler_pin(struct tiler_block *block, struct page **pages,
 307                 uint32_t npages, uint32_t roll, bool wait)
 308 {
 309         int ret;
 310
 311         ret = fill(&block->area, pages, npages, roll, wait);
 312
 313         if (ret)
 314                 tiler_unpin(block);
 315
 316         return ret;
 317 }
 318
 319 int tiler_unpin(struct tiler_block *block)
 320 {
 321         return fill(&block->area, NULL, 0, 0, false);
 322 }
 323
 324 /*
 325  * Reserve/release
 326  */
 327 struct tiler_block *tiler_reserve_2d(enum tiler_fmt fmt, uint16_t w,
 328                 uint16_t h, uint16_t align)
 329 {
 330         struct tiler_block *block = kzalloc(sizeof(*block), GFP_KERNEL);
 331         u32 min_align = 128;
 332         int ret;
 333
 334         BUG_ON(!validfmt(fmt));
 335
 336         /* convert width/height to slots */
 337         w = DIV_ROUND_UP(w, geom[fmt].slot_w);
 338         h = DIV_ROUND_UP(h, geom[fmt].slot_h);
 339
 340         /* convert alignment to slots */
 341         min_align = max(min_align, (geom[fmt].slot_w * geom[fmt].cpp));
 342         align = ALIGN(align, min_align);
 343         align /= geom[fmt].slot_w * geom[fmt].cpp;
 344
 345         block->fmt = fmt;
 346
 347         ret = tcm_reserve_2d(containers[fmt], w, h, align, &block->area);
 348         if (ret) {
 349                 kfree(block);
 350                 return 0;
 351         }
 352
 353         /* add to allocation list */
 354         spin_lock(&omap_dmm->list_lock);
 355         list_add(&block->alloc_node, &omap_dmm->alloc_head);
 356         spin_unlock(&omap_dmm->list_lock);
 357
 358         return block;
 359 }
 360
 361 struct tiler_block *tiler_reserve_1d(size_t size)
 362 {
 363         struct tiler_block *block = kzalloc(sizeof(*block), GFP_KERNEL);
 364         int num_pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
 365
 366         if (!block)
 367                 return 0;
 368
 369         block->fmt = TILFMT_PAGE;
 370
 371         if (tcm_reserve_1d(containers[TILFMT_PAGE], num_pages,
 372                                 &block->area)) {
 373                 kfree(block);
 374                 return 0;
 375         }
 376
 377         spin_lock(&omap_dmm->list_lock);
 378         list_add(&block->alloc_node, &omap_dmm->alloc_head);
 379         spin_unlock(&omap_dmm->list_lock);
 380
 381         return block;
 382 }
 383
 384 /* note: if you have pin'd pages, you should have already unpin'd first! */
 385 int tiler_release(struct tiler_block *block)
 386 {
 387         int ret = tcm_free(&block->area);
 388
 389         if (block->area.tcm)
 390                 dev_err(omap_dmm->dev, "failed to release block\n");
 391
 392         spin_lock(&omap_dmm->list_lock);
 393         list_del(&block->alloc_node);
 394         spin_unlock(&omap_dmm->list_lock);
 395
 396         kfree(block);
 397         return ret;
 398 }
 399
 400 /*
 401  * Utils
 402  */
 403
 404 /* calculate the tiler space address of a pixel in a view orientation */
 405 static u32 tiler_get_address(u32 orient, enum tiler_fmt fmt, u32 x, u32 y)
 406 {
 407         u32 x_bits, y_bits, tmp, x_mask, y_mask, alignment;
 408
 409         x_bits = CONT_WIDTH_BITS - geom[fmt].x_shft;
 410         y_bits = CONT_HEIGHT_BITS - geom[fmt].y_shft;
 411         alignment = geom[fmt].x_shft + geom[fmt].y_shft;
 412
 413         /* validate coordinate */
 414         x_mask = MASK(x_bits);
 415         y_mask = MASK(y_bits);
 416
 417         if (x < 0 || x > x_mask || y < 0 || y > y_mask)
 418                 return 0;
 419
 420         /* account for mirroring */
 421         if (orient & MASK_X_INVERT)
 422                 x ^= x_mask;
 423         if (orient & MASK_Y_INVERT)
 424                 y ^= y_mask;
 425
 426         /* get coordinate address */
 427         if (orient & MASK_XY_FLIP)
 428                 tmp = ((x << y_bits) + y);
 429         else
 430                 tmp = ((y << x_bits) + x);
 431
 432         return TIL_ADDR((tmp << alignment), orient, fmt);
 433 }
 434
 435 dma_addr_t tiler_ssptr(struct tiler_block *block)
 436 {
 437         BUG_ON(!validfmt(block->fmt));
 438
 439         return TILVIEW_8BIT + tiler_get_address(0, block->fmt,
 440                         block->area.p0.x * geom[block->fmt].slot_w,
 441                         block->area.p0.y * geom[block->fmt].slot_h);
 442 }
 443
 444 void tiler_align(enum tiler_fmt fmt, uint16_t *w, uint16_t *h)
 445 {
 446         BUG_ON(!validfmt(fmt));
 447         *w = round_up(*w, geom[fmt].slot_w);
 448         *h = round_up(*h, geom[fmt].slot_h);
 449 }
 450
 451 uint32_t tiler_stride(enum tiler_fmt fmt)
 452 {
 453         BUG_ON(!validfmt(fmt));
 454
 455         return 1 << (CONT_WIDTH_BITS + geom[fmt].y_shft);
 456 }
 457
 458 size_t tiler_size(enum tiler_fmt fmt, uint16_t w, uint16_t h)
 459 {
 460         tiler_align(fmt, &w, &h);
 461         return geom[fmt].cpp * w * h;
 462 }
 463
 464 size_t tiler_vsize(enum tiler_fmt fmt, uint16_t w, uint16_t h)
 465 {
 466         BUG_ON(!validfmt(fmt));
 467         return round_up(geom[fmt].cpp * w, PAGE_SIZE) * h;
 468 }
 469
 470 bool dmm_is_initialized(void)
 471 {
 472         return omap_dmm ? true : false;
 473 }
 474
 475 static int omap_dmm_remove(struct platform_device *dev)
 476 {
 477         struct tiler_block *block, *_block;
 478         int i;
 479
 480         if (omap_dmm) {
 481                 /* free all area regions */
 482                 spin_lock(&omap_dmm->list_lock);
 483                 list_for_each_entry_safe(block, _block, &omap_dmm->alloc_head,
 484                                         alloc_node) {
 485                         list_del(&block->alloc_node);
 486                         kfree(block);
 487                 }
 488                 spin_unlock(&omap_dmm->list_lock);
 489
 490                 for (i = 0; i < omap_dmm->num_lut; i++)
 491                         if (omap_dmm->tcm && omap_dmm->tcm[i])
 492                                 omap_dmm->tcm[i]->deinit(omap_dmm->tcm[i]);
 493                 kfree(omap_dmm->tcm);
 494
 495                 kfree(omap_dmm->engines);
 496                 if (omap_dmm->refill_va)
 497                         dma_free_coherent(omap_dmm->dev,
 498                                 REFILL_BUFFER_SIZE * omap_dmm->num_engines,
 499                                 omap_dmm->refill_va,
 500                                 omap_dmm->refill_pa);
 501                 if (omap_dmm->dummy_page)
 502                         __free_page(omap_dmm->dummy_page);
 503
 504                 vfree(omap_dmm->lut);
 505
 506                 if (omap_dmm->irq != -1)
 507                         free_irq(omap_dmm->irq, omap_dmm);
 508
 509                 iounmap(omap_dmm->base);
 510                 kfree(omap_dmm);
 511                 omap_dmm = NULL;
 512         }
 513
 514         return 0;
 515 }
 516
 517 static int omap_dmm_probe(struct platform_device *dev)
 518 {
 519         int ret = -EFAULT, i;
 520         struct tcm_area area = {0};
 521         u32 hwinfo, pat_geom, lut_table_size;
 522         struct resource *mem;
 523
 524         omap_dmm = kzalloc(sizeof(*omap_dmm), GFP_KERNEL);
 525         if (!omap_dmm) {
 526                 dev_err(&dev->dev, "failed to allocate driver data section\n");
 527                 goto fail;
 528         }
 529
 530         /* lookup hwmod data - base address and irq */
 531         mem = platform_get_resource(dev, IORESOURCE_MEM, 0);
 532         if (!mem) {
 533                 dev_err(&dev->dev, "failed to get base address resource\n");
 534                 goto fail;
 535         }
 536
 537         omap_dmm->base = ioremap(mem->start, SZ_2K);
 538
 539         if (!omap_dmm->base) {
 540                 dev_err(&dev->dev, "failed to get dmm base address\n");
 541                 goto fail;
 542         }
 543
 544         omap_dmm->irq = platform_get_irq(dev, 0);
 545         if (omap_dmm->irq < 0) {
 546                 dev_err(&dev->dev, "failed to get IRQ resource\n");
 547                 goto fail;
 548         }
 549
 550         omap_dmm->dev = &dev->dev;
 551
 552         hwinfo = readl(omap_dmm->base + DMM_PAT_HWINFO);
 553         omap_dmm->num_engines = (hwinfo >> 24) & 0x1F;
 554         omap_dmm->num_lut = (hwinfo >> 16) & 0x1F;
 555         omap_dmm->container_width = 256;
 556         omap_dmm->container_height = 128;
 557
 558         /* read out actual LUT width and height */
 559         pat_geom = readl(omap_dmm->base + DMM_PAT_GEOMETRY);
 560         omap_dmm->lut_width = ((pat_geom >> 16) & 0xF) << 5;
 561         omap_dmm->lut_height = ((pat_geom >> 24) & 0xF) << 5;
 562
 563         /* initialize DMM registers */
 564         writel(0x88888888, omap_dmm->base + DMM_PAT_VIEW__0);
 565         writel(0x88888888, omap_dmm->base + DMM_PAT_VIEW__1);
 566         writel(0x80808080, omap_dmm->base + DMM_PAT_VIEW_MAP__0);
 567         writel(0x80000000, omap_dmm->base + DMM_PAT_VIEW_MAP_BASE);
 568         writel(0x88888888, omap_dmm->base + DMM_TILER_OR__0);
 569         writel(0x88888888, omap_dmm->base + DMM_TILER_OR__1);
 570
 571         ret = request_irq(omap_dmm->irq, omap_dmm_irq_handler, IRQF_SHARED,
 572                                 "omap_dmm_irq_handler", omap_dmm);
 573
 574         if (ret) {
 575                 dev_err(&dev->dev, "couldn't register IRQ %d, error %d\n",
 576                         omap_dmm->irq, ret);
 577                 omap_dmm->irq = -1;
 578                 goto fail;
 579         }
 580
 581         /* Enable all interrupts for each refill engine except
 582          * ERR_LUT_MISS<n> (which is just advisory, and we don't care
 583          * about because we want to be able to refill live scanout
 584          * buffers for accelerated pan/scroll) and FILL_DSC<n> which
 585          * we just generally don't care about.
 586          */
 587         writel(0x7e7e7e7e, omap_dmm->base + DMM_PAT_IRQENABLE_SET);
 588
 589         lut_table_size = omap_dmm->lut_width * omap_dmm->lut_height *
 590                         omap_dmm->num_lut;
 591
 592         omap_dmm->lut = vmalloc(lut_table_size * sizeof(*omap_dmm->lut));
 593         if (!omap_dmm->lut) {
 594                 dev_err(&dev->dev, "could not allocate lut table\n");
 595                 ret = -ENOMEM;
 596                 goto fail;
 597         }
 598
 599         omap_dmm->dummy_page = alloc_page(GFP_KERNEL | __GFP_DMA32);
 600         if (!omap_dmm->dummy_page) {
 601                 dev_err(&dev->dev, "could not allocate dummy page\n");
 602                 ret = -ENOMEM;
 603                 goto fail;
 604         }
 605
 606         /* set dma mask for device */
 607         /* NOTE: this is a workaround for the hwmod not initializing properly */
 608         dev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
 609
 610         omap_dmm->dummy_pa = page_to_phys(omap_dmm->dummy_page);
 611
 612         /* alloc refill memory */
 613         omap_dmm->refill_va = dma_alloc_coherent(&dev->dev,
 614                                 REFILL_BUFFER_SIZE * omap_dmm->num_engines,
 615                                 &omap_dmm->refill_pa, GFP_KERNEL);
 616         if (!omap_dmm->refill_va) {
 617                 dev_err(&dev->dev, "could not allocate refill memory\n");
 618                 goto fail;
 619         }
 620
 621         /* alloc engines */
 622         omap_dmm->engines = kzalloc(
 623                         omap_dmm->num_engines * sizeof(struct refill_engine),
 624                         GFP_KERNEL);
 625         if (!omap_dmm->engines) {
 626                 dev_err(&dev->dev, "could not allocate engines\n");
 627                 ret = -ENOMEM;
 628                 goto fail;
 629         }
 630
 631         sema_init(&omap_dmm->engine_sem, omap_dmm->num_engines);
 632         INIT_LIST_HEAD(&omap_dmm->idle_head);
 633         for (i = 0; i < omap_dmm->num_engines; i++) {
 634                 omap_dmm->engines[i].id = i;
 635                 omap_dmm->engines[i].dmm = omap_dmm;
 636                 omap_dmm->engines[i].refill_va = omap_dmm->refill_va +
 637                                                 (REFILL_BUFFER_SIZE * i);
 638                 omap_dmm->engines[i].refill_pa = omap_dmm->refill_pa +
 639                                                 (REFILL_BUFFER_SIZE * i);
 640                 init_waitqueue_head(&omap_dmm->engines[i].wait_for_refill);
 641
 642                 list_add(&omap_dmm->engines[i].idle_node, &omap_dmm->idle_head);
 643         }
 644
 645         omap_dmm->tcm = kzalloc(omap_dmm->num_lut * sizeof(*omap_dmm->tcm),
 646                                 GFP_KERNEL);
 647         if (!omap_dmm->tcm) {
 648                 dev_err(&dev->dev, "failed to allocate lut ptrs\n");
 649                 ret = -ENOMEM;
 650                 goto fail;
 651         }
 652
 653         /* init containers */
 654         for (i = 0; i < omap_dmm->num_lut; i++) {
 655                 omap_dmm->tcm[i] = sita_init(omap_dmm->container_width,
 656                                                 omap_dmm->container_height,
 657                                                 NULL);
 658
 659                 if (!omap_dmm->tcm[i]) {
 660                         dev_err(&dev->dev, "failed to allocate container\n");
 661                         ret = -ENOMEM;
 662                         goto fail;
 663                 }
 664
 665                 omap_dmm->tcm[i]->lut_id = i;
 666         }
 667
 668         /* assign access mode containers to applicable tcm container */
 669         /* OMAP 4 has 1 container for all 4 views */
 670         containers[TILFMT_8BIT] = omap_dmm->tcm[0];
 671         containers[TILFMT_16BIT] = omap_dmm->tcm[0];
 672         containers[TILFMT_32BIT] = omap_dmm->tcm[0];
 673         containers[TILFMT_PAGE] = omap_dmm->tcm[0];
 674
 675         INIT_LIST_HEAD(&omap_dmm->alloc_head);
 676         spin_lock_init(&omap_dmm->list_lock);
 677
 678         area = (struct tcm_area) {
 679                 .is2d = true,
 680                 .tcm = NULL,
 681                 .p1.x = omap_dmm->container_width - 1,
 682                 .p1.y = omap_dmm->container_height - 1,
 683         };
 684
 685         for (i = 0; i < lut_table_size; i++)
 686                 omap_dmm->lut[i] = omap_dmm->dummy_pa;
 687
 688         /* initialize all LUTs to dummy page entries */
 689         for (i = 0; i < omap_dmm->num_lut; i++) {
 690                 area.tcm = omap_dmm->tcm[i];
 691                 if (fill(&area, NULL, 0, 0, true))
 692                         dev_err(omap_dmm->dev, "refill failed");
 693         }
 694
 695         dev_info(omap_dmm->dev, "initialized all PAT entries\n");
 696
 697         return 0;
 698
 699 fail:
 700         omap_dmm_remove(dev);
 701         return ret;
 702 }
 703
 704 /*
 705  * debugfs support
 706  */
 707
 708 #ifdef CONFIG_DEBUG_FS
 709
 710 static const char *alphabet = "abcdefghijklmnopqrstuvwxyz"
 711                                 "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789";
 712 static const char *special = ".,:;'\"`~!^-+";
 713
 714 static void fill_map(char **map, int xdiv, int ydiv, struct tcm_area *a,
 715                                                         char c, bool ovw)
 716 {
 717         int x, y;
 718         for (y = a->p0.y / ydiv; y <= a->p1.y / ydiv; y++)
 719                 for (x = a->p0.x / xdiv; x <= a->p1.x / xdiv; x++)
 720                         if (map[y][x] == ' ' || ovw)
 721                                 map[y][x] = c;
 722 }
 723
 724 static void fill_map_pt(char **map, int xdiv, int ydiv, struct tcm_pt *p,
 725                                                                         char c)
 726 {
 727         map[p->y / ydiv][p->x / xdiv] = c;
 728 }
 729
 730 static char read_map_pt(char **map, int xdiv, int ydiv, struct tcm_pt *p)
 731 {
 732         return map[p->y / ydiv][p->x / xdiv];
 733 }
 734
 735 static int map_width(int xdiv, int x0, int x1)
 736 {
 737         return (x1 / xdiv) - (x0 / xdiv) + 1;
 738 }
 739
 740 static void text_map(char **map, int xdiv, char *nice, int yd, int x0, int x1)
 741 {
 742         char *p = map[yd] + (x0 / xdiv);
 743         int w = (map_width(xdiv, x0, x1) - strlen(nice)) / 2;
 744         if (w >= 0) {
 745                 p += w;
 746                 while (*nice)
 747                         *p++ = *nice++;
 748         }
 749 }
 750
 751 static void map_1d_info(char **map, int xdiv, int ydiv, char *nice,
 752                                                         struct tcm_area *a)
 753 {
 754         sprintf(nice, "%dK", tcm_sizeof(*a) * 4);
 755         if (a->p0.y + 1 < a->p1.y) {
 756                 text_map(map, xdiv, nice, (a->p0.y + a->p1.y) / 2 / ydiv, 0,
 757                                                         256 - 1);
 758         } else if (a->p0.y < a->p1.y) {
 759                 if (strlen(nice) < map_width(xdiv, a->p0.x, 256 - 1))
 760                         text_map(map, xdiv, nice, a->p0.y / ydiv,
 761                                         a->p0.x + xdiv, 256 - 1);
 762                 else if (strlen(nice) < map_width(xdiv, 0, a->p1.x))
 763                         text_map(map, xdiv, nice, a->p1.y / ydiv,
 764                                         0, a->p1.y - xdiv);
 765         } else if (strlen(nice) + 1 < map_width(xdiv, a->p0.x, a->p1.x)) {
 766                 text_map(map, xdiv, nice, a->p0.y / ydiv, a->p0.x, a->p1.x);
 767         }
 768 }
 769
 770 static void map_2d_info(char **map, int xdiv, int ydiv, char *nice,
 771                                                         struct tcm_area *a)
 772 {
 773         sprintf(nice, "(%d*%d)", tcm_awidth(*a), tcm_aheight(*a));
 774         if (strlen(nice) + 1 < map_width(xdiv, a->p0.x, a->p1.x))
 775                 text_map(map, xdiv, nice, (a->p0.y + a->p1.y) / 2 / ydiv,
 776                                                         a->p0.x, a->p1.x);
 777 }
 778
 779 int tiler_map_show(struct seq_file *s, void *arg)
 780 {
 781         int xdiv = 2, ydiv = 1;
 782         char **map = NULL, *global_map;
 783         struct tiler_block *block;
 784         struct tcm_area a, p;
 785         int i;
 786         const char *m2d = alphabet;
 787         const char *a2d = special;
 788         const char *m2dp = m2d, *a2dp = a2d;
 789         char nice[128];
 790         int h_adj;
 791         int w_adj;
 792         unsigned long flags;
 793
 794         if (!omap_dmm) {
 795                 /* early return if dmm/tiler device is not initialized */
 796                 return 0;
 797         }
 798
 799         h_adj = omap_dmm->lut_height / ydiv;
 800         w_adj = omap_dmm->lut_width / xdiv;
 801
 802         map = kzalloc(h_adj * sizeof(*map), GFP_KERNEL);
 803         global_map = kzalloc((w_adj + 1) * h_adj, GFP_KERNEL);
 804
 805         if (!map || !global_map)
 806                 goto error;
 807
 808         memset(global_map, ' ', (w_adj + 1) * h_adj);
 809         for (i = 0; i < omap_dmm->lut_height; i++) {
 810                 map[i] = global_map + i * (w_adj + 1);
 811                 map[i][w_adj] = 0;
 812         }
 813         spin_lock_irqsave(&omap_dmm->list_lock, flags);
 814
 815         list_for_each_entry(block, &omap_dmm->alloc_head, alloc_node) {
 816                 if (block->fmt != TILFMT_PAGE) {
 817                         fill_map(map, xdiv, ydiv, &block->area, *m2dp, true);
 818                         if (!*++a2dp)
 819                                 a2dp = a2d;
 820                         if (!*++m2dp)
 821                                 m2dp = m2d;
 822                         map_2d_info(map, xdiv, ydiv, nice, &block->area);
 823                 } else {
 824                         bool start = read_map_pt(map, xdiv, ydiv,
 825                                                         &block->area.p0)
 826                                                                         == ' ';
 827                         bool end = read_map_pt(map, xdiv, ydiv, &block->area.p1)
 828                                                                         == ' ';
 829                         tcm_for_each_slice(a, block->area, p)
 830                                 fill_map(map, xdiv, ydiv, &a, '=', true);
 831                         fill_map_pt(map, xdiv, ydiv, &block->area.p0,
 832                                                         start ? '<' : 'X');
 833                         fill_map_pt(map, xdiv, ydiv, &block->area.p1,
 834                                                         end ? '>' : 'X');
 835                         map_1d_info(map, xdiv, ydiv, nice, &block->area);
 836                 }
 837         }
 838
 839         spin_unlock_irqrestore(&omap_dmm->list_lock, flags);
 840
 841         if (s) {
 842                 seq_printf(s, "BEGIN DMM TILER MAP\n");
 843                 for (i = 0; i < 128; i++)
 844                         seq_printf(s, "%03d:%s\n", i, map[i]);
 845                 seq_printf(s, "END TILER MAP\n");
 846         } else {
 847                 dev_dbg(omap_dmm->dev, "BEGIN DMM TILER MAP\n");
 848                 for (i = 0; i < 128; i++)
 849                         dev_dbg(omap_dmm->dev, "%03d:%s\n", i, map[i]);
 850                 dev_dbg(omap_dmm->dev, "END TILER MAP\n");
 851         }
 852
 853 error:
 854         kfree(map);
 855         kfree(global_map);
 856
 857         return 0;
 858 }
 859 #endif
 860
 861 struct platform_driver omap_dmm_driver = {
 862         .probe = omap_dmm_probe,
 863         .remove = omap_dmm_remove,
 864         .driver = {
 865                 .owner = THIS_MODULE,
 866                 .name = DMM_DRIVER_NAME,
 867         },
 868 };
 869
 870 MODULE_LICENSE("GPL v2");
 871 MODULE_AUTHOR("Andy Gross <andy.gross@ti.com>");
 872 MODULE_DESCRIPTION("OMAP DMM/Tiler Driver");
 873 MODULE_ALIAS("platform:" DMM_DRIVER_NAME);