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44 * Configuration and status register (CSR) type definitions for
47 * This file is auto generated. Do not edit.
52 #ifndef __CVMX_USBNX_TYPEDEFS_H__
53 #define __CVMX_USBNX_TYPEDEFS_H__
55 #define CVMX_USBNXBID1(bid) (((bid) & 1) * 0x10000000ull)
56 #define CVMX_USBNXBID2(bid) (((bid) & 1) * 0x100000000000ull)
58 #define CVMX_USBNXREG1(reg, bid) \
59 (CVMX_ADD_IO_SEG(0x0001180068000000ull | reg) + CVMX_USBNXBID1(bid))
60 #define CVMX_USBNXREG2(reg, bid) \
61 (CVMX_ADD_IO_SEG(0x00016F0000000000ull | reg) + CVMX_USBNXBID2(bid))
63 #define CVMX_USBNX_CLK_CTL(bid) CVMX_USBNXREG1(0x10, bid)
64 #define CVMX_USBNX_DMA0_INB_CHN0(bid) CVMX_USBNXREG2(0x818, bid)
65 #define CVMX_USBNX_DMA0_OUTB_CHN0(bid) CVMX_USBNXREG2(0x858, bid)
66 #define CVMX_USBNX_USBP_CTL_STATUS(bid) CVMX_USBNXREG1(0x18, bid)
71 * USBN_CLK_CTL = USBN's Clock Control
73 * This register is used to control the frequency of the hclk and the hreset and phy_rst signals.
75 union cvmx_usbnx_clk_ctl {
78 * struct cvmx_usbnx_clk_ctl_s
79 * @divide2: The 'hclk' used by the USB subsystem is derived
81 * Also see the field DIVIDE. DIVIDE2<1> must currently
82 * be zero because it is not implemented, so the maximum
83 * ratio of eclk/hclk is currently 16.
84 * The actual divide number for hclk is:
85 * (DIVIDE2 + 1) * (DIVIDE + 1)
86 * @hclk_rst: When this field is '0' the HCLK-DIVIDER used to
87 * generate the hclk in the USB Subsystem is held
88 * in reset. This bit must be set to '0' before
89 * changing the value os DIVIDE in this register.
90 * The reset to the HCLK_DIVIDERis also asserted
91 * when core reset is asserted.
92 * @p_x_on: Force USB-PHY on during suspend.
93 * '1' USB-PHY XO block is powered-down during
95 * '0' USB-PHY XO block is powered-up during
97 * The value of this field must be set while POR is
99 * @p_com_on: '0' Force USB-PHY XO Bias, Bandgap and PLL to
100 * remain powered in Suspend Mode.
101 * '1' The USB-PHY XO Bias, Bandgap and PLL are
102 * powered down in suspend mode.
103 * The value of this field must be set while POR is
105 * @p_c_sel: Phy clock speed select.
106 * Selects the reference clock / crystal frequency.
108 * '10': 48 MHz (reserved when a crystal is used)
109 * '01': 24 MHz (reserved when a crystal is used)
111 * The value of this field must be set while POR is
113 * NOTE: if a crystal is used as a reference clock,
114 * this field must be set to 12 MHz.
115 * @cdiv_byp: Used to enable the bypass input to the USB_CLK_DIV.
116 * @sd_mode: Scaledown mode for the USBC. Control timing events
117 * in the USBC, for normal operation this must be '0'.
118 * @s_bist: Starts bist on the hclk memories, during the '0'
120 * @por: Power On Reset for the PHY.
121 * Resets all the PHYS registers and state machines.
122 * @enable: When '1' allows the generation of the hclk. When
123 * '0' the hclk will not be generated. SEE DIVIDE
124 * field of this register.
125 * @prst: When this field is '0' the reset associated with
126 * the phy_clk functionality in the USB Subsystem is
127 * help in reset. This bit should not be set to '1'
128 * until the time it takes 6 clocks (hclk or phy_clk,
129 * whichever is slower) has passed. Under normal
130 * operation once this bit is set to '1' it should not
132 * @hrst: When this field is '0' the reset associated with
133 * the hclk functioanlity in the USB Subsystem is
134 * held in reset.This bit should not be set to '1'
135 * until 12ms after phy_clk is stable. Under normal
136 * operation, once this bit is set to '1' it should
138 * @divide: The frequency of 'hclk' used by the USB subsystem
139 * is the eclk frequency divided by the value of
140 * (DIVIDE2 + 1) * (DIVIDE + 1), also see the field
141 * DIVIDE2 of this register.
142 * The hclk frequency should be less than 125Mhz.
143 * After writing a value to this field the SW should
144 * read the field for the value written.
145 * The ENABLE field of this register should not be set
146 * until AFTER this field is set and then read.
148 struct cvmx_usbnx_clk_ctl_s {
149 uint64_t reserved_20_63 : 44;
150 uint64_t divide2 : 2;
151 uint64_t hclk_rst : 1;
153 uint64_t reserved_14_15 : 2;
154 uint64_t p_com_on : 1;
155 uint64_t p_c_sel : 2;
156 uint64_t cdiv_byp : 1;
157 uint64_t sd_mode : 2;
166 * struct cvmx_usbnx_clk_ctl_cn30xx
167 * @hclk_rst: When this field is '0' the HCLK-DIVIDER used to
168 * generate the hclk in the USB Subsystem is held
169 * in reset. This bit must be set to '0' before
170 * changing the value os DIVIDE in this register.
171 * The reset to the HCLK_DIVIDERis also asserted
172 * when core reset is asserted.
173 * @p_x_on: Force USB-PHY on during suspend.
174 * '1' USB-PHY XO block is powered-down during
176 * '0' USB-PHY XO block is powered-up during
178 * The value of this field must be set while POR is
180 * @p_rclk: Phy refrence clock enable.
181 * '1' The PHY PLL uses the XO block output as a
184 * @p_xenbn: Phy external clock enable.
185 * '1' The XO block uses the clock from a crystal.
186 * '0' The XO block uses an external clock supplied
187 * on the XO pin. USB_XI should be tied to
188 * ground for this usage.
189 * @p_com_on: '0' Force USB-PHY XO Bias, Bandgap and PLL to
190 * remain powered in Suspend Mode.
191 * '1' The USB-PHY XO Bias, Bandgap and PLL are
192 * powered down in suspend mode.
193 * The value of this field must be set while POR is
195 * @p_c_sel: Phy clock speed select.
196 * Selects the reference clock / crystal frequency.
201 * The value of this field must be set while POR is
203 * @cdiv_byp: Used to enable the bypass input to the USB_CLK_DIV.
204 * @sd_mode: Scaledown mode for the USBC. Control timing events
205 * in the USBC, for normal operation this must be '0'.
206 * @s_bist: Starts bist on the hclk memories, during the '0'
208 * @por: Power On Reset for the PHY.
209 * Resets all the PHYS registers and state machines.
210 * @enable: When '1' allows the generation of the hclk. When
211 * '0' the hclk will not be generated.
212 * @prst: When this field is '0' the reset associated with
213 * the phy_clk functionality in the USB Subsystem is
214 * help in reset. This bit should not be set to '1'
215 * until the time it takes 6 clocks (hclk or phy_clk,
216 * whichever is slower) has passed. Under normal
217 * operation once this bit is set to '1' it should not
219 * @hrst: When this field is '0' the reset associated with
220 * the hclk functioanlity in the USB Subsystem is
221 * held in reset.This bit should not be set to '1'
222 * until 12ms after phy_clk is stable. Under normal
223 * operation, once this bit is set to '1' it should
225 * @divide: The 'hclk' used by the USB subsystem is derived
226 * from the eclk. The eclk will be divided by the
227 * value of this field +1 to determine the hclk
228 * frequency. (Also see HRST of this register).
229 * The hclk frequency must be less than 125 MHz.
231 struct cvmx_usbnx_clk_ctl_cn30xx {
232 uint64_t reserved_18_63 : 46;
233 uint64_t hclk_rst : 1;
236 uint64_t p_xenbn : 1;
237 uint64_t p_com_on : 1;
238 uint64_t p_c_sel : 2;
239 uint64_t cdiv_byp : 1;
240 uint64_t sd_mode : 2;
248 struct cvmx_usbnx_clk_ctl_cn30xx cn31xx;
250 * struct cvmx_usbnx_clk_ctl_cn50xx
251 * @divide2: The 'hclk' used by the USB subsystem is derived
253 * Also see the field DIVIDE. DIVIDE2<1> must currently
254 * be zero because it is not implemented, so the maximum
255 * ratio of eclk/hclk is currently 16.
256 * The actual divide number for hclk is:
257 * (DIVIDE2 + 1) * (DIVIDE + 1)
258 * @hclk_rst: When this field is '0' the HCLK-DIVIDER used to
259 * generate the hclk in the USB Subsystem is held
260 * in reset. This bit must be set to '0' before
261 * changing the value os DIVIDE in this register.
262 * The reset to the HCLK_DIVIDERis also asserted
263 * when core reset is asserted.
264 * @p_rtype: PHY reference clock type
265 * '0' The USB-PHY uses a 12MHz crystal as a clock
266 * source at the USB_XO and USB_XI pins
268 * '2' The USB_PHY uses 12/24/48MHz 2.5V board clock
269 * at the USB_XO pin. USB_XI should be tied to
270 * ground in this case.
272 * (bit 14 was P_XENBN on 3xxx)
273 * (bit 15 was P_RCLK on 3xxx)
274 * @p_com_on: '0' Force USB-PHY XO Bias, Bandgap and PLL to
275 * remain powered in Suspend Mode.
276 * '1' The USB-PHY XO Bias, Bandgap and PLL are
277 * powered down in suspend mode.
278 * The value of this field must be set while POR is
280 * @p_c_sel: Phy clock speed select.
281 * Selects the reference clock / crystal frequency.
283 * '10': 48 MHz (reserved when a crystal is used)
284 * '01': 24 MHz (reserved when a crystal is used)
286 * The value of this field must be set while POR is
288 * NOTE: if a crystal is used as a reference clock,
289 * this field must be set to 12 MHz.
290 * @cdiv_byp: Used to enable the bypass input to the USB_CLK_DIV.
291 * @sd_mode: Scaledown mode for the USBC. Control timing events
292 * in the USBC, for normal operation this must be '0'.
293 * @s_bist: Starts bist on the hclk memories, during the '0'
295 * @por: Power On Reset for the PHY.
296 * Resets all the PHYS registers and state machines.
297 * @enable: When '1' allows the generation of the hclk. When
298 * '0' the hclk will not be generated. SEE DIVIDE
299 * field of this register.
300 * @prst: When this field is '0' the reset associated with
301 * the phy_clk functionality in the USB Subsystem is
302 * help in reset. This bit should not be set to '1'
303 * until the time it takes 6 clocks (hclk or phy_clk,
304 * whichever is slower) has passed. Under normal
305 * operation once this bit is set to '1' it should not
307 * @hrst: When this field is '0' the reset associated with
308 * the hclk functioanlity in the USB Subsystem is
309 * held in reset.This bit should not be set to '1'
310 * until 12ms after phy_clk is stable. Under normal
311 * operation, once this bit is set to '1' it should
313 * @divide: The frequency of 'hclk' used by the USB subsystem
314 * is the eclk frequency divided by the value of
315 * (DIVIDE2 + 1) * (DIVIDE + 1), also see the field
316 * DIVIDE2 of this register.
317 * The hclk frequency should be less than 125Mhz.
318 * After writing a value to this field the SW should
319 * read the field for the value written.
320 * The ENABLE field of this register should not be set
321 * until AFTER this field is set and then read.
323 struct cvmx_usbnx_clk_ctl_cn50xx {
324 uint64_t reserved_20_63 : 44;
325 uint64_t divide2 : 2;
326 uint64_t hclk_rst : 1;
327 uint64_t reserved_16_16 : 1;
328 uint64_t p_rtype : 2;
329 uint64_t p_com_on : 1;
330 uint64_t p_c_sel : 2;
331 uint64_t cdiv_byp : 1;
332 uint64_t sd_mode : 2;
340 struct cvmx_usbnx_clk_ctl_cn50xx cn52xx;
341 struct cvmx_usbnx_clk_ctl_cn50xx cn56xx;
343 typedef union cvmx_usbnx_clk_ctl cvmx_usbnx_clk_ctl_t;
346 * cvmx_usbn#_usbp_ctl_status
348 * USBN_USBP_CTL_STATUS = USBP Control And Status Register
350 * Contains general control and status information for the USBN block.
352 union cvmx_usbnx_usbp_ctl_status {
355 * struct cvmx_usbnx_usbp_ctl_status_s
356 * @txrisetune: HS Transmitter Rise/Fall Time Adjustment
357 * @txvreftune: HS DC Voltage Level Adjustment
358 * @txfslstune: FS/LS Source Impedence Adjustment
359 * @txhsxvtune: Transmitter High-Speed Crossover Adjustment
360 * @sqrxtune: Squelch Threshold Adjustment
361 * @compdistune: Disconnect Threshold Adjustment
362 * @otgtune: VBUS Valid Threshold Adjustment
363 * @otgdisable: OTG Block Disable
364 * @portreset: Per_Port Reset
365 * @drvvbus: Drive VBUS
366 * @lsbist: Low-Speed BIST Enable.
367 * @fsbist: Full-Speed BIST Enable.
368 * @hsbist: High-Speed BIST Enable.
369 * @bist_done: PHY Bist Done.
370 * Asserted at the end of the PHY BIST sequence.
371 * @bist_err: PHY Bist Error.
372 * Indicates an internal error was detected during
374 * @tdata_out: PHY Test Data Out.
375 * Presents either internaly generated signals or
376 * test register contents, based upon the value of
378 * @siddq: Drives the USBP (USB-PHY) SIDDQ input.
379 * Normally should be set to zero.
380 * When customers have no intent to use USB PHY
381 * interface, they should:
382 * - still provide 3.3V to USB_VDD33, and
383 * - tie USB_REXT to 3.3V supply, and
384 * - set USBN*_USBP_CTL_STATUS[SIDDQ]=1
385 * @txpreemphasistune: HS Transmitter Pre-Emphasis Enable
386 * @dma_bmode: When set to 1 the L2C DMA address will be updated
387 * with byte-counts between packets. When set to 0
388 * the L2C DMA address is incremented to the next
389 * 4-byte aligned address after adding byte-count.
390 * @usbc_end: Bigendian input to the USB Core. This should be
391 * set to '0' for operation.
392 * @usbp_bist: PHY, This is cleared '0' to run BIST on the USBP.
393 * @tclk: PHY Test Clock, used to load TDATA_IN to the USBP.
394 * @dp_pulld: PHY DP_PULLDOWN input to the USB-PHY.
395 * This signal enables the pull-down resistance on
396 * the D+ line. '1' pull down-resistance is connected
397 * to D+/ '0' pull down resistance is not connected
398 * to D+. When an A/B device is acting as a host
399 * (downstream-facing port), dp_pulldown and
400 * dm_pulldown are enabled. This must not toggle
401 * during normal opeartion.
402 * @dm_pulld: PHY DM_PULLDOWN input to the USB-PHY.
403 * This signal enables the pull-down resistance on
404 * the D- line. '1' pull down-resistance is connected
405 * to D-. '0' pull down resistance is not connected
406 * to D-. When an A/B device is acting as a host
407 * (downstream-facing port), dp_pulldown and
408 * dm_pulldown are enabled. This must not toggle
409 * during normal opeartion.
410 * @hst_mode: When '0' the USB is acting as HOST, when '1'
411 * USB is acting as device. This field needs to be
412 * set while the USB is in reset.
413 * @tuning: Transmitter Tuning for High-Speed Operation.
414 * Tunes the current supply and rise/fall output
415 * times for high-speed operation.
416 * [20:19] == 11: Current supply increased
418 * [20:19] == 10: Current supply increased
420 * [20:19] == 01: Design default.
421 * [20:19] == 00: Current supply decreased
423 * [22:21] == 11: Rise and fall times are increased.
424 * [22:21] == 10: Design default.
425 * [22:21] == 01: Rise and fall times are decreased.
426 * [22:21] == 00: Rise and fall times are decreased
427 * further as compared to the 01 setting.
428 * @tx_bs_enh: Transmit Bit Stuffing on [15:8].
429 * Enables or disables bit stuffing on data[15:8]
430 * when bit-stuffing is enabled.
431 * @tx_bs_en: Transmit Bit Stuffing on [7:0].
432 * Enables or disables bit stuffing on data[7:0]
433 * when bit-stuffing is enabled.
434 * @loop_enb: PHY Loopback Test Enable.
435 * '1': During data transmission the receive is
437 * '0': During data transmission the receive is
439 * Must be '0' for normal operation.
440 * @vtest_enb: Analog Test Pin Enable.
441 * '1' The PHY's analog_test pin is enabled for the
442 * input and output of applicable analog test signals.
443 * '0' THe analog_test pin is disabled.
444 * @bist_enb: Built-In Self Test Enable.
445 * Used to activate BIST in the PHY.
446 * @tdata_sel: Test Data Out Select.
447 * '1' test_data_out[3:0] (PHY) register contents
448 * are output. '0' internaly generated signals are
450 * @taddr_in: Mode Address for Test Interface.
451 * Specifies the register address for writing to or
452 * reading from the PHY test interface register.
453 * @tdata_in: Internal Testing Register Input Data and Select
454 * This is a test bus. Data is present on [3:0],
455 * and its corresponding select (enable) is present
457 * @ate_reset: Reset input from automatic test equipment.
458 * This is a test signal. When the USB Core is
459 * powered up (not in Susned Mode), an automatic
460 * tester can use this to disable phy_clock and
461 * free_clk, then re-eanable them with an aligned
463 * '1': The phy_clk and free_clk outputs are
464 * disabled. "0": The phy_clock and free_clk outputs
465 * are available within a specific period after the
468 struct cvmx_usbnx_usbp_ctl_status_s {
469 uint64_t txrisetune : 1;
470 uint64_t txvreftune : 4;
471 uint64_t txfslstune : 4;
472 uint64_t txhsxvtune : 2;
473 uint64_t sqrxtune : 3;
474 uint64_t compdistune : 3;
475 uint64_t otgtune : 3;
476 uint64_t otgdisable : 1;
477 uint64_t portreset : 1;
478 uint64_t drvvbus : 1;
482 uint64_t bist_done : 1;
483 uint64_t bist_err : 1;
484 uint64_t tdata_out : 4;
486 uint64_t txpreemphasistune : 1;
487 uint64_t dma_bmode : 1;
488 uint64_t usbc_end : 1;
489 uint64_t usbp_bist : 1;
491 uint64_t dp_pulld : 1;
492 uint64_t dm_pulld : 1;
493 uint64_t hst_mode : 1;
495 uint64_t tx_bs_enh : 1;
496 uint64_t tx_bs_en : 1;
497 uint64_t loop_enb : 1;
498 uint64_t vtest_enb : 1;
499 uint64_t bist_enb : 1;
500 uint64_t tdata_sel : 1;
501 uint64_t taddr_in : 4;
502 uint64_t tdata_in : 8;
503 uint64_t ate_reset : 1;
506 * struct cvmx_usbnx_usbp_ctl_status_cn30xx
507 * @bist_done: PHY Bist Done.
508 * Asserted at the end of the PHY BIST sequence.
509 * @bist_err: PHY Bist Error.
510 * Indicates an internal error was detected during
512 * @tdata_out: PHY Test Data Out.
513 * Presents either internaly generated signals or
514 * test register contents, based upon the value of
516 * @dma_bmode: When set to 1 the L2C DMA address will be updated
517 * with byte-counts between packets. When set to 0
518 * the L2C DMA address is incremented to the next
519 * 4-byte aligned address after adding byte-count.
520 * @usbc_end: Bigendian input to the USB Core. This should be
521 * set to '0' for operation.
522 * @usbp_bist: PHY, This is cleared '0' to run BIST on the USBP.
523 * @tclk: PHY Test Clock, used to load TDATA_IN to the USBP.
524 * @dp_pulld: PHY DP_PULLDOWN input to the USB-PHY.
525 * This signal enables the pull-down resistance on
526 * the D+ line. '1' pull down-resistance is connected
527 * to D+/ '0' pull down resistance is not connected
528 * to D+. When an A/B device is acting as a host
529 * (downstream-facing port), dp_pulldown and
530 * dm_pulldown are enabled. This must not toggle
531 * during normal opeartion.
532 * @dm_pulld: PHY DM_PULLDOWN input to the USB-PHY.
533 * This signal enables the pull-down resistance on
534 * the D- line. '1' pull down-resistance is connected
535 * to D-. '0' pull down resistance is not connected
536 * to D-. When an A/B device is acting as a host
537 * (downstream-facing port), dp_pulldown and
538 * dm_pulldown are enabled. This must not toggle
539 * during normal opeartion.
540 * @hst_mode: When '0' the USB is acting as HOST, when '1'
541 * USB is acting as device. This field needs to be
542 * set while the USB is in reset.
543 * @tuning: Transmitter Tuning for High-Speed Operation.
544 * Tunes the current supply and rise/fall output
545 * times for high-speed operation.
546 * [20:19] == 11: Current supply increased
548 * [20:19] == 10: Current supply increased
550 * [20:19] == 01: Design default.
551 * [20:19] == 00: Current supply decreased
553 * [22:21] == 11: Rise and fall times are increased.
554 * [22:21] == 10: Design default.
555 * [22:21] == 01: Rise and fall times are decreased.
556 * [22:21] == 00: Rise and fall times are decreased
557 * further as compared to the 01 setting.
558 * @tx_bs_enh: Transmit Bit Stuffing on [15:8].
559 * Enables or disables bit stuffing on data[15:8]
560 * when bit-stuffing is enabled.
561 * @tx_bs_en: Transmit Bit Stuffing on [7:0].
562 * Enables or disables bit stuffing on data[7:0]
563 * when bit-stuffing is enabled.
564 * @loop_enb: PHY Loopback Test Enable.
565 * '1': During data transmission the receive is
567 * '0': During data transmission the receive is
569 * Must be '0' for normal operation.
570 * @vtest_enb: Analog Test Pin Enable.
571 * '1' The PHY's analog_test pin is enabled for the
572 * input and output of applicable analog test signals.
573 * '0' THe analog_test pin is disabled.
574 * @bist_enb: Built-In Self Test Enable.
575 * Used to activate BIST in the PHY.
576 * @tdata_sel: Test Data Out Select.
577 * '1' test_data_out[3:0] (PHY) register contents
578 * are output. '0' internaly generated signals are
580 * @taddr_in: Mode Address for Test Interface.
581 * Specifies the register address for writing to or
582 * reading from the PHY test interface register.
583 * @tdata_in: Internal Testing Register Input Data and Select
584 * This is a test bus. Data is present on [3:0],
585 * and its corresponding select (enable) is present
587 * @ate_reset: Reset input from automatic test equipment.
588 * This is a test signal. When the USB Core is
589 * powered up (not in Susned Mode), an automatic
590 * tester can use this to disable phy_clock and
591 * free_clk, then re-eanable them with an aligned
593 * '1': The phy_clk and free_clk outputs are
594 * disabled. "0": The phy_clock and free_clk outputs
595 * are available within a specific period after the
598 struct cvmx_usbnx_usbp_ctl_status_cn30xx {
599 uint64_t reserved_38_63 : 26;
600 uint64_t bist_done : 1;
601 uint64_t bist_err : 1;
602 uint64_t tdata_out : 4;
603 uint64_t reserved_30_31 : 2;
604 uint64_t dma_bmode : 1;
605 uint64_t usbc_end : 1;
606 uint64_t usbp_bist : 1;
608 uint64_t dp_pulld : 1;
609 uint64_t dm_pulld : 1;
610 uint64_t hst_mode : 1;
612 uint64_t tx_bs_enh : 1;
613 uint64_t tx_bs_en : 1;
614 uint64_t loop_enb : 1;
615 uint64_t vtest_enb : 1;
616 uint64_t bist_enb : 1;
617 uint64_t tdata_sel : 1;
618 uint64_t taddr_in : 4;
619 uint64_t tdata_in : 8;
620 uint64_t ate_reset : 1;
623 * struct cvmx_usbnx_usbp_ctl_status_cn50xx
624 * @txrisetune: HS Transmitter Rise/Fall Time Adjustment
625 * @txvreftune: HS DC Voltage Level Adjustment
626 * @txfslstune: FS/LS Source Impedence Adjustment
627 * @txhsxvtune: Transmitter High-Speed Crossover Adjustment
628 * @sqrxtune: Squelch Threshold Adjustment
629 * @compdistune: Disconnect Threshold Adjustment
630 * @otgtune: VBUS Valid Threshold Adjustment
631 * @otgdisable: OTG Block Disable
632 * @portreset: Per_Port Reset
633 * @drvvbus: Drive VBUS
634 * @lsbist: Low-Speed BIST Enable.
635 * @fsbist: Full-Speed BIST Enable.
636 * @hsbist: High-Speed BIST Enable.
637 * @bist_done: PHY Bist Done.
638 * Asserted at the end of the PHY BIST sequence.
639 * @bist_err: PHY Bist Error.
640 * Indicates an internal error was detected during
642 * @tdata_out: PHY Test Data Out.
643 * Presents either internaly generated signals or
644 * test register contents, based upon the value of
646 * @txpreemphasistune: HS Transmitter Pre-Emphasis Enable
647 * @dma_bmode: When set to 1 the L2C DMA address will be updated
648 * with byte-counts between packets. When set to 0
649 * the L2C DMA address is incremented to the next
650 * 4-byte aligned address after adding byte-count.
651 * @usbc_end: Bigendian input to the USB Core. This should be
652 * set to '0' for operation.
653 * @usbp_bist: PHY, This is cleared '0' to run BIST on the USBP.
654 * @tclk: PHY Test Clock, used to load TDATA_IN to the USBP.
655 * @dp_pulld: PHY DP_PULLDOWN input to the USB-PHY.
656 * This signal enables the pull-down resistance on
657 * the D+ line. '1' pull down-resistance is connected
658 * to D+/ '0' pull down resistance is not connected
659 * to D+. When an A/B device is acting as a host
660 * (downstream-facing port), dp_pulldown and
661 * dm_pulldown are enabled. This must not toggle
662 * during normal opeartion.
663 * @dm_pulld: PHY DM_PULLDOWN input to the USB-PHY.
664 * This signal enables the pull-down resistance on
665 * the D- line. '1' pull down-resistance is connected
666 * to D-. '0' pull down resistance is not connected
667 * to D-. When an A/B device is acting as a host
668 * (downstream-facing port), dp_pulldown and
669 * dm_pulldown are enabled. This must not toggle
670 * during normal opeartion.
671 * @hst_mode: When '0' the USB is acting as HOST, when '1'
672 * USB is acting as device. This field needs to be
673 * set while the USB is in reset.
674 * @tx_bs_enh: Transmit Bit Stuffing on [15:8].
675 * Enables or disables bit stuffing on data[15:8]
676 * when bit-stuffing is enabled.
677 * @tx_bs_en: Transmit Bit Stuffing on [7:0].
678 * Enables or disables bit stuffing on data[7:0]
679 * when bit-stuffing is enabled.
680 * @loop_enb: PHY Loopback Test Enable.
681 * '1': During data transmission the receive is
683 * '0': During data transmission the receive is
685 * Must be '0' for normal operation.
686 * @vtest_enb: Analog Test Pin Enable.
687 * '1' The PHY's analog_test pin is enabled for the
688 * input and output of applicable analog test signals.
689 * '0' THe analog_test pin is disabled.
690 * @bist_enb: Built-In Self Test Enable.
691 * Used to activate BIST in the PHY.
692 * @tdata_sel: Test Data Out Select.
693 * '1' test_data_out[3:0] (PHY) register contents
694 * are output. '0' internaly generated signals are
696 * @taddr_in: Mode Address for Test Interface.
697 * Specifies the register address for writing to or
698 * reading from the PHY test interface register.
699 * @tdata_in: Internal Testing Register Input Data and Select
700 * This is a test bus. Data is present on [3:0],
701 * and its corresponding select (enable) is present
703 * @ate_reset: Reset input from automatic test equipment.
704 * This is a test signal. When the USB Core is
705 * powered up (not in Susned Mode), an automatic
706 * tester can use this to disable phy_clock and
707 * free_clk, then re-eanable them with an aligned
709 * '1': The phy_clk and free_clk outputs are
710 * disabled. "0": The phy_clock and free_clk outputs
711 * are available within a specific period after the
714 struct cvmx_usbnx_usbp_ctl_status_cn50xx {
715 uint64_t txrisetune : 1;
716 uint64_t txvreftune : 4;
717 uint64_t txfslstune : 4;
718 uint64_t txhsxvtune : 2;
719 uint64_t sqrxtune : 3;
720 uint64_t compdistune : 3;
721 uint64_t otgtune : 3;
722 uint64_t otgdisable : 1;
723 uint64_t portreset : 1;
724 uint64_t drvvbus : 1;
728 uint64_t bist_done : 1;
729 uint64_t bist_err : 1;
730 uint64_t tdata_out : 4;
731 uint64_t reserved_31_31 : 1;
732 uint64_t txpreemphasistune : 1;
733 uint64_t dma_bmode : 1;
734 uint64_t usbc_end : 1;
735 uint64_t usbp_bist : 1;
737 uint64_t dp_pulld : 1;
738 uint64_t dm_pulld : 1;
739 uint64_t hst_mode : 1;
740 uint64_t reserved_19_22 : 4;
741 uint64_t tx_bs_enh : 1;
742 uint64_t tx_bs_en : 1;
743 uint64_t loop_enb : 1;
744 uint64_t vtest_enb : 1;
745 uint64_t bist_enb : 1;
746 uint64_t tdata_sel : 1;
747 uint64_t taddr_in : 4;
748 uint64_t tdata_in : 8;
749 uint64_t ate_reset : 1;
752 * struct cvmx_usbnx_usbp_ctl_status_cn52xx
753 * @txrisetune: HS Transmitter Rise/Fall Time Adjustment
754 * @txvreftune: HS DC Voltage Level Adjustment
755 * @txfslstune: FS/LS Source Impedence Adjustment
756 * @txhsxvtune: Transmitter High-Speed Crossover Adjustment
757 * @sqrxtune: Squelch Threshold Adjustment
758 * @compdistune: Disconnect Threshold Adjustment
759 * @otgtune: VBUS Valid Threshold Adjustment
760 * @otgdisable: OTG Block Disable
761 * @portreset: Per_Port Reset
762 * @drvvbus: Drive VBUS
763 * @lsbist: Low-Speed BIST Enable.
764 * @fsbist: Full-Speed BIST Enable.
765 * @hsbist: High-Speed BIST Enable.
766 * @bist_done: PHY Bist Done.
767 * Asserted at the end of the PHY BIST sequence.
768 * @bist_err: PHY Bist Error.
769 * Indicates an internal error was detected during
771 * @tdata_out: PHY Test Data Out.
772 * Presents either internaly generated signals or
773 * test register contents, based upon the value of
775 * @siddq: Drives the USBP (USB-PHY) SIDDQ input.
776 * Normally should be set to zero.
777 * When customers have no intent to use USB PHY
778 * interface, they should:
779 * - still provide 3.3V to USB_VDD33, and
780 * - tie USB_REXT to 3.3V supply, and
781 * - set USBN*_USBP_CTL_STATUS[SIDDQ]=1
782 * @txpreemphasistune: HS Transmitter Pre-Emphasis Enable
783 * @dma_bmode: When set to 1 the L2C DMA address will be updated
784 * with byte-counts between packets. When set to 0
785 * the L2C DMA address is incremented to the next
786 * 4-byte aligned address after adding byte-count.
787 * @usbc_end: Bigendian input to the USB Core. This should be
788 * set to '0' for operation.
789 * @usbp_bist: PHY, This is cleared '0' to run BIST on the USBP.
790 * @tclk: PHY Test Clock, used to load TDATA_IN to the USBP.
791 * @dp_pulld: PHY DP_PULLDOWN input to the USB-PHY.
792 * This signal enables the pull-down resistance on
793 * the D+ line. '1' pull down-resistance is connected
794 * to D+/ '0' pull down resistance is not connected
795 * to D+. When an A/B device is acting as a host
796 * (downstream-facing port), dp_pulldown and
797 * dm_pulldown are enabled. This must not toggle
798 * during normal opeartion.
799 * @dm_pulld: PHY DM_PULLDOWN input to the USB-PHY.
800 * This signal enables the pull-down resistance on
801 * the D- line. '1' pull down-resistance is connected
802 * to D-. '0' pull down resistance is not connected
803 * to D-. When an A/B device is acting as a host
804 * (downstream-facing port), dp_pulldown and
805 * dm_pulldown are enabled. This must not toggle
806 * during normal opeartion.
807 * @hst_mode: When '0' the USB is acting as HOST, when '1'
808 * USB is acting as device. This field needs to be
809 * set while the USB is in reset.
810 * @tx_bs_enh: Transmit Bit Stuffing on [15:8].
811 * Enables or disables bit stuffing on data[15:8]
812 * when bit-stuffing is enabled.
813 * @tx_bs_en: Transmit Bit Stuffing on [7:0].
814 * Enables or disables bit stuffing on data[7:0]
815 * when bit-stuffing is enabled.
816 * @loop_enb: PHY Loopback Test Enable.
817 * '1': During data transmission the receive is
819 * '0': During data transmission the receive is
821 * Must be '0' for normal operation.
822 * @vtest_enb: Analog Test Pin Enable.
823 * '1' The PHY's analog_test pin is enabled for the
824 * input and output of applicable analog test signals.
825 * '0' THe analog_test pin is disabled.
826 * @bist_enb: Built-In Self Test Enable.
827 * Used to activate BIST in the PHY.
828 * @tdata_sel: Test Data Out Select.
829 * '1' test_data_out[3:0] (PHY) register contents
830 * are output. '0' internaly generated signals are
832 * @taddr_in: Mode Address for Test Interface.
833 * Specifies the register address for writing to or
834 * reading from the PHY test interface register.
835 * @tdata_in: Internal Testing Register Input Data and Select
836 * This is a test bus. Data is present on [3:0],
837 * and its corresponding select (enable) is present
839 * @ate_reset: Reset input from automatic test equipment.
840 * This is a test signal. When the USB Core is
841 * powered up (not in Susned Mode), an automatic
842 * tester can use this to disable phy_clock and
843 * free_clk, then re-eanable them with an aligned
845 * '1': The phy_clk and free_clk outputs are
846 * disabled. "0": The phy_clock and free_clk outputs
847 * are available within a specific period after the
850 struct cvmx_usbnx_usbp_ctl_status_cn52xx {
851 uint64_t txrisetune : 1;
852 uint64_t txvreftune : 4;
853 uint64_t txfslstune : 4;
854 uint64_t txhsxvtune : 2;
855 uint64_t sqrxtune : 3;
856 uint64_t compdistune : 3;
857 uint64_t otgtune : 3;
858 uint64_t otgdisable : 1;
859 uint64_t portreset : 1;
860 uint64_t drvvbus : 1;
864 uint64_t bist_done : 1;
865 uint64_t bist_err : 1;
866 uint64_t tdata_out : 4;
868 uint64_t txpreemphasistune : 1;
869 uint64_t dma_bmode : 1;
870 uint64_t usbc_end : 1;
871 uint64_t usbp_bist : 1;
873 uint64_t dp_pulld : 1;
874 uint64_t dm_pulld : 1;
875 uint64_t hst_mode : 1;
876 uint64_t reserved_19_22 : 4;
877 uint64_t tx_bs_enh : 1;
878 uint64_t tx_bs_en : 1;
879 uint64_t loop_enb : 1;
880 uint64_t vtest_enb : 1;
881 uint64_t bist_enb : 1;
882 uint64_t tdata_sel : 1;
883 uint64_t taddr_in : 4;
884 uint64_t tdata_in : 8;
885 uint64_t ate_reset : 1;
888 typedef union cvmx_usbnx_usbp_ctl_status cvmx_usbnx_usbp_ctl_status_t;