2 * Copyright 2011 Analog Devices Inc.
4 * Licensed under the GPL-2.
8 #include <linux/kernel.h>
9 #include <linux/module.h>
10 #include <linux/platform_device.h>
11 #include <linux/slab.h>
12 #include <linux/interrupt.h>
13 #include <linux/irq.h>
14 #include <linux/delay.h>
16 #include <asm/gptimers.h>
17 #include <asm/portmux.h>
19 #include <linux/iio/iio.h>
20 #include <linux/iio/trigger.h>
22 #include "iio-trig-bfin-timer.h"
25 unsigned short id, bit;
32 * this covers all hardware timer configurations on
33 * all Blackfin derivatives out there today
36 static struct bfin_timer iio_bfin_timer_code[MAX_BLACKFIN_GPTIMERS] = {
37 {TIMER0_id, TIMER0bit, TIMER_STATUS_TIMIL0, IRQ_TIMER0, P_TMR0},
38 {TIMER1_id, TIMER1bit, TIMER_STATUS_TIMIL1, IRQ_TIMER1, P_TMR1},
39 {TIMER2_id, TIMER2bit, TIMER_STATUS_TIMIL2, IRQ_TIMER2, P_TMR2},
40 #if (MAX_BLACKFIN_GPTIMERS > 3)
41 {TIMER3_id, TIMER3bit, TIMER_STATUS_TIMIL3, IRQ_TIMER3, P_TMR3},
42 {TIMER4_id, TIMER4bit, TIMER_STATUS_TIMIL4, IRQ_TIMER4, P_TMR4},
43 {TIMER5_id, TIMER5bit, TIMER_STATUS_TIMIL5, IRQ_TIMER5, P_TMR5},
44 {TIMER6_id, TIMER6bit, TIMER_STATUS_TIMIL6, IRQ_TIMER6, P_TMR6},
45 {TIMER7_id, TIMER7bit, TIMER_STATUS_TIMIL7, IRQ_TIMER7, P_TMR7},
47 #if (MAX_BLACKFIN_GPTIMERS > 8)
48 {TIMER8_id, TIMER8bit, TIMER_STATUS_TIMIL8, IRQ_TIMER8, P_TMR8},
49 {TIMER9_id, TIMER9bit, TIMER_STATUS_TIMIL9, IRQ_TIMER9, P_TMR9},
50 {TIMER10_id, TIMER10bit, TIMER_STATUS_TIMIL10, IRQ_TIMER10, P_TMR10},
51 #if (MAX_BLACKFIN_GPTIMERS > 11)
52 {TIMER11_id, TIMER11bit, TIMER_STATUS_TIMIL11, IRQ_TIMER11, P_TMR11},
57 struct bfin_tmr_state {
58 struct iio_trigger *trig;
66 static int iio_bfin_tmr_set_state(struct iio_trigger *trig, bool state)
68 struct bfin_tmr_state *st = trig->private_data;
70 if (get_gptimer_period(st->t->id) == 0)
74 enable_gptimers(st->t->bit);
76 disable_gptimers(st->t->bit);
81 static ssize_t iio_bfin_tmr_frequency_store(struct device *dev,
82 struct device_attribute *attr, const char *buf, size_t count)
84 struct iio_trigger *trig = to_iio_trigger(dev);
85 struct bfin_tmr_state *st = trig->private_data;
90 ret = strict_strtoul(buf, 10, &val);
99 enabled = get_enabled_gptimers() & st->t->bit;
102 disable_gptimers(st->t->bit);
107 val = get_sclk() / val;
108 if (val <= 4 || val <= st->duty) {
113 set_gptimer_period(st->t->id, val);
114 set_gptimer_pwidth(st->t->id, val - st->duty);
117 enable_gptimers(st->t->bit);
120 return ret ? ret : count;
123 static ssize_t iio_bfin_tmr_frequency_show(struct device *dev,
124 struct device_attribute *attr,
127 struct iio_trigger *trig = to_iio_trigger(dev);
128 struct bfin_tmr_state *st = trig->private_data;
129 unsigned int period = get_gptimer_period(st->t->id);
135 val = get_sclk() / get_gptimer_period(st->t->id);
137 return sprintf(buf, "%lu\n", val);
140 static DEVICE_ATTR(frequency, S_IRUGO | S_IWUSR, iio_bfin_tmr_frequency_show,
141 iio_bfin_tmr_frequency_store);
143 static struct attribute *iio_bfin_tmr_trigger_attrs[] = {
144 &dev_attr_frequency.attr,
148 static const struct attribute_group iio_bfin_tmr_trigger_attr_group = {
149 .attrs = iio_bfin_tmr_trigger_attrs,
152 static const struct attribute_group *iio_bfin_tmr_trigger_attr_groups[] = {
153 &iio_bfin_tmr_trigger_attr_group,
157 static irqreturn_t iio_bfin_tmr_trigger_isr(int irq, void *devid)
159 struct bfin_tmr_state *st = devid;
161 clear_gptimer_intr(st->t->id);
162 iio_trigger_poll(st->trig, 0);
167 static int iio_bfin_tmr_get_number(int irq)
171 for (i = 0; i < MAX_BLACKFIN_GPTIMERS; i++)
172 if (iio_bfin_timer_code[i].irq == irq)
178 static const struct iio_trigger_ops iio_bfin_tmr_trigger_ops = {
179 .owner = THIS_MODULE,
180 .set_trigger_state = iio_bfin_tmr_set_state,
183 static int iio_bfin_tmr_trigger_probe(struct platform_device *pdev)
185 struct iio_bfin_timer_trigger_pdata *pdata = pdev->dev.platform_data;
186 struct bfin_tmr_state *st;
190 st = kzalloc(sizeof(*st), GFP_KERNEL);
196 st->irq = platform_get_irq(pdev, 0);
198 dev_err(&pdev->dev, "No IRQs specified");
203 ret = iio_bfin_tmr_get_number(st->irq);
208 st->t = &iio_bfin_timer_code[st->timer_num];
210 st->trig = iio_trigger_alloc("bfintmr%d", st->timer_num);
216 st->trig->private_data = st;
217 st->trig->ops = &iio_bfin_tmr_trigger_ops;
218 st->trig->dev.groups = iio_bfin_tmr_trigger_attr_groups;
219 ret = iio_trigger_register(st->trig);
223 ret = request_irq(st->irq, iio_bfin_tmr_trigger_isr,
224 0, st->trig->name, st);
227 "request IRQ-%d failed", st->irq);
231 config = PWM_OUT | PERIOD_CNT | IRQ_ENA;
233 if (pdata && pdata->output_enable) {
234 unsigned long long val;
236 st->output_enable = true;
238 ret = peripheral_request(st->t->pin, st->trig->name);
242 val = (unsigned long long)get_sclk() * pdata->duty_ns;
243 do_div(val, NSEC_PER_SEC);
247 * The interrupt will be generated at the end of the period,
248 * since we want the interrupt to be generated at end of the
249 * pulse we invert both polarity and duty cycle, so that the
250 * pulse will be generated directly before the interrupt.
252 if (pdata->active_low)
259 set_gptimer_config(st->t->id, config);
261 dev_info(&pdev->dev, "iio trigger Blackfin TMR%d, IRQ-%d",
262 st->timer_num, st->irq);
263 platform_set_drvdata(pdev, st);
267 free_irq(st->irq, st);
269 iio_trigger_unregister(st->trig);
271 iio_trigger_put(st->trig);
278 static int iio_bfin_tmr_trigger_remove(struct platform_device *pdev)
280 struct bfin_tmr_state *st = platform_get_drvdata(pdev);
282 disable_gptimers(st->t->bit);
283 if (st->output_enable)
284 peripheral_free(st->t->pin);
285 free_irq(st->irq, st);
286 iio_trigger_unregister(st->trig);
287 iio_trigger_put(st->trig);
293 static struct platform_driver iio_bfin_tmr_trigger_driver = {
295 .name = "iio_bfin_tmr_trigger",
296 .owner = THIS_MODULE,
298 .probe = iio_bfin_tmr_trigger_probe,
299 .remove = iio_bfin_tmr_trigger_remove,
302 module_platform_driver(iio_bfin_tmr_trigger_driver);
304 MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
305 MODULE_DESCRIPTION("Blackfin system timer based trigger for the iio subsystem");
306 MODULE_LICENSE("GPL v2");
307 MODULE_ALIAS("platform:iio-trig-bfin-timer");