2 * AD9832 SPI DDS driver
4 * Copyright 2011 Analog Devices Inc.
6 * Licensed under the GPL-2.
9 #include <linux/device.h>
10 #include <linux/kernel.h>
11 #include <linux/slab.h>
12 #include <linux/sysfs.h>
13 #include <linux/spi/spi.h>
14 #include <linux/regulator/consumer.h>
15 #include <linux/err.h>
16 #include <asm/div64.h>
24 static unsigned long ad9832_calc_freqreg(unsigned long mclk, unsigned long fout)
26 unsigned long long freqreg = (u64) fout *
27 (u64) ((u64) 1L << AD9832_FREQ_BITS);
28 do_div(freqreg, mclk);
32 static int ad9832_write_frequency(struct ad9832_state *st,
33 unsigned addr, unsigned long fout)
37 if (fout > (st->mclk / 2))
40 regval = ad9832_calc_freqreg(st->mclk, fout);
42 st->freq_data[0] = cpu_to_be16((AD9832_CMD_FRE8BITSW << CMD_SHIFT) |
44 ((regval >> 24) & 0xFF));
45 st->freq_data[1] = cpu_to_be16((AD9832_CMD_FRE16BITSW << CMD_SHIFT) |
46 ((addr - 1) << ADD_SHIFT) |
47 ((regval >> 16) & 0xFF));
48 st->freq_data[2] = cpu_to_be16((AD9832_CMD_FRE8BITSW << CMD_SHIFT) |
49 ((addr - 2) << ADD_SHIFT) |
50 ((regval >> 8) & 0xFF));
51 st->freq_data[3] = cpu_to_be16((AD9832_CMD_FRE16BITSW << CMD_SHIFT) |
52 ((addr - 3) << ADD_SHIFT) |
53 ((regval >> 0) & 0xFF));
55 return spi_sync(st->spi, &st->freq_msg);;
58 static int ad9832_write_phase(struct ad9832_state *st,
59 unsigned long addr, unsigned long phase)
61 if (phase > (1 << AD9832_PHASE_BITS))
64 st->phase_data[0] = cpu_to_be16((AD9832_CMD_PHA8BITSW << CMD_SHIFT) |
66 ((phase >> 8) & 0xFF));
67 st->phase_data[1] = cpu_to_be16((AD9832_CMD_PHA16BITSW << CMD_SHIFT) |
68 ((addr - 1) << ADD_SHIFT) |
71 return spi_sync(st->spi, &st->phase_msg);
74 static ssize_t ad9832_write(struct device *dev,
75 struct device_attribute *attr,
79 struct iio_dev *dev_info = dev_get_drvdata(dev);
80 struct ad9832_state *st = dev_info->dev_data;
81 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
85 ret = strict_strtoul(buf, 10, &val);
89 mutex_lock(&dev_info->mlock);
90 switch (this_attr->address) {
93 ret = ad9832_write_frequency(st, this_attr->address, val);
99 ret = ad9832_write_phase(st, this_attr->address, val);
101 case AD9832_PINCTRL_EN:
103 st->ctrl_ss &= ~AD9832_SELSRC;
105 st->ctrl_ss |= AD9832_SELSRC;
106 st->data = cpu_to_be16((AD9832_CMD_SYNCSELSRC << CMD_SHIFT) |
108 ret = spi_sync(st->spi, &st->msg);
110 case AD9832_FREQ_SYM:
112 st->ctrl_fp |= AD9832_FREQ;
114 st->ctrl_fp &= ~AD9832_FREQ;
119 st->data = cpu_to_be16((AD9832_CMD_FPSELECT << CMD_SHIFT) |
121 ret = spi_sync(st->spi, &st->msg);
123 case AD9832_PHASE_SYM:
124 if (val < 0 || val > 3) {
129 st->ctrl_fp &= ~AD9832_PHASE(3);
130 st->ctrl_fp |= AD9832_PHASE(val);
132 st->data = cpu_to_be16((AD9832_CMD_FPSELECT << CMD_SHIFT) |
134 ret = spi_sync(st->spi, &st->msg);
136 case AD9832_OUTPUT_EN:
138 st->ctrl_src &= ~(AD9832_RESET | AD9832_SLEEP |
141 st->ctrl_src |= AD9832_RESET;
143 st->data = cpu_to_be16((AD9832_CMD_SLEEPRESCLR << CMD_SHIFT) |
145 ret = spi_sync(st->spi, &st->msg);
150 mutex_unlock(&dev_info->mlock);
153 return ret ? ret : len;
157 * see dds.h for further information
160 static IIO_DEV_ATTR_FREQ(0, 0, S_IWUSR, NULL, ad9832_write, AD9832_FREQ0HM);
161 static IIO_DEV_ATTR_FREQ(0, 1, S_IWUSR, NULL, ad9832_write, AD9832_FREQ1HM);
162 static IIO_DEV_ATTR_FREQSYMBOL(0, S_IWUSR, NULL, ad9832_write, AD9832_FREQ_SYM);
163 static IIO_CONST_ATTR_FREQ_SCALE(0, "1"); /* 1Hz */
165 static IIO_DEV_ATTR_PHASE(0, 0, S_IWUSR, NULL, ad9832_write, AD9832_PHASE0H);
166 static IIO_DEV_ATTR_PHASE(0, 1, S_IWUSR, NULL, ad9832_write, AD9832_PHASE1H);
167 static IIO_DEV_ATTR_PHASE(0, 2, S_IWUSR, NULL, ad9832_write, AD9832_PHASE2H);
168 static IIO_DEV_ATTR_PHASE(0, 3, S_IWUSR, NULL, ad9832_write, AD9832_PHASE3H);
169 static IIO_DEV_ATTR_PHASESYMBOL(0, S_IWUSR, NULL,
170 ad9832_write, AD9832_PHASE_SYM);
171 static IIO_CONST_ATTR_PHASE_SCALE(0, "0.0015339808"); /* 2PI/2^12 rad*/
173 static IIO_DEV_ATTR_PINCONTROL_EN(0, S_IWUSR, NULL,
174 ad9832_write, AD9832_PINCTRL_EN);
175 static IIO_DEV_ATTR_OUT_ENABLE(0, S_IWUSR, NULL,
176 ad9832_write, AD9832_OUTPUT_EN);
178 static struct attribute *ad9832_attributes[] = {
179 &iio_dev_attr_dds0_freq0.dev_attr.attr,
180 &iio_dev_attr_dds0_freq1.dev_attr.attr,
181 &iio_const_attr_dds0_freq_scale.dev_attr.attr,
182 &iio_dev_attr_dds0_phase0.dev_attr.attr,
183 &iio_dev_attr_dds0_phase1.dev_attr.attr,
184 &iio_dev_attr_dds0_phase2.dev_attr.attr,
185 &iio_dev_attr_dds0_phase3.dev_attr.attr,
186 &iio_const_attr_dds0_phase_scale.dev_attr.attr,
187 &iio_dev_attr_dds0_pincontrol_en.dev_attr.attr,
188 &iio_dev_attr_dds0_freqsymbol.dev_attr.attr,
189 &iio_dev_attr_dds0_phasesymbol.dev_attr.attr,
190 &iio_dev_attr_dds0_out_enable.dev_attr.attr,
194 static const struct attribute_group ad9832_attribute_group = {
195 .attrs = ad9832_attributes,
198 static const struct iio_info ad9832_info = {
199 .attrs = &ad9832_attribute_group,
200 .driver_module = THIS_MODULE,
203 static int __devinit ad9832_probe(struct spi_device *spi)
205 struct ad9832_platform_data *pdata = spi->dev.platform_data;
206 struct ad9832_state *st;
210 dev_dbg(&spi->dev, "no platform data?\n");
214 st = kzalloc(sizeof(*st), GFP_KERNEL);
220 st->reg = regulator_get(&spi->dev, "vcc");
221 if (!IS_ERR(st->reg)) {
222 ret = regulator_enable(st->reg);
227 st->mclk = pdata->mclk;
229 spi_set_drvdata(spi, st);
232 st->indio_dev = iio_allocate_device(0);
233 if (st->indio_dev == NULL) {
235 goto error_disable_reg;
238 st->indio_dev->dev.parent = &spi->dev;
239 st->indio_dev->name = spi_get_device_id(spi)->name;
240 st->indio_dev->info = &ad9832_info;
241 st->indio_dev->dev_data = (void *) st;
242 st->indio_dev->modes = INDIO_DIRECT_MODE;
244 /* Setup default messages */
246 st->xfer.tx_buf = &st->data;
249 spi_message_init(&st->msg);
250 spi_message_add_tail(&st->xfer, &st->msg);
252 st->freq_xfer[0].tx_buf = &st->freq_data[0];
253 st->freq_xfer[0].len = 2;
254 st->freq_xfer[0].cs_change = 1;
255 st->freq_xfer[1].tx_buf = &st->freq_data[1];
256 st->freq_xfer[1].len = 2;
257 st->freq_xfer[1].cs_change = 1;
258 st->freq_xfer[2].tx_buf = &st->freq_data[2];
259 st->freq_xfer[2].len = 2;
260 st->freq_xfer[2].cs_change = 1;
261 st->freq_xfer[3].tx_buf = &st->freq_data[3];
262 st->freq_xfer[3].len = 2;
264 spi_message_init(&st->freq_msg);
265 spi_message_add_tail(&st->freq_xfer[0], &st->freq_msg);
266 spi_message_add_tail(&st->freq_xfer[1], &st->freq_msg);
267 spi_message_add_tail(&st->freq_xfer[2], &st->freq_msg);
268 spi_message_add_tail(&st->freq_xfer[3], &st->freq_msg);
270 st->phase_xfer[0].tx_buf = &st->phase_data[0];
271 st->phase_xfer[0].len = 2;
272 st->phase_xfer[0].cs_change = 1;
273 st->phase_xfer[1].tx_buf = &st->phase_data[1];
274 st->phase_xfer[1].len = 2;
276 spi_message_init(&st->phase_msg);
277 spi_message_add_tail(&st->phase_xfer[0], &st->phase_msg);
278 spi_message_add_tail(&st->phase_xfer[1], &st->phase_msg);
280 st->ctrl_src = AD9832_SLEEP | AD9832_RESET | AD9832_CLR;
281 st->data = cpu_to_be16((AD9832_CMD_SLEEPRESCLR << CMD_SHIFT) |
283 ret = spi_sync(st->spi, &st->msg);
285 dev_err(&spi->dev, "device init failed\n");
286 goto error_free_device;
289 ret = ad9832_write_frequency(st, AD9832_FREQ0HM, pdata->freq0);
291 goto error_free_device;
293 ret = ad9832_write_frequency(st, AD9832_FREQ1HM, pdata->freq1);
295 goto error_free_device;
297 ret = ad9832_write_phase(st, AD9832_PHASE0H, pdata->phase0);
299 goto error_free_device;
301 ret = ad9832_write_phase(st, AD9832_PHASE1H, pdata->phase1);
303 goto error_free_device;
305 ret = ad9832_write_phase(st, AD9832_PHASE2H, pdata->phase2);
307 goto error_free_device;
309 ret = ad9832_write_phase(st, AD9832_PHASE3H, pdata->phase3);
311 goto error_free_device;
313 ret = iio_device_register(st->indio_dev);
315 goto error_free_device;
320 iio_free_device(st->indio_dev);
322 if (!IS_ERR(st->reg))
323 regulator_disable(st->reg);
325 if (!IS_ERR(st->reg))
326 regulator_put(st->reg);
332 static int __devexit ad9832_remove(struct spi_device *spi)
334 struct ad9832_state *st = spi_get_drvdata(spi);
336 iio_device_unregister(st->indio_dev);
337 if (!IS_ERR(st->reg)) {
338 regulator_disable(st->reg);
339 regulator_put(st->reg);
345 static const struct spi_device_id ad9832_id[] = {
351 static struct spi_driver ad9832_driver = {
354 .bus = &spi_bus_type,
355 .owner = THIS_MODULE,
357 .probe = ad9832_probe,
358 .remove = __devexit_p(ad9832_remove),
359 .id_table = ad9832_id,
362 static int __init ad9832_init(void)
364 return spi_register_driver(&ad9832_driver);
366 module_init(ad9832_init);
368 static void __exit ad9832_exit(void)
370 spi_unregister_driver(&ad9832_driver);
372 module_exit(ad9832_exit);
374 MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
375 MODULE_DESCRIPTION("Analog Devices AD9832/AD9835 DDS");
376 MODULE_LICENSE("GPL v2");
377 MODULE_ALIAS("spi:ad9832");