2 * AD7190 AD7192 AD7195 SPI ADC driver
4 * Copyright 2011 Analog Devices Inc.
6 * Licensed under the GPL-2.
9 #include <linux/interrupt.h>
10 #include <linux/device.h>
11 #include <linux/kernel.h>
12 #include <linux/slab.h>
13 #include <linux/sysfs.h>
14 #include <linux/spi/spi.h>
15 #include <linux/regulator/consumer.h>
16 #include <linux/err.h>
17 #include <linux/sched.h>
18 #include <linux/delay.h>
22 #include "../ring_generic.h"
23 #include "../ring_sw.h"
24 #include "../trigger.h"
29 #define AD7192_REG_COMM 0 /* Communications Register (WO, 8-bit) */
30 #define AD7192_REG_STAT 0 /* Status Register (RO, 8-bit) */
31 #define AD7192_REG_MODE 1 /* Mode Register (RW, 24-bit */
32 #define AD7192_REG_CONF 2 /* Configuration Register (RW, 24-bit) */
33 #define AD7192_REG_DATA 3 /* Data Register (RO, 24/32-bit) */
34 #define AD7192_REG_ID 4 /* ID Register (RO, 8-bit) */
35 #define AD7192_REG_GPOCON 5 /* GPOCON Register (RO, 8-bit) */
36 #define AD7192_REG_OFFSET 6 /* Offset Register (RW, 16-bit
37 * (AD7792)/24-bit (AD7192)) */
38 #define AD7192_REG_FULLSALE 7 /* Full-Scale Register
39 * (RW, 16-bit (AD7792)/24-bit (AD7192)) */
41 /* Communications Register Bit Designations (AD7192_REG_COMM) */
42 #define AD7192_COMM_WEN (1 << 7) /* Write Enable */
43 #define AD7192_COMM_WRITE (0 << 6) /* Write Operation */
44 #define AD7192_COMM_READ (1 << 6) /* Read Operation */
45 #define AD7192_COMM_ADDR(x) (((x) & 0x7) << 3) /* Register Address */
46 #define AD7192_COMM_CREAD (1 << 2) /* Continuous Read of Data Register */
48 /* Status Register Bit Designations (AD7192_REG_STAT) */
49 #define AD7192_STAT_RDY (1 << 7) /* Ready */
50 #define AD7192_STAT_ERR (1 << 6) /* Error (Overrange, Underrange) */
51 #define AD7192_STAT_NOREF (1 << 5) /* Error no external reference */
52 #define AD7192_STAT_PARITY (1 << 4) /* Parity */
53 #define AD7192_STAT_CH3 (1 << 2) /* Channel 3 */
54 #define AD7192_STAT_CH2 (1 << 1) /* Channel 2 */
55 #define AD7192_STAT_CH1 (1 << 0) /* Channel 1 */
57 /* Mode Register Bit Designations (AD7192_REG_MODE) */
58 #define AD7192_MODE_SEL(x) (((x) & 0x7) << 21) /* Operation Mode Select */
59 #define AD7192_MODE_DAT_STA (1 << 20) /* Status Register transmission */
60 #define AD7192_MODE_CLKSRC(x) (((x) & 0x3) << 18) /* Clock Source Select */
61 #define AD7192_MODE_SINC3 (1 << 15) /* SINC3 Filter Select */
62 #define AD7192_MODE_ACX (1 << 14) /* AC excitation enable(AD7195 only)*/
63 #define AD7192_MODE_ENPAR (1 << 13) /* Parity Enable */
64 #define AD7192_MODE_CLKDIV (1 << 12) /* Clock divide by 2 (AD7190/2 only)*/
65 #define AD7192_MODE_SCYCLE (1 << 11) /* Single cycle conversion */
66 #define AD7192_MODE_REJ60 (1 << 10) /* 50/60Hz notch filter */
67 #define AD7192_MODE_RATE(x) ((x) & 0x3FF) /* Filter Update Rate Select */
69 /* Mode Register: AD7192_MODE_SEL options */
70 #define AD7192_MODE_CONT 0 /* Continuous Conversion Mode */
71 #define AD7192_MODE_SINGLE 1 /* Single Conversion Mode */
72 #define AD7192_MODE_IDLE 2 /* Idle Mode */
73 #define AD7192_MODE_PWRDN 3 /* Power-Down Mode */
74 #define AD7192_MODE_CAL_INT_ZERO 4 /* Internal Zero-Scale Calibration */
75 #define AD7192_MODE_CAL_INT_FULL 5 /* Internal Full-Scale Calibration */
76 #define AD7192_MODE_CAL_SYS_ZERO 6 /* System Zero-Scale Calibration */
77 #define AD7192_MODE_CAL_SYS_FULL 7 /* System Full-Scale Calibration */
79 /* Mode Register: AD7192_MODE_CLKSRC options */
80 #define AD7192_CLK_EXT_MCLK1_2 0 /* External 4.92 MHz Clock connected
81 * from MCLK1 to MCLK2 */
82 #define AD7192_CLK_EXT_MCLK2 1 /* External Clock applied to MCLK2 */
83 #define AD7192_CLK_INT 2 /* Internal 4.92 MHz Clock not
84 * available at the MCLK2 pin */
85 #define AD7192_CLK_INT_CO 3 /* Internal 4.92 MHz Clock available
89 /* Configuration Register Bit Designations (AD7192_REG_CONF) */
91 #define AD7192_CONF_CHOP (1 << 23) /* CHOP enable */
92 #define AD7192_CONF_REFSEL (1 << 20) /* REFIN1/REFIN2 Reference Select */
93 #define AD7192_CONF_CHAN(x) (((x) & 0xFF) << 8) /* Channel select */
94 #define AD7192_CONF_BURN (1 << 7) /* Burnout current enable */
95 #define AD7192_CONF_REFDET (1 << 6) /* Reference detect enable */
96 #define AD7192_CONF_BUF (1 << 4) /* Buffered Mode Enable */
97 #define AD7192_CONF_UNIPOLAR (1 << 3) /* Unipolar/Bipolar Enable */
98 #define AD7192_CONF_GAIN(x) ((x) & 0x7) /* Gain Select */
100 #define AD7192_CH_AIN1P_AIN2M 0 /* AIN1(+) - AIN2(-) */
101 #define AD7192_CH_AIN3P_AIN4M 1 /* AIN3(+) - AIN4(-) */
102 #define AD7192_CH_TEMP 2 /* Temp Sensor */
103 #define AD7192_CH_AIN2P_AIN2M 3 /* AIN2(+) - AIN2(-) */
104 #define AD7192_CH_AIN1 4 /* AIN1 - AINCOM */
105 #define AD7192_CH_AIN2 5 /* AIN2 - AINCOM */
106 #define AD7192_CH_AIN3 6 /* AIN3 - AINCOM */
107 #define AD7192_CH_AIN4 7 /* AIN4 - AINCOM */
109 /* ID Register Bit Designations (AD7192_REG_ID) */
110 #define ID_AD7190 0x4
111 #define ID_AD7192 0x0
112 #define ID_AD7195 0x6
113 #define AD7192_ID_MASK 0x0F
115 /* GPOCON Register Bit Designations (AD7192_REG_GPOCON) */
116 #define AD7192_GPOCON_BPDSW (1 << 6) /* Bridge power-down switch enable */
117 #define AD7192_GPOCON_GP32EN (1 << 5) /* Digital Output P3 and P2 enable */
118 #define AD7192_GPOCON_GP10EN (1 << 4) /* Digital Output P1 and P0 enable */
119 #define AD7192_GPOCON_P3DAT (1 << 3) /* P3 state */
120 #define AD7192_GPOCON_P2DAT (1 << 2) /* P2 state */
121 #define AD7192_GPOCON_P1DAT (1 << 1) /* P1 state */
122 #define AD7192_GPOCON_P0DAT (1 << 0) /* P0 state */
124 #define AD7192_INT_FREQ_MHz 4915200
127 * The AD7190/2/5 features a dual use data out ready DOUT/RDY output.
128 * In order to avoid contentions on the SPI bus, it's therefore necessary
129 * to use spi bus locking.
131 * The DOUT/RDY output must also be wired to an interrupt capable GPIO.
134 struct ad7192_state {
135 struct spi_device *spi;
136 struct iio_trigger *trig;
137 struct regulator *reg;
138 struct ad7192_platform_data *pdata;
139 wait_queue_head_t wq_data_avail;
147 u32 scale_avail[8][2];
148 u32 available_scan_masks[9];
152 * DMA (thus cache coherency maintenance) requires the
153 * transfer buffers to live in their own cache lines.
155 u8 data[4] ____cacheline_aligned;
158 static int __ad7192_write_reg(struct ad7192_state *st, bool locked,
159 bool cs_change, unsigned char reg,
160 unsigned size, unsigned val)
163 struct spi_transfer t = {
166 .cs_change = cs_change,
168 struct spi_message m;
170 data[0] = AD7192_COMM_WRITE | AD7192_COMM_ADDR(reg);
189 spi_message_init(&m);
190 spi_message_add_tail(&t, &m);
193 return spi_sync_locked(st->spi, &m);
195 return spi_sync(st->spi, &m);
198 static int ad7192_write_reg(struct ad7192_state *st,
199 unsigned reg, unsigned size, unsigned val)
201 return __ad7192_write_reg(st, false, false, reg, size, val);
204 static int __ad7192_read_reg(struct ad7192_state *st, bool locked,
205 bool cs_change, unsigned char reg,
206 int *val, unsigned size)
210 struct spi_transfer t[] = {
217 .cs_change = cs_change,
220 struct spi_message m;
222 data[0] = AD7192_COMM_READ | AD7192_COMM_ADDR(reg);
224 spi_message_init(&m);
225 spi_message_add_tail(&t[0], &m);
226 spi_message_add_tail(&t[1], &m);
229 ret = spi_sync_locked(st->spi, &m);
231 ret = spi_sync(st->spi, &m);
238 *val = data[0] << 16 | data[1] << 8 | data[2];
241 *val = data[0] << 8 | data[1];
253 static int ad7192_read_reg(struct ad7192_state *st,
254 unsigned reg, int *val, unsigned size)
256 return __ad7192_read_reg(st, 0, 0, reg, val, size);
259 static int ad7192_read(struct ad7192_state *st, unsigned ch,
260 unsigned len, int *val)
263 st->conf = (st->conf & ~AD7192_CONF_CHAN(-1)) |
264 AD7192_CONF_CHAN(1 << ch);
265 st->mode = (st->mode & ~AD7192_MODE_SEL(-1)) |
266 AD7192_MODE_SEL(AD7192_MODE_SINGLE);
268 ad7192_write_reg(st, AD7192_REG_CONF, 3, st->conf);
270 spi_bus_lock(st->spi->master);
273 ret = __ad7192_write_reg(st, 1, 1, AD7192_REG_MODE, 3, st->mode);
278 enable_irq(st->spi->irq);
279 wait_event_interruptible(st->wq_data_avail, st->done);
281 ret = __ad7192_read_reg(st, 1, 0, AD7192_REG_DATA, val, len);
283 spi_bus_unlock(st->spi->master);
288 static int ad7192_calibrate(struct ad7192_state *st, unsigned mode, unsigned ch)
292 st->conf = (st->conf & ~AD7192_CONF_CHAN(-1)) |
293 AD7192_CONF_CHAN(1 << ch);
294 st->mode = (st->mode & ~AD7192_MODE_SEL(-1)) | AD7192_MODE_SEL(mode);
296 ad7192_write_reg(st, AD7192_REG_CONF, 3, st->conf);
298 spi_bus_lock(st->spi->master);
301 ret = __ad7192_write_reg(st, 1, 1, AD7192_REG_MODE, 3,
302 (st->devid != ID_AD7195) ?
303 st->mode | AD7192_MODE_CLKDIV :
309 enable_irq(st->spi->irq);
310 wait_event_interruptible(st->wq_data_avail, st->done);
312 st->mode = (st->mode & ~AD7192_MODE_SEL(-1)) |
313 AD7192_MODE_SEL(AD7192_MODE_IDLE);
315 ret = __ad7192_write_reg(st, 1, 0, AD7192_REG_MODE, 3, st->mode);
317 spi_bus_unlock(st->spi->master);
322 static const u8 ad7192_calib_arr[8][2] = {
323 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN1},
324 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN1},
325 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN2},
326 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN2},
327 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN3},
328 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN3},
329 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN4},
330 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN4}
333 static int ad7192_calibrate_all(struct ad7192_state *st)
337 for (i = 0; i < ARRAY_SIZE(ad7192_calib_arr); i++) {
338 ret = ad7192_calibrate(st, ad7192_calib_arr[i][0],
339 ad7192_calib_arr[i][1]);
346 dev_err(&st->spi->dev, "Calibration failed\n");
350 static int ad7192_setup(struct ad7192_state *st)
352 struct iio_dev *indio_dev = spi_get_drvdata(st->spi);
353 struct ad7192_platform_data *pdata = st->pdata;
354 unsigned long long scale_uv;
358 /* reset the serial interface */
359 memset(&ones, 0xFF, 6);
360 ret = spi_write(st->spi, &ones, 6);
363 msleep(1); /* Wait for at least 500us */
365 /* write/read test for device presence */
366 ret = ad7192_read_reg(st, AD7192_REG_ID, &id, 1);
370 id &= AD7192_ID_MASK;
373 dev_warn(&st->spi->dev, "device ID query failed (0x%X)\n", id);
375 switch (pdata->clock_source_sel) {
376 case AD7192_CLK_EXT_MCLK1_2:
377 case AD7192_CLK_EXT_MCLK2:
378 st->mclk = AD7192_INT_FREQ_MHz;
381 case AD7192_CLK_INT_CO:
382 if (pdata->ext_clk_Hz)
383 st->mclk = pdata->ext_clk_Hz;
385 st->mclk = AD7192_INT_FREQ_MHz;
392 st->mode = AD7192_MODE_SEL(AD7192_MODE_IDLE) |
393 AD7192_MODE_CLKSRC(pdata->clock_source_sel) |
394 AD7192_MODE_RATE(480);
396 st->conf = AD7192_CONF_GAIN(0);
399 st->mode |= AD7192_MODE_REJ60;
402 st->mode |= AD7192_MODE_SINC3;
404 if (pdata->refin2_en && (st->devid != ID_AD7195))
405 st->conf |= AD7192_CONF_REFSEL;
407 if (pdata->chop_en) {
408 st->conf |= AD7192_CONF_CHOP;
410 st->f_order = 3; /* SINC 3rd order */
412 st->f_order = 4; /* SINC 4th order */
418 st->conf |= AD7192_CONF_BUF;
420 if (pdata->unipolar_en)
421 st->conf |= AD7192_CONF_UNIPOLAR;
423 if (pdata->burnout_curr_en)
424 st->conf |= AD7192_CONF_BURN;
426 ret = ad7192_write_reg(st, AD7192_REG_MODE, 3, st->mode);
430 ret = ad7192_write_reg(st, AD7192_REG_CONF, 3, st->conf);
434 ret = ad7192_calibrate_all(st);
438 /* Populate available ADC input ranges */
439 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) {
440 scale_uv = ((u64)st->int_vref_mv * 100000000)
441 >> (indio_dev->channels[0].scan_type.realbits -
442 ((st->conf & AD7192_CONF_UNIPOLAR) ? 0 : 1));
445 st->scale_avail[i][1] = do_div(scale_uv, 100000000) * 10;
446 st->scale_avail[i][0] = scale_uv;
451 dev_err(&st->spi->dev, "setup failed\n");
455 static int ad7192_scan_from_ring(struct ad7192_state *st, unsigned ch, int *val)
457 struct iio_ring_buffer *ring = iio_priv_to_dev(st)->ring;
460 u32 *dat32 = (u32 *)dat64;
462 if (!(ring->scan_mask & (1 << ch)))
465 ret = ring->access->read_last(ring, (u8 *) &dat64);
474 static int ad7192_ring_preenable(struct iio_dev *indio_dev)
476 struct ad7192_state *st = iio_priv(indio_dev);
477 struct iio_ring_buffer *ring = indio_dev->ring;
481 if (!ring->scan_count)
484 channel = __ffs(ring->scan_mask);
486 d_size = ring->scan_count *
487 indio_dev->channels[0].scan_type.storagebits / 8;
489 if (ring->scan_timestamp) {
490 d_size += sizeof(s64);
492 if (d_size % sizeof(s64))
493 d_size += sizeof(s64) - (d_size % sizeof(s64));
496 if (indio_dev->ring->access->set_bytes_per_datum)
497 indio_dev->ring->access->set_bytes_per_datum(indio_dev->ring,
500 st->mode = (st->mode & ~AD7192_MODE_SEL(-1)) |
501 AD7192_MODE_SEL(AD7192_MODE_CONT);
502 st->conf = (st->conf & ~AD7192_CONF_CHAN(-1)) |
503 AD7192_CONF_CHAN(1 << indio_dev->channels[channel].address);
505 ad7192_write_reg(st, AD7192_REG_CONF, 3, st->conf);
507 spi_bus_lock(st->spi->master);
508 __ad7192_write_reg(st, 1, 1, AD7192_REG_MODE, 3, st->mode);
511 enable_irq(st->spi->irq);
516 static int ad7192_ring_postdisable(struct iio_dev *indio_dev)
518 struct ad7192_state *st = iio_priv(indio_dev);
520 st->mode = (st->mode & ~AD7192_MODE_SEL(-1)) |
521 AD7192_MODE_SEL(AD7192_MODE_IDLE);
524 wait_event_interruptible(st->wq_data_avail, st->done);
527 disable_irq_nosync(st->spi->irq);
529 __ad7192_write_reg(st, 1, 0, AD7192_REG_MODE, 3, st->mode);
531 return spi_bus_unlock(st->spi->master);
535 * ad7192_trigger_handler() bh of trigger launched polling to ring buffer
537 static irqreturn_t ad7192_trigger_handler(int irq, void *p)
539 struct iio_poll_func *pf = p;
540 struct iio_dev *indio_dev = pf->private_data;
541 struct iio_ring_buffer *ring = indio_dev->ring;
542 struct ad7192_state *st = iio_priv(indio_dev);
544 s32 *dat32 = (s32 *)dat64;
546 if (ring->scan_count)
547 __ad7192_read_reg(st, 1, 1, AD7192_REG_DATA,
549 indio_dev->channels[0].scan_type.realbits/8);
551 /* Guaranteed to be aligned with 8 byte boundary */
552 if (ring->scan_timestamp)
553 dat64[1] = pf->timestamp;
555 ring->access->store_to(ring, (u8 *)dat64, pf->timestamp);
557 iio_trigger_notify_done(indio_dev->trig);
559 enable_irq(st->spi->irq);
564 static const struct iio_ring_setup_ops ad7192_ring_setup_ops = {
565 .preenable = &ad7192_ring_preenable,
566 .postenable = &iio_triggered_ring_postenable,
567 .predisable = &iio_triggered_ring_predisable,
568 .postdisable = &ad7192_ring_postdisable,
571 static int ad7192_register_ring_funcs_and_init(struct iio_dev *indio_dev)
575 indio_dev->ring = iio_sw_rb_allocate(indio_dev);
576 if (!indio_dev->ring) {
580 /* Effectively select the ring buffer implementation */
581 indio_dev->ring->access = &ring_sw_access_funcs;
582 indio_dev->pollfunc = iio_alloc_pollfunc(&iio_pollfunc_store_time,
583 &ad7192_trigger_handler,
588 if (indio_dev->pollfunc == NULL) {
590 goto error_deallocate_sw_rb;
593 /* Ring buffer functions - here trigger setup related */
594 indio_dev->ring->setup_ops = &ad7192_ring_setup_ops;
596 /* Flag that polled ring buffering is possible */
597 indio_dev->modes |= INDIO_RING_TRIGGERED;
600 error_deallocate_sw_rb:
601 iio_sw_rb_free(indio_dev->ring);
606 static void ad7192_ring_cleanup(struct iio_dev *indio_dev)
608 /* ensure that the trigger has been detached */
609 if (indio_dev->trig) {
610 iio_put_trigger(indio_dev->trig);
611 iio_trigger_dettach_poll_func(indio_dev->trig,
612 indio_dev->pollfunc);
614 iio_dealloc_pollfunc(indio_dev->pollfunc);
615 iio_sw_rb_free(indio_dev->ring);
619 * ad7192_data_rdy_trig_poll() the event handler for the data rdy trig
621 static irqreturn_t ad7192_data_rdy_trig_poll(int irq, void *private)
623 struct ad7192_state *st = iio_priv(private);
626 wake_up_interruptible(&st->wq_data_avail);
627 disable_irq_nosync(irq);
629 iio_trigger_poll(st->trig, iio_get_time_ns());
634 static int ad7192_probe_trigger(struct iio_dev *indio_dev)
636 struct ad7192_state *st = iio_priv(indio_dev);
639 st->trig = iio_allocate_trigger("%s-dev%d",
640 spi_get_device_id(st->spi)->name,
642 if (st->trig == NULL) {
647 ret = request_irq(st->spi->irq,
648 ad7192_data_rdy_trig_poll,
650 spi_get_device_id(st->spi)->name,
653 goto error_free_trig;
655 disable_irq_nosync(st->spi->irq);
657 st->trig->dev.parent = &st->spi->dev;
658 st->trig->owner = THIS_MODULE;
659 st->trig->private_data = indio_dev;
661 ret = iio_trigger_register(st->trig);
663 /* select default trigger */
664 indio_dev->trig = st->trig;
671 free_irq(st->spi->irq, indio_dev);
673 iio_free_trigger(st->trig);
678 static void ad7192_remove_trigger(struct iio_dev *indio_dev)
680 struct ad7192_state *st = iio_priv(indio_dev);
682 iio_trigger_unregister(st->trig);
683 free_irq(st->spi->irq, indio_dev);
684 iio_free_trigger(st->trig);
687 static ssize_t ad7192_read_frequency(struct device *dev,
688 struct device_attribute *attr,
691 struct iio_dev *indio_dev = dev_get_drvdata(dev);
692 struct ad7192_state *st = iio_priv(indio_dev);
694 return sprintf(buf, "%d\n", st->mclk /
695 (st->f_order * 1024 * AD7192_MODE_RATE(st->mode)));
698 static ssize_t ad7192_write_frequency(struct device *dev,
699 struct device_attribute *attr,
703 struct iio_dev *indio_dev = dev_get_drvdata(dev);
704 struct ad7192_state *st = iio_priv(indio_dev);
708 ret = strict_strtoul(buf, 10, &lval);
712 mutex_lock(&indio_dev->mlock);
713 if (iio_ring_enabled(indio_dev)) {
714 mutex_unlock(&indio_dev->mlock);
718 div = st->mclk / (lval * st->f_order * 1024);
719 if (div < 1 || div > 1023) {
724 st->mode &= ~AD7192_MODE_RATE(-1);
725 st->mode |= AD7192_MODE_RATE(div);
726 ad7192_write_reg(st, AD7192_REG_MODE, 3, st->mode);
729 mutex_unlock(&indio_dev->mlock);
731 return ret ? ret : len;
734 static IIO_DEV_ATTR_SAMP_FREQ(S_IWUSR | S_IRUGO,
735 ad7192_read_frequency,
736 ad7192_write_frequency);
739 static ssize_t ad7192_show_scale_available(struct device *dev,
740 struct device_attribute *attr, char *buf)
742 struct iio_dev *indio_dev = dev_get_drvdata(dev);
743 struct ad7192_state *st = iio_priv(indio_dev);
746 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)
747 len += sprintf(buf + len, "%d.%09u ", st->scale_avail[i][0],
748 st->scale_avail[i][1]);
750 len += sprintf(buf + len, "\n");
755 static IIO_DEVICE_ATTR_NAMED(in_m_in_scale_available, in-in_scale_available,
756 S_IRUGO, ad7192_show_scale_available, NULL, 0);
758 static IIO_DEVICE_ATTR(in_scale_available, S_IRUGO,
759 ad7192_show_scale_available, NULL, 0);
761 static ssize_t ad7192_show_ac_excitation(struct device *dev,
762 struct device_attribute *attr,
765 struct iio_dev *indio_dev = dev_get_drvdata(dev);
766 struct ad7192_state *st = iio_priv(indio_dev);
768 return sprintf(buf, "%d\n", !!(st->mode & AD7192_MODE_ACX));
771 static ssize_t ad7192_show_bridge_switch(struct device *dev,
772 struct device_attribute *attr,
775 struct iio_dev *indio_dev = dev_get_drvdata(dev);
776 struct ad7192_state *st = iio_priv(indio_dev);
778 return sprintf(buf, "%d\n", !!(st->gpocon & AD7192_GPOCON_BPDSW));
781 static ssize_t ad7192_set(struct device *dev,
782 struct device_attribute *attr,
786 struct iio_dev *indio_dev = dev_get_drvdata(dev);
787 struct ad7192_state *st = iio_priv(indio_dev);
788 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
792 ret = strtobool(buf, &val);
796 mutex_lock(&indio_dev->mlock);
797 if (iio_ring_enabled(indio_dev)) {
798 mutex_unlock(&indio_dev->mlock);
802 switch (this_attr->address) {
803 case AD7192_REG_GPOCON:
805 st->gpocon |= AD7192_GPOCON_BPDSW;
807 st->gpocon &= ~AD7192_GPOCON_BPDSW;
809 ad7192_write_reg(st, AD7192_REG_GPOCON, 1, st->gpocon);
811 case AD7192_REG_MODE:
813 st->mode |= AD7192_MODE_ACX;
815 st->mode &= ~AD7192_MODE_ACX;
817 ad7192_write_reg(st, AD7192_REG_GPOCON, 3, st->mode);
823 mutex_unlock(&indio_dev->mlock);
825 return ret ? ret : len;
828 static IIO_DEVICE_ATTR(bridge_switch_en, S_IRUGO | S_IWUSR,
829 ad7192_show_bridge_switch, ad7192_set,
832 static IIO_DEVICE_ATTR(ac_excitation_en, S_IRUGO | S_IWUSR,
833 ad7192_show_ac_excitation, ad7192_set,
836 static struct attribute *ad7192_attributes[] = {
837 &iio_dev_attr_sampling_frequency.dev_attr.attr,
838 &iio_dev_attr_in_m_in_scale_available.dev_attr.attr,
839 &iio_dev_attr_in_scale_available.dev_attr.attr,
840 &iio_dev_attr_bridge_switch_en.dev_attr.attr,
841 &iio_dev_attr_ac_excitation_en.dev_attr.attr,
845 static mode_t ad7192_attr_is_visible(struct kobject *kobj,
846 struct attribute *attr, int n)
848 struct device *dev = container_of(kobj, struct device, kobj);
849 struct iio_dev *dev_info = dev_get_drvdata(dev);
850 struct ad7192_state *st = iio_priv(dev_info);
852 mode_t mode = attr->mode;
854 if ((st->devid != ID_AD7195) &&
855 (attr == &iio_dev_attr_ac_excitation_en.dev_attr.attr))
861 static const struct attribute_group ad7192_attribute_group = {
862 .attrs = ad7192_attributes,
863 .is_visible = ad7192_attr_is_visible,
866 static int ad7192_read_raw(struct iio_dev *indio_dev,
867 struct iio_chan_spec const *chan,
872 struct ad7192_state *st = iio_priv(indio_dev);
874 bool unipolar = !!(st->conf & AD7192_CONF_UNIPOLAR);
878 mutex_lock(&indio_dev->mlock);
879 if (iio_ring_enabled(indio_dev))
880 ret = ad7192_scan_from_ring(st,
881 chan->scan_index, &smpl);
883 ret = ad7192_read(st, chan->address,
884 chan->scan_type.realbits / 8, &smpl);
885 mutex_unlock(&indio_dev->mlock);
890 *val = (smpl >> chan->scan_type.shift) &
891 ((1 << (chan->scan_type.realbits)) - 1);
893 switch (chan->type) {
897 *val -= (1 << (chan->scan_type.realbits - 1));
901 *val /= 2815; /* temp Kelvin */
902 *val -= 273; /* temp Celsius */
909 case (1 << IIO_CHAN_INFO_SCALE_SHARED):
910 mutex_lock(&indio_dev->mlock);
911 *val = st->scale_avail[AD7192_CONF_GAIN(st->conf)][0];
912 *val2 = st->scale_avail[AD7192_CONF_GAIN(st->conf)][1];
913 mutex_unlock(&indio_dev->mlock);
915 return IIO_VAL_INT_PLUS_NANO;
917 case (1 << IIO_CHAN_INFO_SCALE_SEPARATE):
926 static int ad7192_write_raw(struct iio_dev *indio_dev,
927 struct iio_chan_spec const *chan,
932 struct ad7192_state *st = iio_priv(indio_dev);
936 mutex_lock(&indio_dev->mlock);
937 if (iio_ring_enabled(indio_dev)) {
938 mutex_unlock(&indio_dev->mlock);
943 case (1 << IIO_CHAN_INFO_SCALE_SHARED):
945 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)
946 if (val2 == st->scale_avail[i][1]) {
948 st->conf &= ~AD7192_CONF_GAIN(-1);
949 st->conf |= AD7192_CONF_GAIN(i);
951 if (tmp != st->conf) {
952 ad7192_write_reg(st, AD7192_REG_CONF,
954 ad7192_calibrate_all(st);
963 mutex_unlock(&indio_dev->mlock);
968 static int ad7192_validate_trigger(struct iio_dev *indio_dev,
969 struct iio_trigger *trig)
971 if (indio_dev->trig != trig)
977 static int ad7192_write_raw_get_fmt(struct iio_dev *indio_dev,
978 struct iio_chan_spec const *chan,
981 return IIO_VAL_INT_PLUS_NANO;
984 static const struct iio_info ad7192_info = {
985 .read_raw = &ad7192_read_raw,
986 .write_raw = &ad7192_write_raw,
987 .write_raw_get_fmt = &ad7192_write_raw_get_fmt,
988 .attrs = &ad7192_attribute_group,
989 .validate_trigger = ad7192_validate_trigger,
990 .driver_module = THIS_MODULE,
993 #define AD7192_CHAN_DIFF(_chan, _chan2, _name, _address, _si) \
994 { .type = IIO_IN_DIFF, \
996 .extend_name = _name, \
998 .channel2 = _chan2, \
999 .info_mask = (1 << IIO_CHAN_INFO_SCALE_SHARED), \
1000 .address = _address, \
1001 .scan_index = _si, \
1002 .scan_type = IIO_ST('s', 24, 32, 0)}
1004 #define AD7192_CHAN(_chan, _address, _si) \
1008 .info_mask = (1 << IIO_CHAN_INFO_SCALE_SHARED), \
1009 .address = _address, \
1010 .scan_index = _si, \
1011 .scan_type = IIO_ST('s', 24, 32, 0)}
1013 #define AD7192_CHAN_TEMP(_chan, _address, _si) \
1014 { .type = IIO_TEMP, \
1017 .info_mask = (1 << IIO_CHAN_INFO_SCALE_SEPARATE), \
1018 .address = _address, \
1019 .scan_index = _si, \
1020 .scan_type = IIO_ST('s', 24, 32, 0)}
1022 static struct iio_chan_spec ad7192_channels[] = {
1023 AD7192_CHAN_DIFF(1, 2, NULL, AD7192_CH_AIN1P_AIN2M, 0),
1024 AD7192_CHAN_DIFF(3, 4, NULL, AD7192_CH_AIN3P_AIN4M, 1),
1025 AD7192_CHAN_TEMP(0, AD7192_CH_TEMP, 2),
1026 AD7192_CHAN_DIFF(2, 2, "shorted", AD7192_CH_AIN2P_AIN2M, 3),
1027 AD7192_CHAN(1, AD7192_CH_AIN1, 4),
1028 AD7192_CHAN(2, AD7192_CH_AIN2, 5),
1029 AD7192_CHAN(3, AD7192_CH_AIN3, 6),
1030 AD7192_CHAN(4, AD7192_CH_AIN4, 7),
1031 IIO_CHAN_SOFT_TIMESTAMP(8),
1034 static int __devinit ad7192_probe(struct spi_device *spi)
1036 struct ad7192_platform_data *pdata = spi->dev.platform_data;
1037 struct ad7192_state *st;
1038 struct iio_dev *indio_dev;
1039 int ret, i , voltage_uv = 0, regdone = 0;
1042 dev_err(&spi->dev, "no platform data?\n");
1047 dev_err(&spi->dev, "no IRQ?\n");
1051 indio_dev = iio_allocate_device(sizeof(*st));
1052 if (indio_dev == NULL)
1055 st = iio_priv(indio_dev);
1057 st->reg = regulator_get(&spi->dev, "vcc");
1058 if (!IS_ERR(st->reg)) {
1059 ret = regulator_enable(st->reg);
1063 voltage_uv = regulator_get_voltage(st->reg);
1068 if (pdata && pdata->vref_mv)
1069 st->int_vref_mv = pdata->vref_mv;
1070 else if (voltage_uv)
1071 st->int_vref_mv = voltage_uv / 1000;
1073 dev_warn(&spi->dev, "reference voltage undefined\n");
1075 spi_set_drvdata(spi, indio_dev);
1077 st->devid = spi_get_device_id(spi)->driver_data;
1078 indio_dev->dev.parent = &spi->dev;
1079 indio_dev->name = spi_get_device_id(spi)->name;
1080 indio_dev->modes = INDIO_DIRECT_MODE;
1081 indio_dev->channels = ad7192_channels;
1082 indio_dev->num_channels = ARRAY_SIZE(ad7192_channels);
1083 indio_dev->available_scan_masks = st->available_scan_masks;
1084 indio_dev->info = &ad7192_info;
1086 for (i = 0; i < indio_dev->num_channels; i++)
1087 st->available_scan_masks[i] = (1 << i) | (1 <<
1088 indio_dev->channels[indio_dev->num_channels - 1].
1091 init_waitqueue_head(&st->wq_data_avail);
1093 ret = ad7192_register_ring_funcs_and_init(indio_dev);
1095 goto error_disable_reg;
1097 ret = iio_device_register(indio_dev);
1099 goto error_unreg_ring;
1102 ret = ad7192_probe_trigger(indio_dev);
1104 goto error_unreg_ring;
1106 ret = iio_ring_buffer_register_ex(indio_dev->ring, 0,
1107 indio_dev->channels,
1108 indio_dev->num_channels);
1110 goto error_remove_trigger;
1112 ret = ad7192_setup(st);
1114 goto error_uninitialize_ring;
1118 error_uninitialize_ring:
1119 iio_ring_buffer_unregister(indio_dev->ring);
1120 error_remove_trigger:
1121 ad7192_remove_trigger(indio_dev);
1123 ad7192_ring_cleanup(indio_dev);
1125 if (!IS_ERR(st->reg))
1126 regulator_disable(st->reg);
1128 if (!IS_ERR(st->reg))
1129 regulator_put(st->reg);
1132 iio_device_unregister(indio_dev);
1134 iio_free_device(indio_dev);
1139 static int ad7192_remove(struct spi_device *spi)
1141 struct iio_dev *indio_dev = spi_get_drvdata(spi);
1142 struct ad7192_state *st = iio_priv(indio_dev);
1144 iio_ring_buffer_unregister(indio_dev->ring);
1145 ad7192_remove_trigger(indio_dev);
1146 ad7192_ring_cleanup(indio_dev);
1148 if (!IS_ERR(st->reg)) {
1149 regulator_disable(st->reg);
1150 regulator_put(st->reg);
1153 iio_device_unregister(indio_dev);
1158 static const struct spi_device_id ad7192_id[] = {
1159 {"ad7190", ID_AD7190},
1160 {"ad7192", ID_AD7192},
1161 {"ad7195", ID_AD7195},
1165 static struct spi_driver ad7192_driver = {
1168 .owner = THIS_MODULE,
1170 .probe = ad7192_probe,
1171 .remove = __devexit_p(ad7192_remove),
1172 .id_table = ad7192_id,
1175 static int __init ad7192_init(void)
1177 return spi_register_driver(&ad7192_driver);
1179 module_init(ad7192_init);
1181 static void __exit ad7192_exit(void)
1183 spi_unregister_driver(&ad7192_driver);
1185 module_exit(ad7192_exit);
1187 MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
1188 MODULE_DESCRIPTION("Analog Devices AD7190, AD7192, AD7195 ADC");
1189 MODULE_LICENSE("GPL v2");