Pileus Git - ~andy/linux/blob - drivers/staging/iio/accel/lis3l02dq_ring.c

   1 #include <linux/interrupt.h>
   2 #include <linux/gpio.h>
   3 #include <linux/mutex.h>
   4 #include <linux/kernel.h>
   5 #include <linux/spi/spi.h>
   6 #include <linux/slab.h>
   7
   8 #include "../iio.h"
   9 #include "../ring_sw.h"
  10 #include "../kfifo_buf.h"
  11 #include "../trigger.h"
  12 #include "lis3l02dq.h"
  13
  14 /**
  15  * combine_8_to_16() utility function to munge to u8s into u16
  16  **/
  17 static inline u16 combine_8_to_16(u8 lower, u8 upper)
  18 {
  19         u16 _lower = lower;
  20         u16 _upper = upper;
  21         return _lower | (_upper << 8);
  22 }
  23
  24 /**
  25  * lis3l02dq_data_rdy_trig_poll() the event handler for the data rdy trig
  26  **/
  27 irqreturn_t lis3l02dq_data_rdy_trig_poll(int irq, void *private)
  28 {
  29         struct iio_dev *indio_dev = private;
  30         struct lis3l02dq_state *st = iio_priv(indio_dev);
  31
  32         if (st->trigger_on) {
  33                 iio_trigger_poll(st->trig, iio_get_time_ns());
  34                 return IRQ_HANDLED;
  35         } else
  36                 return IRQ_WAKE_THREAD;
  37 }
  38
  39 /**
  40  * lis3l02dq_read_accel_from_ring() individual acceleration read from ring
  41  **/
  42 ssize_t lis3l02dq_read_accel_from_ring(struct iio_ring_buffer *ring,
  43                                        int index,
  44                                        int *val)
  45 {
  46         int ret;
  47         s16 *data;
  48
  49         if (!iio_scan_mask_query(ring, index))
  50                 return -EINVAL;
  51
  52         if (!ring->access->read_last)
  53                 return -EBUSY;
  54
  55         data = kmalloc(ring->access->get_bytes_per_datum(ring),
  56                        GFP_KERNEL);
  57         if (data == NULL)
  58                 return -ENOMEM;
  59
  60         ret = ring->access->read_last(ring, (u8 *)data);
  61         if (ret)
  62                 goto error_free_data;
  63         *val = data[bitmap_weight(&ring->scan_mask, index)];
  64 error_free_data:
  65         kfree(data);
  66
  67         return ret;
  68 }
  69
  70 static const u8 read_all_tx_array[] = {
  71         LIS3L02DQ_READ_REG(LIS3L02DQ_REG_OUT_X_L_ADDR), 0,
  72         LIS3L02DQ_READ_REG(LIS3L02DQ_REG_OUT_X_H_ADDR), 0,
  73         LIS3L02DQ_READ_REG(LIS3L02DQ_REG_OUT_Y_L_ADDR), 0,
  74         LIS3L02DQ_READ_REG(LIS3L02DQ_REG_OUT_Y_H_ADDR), 0,
  75         LIS3L02DQ_READ_REG(LIS3L02DQ_REG_OUT_Z_L_ADDR), 0,
  76         LIS3L02DQ_READ_REG(LIS3L02DQ_REG_OUT_Z_H_ADDR), 0,
  77 };
  78
  79 /**
  80  * lis3l02dq_read_all() Reads all channels currently selected
  81  * @st:         device specific state
  82  * @rx_array:   (dma capable) receive array, must be at least
  83  *              4*number of channels
  84  **/
  85 static int lis3l02dq_read_all(struct iio_dev *indio_dev, u8 *rx_array)
  86 {
  87         struct iio_ring_buffer *ring = indio_dev->ring;
  88         struct lis3l02dq_state *st = iio_priv(indio_dev);
  89         struct spi_transfer *xfers;
  90         struct spi_message msg;
  91         int ret, i, j = 0;
  92
  93         xfers = kzalloc((ring->scan_count) * 2
  94                         * sizeof(*xfers), GFP_KERNEL);
  95         if (!xfers)
  96                 return -ENOMEM;
  97
  98         mutex_lock(&st->buf_lock);
  99
 100         for (i = 0; i < ARRAY_SIZE(read_all_tx_array)/4; i++)
 101                 if (ring->scan_mask & (1 << i)) {
 102                         /* lower byte */
 103                         xfers[j].tx_buf = st->tx + 2*j;
 104                         st->tx[2*j] = read_all_tx_array[i*4];
 105                         st->tx[2*j + 1] = 0;
 106                         if (rx_array)
 107                                 xfers[j].rx_buf = rx_array + j*2;
 108                         xfers[j].bits_per_word = 8;
 109                         xfers[j].len = 2;
 110                         xfers[j].cs_change = 1;
 111                         j++;
 112
 113                         /* upper byte */
 114                         xfers[j].tx_buf = st->tx + 2*j;
 115                         st->tx[2*j] = read_all_tx_array[i*4 + 2];
 116                         st->tx[2*j + 1] = 0;
 117                         if (rx_array)
 118                                 xfers[j].rx_buf = rx_array + j*2;
 119                         xfers[j].bits_per_word = 8;
 120                         xfers[j].len = 2;
 121                         xfers[j].cs_change = 1;
 122                         j++;
 123                 }
 124
 125         /* After these are transmitted, the rx_buff should have
 126          * values in alternate bytes
 127          */
 128         spi_message_init(&msg);
 129         for (j = 0; j < ring->scan_count * 2; j++)
 130                 spi_message_add_tail(&xfers[j], &msg);
 131
 132         ret = spi_sync(st->us, &msg);
 133         mutex_unlock(&st->buf_lock);
 134         kfree(xfers);
 135
 136         return ret;
 137 }
 138
 139 static int lis3l02dq_get_ring_element(struct iio_dev *indio_dev,
 140                                 u8 *buf)
 141 {
 142         int ret, i;
 143         u8 *rx_array ;
 144         s16 *data = (s16 *)buf;
 145
 146         rx_array = kzalloc(4 * (indio_dev->ring->scan_count), GFP_KERNEL);
 147         if (rx_array == NULL)
 148                 return -ENOMEM;
 149         ret = lis3l02dq_read_all(indio_dev, rx_array);
 150         if (ret < 0)
 151                 return ret;
 152         for (i = 0; i < indio_dev->ring->scan_count; i++)
 153                 data[i] = combine_8_to_16(rx_array[i*4+1],
 154                                         rx_array[i*4+3]);
 155         kfree(rx_array);
 156
 157         return i*sizeof(data[0]);
 158 }
 159
 160 static irqreturn_t lis3l02dq_trigger_handler(int irq, void *p)
 161 {
 162         struct iio_poll_func *pf = p;
 163         struct iio_dev *indio_dev = pf->private_data;
 164         struct iio_ring_buffer *ring = indio_dev->ring;
 165         int len = 0;
 166         size_t datasize = ring->access->get_bytes_per_datum(ring);
 167         char *data = kmalloc(datasize, GFP_KERNEL);
 168
 169         if (data == NULL) {
 170                 dev_err(indio_dev->dev.parent,
 171                         "memory alloc failed in ring bh");
 172                 return -ENOMEM;
 173         }
 174
 175         if (ring->scan_count)
 176                 len = lis3l02dq_get_ring_element(indio_dev, data);
 177
 178           /* Guaranteed to be aligned with 8 byte boundary */
 179         if (ring->scan_timestamp)
 180                 *(s64 *)(((phys_addr_t)data + len
 181                                 + sizeof(s64) - 1) & ~(sizeof(s64) - 1))
 182                         = pf->timestamp;
 183         ring->access->store_to(ring, (u8 *)data, pf->timestamp);
 184
 185         iio_trigger_notify_done(indio_dev->trig);
 186         kfree(data);
 187         return IRQ_HANDLED;
 188 }
 189
 190 /* Caller responsible for locking as necessary. */
 191 static int
 192 __lis3l02dq_write_data_ready_config(struct device *dev, bool state)
 193 {
 194         int ret;
 195         u8 valold;
 196         bool currentlyset;
 197         struct iio_dev *indio_dev = dev_get_drvdata(dev);
 198         struct lis3l02dq_state *st = iio_priv(indio_dev);
 199
 200 /* Get the current event mask register */
 201         ret = lis3l02dq_spi_read_reg_8(indio_dev,
 202                                        LIS3L02DQ_REG_CTRL_2_ADDR,
 203                                        &valold);
 204         if (ret)
 205                 goto error_ret;
 206 /* Find out if data ready is already on */
 207         currentlyset
 208                 = valold & LIS3L02DQ_REG_CTRL_2_ENABLE_DATA_READY_GENERATION;
 209
 210 /* Disable requested */
 211         if (!state && currentlyset) {
 212                 /* disable the data ready signal */
 213                 valold &= ~LIS3L02DQ_REG_CTRL_2_ENABLE_DATA_READY_GENERATION;
 214
 215                 /* The double write is to overcome a hardware bug?*/
 216                 ret = lis3l02dq_spi_write_reg_8(indio_dev,
 217                                                 LIS3L02DQ_REG_CTRL_2_ADDR,
 218                                                 valold);
 219                 if (ret)
 220                         goto error_ret;
 221                 ret = lis3l02dq_spi_write_reg_8(indio_dev,
 222                                                 LIS3L02DQ_REG_CTRL_2_ADDR,
 223                                                 valold);
 224                 if (ret)
 225                         goto error_ret;
 226                 st->trigger_on = false;
 227 /* Enable requested */
 228         } else if (state && !currentlyset) {
 229                 /* if not set, enable requested */
 230                 /* first disable all events */
 231                 ret = lis3l02dq_disable_all_events(indio_dev);
 232                 if (ret < 0)
 233                         goto error_ret;
 234
 235                 valold = ret |
 236                         LIS3L02DQ_REG_CTRL_2_ENABLE_DATA_READY_GENERATION;
 237
 238                 st->trigger_on = true;
 239                 ret = lis3l02dq_spi_write_reg_8(indio_dev,
 240                                                 LIS3L02DQ_REG_CTRL_2_ADDR,
 241                                                 valold);
 242                 if (ret)
 243                         goto error_ret;
 244         }
 245
 246         return 0;
 247 error_ret:
 248         return ret;
 249 }
 250
 251 /**
 252  * lis3l02dq_data_rdy_trigger_set_state() set datardy interrupt state
 253  *
 254  * If disabling the interrupt also does a final read to ensure it is clear.
 255  * This is only important in some cases where the scan enable elements are
 256  * switched before the ring is reenabled.
 257  **/
 258 static int lis3l02dq_data_rdy_trigger_set_state(struct iio_trigger *trig,
 259                                                 bool state)
 260 {
 261         struct iio_dev *indio_dev = trig->private_data;
 262         int ret = 0;
 263         u8 t;
 264
 265         __lis3l02dq_write_data_ready_config(&indio_dev->dev, state);
 266         if (state == false) {
 267                 /*
 268                  * A possible quirk with teh handler is currently worked around
 269                  *  by ensuring outstanding read events are cleared.
 270                  */
 271                 ret = lis3l02dq_read_all(indio_dev, NULL);
 272         }
 273         lis3l02dq_spi_read_reg_8(indio_dev,
 274                                  LIS3L02DQ_REG_WAKE_UP_SRC_ADDR,
 275                                  &t);
 276         return ret;
 277 }
 278
 279 /**
 280  * lis3l02dq_trig_try_reen() try renabling irq for data rdy trigger
 281  * @trig:       the datardy trigger
 282  */
 283 static int lis3l02dq_trig_try_reen(struct iio_trigger *trig)
 284 {
 285         struct iio_dev *indio_dev = trig->private_data;
 286         struct lis3l02dq_state *st = iio_priv(indio_dev);
 287         int i;
 288
 289         /* If gpio still high (or high again) */
 290         /* In theory possible we will need to do this several times */
 291         for (i = 0; i < 5; i++)
 292                 if (gpio_get_value(irq_to_gpio(st->us->irq)))
 293                         lis3l02dq_read_all(indio_dev, NULL);
 294                 else
 295                         break;
 296         if (i == 5)
 297                 printk(KERN_INFO
 298                        "Failed to clear the interrupt for lis3l02dq\n");
 299
 300         /* irq reenabled so success! */
 301         return 0;
 302 }
 303
 304 static const struct iio_trigger_ops lis3l02dq_trigger_ops = {
 305         .owner = THIS_MODULE,
 306         .set_trigger_state = &lis3l02dq_data_rdy_trigger_set_state,
 307         .try_reenable = &lis3l02dq_trig_try_reen,
 308 };
 309
 310 int lis3l02dq_probe_trigger(struct iio_dev *indio_dev)
 311 {
 312         int ret;
 313         struct lis3l02dq_state *st = iio_priv(indio_dev);
 314
 315         st->trig = iio_allocate_trigger("lis3l02dq-dev%d", indio_dev->id);
 316         if (!st->trig) {
 317                 ret = -ENOMEM;
 318                 goto error_ret;
 319         }
 320
 321         st->trig->dev.parent = &st->us->dev;
 322         st->trig->ops = &lis3l02dq_trigger_ops;
 323         st->trig->private_data = indio_dev;
 324         ret = iio_trigger_register(st->trig);
 325         if (ret)
 326                 goto error_free_trig;
 327
 328         return 0;
 329
 330 error_free_trig:
 331         iio_free_trigger(st->trig);
 332 error_ret:
 333         return ret;
 334 }
 335
 336 void lis3l02dq_remove_trigger(struct iio_dev *indio_dev)
 337 {
 338         struct lis3l02dq_state *st = iio_priv(indio_dev);
 339
 340         iio_trigger_unregister(st->trig);
 341         iio_free_trigger(st->trig);
 342 }
 343
 344 void lis3l02dq_unconfigure_ring(struct iio_dev *indio_dev)
 345 {
 346         iio_dealloc_pollfunc(indio_dev->pollfunc);
 347         lis3l02dq_free_buf(indio_dev->ring);
 348 }
 349
 350 static int lis3l02dq_ring_postenable(struct iio_dev *indio_dev)
 351 {
 352         /* Disable unwanted channels otherwise the interrupt will not clear */
 353         u8 t;
 354         int ret;
 355         bool oneenabled = false;
 356
 357         ret = lis3l02dq_spi_read_reg_8(indio_dev,
 358                                        LIS3L02DQ_REG_CTRL_1_ADDR,
 359                                        &t);
 360         if (ret)
 361                 goto error_ret;
 362
 363         if (iio_scan_mask_query(indio_dev->ring, 0)) {
 364                 t |= LIS3L02DQ_REG_CTRL_1_AXES_X_ENABLE;
 365                 oneenabled = true;
 366         } else
 367                 t &= ~LIS3L02DQ_REG_CTRL_1_AXES_X_ENABLE;
 368         if (iio_scan_mask_query(indio_dev->ring, 1)) {
 369                 t |= LIS3L02DQ_REG_CTRL_1_AXES_Y_ENABLE;
 370                 oneenabled = true;
 371         } else
 372                 t &= ~LIS3L02DQ_REG_CTRL_1_AXES_Y_ENABLE;
 373         if (iio_scan_mask_query(indio_dev->ring, 2)) {
 374                 t |= LIS3L02DQ_REG_CTRL_1_AXES_Z_ENABLE;
 375                 oneenabled = true;
 376         } else
 377                 t &= ~LIS3L02DQ_REG_CTRL_1_AXES_Z_ENABLE;
 378
 379         if (!oneenabled) /* what happens in this case is unknown */
 380                 return -EINVAL;
 381         ret = lis3l02dq_spi_write_reg_8(indio_dev,
 382                                         LIS3L02DQ_REG_CTRL_1_ADDR,
 383                                         t);
 384         if (ret)
 385                 goto error_ret;
 386
 387         return iio_triggered_ring_postenable(indio_dev);
 388 error_ret:
 389         return ret;
 390 }
 391
 392 /* Turn all channels on again */
 393 static int lis3l02dq_ring_predisable(struct iio_dev *indio_dev)
 394 {
 395         u8 t;
 396         int ret;
 397
 398         ret = iio_triggered_ring_predisable(indio_dev);
 399         if (ret)
 400                 goto error_ret;
 401
 402         ret = lis3l02dq_spi_read_reg_8(indio_dev,
 403                                        LIS3L02DQ_REG_CTRL_1_ADDR,
 404                                        &t);
 405         if (ret)
 406                 goto error_ret;
 407         t |= LIS3L02DQ_REG_CTRL_1_AXES_X_ENABLE |
 408                 LIS3L02DQ_REG_CTRL_1_AXES_Y_ENABLE |
 409                 LIS3L02DQ_REG_CTRL_1_AXES_Z_ENABLE;
 410
 411         ret = lis3l02dq_spi_write_reg_8(indio_dev,
 412                                         LIS3L02DQ_REG_CTRL_1_ADDR,
 413                                         t);
 414
 415 error_ret:
 416         return ret;
 417 }
 418
 419 static const struct iio_ring_setup_ops lis3l02dq_ring_setup_ops = {
 420         .preenable = &iio_sw_ring_preenable,
 421         .postenable = &lis3l02dq_ring_postenable,
 422         .predisable = &lis3l02dq_ring_predisable,
 423 };
 424
 425 int lis3l02dq_configure_ring(struct iio_dev *indio_dev)
 426 {
 427         int ret;
 428         struct iio_ring_buffer *ring;
 429
 430         ring = lis3l02dq_alloc_buf(indio_dev);
 431         if (!ring)
 432                 return -ENOMEM;
 433
 434         indio_dev->ring = ring;
 435         /* Effectively select the ring buffer implementation */
 436         indio_dev->ring->access = &lis3l02dq_access_funcs;
 437         ring->bpe = 2;
 438
 439         ring->scan_timestamp = true;
 440         ring->setup_ops = &lis3l02dq_ring_setup_ops;
 441         ring->owner = THIS_MODULE;
 442
 443         /* Set default scan mode */
 444         iio_scan_mask_set(ring, 0);
 445         iio_scan_mask_set(ring, 1);
 446         iio_scan_mask_set(ring, 2);
 447
 448         /* Functions are NULL as we set handler below */
 449         indio_dev->pollfunc = iio_alloc_pollfunc(&iio_pollfunc_store_time,
 450                                                  &lis3l02dq_trigger_handler,
 451                                                  0,
 452                                                  indio_dev,
 453                                                  "lis3l02dq_consumer%d",
 454                                                  indio_dev->id);
 455
 456         if (indio_dev->pollfunc == NULL) {
 457                 ret = -ENOMEM;
 458                 goto error_iio_sw_rb_free;
 459         }
 460
 461         indio_dev->modes |= INDIO_RING_TRIGGERED;
 462         return 0;
 463
 464 error_iio_sw_rb_free:
 465         lis3l02dq_free_buf(indio_dev->ring);
 466         return ret;
 467 }