1 #include <linux/interrupt.h>
3 #include <linux/gpio.h>
4 #include <linux/mutex.h>
5 #include <linux/device.h>
6 #include <linux/kernel.h>
7 #include <linux/spi/spi.h>
8 #include <linux/sysfs.h>
9 #include <linux/slab.h>
13 #include "../ring_sw.h"
14 #include "../kfifo_buf.h"
16 #include "../trigger.h"
17 #include "lis3l02dq.h"
20 * combine_8_to_16() utility function to munge to u8s into u16
22 static inline u16 combine_8_to_16(u8 lower, u8 upper)
26 return _lower | (_upper << 8);
30 * lis3l02dq_data_rdy_trig_poll() the event handler for the data rdy trig
32 irqreturn_t lis3l02dq_data_rdy_trig_poll(int irq, void *private)
34 struct iio_dev *indio_dev = private;
35 struct lis3l02dq_state *st = iio_priv(indio_dev);
38 iio_trigger_poll(st->trig, iio_get_time_ns());
41 return IRQ_WAKE_THREAD;
45 * lis3l02dq_read_accel_from_ring() individual acceleration read from ring
47 ssize_t lis3l02dq_read_accel_from_ring(struct iio_ring_buffer *ring,
54 if (!iio_scan_mask_query(ring, index))
57 if (!ring->access->read_last)
60 data = kmalloc(ring->access->get_bytes_per_datum(ring),
65 ret = ring->access->read_last(ring, (u8 *)data);
68 *val = data[bitmap_weight(&ring->scan_mask, index)];
75 static const u8 read_all_tx_array[] = {
76 LIS3L02DQ_READ_REG(LIS3L02DQ_REG_OUT_X_L_ADDR), 0,
77 LIS3L02DQ_READ_REG(LIS3L02DQ_REG_OUT_X_H_ADDR), 0,
78 LIS3L02DQ_READ_REG(LIS3L02DQ_REG_OUT_Y_L_ADDR), 0,
79 LIS3L02DQ_READ_REG(LIS3L02DQ_REG_OUT_Y_H_ADDR), 0,
80 LIS3L02DQ_READ_REG(LIS3L02DQ_REG_OUT_Z_L_ADDR), 0,
81 LIS3L02DQ_READ_REG(LIS3L02DQ_REG_OUT_Z_H_ADDR), 0,
85 * lis3l02dq_read_all() Reads all channels currently selected
86 * @st: device specific state
87 * @rx_array: (dma capable) receive array, must be at least
88 * 4*number of channels
90 static int lis3l02dq_read_all(struct iio_dev *indio_dev, u8 *rx_array)
92 struct iio_ring_buffer *ring = indio_dev->ring;
93 struct lis3l02dq_state *st = iio_priv(indio_dev);
94 struct spi_transfer *xfers;
95 struct spi_message msg;
98 xfers = kzalloc((ring->scan_count) * 2
99 * sizeof(*xfers), GFP_KERNEL);
103 mutex_lock(&st->buf_lock);
105 for (i = 0; i < ARRAY_SIZE(read_all_tx_array)/4; i++)
106 if (ring->scan_mask & (1 << i)) {
108 xfers[j].tx_buf = st->tx + 2*j;
109 st->tx[2*j] = read_all_tx_array[i*4];
112 xfers[j].rx_buf = rx_array + j*2;
113 xfers[j].bits_per_word = 8;
115 xfers[j].cs_change = 1;
119 xfers[j].tx_buf = st->tx + 2*j;
120 st->tx[2*j] = read_all_tx_array[i*4 + 2];
123 xfers[j].rx_buf = rx_array + j*2;
124 xfers[j].bits_per_word = 8;
126 xfers[j].cs_change = 1;
130 /* After these are transmitted, the rx_buff should have
131 * values in alternate bytes
133 spi_message_init(&msg);
134 for (j = 0; j < ring->scan_count * 2; j++)
135 spi_message_add_tail(&xfers[j], &msg);
137 ret = spi_sync(st->us, &msg);
138 mutex_unlock(&st->buf_lock);
144 static int lis3l02dq_get_ring_element(struct iio_dev *indio_dev,
149 s16 *data = (s16 *)buf;
151 rx_array = kzalloc(4 * (indio_dev->ring->scan_count), GFP_KERNEL);
152 if (rx_array == NULL)
154 ret = lis3l02dq_read_all(indio_dev, rx_array);
157 for (i = 0; i < indio_dev->ring->scan_count; i++)
158 data[i] = combine_8_to_16(rx_array[i*4+1],
162 return i*sizeof(data[0]);
165 static irqreturn_t lis3l02dq_trigger_handler(int irq, void *p)
167 struct iio_poll_func *pf = p;
168 struct iio_dev *indio_dev = pf->private_data;
169 struct iio_ring_buffer *ring = indio_dev->ring;
171 size_t datasize = ring->access->get_bytes_per_datum(ring);
172 char *data = kmalloc(datasize, GFP_KERNEL);
175 dev_err(indio_dev->dev.parent,
176 "memory alloc failed in ring bh");
180 if (ring->scan_count)
181 len = lis3l02dq_get_ring_element(indio_dev, data);
183 /* Guaranteed to be aligned with 8 byte boundary */
184 if (ring->scan_timestamp)
185 *(s64 *)(((phys_addr_t)data + len
186 + sizeof(s64) - 1) & ~(sizeof(s64) - 1))
188 ring->access->store_to(ring, (u8 *)data, pf->timestamp);
190 iio_trigger_notify_done(indio_dev->trig);
195 /* Caller responsible for locking as necessary. */
197 __lis3l02dq_write_data_ready_config(struct device *dev, bool state)
202 struct iio_dev *indio_dev = dev_get_drvdata(dev);
203 struct lis3l02dq_state *st = iio_priv(indio_dev);
205 /* Get the current event mask register */
206 ret = lis3l02dq_spi_read_reg_8(indio_dev,
207 LIS3L02DQ_REG_CTRL_2_ADDR,
211 /* Find out if data ready is already on */
213 = valold & LIS3L02DQ_REG_CTRL_2_ENABLE_DATA_READY_GENERATION;
215 /* Disable requested */
216 if (!state && currentlyset) {
217 /* disable the data ready signal */
218 valold &= ~LIS3L02DQ_REG_CTRL_2_ENABLE_DATA_READY_GENERATION;
220 /* The double write is to overcome a hardware bug?*/
221 ret = lis3l02dq_spi_write_reg_8(indio_dev,
222 LIS3L02DQ_REG_CTRL_2_ADDR,
226 ret = lis3l02dq_spi_write_reg_8(indio_dev,
227 LIS3L02DQ_REG_CTRL_2_ADDR,
231 st->trigger_on = false;
232 /* Enable requested */
233 } else if (state && !currentlyset) {
234 /* if not set, enable requested */
235 /* first disable all events */
236 ret = lis3l02dq_disable_all_events(indio_dev);
241 LIS3L02DQ_REG_CTRL_2_ENABLE_DATA_READY_GENERATION;
243 st->trigger_on = true;
244 ret = lis3l02dq_spi_write_reg_8(indio_dev,
245 LIS3L02DQ_REG_CTRL_2_ADDR,
257 * lis3l02dq_data_rdy_trigger_set_state() set datardy interrupt state
259 * If disabling the interrupt also does a final read to ensure it is clear.
260 * This is only important in some cases where the scan enable elements are
261 * switched before the ring is reenabled.
263 static int lis3l02dq_data_rdy_trigger_set_state(struct iio_trigger *trig,
266 struct iio_dev *indio_dev = trig->private_data;
270 __lis3l02dq_write_data_ready_config(&indio_dev->dev, state);
271 if (state == false) {
273 * A possible quirk with teh handler is currently worked around
274 * by ensuring outstanding read events are cleared.
276 ret = lis3l02dq_read_all(indio_dev, NULL);
278 lis3l02dq_spi_read_reg_8(indio_dev,
279 LIS3L02DQ_REG_WAKE_UP_SRC_ADDR,
285 * lis3l02dq_trig_try_reen() try renabling irq for data rdy trigger
286 * @trig: the datardy trigger
288 static int lis3l02dq_trig_try_reen(struct iio_trigger *trig)
290 struct iio_dev *indio_dev = trig->private_data;
291 struct lis3l02dq_state *st = iio_priv(indio_dev);
294 /* If gpio still high (or high again) */
295 /* In theory possible we will need to do this several times */
296 for (i = 0; i < 5; i++)
297 if (gpio_get_value(irq_to_gpio(st->us->irq)))
298 lis3l02dq_read_all(indio_dev, NULL);
303 "Failed to clear the interrupt for lis3l02dq\n");
305 /* irq reenabled so success! */
309 int lis3l02dq_probe_trigger(struct iio_dev *indio_dev)
312 struct lis3l02dq_state *st = iio_priv(indio_dev);
314 st->trig = iio_allocate_trigger("lis3l02dq-dev%d", indio_dev->id);
320 st->trig->dev.parent = &st->us->dev;
321 st->trig->owner = THIS_MODULE;
322 st->trig->private_data = indio_dev;
323 st->trig->set_trigger_state = &lis3l02dq_data_rdy_trigger_set_state;
324 st->trig->try_reenable = &lis3l02dq_trig_try_reen;
325 ret = iio_trigger_register(st->trig);
327 goto error_free_trig;
332 iio_free_trigger(st->trig);
337 void lis3l02dq_remove_trigger(struct iio_dev *indio_dev)
339 struct lis3l02dq_state *st = iio_priv(indio_dev);
341 iio_trigger_unregister(st->trig);
342 iio_free_trigger(st->trig);
345 void lis3l02dq_unconfigure_ring(struct iio_dev *indio_dev)
347 iio_dealloc_pollfunc(indio_dev->pollfunc);
348 lis3l02dq_free_buf(indio_dev->ring);
351 static int lis3l02dq_ring_postenable(struct iio_dev *indio_dev)
353 /* Disable unwanted channels otherwise the interrupt will not clear */
356 bool oneenabled = false;
358 ret = lis3l02dq_spi_read_reg_8(indio_dev,
359 LIS3L02DQ_REG_CTRL_1_ADDR,
364 if (iio_scan_mask_query(indio_dev->ring, 0)) {
365 t |= LIS3L02DQ_REG_CTRL_1_AXES_X_ENABLE;
368 t &= ~LIS3L02DQ_REG_CTRL_1_AXES_X_ENABLE;
369 if (iio_scan_mask_query(indio_dev->ring, 1)) {
370 t |= LIS3L02DQ_REG_CTRL_1_AXES_Y_ENABLE;
373 t &= ~LIS3L02DQ_REG_CTRL_1_AXES_Y_ENABLE;
374 if (iio_scan_mask_query(indio_dev->ring, 2)) {
375 t |= LIS3L02DQ_REG_CTRL_1_AXES_Z_ENABLE;
378 t &= ~LIS3L02DQ_REG_CTRL_1_AXES_Z_ENABLE;
380 if (!oneenabled) /* what happens in this case is unknown */
382 ret = lis3l02dq_spi_write_reg_8(indio_dev,
383 LIS3L02DQ_REG_CTRL_1_ADDR,
388 return iio_triggered_ring_postenable(indio_dev);
393 /* Turn all channels on again */
394 static int lis3l02dq_ring_predisable(struct iio_dev *indio_dev)
399 ret = iio_triggered_ring_predisable(indio_dev);
403 ret = lis3l02dq_spi_read_reg_8(indio_dev,
404 LIS3L02DQ_REG_CTRL_1_ADDR,
408 t |= LIS3L02DQ_REG_CTRL_1_AXES_X_ENABLE |
409 LIS3L02DQ_REG_CTRL_1_AXES_Y_ENABLE |
410 LIS3L02DQ_REG_CTRL_1_AXES_Z_ENABLE;
412 ret = lis3l02dq_spi_write_reg_8(indio_dev,
413 LIS3L02DQ_REG_CTRL_1_ADDR,
420 static const struct iio_ring_setup_ops lis3l02dq_ring_setup_ops = {
421 .preenable = &iio_sw_ring_preenable,
422 .postenable = &lis3l02dq_ring_postenable,
423 .predisable = &lis3l02dq_ring_predisable,
426 int lis3l02dq_configure_ring(struct iio_dev *indio_dev)
429 struct iio_ring_buffer *ring;
431 ring = lis3l02dq_alloc_buf(indio_dev);
435 indio_dev->ring = ring;
436 /* Effectively select the ring buffer implementation */
437 indio_dev->ring->access = &lis3l02dq_access_funcs;
440 ring->scan_timestamp = true;
441 ring->setup_ops = &lis3l02dq_ring_setup_ops;
442 ring->owner = THIS_MODULE;
444 /* Set default scan mode */
445 iio_scan_mask_set(ring, 0);
446 iio_scan_mask_set(ring, 1);
447 iio_scan_mask_set(ring, 2);
449 /* Functions are NULL as we set handler below */
450 indio_dev->pollfunc = iio_alloc_pollfunc(&iio_pollfunc_store_time,
451 &lis3l02dq_trigger_handler,
454 "lis3l02dq_consumer%d",
457 if (indio_dev->pollfunc == NULL) {
459 goto error_iio_sw_rb_free;
462 indio_dev->modes |= INDIO_RING_TRIGGERED;
465 error_iio_sw_rb_free:
466 lis3l02dq_free_buf(indio_dev->ring);