2 * lis3l02dq.c support STMicroelectronics LISD02DQ
3 * 3d 2g Linear Accelerometers via SPI
5 * Copyright (c) 2007 Jonathan Cameron <jic23@kernel.org>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 * 16 bit left justified mode used.
15 #include <linux/interrupt.h>
16 #include <linux/irq.h>
17 #include <linux/gpio.h>
18 #include <linux/of_gpio.h>
19 #include <linux/mutex.h>
20 #include <linux/device.h>
21 #include <linux/kernel.h>
22 #include <linux/spi/spi.h>
23 #include <linux/slab.h>
24 #include <linux/sysfs.h>
25 #include <linux/module.h>
27 #include <linux/iio/iio.h>
28 #include <linux/iio/sysfs.h>
29 #include <linux/iio/events.h>
30 #include <linux/iio/buffer.h>
32 #include "lis3l02dq.h"
34 /* At the moment the spi framework doesn't allow global setting of cs_change.
35 * It's in the likely to be added comment at the top of spi.h.
36 * This means that use cannot be made of spi_write etc.
38 /* direct copy of the irq_default_primary_handler */
39 #ifndef CONFIG_IIO_BUFFER
40 static irqreturn_t lis3l02dq_nobuffer(int irq, void *private)
42 return IRQ_WAKE_THREAD;
47 * lis3l02dq_spi_read_reg_8() - read single byte from a single register
48 * @indio_dev: iio_dev for this actual device
49 * @reg_address: the address of the register to be read
50 * @val: pass back the resulting value
52 int lis3l02dq_spi_read_reg_8(struct iio_dev *indio_dev,
53 u8 reg_address, u8 *val)
55 struct lis3l02dq_state *st = iio_priv(indio_dev);
57 struct spi_transfer xfer = {
64 mutex_lock(&st->buf_lock);
65 st->tx[0] = LIS3L02DQ_READ_REG(reg_address);
68 ret = spi_sync_transfer(st->us, &xfer, 1);
70 mutex_unlock(&st->buf_lock);
76 * lis3l02dq_spi_write_reg_8() - write single byte to a register
77 * @indio_dev: iio_dev for this device
78 * @reg_address: the address of the register to be written
79 * @val: the value to write
81 int lis3l02dq_spi_write_reg_8(struct iio_dev *indio_dev,
86 struct lis3l02dq_state *st = iio_priv(indio_dev);
88 mutex_lock(&st->buf_lock);
89 st->tx[0] = LIS3L02DQ_WRITE_REG(reg_address);
91 ret = spi_write(st->us, st->tx, 2);
92 mutex_unlock(&st->buf_lock);
98 * lisl302dq_spi_write_reg_s16() - write 2 bytes to a pair of registers
99 * @indio_dev: iio_dev for this device
100 * @lower_reg_address: the address of the lower of the two registers.
101 * Second register is assumed to have address one greater.
102 * @value: value to be written
104 static int lis3l02dq_spi_write_reg_s16(struct iio_dev *indio_dev,
105 u8 lower_reg_address,
109 struct lis3l02dq_state *st = iio_priv(indio_dev);
110 struct spi_transfer xfers[] = { {
116 .tx_buf = st->tx + 2,
122 mutex_lock(&st->buf_lock);
123 st->tx[0] = LIS3L02DQ_WRITE_REG(lower_reg_address);
124 st->tx[1] = value & 0xFF;
125 st->tx[2] = LIS3L02DQ_WRITE_REG(lower_reg_address + 1);
126 st->tx[3] = (value >> 8) & 0xFF;
128 ret = spi_sync_transfer(st->us, xfers, ARRAY_SIZE(xfers));
129 mutex_unlock(&st->buf_lock);
134 static int lis3l02dq_read_reg_s16(struct iio_dev *indio_dev,
135 u8 lower_reg_address,
138 struct lis3l02dq_state *st = iio_priv(indio_dev);
141 struct spi_transfer xfers[] = { {
148 .tx_buf = st->tx + 2,
149 .rx_buf = st->rx + 2,
155 mutex_lock(&st->buf_lock);
156 st->tx[0] = LIS3L02DQ_READ_REG(lower_reg_address);
158 st->tx[2] = LIS3L02DQ_READ_REG(lower_reg_address + 1);
161 ret = spi_sync_transfer(st->us, xfers, ARRAY_SIZE(xfers));
163 dev_err(&st->us->dev, "problem when reading 16 bit register");
166 tempval = (s16)(st->rx[1]) | ((s16)(st->rx[3]) << 8);
170 mutex_unlock(&st->buf_lock);
174 enum lis3l02dq_rm_ind {
180 static u8 lis3l02dq_axis_map[3][3] = {
181 [LIS3L02DQ_ACCEL] = { LIS3L02DQ_REG_OUT_X_L_ADDR,
182 LIS3L02DQ_REG_OUT_Y_L_ADDR,
183 LIS3L02DQ_REG_OUT_Z_L_ADDR },
184 [LIS3L02DQ_GAIN] = { LIS3L02DQ_REG_GAIN_X_ADDR,
185 LIS3L02DQ_REG_GAIN_Y_ADDR,
186 LIS3L02DQ_REG_GAIN_Z_ADDR },
187 [LIS3L02DQ_BIAS] = { LIS3L02DQ_REG_OFFSET_X_ADDR,
188 LIS3L02DQ_REG_OFFSET_Y_ADDR,
189 LIS3L02DQ_REG_OFFSET_Z_ADDR }
192 static int lis3l02dq_read_thresh(struct iio_dev *indio_dev,
196 return lis3l02dq_read_reg_s16(indio_dev, LIS3L02DQ_REG_THS_L_ADDR, val);
199 static int lis3l02dq_write_thresh(struct iio_dev *indio_dev,
204 return lis3l02dq_spi_write_reg_s16(indio_dev,
205 LIS3L02DQ_REG_THS_L_ADDR,
209 static int lis3l02dq_write_raw(struct iio_dev *indio_dev,
210 struct iio_chan_spec const *chan,
215 int ret = -EINVAL, reg;
219 case IIO_CHAN_INFO_CALIBBIAS:
220 if (val > 255 || val < -256)
223 reg = lis3l02dq_axis_map[LIS3L02DQ_BIAS][chan->address];
224 ret = lis3l02dq_spi_write_reg_8(indio_dev, reg, sval);
226 case IIO_CHAN_INFO_CALIBSCALE:
230 reg = lis3l02dq_axis_map[LIS3L02DQ_GAIN][chan->address];
231 ret = lis3l02dq_spi_write_reg_8(indio_dev, reg, uval);
237 static int lis3l02dq_read_raw(struct iio_dev *indio_dev,
238 struct iio_chan_spec const *chan,
249 case IIO_CHAN_INFO_RAW:
250 /* Take the iio_dev status lock */
251 mutex_lock(&indio_dev->mlock);
252 if (indio_dev->currentmode == INDIO_BUFFER_TRIGGERED) {
255 reg = lis3l02dq_axis_map
256 [LIS3L02DQ_ACCEL][chan->address];
257 ret = lis3l02dq_read_reg_s16(indio_dev, reg, val);
259 mutex_unlock(&indio_dev->mlock);
261 case IIO_CHAN_INFO_SCALE:
264 return IIO_VAL_INT_PLUS_MICRO;
265 case IIO_CHAN_INFO_CALIBSCALE:
266 reg = lis3l02dq_axis_map[LIS3L02DQ_GAIN][chan->address];
267 ret = lis3l02dq_spi_read_reg_8(indio_dev, reg, &utemp);
270 /* to match with what previous code does */
274 case IIO_CHAN_INFO_CALIBBIAS:
275 reg = lis3l02dq_axis_map[LIS3L02DQ_BIAS][chan->address];
276 ret = lis3l02dq_spi_read_reg_8(indio_dev, reg, (u8 *)&stemp);
277 /* to match with what previous code does */
285 static ssize_t lis3l02dq_read_frequency(struct device *dev,
286 struct device_attribute *attr,
289 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
292 ret = lis3l02dq_spi_read_reg_8(indio_dev,
293 LIS3L02DQ_REG_CTRL_1_ADDR,
297 t &= LIS3L02DQ_DEC_MASK;
299 case LIS3L02DQ_REG_CTRL_1_DF_128:
300 len = sprintf(buf, "280\n");
302 case LIS3L02DQ_REG_CTRL_1_DF_64:
303 len = sprintf(buf, "560\n");
305 case LIS3L02DQ_REG_CTRL_1_DF_32:
306 len = sprintf(buf, "1120\n");
308 case LIS3L02DQ_REG_CTRL_1_DF_8:
309 len = sprintf(buf, "4480\n");
315 static ssize_t lis3l02dq_write_frequency(struct device *dev,
316 struct device_attribute *attr,
320 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
325 ret = kstrtoul(buf, 10, &val);
329 mutex_lock(&indio_dev->mlock);
330 ret = lis3l02dq_spi_read_reg_8(indio_dev,
331 LIS3L02DQ_REG_CTRL_1_ADDR,
334 goto error_ret_mutex;
335 /* Wipe the bits clean */
336 t &= ~LIS3L02DQ_DEC_MASK;
339 t |= LIS3L02DQ_REG_CTRL_1_DF_128;
342 t |= LIS3L02DQ_REG_CTRL_1_DF_64;
345 t |= LIS3L02DQ_REG_CTRL_1_DF_32;
348 t |= LIS3L02DQ_REG_CTRL_1_DF_8;
352 goto error_ret_mutex;
355 ret = lis3l02dq_spi_write_reg_8(indio_dev,
356 LIS3L02DQ_REG_CTRL_1_ADDR,
360 mutex_unlock(&indio_dev->mlock);
362 return ret ? ret : len;
365 static int lis3l02dq_initial_setup(struct iio_dev *indio_dev)
367 struct lis3l02dq_state *st = iio_priv(indio_dev);
371 st->us->mode = SPI_MODE_3;
375 val = LIS3L02DQ_DEFAULT_CTRL1;
376 /* Write suitable defaults to ctrl1 */
377 ret = lis3l02dq_spi_write_reg_8(indio_dev,
378 LIS3L02DQ_REG_CTRL_1_ADDR,
381 dev_err(&st->us->dev, "problem with setup control register 1");
384 /* Repeat as sometimes doesn't work first time? */
385 ret = lis3l02dq_spi_write_reg_8(indio_dev,
386 LIS3L02DQ_REG_CTRL_1_ADDR,
389 dev_err(&st->us->dev, "problem with setup control register 1");
393 /* Read back to check this has worked acts as loose test of correct
395 ret = lis3l02dq_spi_read_reg_8(indio_dev,
396 LIS3L02DQ_REG_CTRL_1_ADDR,
398 if (ret || (valtest != val)) {
399 dev_err(&indio_dev->dev,
400 "device not playing ball %d %d\n", valtest, val);
405 val = LIS3L02DQ_DEFAULT_CTRL2;
406 ret = lis3l02dq_spi_write_reg_8(indio_dev,
407 LIS3L02DQ_REG_CTRL_2_ADDR,
410 dev_err(&st->us->dev, "problem with setup control register 2");
414 val = LIS3L02DQ_REG_WAKE_UP_CFG_LATCH_SRC;
415 ret = lis3l02dq_spi_write_reg_8(indio_dev,
416 LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
419 dev_err(&st->us->dev, "problem with interrupt cfg register");
425 static IIO_DEV_ATTR_SAMP_FREQ(S_IWUSR | S_IRUGO,
426 lis3l02dq_read_frequency,
427 lis3l02dq_write_frequency);
429 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("280 560 1120 4480");
431 static irqreturn_t lis3l02dq_event_handler(int irq, void *private)
433 struct iio_dev *indio_dev = private;
436 s64 timestamp = iio_get_time_ns();
438 lis3l02dq_spi_read_reg_8(indio_dev,
439 LIS3L02DQ_REG_WAKE_UP_SRC_ADDR,
442 if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Z_HIGH)
443 iio_push_event(indio_dev,
444 IIO_MOD_EVENT_CODE(IIO_ACCEL,
451 if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Z_LOW)
452 iio_push_event(indio_dev,
453 IIO_MOD_EVENT_CODE(IIO_ACCEL,
460 if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Y_HIGH)
461 iio_push_event(indio_dev,
462 IIO_MOD_EVENT_CODE(IIO_ACCEL,
469 if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Y_LOW)
470 iio_push_event(indio_dev,
471 IIO_MOD_EVENT_CODE(IIO_ACCEL,
478 if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_X_HIGH)
479 iio_push_event(indio_dev,
480 IIO_MOD_EVENT_CODE(IIO_ACCEL,
487 if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_X_LOW)
488 iio_push_event(indio_dev,
489 IIO_MOD_EVENT_CODE(IIO_ACCEL,
496 /* Ack and allow for new interrupts */
497 lis3l02dq_spi_read_reg_8(indio_dev,
498 LIS3L02DQ_REG_WAKE_UP_ACK_ADDR,
504 #define LIS3L02DQ_INFO_MASK \
505 (IIO_CHAN_INFO_RAW_SEPARATE_BIT | \
506 IIO_CHAN_INFO_SCALE_SHARED_BIT | \
507 IIO_CHAN_INFO_CALIBSCALE_SEPARATE_BIT | \
508 IIO_CHAN_INFO_CALIBBIAS_SEPARATE_BIT)
510 #define LIS3L02DQ_EVENT_MASK \
511 (IIO_EV_BIT(IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING) | \
512 IIO_EV_BIT(IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING))
514 #define LIS3L02DQ_CHAN(index, mod) \
519 .info_mask = LIS3L02DQ_INFO_MASK, \
521 .scan_index = index, \
527 .event_mask = LIS3L02DQ_EVENT_MASK, \
530 static const struct iio_chan_spec lis3l02dq_channels[] = {
531 LIS3L02DQ_CHAN(0, IIO_MOD_X),
532 LIS3L02DQ_CHAN(1, IIO_MOD_Y),
533 LIS3L02DQ_CHAN(2, IIO_MOD_Z),
534 IIO_CHAN_SOFT_TIMESTAMP(3)
538 static int lis3l02dq_read_event_config(struct iio_dev *indio_dev,
544 u8 mask = (1 << (IIO_EVENT_CODE_EXTRACT_MODIFIER(event_code)*2 +
545 (IIO_EVENT_CODE_EXTRACT_DIR(event_code) ==
546 IIO_EV_DIR_RISING)));
547 ret = lis3l02dq_spi_read_reg_8(indio_dev,
548 LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
553 return !!(val & mask);
556 int lis3l02dq_disable_all_events(struct iio_dev *indio_dev)
561 ret = lis3l02dq_spi_read_reg_8(indio_dev,
562 LIS3L02DQ_REG_CTRL_2_ADDR,
565 control &= ~LIS3L02DQ_REG_CTRL_2_ENABLE_INTERRUPT;
566 ret = lis3l02dq_spi_write_reg_8(indio_dev,
567 LIS3L02DQ_REG_CTRL_2_ADDR,
571 /* Also for consistency clear the mask */
572 ret = lis3l02dq_spi_read_reg_8(indio_dev,
573 LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
579 ret = lis3l02dq_spi_write_reg_8(indio_dev,
580 LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
590 static int lis3l02dq_write_event_config(struct iio_dev *indio_dev,
597 bool changed = false;
598 u8 mask = (1 << (IIO_EVENT_CODE_EXTRACT_MODIFIER(event_code)*2 +
599 (IIO_EVENT_CODE_EXTRACT_DIR(event_code) ==
600 IIO_EV_DIR_RISING)));
602 mutex_lock(&indio_dev->mlock);
603 /* read current control */
604 ret = lis3l02dq_spi_read_reg_8(indio_dev,
605 LIS3L02DQ_REG_CTRL_2_ADDR,
609 ret = lis3l02dq_spi_read_reg_8(indio_dev,
610 LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
614 currentlyset = val & mask;
616 if (!currentlyset && state) {
619 } else if (currentlyset && !state) {
625 ret = lis3l02dq_spi_write_reg_8(indio_dev,
626 LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
630 control = val & 0x3f ?
631 (control | LIS3L02DQ_REG_CTRL_2_ENABLE_INTERRUPT) :
632 (control & ~LIS3L02DQ_REG_CTRL_2_ENABLE_INTERRUPT);
633 ret = lis3l02dq_spi_write_reg_8(indio_dev,
634 LIS3L02DQ_REG_CTRL_2_ADDR,
641 mutex_unlock(&indio_dev->mlock);
645 static struct attribute *lis3l02dq_attributes[] = {
646 &iio_dev_attr_sampling_frequency.dev_attr.attr,
647 &iio_const_attr_sampling_frequency_available.dev_attr.attr,
651 static const struct attribute_group lis3l02dq_attribute_group = {
652 .attrs = lis3l02dq_attributes,
655 static const struct iio_info lis3l02dq_info = {
656 .read_raw = &lis3l02dq_read_raw,
657 .write_raw = &lis3l02dq_write_raw,
658 .read_event_value = &lis3l02dq_read_thresh,
659 .write_event_value = &lis3l02dq_write_thresh,
660 .write_event_config = &lis3l02dq_write_event_config,
661 .read_event_config = &lis3l02dq_read_event_config,
662 .driver_module = THIS_MODULE,
663 .attrs = &lis3l02dq_attribute_group,
666 static int lis3l02dq_probe(struct spi_device *spi)
669 struct lis3l02dq_state *st;
670 struct iio_dev *indio_dev;
672 indio_dev = iio_device_alloc(sizeof *st);
673 if (indio_dev == NULL) {
677 st = iio_priv(indio_dev);
678 /* this is only used for removal purposes */
679 spi_set_drvdata(spi, indio_dev);
682 st->gpio = of_get_gpio(spi->dev.of_node, 0);
683 mutex_init(&st->buf_lock);
684 indio_dev->name = spi->dev.driver->name;
685 indio_dev->dev.parent = &spi->dev;
686 indio_dev->info = &lis3l02dq_info;
687 indio_dev->channels = lis3l02dq_channels;
688 indio_dev->num_channels = ARRAY_SIZE(lis3l02dq_channels);
690 indio_dev->modes = INDIO_DIRECT_MODE;
692 ret = lis3l02dq_configure_buffer(indio_dev);
696 ret = iio_buffer_register(indio_dev,
698 ARRAY_SIZE(lis3l02dq_channels));
700 printk(KERN_ERR "failed to initialize the buffer\n");
701 goto error_unreg_buffer_funcs;
705 ret = request_threaded_irq(st->us->irq,
707 &lis3l02dq_event_handler,
712 goto error_uninitialize_buffer;
714 ret = lis3l02dq_probe_trigger(indio_dev);
716 goto error_free_interrupt;
719 /* Get the device into a sane initial state */
720 ret = lis3l02dq_initial_setup(indio_dev);
722 goto error_remove_trigger;
724 ret = iio_device_register(indio_dev);
726 goto error_remove_trigger;
730 error_remove_trigger:
732 lis3l02dq_remove_trigger(indio_dev);
733 error_free_interrupt:
735 free_irq(st->us->irq, indio_dev);
736 error_uninitialize_buffer:
737 iio_buffer_unregister(indio_dev);
738 error_unreg_buffer_funcs:
739 lis3l02dq_unconfigure_buffer(indio_dev);
741 iio_device_free(indio_dev);
746 /* Power down the device */
747 static int lis3l02dq_stop_device(struct iio_dev *indio_dev)
750 struct lis3l02dq_state *st = iio_priv(indio_dev);
753 mutex_lock(&indio_dev->mlock);
754 ret = lis3l02dq_spi_write_reg_8(indio_dev,
755 LIS3L02DQ_REG_CTRL_1_ADDR,
758 dev_err(&st->us->dev, "problem with turning device off: ctrl1");
762 ret = lis3l02dq_spi_write_reg_8(indio_dev,
763 LIS3L02DQ_REG_CTRL_2_ADDR,
766 dev_err(&st->us->dev, "problem with turning device off: ctrl2");
768 mutex_unlock(&indio_dev->mlock);
772 /* fixme, confirm ordering in this function */
773 static int lis3l02dq_remove(struct spi_device *spi)
775 struct iio_dev *indio_dev = spi_get_drvdata(spi);
776 struct lis3l02dq_state *st = iio_priv(indio_dev);
778 iio_device_unregister(indio_dev);
780 lis3l02dq_disable_all_events(indio_dev);
781 lis3l02dq_stop_device(indio_dev);
784 free_irq(st->us->irq, indio_dev);
786 lis3l02dq_remove_trigger(indio_dev);
787 iio_buffer_unregister(indio_dev);
788 lis3l02dq_unconfigure_buffer(indio_dev);
790 iio_device_free(indio_dev);
795 static struct spi_driver lis3l02dq_driver = {
798 .owner = THIS_MODULE,
800 .probe = lis3l02dq_probe,
801 .remove = lis3l02dq_remove,
803 module_spi_driver(lis3l02dq_driver);
805 MODULE_AUTHOR("Jonathan Cameron <jic23@kernel.org>");
806 MODULE_DESCRIPTION("ST LIS3L02DQ Accelerometer SPI driver");
807 MODULE_LICENSE("GPL v2");
808 MODULE_ALIAS("spi:lis3l02dq");