Pileus Git - ~andy/linux/blob - drivers/staging/iio/accel/lis3l02dq_core.c

   1 /*
   2  * lis3l02dq.c  support STMicroelectronics LISD02DQ
   3  *              3d 2g Linear Accelerometers via SPI
   4  *
   5  * Copyright (c) 2007 Jonathan Cameron <jic23@cam.ac.uk>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * Settings:
  12  * 16 bit left justified mode used.
  13  */
  14
  15 #include <linux/interrupt.h>
  16 #include <linux/irq.h>
  17 #include <linux/gpio.h>
  18 #include <linux/workqueue.h>
  19 #include <linux/mutex.h>
  20 #include <linux/device.h>
  21 #include <linux/kernel.h>
  22 #include <linux/spi/spi.h>
  23 #include <linux/slab.h>
  24
  25 #include <linux/sysfs.h>
  26 #include <linux/list.h>
  27
  28 #include "../iio.h"
  29 #include "../sysfs.h"
  30 #include "../ring_generic.h"
  31 #include "../ring_sw.h"
  32
  33 #include "accel.h"
  34
  35 #include "lis3l02dq.h"
  36
  37 /* At the moment the spi framework doesn't allow global setting of cs_change.
  38  * It's in the likely to be added comment at the top of spi.h.
  39  * This means that use cannot be made of spi_write etc.
  40  */
  41
  42 /**
  43  * lis3l02dq_spi_read_reg_8() - read single byte from a single register
  44  * @indio_dev: iio_dev for this actual device
  45  * @reg_address: the address of the register to be read
  46  * @val: pass back the resulting value
  47  **/
  48 int lis3l02dq_spi_read_reg_8(struct iio_dev *indio_dev,
  49                              u8 reg_address, u8 *val)
  50 {
  51         struct iio_sw_ring_helper_state *h = iio_dev_get_devdata(indio_dev);
  52         struct lis3l02dq_state *st = lis3l02dq_h_to_s(h);
  53         struct spi_message msg;
  54         int ret;
  55         struct spi_transfer xfer = {
  56                 .tx_buf = st->tx,
  57                 .rx_buf = st->rx,
  58                 .bits_per_word = 8,
  59                 .len = 2,
  60         };
  61
  62         mutex_lock(&st->buf_lock);
  63         st->tx[0] = LIS3L02DQ_READ_REG(reg_address);
  64         st->tx[1] = 0;
  65
  66         spi_message_init(&msg);
  67         spi_message_add_tail(&xfer, &msg);
  68         ret = spi_sync(st->us, &msg);
  69         *val = st->rx[1];
  70         mutex_unlock(&st->buf_lock);
  71
  72         return ret;
  73 }
  74
  75 /**
  76  * lis3l02dq_spi_write_reg_8() - write single byte to a register
  77  * @indio_dev: iio_dev for this device
  78  * @reg_address: the address of the register to be written
  79  * @val: the value to write
  80  **/
  81 int lis3l02dq_spi_write_reg_8(struct iio_dev *indio_dev,
  82                               u8 reg_address,
  83                               u8 *val)
  84 {
  85         int ret;
  86         struct iio_sw_ring_helper_state *h
  87                 = iio_dev_get_devdata(indio_dev);
  88         struct lis3l02dq_state *st = lis3l02dq_h_to_s(h);
  89
  90         mutex_lock(&st->buf_lock);
  91         st->tx[0] = LIS3L02DQ_WRITE_REG(reg_address);
  92         st->tx[1] = *val;
  93         ret = spi_write(st->us, st->tx, 2);
  94         mutex_unlock(&st->buf_lock);
  95
  96         return ret;
  97 }
  98
  99 /**
 100  * lisl302dq_spi_write_reg_s16() - write 2 bytes to a pair of registers
 101  * @indio_dev: iio_dev for this device
 102  * @lower_reg_address: the address of the lower of the two registers.
 103  *               Second register is assumed to have address one greater.
 104  * @value: value to be written
 105  **/
 106 static int lis3l02dq_spi_write_reg_s16(struct iio_dev *indio_dev,
 107                                        u8 lower_reg_address,
 108                                        s16 value)
 109 {
 110         int ret;
 111         struct spi_message msg;
 112         struct iio_sw_ring_helper_state *h
 113                 = iio_dev_get_devdata(indio_dev);
 114         struct lis3l02dq_state *st = lis3l02dq_h_to_s(h);
 115         struct spi_transfer xfers[] = { {
 116                         .tx_buf = st->tx,
 117                         .bits_per_word = 8,
 118                         .len = 2,
 119                         .cs_change = 1,
 120                 }, {
 121                         .tx_buf = st->tx + 2,
 122                         .bits_per_word = 8,
 123                         .len = 2,
 124                 },
 125         };
 126
 127         mutex_lock(&st->buf_lock);
 128         st->tx[0] = LIS3L02DQ_WRITE_REG(lower_reg_address);
 129         st->tx[1] = value & 0xFF;
 130         st->tx[2] = LIS3L02DQ_WRITE_REG(lower_reg_address + 1);
 131         st->tx[3] = (value >> 8) & 0xFF;
 132
 133         spi_message_init(&msg);
 134         spi_message_add_tail(&xfers[0], &msg);
 135         spi_message_add_tail(&xfers[1], &msg);
 136         ret = spi_sync(st->us, &msg);
 137         mutex_unlock(&st->buf_lock);
 138
 139         return ret;
 140 }
 141
 142 static int lis3l02dq_read_reg_s16(struct iio_dev *indio_dev,
 143                                   u8 lower_reg_address,
 144                                   int *val)
 145 {
 146         struct iio_sw_ring_helper_state *h
 147                 = iio_dev_get_devdata(indio_dev);
 148         struct lis3l02dq_state *st = lis3l02dq_h_to_s(h);
 149
 150         struct spi_message msg;
 151         int ret;
 152         s16 tempval;
 153         struct spi_transfer xfers[] = { {
 154                         .tx_buf = st->tx,
 155                         .rx_buf = st->rx,
 156                         .bits_per_word = 8,
 157                         .len = 2,
 158                         .cs_change = 1,
 159                 }, {
 160                         .tx_buf = st->tx + 2,
 161                         .rx_buf = st->rx + 2,
 162                         .bits_per_word = 8,
 163                         .len = 2,
 164                 },
 165         };
 166
 167         mutex_lock(&st->buf_lock);
 168         st->tx[0] = LIS3L02DQ_READ_REG(lower_reg_address);
 169         st->tx[1] = 0;
 170         st->tx[2] = LIS3L02DQ_READ_REG(lower_reg_address + 1);
 171         st->tx[3] = 0;
 172
 173         spi_message_init(&msg);
 174         spi_message_add_tail(&xfers[0], &msg);
 175         spi_message_add_tail(&xfers[1], &msg);
 176         ret = spi_sync(st->us, &msg);
 177         if (ret) {
 178                 dev_err(&st->us->dev, "problem when reading 16 bit register");
 179                 goto error_ret;
 180         }
 181         tempval = (s16)(st->rx[1]) | ((s16)(st->rx[3]) << 8);
 182
 183         *val = tempval;
 184 error_ret:
 185         mutex_unlock(&st->buf_lock);
 186         return ret;
 187 }
 188
 189 enum lis3l02dq_rm_ind {
 190         LIS3L02DQ_ACCEL,
 191         LIS3L02DQ_GAIN,
 192         LIS3L02DQ_BIAS,
 193 };
 194
 195 static u8 lis3l02dq_axis_map[3][3] = {
 196         [LIS3L02DQ_ACCEL] = { LIS3L02DQ_REG_OUT_X_L_ADDR,
 197                               LIS3L02DQ_REG_OUT_Y_L_ADDR,
 198                               LIS3L02DQ_REG_OUT_Z_L_ADDR },
 199         [LIS3L02DQ_GAIN] = { LIS3L02DQ_REG_GAIN_X_ADDR,
 200                              LIS3L02DQ_REG_GAIN_Y_ADDR,
 201                              LIS3L02DQ_REG_GAIN_Z_ADDR },
 202         [LIS3L02DQ_BIAS] = { LIS3L02DQ_REG_OFFSET_X_ADDR,
 203                              LIS3L02DQ_REG_OFFSET_Y_ADDR,
 204                              LIS3L02DQ_REG_OFFSET_Z_ADDR }
 205 };
 206
 207 static int lis3l02dq_read_thresh(struct iio_dev *indio_dev,
 208                                  int e,
 209                                  int *val)
 210 {
 211         return lis3l02dq_read_reg_s16(indio_dev, LIS3L02DQ_REG_THS_L_ADDR, val);
 212 }
 213
 214 static int lis3l02dq_write_thresh(struct iio_dev *indio_dev,
 215                                   int event_code,
 216                                   int val)
 217 {
 218         u16 value = val;
 219         return lis3l02dq_spi_write_reg_s16(indio_dev,
 220                                            LIS3L02DQ_REG_THS_L_ADDR,
 221                                            value);
 222 }
 223
 224 static int lis3l02dq_read_raw(struct iio_dev *indio_dev,
 225                               struct iio_chan_spec const *chan,
 226                               int *val,
 227                               int *val2,
 228                               long mask)
 229 {
 230         u8 utemp;
 231         s8 stemp;
 232         ssize_t ret = 0;
 233         u8 reg;
 234
 235         switch (mask) {
 236         case 0:
 237                 /* Take the iio_dev status lock */
 238                 mutex_lock(&indio_dev->mlock);
 239                 if (indio_dev->currentmode == INDIO_RING_TRIGGERED)
 240                         ret = lis3l02dq_read_accel_from_ring(indio_dev->ring,
 241                                                              chan->scan_index,
 242                                                              val);
 243                 else {
 244                         reg = lis3l02dq_axis_map
 245                                 [LIS3L02DQ_ACCEL][chan->address];
 246                         ret = lis3l02dq_read_reg_s16(indio_dev, reg, val);
 247                 }
 248                 mutex_unlock(&indio_dev->mlock);
 249                 return IIO_VAL_INT;
 250         case (1 << IIO_CHAN_INFO_SCALE_SHARED):
 251                 *val = 0;
 252                 *val2 = 9580;
 253                 return IIO_VAL_INT_PLUS_MICRO;
 254         case (1 << IIO_CHAN_INFO_CALIBSCALE_SEPARATE):
 255                 reg = lis3l02dq_axis_map[LIS3L02DQ_GAIN][chan->address];
 256                 ret = lis3l02dq_spi_read_reg_8(indio_dev, reg, &utemp);
 257                 if (ret)
 258                         goto error_ret;
 259                 /* to match with what previous code does */
 260                 *val = utemp;
 261                 return IIO_VAL_INT;
 262
 263         case (1 << IIO_CHAN_INFO_CALIBBIAS_SEPARATE):
 264                 reg = lis3l02dq_axis_map[LIS3L02DQ_BIAS][chan->address];
 265                 ret = lis3l02dq_spi_read_reg_8(indio_dev, reg, (u8 *)&stemp);
 266                 /* to match with what previous code does */
 267                 *val = stemp;
 268                 return IIO_VAL_INT;
 269         }
 270 error_ret:
 271         return ret;
 272 }
 273
 274 static ssize_t lis3l02dq_read_frequency(struct device *dev,
 275                                         struct device_attribute *attr,
 276                                         char *buf)
 277 {
 278         struct iio_dev *indio_dev = dev_get_drvdata(dev);
 279         int ret, len = 0;
 280         s8 t;
 281         ret = lis3l02dq_spi_read_reg_8(indio_dev,
 282                                        LIS3L02DQ_REG_CTRL_1_ADDR,
 283                                        (u8 *)&t);
 284         if (ret)
 285                 return ret;
 286         t &= LIS3L02DQ_DEC_MASK;
 287         switch (t) {
 288         case LIS3L02DQ_REG_CTRL_1_DF_128:
 289                 len = sprintf(buf, "280\n");
 290                 break;
 291         case LIS3L02DQ_REG_CTRL_1_DF_64:
 292                 len = sprintf(buf, "560\n");
 293                 break;
 294         case LIS3L02DQ_REG_CTRL_1_DF_32:
 295                 len = sprintf(buf, "1120\n");
 296                 break;
 297         case LIS3L02DQ_REG_CTRL_1_DF_8:
 298                 len = sprintf(buf, "4480\n");
 299                 break;
 300         }
 301         return len;
 302 }
 303
 304 static ssize_t lis3l02dq_write_frequency(struct device *dev,
 305                                          struct device_attribute *attr,
 306                                          const char *buf,
 307                                          size_t len)
 308 {
 309         struct iio_dev *indio_dev = dev_get_drvdata(dev);
 310         long val;
 311         int ret;
 312         u8 t;
 313
 314         ret = strict_strtol(buf, 10, &val);
 315         if (ret)
 316                 return ret;
 317
 318         mutex_lock(&indio_dev->mlock);
 319         ret = lis3l02dq_spi_read_reg_8(indio_dev,
 320                                        LIS3L02DQ_REG_CTRL_1_ADDR,
 321                                        &t);
 322         if (ret)
 323                 goto error_ret_mutex;
 324         /* Wipe the bits clean */
 325         t &= ~LIS3L02DQ_DEC_MASK;
 326         switch (val) {
 327         case 280:
 328                 t |= LIS3L02DQ_REG_CTRL_1_DF_128;
 329                 break;
 330         case 560:
 331                 t |= LIS3L02DQ_REG_CTRL_1_DF_64;
 332                 break;
 333         case 1120:
 334                 t |= LIS3L02DQ_REG_CTRL_1_DF_32;
 335                 break;
 336         case 4480:
 337                 t |= LIS3L02DQ_REG_CTRL_1_DF_8;
 338                 break;
 339         default:
 340                 ret = -EINVAL;
 341                 goto error_ret_mutex;
 342         }
 343
 344         ret = lis3l02dq_spi_write_reg_8(indio_dev,
 345                                         LIS3L02DQ_REG_CTRL_1_ADDR,
 346                                         &t);
 347
 348 error_ret_mutex:
 349         mutex_unlock(&indio_dev->mlock);
 350
 351         return ret ? ret : len;
 352 }
 353
 354 static int lis3l02dq_initial_setup(struct lis3l02dq_state *st)
 355 {
 356         int ret;
 357         u8 val, valtest;
 358
 359         st->us->mode = SPI_MODE_3;
 360
 361         spi_setup(st->us);
 362
 363         val = LIS3L02DQ_DEFAULT_CTRL1;
 364         /* Write suitable defaults to ctrl1 */
 365         ret = lis3l02dq_spi_write_reg_8(st->help.indio_dev,
 366                                         LIS3L02DQ_REG_CTRL_1_ADDR,
 367                                         &val);
 368         if (ret) {
 369                 dev_err(&st->us->dev, "problem with setup control register 1");
 370                 goto err_ret;
 371         }
 372         /* Repeat as sometimes doesn't work first time?*/
 373         ret = lis3l02dq_spi_write_reg_8(st->help.indio_dev,
 374                                         LIS3L02DQ_REG_CTRL_1_ADDR,
 375                                         &val);
 376         if (ret) {
 377                 dev_err(&st->us->dev, "problem with setup control register 1");
 378                 goto err_ret;
 379         }
 380
 381         /* Read back to check this has worked acts as loose test of correct
 382          * chip */
 383         ret = lis3l02dq_spi_read_reg_8(st->help.indio_dev,
 384                                        LIS3L02DQ_REG_CTRL_1_ADDR,
 385                                        &valtest);
 386         if (ret || (valtest != val)) {
 387                 dev_err(&st->help.indio_dev->dev,
 388                         "device not playing ball %d %d\n", valtest, val);
 389                 ret = -EINVAL;
 390                 goto err_ret;
 391         }
 392
 393         val = LIS3L02DQ_DEFAULT_CTRL2;
 394         ret = lis3l02dq_spi_write_reg_8(st->help.indio_dev,
 395                                         LIS3L02DQ_REG_CTRL_2_ADDR,
 396                                         &val);
 397         if (ret) {
 398                 dev_err(&st->us->dev, "problem with setup control register 2");
 399                 goto err_ret;
 400         }
 401
 402         val = LIS3L02DQ_REG_WAKE_UP_CFG_LATCH_SRC;
 403         ret = lis3l02dq_spi_write_reg_8(st->help.indio_dev,
 404                                         LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
 405                                         &val);
 406         if (ret)
 407                 dev_err(&st->us->dev, "problem with interrupt cfg register");
 408 err_ret:
 409
 410         return ret;
 411 }
 412
 413 static IIO_DEV_ATTR_SAMP_FREQ(S_IWUSR | S_IRUGO,
 414                               lis3l02dq_read_frequency,
 415                               lis3l02dq_write_frequency);
 416
 417 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("280 560 1120 4480");
 418
 419 static irqreturn_t lis3l02dq_event_handler(int irq, void *_int_info)
 420 {
 421         struct iio_interrupt *int_info = _int_info;
 422         struct iio_dev *indio_dev = int_info->dev_info;
 423         struct iio_sw_ring_helper_state *h
 424                 = iio_dev_get_devdata(indio_dev);
 425         struct lis3l02dq_state *st = lis3l02dq_h_to_s(h);
 426
 427         disable_irq_nosync(irq);
 428         st->thresh_timestamp = iio_get_time_ns();
 429         schedule_work(&st->work_thresh);
 430
 431         return IRQ_HANDLED;
 432 }
 433
 434 #define LIS3L02DQ_INFO_MASK                             \
 435         ((1 << IIO_CHAN_INFO_SCALE_SHARED) |            \
 436          (1 << IIO_CHAN_INFO_CALIBSCALE_SEPARATE) |     \
 437          (1 << IIO_CHAN_INFO_CALIBBIAS_SEPARATE))
 438
 439 #define LIS3L02DQ_EVENT_MASK                                    \
 440         (IIO_EV_BIT(IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING) |    \
 441          IIO_EV_BIT(IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING))
 442
 443 static struct iio_chan_spec lis3l02dq_channels[] = {
 444         IIO_CHAN(IIO_ACCEL, 1, 0, 0, NULL, 0, IIO_MOD_X, LIS3L02DQ_INFO_MASK,
 445                  0, 0, IIO_ST('s', 12, 16, 0),
 446                  LIS3L02DQ_EVENT_MASK, NULL),
 447         IIO_CHAN(IIO_ACCEL, 1, 0, 0, NULL, 0, IIO_MOD_Y, LIS3L02DQ_INFO_MASK,
 448                  1, 1, IIO_ST('s', 12, 16, 0),
 449                  LIS3L02DQ_EVENT_MASK, NULL),
 450         IIO_CHAN(IIO_ACCEL, 1, 0, 0, NULL, 0, IIO_MOD_Z, LIS3L02DQ_INFO_MASK,
 451                  2, 2, IIO_ST('s', 12, 16, 0),
 452                  LIS3L02DQ_EVENT_MASK, NULL),
 453         IIO_CHAN_SOFT_TIMESTAMP(3)
 454 };
 455
 456
 457 static ssize_t lis3l02dq_read_event_config(struct iio_dev *indio_dev,
 458                                            int event_code)
 459 {
 460
 461         u8 val;
 462         int ret;
 463         u8 mask = (1 << (IIO_EVENT_CODE_EXTRACT_MODIFIER(event_code)*2 +
 464                          (IIO_EVENT_CODE_EXTRACT_DIR(event_code) ==
 465                           IIO_EV_DIR_RISING)));
 466         ret = lis3l02dq_spi_read_reg_8(indio_dev,
 467                                        LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
 468                                        &val);
 469         if (ret < 0)
 470                 return ret;
 471
 472         return !!(val & mask);
 473 }
 474
 475 int lis3l02dq_disable_all_events(struct iio_dev *indio_dev)
 476 {
 477         struct iio_sw_ring_helper_state *h
 478                 = iio_dev_get_devdata(indio_dev);
 479         struct lis3l02dq_state *st = lis3l02dq_h_to_s(h);
 480         int ret;
 481         u8 control, val;
 482         bool irqtofree;
 483
 484         ret = lis3l02dq_spi_read_reg_8(indio_dev,
 485                                        LIS3L02DQ_REG_CTRL_2_ADDR,
 486                                        &control);
 487
 488         irqtofree = !!(control & LIS3L02DQ_REG_CTRL_2_ENABLE_INTERRUPT);
 489
 490         control &= ~LIS3L02DQ_REG_CTRL_2_ENABLE_INTERRUPT;
 491         ret = lis3l02dq_spi_write_reg_8(indio_dev,
 492                                         LIS3L02DQ_REG_CTRL_2_ADDR,
 493                                         &control);
 494         if (ret)
 495                 goto error_ret;
 496         /* Also for consistency clear the mask */
 497         ret = lis3l02dq_spi_read_reg_8(indio_dev,
 498                                        LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
 499                                        &val);
 500         if (ret)
 501                 goto error_ret;
 502         val &= ~0x3f;
 503
 504         ret = lis3l02dq_spi_write_reg_8(indio_dev,
 505                                         LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
 506                                         &val);
 507         if (ret)
 508                 goto error_ret;
 509
 510         if (irqtofree)
 511                 free_irq(st->us->irq, indio_dev->interrupts[0]);
 512
 513         ret = control;
 514 error_ret:
 515         return ret;
 516 }
 517
 518 static int lis3l02dq_write_event_config(struct iio_dev *indio_dev,
 519                                         int event_code,
 520                                         struct iio_event_handler_list *list_el,
 521                                         int state)
 522 {
 523         struct iio_sw_ring_helper_state *h
 524                 = iio_dev_get_devdata(indio_dev);
 525         struct lis3l02dq_state *st = lis3l02dq_h_to_s(h);
 526         int ret = 0;
 527         u8 val, control;
 528         u8 currentlyset;
 529         bool changed = false;
 530         u8 mask = (1 << (IIO_EVENT_CODE_EXTRACT_MODIFIER(event_code)*2 +
 531                          (IIO_EVENT_CODE_EXTRACT_DIR(event_code) ==
 532                           IIO_EV_DIR_RISING)));
 533
 534         mutex_lock(&indio_dev->mlock);
 535         /* read current control */
 536         ret = lis3l02dq_spi_read_reg_8(indio_dev,
 537                                        LIS3L02DQ_REG_CTRL_2_ADDR,
 538                                        &control);
 539         if (ret)
 540                 goto error_ret;
 541         ret = lis3l02dq_spi_read_reg_8(indio_dev,
 542                                        LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
 543                                        &val);
 544         if (ret < 0)
 545                 goto error_ret;
 546         currentlyset = val & mask;
 547
 548         if (!currentlyset && state) {
 549                 changed = true;
 550                 val |= mask;
 551         } else if (currentlyset && !state) {
 552                 changed = true;
 553                 val &= ~mask;
 554         }
 555
 556         if (changed) {
 557                 if (!(control & LIS3L02DQ_REG_CTRL_2_ENABLE_INTERRUPT)) {
 558                         ret = request_irq(st->us->irq,
 559                                           &lis3l02dq_event_handler,
 560                                           IRQF_TRIGGER_RISING,
 561                                           "lis3l02dq_event",
 562                                           indio_dev->interrupts[0]);
 563                         if (ret)
 564                                 goto error_ret;
 565                 }
 566
 567                 ret = lis3l02dq_spi_write_reg_8(indio_dev,
 568                                                 LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
 569                                                 &val);
 570                 if (ret)
 571                         goto error_ret;
 572                 control = val & 0x3f ?
 573                         (control | LIS3L02DQ_REG_CTRL_2_ENABLE_INTERRUPT) :
 574                         (control & ~LIS3L02DQ_REG_CTRL_2_ENABLE_INTERRUPT);
 575                 ret = lis3l02dq_spi_write_reg_8(indio_dev,
 576                                                LIS3L02DQ_REG_CTRL_2_ADDR,
 577                                                &control);
 578                 if (ret)
 579                         goto error_ret;
 580
 581                 /* remove interrupt handler if nothing is still on */
 582                 if (!(val & 0x3f))
 583                         free_irq(st->us->irq, indio_dev->interrupts[0]);
 584         }
 585
 586 error_ret:
 587         mutex_unlock(&indio_dev->mlock);
 588         return ret;
 589 }
 590
 591 /* Unforunately it appears the interrupt won't clear unless you read from the
 592  * src register.
 593  */
 594 static void lis3l02dq_thresh_handler_bh_no_check(struct work_struct *work_s)
 595 {
 596         struct lis3l02dq_state *st
 597                 = container_of(work_s,
 598                                struct lis3l02dq_state, work_thresh);
 599         u8 t;
 600
 601         lis3l02dq_spi_read_reg_8(st->help.indio_dev,
 602                                  LIS3L02DQ_REG_WAKE_UP_SRC_ADDR,
 603                                  &t);
 604
 605         if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Z_HIGH)
 606                 iio_push_event(st->help.indio_dev, 0,
 607                                IIO_MOD_EVENT_CODE(IIO_EV_CLASS_ACCEL,
 608                                                   0,
 609                                                   IIO_EV_MOD_Z,
 610                                                   IIO_EV_TYPE_THRESH,
 611                                                   IIO_EV_DIR_RISING),
 612                                st->thresh_timestamp);
 613
 614         if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Z_LOW)
 615                 iio_push_event(st->help.indio_dev, 0,
 616                                IIO_MOD_EVENT_CODE(IIO_EV_CLASS_ACCEL,
 617                                                   0,
 618                                                   IIO_EV_MOD_Z,
 619                                                   IIO_EV_TYPE_THRESH,
 620                                                   IIO_EV_DIR_FALLING),
 621                                st->thresh_timestamp);
 622
 623         if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Y_HIGH)
 624                 iio_push_event(st->help.indio_dev, 0,
 625                                IIO_MOD_EVENT_CODE(IIO_EV_CLASS_ACCEL,
 626                                                   0,
 627                                                   IIO_EV_MOD_Y,
 628                                                   IIO_EV_TYPE_THRESH,
 629                                                   IIO_EV_DIR_RISING),
 630                                st->thresh_timestamp);
 631
 632         if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Y_LOW)
 633                 iio_push_event(st->help.indio_dev, 0,
 634                                IIO_MOD_EVENT_CODE(IIO_EV_CLASS_ACCEL,
 635                                                   0,
 636                                                   IIO_EV_MOD_Y,
 637                                                   IIO_EV_TYPE_THRESH,
 638                                                   IIO_EV_DIR_FALLING),
 639                                st->thresh_timestamp);
 640
 641         if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_X_HIGH)
 642                 iio_push_event(st->help.indio_dev, 0,
 643                                IIO_MOD_EVENT_CODE(IIO_EV_CLASS_ACCEL,
 644                                                   0,
 645                                                   IIO_EV_MOD_X,
 646                                                   IIO_EV_TYPE_THRESH,
 647                                                   IIO_EV_DIR_RISING),
 648                                st->thresh_timestamp);
 649
 650         if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_X_LOW)
 651                 iio_push_event(st->help.indio_dev, 0,
 652                                IIO_MOD_EVENT_CODE(IIO_EV_CLASS_ACCEL,
 653                                                   0,
 654                                                   IIO_EV_MOD_X,
 655                                                   IIO_EV_TYPE_THRESH,
 656                                                   IIO_EV_DIR_FALLING),
 657                                st->thresh_timestamp);
 658         /* reenable the irq */
 659         enable_irq(st->us->irq);
 660         /* Ack and allow for new interrupts */
 661         lis3l02dq_spi_read_reg_8(st->help.indio_dev,
 662                                  LIS3L02DQ_REG_WAKE_UP_ACK_ADDR,
 663                                  &t);
 664
 665         return;
 666 }
 667
 668 static IIO_CONST_ATTR_NAME("lis3l02dq");
 669
 670 static struct attribute *lis3l02dq_attributes[] = {
 671         &iio_dev_attr_sampling_frequency.dev_attr.attr,
 672         &iio_const_attr_sampling_frequency_available.dev_attr.attr,
 673         &iio_const_attr_name.dev_attr.attr,
 674         NULL
 675 };
 676
 677 static const struct attribute_group lis3l02dq_attribute_group = {
 678         .attrs = lis3l02dq_attributes,
 679 };
 680
 681 static int __devinit lis3l02dq_probe(struct spi_device *spi)
 682 {
 683         int ret, regdone = 0;
 684         struct lis3l02dq_state *st = kzalloc(sizeof *st, GFP_KERNEL);
 685         if (!st) {
 686                 ret =  -ENOMEM;
 687                 goto error_ret;
 688         }
 689         INIT_WORK(&st->work_thresh, lis3l02dq_thresh_handler_bh_no_check);
 690         /* this is only used tor removal purposes */
 691         spi_set_drvdata(spi, st);
 692
 693         /* Allocate the comms buffers */
 694         st->rx = kzalloc(sizeof(*st->rx)*LIS3L02DQ_MAX_RX, GFP_KERNEL);
 695         if (st->rx == NULL) {
 696                 ret = -ENOMEM;
 697                 goto error_free_st;
 698         }
 699         st->tx = kzalloc(sizeof(*st->tx)*LIS3L02DQ_MAX_TX, GFP_KERNEL);
 700         if (st->tx == NULL) {
 701                 ret = -ENOMEM;
 702                 goto error_free_rx;
 703         }
 704         st->us = spi;
 705         mutex_init(&st->buf_lock);
 706         /* setup the industrialio driver allocated elements */
 707         st->help.indio_dev = iio_allocate_device(0);
 708         if (st->help.indio_dev == NULL) {
 709                 ret = -ENOMEM;
 710                 goto error_free_tx;
 711         }
 712
 713         st->help.indio_dev->dev.parent = &spi->dev;
 714         st->help.indio_dev->num_interrupt_lines = 1;
 715         st->help.indio_dev->channels = lis3l02dq_channels;
 716         st->help.indio_dev->num_channels = ARRAY_SIZE(lis3l02dq_channels);
 717         st->help.indio_dev->read_raw = &lis3l02dq_read_raw;
 718         st->help.indio_dev->read_event_value = &lis3l02dq_read_thresh;
 719         st->help.indio_dev->write_event_value = &lis3l02dq_write_thresh;
 720         st->help.indio_dev->write_event_config = &lis3l02dq_write_event_config;
 721         st->help.indio_dev->read_event_config = &lis3l02dq_read_event_config;
 722         st->help.indio_dev->attrs = &lis3l02dq_attribute_group;
 723         st->help.indio_dev->dev_data = (void *)(&st->help);
 724         st->help.indio_dev->driver_module = THIS_MODULE;
 725         st->help.indio_dev->modes = INDIO_DIRECT_MODE;
 726
 727         ret = lis3l02dq_configure_ring(st->help.indio_dev);
 728         if (ret)
 729                 goto error_free_dev;
 730
 731         ret = iio_device_register(st->help.indio_dev);
 732         if (ret)
 733                 goto error_unreg_ring_funcs;
 734         regdone = 1;
 735
 736         ret = iio_ring_buffer_register_ex(st->help.indio_dev->ring, 0,
 737                                           lis3l02dq_channels,
 738                                           ARRAY_SIZE(lis3l02dq_channels));
 739         if (ret) {
 740                 printk(KERN_ERR "failed to initialize the ring\n");
 741                 goto error_unreg_ring_funcs;
 742         }
 743
 744         if (spi->irq && gpio_is_valid(irq_to_gpio(spi->irq)) > 0) {
 745                 st->inter = 0;
 746                 ret = iio_register_interrupt_line(spi->irq,
 747                                                   st->help.indio_dev,
 748                                                   0,
 749                                                   IRQF_TRIGGER_RISING,
 750                                                   "lis3l02dq");
 751                 if (ret)
 752                         goto error_uninitialize_ring;
 753                 ret = lis3l02dq_probe_trigger(st->help.indio_dev);
 754                 if (ret)
 755                         goto error_unregister_line;
 756         }
 757
 758         /* Get the device into a sane initial state */
 759         ret = lis3l02dq_initial_setup(st);
 760         if (ret)
 761                 goto error_remove_trigger;
 762         return 0;
 763
 764 error_remove_trigger:
 765         if (st->help.indio_dev->modes & INDIO_RING_TRIGGERED)
 766                 lis3l02dq_remove_trigger(st->help.indio_dev);
 767 error_unregister_line:
 768         if (st->help.indio_dev->modes & INDIO_RING_TRIGGERED)
 769                 iio_unregister_interrupt_line(st->help.indio_dev, 0);
 770 error_uninitialize_ring:
 771         iio_ring_buffer_unregister(st->help.indio_dev->ring);
 772 error_unreg_ring_funcs:
 773         lis3l02dq_unconfigure_ring(st->help.indio_dev);
 774 error_free_dev:
 775         if (regdone)
 776                 iio_device_unregister(st->help.indio_dev);
 777         else
 778                 iio_free_device(st->help.indio_dev);
 779 error_free_tx:
 780         kfree(st->tx);
 781 error_free_rx:
 782         kfree(st->rx);
 783 error_free_st:
 784         kfree(st);
 785 error_ret:
 786         return ret;
 787 }
 788
 789 /* Power down the device */
 790 static int lis3l02dq_stop_device(struct iio_dev *indio_dev)
 791 {
 792         int ret;
 793         struct iio_sw_ring_helper_state *h
 794                 = iio_dev_get_devdata(indio_dev);
 795         struct lis3l02dq_state *st = lis3l02dq_h_to_s(h);
 796         u8 val = 0;
 797
 798         mutex_lock(&indio_dev->mlock);
 799         ret = lis3l02dq_spi_write_reg_8(indio_dev,
 800                                         LIS3L02DQ_REG_CTRL_1_ADDR,
 801                                         &val);
 802         if (ret) {
 803                 dev_err(&st->us->dev, "problem with turning device off: ctrl1");
 804                 goto err_ret;
 805         }
 806
 807         ret = lis3l02dq_spi_write_reg_8(indio_dev,
 808                                         LIS3L02DQ_REG_CTRL_2_ADDR,
 809                                         &val);
 810         if (ret)
 811                 dev_err(&st->us->dev, "problem with turning device off: ctrl2");
 812 err_ret:
 813         mutex_unlock(&indio_dev->mlock);
 814         return ret;
 815 }
 816
 817 /* fixme, confirm ordering in this function */
 818 static int lis3l02dq_remove(struct spi_device *spi)
 819 {
 820         int ret;
 821         struct lis3l02dq_state *st = spi_get_drvdata(spi);
 822         struct iio_dev *indio_dev = st->help.indio_dev;
 823         ret = lis3l02dq_disable_all_events(indio_dev);
 824         if (ret)
 825                 goto err_ret;
 826
 827         ret = lis3l02dq_stop_device(indio_dev);
 828         if (ret)
 829                 goto err_ret;
 830
 831         flush_scheduled_work();
 832
 833         lis3l02dq_remove_trigger(indio_dev);
 834         if (spi->irq && gpio_is_valid(irq_to_gpio(spi->irq)) > 0)
 835                 iio_unregister_interrupt_line(indio_dev, 0);
 836
 837         iio_ring_buffer_unregister(indio_dev->ring);
 838         lis3l02dq_unconfigure_ring(indio_dev);
 839         iio_device_unregister(indio_dev);
 840         kfree(st->tx);
 841         kfree(st->rx);
 842         kfree(st);
 843
 844         return 0;
 845
 846 err_ret:
 847         return ret;
 848 }
 849
 850 static struct spi_driver lis3l02dq_driver = {
 851         .driver = {
 852                 .name = "lis3l02dq",
 853                 .owner = THIS_MODULE,
 854         },
 855         .probe = lis3l02dq_probe,
 856         .remove = __devexit_p(lis3l02dq_remove),
 857 };
 858
 859 static __init int lis3l02dq_init(void)
 860 {
 861         return spi_register_driver(&lis3l02dq_driver);
 862 }
 863 module_init(lis3l02dq_init);
 864
 865 static __exit void lis3l02dq_exit(void)
 866 {
 867         spi_unregister_driver(&lis3l02dq_driver);
 868 }
 869 module_exit(lis3l02dq_exit);
 870
 871 MODULE_AUTHOR("Jonathan Cameron <jic23@cam.ac.uk>");
 872 MODULE_DESCRIPTION("ST LIS3L02DQ Accelerometer SPI driver");
 873 MODULE_LICENSE("GPL v2");