Pileus Git - ~andy/linux/blob - drivers/staging/iio/accel/lis3l02dq_core.c

   1 /*
   2  * lis3l02dq.c  support STMicroelectronics LISD02DQ
   3  *              3d 2g Linear Accelerometers via SPI
   4  *
   5  * Copyright (c) 2007 Jonathan Cameron <jic23@cam.ac.uk>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * Settings:
  12  * 16 bit left justified mode used.
  13  */
  14
  15 #include <linux/interrupt.h>
  16 #include <linux/irq.h>
  17 #include <linux/gpio.h>
  18 #include <linux/mutex.h>
  19 #include <linux/device.h>
  20 #include <linux/kernel.h>
  21 #include <linux/spi/spi.h>
  22 #include <linux/slab.h>
  23 #include <linux/sysfs.h>
  24
  25 #include "../iio.h"
  26 #include "../sysfs.h"
  27 #include "../ring_generic.h"
  28
  29 #include "accel.h"
  30
  31 #include "lis3l02dq.h"
  32
  33 /* At the moment the spi framework doesn't allow global setting of cs_change.
  34  * It's in the likely to be added comment at the top of spi.h.
  35  * This means that use cannot be made of spi_write etc.
  36  */
  37 /* direct copy of the irq_default_primary_handler */
  38 #ifndef CONFIG_IIO_RING_BUFFER
  39 static irqreturn_t lis3l02dq_noring(int irq, void *private)
  40 {
  41         return IRQ_WAKE_THREAD;
  42 }
  43 #endif
  44
  45 /**
  46  * lis3l02dq_spi_read_reg_8() - read single byte from a single register
  47  * @indio_dev: iio_dev for this actual device
  48  * @reg_address: the address of the register to be read
  49  * @val: pass back the resulting value
  50  **/
  51 int lis3l02dq_spi_read_reg_8(struct iio_dev *indio_dev,
  52                              u8 reg_address, u8 *val)
  53 {
  54         struct lis3l02dq_state *st = iio_priv(indio_dev);
  55         struct spi_message msg;
  56         int ret;
  57         struct spi_transfer xfer = {
  58                 .tx_buf = st->tx,
  59                 .rx_buf = st->rx,
  60                 .bits_per_word = 8,
  61                 .len = 2,
  62         };
  63
  64         mutex_lock(&st->buf_lock);
  65         st->tx[0] = LIS3L02DQ_READ_REG(reg_address);
  66         st->tx[1] = 0;
  67
  68         spi_message_init(&msg);
  69         spi_message_add_tail(&xfer, &msg);
  70         ret = spi_sync(st->us, &msg);
  71         *val = st->rx[1];
  72         mutex_unlock(&st->buf_lock);
  73
  74         return ret;
  75 }
  76
  77 /**
  78  * lis3l02dq_spi_write_reg_8() - write single byte to a register
  79  * @indio_dev: iio_dev for this device
  80  * @reg_address: the address of the register to be written
  81  * @val: the value to write
  82  **/
  83 int lis3l02dq_spi_write_reg_8(struct iio_dev *indio_dev,
  84                               u8 reg_address,
  85                               u8 val)
  86 {
  87         int ret;
  88         struct lis3l02dq_state *st = iio_priv(indio_dev);
  89
  90         mutex_lock(&st->buf_lock);
  91         st->tx[0] = LIS3L02DQ_WRITE_REG(reg_address);
  92         st->tx[1] = val;
  93         ret = spi_write(st->us, st->tx, 2);
  94         mutex_unlock(&st->buf_lock);
  95
  96         return ret;
  97 }
  98
  99 /**
 100  * lisl302dq_spi_write_reg_s16() - write 2 bytes to a pair of registers
 101  * @indio_dev: iio_dev for this device
 102  * @lower_reg_address: the address of the lower of the two registers.
 103  *               Second register is assumed to have address one greater.
 104  * @value: value to be written
 105  **/
 106 static int lis3l02dq_spi_write_reg_s16(struct iio_dev *indio_dev,
 107                                        u8 lower_reg_address,
 108                                        s16 value)
 109 {
 110         int ret;
 111         struct spi_message msg;
 112         struct lis3l02dq_state *st = iio_priv(indio_dev);
 113         struct spi_transfer xfers[] = { {
 114                         .tx_buf = st->tx,
 115                         .bits_per_word = 8,
 116                         .len = 2,
 117                         .cs_change = 1,
 118                 }, {
 119                         .tx_buf = st->tx + 2,
 120                         .bits_per_word = 8,
 121                         .len = 2,
 122                 },
 123         };
 124
 125         mutex_lock(&st->buf_lock);
 126         st->tx[0] = LIS3L02DQ_WRITE_REG(lower_reg_address);
 127         st->tx[1] = value & 0xFF;
 128         st->tx[2] = LIS3L02DQ_WRITE_REG(lower_reg_address + 1);
 129         st->tx[3] = (value >> 8) & 0xFF;
 130
 131         spi_message_init(&msg);
 132         spi_message_add_tail(&xfers[0], &msg);
 133         spi_message_add_tail(&xfers[1], &msg);
 134         ret = spi_sync(st->us, &msg);
 135         mutex_unlock(&st->buf_lock);
 136
 137         return ret;
 138 }
 139
 140 static int lis3l02dq_read_reg_s16(struct iio_dev *indio_dev,
 141                                   u8 lower_reg_address,
 142                                   int *val)
 143 {
 144         struct lis3l02dq_state *st = iio_priv(indio_dev);
 145
 146         struct spi_message msg;
 147         int ret;
 148         s16 tempval;
 149         struct spi_transfer xfers[] = { {
 150                         .tx_buf = st->tx,
 151                         .rx_buf = st->rx,
 152                         .bits_per_word = 8,
 153                         .len = 2,
 154                         .cs_change = 1,
 155                 }, {
 156                         .tx_buf = st->tx + 2,
 157                         .rx_buf = st->rx + 2,
 158                         .bits_per_word = 8,
 159                         .len = 2,
 160                 },
 161         };
 162
 163         mutex_lock(&st->buf_lock);
 164         st->tx[0] = LIS3L02DQ_READ_REG(lower_reg_address);
 165         st->tx[1] = 0;
 166         st->tx[2] = LIS3L02DQ_READ_REG(lower_reg_address + 1);
 167         st->tx[3] = 0;
 168
 169         spi_message_init(&msg);
 170         spi_message_add_tail(&xfers[0], &msg);
 171         spi_message_add_tail(&xfers[1], &msg);
 172         ret = spi_sync(st->us, &msg);
 173         if (ret) {
 174                 dev_err(&st->us->dev, "problem when reading 16 bit register");
 175                 goto error_ret;
 176         }
 177         tempval = (s16)(st->rx[1]) | ((s16)(st->rx[3]) << 8);
 178
 179         *val = tempval;
 180 error_ret:
 181         mutex_unlock(&st->buf_lock);
 182         return ret;
 183 }
 184
 185 enum lis3l02dq_rm_ind {
 186         LIS3L02DQ_ACCEL,
 187         LIS3L02DQ_GAIN,
 188         LIS3L02DQ_BIAS,
 189 };
 190
 191 static u8 lis3l02dq_axis_map[3][3] = {
 192         [LIS3L02DQ_ACCEL] = { LIS3L02DQ_REG_OUT_X_L_ADDR,
 193                               LIS3L02DQ_REG_OUT_Y_L_ADDR,
 194                               LIS3L02DQ_REG_OUT_Z_L_ADDR },
 195         [LIS3L02DQ_GAIN] = { LIS3L02DQ_REG_GAIN_X_ADDR,
 196                              LIS3L02DQ_REG_GAIN_Y_ADDR,
 197                              LIS3L02DQ_REG_GAIN_Z_ADDR },
 198         [LIS3L02DQ_BIAS] = { LIS3L02DQ_REG_OFFSET_X_ADDR,
 199                              LIS3L02DQ_REG_OFFSET_Y_ADDR,
 200                              LIS3L02DQ_REG_OFFSET_Z_ADDR }
 201 };
 202
 203 static int lis3l02dq_read_thresh(struct iio_dev *indio_dev,
 204                                  int e,
 205                                  int *val)
 206 {
 207         return lis3l02dq_read_reg_s16(indio_dev, LIS3L02DQ_REG_THS_L_ADDR, val);
 208 }
 209
 210 static int lis3l02dq_write_thresh(struct iio_dev *indio_dev,
 211                                   int event_code,
 212                                   int val)
 213 {
 214         u16 value = val;
 215         return lis3l02dq_spi_write_reg_s16(indio_dev,
 216                                            LIS3L02DQ_REG_THS_L_ADDR,
 217                                            value);
 218 }
 219
 220 static int lis3l02dq_write_raw(struct iio_dev *indio_dev,
 221                                struct iio_chan_spec const *chan,
 222                                int val,
 223                                int val2,
 224                                long mask)
 225 {
 226         int ret = -EINVAL, reg;
 227         u8 uval;
 228         s8 sval;
 229         switch (mask) {
 230         case (1 << IIO_CHAN_INFO_CALIBBIAS_SEPARATE):
 231                 if (val > 255 || val < -256)
 232                         return -EINVAL;
 233                 sval = val;
 234                 reg = lis3l02dq_axis_map[LIS3L02DQ_BIAS][chan->address];
 235                 ret = lis3l02dq_spi_write_reg_8(indio_dev, reg, sval);
 236                 break;
 237         case (1 << IIO_CHAN_INFO_CALIBSCALE_SEPARATE):
 238                 if (val & ~0xFF)
 239                         return -EINVAL;
 240                 uval = val;
 241                 reg = lis3l02dq_axis_map[LIS3L02DQ_GAIN][chan->address];
 242                 ret = lis3l02dq_spi_write_reg_8(indio_dev, reg, uval);
 243                 break;
 244         }
 245         return ret;
 246 }
 247
 248 static int lis3l02dq_read_raw(struct iio_dev *indio_dev,
 249                               struct iio_chan_spec const *chan,
 250                               int *val,
 251                               int *val2,
 252                               long mask)
 253 {
 254         u8 utemp;
 255         s8 stemp;
 256         ssize_t ret = 0;
 257         u8 reg;
 258
 259         switch (mask) {
 260         case 0:
 261                 /* Take the iio_dev status lock */
 262                 mutex_lock(&indio_dev->mlock);
 263                 if (indio_dev->currentmode == INDIO_RING_TRIGGERED)
 264                         ret = lis3l02dq_read_accel_from_ring(indio_dev->ring,
 265                                                              chan->scan_index,
 266                                                              val);
 267                 else {
 268                         reg = lis3l02dq_axis_map
 269                                 [LIS3L02DQ_ACCEL][chan->address];
 270                         ret = lis3l02dq_read_reg_s16(indio_dev, reg, val);
 271                 }
 272                 mutex_unlock(&indio_dev->mlock);
 273                 return IIO_VAL_INT;
 274         case (1 << IIO_CHAN_INFO_SCALE_SHARED):
 275                 *val = 0;
 276                 *val2 = 9580;
 277                 return IIO_VAL_INT_PLUS_MICRO;
 278         case (1 << IIO_CHAN_INFO_CALIBSCALE_SEPARATE):
 279                 reg = lis3l02dq_axis_map[LIS3L02DQ_GAIN][chan->address];
 280                 ret = lis3l02dq_spi_read_reg_8(indio_dev, reg, &utemp);
 281                 if (ret)
 282                         goto error_ret;
 283                 /* to match with what previous code does */
 284                 *val = utemp;
 285                 return IIO_VAL_INT;
 286
 287         case (1 << IIO_CHAN_INFO_CALIBBIAS_SEPARATE):
 288                 reg = lis3l02dq_axis_map[LIS3L02DQ_BIAS][chan->address];
 289                 ret = lis3l02dq_spi_read_reg_8(indio_dev, reg, (u8 *)&stemp);
 290                 /* to match with what previous code does */
 291                 *val = stemp;
 292                 return IIO_VAL_INT;
 293         }
 294 error_ret:
 295         return ret;
 296 }
 297
 298 static ssize_t lis3l02dq_read_frequency(struct device *dev,
 299                                         struct device_attribute *attr,
 300                                         char *buf)
 301 {
 302         struct iio_dev *indio_dev = dev_get_drvdata(dev);
 303         int ret, len = 0;
 304         s8 t;
 305         ret = lis3l02dq_spi_read_reg_8(indio_dev,
 306                                        LIS3L02DQ_REG_CTRL_1_ADDR,
 307                                        (u8 *)&t);
 308         if (ret)
 309                 return ret;
 310         t &= LIS3L02DQ_DEC_MASK;
 311         switch (t) {
 312         case LIS3L02DQ_REG_CTRL_1_DF_128:
 313                 len = sprintf(buf, "280\n");
 314                 break;
 315         case LIS3L02DQ_REG_CTRL_1_DF_64:
 316                 len = sprintf(buf, "560\n");
 317                 break;
 318         case LIS3L02DQ_REG_CTRL_1_DF_32:
 319                 len = sprintf(buf, "1120\n");
 320                 break;
 321         case LIS3L02DQ_REG_CTRL_1_DF_8:
 322                 len = sprintf(buf, "4480\n");
 323                 break;
 324         }
 325         return len;
 326 }
 327
 328 static ssize_t lis3l02dq_write_frequency(struct device *dev,
 329                                          struct device_attribute *attr,
 330                                          const char *buf,
 331                                          size_t len)
 332 {
 333         struct iio_dev *indio_dev = dev_get_drvdata(dev);
 334         long val;
 335         int ret;
 336         u8 t;
 337
 338         ret = strict_strtol(buf, 10, &val);
 339         if (ret)
 340                 return ret;
 341
 342         mutex_lock(&indio_dev->mlock);
 343         ret = lis3l02dq_spi_read_reg_8(indio_dev,
 344                                        LIS3L02DQ_REG_CTRL_1_ADDR,
 345                                        &t);
 346         if (ret)
 347                 goto error_ret_mutex;
 348         /* Wipe the bits clean */
 349         t &= ~LIS3L02DQ_DEC_MASK;
 350         switch (val) {
 351         case 280:
 352                 t |= LIS3L02DQ_REG_CTRL_1_DF_128;
 353                 break;
 354         case 560:
 355                 t |= LIS3L02DQ_REG_CTRL_1_DF_64;
 356                 break;
 357         case 1120:
 358                 t |= LIS3L02DQ_REG_CTRL_1_DF_32;
 359                 break;
 360         case 4480:
 361                 t |= LIS3L02DQ_REG_CTRL_1_DF_8;
 362                 break;
 363         default:
 364                 ret = -EINVAL;
 365                 goto error_ret_mutex;
 366         }
 367
 368         ret = lis3l02dq_spi_write_reg_8(indio_dev,
 369                                         LIS3L02DQ_REG_CTRL_1_ADDR,
 370                                         t);
 371
 372 error_ret_mutex:
 373         mutex_unlock(&indio_dev->mlock);
 374
 375         return ret ? ret : len;
 376 }
 377
 378 static int lis3l02dq_initial_setup(struct iio_dev *indio_dev)
 379 {
 380         struct lis3l02dq_state *st = iio_priv(indio_dev);
 381         int ret;
 382         u8 val, valtest;
 383
 384         st->us->mode = SPI_MODE_3;
 385
 386         spi_setup(st->us);
 387
 388         val = LIS3L02DQ_DEFAULT_CTRL1;
 389         /* Write suitable defaults to ctrl1 */
 390         ret = lis3l02dq_spi_write_reg_8(indio_dev,
 391                                         LIS3L02DQ_REG_CTRL_1_ADDR,
 392                                         val);
 393         if (ret) {
 394                 dev_err(&st->us->dev, "problem with setup control register 1");
 395                 goto err_ret;
 396         }
 397         /* Repeat as sometimes doesn't work first time?*/
 398         ret = lis3l02dq_spi_write_reg_8(indio_dev,
 399                                         LIS3L02DQ_REG_CTRL_1_ADDR,
 400                                         val);
 401         if (ret) {
 402                 dev_err(&st->us->dev, "problem with setup control register 1");
 403                 goto err_ret;
 404         }
 405
 406         /* Read back to check this has worked acts as loose test of correct
 407          * chip */
 408         ret = lis3l02dq_spi_read_reg_8(indio_dev,
 409                                        LIS3L02DQ_REG_CTRL_1_ADDR,
 410                                        &valtest);
 411         if (ret || (valtest != val)) {
 412                 dev_err(&indio_dev->dev,
 413                         "device not playing ball %d %d\n", valtest, val);
 414                 ret = -EINVAL;
 415                 goto err_ret;
 416         }
 417
 418         val = LIS3L02DQ_DEFAULT_CTRL2;
 419         ret = lis3l02dq_spi_write_reg_8(indio_dev,
 420                                         LIS3L02DQ_REG_CTRL_2_ADDR,
 421                                         val);
 422         if (ret) {
 423                 dev_err(&st->us->dev, "problem with setup control register 2");
 424                 goto err_ret;
 425         }
 426
 427         val = LIS3L02DQ_REG_WAKE_UP_CFG_LATCH_SRC;
 428         ret = lis3l02dq_spi_write_reg_8(indio_dev,
 429                                         LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
 430                                         val);
 431         if (ret)
 432                 dev_err(&st->us->dev, "problem with interrupt cfg register");
 433 err_ret:
 434
 435         return ret;
 436 }
 437
 438 static IIO_DEV_ATTR_SAMP_FREQ(S_IWUSR | S_IRUGO,
 439                               lis3l02dq_read_frequency,
 440                               lis3l02dq_write_frequency);
 441
 442 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("280 560 1120 4480");
 443
 444 static irqreturn_t lis3l02dq_event_handler(int irq, void *private)
 445 {
 446         struct iio_dev *indio_dev = private;
 447         u8 t;
 448
 449         s64 timestamp = iio_get_time_ns();
 450
 451         lis3l02dq_spi_read_reg_8(indio_dev,
 452                                  LIS3L02DQ_REG_WAKE_UP_SRC_ADDR,
 453                                  &t);
 454
 455         if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Z_HIGH)
 456                 iio_push_event(indio_dev, 0,
 457                                IIO_MOD_EVENT_CODE(IIO_EV_CLASS_ACCEL,
 458                                                   0,
 459                                                   IIO_EV_MOD_Z,
 460                                                   IIO_EV_TYPE_THRESH,
 461                                                   IIO_EV_DIR_RISING),
 462                                timestamp);
 463
 464         if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Z_LOW)
 465                 iio_push_event(indio_dev, 0,
 466                                IIO_MOD_EVENT_CODE(IIO_EV_CLASS_ACCEL,
 467                                                   0,
 468                                                   IIO_EV_MOD_Z,
 469                                                   IIO_EV_TYPE_THRESH,
 470                                                   IIO_EV_DIR_FALLING),
 471                                timestamp);
 472
 473         if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Y_HIGH)
 474                 iio_push_event(indio_dev, 0,
 475                                IIO_MOD_EVENT_CODE(IIO_EV_CLASS_ACCEL,
 476                                                   0,
 477                                                   IIO_EV_MOD_Y,
 478                                                   IIO_EV_TYPE_THRESH,
 479                                                   IIO_EV_DIR_RISING),
 480                                timestamp);
 481
 482         if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Y_LOW)
 483                 iio_push_event(indio_dev, 0,
 484                                IIO_MOD_EVENT_CODE(IIO_EV_CLASS_ACCEL,
 485                                                   0,
 486                                                   IIO_EV_MOD_Y,
 487                                                   IIO_EV_TYPE_THRESH,
 488                                                   IIO_EV_DIR_FALLING),
 489                                timestamp);
 490
 491         if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_X_HIGH)
 492                 iio_push_event(indio_dev, 0,
 493                                IIO_MOD_EVENT_CODE(IIO_EV_CLASS_ACCEL,
 494                                                   0,
 495                                                   IIO_EV_MOD_X,
 496                                                   IIO_EV_TYPE_THRESH,
 497                                                   IIO_EV_DIR_RISING),
 498                                timestamp);
 499
 500         if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_X_LOW)
 501                 iio_push_event(indio_dev, 0,
 502                                IIO_MOD_EVENT_CODE(IIO_EV_CLASS_ACCEL,
 503                                                   0,
 504                                                   IIO_EV_MOD_X,
 505                                                   IIO_EV_TYPE_THRESH,
 506                                                   IIO_EV_DIR_FALLING),
 507                                timestamp);
 508
 509         /* Ack and allow for new interrupts */
 510         lis3l02dq_spi_read_reg_8(indio_dev,
 511                                  LIS3L02DQ_REG_WAKE_UP_ACK_ADDR,
 512                                  &t);
 513
 514         return IRQ_HANDLED;
 515 }
 516
 517 #define LIS3L02DQ_INFO_MASK                             \
 518         ((1 << IIO_CHAN_INFO_SCALE_SHARED) |            \
 519          (1 << IIO_CHAN_INFO_CALIBSCALE_SEPARATE) |     \
 520          (1 << IIO_CHAN_INFO_CALIBBIAS_SEPARATE))
 521
 522 #define LIS3L02DQ_EVENT_MASK                                    \
 523         (IIO_EV_BIT(IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING) |    \
 524          IIO_EV_BIT(IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING))
 525
 526 static struct iio_chan_spec lis3l02dq_channels[] = {
 527         IIO_CHAN(IIO_ACCEL, 1, 0, 0, NULL, 0, IIO_MOD_X, LIS3L02DQ_INFO_MASK,
 528                  0, 0, IIO_ST('s', 12, 16, 0), LIS3L02DQ_EVENT_MASK),
 529         IIO_CHAN(IIO_ACCEL, 1, 0, 0, NULL, 0, IIO_MOD_Y, LIS3L02DQ_INFO_MASK,
 530                  1, 1, IIO_ST('s', 12, 16, 0), LIS3L02DQ_EVENT_MASK),
 531         IIO_CHAN(IIO_ACCEL, 1, 0, 0, NULL, 0, IIO_MOD_Z, LIS3L02DQ_INFO_MASK,
 532                  2, 2, IIO_ST('s', 12, 16, 0), LIS3L02DQ_EVENT_MASK),
 533         IIO_CHAN_SOFT_TIMESTAMP(3)
 534 };
 535
 536
 537 static ssize_t lis3l02dq_read_event_config(struct iio_dev *indio_dev,
 538                                            int event_code)
 539 {
 540
 541         u8 val;
 542         int ret;
 543         u8 mask = (1 << (IIO_EVENT_CODE_EXTRACT_MODIFIER(event_code)*2 +
 544                          (IIO_EVENT_CODE_EXTRACT_DIR(event_code) ==
 545                           IIO_EV_DIR_RISING)));
 546         ret = lis3l02dq_spi_read_reg_8(indio_dev,
 547                                        LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
 548                                        &val);
 549         if (ret < 0)
 550                 return ret;
 551
 552         return !!(val & mask);
 553 }
 554
 555 int lis3l02dq_disable_all_events(struct iio_dev *indio_dev)
 556 {
 557         int ret;
 558         u8 control, val;
 559
 560         ret = lis3l02dq_spi_read_reg_8(indio_dev,
 561                                        LIS3L02DQ_REG_CTRL_2_ADDR,
 562                                        &control);
 563
 564         control &= ~LIS3L02DQ_REG_CTRL_2_ENABLE_INTERRUPT;
 565         ret = lis3l02dq_spi_write_reg_8(indio_dev,
 566                                         LIS3L02DQ_REG_CTRL_2_ADDR,
 567                                         control);
 568         if (ret)
 569                 goto error_ret;
 570         /* Also for consistency clear the mask */
 571         ret = lis3l02dq_spi_read_reg_8(indio_dev,
 572                                        LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
 573                                        &val);
 574         if (ret)
 575                 goto error_ret;
 576         val &= ~0x3f;
 577
 578         ret = lis3l02dq_spi_write_reg_8(indio_dev,
 579                                         LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
 580                                         val);
 581         if (ret)
 582                 goto error_ret;
 583
 584         ret = control;
 585 error_ret:
 586         return ret;
 587 }
 588
 589 static int lis3l02dq_write_event_config(struct iio_dev *indio_dev,
 590                                         int event_code,
 591                                         int state)
 592 {
 593         int ret = 0;
 594         u8 val, control;
 595         u8 currentlyset;
 596         bool changed = false;
 597         u8 mask = (1 << (IIO_EVENT_CODE_EXTRACT_MODIFIER(event_code)*2 +
 598                          (IIO_EVENT_CODE_EXTRACT_DIR(event_code) ==
 599                           IIO_EV_DIR_RISING)));
 600
 601         mutex_lock(&indio_dev->mlock);
 602         /* read current control */
 603         ret = lis3l02dq_spi_read_reg_8(indio_dev,
 604                                        LIS3L02DQ_REG_CTRL_2_ADDR,
 605                                        &control);
 606         if (ret)
 607                 goto error_ret;
 608         ret = lis3l02dq_spi_read_reg_8(indio_dev,
 609                                        LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
 610                                        &val);
 611         if (ret < 0)
 612                 goto error_ret;
 613         currentlyset = val & mask;
 614
 615         if (!currentlyset && state) {
 616                 changed = true;
 617                 val |= mask;
 618         } else if (currentlyset && !state) {
 619                 changed = true;
 620                 val &= ~mask;
 621         }
 622
 623         if (changed) {
 624                 ret = lis3l02dq_spi_write_reg_8(indio_dev,
 625                                                 LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
 626                                                 val);
 627                 if (ret)
 628                         goto error_ret;
 629                 control = val & 0x3f ?
 630                         (control | LIS3L02DQ_REG_CTRL_2_ENABLE_INTERRUPT) :
 631                         (control & ~LIS3L02DQ_REG_CTRL_2_ENABLE_INTERRUPT);
 632                 ret = lis3l02dq_spi_write_reg_8(indio_dev,
 633                                                LIS3L02DQ_REG_CTRL_2_ADDR,
 634                                                control);
 635                 if (ret)
 636                         goto error_ret;
 637         }
 638
 639 error_ret:
 640         mutex_unlock(&indio_dev->mlock);
 641         return ret;
 642 }
 643
 644 static struct attribute *lis3l02dq_attributes[] = {
 645         &iio_dev_attr_sampling_frequency.dev_attr.attr,
 646         &iio_const_attr_sampling_frequency_available.dev_attr.attr,
 647         NULL
 648 };
 649
 650 static const struct attribute_group lis3l02dq_attribute_group = {
 651         .attrs = lis3l02dq_attributes,
 652 };
 653
 654 static const struct iio_info lis3l02dq_info = {
 655         .num_interrupt_lines = 1,
 656         .read_raw = &lis3l02dq_read_raw,
 657         .write_raw = &lis3l02dq_write_raw,
 658         .read_event_value = &lis3l02dq_read_thresh,
 659         .write_event_value = &lis3l02dq_write_thresh,
 660         .write_event_config = &lis3l02dq_write_event_config,
 661         .read_event_config = &lis3l02dq_read_event_config,
 662         .driver_module = THIS_MODULE,
 663         .attrs = &lis3l02dq_attribute_group,
 664 };
 665
 666 static int __devinit lis3l02dq_probe(struct spi_device *spi)
 667 {
 668         int ret, regdone = 0;
 669         struct lis3l02dq_state *st;
 670         struct iio_dev *indio_dev;
 671
 672         indio_dev = iio_allocate_device(sizeof *st);
 673         if (indio_dev == NULL) {
 674                 ret = -ENOMEM;
 675                 goto error_ret;
 676         }
 677         st = iio_priv(indio_dev);
 678         /* this is only used tor removal purposes */
 679         spi_set_drvdata(spi, indio_dev);
 680
 681         st->us = spi;
 682         mutex_init(&st->buf_lock);
 683         indio_dev->name = spi->dev.driver->name;
 684         indio_dev->dev.parent = &spi->dev;
 685         indio_dev->info = &lis3l02dq_info;
 686         indio_dev->channels = lis3l02dq_channels;
 687         indio_dev->num_channels = ARRAY_SIZE(lis3l02dq_channels);
 688
 689         indio_dev->modes = INDIO_DIRECT_MODE;
 690
 691         ret = lis3l02dq_configure_ring(indio_dev);
 692         if (ret)
 693                 goto error_free_dev;
 694
 695         ret = iio_device_register(indio_dev);
 696         if (ret)
 697                 goto error_unreg_ring_funcs;
 698         regdone = 1;
 699
 700         ret = iio_ring_buffer_register_ex(indio_dev->ring, 0,
 701                                           lis3l02dq_channels,
 702                                           ARRAY_SIZE(lis3l02dq_channels));
 703         if (ret) {
 704                 printk(KERN_ERR "failed to initialize the ring\n");
 705                 goto error_unreg_ring_funcs;
 706         }
 707
 708         if (spi->irq && gpio_is_valid(irq_to_gpio(spi->irq)) > 0) {
 709                 ret = request_threaded_irq(st->us->irq,
 710                                            &lis3l02dq_th,
 711                                            &lis3l02dq_event_handler,
 712                                            IRQF_TRIGGER_RISING,
 713                                            "lis3l02dq",
 714                                            indio_dev);
 715                 if (ret)
 716                         goto error_uninitialize_ring;
 717
 718                 ret = lis3l02dq_probe_trigger(indio_dev);
 719                 if (ret)
 720                         goto error_free_interrupt;
 721         }
 722
 723         /* Get the device into a sane initial state */
 724         ret = lis3l02dq_initial_setup(indio_dev);
 725         if (ret)
 726                 goto error_remove_trigger;
 727         return 0;
 728
 729 error_remove_trigger:
 730         if (indio_dev->modes & INDIO_RING_TRIGGERED)
 731                 lis3l02dq_remove_trigger(indio_dev);
 732 error_free_interrupt:
 733         if (spi->irq && gpio_is_valid(irq_to_gpio(spi->irq)) > 0)
 734                 free_irq(st->us->irq, indio_dev);
 735 error_uninitialize_ring:
 736         iio_ring_buffer_unregister(indio_dev->ring);
 737 error_unreg_ring_funcs:
 738         lis3l02dq_unconfigure_ring(indio_dev);
 739 error_free_dev:
 740         if (regdone)
 741                 iio_device_unregister(indio_dev);
 742         else
 743                 iio_free_device(indio_dev);
 744 error_ret:
 745         return ret;
 746 }
 747
 748 /* Power down the device */
 749 static int lis3l02dq_stop_device(struct iio_dev *indio_dev)
 750 {
 751         int ret;
 752         struct lis3l02dq_state *st = iio_priv(indio_dev);
 753         u8 val = 0;
 754
 755         mutex_lock(&indio_dev->mlock);
 756         ret = lis3l02dq_spi_write_reg_8(indio_dev,
 757                                         LIS3L02DQ_REG_CTRL_1_ADDR,
 758                                         val);
 759         if (ret) {
 760                 dev_err(&st->us->dev, "problem with turning device off: ctrl1");
 761                 goto err_ret;
 762         }
 763
 764         ret = lis3l02dq_spi_write_reg_8(indio_dev,
 765                                         LIS3L02DQ_REG_CTRL_2_ADDR,
 766                                         val);
 767         if (ret)
 768                 dev_err(&st->us->dev, "problem with turning device off: ctrl2");
 769 err_ret:
 770         mutex_unlock(&indio_dev->mlock);
 771         return ret;
 772 }
 773
 774 /* fixme, confirm ordering in this function */
 775 static int lis3l02dq_remove(struct spi_device *spi)
 776 {
 777         int ret;
 778         struct iio_dev *indio_dev = spi_get_drvdata(spi);
 779         struct lis3l02dq_state *st = iio_priv(indio_dev);
 780
 781         ret = lis3l02dq_disable_all_events(indio_dev);
 782         if (ret)
 783                 goto err_ret;
 784
 785         ret = lis3l02dq_stop_device(indio_dev);
 786         if (ret)
 787                 goto err_ret;
 788
 789         if (spi->irq && gpio_is_valid(irq_to_gpio(spi->irq)) > 0)
 790                 free_irq(st->us->irq, indio_dev);
 791
 792         lis3l02dq_remove_trigger(indio_dev);
 793         iio_ring_buffer_unregister(indio_dev->ring);
 794         lis3l02dq_unconfigure_ring(indio_dev);
 795         iio_device_unregister(indio_dev);
 796
 797         return 0;
 798
 799 err_ret:
 800         return ret;
 801 }
 802
 803 static struct spi_driver lis3l02dq_driver = {
 804         .driver = {
 805                 .name = "lis3l02dq",
 806                 .owner = THIS_MODULE,
 807         },
 808         .probe = lis3l02dq_probe,
 809         .remove = __devexit_p(lis3l02dq_remove),
 810 };
 811
 812 static __init int lis3l02dq_init(void)
 813 {
 814         return spi_register_driver(&lis3l02dq_driver);
 815 }
 816 module_init(lis3l02dq_init);
 817
 818 static __exit void lis3l02dq_exit(void)
 819 {
 820         spi_unregister_driver(&lis3l02dq_driver);
 821 }
 822 module_exit(lis3l02dq_exit);
 823
 824 MODULE_AUTHOR("Jonathan Cameron <jic23@cam.ac.uk>");
 825 MODULE_DESCRIPTION("ST LIS3L02DQ Accelerometer SPI driver");
 826 MODULE_LICENSE("GPL v2");