Pileus Git - ~andy/linux/blob - drivers/staging/goldfish/goldfish_nand_reg.h

   1 /* drivers/mtd/devices/goldfish_nand_reg.h
   2 **
   3 ** Copyright (C) 2007 Google, Inc.
   4 **
   5 ** This software is licensed under the terms of the GNU General Public
   6 ** License version 2, as published by the Free Software Foundation, and
   7 ** may be copied, distributed, and modified under those terms.
   8 **
   9 ** This program is distributed in the hope that it will be useful,
  10 ** but WITHOUT ANY WARRANTY; without even the implied warranty of
  11 ** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12 ** GNU General Public License for more details.
  13 **
  14 */
  15
  16 #ifndef GOLDFISH_NAND_REG_H
  17 #define GOLDFISH_NAND_REG_H
  18
  19 enum nand_cmd {
  20         NAND_CMD_GET_DEV_NAME,  /* Write device name for NAND_DEV to NAND_DATA (vaddr) */
  21         NAND_CMD_READ,
  22         NAND_CMD_WRITE,
  23         NAND_CMD_ERASE,
  24         NAND_CMD_BLOCK_BAD_GET, /* NAND_RESULT is 1 if block is bad, 0 if it is not */
  25         NAND_CMD_BLOCK_BAD_SET,
  26         NAND_CMD_READ_WITH_PARAMS,
  27         NAND_CMD_WRITE_WITH_PARAMS,
  28         NAND_CMD_ERASE_WITH_PARAMS
  29 };
  30
  31 enum nand_dev_flags {
  32         NAND_DEV_FLAG_READ_ONLY = 0x00000001,
  33         NAND_DEV_FLAG_CMD_PARAMS_CAP = 0x00000002,
  34 };
  35
  36 #define NAND_VERSION_CURRENT (1)
  37
  38 enum nand_reg {
  39         /* Global */
  40         NAND_VERSION        = 0x000,
  41         NAND_NUM_DEV        = 0x004,
  42         NAND_DEV            = 0x008,
  43
  44         /* Dev info */
  45         NAND_DEV_FLAGS      = 0x010,
  46         NAND_DEV_NAME_LEN   = 0x014,
  47         NAND_DEV_PAGE_SIZE  = 0x018,
  48         NAND_DEV_EXTRA_SIZE = 0x01c,
  49         NAND_DEV_ERASE_SIZE = 0x020,
  50         NAND_DEV_SIZE_LOW   = 0x028,
  51         NAND_DEV_SIZE_HIGH  = 0x02c,
  52
  53         /* Command */
  54         NAND_RESULT         = 0x040,
  55         NAND_COMMAND        = 0x044,
  56         NAND_DATA           = 0x048,
  57         NAND_TRANSFER_SIZE  = 0x04c,
  58         NAND_ADDR_LOW       = 0x050,
  59         NAND_ADDR_HIGH      = 0x054,
  60         NAND_CMD_PARAMS_ADDR_LOW = 0x058,
  61         NAND_CMD_PARAMS_ADDR_HIGH = 0x05c,
  62 };
  63
  64 struct cmd_params {
  65         uint32_t dev;
  66         uint32_t addr_low;
  67         uint32_t addr_high;
  68         uint32_t transfer_size;
  69         uint32_t data;
  70         uint32_t result;
  71 };
  72 #endif