Pileus Git - ~andy/linux/blob - drivers/staging/gma500/psb_drv.c

   1 /**************************************************************************
   2  * Copyright (c) 2007-2011, Intel Corporation.
   3  * All Rights Reserved.
   4  * Copyright (c) 2008, Tungsten Graphics, Inc. Cedar Park, TX., USA.
   5  * All Rights Reserved.
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms and conditions of the GNU General Public License,
   9  * version 2, as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program; if not, write to the Free Software Foundation, Inc.,
  18  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  **************************************************************************/
  21
  22 #include <drm/drmP.h>
  23 #include <drm/drm.h>
  24 #include "psb_drm.h"
  25 #include "psb_drv.h"
  26 #include "psb_fb.h"
  27 #include "psb_reg.h"
  28 #include "psb_intel_reg.h"
  29 #include "psb_intel_bios.h"
  30 #include "mid_bios.h"
  31 #include "mdfld_dsi_dbi.h"
  32 #include <drm/drm_pciids.h>
  33 #include "psb_powermgmt.h"
  34 #include <linux/cpu.h>
  35 #include <linux/notifier.h>
  36 #include <linux/spinlock.h>
  37 #include <linux/pm_runtime.h>
  38 #include <acpi/video.h>
  39
  40 static int drm_psb_trap_pagefaults;
  41
  42 int drm_psb_no_fb;
  43
  44 static int psb_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
  45
  46 MODULE_PARM_DESC(no_fb, "Disable FBdev");
  47 MODULE_PARM_DESC(trap_pagefaults, "Error and reset on MMU pagefaults");
  48 module_param_named(no_fb, drm_psb_no_fb, int, 0600);
  49 module_param_named(trap_pagefaults, drm_psb_trap_pagefaults, int, 0600);
  50
  51
  52 static DEFINE_PCI_DEVICE_TABLE(pciidlist) = {
  53         { 0x8086, 0x8108, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &psb_chip_ops },
  54         { 0x8086, 0x8109, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &psb_chip_ops },
  55         { 0x8086, 0x4100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mrst_chip_ops},
  56         { 0x8086, 0x4101, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mrst_chip_ops},
  57         { 0x8086, 0x4102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mrst_chip_ops},
  58         { 0x8086, 0x4103, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mrst_chip_ops},
  59         { 0x8086, 0x4104, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mrst_chip_ops},
  60         { 0x8086, 0x4105, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mrst_chip_ops},
  61         { 0x8086, 0x4106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mrst_chip_ops},
  62         { 0x8086, 0x4107, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mrst_chip_ops},
  63         { 0x8086, 0x0130, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mdfld_chip_ops},
  64         { 0x8086, 0x0131, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mdfld_chip_ops},
  65         { 0x8086, 0x0132, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mdfld_chip_ops},
  66         { 0x8086, 0x0133, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mdfld_chip_ops},
  67         { 0x8086, 0x0134, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mdfld_chip_ops},
  68         { 0x8086, 0x0135, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mdfld_chip_ops},
  69         { 0x8086, 0x0136, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mdfld_chip_ops},
  70         { 0x8086, 0x0137, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mdfld_chip_ops},
  71         { 0x8086, 0x0be0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops},
  72         { 0x8086, 0x0be1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops},
  73         { 0x8086, 0x0be2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops},
  74         { 0x8086, 0x0be3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops},
  75         { 0x8086, 0x0be4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops},
  76         { 0x8086, 0x0be5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops},
  77         { 0x8086, 0x0be6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops},
  78         { 0x8086, 0x0be7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops},
  79         { 0, 0, 0}
  80 };
  81 MODULE_DEVICE_TABLE(pci, pciidlist);
  82
  83 /*
  84  * Standard IOCTLs.
  85  */
  86
  87 #define DRM_IOCTL_PSB_SIZES     \
  88                 DRM_IOR(DRM_PSB_SIZES + DRM_COMMAND_BASE, \
  89                         struct drm_psb_sizes_arg)
  90 #define DRM_IOCTL_PSB_FUSE_REG  \
  91                 DRM_IOWR(DRM_PSB_FUSE_REG + DRM_COMMAND_BASE, uint32_t)
  92 #define DRM_IOCTL_PSB_DC_STATE  \
  93                 DRM_IOW(DRM_PSB_DC_STATE + DRM_COMMAND_BASE, \
  94                         struct drm_psb_dc_state_arg)
  95 #define DRM_IOCTL_PSB_ADB       \
  96                 DRM_IOWR(DRM_PSB_ADB + DRM_COMMAND_BASE, uint32_t)
  97 #define DRM_IOCTL_PSB_MODE_OPERATION    \
  98                 DRM_IOWR(DRM_PSB_MODE_OPERATION + DRM_COMMAND_BASE, \
  99                          struct drm_psb_mode_operation_arg)
 100 #define DRM_IOCTL_PSB_STOLEN_MEMORY     \
 101                 DRM_IOWR(DRM_PSB_STOLEN_MEMORY + DRM_COMMAND_BASE, \
 102                          struct drm_psb_stolen_memory_arg)
 103 #define DRM_IOCTL_PSB_REGISTER_RW       \
 104                 DRM_IOWR(DRM_PSB_REGISTER_RW + DRM_COMMAND_BASE, \
 105                          struct drm_psb_register_rw_arg)
 106 #define DRM_IOCTL_PSB_DPST      \
 107                 DRM_IOWR(DRM_PSB_DPST + DRM_COMMAND_BASE, \
 108                          uint32_t)
 109 #define DRM_IOCTL_PSB_GAMMA     \
 110                 DRM_IOWR(DRM_PSB_GAMMA + DRM_COMMAND_BASE, \
 111                          struct drm_psb_dpst_lut_arg)
 112 #define DRM_IOCTL_PSB_DPST_BL   \
 113                 DRM_IOWR(DRM_PSB_DPST_BL + DRM_COMMAND_BASE, \
 114                          uint32_t)
 115 #define DRM_IOCTL_PSB_GET_PIPE_FROM_CRTC_ID     \
 116                 DRM_IOWR(DRM_PSB_GET_PIPE_FROM_CRTC_ID + DRM_COMMAND_BASE, \
 117                          struct drm_psb_get_pipe_from_crtc_id_arg)
 118
 119 static int psb_sizes_ioctl(struct drm_device *dev, void *data,
 120                            struct drm_file *file_priv);
 121 static int psb_dc_state_ioctl(struct drm_device *dev, void * data,
 122                               struct drm_file *file_priv);
 123 static int psb_adb_ioctl(struct drm_device *dev, void *data,
 124                          struct drm_file *file_priv);
 125 static int psb_mode_operation_ioctl(struct drm_device *dev, void *data,
 126                                     struct drm_file *file_priv);
 127 static int psb_stolen_memory_ioctl(struct drm_device *dev, void *data,
 128                                    struct drm_file *file_priv);
 129 static int psb_register_rw_ioctl(struct drm_device *dev, void *data,
 130                                  struct drm_file *file_priv);
 131 static int psb_dpst_ioctl(struct drm_device *dev, void *data,
 132                           struct drm_file *file_priv);
 133 static int psb_gamma_ioctl(struct drm_device *dev, void *data,
 134                            struct drm_file *file_priv);
 135 static int psb_dpst_bl_ioctl(struct drm_device *dev, void *data,
 136                              struct drm_file *file_priv);
 137
 138 #define PSB_IOCTL_DEF(ioctl, func, flags) \
 139         [DRM_IOCTL_NR(ioctl) - DRM_COMMAND_BASE] = {ioctl, flags, func}
 140
 141 static struct drm_ioctl_desc psb_ioctls[] = {
 142         PSB_IOCTL_DEF(DRM_IOCTL_PSB_SIZES, psb_sizes_ioctl, DRM_AUTH),
 143         PSB_IOCTL_DEF(DRM_IOCTL_PSB_DC_STATE, psb_dc_state_ioctl, DRM_AUTH),
 144         PSB_IOCTL_DEF(DRM_IOCTL_PSB_ADB, psb_adb_ioctl, DRM_AUTH),
 145         PSB_IOCTL_DEF(DRM_IOCTL_PSB_MODE_OPERATION, psb_mode_operation_ioctl,
 146                       DRM_AUTH),
 147         PSB_IOCTL_DEF(DRM_IOCTL_PSB_STOLEN_MEMORY, psb_stolen_memory_ioctl,
 148                       DRM_AUTH),
 149         PSB_IOCTL_DEF(DRM_IOCTL_PSB_REGISTER_RW, psb_register_rw_ioctl,
 150                       DRM_AUTH),
 151         PSB_IOCTL_DEF(DRM_IOCTL_PSB_DPST, psb_dpst_ioctl, DRM_AUTH),
 152         PSB_IOCTL_DEF(DRM_IOCTL_PSB_GAMMA, psb_gamma_ioctl, DRM_AUTH),
 153         PSB_IOCTL_DEF(DRM_IOCTL_PSB_DPST_BL, psb_dpst_bl_ioctl, DRM_AUTH),
 154         PSB_IOCTL_DEF(DRM_IOCTL_PSB_GET_PIPE_FROM_CRTC_ID,
 155                                         psb_intel_get_pipe_from_crtc_id, 0),
 156
 157 };
 158
 159 static void psb_lastclose(struct drm_device *dev)
 160 {
 161         return;
 162 }
 163
 164 static void psb_do_takedown(struct drm_device *dev)
 165 {
 166         /* FIXME: do we need to clean up the gtt here ? */
 167 }
 168
 169 static int psb_do_init(struct drm_device *dev)
 170 {
 171         struct drm_psb_private *dev_priv =
 172             (struct drm_psb_private *) dev->dev_private;
 173         struct psb_gtt *pg = dev_priv->pg;
 174
 175         uint32_t stolen_gtt;
 176
 177         int ret = -ENOMEM;
 178
 179         if (pg->mmu_gatt_start & 0x0FFFFFFF) {
 180                 dev_err(dev->dev, "Gatt must be 256M aligned. This is a bug.\n");
 181                 ret = -EINVAL;
 182                 goto out_err;
 183         }
 184
 185
 186         stolen_gtt = (pg->stolen_size >> PAGE_SHIFT) * 4;
 187         stolen_gtt = (stolen_gtt + PAGE_SIZE - 1) >> PAGE_SHIFT;
 188         stolen_gtt =
 189             (stolen_gtt < pg->gtt_pages) ? stolen_gtt : pg->gtt_pages;
 190
 191         dev_priv->gatt_free_offset = pg->mmu_gatt_start +
 192             (stolen_gtt << PAGE_SHIFT) * 1024;
 193
 194         if (1 || drm_debug) {
 195                 uint32_t core_id = PSB_RSGX32(PSB_CR_CORE_ID);
 196                 uint32_t core_rev = PSB_RSGX32(PSB_CR_CORE_REVISION);
 197                 DRM_INFO("SGX core id = 0x%08x\n", core_id);
 198                 DRM_INFO("SGX core rev major = 0x%02x, minor = 0x%02x\n",
 199                          (core_rev & _PSB_CC_REVISION_MAJOR_MASK) >>
 200                          _PSB_CC_REVISION_MAJOR_SHIFT,
 201                          (core_rev & _PSB_CC_REVISION_MINOR_MASK) >>
 202                          _PSB_CC_REVISION_MINOR_SHIFT);
 203                 DRM_INFO
 204                     ("SGX core rev maintenance = 0x%02x, designer = 0x%02x\n",
 205                      (core_rev & _PSB_CC_REVISION_MAINTENANCE_MASK) >>
 206                      _PSB_CC_REVISION_MAINTENANCE_SHIFT,
 207                      (core_rev & _PSB_CC_REVISION_DESIGNER_MASK) >>
 208                      _PSB_CC_REVISION_DESIGNER_SHIFT);
 209         }
 210
 211
 212         spin_lock_init(&dev_priv->irqmask_lock);
 213
 214         PSB_WSGX32(0x00000000, PSB_CR_BIF_BANK0);
 215         PSB_WSGX32(0x00000000, PSB_CR_BIF_BANK1);
 216         PSB_RSGX32(PSB_CR_BIF_BANK1);
 217         PSB_WSGX32(PSB_RSGX32(PSB_CR_BIF_CTRL) | _PSB_MMU_ER_MASK,
 218                                                         PSB_CR_BIF_CTRL);
 219         psb_spank(dev_priv);
 220
 221         /* mmu_gatt ?? */
 222         PSB_WSGX32(pg->gatt_start, PSB_CR_BIF_TWOD_REQ_BASE);
 223         return 0;
 224 out_err:
 225         psb_do_takedown(dev);
 226         return ret;
 227 }
 228
 229 static int psb_driver_unload(struct drm_device *dev)
 230 {
 231         struct drm_psb_private *dev_priv = dev->dev_private;
 232
 233         /* Kill vblank etc here */
 234
 235         gma_backlight_exit(dev);
 236
 237         if (drm_psb_no_fb == 0)
 238                 psb_modeset_cleanup(dev);
 239
 240         if (dev_priv) {
 241                 psb_lid_timer_takedown(dev_priv);
 242
 243                 psb_do_takedown(dev);
 244
 245
 246                 if (dev_priv->pf_pd) {
 247                         psb_mmu_free_pagedir(dev_priv->pf_pd);
 248                         dev_priv->pf_pd = NULL;
 249                 }
 250                 if (dev_priv->mmu) {
 251                         struct psb_gtt *pg = dev_priv->pg;
 252
 253                         down_read(&pg->sem);
 254                         psb_mmu_remove_pfn_sequence(
 255                                 psb_mmu_get_default_pd
 256                                 (dev_priv->mmu),
 257                                 pg->mmu_gatt_start,
 258                                 dev_priv->vram_stolen_size >> PAGE_SHIFT);
 259                         up_read(&pg->sem);
 260                         psb_mmu_driver_takedown(dev_priv->mmu);
 261                         dev_priv->mmu = NULL;
 262                 }
 263                 psb_gtt_takedown(dev);
 264                 if (dev_priv->scratch_page) {
 265                         __free_page(dev_priv->scratch_page);
 266                         dev_priv->scratch_page = NULL;
 267                 }
 268                 if (dev_priv->vdc_reg) {
 269                         iounmap(dev_priv->vdc_reg);
 270                         dev_priv->vdc_reg = NULL;
 271                 }
 272                 if (dev_priv->sgx_reg) {
 273                         iounmap(dev_priv->sgx_reg);
 274                         dev_priv->sgx_reg = NULL;
 275                 }
 276
 277                 kfree(dev_priv);
 278                 dev->dev_private = NULL;
 279
 280                 /*destroy VBT data*/
 281                 psb_intel_destroy_bios(dev);
 282         }
 283
 284         gma_power_uninit(dev);
 285
 286         return 0;
 287 }
 288
 289
 290 static int psb_driver_load(struct drm_device *dev, unsigned long chipset)
 291 {
 292         struct drm_psb_private *dev_priv;
 293         unsigned long resource_start;
 294         struct psb_gtt *pg;
 295         unsigned long irqflags;
 296         int ret = -ENOMEM;
 297         uint32_t tt_pages;
 298         struct drm_connector *connector;
 299         struct psb_intel_output *psb_intel_output;
 300
 301         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
 302         if (dev_priv == NULL)
 303                 return -ENOMEM;
 304
 305         dev_priv->ops = (struct psb_ops *)chipset;
 306         dev_priv->dev = dev;
 307         dev->dev_private = (void *) dev_priv;
 308
 309         dev_priv->num_pipe = dev_priv->ops->pipes;
 310
 311         resource_start = pci_resource_start(dev->pdev, PSB_MMIO_RESOURCE);
 312
 313         dev_priv->vdc_reg =
 314             ioremap(resource_start + PSB_VDC_OFFSET, PSB_VDC_SIZE);
 315         if (!dev_priv->vdc_reg)
 316                 goto out_err;
 317
 318         dev_priv->sgx_reg = ioremap(resource_start + dev_priv->ops->sgx_offset,
 319                                                         PSB_SGX_SIZE);
 320         if (!dev_priv->sgx_reg)
 321                 goto out_err;
 322
 323         ret = dev_priv->ops->chip_setup(dev);
 324         if (ret)
 325                 goto out_err;
 326
 327         /* Init OSPM support */
 328         gma_power_init(dev);
 329
 330         ret = -ENOMEM;
 331
 332         dev_priv->scratch_page = alloc_page(GFP_DMA32 | __GFP_ZERO);
 333         if (!dev_priv->scratch_page)
 334                 goto out_err;
 335
 336         set_pages_uc(dev_priv->scratch_page, 1);
 337
 338         ret = psb_gtt_init(dev, 0);
 339         if (ret)
 340                 goto out_err;
 341
 342         dev_priv->mmu = psb_mmu_driver_init((void *)0,
 343                                         drm_psb_trap_pagefaults, 0,
 344                                         dev_priv);
 345         if (!dev_priv->mmu)
 346                 goto out_err;
 347
 348         pg = dev_priv->pg;
 349
 350         tt_pages = (pg->gatt_pages < PSB_TT_PRIV0_PLIMIT) ?
 351                 (pg->gatt_pages) : PSB_TT_PRIV0_PLIMIT;
 352
 353
 354         dev_priv->pf_pd = psb_mmu_alloc_pd(dev_priv->mmu, 1, 0);
 355         if (!dev_priv->pf_pd)
 356                 goto out_err;
 357
 358         psb_mmu_set_pd_context(psb_mmu_get_default_pd(dev_priv->mmu), 0);
 359         psb_mmu_set_pd_context(dev_priv->pf_pd, 1);
 360
 361         ret = psb_do_init(dev);
 362         if (ret)
 363                 return ret;
 364
 365         PSB_WSGX32(0x20000000, PSB_CR_PDS_EXEC_BASE);
 366         PSB_WSGX32(0x30000000, PSB_CR_BIF_3D_REQ_BASE);
 367
 368 /*      igd_opregion_init(&dev_priv->opregion_dev); */
 369         acpi_video_register();
 370         if (dev_priv->lid_state)
 371                 psb_lid_timer_init(dev_priv);
 372
 373         ret = drm_vblank_init(dev, dev_priv->num_pipe);
 374         if (ret)
 375                 goto out_err;
 376
 377         /*
 378          * Install interrupt handlers prior to powering off SGX or else we will
 379          * crash.
 380          */
 381         dev_priv->vdc_irq_mask = 0;
 382         dev_priv->pipestat[0] = 0;
 383         dev_priv->pipestat[1] = 0;
 384         dev_priv->pipestat[2] = 0;
 385         spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
 386         PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
 387         PSB_WVDC32(0x00000000, PSB_INT_ENABLE_R);
 388         PSB_WVDC32(0xFFFFFFFF, PSB_INT_MASK_R);
 389         spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
 390         if (drm_core_check_feature(dev, DRIVER_MODESET))
 391                 drm_irq_install(dev);
 392
 393         dev->vblank_disable_allowed = 1;
 394
 395         dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
 396
 397         dev->driver->get_vblank_counter = psb_get_vblank_counter;
 398
 399         /* FIXME: this is not the right place for this stuff ! */
 400         if (IS_MFLD(dev)) {
 401 #ifdef CONFIG_MDFLD_DSI_DPU
 402                 /*init dpu info*/
 403                 mdfld_dbi_dpu_init(dev);
 404 #else
 405                 mdfld_dbi_dsr_init(dev);
 406 #endif /*CONFIG_MDFLD_DSI_DPU*/
 407                 /* INIT_WORK(&dev_priv->te_work, mdfld_te_handler_work);*/
 408         }
 409
 410         if (drm_psb_no_fb == 0) {
 411                 psb_modeset_init(dev);
 412                 psb_fbdev_init(dev);
 413                 drm_kms_helper_poll_init(dev);
 414         }
 415
 416         /* Only add backlight support if we have LVDS output */
 417         list_for_each_entry(connector, &dev->mode_config.connector_list,
 418                             head) {
 419                 psb_intel_output = to_psb_intel_output(connector);
 420
 421                 switch (psb_intel_output->type) {
 422                 case INTEL_OUTPUT_LVDS:
 423                         ret = gma_backlight_init(dev);
 424                         break;
 425                 }
 426         }
 427
 428         if (ret)
 429                 return ret;
 430 #if 0
 431         /*enable runtime pm at last*/
 432         pm_runtime_enable(&dev->pdev->dev);
 433         pm_runtime_set_active(&dev->pdev->dev);
 434 #endif
 435         /*Intel drm driver load is done, continue doing pvr load*/
 436         return 0;
 437 out_err:
 438         psb_driver_unload(dev);
 439         return ret;
 440 }
 441
 442 int psb_driver_device_is_agp(struct drm_device *dev)
 443 {
 444         return 0;
 445 }
 446
 447
 448 static int psb_sizes_ioctl(struct drm_device *dev, void *data,
 449                            struct drm_file *file_priv)
 450 {
 451         struct drm_psb_private *dev_priv = psb_priv(dev);
 452         struct drm_psb_sizes_arg *arg =
 453                 (struct drm_psb_sizes_arg *) data;
 454
 455         *arg = dev_priv->sizes;
 456         return 0;
 457 }
 458
 459 static int psb_dc_state_ioctl(struct drm_device *dev, void * data,
 460                                 struct drm_file *file_priv)
 461 {
 462         uint32_t flags;
 463         uint32_t obj_id;
 464         struct drm_mode_object *obj;
 465         struct drm_connector *connector;
 466         struct drm_crtc *crtc;
 467         struct drm_psb_dc_state_arg *arg =
 468                 (struct drm_psb_dc_state_arg *)data;
 469
 470
 471         /* Double check MRST case */
 472         if (IS_MRST(dev) || IS_MFLD(dev))
 473                 return -EOPNOTSUPP;
 474
 475         flags = arg->flags;
 476         obj_id = arg->obj_id;
 477
 478         if (flags & PSB_DC_CRTC_MASK) {
 479                 obj = drm_mode_object_find(dev, obj_id,
 480                                 DRM_MODE_OBJECT_CRTC);
 481                 if (!obj) {
 482                         dev_dbg(dev->dev, "Invalid CRTC object.\n");
 483                         return -EINVAL;
 484                 }
 485
 486                 crtc = obj_to_crtc(obj);
 487
 488                 mutex_lock(&dev->mode_config.mutex);
 489                 if (drm_helper_crtc_in_use(crtc)) {
 490                         if (flags & PSB_DC_CRTC_SAVE)
 491                                 crtc->funcs->save(crtc);
 492                         else
 493                                 crtc->funcs->restore(crtc);
 494                 }
 495                 mutex_unlock(&dev->mode_config.mutex);
 496
 497                 return 0;
 498         } else if (flags & PSB_DC_OUTPUT_MASK) {
 499                 obj = drm_mode_object_find(dev, obj_id,
 500                                 DRM_MODE_OBJECT_CONNECTOR);
 501                 if (!obj) {
 502                         dev_dbg(dev->dev, "Invalid connector id.\n");
 503                         return -EINVAL;
 504                 }
 505
 506                 connector = obj_to_connector(obj);
 507                 if (flags & PSB_DC_OUTPUT_SAVE)
 508                         connector->funcs->save(connector);
 509                 else
 510                         connector->funcs->restore(connector);
 511
 512                 return 0;
 513         }
 514         return -EINVAL;
 515 }
 516
 517 static int psb_dpst_bl_ioctl(struct drm_device *dev, void *data,
 518                        struct drm_file *file_priv)
 519 {
 520         struct drm_psb_private *dev_priv = psb_priv(dev);
 521         uint32_t *arg = data;
 522         struct backlight_device *bd = dev_priv->backlight_device;
 523         dev_priv->blc_adj2 = *arg;
 524
 525 #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
 526         if (bd) {
 527                 bd->props.brightness = bd->ops->get_brightness(bd);
 528                 backlight_update_status(bd);
 529         }
 530 #endif
 531         return 0;
 532 }
 533
 534 static int psb_adb_ioctl(struct drm_device *dev, void *data,
 535                         struct drm_file *file_priv)
 536 {
 537         struct drm_psb_private *dev_priv = psb_priv(dev);
 538         uint32_t *arg = data;
 539         struct backlight_device *bd = dev_priv->backlight_device;
 540         dev_priv->blc_adj1 = *arg;
 541
 542 #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
 543         if (bd) {
 544                 bd->props.brightness = bd->ops->get_brightness(bd);
 545                 backlight_update_status(bd);
 546         }
 547 #endif
 548         return 0;
 549 }
 550
 551 /* return the current mode to the dpst module */
 552 static int psb_dpst_ioctl(struct drm_device *dev, void *data,
 553                           struct drm_file *file_priv)
 554 {
 555         struct drm_psb_private *dev_priv = psb_priv(dev);
 556         uint32_t *arg = data;
 557         uint32_t x;
 558         uint32_t y;
 559         uint32_t reg;
 560
 561         if (!gma_power_begin(dev, 0))
 562                 return -EIO;
 563
 564         reg = PSB_RVDC32(PIPEASRC);
 565
 566         gma_power_end(dev);
 567
 568         /* horizontal is the left 16 bits */
 569         x = reg >> 16;
 570         /* vertical is the right 16 bits */
 571         y = reg & 0x0000ffff;
 572
 573         /* the values are the image size minus one */
 574         x++;
 575         y++;
 576
 577         *arg = (x << 16) | y;
 578
 579         return 0;
 580 }
 581 static int psb_gamma_ioctl(struct drm_device *dev, void *data,
 582                            struct drm_file *file_priv)
 583 {
 584         struct drm_psb_dpst_lut_arg *lut_arg = data;
 585         struct drm_mode_object *obj;
 586         struct drm_crtc *crtc;
 587         struct drm_connector *connector;
 588         struct psb_intel_crtc *psb_intel_crtc;
 589         int i = 0;
 590         int32_t obj_id;
 591
 592         obj_id = lut_arg->output_id;
 593         obj = drm_mode_object_find(dev, obj_id, DRM_MODE_OBJECT_CONNECTOR);
 594         if (!obj) {
 595                 dev_dbg(dev->dev, "Invalid Connector object.\n");
 596                 return -EINVAL;
 597         }
 598
 599         connector = obj_to_connector(obj);
 600         crtc = connector->encoder->crtc;
 601         psb_intel_crtc = to_psb_intel_crtc(crtc);
 602
 603         for (i = 0; i < 256; i++)
 604                 psb_intel_crtc->lut_adj[i] = lut_arg->lut[i];
 605
 606         psb_intel_crtc_load_lut(crtc);
 607
 608         return 0;
 609 }
 610
 611 static int psb_mode_operation_ioctl(struct drm_device *dev, void *data,
 612                                 struct drm_file *file_priv)
 613 {
 614         uint32_t obj_id;
 615         uint16_t op;
 616         struct drm_mode_modeinfo *umode;
 617         struct drm_display_mode *mode = NULL;
 618         struct drm_psb_mode_operation_arg *arg;
 619         struct drm_mode_object *obj;
 620         struct drm_connector *connector;
 621         struct drm_framebuffer *drm_fb;
 622         struct psb_framebuffer *psb_fb;
 623         struct drm_connector_helper_funcs *connector_funcs;
 624         int ret = 0;
 625         int resp = MODE_OK;
 626         struct drm_psb_private *dev_priv = psb_priv(dev);
 627
 628         arg = (struct drm_psb_mode_operation_arg *)data;
 629         obj_id = arg->obj_id;
 630         op = arg->operation;
 631
 632         switch (op) {
 633         case PSB_MODE_OPERATION_SET_DC_BASE:
 634                 obj = drm_mode_object_find(dev, obj_id, DRM_MODE_OBJECT_FB);
 635                 if (!obj) {
 636                         dev_dbg(dev->dev, "Invalid FB id %d\n", obj_id);
 637                         return -EINVAL;
 638                 }
 639
 640                 drm_fb = obj_to_fb(obj);
 641                 psb_fb = to_psb_fb(drm_fb);
 642
 643                 if (gma_power_begin(dev, 0)) {
 644                         REG_WRITE(DSPASURF, psb_fb->gtt->offset);
 645                         REG_READ(DSPASURF);
 646                         gma_power_end(dev);
 647                 } else {
 648                         dev_priv->saveDSPASURF = psb_fb->gtt->offset;
 649                 }
 650
 651                 return 0;
 652         case PSB_MODE_OPERATION_MODE_VALID:
 653                 umode = &arg->mode;
 654
 655                 mutex_lock(&dev->mode_config.mutex);
 656
 657                 obj = drm_mode_object_find(dev, obj_id,
 658                                         DRM_MODE_OBJECT_CONNECTOR);
 659                 if (!obj) {
 660                         ret = -EINVAL;
 661                         goto mode_op_out;
 662                 }
 663
 664                 connector = obj_to_connector(obj);
 665
 666                 mode = drm_mode_create(dev);
 667                 if (!mode) {
 668                         ret = -ENOMEM;
 669                         goto mode_op_out;
 670                 }
 671
 672                 /* drm_crtc_convert_umode(mode, umode); */
 673                 {
 674                         mode->clock = umode->clock;
 675                         mode->hdisplay = umode->hdisplay;
 676                         mode->hsync_start = umode->hsync_start;
 677                         mode->hsync_end = umode->hsync_end;
 678                         mode->htotal = umode->htotal;
 679                         mode->hskew = umode->hskew;
 680                         mode->vdisplay = umode->vdisplay;
 681                         mode->vsync_start = umode->vsync_start;
 682                         mode->vsync_end = umode->vsync_end;
 683                         mode->vtotal = umode->vtotal;
 684                         mode->vscan = umode->vscan;
 685                         mode->vrefresh = umode->vrefresh;
 686                         mode->flags = umode->flags;
 687                         mode->type = umode->type;
 688                         strncpy(mode->name, umode->name, DRM_DISPLAY_MODE_LEN);
 689                         mode->name[DRM_DISPLAY_MODE_LEN-1] = 0;
 690                 }
 691
 692                 connector_funcs = (struct drm_connector_helper_funcs *)
 693                                    connector->helper_private;
 694
 695                 if (connector_funcs->mode_valid) {
 696                         resp = connector_funcs->mode_valid(connector, mode);
 697                         arg->data = (void *)resp;
 698                 }
 699
 700                 /*do some clean up work*/
 701                 if (mode)
 702                         drm_mode_destroy(dev, mode);
 703 mode_op_out:
 704                 mutex_unlock(&dev->mode_config.mutex);
 705                 return ret;
 706
 707         default:
 708                 dev_dbg(dev->dev, "Unsupported psb mode operation\n");
 709                 return -EOPNOTSUPP;
 710         }
 711
 712         return 0;
 713 }
 714
 715 static int psb_stolen_memory_ioctl(struct drm_device *dev, void *data,
 716                                    struct drm_file *file_priv)
 717 {
 718         struct drm_psb_private *dev_priv = psb_priv(dev);
 719         struct drm_psb_stolen_memory_arg *arg = data;
 720
 721         arg->base = dev_priv->stolen_base;
 722         arg->size = dev_priv->vram_stolen_size;
 723
 724         return 0;
 725 }
 726
 727 /* FIXME: needs Medfield changes */
 728 static int psb_register_rw_ioctl(struct drm_device *dev, void *data,
 729                                  struct drm_file *file_priv)
 730 {
 731         struct drm_psb_private *dev_priv = psb_priv(dev);
 732         struct drm_psb_register_rw_arg *arg = data;
 733         bool usage = arg->b_force_hw_on ? true : false;
 734
 735         if (arg->display_write_mask != 0) {
 736                 if (gma_power_begin(dev, usage)) {
 737                         if (arg->display_write_mask & REGRWBITS_PFIT_CONTROLS)
 738                                 PSB_WVDC32(arg->display.pfit_controls,
 739                                            PFIT_CONTROL);
 740                         if (arg->display_write_mask &
 741                             REGRWBITS_PFIT_AUTOSCALE_RATIOS)
 742                                 PSB_WVDC32(arg->display.pfit_autoscale_ratios,
 743                                            PFIT_AUTO_RATIOS);
 744                         if (arg->display_write_mask &
 745                             REGRWBITS_PFIT_PROGRAMMED_SCALE_RATIOS)
 746                                 PSB_WVDC32(
 747                                    arg->display.pfit_programmed_scale_ratios,
 748                                    PFIT_PGM_RATIOS);
 749                         if (arg->display_write_mask & REGRWBITS_PIPEASRC)
 750                                 PSB_WVDC32(arg->display.pipeasrc,
 751                                            PIPEASRC);
 752                         if (arg->display_write_mask & REGRWBITS_PIPEBSRC)
 753                                 PSB_WVDC32(arg->display.pipebsrc,
 754                                            PIPEBSRC);
 755                         if (arg->display_write_mask & REGRWBITS_VTOTAL_A)
 756                                 PSB_WVDC32(arg->display.vtotal_a,
 757                                            VTOTAL_A);
 758                         if (arg->display_write_mask & REGRWBITS_VTOTAL_B)
 759                                 PSB_WVDC32(arg->display.vtotal_b,
 760                                            VTOTAL_B);
 761                         gma_power_end(dev);
 762                 } else {
 763                         if (arg->display_write_mask & REGRWBITS_PFIT_CONTROLS)
 764                                 dev_priv->savePFIT_CONTROL =
 765                                                 arg->display.pfit_controls;
 766                         if (arg->display_write_mask &
 767                             REGRWBITS_PFIT_AUTOSCALE_RATIOS)
 768                                 dev_priv->savePFIT_AUTO_RATIOS =
 769                                         arg->display.pfit_autoscale_ratios;
 770                         if (arg->display_write_mask &
 771                             REGRWBITS_PFIT_PROGRAMMED_SCALE_RATIOS)
 772                                 dev_priv->savePFIT_PGM_RATIOS =
 773                                    arg->display.pfit_programmed_scale_ratios;
 774                         if (arg->display_write_mask & REGRWBITS_PIPEASRC)
 775                                 dev_priv->savePIPEASRC = arg->display.pipeasrc;
 776                         if (arg->display_write_mask & REGRWBITS_PIPEBSRC)
 777                                 dev_priv->savePIPEBSRC = arg->display.pipebsrc;
 778                         if (arg->display_write_mask & REGRWBITS_VTOTAL_A)
 779                                 dev_priv->saveVTOTAL_A = arg->display.vtotal_a;
 780                         if (arg->display_write_mask & REGRWBITS_VTOTAL_B)
 781                                 dev_priv->saveVTOTAL_B = arg->display.vtotal_b;
 782                 }
 783         }
 784
 785         if (arg->display_read_mask != 0) {
 786                 if (gma_power_begin(dev, usage)) {
 787                         if (arg->display_read_mask &
 788                             REGRWBITS_PFIT_CONTROLS)
 789                                 arg->display.pfit_controls =
 790                                                 PSB_RVDC32(PFIT_CONTROL);
 791                         if (arg->display_read_mask &
 792                             REGRWBITS_PFIT_AUTOSCALE_RATIOS)
 793                                 arg->display.pfit_autoscale_ratios =
 794                                                 PSB_RVDC32(PFIT_AUTO_RATIOS);
 795                         if (arg->display_read_mask &
 796                             REGRWBITS_PFIT_PROGRAMMED_SCALE_RATIOS)
 797                                 arg->display.pfit_programmed_scale_ratios =
 798                                                 PSB_RVDC32(PFIT_PGM_RATIOS);
 799                         if (arg->display_read_mask & REGRWBITS_PIPEASRC)
 800                                 arg->display.pipeasrc = PSB_RVDC32(PIPEASRC);
 801                         if (arg->display_read_mask & REGRWBITS_PIPEBSRC)
 802                                 arg->display.pipebsrc = PSB_RVDC32(PIPEBSRC);
 803                         if (arg->display_read_mask & REGRWBITS_VTOTAL_A)
 804                                 arg->display.vtotal_a = PSB_RVDC32(VTOTAL_A);
 805                         if (arg->display_read_mask & REGRWBITS_VTOTAL_B)
 806                                 arg->display.vtotal_b = PSB_RVDC32(VTOTAL_B);
 807                         gma_power_end(dev);
 808                 } else {
 809                         if (arg->display_read_mask &
 810                             REGRWBITS_PFIT_CONTROLS)
 811                                 arg->display.pfit_controls =
 812                                                 dev_priv->savePFIT_CONTROL;
 813                         if (arg->display_read_mask &
 814                             REGRWBITS_PFIT_AUTOSCALE_RATIOS)
 815                                 arg->display.pfit_autoscale_ratios =
 816                                                 dev_priv->savePFIT_AUTO_RATIOS;
 817                         if (arg->display_read_mask &
 818                             REGRWBITS_PFIT_PROGRAMMED_SCALE_RATIOS)
 819                                 arg->display.pfit_programmed_scale_ratios =
 820                                                 dev_priv->savePFIT_PGM_RATIOS;
 821                         if (arg->display_read_mask & REGRWBITS_PIPEASRC)
 822                                 arg->display.pipeasrc = dev_priv->savePIPEASRC;
 823                         if (arg->display_read_mask & REGRWBITS_PIPEBSRC)
 824                                 arg->display.pipebsrc = dev_priv->savePIPEBSRC;
 825                         if (arg->display_read_mask & REGRWBITS_VTOTAL_A)
 826                                 arg->display.vtotal_a = dev_priv->saveVTOTAL_A;
 827                         if (arg->display_read_mask & REGRWBITS_VTOTAL_B)
 828                                 arg->display.vtotal_b = dev_priv->saveVTOTAL_B;
 829                 }
 830         }
 831
 832         if (arg->overlay_write_mask != 0) {
 833                 if (gma_power_begin(dev, usage)) {
 834                         if (arg->overlay_write_mask & OV_REGRWBITS_OGAM_ALL) {
 835                                 PSB_WVDC32(arg->overlay.OGAMC5, OV_OGAMC5);
 836                                 PSB_WVDC32(arg->overlay.OGAMC4, OV_OGAMC4);
 837                                 PSB_WVDC32(arg->overlay.OGAMC3, OV_OGAMC3);
 838                                 PSB_WVDC32(arg->overlay.OGAMC2, OV_OGAMC2);
 839                                 PSB_WVDC32(arg->overlay.OGAMC1, OV_OGAMC1);
 840                                 PSB_WVDC32(arg->overlay.OGAMC0, OV_OGAMC0);
 841                         }
 842                         if (arg->overlay_write_mask & OVC_REGRWBITS_OGAM_ALL) {
 843                                 PSB_WVDC32(arg->overlay.OGAMC5, OVC_OGAMC5);
 844                                 PSB_WVDC32(arg->overlay.OGAMC4, OVC_OGAMC4);
 845                                 PSB_WVDC32(arg->overlay.OGAMC3, OVC_OGAMC3);
 846                                 PSB_WVDC32(arg->overlay.OGAMC2, OVC_OGAMC2);
 847                                 PSB_WVDC32(arg->overlay.OGAMC1, OVC_OGAMC1);
 848                                 PSB_WVDC32(arg->overlay.OGAMC0, OVC_OGAMC0);
 849                         }
 850
 851                         if (arg->overlay_write_mask & OV_REGRWBITS_OVADD) {
 852                                 PSB_WVDC32(arg->overlay.OVADD, OV_OVADD);
 853
 854                                 if (arg->overlay.b_wait_vblank) {
 855                                         /* Wait for 20ms.*/
 856                                         unsigned long vblank_timeout = jiffies
 857                                                                 + HZ/50;
 858                                         uint32_t temp;
 859                                         while (time_before_eq(jiffies,
 860                                                         vblank_timeout)) {
 861                                                 temp = PSB_RVDC32(OV_DOVASTA);
 862                                                 if ((temp & (0x1 << 31)) != 0)
 863                                                         break;
 864                                                 cpu_relax();
 865                                         }
 866                                 }
 867                         }
 868                         if (arg->overlay_write_mask & OVC_REGRWBITS_OVADD) {
 869                                 PSB_WVDC32(arg->overlay.OVADD, OVC_OVADD);
 870                                 if (arg->overlay.b_wait_vblank) {
 871                                         /* Wait for 20ms.*/
 872                                         unsigned long vblank_timeout =
 873                                                         jiffies + HZ/50;
 874                                         uint32_t temp;
 875                                         while (time_before_eq(jiffies,
 876                                                         vblank_timeout)) {
 877                                                 temp = PSB_RVDC32(OVC_DOVCSTA);
 878                                                 if ((temp & (0x1 << 31)) != 0)
 879                                                         break;
 880                                                 cpu_relax();
 881                                         }
 882                                 }
 883                         }
 884                         gma_power_end(dev);
 885                 } else {
 886                         if (arg->overlay_write_mask & OV_REGRWBITS_OGAM_ALL) {
 887                                 dev_priv->saveOV_OGAMC5 = arg->overlay.OGAMC5;
 888                                 dev_priv->saveOV_OGAMC4 = arg->overlay.OGAMC4;
 889                                 dev_priv->saveOV_OGAMC3 = arg->overlay.OGAMC3;
 890                                 dev_priv->saveOV_OGAMC2 = arg->overlay.OGAMC2;
 891                                 dev_priv->saveOV_OGAMC1 = arg->overlay.OGAMC1;
 892                                 dev_priv->saveOV_OGAMC0 = arg->overlay.OGAMC0;
 893                         }
 894                         if (arg->overlay_write_mask & OVC_REGRWBITS_OGAM_ALL) {
 895                                 dev_priv->saveOVC_OGAMC5 = arg->overlay.OGAMC5;
 896                                 dev_priv->saveOVC_OGAMC4 = arg->overlay.OGAMC4;
 897                                 dev_priv->saveOVC_OGAMC3 = arg->overlay.OGAMC3;
 898                                 dev_priv->saveOVC_OGAMC2 = arg->overlay.OGAMC2;
 899                                 dev_priv->saveOVC_OGAMC1 = arg->overlay.OGAMC1;
 900                                 dev_priv->saveOVC_OGAMC0 = arg->overlay.OGAMC0;
 901                         }
 902                         if (arg->overlay_write_mask & OV_REGRWBITS_OVADD)
 903                                 dev_priv->saveOV_OVADD = arg->overlay.OVADD;
 904                         if (arg->overlay_write_mask & OVC_REGRWBITS_OVADD)
 905                                 dev_priv->saveOVC_OVADD = arg->overlay.OVADD;
 906                 }
 907         }
 908
 909         if (arg->overlay_read_mask != 0) {
 910                 if (gma_power_begin(dev, usage)) {
 911                         if (arg->overlay_read_mask & OV_REGRWBITS_OGAM_ALL) {
 912                                 arg->overlay.OGAMC5 = PSB_RVDC32(OV_OGAMC5);
 913                                 arg->overlay.OGAMC4 = PSB_RVDC32(OV_OGAMC4);
 914                                 arg->overlay.OGAMC3 = PSB_RVDC32(OV_OGAMC3);
 915                                 arg->overlay.OGAMC2 = PSB_RVDC32(OV_OGAMC2);
 916                                 arg->overlay.OGAMC1 = PSB_RVDC32(OV_OGAMC1);
 917                                 arg->overlay.OGAMC0 = PSB_RVDC32(OV_OGAMC0);
 918                         }
 919                         if (arg->overlay_read_mask & OVC_REGRWBITS_OGAM_ALL) {
 920                                 arg->overlay.OGAMC5 = PSB_RVDC32(OVC_OGAMC5);
 921                                 arg->overlay.OGAMC4 = PSB_RVDC32(OVC_OGAMC4);
 922                                 arg->overlay.OGAMC3 = PSB_RVDC32(OVC_OGAMC3);
 923                                 arg->overlay.OGAMC2 = PSB_RVDC32(OVC_OGAMC2);
 924                                 arg->overlay.OGAMC1 = PSB_RVDC32(OVC_OGAMC1);
 925                                 arg->overlay.OGAMC0 = PSB_RVDC32(OVC_OGAMC0);
 926                         }
 927                         if (arg->overlay_read_mask & OV_REGRWBITS_OVADD)
 928                                 arg->overlay.OVADD = PSB_RVDC32(OV_OVADD);
 929                         if (arg->overlay_read_mask & OVC_REGRWBITS_OVADD)
 930                                 arg->overlay.OVADD = PSB_RVDC32(OVC_OVADD);
 931                         gma_power_end(dev);
 932                 } else {
 933                         if (arg->overlay_read_mask & OV_REGRWBITS_OGAM_ALL) {
 934                                 arg->overlay.OGAMC5 = dev_priv->saveOV_OGAMC5;
 935                                 arg->overlay.OGAMC4 = dev_priv->saveOV_OGAMC4;
 936                                 arg->overlay.OGAMC3 = dev_priv->saveOV_OGAMC3;
 937                                 arg->overlay.OGAMC2 = dev_priv->saveOV_OGAMC2;
 938                                 arg->overlay.OGAMC1 = dev_priv->saveOV_OGAMC1;
 939                                 arg->overlay.OGAMC0 = dev_priv->saveOV_OGAMC0;
 940                         }
 941                         if (arg->overlay_read_mask & OVC_REGRWBITS_OGAM_ALL) {
 942                                 arg->overlay.OGAMC5 = dev_priv->saveOVC_OGAMC5;
 943                                 arg->overlay.OGAMC4 = dev_priv->saveOVC_OGAMC4;
 944                                 arg->overlay.OGAMC3 = dev_priv->saveOVC_OGAMC3;
 945                                 arg->overlay.OGAMC2 = dev_priv->saveOVC_OGAMC2;
 946                                 arg->overlay.OGAMC1 = dev_priv->saveOVC_OGAMC1;
 947                                 arg->overlay.OGAMC0 = dev_priv->saveOVC_OGAMC0;
 948                         }
 949                         if (arg->overlay_read_mask & OV_REGRWBITS_OVADD)
 950                                 arg->overlay.OVADD = dev_priv->saveOV_OVADD;
 951                         if (arg->overlay_read_mask & OVC_REGRWBITS_OVADD)
 952                                 arg->overlay.OVADD = dev_priv->saveOVC_OVADD;
 953                 }
 954         }
 955
 956         if (arg->sprite_enable_mask != 0) {
 957                 if (gma_power_begin(dev, usage)) {
 958                         PSB_WVDC32(0x1F3E, DSPARB);
 959                         PSB_WVDC32(arg->sprite.dspa_control
 960                                         | PSB_RVDC32(DSPACNTR), DSPACNTR);
 961                         PSB_WVDC32(arg->sprite.dspa_key_value, DSPAKEYVAL);
 962                         PSB_WVDC32(arg->sprite.dspa_key_mask, DSPAKEYMASK);
 963                         PSB_WVDC32(PSB_RVDC32(DSPASURF), DSPASURF);
 964                         PSB_RVDC32(DSPASURF);
 965                         PSB_WVDC32(arg->sprite.dspc_control, DSPCCNTR);
 966                         PSB_WVDC32(arg->sprite.dspc_stride, DSPCSTRIDE);
 967                         PSB_WVDC32(arg->sprite.dspc_position, DSPCPOS);
 968                         PSB_WVDC32(arg->sprite.dspc_linear_offset, DSPCLINOFF);
 969                         PSB_WVDC32(arg->sprite.dspc_size, DSPCSIZE);
 970                         PSB_WVDC32(arg->sprite.dspc_surface, DSPCSURF);
 971                         PSB_RVDC32(DSPCSURF);
 972                         gma_power_end(dev);
 973                 }
 974         }
 975
 976         if (arg->sprite_disable_mask != 0) {
 977                 if (gma_power_begin(dev, usage)) {
 978                         PSB_WVDC32(0x3F3E, DSPARB);
 979                         PSB_WVDC32(0x0, DSPCCNTR);
 980                         PSB_WVDC32(arg->sprite.dspc_surface, DSPCSURF);
 981                         PSB_RVDC32(DSPCSURF);
 982                         gma_power_end(dev);
 983                 }
 984         }
 985
 986         if (arg->subpicture_enable_mask != 0) {
 987                 if (gma_power_begin(dev, usage)) {
 988                         uint32_t temp;
 989                         if (arg->subpicture_enable_mask & REGRWBITS_DSPACNTR) {
 990                                 temp =  PSB_RVDC32(DSPACNTR);
 991                                 temp &= ~DISPPLANE_PIXFORMAT_MASK;
 992                                 temp &= ~DISPPLANE_BOTTOM;
 993                                 temp |= DISPPLANE_32BPP;
 994                                 PSB_WVDC32(temp, DSPACNTR);
 995
 996                                 temp =  PSB_RVDC32(DSPABASE);
 997                                 PSB_WVDC32(temp, DSPABASE);
 998                                 PSB_RVDC32(DSPABASE);
 999                                 temp =  PSB_RVDC32(DSPASURF);
1000                                 PSB_WVDC32(temp, DSPASURF);
1001                                 PSB_RVDC32(DSPASURF);
1002                         }
1003                         if (arg->subpicture_enable_mask & REGRWBITS_DSPBCNTR) {
1004                                 temp =  PSB_RVDC32(DSPBCNTR);
1005                                 temp &= ~DISPPLANE_PIXFORMAT_MASK;
1006                                 temp &= ~DISPPLANE_BOTTOM;
1007                                 temp |= DISPPLANE_32BPP;
1008                                 PSB_WVDC32(temp, DSPBCNTR);
1009
1010                                 temp =  PSB_RVDC32(DSPBBASE);
1011                                 PSB_WVDC32(temp, DSPBBASE);
1012                                 PSB_RVDC32(DSPBBASE);
1013                                 temp =  PSB_RVDC32(DSPBSURF);
1014                                 PSB_WVDC32(temp, DSPBSURF);
1015                                 PSB_RVDC32(DSPBSURF);
1016                         }
1017                         if (arg->subpicture_enable_mask & REGRWBITS_DSPCCNTR) {
1018                                 temp =  PSB_RVDC32(DSPCCNTR);
1019                                 temp &= ~DISPPLANE_PIXFORMAT_MASK;
1020                                 temp &= ~DISPPLANE_BOTTOM;
1021                                 temp |= DISPPLANE_32BPP;
1022                                 PSB_WVDC32(temp, DSPCCNTR);
1023
1024                                 temp =  PSB_RVDC32(DSPCBASE);
1025                                 PSB_WVDC32(temp, DSPCBASE);
1026                                 PSB_RVDC32(DSPCBASE);
1027                                 temp =  PSB_RVDC32(DSPCSURF);
1028                                 PSB_WVDC32(temp, DSPCSURF);
1029                                 PSB_RVDC32(DSPCSURF);
1030                         }
1031                         gma_power_end(dev);
1032                 }
1033         }
1034
1035         if (arg->subpicture_disable_mask != 0) {
1036                 if (gma_power_begin(dev, usage)) {
1037                         uint32_t temp;
1038                         if (arg->subpicture_disable_mask & REGRWBITS_DSPACNTR) {
1039                                 temp =  PSB_RVDC32(DSPACNTR);
1040                                 temp &= ~DISPPLANE_PIXFORMAT_MASK;
1041                                 temp |= DISPPLANE_32BPP_NO_ALPHA;
1042                                 PSB_WVDC32(temp, DSPACNTR);
1043
1044                                 temp =  PSB_RVDC32(DSPABASE);
1045                                 PSB_WVDC32(temp, DSPABASE);
1046                                 PSB_RVDC32(DSPABASE);
1047                                 temp =  PSB_RVDC32(DSPASURF);
1048                                 PSB_WVDC32(temp, DSPASURF);
1049                                 PSB_RVDC32(DSPASURF);
1050                         }
1051                         if (arg->subpicture_disable_mask & REGRWBITS_DSPBCNTR) {
1052                                 temp =  PSB_RVDC32(DSPBCNTR);
1053                                 temp &= ~DISPPLANE_PIXFORMAT_MASK;
1054                                 temp |= DISPPLANE_32BPP_NO_ALPHA;
1055                                 PSB_WVDC32(temp, DSPBCNTR);
1056
1057                                 temp =  PSB_RVDC32(DSPBBASE);
1058                                 PSB_WVDC32(temp, DSPBBASE);
1059                                 PSB_RVDC32(DSPBBASE);
1060                                 temp =  PSB_RVDC32(DSPBSURF);
1061                                 PSB_WVDC32(temp, DSPBSURF);
1062                                 PSB_RVDC32(DSPBSURF);
1063                         }
1064                         if (arg->subpicture_disable_mask & REGRWBITS_DSPCCNTR) {
1065                                 temp =  PSB_RVDC32(DSPCCNTR);
1066                                 temp &= ~DISPPLANE_PIXFORMAT_MASK;
1067                                 temp |= DISPPLANE_32BPP_NO_ALPHA;
1068                                 PSB_WVDC32(temp, DSPCCNTR);
1069
1070                                 temp =  PSB_RVDC32(DSPCBASE);
1071                                 PSB_WVDC32(temp, DSPCBASE);
1072                                 PSB_RVDC32(DSPCBASE);
1073                                 temp =  PSB_RVDC32(DSPCSURF);
1074                                 PSB_WVDC32(temp, DSPCSURF);
1075                                 PSB_RVDC32(DSPCSURF);
1076                         }
1077                         gma_power_end(dev);
1078                 }
1079         }
1080
1081         return 0;
1082 }
1083
1084 static int psb_driver_open(struct drm_device *dev, struct drm_file *priv)
1085 {
1086         return 0;
1087 }
1088
1089 static void psb_driver_close(struct drm_device *dev, struct drm_file *priv)
1090 {
1091 }
1092
1093 static long psb_unlocked_ioctl(struct file *filp, unsigned int cmd,
1094                                unsigned long arg)
1095 {
1096         struct drm_file *file_priv = filp->private_data;
1097         struct drm_device *dev = file_priv->minor->dev;
1098         struct drm_psb_private *dev_priv = dev->dev_private;
1099         static unsigned int runtime_allowed;
1100
1101         if (runtime_allowed == 1 && dev_priv->is_lvds_on) {
1102                 runtime_allowed++;
1103                 pm_runtime_allow(&dev->pdev->dev);
1104                 dev_priv->rpm_enabled = 1;
1105         }
1106         return drm_ioctl(filp, cmd, arg);
1107         /* FIXME: do we need to wrap the other side of this */
1108 }
1109
1110
1111 /* When a client dies:
1112  *    - Check for and clean up flipped page state
1113  */
1114 void psb_driver_preclose(struct drm_device *dev, struct drm_file *priv)
1115 {
1116 }
1117
1118 static void psb_remove(struct pci_dev *pdev)
1119 {
1120         struct drm_device *dev = pci_get_drvdata(pdev);
1121         drm_put_dev(dev);
1122 }
1123
1124 static const struct dev_pm_ops psb_pm_ops = {
1125         .runtime_suspend = psb_runtime_suspend,
1126         .runtime_resume = psb_runtime_resume,
1127         .runtime_idle = psb_runtime_idle,
1128 };
1129
1130 static struct vm_operations_struct psb_gem_vm_ops = {
1131         .fault = psb_gem_fault,
1132         .open = drm_gem_vm_open,
1133         .close = drm_gem_vm_close,
1134 };
1135
1136 static struct drm_driver driver = {
1137         .driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | \
1138                            DRIVER_IRQ_VBL | DRIVER_MODESET | DRIVER_GEM ,
1139         .load = psb_driver_load,
1140         .unload = psb_driver_unload,
1141
1142         .ioctls = psb_ioctls,
1143         .num_ioctls = DRM_ARRAY_SIZE(psb_ioctls),
1144         .device_is_agp = psb_driver_device_is_agp,
1145         .irq_preinstall = psb_irq_preinstall,
1146         .irq_postinstall = psb_irq_postinstall,
1147         .irq_uninstall = psb_irq_uninstall,
1148         .irq_handler = psb_irq_handler,
1149         .enable_vblank = psb_enable_vblank,
1150         .disable_vblank = psb_disable_vblank,
1151         .get_vblank_counter = psb_get_vblank_counter,
1152         .lastclose = psb_lastclose,
1153         .open = psb_driver_open,
1154         .preclose = psb_driver_preclose,
1155         .postclose = psb_driver_close,
1156         .reclaim_buffers = drm_core_reclaim_buffers,
1157
1158         .gem_init_object = psb_gem_init_object,
1159         .gem_free_object = psb_gem_free_object,
1160         .gem_vm_ops = &psb_gem_vm_ops,
1161         .dumb_create = psb_gem_dumb_create,
1162         .dumb_map_offset = psb_gem_dumb_map_gtt,
1163         .dumb_destroy = psb_gem_dumb_destroy,
1164
1165         .fops = {
1166                  .owner = THIS_MODULE,
1167                  .open = drm_open,
1168                  .release = drm_release,
1169                  .unlocked_ioctl = psb_unlocked_ioctl,
1170                  .mmap = drm_gem_mmap,
1171                  .poll = drm_poll,
1172                  .fasync = drm_fasync,
1173                  .read = drm_read,
1174          },
1175         .name = DRIVER_NAME,
1176         .desc = DRIVER_DESC,
1177         .date = PSB_DRM_DRIVER_DATE,
1178         .major = PSB_DRM_DRIVER_MAJOR,
1179         .minor = PSB_DRM_DRIVER_MINOR,
1180         .patchlevel = PSB_DRM_DRIVER_PATCHLEVEL
1181 };
1182
1183 static struct pci_driver psb_pci_driver = {
1184         .name = DRIVER_NAME,
1185         .id_table = pciidlist,
1186         .resume = gma_power_resume,
1187         .suspend = gma_power_suspend,
1188         .probe = psb_probe,
1189         .remove = psb_remove,
1190 #ifdef CONFIG_PM
1191         .driver.pm = &psb_pm_ops,
1192 #endif
1193 };
1194
1195 static int psb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1196 {
1197         /* MLD Added this from Inaky's patch */
1198         if (pci_enable_msi(pdev))
1199                 dev_warn(&pdev->dev, "Enable MSI failed!\n");
1200         return drm_get_pci_dev(pdev, ent, &driver);
1201 }
1202
1203 static int __init psb_init(void)
1204 {
1205         return drm_pci_init(&driver, &psb_pci_driver);
1206 }
1207
1208 static void __exit psb_exit(void)
1209 {
1210         drm_pci_exit(&driver, &psb_pci_driver);
1211 }
1212
1213 late_initcall(psb_init);
1214 module_exit(psb_exit);
1215
1216 MODULE_AUTHOR("Alan Cox <alan@linux.intel.com> and others");
1217 MODULE_DESCRIPTION(DRIVER_DESC);
1218 MODULE_LICENSE("GPL");