Pileus Git - ~andy/linux/blob - drivers/staging/gma500/psb_drv.c

   1 /**************************************************************************
   2  * Copyright (c) 2007-2011, Intel Corporation.
   3  * All Rights Reserved.
   4  * Copyright (c) 2008, Tungsten Graphics, Inc. Cedar Park, TX., USA.
   5  * All Rights Reserved.
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms and conditions of the GNU General Public License,
   9  * version 2, as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program; if not, write to the Free Software Foundation, Inc.,
  18  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  **************************************************************************/
  21
  22 #include <drm/drmP.h>
  23 #include <drm/drm.h>
  24 #include "psb_drm.h"
  25 #include "psb_drv.h"
  26 #include "psb_fb.h"
  27 #include "psb_reg.h"
  28 #include "psb_intel_reg.h"
  29 #include "psb_intel_bios.h"
  30 #include "mrst_bios.h"
  31 #include "mdfld_dsi_dbi.h"
  32 #include <drm/drm_pciids.h>
  33 #include "psb_powermgmt.h"
  34 #include <linux/cpu.h>
  35 #include <linux/notifier.h>
  36 #include <linux/spinlock.h>
  37 #include <linux/pm_runtime.h>
  38 #include <acpi/video.h>
  39
  40 static int drm_psb_trap_pagefaults;
  41
  42 int drm_psb_no_fb;
  43
  44 static int psb_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
  45
  46 MODULE_PARM_DESC(no_fb, "Disable FBdev");
  47 MODULE_PARM_DESC(trap_pagefaults, "Error and reset on MMU pagefaults");
  48 module_param_named(no_fb, drm_psb_no_fb, int, 0600);
  49 module_param_named(trap_pagefaults, drm_psb_trap_pagefaults, int, 0600);
  50
  51
  52 static DEFINE_PCI_DEVICE_TABLE(pciidlist) = {
  53         { 0x8086, 0x8108, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &psb_chip_ops },
  54         { 0x8086, 0x8109, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &psb_chip_ops },
  55         { 0x8086, 0x4100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mrst_chip_ops},
  56         { 0x8086, 0x4101, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mrst_chip_ops},
  57         { 0x8086, 0x4102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mrst_chip_ops},
  58         { 0x8086, 0x4103, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mrst_chip_ops},
  59         { 0x8086, 0x4104, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mrst_chip_ops},
  60         { 0x8086, 0x4105, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mrst_chip_ops},
  61         { 0x8086, 0x4106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mrst_chip_ops},
  62         { 0x8086, 0x4107, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mrst_chip_ops},
  63         { 0x8086, 0x0130, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mdfld_chip_ops},
  64         { 0x8086, 0x0131, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mdfld_chip_ops},
  65         { 0x8086, 0x0132, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mdfld_chip_ops},
  66         { 0x8086, 0x0133, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mdfld_chip_ops},
  67         { 0x8086, 0x0134, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mdfld_chip_ops},
  68         { 0x8086, 0x0135, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mdfld_chip_ops},
  69         { 0x8086, 0x0136, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mdfld_chip_ops},
  70         { 0x8086, 0x0137, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mdfld_chip_ops},
  71         { 0, 0, 0}
  72 };
  73 MODULE_DEVICE_TABLE(pci, pciidlist);
  74
  75 /*
  76  * Standard IOCTLs.
  77  */
  78
  79 #define DRM_IOCTL_PSB_SIZES     \
  80                 DRM_IOR(DRM_PSB_SIZES + DRM_COMMAND_BASE, \
  81                         struct drm_psb_sizes_arg)
  82 #define DRM_IOCTL_PSB_FUSE_REG  \
  83                 DRM_IOWR(DRM_PSB_FUSE_REG + DRM_COMMAND_BASE, uint32_t)
  84 #define DRM_IOCTL_PSB_DC_STATE  \
  85                 DRM_IOW(DRM_PSB_DC_STATE + DRM_COMMAND_BASE, \
  86                         struct drm_psb_dc_state_arg)
  87 #define DRM_IOCTL_PSB_ADB       \
  88                 DRM_IOWR(DRM_PSB_ADB + DRM_COMMAND_BASE, uint32_t)
  89 #define DRM_IOCTL_PSB_MODE_OPERATION    \
  90                 DRM_IOWR(DRM_PSB_MODE_OPERATION + DRM_COMMAND_BASE, \
  91                          struct drm_psb_mode_operation_arg)
  92 #define DRM_IOCTL_PSB_STOLEN_MEMORY     \
  93                 DRM_IOWR(DRM_PSB_STOLEN_MEMORY + DRM_COMMAND_BASE, \
  94                          struct drm_psb_stolen_memory_arg)
  95 #define DRM_IOCTL_PSB_REGISTER_RW       \
  96                 DRM_IOWR(DRM_PSB_REGISTER_RW + DRM_COMMAND_BASE, \
  97                          struct drm_psb_register_rw_arg)
  98 #define DRM_IOCTL_PSB_DPST      \
  99                 DRM_IOWR(DRM_PSB_DPST + DRM_COMMAND_BASE, \
 100                          uint32_t)
 101 #define DRM_IOCTL_PSB_GAMMA     \
 102                 DRM_IOWR(DRM_PSB_GAMMA + DRM_COMMAND_BASE, \
 103                          struct drm_psb_dpst_lut_arg)
 104 #define DRM_IOCTL_PSB_DPST_BL   \
 105                 DRM_IOWR(DRM_PSB_DPST_BL + DRM_COMMAND_BASE, \
 106                          uint32_t)
 107 #define DRM_IOCTL_PSB_GET_PIPE_FROM_CRTC_ID     \
 108                 DRM_IOWR(DRM_PSB_GET_PIPE_FROM_CRTC_ID + DRM_COMMAND_BASE, \
 109                          struct drm_psb_get_pipe_from_crtc_id_arg)
 110
 111 static int psb_sizes_ioctl(struct drm_device *dev, void *data,
 112                            struct drm_file *file_priv);
 113 static int psb_dc_state_ioctl(struct drm_device *dev, void * data,
 114                               struct drm_file *file_priv);
 115 static int psb_adb_ioctl(struct drm_device *dev, void *data,
 116                          struct drm_file *file_priv);
 117 static int psb_mode_operation_ioctl(struct drm_device *dev, void *data,
 118                                     struct drm_file *file_priv);
 119 static int psb_stolen_memory_ioctl(struct drm_device *dev, void *data,
 120                                    struct drm_file *file_priv);
 121 static int psb_register_rw_ioctl(struct drm_device *dev, void *data,
 122                                  struct drm_file *file_priv);
 123 static int psb_dpst_ioctl(struct drm_device *dev, void *data,
 124                           struct drm_file *file_priv);
 125 static int psb_gamma_ioctl(struct drm_device *dev, void *data,
 126                            struct drm_file *file_priv);
 127 static int psb_dpst_bl_ioctl(struct drm_device *dev, void *data,
 128                              struct drm_file *file_priv);
 129
 130 #define PSB_IOCTL_DEF(ioctl, func, flags) \
 131         [DRM_IOCTL_NR(ioctl) - DRM_COMMAND_BASE] = {ioctl, flags, func}
 132
 133 static struct drm_ioctl_desc psb_ioctls[] = {
 134         PSB_IOCTL_DEF(DRM_IOCTL_PSB_SIZES, psb_sizes_ioctl, DRM_AUTH),
 135         PSB_IOCTL_DEF(DRM_IOCTL_PSB_DC_STATE, psb_dc_state_ioctl, DRM_AUTH),
 136         PSB_IOCTL_DEF(DRM_IOCTL_PSB_ADB, psb_adb_ioctl, DRM_AUTH),
 137         PSB_IOCTL_DEF(DRM_IOCTL_PSB_MODE_OPERATION, psb_mode_operation_ioctl,
 138                       DRM_AUTH),
 139         PSB_IOCTL_DEF(DRM_IOCTL_PSB_STOLEN_MEMORY, psb_stolen_memory_ioctl,
 140                       DRM_AUTH),
 141         PSB_IOCTL_DEF(DRM_IOCTL_PSB_REGISTER_RW, psb_register_rw_ioctl,
 142                       DRM_AUTH),
 143         PSB_IOCTL_DEF(DRM_IOCTL_PSB_DPST, psb_dpst_ioctl, DRM_AUTH),
 144         PSB_IOCTL_DEF(DRM_IOCTL_PSB_GAMMA, psb_gamma_ioctl, DRM_AUTH),
 145         PSB_IOCTL_DEF(DRM_IOCTL_PSB_DPST_BL, psb_dpst_bl_ioctl, DRM_AUTH),
 146         PSB_IOCTL_DEF(DRM_IOCTL_PSB_GET_PIPE_FROM_CRTC_ID,
 147                                         psb_intel_get_pipe_from_crtc_id, 0),
 148
 149 };
 150
 151 static void psb_lastclose(struct drm_device *dev)
 152 {
 153         return;
 154 }
 155
 156 static void psb_do_takedown(struct drm_device *dev)
 157 {
 158         /* FIXME: do we need to clean up the gtt here ? */
 159 }
 160
 161 static int psb_do_init(struct drm_device *dev)
 162 {
 163         struct drm_psb_private *dev_priv =
 164             (struct drm_psb_private *) dev->dev_private;
 165         struct psb_gtt *pg = dev_priv->pg;
 166
 167         uint32_t stolen_gtt;
 168
 169         int ret = -ENOMEM;
 170
 171         if (pg->mmu_gatt_start & 0x0FFFFFFF) {
 172                 dev_err(dev->dev, "Gatt must be 256M aligned. This is a bug.\n");
 173                 ret = -EINVAL;
 174                 goto out_err;
 175         }
 176
 177
 178         stolen_gtt = (pg->stolen_size >> PAGE_SHIFT) * 4;
 179         stolen_gtt = (stolen_gtt + PAGE_SIZE - 1) >> PAGE_SHIFT;
 180         stolen_gtt =
 181             (stolen_gtt < pg->gtt_pages) ? stolen_gtt : pg->gtt_pages;
 182
 183         dev_priv->gatt_free_offset = pg->mmu_gatt_start +
 184             (stolen_gtt << PAGE_SHIFT) * 1024;
 185
 186         if (1 || drm_debug) {
 187                 uint32_t core_id = PSB_RSGX32(PSB_CR_CORE_ID);
 188                 uint32_t core_rev = PSB_RSGX32(PSB_CR_CORE_REVISION);
 189                 DRM_INFO("SGX core id = 0x%08x\n", core_id);
 190                 DRM_INFO("SGX core rev major = 0x%02x, minor = 0x%02x\n",
 191                          (core_rev & _PSB_CC_REVISION_MAJOR_MASK) >>
 192                          _PSB_CC_REVISION_MAJOR_SHIFT,
 193                          (core_rev & _PSB_CC_REVISION_MINOR_MASK) >>
 194                          _PSB_CC_REVISION_MINOR_SHIFT);
 195                 DRM_INFO
 196                     ("SGX core rev maintenance = 0x%02x, designer = 0x%02x\n",
 197                      (core_rev & _PSB_CC_REVISION_MAINTENANCE_MASK) >>
 198                      _PSB_CC_REVISION_MAINTENANCE_SHIFT,
 199                      (core_rev & _PSB_CC_REVISION_DESIGNER_MASK) >>
 200                      _PSB_CC_REVISION_DESIGNER_SHIFT);
 201         }
 202
 203
 204         spin_lock_init(&dev_priv->irqmask_lock);
 205
 206         PSB_WSGX32(0x00000000, PSB_CR_BIF_BANK0);
 207         PSB_WSGX32(0x00000000, PSB_CR_BIF_BANK1);
 208         PSB_RSGX32(PSB_CR_BIF_BANK1);
 209         PSB_WSGX32(PSB_RSGX32(PSB_CR_BIF_CTRL) | _PSB_MMU_ER_MASK,
 210                                                         PSB_CR_BIF_CTRL);
 211         psb_spank(dev_priv);
 212
 213         /* mmu_gatt ?? */
 214         PSB_WSGX32(pg->gatt_start, PSB_CR_BIF_TWOD_REQ_BASE);
 215         return 0;
 216 out_err:
 217         psb_do_takedown(dev);
 218         return ret;
 219 }
 220
 221 static int psb_driver_unload(struct drm_device *dev)
 222 {
 223         struct drm_psb_private *dev_priv = dev->dev_private;
 224
 225         /* Kill vblank etc here */
 226
 227         gma_backlight_exit(dev);
 228
 229         if (drm_psb_no_fb == 0)
 230                 psb_modeset_cleanup(dev);
 231
 232         if (dev_priv) {
 233                 psb_lid_timer_takedown(dev_priv);
 234
 235                 psb_do_takedown(dev);
 236
 237
 238                 if (dev_priv->pf_pd) {
 239                         psb_mmu_free_pagedir(dev_priv->pf_pd);
 240                         dev_priv->pf_pd = NULL;
 241                 }
 242                 if (dev_priv->mmu) {
 243                         struct psb_gtt *pg = dev_priv->pg;
 244
 245                         down_read(&pg->sem);
 246                         psb_mmu_remove_pfn_sequence(
 247                                 psb_mmu_get_default_pd
 248                                 (dev_priv->mmu),
 249                                 pg->mmu_gatt_start,
 250                                 dev_priv->vram_stolen_size >> PAGE_SHIFT);
 251                         up_read(&pg->sem);
 252                         psb_mmu_driver_takedown(dev_priv->mmu);
 253                         dev_priv->mmu = NULL;
 254                 }
 255                 psb_gtt_takedown(dev);
 256                 if (dev_priv->scratch_page) {
 257                         __free_page(dev_priv->scratch_page);
 258                         dev_priv->scratch_page = NULL;
 259                 }
 260                 if (dev_priv->vdc_reg) {
 261                         iounmap(dev_priv->vdc_reg);
 262                         dev_priv->vdc_reg = NULL;
 263                 }
 264                 if (dev_priv->sgx_reg) {
 265                         iounmap(dev_priv->sgx_reg);
 266                         dev_priv->sgx_reg = NULL;
 267                 }
 268
 269                 kfree(dev_priv);
 270                 dev->dev_private = NULL;
 271
 272                 /*destroy VBT data*/
 273                 psb_intel_destroy_bios(dev);
 274         }
 275
 276         gma_power_uninit(dev);
 277
 278         return 0;
 279 }
 280
 281
 282 static int psb_driver_load(struct drm_device *dev, unsigned long chipset)
 283 {
 284         struct drm_psb_private *dev_priv;
 285         unsigned long resource_start;
 286         struct psb_gtt *pg;
 287         unsigned long irqflags;
 288         int ret = -ENOMEM;
 289         uint32_t tt_pages;
 290         struct drm_connector *connector;
 291         struct psb_intel_output *psb_intel_output;
 292
 293         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
 294         if (dev_priv == NULL)
 295                 return -ENOMEM;
 296
 297         dev_priv->ops = (struct psb_ops *)chipset;
 298         dev_priv->dev = dev;
 299         dev->dev_private = (void *) dev_priv;
 300
 301         dev_priv->num_pipe = dev_priv->ops->pipes;
 302
 303         resource_start = pci_resource_start(dev->pdev, PSB_MMIO_RESOURCE);
 304
 305         dev_priv->vdc_reg =
 306             ioremap(resource_start + PSB_VDC_OFFSET, PSB_VDC_SIZE);
 307         if (!dev_priv->vdc_reg)
 308                 goto out_err;
 309
 310         dev_priv->sgx_reg = ioremap(resource_start + dev_priv->ops->sgx_offset,
 311                                                         PSB_SGX_SIZE);
 312         if (!dev_priv->sgx_reg)
 313                 goto out_err;
 314
 315         ret = dev_priv->ops->chip_setup(dev);
 316         if (ret)
 317                 goto out_err;
 318
 319         /* Init OSPM support */
 320         gma_power_init(dev);
 321
 322         ret = -ENOMEM;
 323
 324         dev_priv->scratch_page = alloc_page(GFP_DMA32 | __GFP_ZERO);
 325         if (!dev_priv->scratch_page)
 326                 goto out_err;
 327
 328         set_pages_uc(dev_priv->scratch_page, 1);
 329
 330         ret = psb_gtt_init(dev, 0);
 331         if (ret)
 332                 goto out_err;
 333
 334         dev_priv->mmu = psb_mmu_driver_init((void *)0,
 335                                         drm_psb_trap_pagefaults, 0,
 336                                         dev_priv);
 337         if (!dev_priv->mmu)
 338                 goto out_err;
 339
 340         pg = dev_priv->pg;
 341
 342         tt_pages = (pg->gatt_pages < PSB_TT_PRIV0_PLIMIT) ?
 343                 (pg->gatt_pages) : PSB_TT_PRIV0_PLIMIT;
 344
 345
 346         dev_priv->pf_pd = psb_mmu_alloc_pd(dev_priv->mmu, 1, 0);
 347         if (!dev_priv->pf_pd)
 348                 goto out_err;
 349
 350         psb_mmu_set_pd_context(psb_mmu_get_default_pd(dev_priv->mmu), 0);
 351         psb_mmu_set_pd_context(dev_priv->pf_pd, 1);
 352
 353         ret = psb_do_init(dev);
 354         if (ret)
 355                 return ret;
 356
 357         PSB_WSGX32(0x20000000, PSB_CR_PDS_EXEC_BASE);
 358         PSB_WSGX32(0x30000000, PSB_CR_BIF_3D_REQ_BASE);
 359
 360 /*      igd_opregion_init(&dev_priv->opregion_dev); */
 361         acpi_video_register();
 362         if (dev_priv->lid_state)
 363                 psb_lid_timer_init(dev_priv);
 364
 365         ret = drm_vblank_init(dev, dev_priv->num_pipe);
 366         if (ret)
 367                 goto out_err;
 368
 369         /*
 370          * Install interrupt handlers prior to powering off SGX or else we will
 371          * crash.
 372          */
 373         dev_priv->vdc_irq_mask = 0;
 374         dev_priv->pipestat[0] = 0;
 375         dev_priv->pipestat[1] = 0;
 376         dev_priv->pipestat[2] = 0;
 377         spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
 378         PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
 379         PSB_WVDC32(0x00000000, PSB_INT_ENABLE_R);
 380         PSB_WVDC32(0xFFFFFFFF, PSB_INT_MASK_R);
 381         spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
 382         if (drm_core_check_feature(dev, DRIVER_MODESET))
 383                 drm_irq_install(dev);
 384
 385         dev->vblank_disable_allowed = 1;
 386
 387         dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
 388
 389         dev->driver->get_vblank_counter = psb_get_vblank_counter;
 390
 391         /* FIXME: this is not the right place for this stuff ! */
 392         if (IS_MFLD(dev)) {
 393 #ifdef CONFIG_MDFLD_DSI_DPU
 394                 /*init dpu info*/
 395                 mdfld_dbi_dpu_init(dev);
 396 #else
 397                 mdfld_dbi_dsr_init(dev);
 398 #endif /*CONFIG_MDFLD_DSI_DPU*/
 399                 /* INIT_WORK(&dev_priv->te_work, mdfld_te_handler_work);*/
 400         }
 401
 402         if (drm_psb_no_fb == 0) {
 403                 psb_modeset_init(dev);
 404                 psb_fbdev_init(dev);
 405                 drm_kms_helper_poll_init(dev);
 406         }
 407
 408         /* Only add backlight support if we have LVDS output */
 409         list_for_each_entry(connector, &dev->mode_config.connector_list,
 410                             head) {
 411                 psb_intel_output = to_psb_intel_output(connector);
 412
 413                 switch (psb_intel_output->type) {
 414                 case INTEL_OUTPUT_LVDS:
 415                         ret = gma_backlight_init(dev);
 416                         break;
 417                 }
 418         }
 419
 420         if (ret)
 421                 return ret;
 422 #if 0
 423         /*enable runtime pm at last*/
 424         pm_runtime_enable(&dev->pdev->dev);
 425         pm_runtime_set_active(&dev->pdev->dev);
 426 #endif
 427         /*Intel drm driver load is done, continue doing pvr load*/
 428         return 0;
 429 out_err:
 430         psb_driver_unload(dev);
 431         return ret;
 432 }
 433
 434 int psb_driver_device_is_agp(struct drm_device *dev)
 435 {
 436         return 0;
 437 }
 438
 439
 440 static int psb_sizes_ioctl(struct drm_device *dev, void *data,
 441                            struct drm_file *file_priv)
 442 {
 443         struct drm_psb_private *dev_priv = psb_priv(dev);
 444         struct drm_psb_sizes_arg *arg =
 445                 (struct drm_psb_sizes_arg *) data;
 446
 447         *arg = dev_priv->sizes;
 448         return 0;
 449 }
 450
 451 static int psb_dc_state_ioctl(struct drm_device *dev, void * data,
 452                                 struct drm_file *file_priv)
 453 {
 454         uint32_t flags;
 455         uint32_t obj_id;
 456         struct drm_mode_object *obj;
 457         struct drm_connector *connector;
 458         struct drm_crtc *crtc;
 459         struct drm_psb_dc_state_arg *arg =
 460                 (struct drm_psb_dc_state_arg *)data;
 461
 462
 463         /* Double check MRST case */
 464         if (IS_MRST(dev) || IS_MFLD(dev))
 465                 return -EOPNOTSUPP;
 466
 467         flags = arg->flags;
 468         obj_id = arg->obj_id;
 469
 470         if (flags & PSB_DC_CRTC_MASK) {
 471                 obj = drm_mode_object_find(dev, obj_id,
 472                                 DRM_MODE_OBJECT_CRTC);
 473                 if (!obj) {
 474                         dev_dbg(dev->dev, "Invalid CRTC object.\n");
 475                         return -EINVAL;
 476                 }
 477
 478                 crtc = obj_to_crtc(obj);
 479
 480                 mutex_lock(&dev->mode_config.mutex);
 481                 if (drm_helper_crtc_in_use(crtc)) {
 482                         if (flags & PSB_DC_CRTC_SAVE)
 483                                 crtc->funcs->save(crtc);
 484                         else
 485                                 crtc->funcs->restore(crtc);
 486                 }
 487                 mutex_unlock(&dev->mode_config.mutex);
 488
 489                 return 0;
 490         } else if (flags & PSB_DC_OUTPUT_MASK) {
 491                 obj = drm_mode_object_find(dev, obj_id,
 492                                 DRM_MODE_OBJECT_CONNECTOR);
 493                 if (!obj) {
 494                         dev_dbg(dev->dev, "Invalid connector id.\n");
 495                         return -EINVAL;
 496                 }
 497
 498                 connector = obj_to_connector(obj);
 499                 if (flags & PSB_DC_OUTPUT_SAVE)
 500                         connector->funcs->save(connector);
 501                 else
 502                         connector->funcs->restore(connector);
 503
 504                 return 0;
 505         }
 506         return -EINVAL;
 507 }
 508
 509 static int psb_dpst_bl_ioctl(struct drm_device *dev, void *data,
 510                        struct drm_file *file_priv)
 511 {
 512         struct drm_psb_private *dev_priv = psb_priv(dev);
 513         uint32_t *arg = data;
 514         struct backlight_device *bd = dev_priv->backlight_device;
 515         dev_priv->blc_adj2 = *arg;
 516
 517 #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
 518         if (bd) {
 519                 bd->props.brightness = bd->ops->get_brightness(bd);
 520                 backlight_update_status(bd);
 521         }
 522 #endif
 523         return 0;
 524 }
 525
 526 static int psb_adb_ioctl(struct drm_device *dev, void *data,
 527                         struct drm_file *file_priv)
 528 {
 529         struct drm_psb_private *dev_priv = psb_priv(dev);
 530         uint32_t *arg = data;
 531         struct backlight_device *bd = dev_priv->backlight_device;
 532         dev_priv->blc_adj1 = *arg;
 533
 534 #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
 535         if (bd) {
 536                 bd->props.brightness = bd->ops->get_brightness(bd);
 537                 backlight_update_status(bd);
 538         }
 539 #endif
 540         return 0;
 541 }
 542
 543 /* return the current mode to the dpst module */
 544 static int psb_dpst_ioctl(struct drm_device *dev, void *data,
 545                           struct drm_file *file_priv)
 546 {
 547         struct drm_psb_private *dev_priv = psb_priv(dev);
 548         uint32_t *arg = data;
 549         uint32_t x;
 550         uint32_t y;
 551         uint32_t reg;
 552
 553         if (!gma_power_begin(dev, 0))
 554                 return -EIO;
 555
 556         reg = PSB_RVDC32(PIPEASRC);
 557
 558         gma_power_end(dev);
 559
 560         /* horizontal is the left 16 bits */
 561         x = reg >> 16;
 562         /* vertical is the right 16 bits */
 563         y = reg & 0x0000ffff;
 564
 565         /* the values are the image size minus one */
 566         x++;
 567         y++;
 568
 569         *arg = (x << 16) | y;
 570
 571         return 0;
 572 }
 573 static int psb_gamma_ioctl(struct drm_device *dev, void *data,
 574                            struct drm_file *file_priv)
 575 {
 576         struct drm_psb_dpst_lut_arg *lut_arg = data;
 577         struct drm_mode_object *obj;
 578         struct drm_crtc *crtc;
 579         struct drm_connector *connector;
 580         struct psb_intel_crtc *psb_intel_crtc;
 581         int i = 0;
 582         int32_t obj_id;
 583
 584         obj_id = lut_arg->output_id;
 585         obj = drm_mode_object_find(dev, obj_id, DRM_MODE_OBJECT_CONNECTOR);
 586         if (!obj) {
 587                 dev_dbg(dev->dev, "Invalid Connector object.\n");
 588                 return -EINVAL;
 589         }
 590
 591         connector = obj_to_connector(obj);
 592         crtc = connector->encoder->crtc;
 593         psb_intel_crtc = to_psb_intel_crtc(crtc);
 594
 595         for (i = 0; i < 256; i++)
 596                 psb_intel_crtc->lut_adj[i] = lut_arg->lut[i];
 597
 598         psb_intel_crtc_load_lut(crtc);
 599
 600         return 0;
 601 }
 602
 603 static int psb_mode_operation_ioctl(struct drm_device *dev, void *data,
 604                                 struct drm_file *file_priv)
 605 {
 606         uint32_t obj_id;
 607         uint16_t op;
 608         struct drm_mode_modeinfo *umode;
 609         struct drm_display_mode *mode = NULL;
 610         struct drm_psb_mode_operation_arg *arg;
 611         struct drm_mode_object *obj;
 612         struct drm_connector *connector;
 613         struct drm_framebuffer *drm_fb;
 614         struct psb_framebuffer *psb_fb;
 615         struct drm_connector_helper_funcs *connector_funcs;
 616         int ret = 0;
 617         int resp = MODE_OK;
 618         struct drm_psb_private *dev_priv = psb_priv(dev);
 619
 620         arg = (struct drm_psb_mode_operation_arg *)data;
 621         obj_id = arg->obj_id;
 622         op = arg->operation;
 623
 624         switch (op) {
 625         case PSB_MODE_OPERATION_SET_DC_BASE:
 626                 obj = drm_mode_object_find(dev, obj_id, DRM_MODE_OBJECT_FB);
 627                 if (!obj) {
 628                         dev_dbg(dev->dev, "Invalid FB id %d\n", obj_id);
 629                         return -EINVAL;
 630                 }
 631
 632                 drm_fb = obj_to_fb(obj);
 633                 psb_fb = to_psb_fb(drm_fb);
 634
 635                 if (gma_power_begin(dev, 0)) {
 636                         REG_WRITE(DSPASURF, psb_fb->gtt->offset);
 637                         REG_READ(DSPASURF);
 638                         gma_power_end(dev);
 639                 } else {
 640                         dev_priv->saveDSPASURF = psb_fb->gtt->offset;
 641                 }
 642
 643                 return 0;
 644         case PSB_MODE_OPERATION_MODE_VALID:
 645                 umode = &arg->mode;
 646
 647                 mutex_lock(&dev->mode_config.mutex);
 648
 649                 obj = drm_mode_object_find(dev, obj_id,
 650                                         DRM_MODE_OBJECT_CONNECTOR);
 651                 if (!obj) {
 652                         ret = -EINVAL;
 653                         goto mode_op_out;
 654                 }
 655
 656                 connector = obj_to_connector(obj);
 657
 658                 mode = drm_mode_create(dev);
 659                 if (!mode) {
 660                         ret = -ENOMEM;
 661                         goto mode_op_out;
 662                 }
 663
 664                 /* drm_crtc_convert_umode(mode, umode); */
 665                 {
 666                         mode->clock = umode->clock;
 667                         mode->hdisplay = umode->hdisplay;
 668                         mode->hsync_start = umode->hsync_start;
 669                         mode->hsync_end = umode->hsync_end;
 670                         mode->htotal = umode->htotal;
 671                         mode->hskew = umode->hskew;
 672                         mode->vdisplay = umode->vdisplay;
 673                         mode->vsync_start = umode->vsync_start;
 674                         mode->vsync_end = umode->vsync_end;
 675                         mode->vtotal = umode->vtotal;
 676                         mode->vscan = umode->vscan;
 677                         mode->vrefresh = umode->vrefresh;
 678                         mode->flags = umode->flags;
 679                         mode->type = umode->type;
 680                         strncpy(mode->name, umode->name, DRM_DISPLAY_MODE_LEN);
 681                         mode->name[DRM_DISPLAY_MODE_LEN-1] = 0;
 682                 }
 683
 684                 connector_funcs = (struct drm_connector_helper_funcs *)
 685                                    connector->helper_private;
 686
 687                 if (connector_funcs->mode_valid) {
 688                         resp = connector_funcs->mode_valid(connector, mode);
 689                         arg->data = (void *)resp;
 690                 }
 691
 692                 /*do some clean up work*/
 693                 if (mode)
 694                         drm_mode_destroy(dev, mode);
 695 mode_op_out:
 696                 mutex_unlock(&dev->mode_config.mutex);
 697                 return ret;
 698
 699         default:
 700                 dev_dbg(dev->dev, "Unsupported psb mode operation\n");
 701                 return -EOPNOTSUPP;
 702         }
 703
 704         return 0;
 705 }
 706
 707 static int psb_stolen_memory_ioctl(struct drm_device *dev, void *data,
 708                                    struct drm_file *file_priv)
 709 {
 710         struct drm_psb_private *dev_priv = psb_priv(dev);
 711         struct drm_psb_stolen_memory_arg *arg = data;
 712
 713         arg->base = dev_priv->stolen_base;
 714         arg->size = dev_priv->vram_stolen_size;
 715
 716         return 0;
 717 }
 718
 719 /* FIXME: needs Medfield changes */
 720 static int psb_register_rw_ioctl(struct drm_device *dev, void *data,
 721                                  struct drm_file *file_priv)
 722 {
 723         struct drm_psb_private *dev_priv = psb_priv(dev);
 724         struct drm_psb_register_rw_arg *arg = data;
 725         bool usage = arg->b_force_hw_on ? true : false;
 726
 727         if (arg->display_write_mask != 0) {
 728                 if (gma_power_begin(dev, usage)) {
 729                         if (arg->display_write_mask & REGRWBITS_PFIT_CONTROLS)
 730                                 PSB_WVDC32(arg->display.pfit_controls,
 731                                            PFIT_CONTROL);
 732                         if (arg->display_write_mask &
 733                             REGRWBITS_PFIT_AUTOSCALE_RATIOS)
 734                                 PSB_WVDC32(arg->display.pfit_autoscale_ratios,
 735                                            PFIT_AUTO_RATIOS);
 736                         if (arg->display_write_mask &
 737                             REGRWBITS_PFIT_PROGRAMMED_SCALE_RATIOS)
 738                                 PSB_WVDC32(
 739                                    arg->display.pfit_programmed_scale_ratios,
 740                                    PFIT_PGM_RATIOS);
 741                         if (arg->display_write_mask & REGRWBITS_PIPEASRC)
 742                                 PSB_WVDC32(arg->display.pipeasrc,
 743                                            PIPEASRC);
 744                         if (arg->display_write_mask & REGRWBITS_PIPEBSRC)
 745                                 PSB_WVDC32(arg->display.pipebsrc,
 746                                            PIPEBSRC);
 747                         if (arg->display_write_mask & REGRWBITS_VTOTAL_A)
 748                                 PSB_WVDC32(arg->display.vtotal_a,
 749                                            VTOTAL_A);
 750                         if (arg->display_write_mask & REGRWBITS_VTOTAL_B)
 751                                 PSB_WVDC32(arg->display.vtotal_b,
 752                                            VTOTAL_B);
 753                         gma_power_end(dev);
 754                 } else {
 755                         if (arg->display_write_mask & REGRWBITS_PFIT_CONTROLS)
 756                                 dev_priv->savePFIT_CONTROL =
 757                                                 arg->display.pfit_controls;
 758                         if (arg->display_write_mask &
 759                             REGRWBITS_PFIT_AUTOSCALE_RATIOS)
 760                                 dev_priv->savePFIT_AUTO_RATIOS =
 761                                         arg->display.pfit_autoscale_ratios;
 762                         if (arg->display_write_mask &
 763                             REGRWBITS_PFIT_PROGRAMMED_SCALE_RATIOS)
 764                                 dev_priv->savePFIT_PGM_RATIOS =
 765                                    arg->display.pfit_programmed_scale_ratios;
 766                         if (arg->display_write_mask & REGRWBITS_PIPEASRC)
 767                                 dev_priv->savePIPEASRC = arg->display.pipeasrc;
 768                         if (arg->display_write_mask & REGRWBITS_PIPEBSRC)
 769                                 dev_priv->savePIPEBSRC = arg->display.pipebsrc;
 770                         if (arg->display_write_mask & REGRWBITS_VTOTAL_A)
 771                                 dev_priv->saveVTOTAL_A = arg->display.vtotal_a;
 772                         if (arg->display_write_mask & REGRWBITS_VTOTAL_B)
 773                                 dev_priv->saveVTOTAL_B = arg->display.vtotal_b;
 774                 }
 775         }
 776
 777         if (arg->display_read_mask != 0) {
 778                 if (gma_power_begin(dev, usage)) {
 779                         if (arg->display_read_mask &
 780                             REGRWBITS_PFIT_CONTROLS)
 781                                 arg->display.pfit_controls =
 782                                                 PSB_RVDC32(PFIT_CONTROL);
 783                         if (arg->display_read_mask &
 784                             REGRWBITS_PFIT_AUTOSCALE_RATIOS)
 785                                 arg->display.pfit_autoscale_ratios =
 786                                                 PSB_RVDC32(PFIT_AUTO_RATIOS);
 787                         if (arg->display_read_mask &
 788                             REGRWBITS_PFIT_PROGRAMMED_SCALE_RATIOS)
 789                                 arg->display.pfit_programmed_scale_ratios =
 790                                                 PSB_RVDC32(PFIT_PGM_RATIOS);
 791                         if (arg->display_read_mask & REGRWBITS_PIPEASRC)
 792                                 arg->display.pipeasrc = PSB_RVDC32(PIPEASRC);
 793                         if (arg->display_read_mask & REGRWBITS_PIPEBSRC)
 794                                 arg->display.pipebsrc = PSB_RVDC32(PIPEBSRC);
 795                         if (arg->display_read_mask & REGRWBITS_VTOTAL_A)
 796                                 arg->display.vtotal_a = PSB_RVDC32(VTOTAL_A);
 797                         if (arg->display_read_mask & REGRWBITS_VTOTAL_B)
 798                                 arg->display.vtotal_b = PSB_RVDC32(VTOTAL_B);
 799                         gma_power_end(dev);
 800                 } else {
 801                         if (arg->display_read_mask &
 802                             REGRWBITS_PFIT_CONTROLS)
 803                                 arg->display.pfit_controls =
 804                                                 dev_priv->savePFIT_CONTROL;
 805                         if (arg->display_read_mask &
 806                             REGRWBITS_PFIT_AUTOSCALE_RATIOS)
 807                                 arg->display.pfit_autoscale_ratios =
 808                                                 dev_priv->savePFIT_AUTO_RATIOS;
 809                         if (arg->display_read_mask &
 810                             REGRWBITS_PFIT_PROGRAMMED_SCALE_RATIOS)
 811                                 arg->display.pfit_programmed_scale_ratios =
 812                                                 dev_priv->savePFIT_PGM_RATIOS;
 813                         if (arg->display_read_mask & REGRWBITS_PIPEASRC)
 814                                 arg->display.pipeasrc = dev_priv->savePIPEASRC;
 815                         if (arg->display_read_mask & REGRWBITS_PIPEBSRC)
 816                                 arg->display.pipebsrc = dev_priv->savePIPEBSRC;
 817                         if (arg->display_read_mask & REGRWBITS_VTOTAL_A)
 818                                 arg->display.vtotal_a = dev_priv->saveVTOTAL_A;
 819                         if (arg->display_read_mask & REGRWBITS_VTOTAL_B)
 820                                 arg->display.vtotal_b = dev_priv->saveVTOTAL_B;
 821                 }
 822         }
 823
 824         if (arg->overlay_write_mask != 0) {
 825                 if (gma_power_begin(dev, usage)) {
 826                         if (arg->overlay_write_mask & OV_REGRWBITS_OGAM_ALL) {
 827                                 PSB_WVDC32(arg->overlay.OGAMC5, OV_OGAMC5);
 828                                 PSB_WVDC32(arg->overlay.OGAMC4, OV_OGAMC4);
 829                                 PSB_WVDC32(arg->overlay.OGAMC3, OV_OGAMC3);
 830                                 PSB_WVDC32(arg->overlay.OGAMC2, OV_OGAMC2);
 831                                 PSB_WVDC32(arg->overlay.OGAMC1, OV_OGAMC1);
 832                                 PSB_WVDC32(arg->overlay.OGAMC0, OV_OGAMC0);
 833                         }
 834                         if (arg->overlay_write_mask & OVC_REGRWBITS_OGAM_ALL) {
 835                                 PSB_WVDC32(arg->overlay.OGAMC5, OVC_OGAMC5);
 836                                 PSB_WVDC32(arg->overlay.OGAMC4, OVC_OGAMC4);
 837                                 PSB_WVDC32(arg->overlay.OGAMC3, OVC_OGAMC3);
 838                                 PSB_WVDC32(arg->overlay.OGAMC2, OVC_OGAMC2);
 839                                 PSB_WVDC32(arg->overlay.OGAMC1, OVC_OGAMC1);
 840                                 PSB_WVDC32(arg->overlay.OGAMC0, OVC_OGAMC0);
 841                         }
 842
 843                         if (arg->overlay_write_mask & OV_REGRWBITS_OVADD) {
 844                                 PSB_WVDC32(arg->overlay.OVADD, OV_OVADD);
 845
 846                                 if (arg->overlay.b_wait_vblank) {
 847                                         /* Wait for 20ms.*/
 848                                         unsigned long vblank_timeout = jiffies
 849                                                                 + HZ/50;
 850                                         uint32_t temp;
 851                                         while (time_before_eq(jiffies,
 852                                                         vblank_timeout)) {
 853                                                 temp = PSB_RVDC32(OV_DOVASTA);
 854                                                 if ((temp & (0x1 << 31)) != 0)
 855                                                         break;
 856                                                 cpu_relax();
 857                                         }
 858                                 }
 859                         }
 860                         if (arg->overlay_write_mask & OVC_REGRWBITS_OVADD) {
 861                                 PSB_WVDC32(arg->overlay.OVADD, OVC_OVADD);
 862                                 if (arg->overlay.b_wait_vblank) {
 863                                         /* Wait for 20ms.*/
 864                                         unsigned long vblank_timeout =
 865                                                         jiffies + HZ/50;
 866                                         uint32_t temp;
 867                                         while (time_before_eq(jiffies,
 868                                                         vblank_timeout)) {
 869                                                 temp = PSB_RVDC32(OVC_DOVCSTA);
 870                                                 if ((temp & (0x1 << 31)) != 0)
 871                                                         break;
 872                                                 cpu_relax();
 873                                         }
 874                                 }
 875                         }
 876                         gma_power_end(dev);
 877                 } else {
 878                         if (arg->overlay_write_mask & OV_REGRWBITS_OGAM_ALL) {
 879                                 dev_priv->saveOV_OGAMC5 = arg->overlay.OGAMC5;
 880                                 dev_priv->saveOV_OGAMC4 = arg->overlay.OGAMC4;
 881                                 dev_priv->saveOV_OGAMC3 = arg->overlay.OGAMC3;
 882                                 dev_priv->saveOV_OGAMC2 = arg->overlay.OGAMC2;
 883                                 dev_priv->saveOV_OGAMC1 = arg->overlay.OGAMC1;
 884                                 dev_priv->saveOV_OGAMC0 = arg->overlay.OGAMC0;
 885                         }
 886                         if (arg->overlay_write_mask & OVC_REGRWBITS_OGAM_ALL) {
 887                                 dev_priv->saveOVC_OGAMC5 = arg->overlay.OGAMC5;
 888                                 dev_priv->saveOVC_OGAMC4 = arg->overlay.OGAMC4;
 889                                 dev_priv->saveOVC_OGAMC3 = arg->overlay.OGAMC3;
 890                                 dev_priv->saveOVC_OGAMC2 = arg->overlay.OGAMC2;
 891                                 dev_priv->saveOVC_OGAMC1 = arg->overlay.OGAMC1;
 892                                 dev_priv->saveOVC_OGAMC0 = arg->overlay.OGAMC0;
 893                         }
 894                         if (arg->overlay_write_mask & OV_REGRWBITS_OVADD)
 895                                 dev_priv->saveOV_OVADD = arg->overlay.OVADD;
 896                         if (arg->overlay_write_mask & OVC_REGRWBITS_OVADD)
 897                                 dev_priv->saveOVC_OVADD = arg->overlay.OVADD;
 898                 }
 899         }
 900
 901         if (arg->overlay_read_mask != 0) {
 902                 if (gma_power_begin(dev, usage)) {
 903                         if (arg->overlay_read_mask & OV_REGRWBITS_OGAM_ALL) {
 904                                 arg->overlay.OGAMC5 = PSB_RVDC32(OV_OGAMC5);
 905                                 arg->overlay.OGAMC4 = PSB_RVDC32(OV_OGAMC4);
 906                                 arg->overlay.OGAMC3 = PSB_RVDC32(OV_OGAMC3);
 907                                 arg->overlay.OGAMC2 = PSB_RVDC32(OV_OGAMC2);
 908                                 arg->overlay.OGAMC1 = PSB_RVDC32(OV_OGAMC1);
 909                                 arg->overlay.OGAMC0 = PSB_RVDC32(OV_OGAMC0);
 910                         }
 911                         if (arg->overlay_read_mask & OVC_REGRWBITS_OGAM_ALL) {
 912                                 arg->overlay.OGAMC5 = PSB_RVDC32(OVC_OGAMC5);
 913                                 arg->overlay.OGAMC4 = PSB_RVDC32(OVC_OGAMC4);
 914                                 arg->overlay.OGAMC3 = PSB_RVDC32(OVC_OGAMC3);
 915                                 arg->overlay.OGAMC2 = PSB_RVDC32(OVC_OGAMC2);
 916                                 arg->overlay.OGAMC1 = PSB_RVDC32(OVC_OGAMC1);
 917                                 arg->overlay.OGAMC0 = PSB_RVDC32(OVC_OGAMC0);
 918                         }
 919                         if (arg->overlay_read_mask & OV_REGRWBITS_OVADD)
 920                                 arg->overlay.OVADD = PSB_RVDC32(OV_OVADD);
 921                         if (arg->overlay_read_mask & OVC_REGRWBITS_OVADD)
 922                                 arg->overlay.OVADD = PSB_RVDC32(OVC_OVADD);
 923                         gma_power_end(dev);
 924                 } else {
 925                         if (arg->overlay_read_mask & OV_REGRWBITS_OGAM_ALL) {
 926                                 arg->overlay.OGAMC5 = dev_priv->saveOV_OGAMC5;
 927                                 arg->overlay.OGAMC4 = dev_priv->saveOV_OGAMC4;
 928                                 arg->overlay.OGAMC3 = dev_priv->saveOV_OGAMC3;
 929                                 arg->overlay.OGAMC2 = dev_priv->saveOV_OGAMC2;
 930                                 arg->overlay.OGAMC1 = dev_priv->saveOV_OGAMC1;
 931                                 arg->overlay.OGAMC0 = dev_priv->saveOV_OGAMC0;
 932                         }
 933                         if (arg->overlay_read_mask & OVC_REGRWBITS_OGAM_ALL) {
 934                                 arg->overlay.OGAMC5 = dev_priv->saveOVC_OGAMC5;
 935                                 arg->overlay.OGAMC4 = dev_priv->saveOVC_OGAMC4;
 936                                 arg->overlay.OGAMC3 = dev_priv->saveOVC_OGAMC3;
 937                                 arg->overlay.OGAMC2 = dev_priv->saveOVC_OGAMC2;
 938                                 arg->overlay.OGAMC1 = dev_priv->saveOVC_OGAMC1;
 939                                 arg->overlay.OGAMC0 = dev_priv->saveOVC_OGAMC0;
 940                         }
 941                         if (arg->overlay_read_mask & OV_REGRWBITS_OVADD)
 942                                 arg->overlay.OVADD = dev_priv->saveOV_OVADD;
 943                         if (arg->overlay_read_mask & OVC_REGRWBITS_OVADD)
 944                                 arg->overlay.OVADD = dev_priv->saveOVC_OVADD;
 945                 }
 946         }
 947
 948         if (arg->sprite_enable_mask != 0) {
 949                 if (gma_power_begin(dev, usage)) {
 950                         PSB_WVDC32(0x1F3E, DSPARB);
 951                         PSB_WVDC32(arg->sprite.dspa_control
 952                                         | PSB_RVDC32(DSPACNTR), DSPACNTR);
 953                         PSB_WVDC32(arg->sprite.dspa_key_value, DSPAKEYVAL);
 954                         PSB_WVDC32(arg->sprite.dspa_key_mask, DSPAKEYMASK);
 955                         PSB_WVDC32(PSB_RVDC32(DSPASURF), DSPASURF);
 956                         PSB_RVDC32(DSPASURF);
 957                         PSB_WVDC32(arg->sprite.dspc_control, DSPCCNTR);
 958                         PSB_WVDC32(arg->sprite.dspc_stride, DSPCSTRIDE);
 959                         PSB_WVDC32(arg->sprite.dspc_position, DSPCPOS);
 960                         PSB_WVDC32(arg->sprite.dspc_linear_offset, DSPCLINOFF);
 961                         PSB_WVDC32(arg->sprite.dspc_size, DSPCSIZE);
 962                         PSB_WVDC32(arg->sprite.dspc_surface, DSPCSURF);
 963                         PSB_RVDC32(DSPCSURF);
 964                         gma_power_end(dev);
 965                 }
 966         }
 967
 968         if (arg->sprite_disable_mask != 0) {
 969                 if (gma_power_begin(dev, usage)) {
 970                         PSB_WVDC32(0x3F3E, DSPARB);
 971                         PSB_WVDC32(0x0, DSPCCNTR);
 972                         PSB_WVDC32(arg->sprite.dspc_surface, DSPCSURF);
 973                         PSB_RVDC32(DSPCSURF);
 974                         gma_power_end(dev);
 975                 }
 976         }
 977
 978         if (arg->subpicture_enable_mask != 0) {
 979                 if (gma_power_begin(dev, usage)) {
 980                         uint32_t temp;
 981                         if (arg->subpicture_enable_mask & REGRWBITS_DSPACNTR) {
 982                                 temp =  PSB_RVDC32(DSPACNTR);
 983                                 temp &= ~DISPPLANE_PIXFORMAT_MASK;
 984                                 temp &= ~DISPPLANE_BOTTOM;
 985                                 temp |= DISPPLANE_32BPP;
 986                                 PSB_WVDC32(temp, DSPACNTR);
 987
 988                                 temp =  PSB_RVDC32(DSPABASE);
 989                                 PSB_WVDC32(temp, DSPABASE);
 990                                 PSB_RVDC32(DSPABASE);
 991                                 temp =  PSB_RVDC32(DSPASURF);
 992                                 PSB_WVDC32(temp, DSPASURF);
 993                                 PSB_RVDC32(DSPASURF);
 994                         }
 995                         if (arg->subpicture_enable_mask & REGRWBITS_DSPBCNTR) {
 996                                 temp =  PSB_RVDC32(DSPBCNTR);
 997                                 temp &= ~DISPPLANE_PIXFORMAT_MASK;
 998                                 temp &= ~DISPPLANE_BOTTOM;
 999                                 temp |= DISPPLANE_32BPP;
1000                                 PSB_WVDC32(temp, DSPBCNTR);
1001
1002                                 temp =  PSB_RVDC32(DSPBBASE);
1003                                 PSB_WVDC32(temp, DSPBBASE);
1004                                 PSB_RVDC32(DSPBBASE);
1005                                 temp =  PSB_RVDC32(DSPBSURF);
1006                                 PSB_WVDC32(temp, DSPBSURF);
1007                                 PSB_RVDC32(DSPBSURF);
1008                         }
1009                         if (arg->subpicture_enable_mask & REGRWBITS_DSPCCNTR) {
1010                                 temp =  PSB_RVDC32(DSPCCNTR);
1011                                 temp &= ~DISPPLANE_PIXFORMAT_MASK;
1012                                 temp &= ~DISPPLANE_BOTTOM;
1013                                 temp |= DISPPLANE_32BPP;
1014                                 PSB_WVDC32(temp, DSPCCNTR);
1015
1016                                 temp =  PSB_RVDC32(DSPCBASE);
1017                                 PSB_WVDC32(temp, DSPCBASE);
1018                                 PSB_RVDC32(DSPCBASE);
1019                                 temp =  PSB_RVDC32(DSPCSURF);
1020                                 PSB_WVDC32(temp, DSPCSURF);
1021                                 PSB_RVDC32(DSPCSURF);
1022                         }
1023                         gma_power_end(dev);
1024                 }
1025         }
1026
1027         if (arg->subpicture_disable_mask != 0) {
1028                 if (gma_power_begin(dev, usage)) {
1029                         uint32_t temp;
1030                         if (arg->subpicture_disable_mask & REGRWBITS_DSPACNTR) {
1031                                 temp =  PSB_RVDC32(DSPACNTR);
1032                                 temp &= ~DISPPLANE_PIXFORMAT_MASK;
1033                                 temp |= DISPPLANE_32BPP_NO_ALPHA;
1034                                 PSB_WVDC32(temp, DSPACNTR);
1035
1036                                 temp =  PSB_RVDC32(DSPABASE);
1037                                 PSB_WVDC32(temp, DSPABASE);
1038                                 PSB_RVDC32(DSPABASE);
1039                                 temp =  PSB_RVDC32(DSPASURF);
1040                                 PSB_WVDC32(temp, DSPASURF);
1041                                 PSB_RVDC32(DSPASURF);
1042                         }
1043                         if (arg->subpicture_disable_mask & REGRWBITS_DSPBCNTR) {
1044                                 temp =  PSB_RVDC32(DSPBCNTR);
1045                                 temp &= ~DISPPLANE_PIXFORMAT_MASK;
1046                                 temp |= DISPPLANE_32BPP_NO_ALPHA;
1047                                 PSB_WVDC32(temp, DSPBCNTR);
1048
1049                                 temp =  PSB_RVDC32(DSPBBASE);
1050                                 PSB_WVDC32(temp, DSPBBASE);
1051                                 PSB_RVDC32(DSPBBASE);
1052                                 temp =  PSB_RVDC32(DSPBSURF);
1053                                 PSB_WVDC32(temp, DSPBSURF);
1054                                 PSB_RVDC32(DSPBSURF);
1055                         }
1056                         if (arg->subpicture_disable_mask & REGRWBITS_DSPCCNTR) {
1057                                 temp =  PSB_RVDC32(DSPCCNTR);
1058                                 temp &= ~DISPPLANE_PIXFORMAT_MASK;
1059                                 temp |= DISPPLANE_32BPP_NO_ALPHA;
1060                                 PSB_WVDC32(temp, DSPCCNTR);
1061
1062                                 temp =  PSB_RVDC32(DSPCBASE);
1063                                 PSB_WVDC32(temp, DSPCBASE);
1064                                 PSB_RVDC32(DSPCBASE);
1065                                 temp =  PSB_RVDC32(DSPCSURF);
1066                                 PSB_WVDC32(temp, DSPCSURF);
1067                                 PSB_RVDC32(DSPCSURF);
1068                         }
1069                         gma_power_end(dev);
1070                 }
1071         }
1072
1073         return 0;
1074 }
1075
1076 static int psb_driver_open(struct drm_device *dev, struct drm_file *priv)
1077 {
1078         return 0;
1079 }
1080
1081 static void psb_driver_close(struct drm_device *dev, struct drm_file *priv)
1082 {
1083 }
1084
1085 static long psb_unlocked_ioctl(struct file *filp, unsigned int cmd,
1086                                unsigned long arg)
1087 {
1088         struct drm_file *file_priv = filp->private_data;
1089         struct drm_device *dev = file_priv->minor->dev;
1090         struct drm_psb_private *dev_priv = dev->dev_private;
1091         static unsigned int runtime_allowed;
1092
1093         if (runtime_allowed == 1 && dev_priv->is_lvds_on) {
1094                 runtime_allowed++;
1095                 pm_runtime_allow(&dev->pdev->dev);
1096                 dev_priv->rpm_enabled = 1;
1097         }
1098         return drm_ioctl(filp, cmd, arg);
1099         /* FIXME: do we need to wrap the other side of this */
1100 }
1101
1102
1103 /* When a client dies:
1104  *    - Check for and clean up flipped page state
1105  */
1106 void psb_driver_preclose(struct drm_device *dev, struct drm_file *priv)
1107 {
1108 }
1109
1110 static void psb_remove(struct pci_dev *pdev)
1111 {
1112         struct drm_device *dev = pci_get_drvdata(pdev);
1113         drm_put_dev(dev);
1114 }
1115
1116 static const struct dev_pm_ops psb_pm_ops = {
1117         .runtime_suspend = psb_runtime_suspend,
1118         .runtime_resume = psb_runtime_resume,
1119         .runtime_idle = psb_runtime_idle,
1120 };
1121
1122 static struct vm_operations_struct psb_gem_vm_ops = {
1123         .fault = psb_gem_fault,
1124         .open = drm_gem_vm_open,
1125         .close = drm_gem_vm_close,
1126 };
1127
1128 static struct drm_driver driver = {
1129         .driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | \
1130                            DRIVER_IRQ_VBL | DRIVER_MODESET | DRIVER_GEM ,
1131         .load = psb_driver_load,
1132         .unload = psb_driver_unload,
1133
1134         .ioctls = psb_ioctls,
1135         .num_ioctls = DRM_ARRAY_SIZE(psb_ioctls),
1136         .device_is_agp = psb_driver_device_is_agp,
1137         .irq_preinstall = psb_irq_preinstall,
1138         .irq_postinstall = psb_irq_postinstall,
1139         .irq_uninstall = psb_irq_uninstall,
1140         .irq_handler = psb_irq_handler,
1141         .enable_vblank = psb_enable_vblank,
1142         .disable_vblank = psb_disable_vblank,
1143         .get_vblank_counter = psb_get_vblank_counter,
1144         .lastclose = psb_lastclose,
1145         .open = psb_driver_open,
1146         .preclose = psb_driver_preclose,
1147         .postclose = psb_driver_close,
1148         .reclaim_buffers = drm_core_reclaim_buffers,
1149
1150         .gem_init_object = psb_gem_init_object,
1151         .gem_free_object = psb_gem_free_object,
1152         .gem_vm_ops = &psb_gem_vm_ops,
1153         .dumb_create = psb_gem_dumb_create,
1154         .dumb_map_offset = psb_gem_dumb_map_gtt,
1155         .dumb_destroy = psb_gem_dumb_destroy,
1156
1157         .fops = {
1158                  .owner = THIS_MODULE,
1159                  .open = drm_open,
1160                  .release = drm_release,
1161                  .unlocked_ioctl = psb_unlocked_ioctl,
1162                  .mmap = drm_gem_mmap,
1163                  .poll = drm_poll,
1164                  .fasync = drm_fasync,
1165                  .read = drm_read,
1166          },
1167         .name = DRIVER_NAME,
1168         .desc = DRIVER_DESC,
1169         .date = PSB_DRM_DRIVER_DATE,
1170         .major = PSB_DRM_DRIVER_MAJOR,
1171         .minor = PSB_DRM_DRIVER_MINOR,
1172         .patchlevel = PSB_DRM_DRIVER_PATCHLEVEL
1173 };
1174
1175 static struct pci_driver psb_pci_driver = {
1176         .name = DRIVER_NAME,
1177         .id_table = pciidlist,
1178         .resume = gma_power_resume,
1179         .suspend = gma_power_suspend,
1180         .probe = psb_probe,
1181         .remove = psb_remove,
1182 #ifdef CONFIG_PM
1183         .driver.pm = &psb_pm_ops,
1184 #endif
1185 };
1186
1187 static int psb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1188 {
1189         /* MLD Added this from Inaky's patch */
1190         if (pci_enable_msi(pdev))
1191                 dev_warn(&pdev->dev, "Enable MSI failed!\n");
1192         return drm_get_pci_dev(pdev, ent, &driver);
1193 }
1194
1195 static int __init psb_init(void)
1196 {
1197         return drm_pci_init(&driver, &psb_pci_driver);
1198 }
1199
1200 static void __exit psb_exit(void)
1201 {
1202         drm_pci_exit(&driver, &psb_pci_driver);
1203 }
1204
1205 late_initcall(psb_init);
1206 module_exit(psb_exit);
1207
1208 MODULE_AUTHOR("Alan Cox <alan@linux.intel.com> and others");
1209 MODULE_DESCRIPTION(DRIVER_DESC);
1210 MODULE_LICENSE("GPL");