3 * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
5 * Copyright © 2005 Agere Systems Inc.
9 * Copyright (c) 2011 Mark Einon <mark.einon@gmail.com>
11 *------------------------------------------------------------------------------
15 * This software is provided subject to the following terms and conditions,
16 * which you should read carefully before using the software. Using this
17 * software indicates your acceptance of these terms and conditions. If you do
18 * not agree with these terms and conditions, do not use the software.
20 * Copyright © 2005 Agere Systems Inc.
21 * All rights reserved.
23 * Redistribution and use in source or binary forms, with or without
24 * modifications, are permitted provided that the following conditions are met:
26 * . Redistributions of source code must retain the above copyright notice, this
27 * list of conditions and the following Disclaimer as comments in the code as
28 * well as in the documentation and/or other materials provided with the
31 * . Redistributions in binary form must reproduce the above copyright notice,
32 * this list of conditions and the following Disclaimer in the documentation
33 * and/or other materials provided with the distribution.
35 * . Neither the name of Agere Systems Inc. nor the names of the contributors
36 * may be used to endorse or promote products derived from this software
37 * without specific prior written permission.
41 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
42 * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
43 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
44 * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
45 * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
46 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
47 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
48 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
49 * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
50 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
51 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
56 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
58 #include <linux/pci.h>
59 #include <linux/init.h>
60 #include <linux/module.h>
61 #include <linux/types.h>
62 #include <linux/kernel.h>
64 #include <linux/sched.h>
65 #include <linux/ptrace.h>
66 #include <linux/slab.h>
67 #include <linux/ctype.h>
68 #include <linux/string.h>
69 #include <linux/timer.h>
70 #include <linux/interrupt.h>
72 #include <linux/delay.h>
73 #include <linux/bitops.h>
76 #include <linux/netdevice.h>
77 #include <linux/etherdevice.h>
78 #include <linux/skbuff.h>
79 #include <linux/if_arp.h>
80 #include <linux/ioport.h>
81 #include <linux/crc32.h>
82 #include <linux/random.h>
83 #include <linux/phy.h>
87 MODULE_AUTHOR("Victor Soriano <vjsoriano@agere.com>");
88 MODULE_AUTHOR("Mark Einon <mark.einon@gmail.com>");
89 MODULE_LICENSE("Dual BSD/GPL");
90 MODULE_DESCRIPTION("10/100/1000 Base-T Ethernet Driver for the ET1310 by Agere Systems");
93 #define MAX_NUM_REGISTER_POLLS 1000
94 #define MAX_NUM_WRITE_RETRIES 2
97 #define COUNTER_WRAP_16_BIT 0x10000
98 #define COUNTER_WRAP_12_BIT 0x1000
101 #define INTERNAL_MEM_SIZE 0x400 /* 1024 of internal memory */
102 #define INTERNAL_MEM_RX_OFFSET 0x1FF /* 50% Tx, 50% Rx */
106 * For interrupts, normal running is:
107 * rxdma_xfr_done, phy_interrupt, mac_stat_interrupt,
108 * watchdog_interrupt & txdma_xfer_done
110 * In both cases, when flow control is enabled for either Tx or bi-direction,
111 * we additional enable rx_fbr0_low and rx_fbr1_low, so we know when the
112 * buffer rings are running low.
114 #define INT_MASK_DISABLE 0xffffffff
116 /* NOTE: Masking out MAC_STAT Interrupt for now...
117 * #define INT_MASK_ENABLE 0xfff6bf17
118 * #define INT_MASK_ENABLE_NO_FLOW 0xfff6bfd7
120 #define INT_MASK_ENABLE 0xfffebf17
121 #define INT_MASK_ENABLE_NO_FLOW 0xfffebfd7
123 /* General defines */
124 /* Packet and header sizes */
125 #define NIC_MIN_PACKET_SIZE 60
127 /* Multicast list size */
128 #define NIC_MAX_MCAST_LIST 128
130 /* Supported Filters */
131 #define ET131X_PACKET_TYPE_DIRECTED 0x0001
132 #define ET131X_PACKET_TYPE_MULTICAST 0x0002
133 #define ET131X_PACKET_TYPE_BROADCAST 0x0004
134 #define ET131X_PACKET_TYPE_PROMISCUOUS 0x0008
135 #define ET131X_PACKET_TYPE_ALL_MULTICAST 0x0010
138 #define ET131X_TX_TIMEOUT (1 * HZ)
139 #define NIC_SEND_HANG_THRESHOLD 0
142 #define fMP_DEST_MULTI 0x00000001
143 #define fMP_DEST_BROAD 0x00000002
145 /* MP_ADAPTER flags */
146 #define fMP_ADAPTER_RECV_LOOKASIDE 0x00000004
147 #define fMP_ADAPTER_INTERRUPT_IN_USE 0x00000008
149 /* MP_SHARED flags */
150 #define fMP_ADAPTER_LOWER_POWER 0x00200000
152 #define fMP_ADAPTER_NON_RECOVER_ERROR 0x00800000
153 #define fMP_ADAPTER_HARDWARE_ERROR 0x04000000
155 #define fMP_ADAPTER_FAIL_SEND_MASK 0x3ff00000
157 /* Some offsets in PCI config space that are actually used. */
158 #define ET1310_PCI_MAC_ADDRESS 0xA4
159 #define ET1310_PCI_EEPROM_STATUS 0xB2
160 #define ET1310_PCI_ACK_NACK 0xC0
161 #define ET1310_PCI_REPLAY 0xC2
162 #define ET1310_PCI_L0L1LATENCY 0xCF
164 /* PCI Product IDs */
165 #define ET131X_PCI_DEVICE_ID_GIG 0xED00 /* ET1310 1000 Base-T 8 */
166 #define ET131X_PCI_DEVICE_ID_FAST 0xED01 /* ET1310 100 Base-T */
168 /* Define order of magnitude converter */
169 #define NANO_IN_A_MICRO 1000
171 #define PARM_RX_NUM_BUFS_DEF 4
172 #define PARM_RX_TIME_INT_DEF 10
173 #define PARM_RX_MEM_END_DEF 0x2bc
174 #define PARM_TX_TIME_INT_DEF 40
175 #define PARM_TX_NUM_BUFS_DEF 4
176 #define PARM_DMA_CACHE_DEF 0
179 #define FBR_CHUNKS 32
180 #define MAX_DESC_PER_RING_RX 1024
182 /* number of RFDs - default and min */
183 #define RFD_LOW_WATER_MARK 40
184 #define NIC_DEFAULT_NUM_RFD 1024
187 #define NIC_MIN_NUM_RFD 64
188 #define NUM_PACKETS_HANDLED 256
190 #define ALCATEL_MULTICAST_PKT 0x01000000
191 #define ALCATEL_BROADCAST_PKT 0x02000000
193 /* typedefs for Free Buffer Descriptors */
197 u32 word2; /* Bits 10-31 reserved, 0-9 descriptor */
200 /* Packet Status Ring Descriptors
204 * top 16 bits are from the Alcatel Status Word as enumerated in
205 * PE-MCXMAC Data Sheet IPD DS54 0210-1 (also IPD-DS80 0205-2)
208 * 1: ipa IP checksum assist
209 * 2: ipp IP checksum pass
210 * 3: tcpa TCP checksum assist
211 * 4: tcpp TCP checksum pass
213 * 6: rxmac_error RXMAC Error Indicator
214 * 7: drop Drop packet
215 * 8: ft Frame Truncated
219 * 16: asw_prev_pkt_dropped e.g. IFG too small on previous
220 * 17: asw_RX_DV_event short receive event detected
221 * 18: asw_false_carrier_event bad carrier since last good packet
222 * 19: asw_code_err one or more nibbles signalled as errors
223 * 20: asw_CRC_err CRC error
224 * 21: asw_len_chk_err frame length field incorrect
225 * 22: asw_too_long frame length > 1518 bytes
226 * 23: asw_OK valid CRC + no code error
227 * 24: asw_multicast has a multicast address
228 * 25: asw_broadcast has a broadcast address
229 * 26: asw_dribble_nibble spurious bits after EOP
230 * 27: asw_control_frame is a control frame
231 * 28: asw_pause_frame is a pause frame
232 * 29: asw_unsupported_op unsupported OP code
233 * 30: asw_VLAN_tag VLAN tag detected
234 * 31: asw_long_evt Rx long event
237 * 0-15: length length in bytes
238 * 16-25: bi Buffer Index
239 * 26-27: ri Ring Index
243 struct pkt_stat_desc {
248 /* Typedefs for the RX DMA status word */
251 * rx status word 0 holds part of the status bits of the Rx DMA engine
252 * that get copied out to memory by the ET-1310. Word 0 is a 32 bit word
253 * which contains the Free Buffer ring 0 and 1 available offset.
255 * bit 0-9 FBR1 offset
256 * bit 10 Wrap flag for FBR1
257 * bit 16-25 FBR0 offset
258 * bit 26 Wrap flag for FBR0
262 * RXSTAT_WORD1_t structure holds part of the status bits of the Rx DMA engine
263 * that get copied out to memory by the ET-1310. Word 3 is a 32 bit word
264 * which contains the Packet Status Ring available offset.
267 * bit 16-27 PSRoffset
273 * struct rx_status_block is a structure representing the status of the Rx
274 * DMA engine it sits in free memory, and is pointed to by 0x101c / 0x1020
276 struct rx_status_block {
282 * Structure for look-up table holding free buffer ring pointers, addresses
286 void *virt[MAX_DESC_PER_RING_RX];
287 void *buffer1[MAX_DESC_PER_RING_RX];
288 void *buffer2[MAX_DESC_PER_RING_RX];
289 u32 bus_high[MAX_DESC_PER_RING_RX];
290 u32 bus_low[MAX_DESC_PER_RING_RX];
292 dma_addr_t ring_physaddr;
293 void *mem_virtaddrs[MAX_DESC_PER_RING_RX / FBR_CHUNKS];
294 dma_addr_t mem_physaddrs[MAX_DESC_PER_RING_RX / FBR_CHUNKS];
302 * struct rx_ring is the sructure representing the adaptor's local
303 * reference(s) to the rings
305 ******************************************************************************
306 * IMPORTANT NOTE :- fbr_lookup *fbr[NUM_FBRS] uses index 0 to refer to FBR1
307 * and index 1 to refer to FRB0
308 ******************************************************************************
311 struct fbr_lookup *fbr[NUM_FBRS];
312 void *ps_ring_virtaddr;
313 dma_addr_t ps_ring_physaddr;
317 struct rx_status_block *rx_status_block;
318 dma_addr_t rx_status_bus;
321 struct list_head recv_list;
326 bool unfinished_receives;
328 /* lookaside lists */
329 struct kmem_cache *recv_lookaside;
334 * word 2 of the control bits in the Tx Descriptor ring for the ET-1310
336 * 0-15: length of packet
339 * 29-31: VLAN priority
341 * word 3 of the control bits in the Tx Descriptor ring for the ET-1310
343 * 0: last packet in the sequence
344 * 1: first packet in the sequence
345 * 2: interrupt the processor when this pkt sent
346 * 3: Control word - no packet data
347 * 4: Issue half-duplex backpressure : XON/XOFF
348 * 5: send pause frame
349 * 6: Tx frame has error
353 * 10: Packet is a Huge packet
354 * 11: append VLAN tag
355 * 12: IP checksum assist
356 * 13: TCP checksum assist
357 * 14: UDP checksum assist
360 /* struct tx_desc represents each descriptor on the ring */
364 u32 len_vlan; /* control words how to xmit the */
365 u32 flags; /* data (detailed above) */
369 * The status of the Tx DMA engine it sits in free memory, and is pointed to
370 * by 0x101c / 0x1020. This is a DMA10 type
373 /* TCB (Transmit Control Block: Host Side) */
375 struct tcb *next; /* Next entry in ring */
376 u32 flags; /* Our flags for the packet */
377 u32 count; /* Used to spot stuck/lost packets */
378 u32 stale; /* Used to spot stuck/lost packets */
379 struct sk_buff *skb; /* Network skb we are tied to */
380 u32 index; /* Ring indexes */
384 /* Structure representing our local reference(s) to the ring */
386 /* TCB (Transmit Control Block) memory and lists */
387 struct tcb *tcb_ring;
389 /* List of TCBs that are ready to be used */
390 struct tcb *tcb_qhead;
391 struct tcb *tcb_qtail;
393 /* list of TCBs that are currently being sent. NOTE that access to all
394 * three of these (including used) are controlled via the
395 * TCBSendQLock. This lock should be secured prior to incementing /
396 * decrementing used, or any queue manipulation on send_head /
399 struct tcb *send_head;
400 struct tcb *send_tail;
403 /* The actual descriptor ring */
404 struct tx_desc *tx_desc_ring;
405 dma_addr_t tx_desc_ring_pa;
407 /* send_idx indicates where we last wrote to in the descriptor ring. */
410 /* The location of the write-back status block */
412 dma_addr_t tx_status_pa;
414 /* Packets since the last IRQ: used for interrupt coalescing */
419 * Do not change these values: if changed, then change also in respective
420 * TXdma and Rxdma engines
422 #define NUM_DESC_PER_RING_TX 512 /* TX Do not change these values */
426 * These values are all superseded by registry entries to facilitate tuning.
427 * Once the desired performance has been achieved, the optimal registry values
428 * should be re-populated to these #defines:
430 #define TX_ERROR_PERIOD 1000
432 #define LO_MARK_PERCENT_FOR_PSR 15
433 #define LO_MARK_PERCENT_FOR_RX 15
435 /* RFD (Receive Frame Descriptor) */
437 struct list_head list_node;
439 u32 len; /* total size of receive frame */
446 #define FLOW_TXONLY 1
447 #define FLOW_RXONLY 2
450 /* Struct to define some device statistics */
454 * NOTE: atomic_t types are only guaranteed to store 24-bits; if we
455 * MUST have 32, then we'll need another way to perform atomic
458 u32 unicast_pkts_rcvd;
459 atomic_t unicast_pkts_xmtd;
460 u32 multicast_pkts_rcvd;
461 atomic_t multicast_pkts_xmtd;
462 u32 broadcast_pkts_rcvd;
463 atomic_t broadcast_pkts_xmtd;
464 u32 rcvd_pkts_dropped;
470 u32 tx_excessive_collisions;
471 u32 tx_first_collisions;
472 u32 tx_late_collisions;
482 u32 rx_code_violations;
485 u32 synchronous_iterations;
486 u32 interrupt_status;
489 /* The private adapter structure */
490 struct et131x_adapter {
491 struct net_device *netdev;
492 struct pci_dev *pdev;
493 struct mii_bus *mii_bus;
494 struct phy_device *phydev;
495 struct work_struct task;
497 /* Flags that indicate current state of the adapter */
500 /* local link state, to determine if a state change has occurred */
504 u8 rom_addr[ETH_ALEN];
512 spinlock_t tcb_send_qlock;
513 spinlock_t tcb_ready_qlock;
514 spinlock_t send_hw_lock;
517 spinlock_t rcv_pend_lock;
522 /* Packet Filter and look ahead size */
526 u32 multicast_addr_count;
527 u8 multicast_list[NIC_MAX_MCAST_LIST][ETH_ALEN];
529 /* Pointer to the device's PCI register space */
530 struct address_map __iomem *regs;
532 /* Registry parameters */
533 u8 wanted_flow; /* Flow we want for 802.3x flow control */
534 u32 registry_jumbo_packet; /* Max supported ethernet packet size */
536 /* Derived from the registry: */
537 u8 flowcontrol; /* flow control validated by the far-end */
539 /* Minimize init-time */
540 struct timer_list error_timer;
542 /* variable putting the phy into coma mode when boot up with no cable
543 * plugged in after 5 seconds
547 /* Next two used to save power information at power down. This
548 * information will be used during power up to set up parts of Power
549 * Management in JAGCore
554 /* Tx Memory Variables */
555 struct tx_ring tx_ring;
557 /* Rx Memory Variables */
558 struct rx_ring rx_ring;
561 struct ce_stats stats;
563 struct net_device_stats net_stats;
566 static int eeprom_wait_ready(struct pci_dev *pdev, u32 *status)
572 * 1. Check LBCIF Status Register for bits 6 & 3:2 all equal to 0 and
573 * bits 7,1:0 both equal to 1, at least once after reset.
574 * Subsequent operations need only to check that bits 1:0 are equal
575 * to 1 prior to starting a single byte read/write
578 for (i = 0; i < MAX_NUM_REGISTER_POLLS; i++) {
579 /* Read registers grouped in DWORD1 */
580 if (pci_read_config_dword(pdev, LBCIF_DWORD1_GROUP, ®))
583 /* I2C idle and Phy Queue Avail both true */
584 if ((reg & 0x3000) == 0x3000) {
595 * eeprom_write - Write a byte to the ET1310's EEPROM
596 * @adapter: pointer to our private adapter structure
597 * @addr: the address to write
598 * @data: the value to write
600 * Returns 1 for a successful write.
602 static int eeprom_write(struct et131x_adapter *adapter, u32 addr, u8 data)
604 struct pci_dev *pdev = adapter->pdev;
614 * For an EEPROM, an I2C single byte write is defined as a START
615 * condition followed by the device address, EEPROM address, one byte
616 * of data and a STOP condition. The STOP condition will trigger the
617 * EEPROM's internally timed write cycle to the nonvolatile memory.
618 * All inputs are disabled during this write cycle and the EEPROM will
619 * not respond to any access until the internal write is complete.
622 err = eeprom_wait_ready(pdev, NULL);
627 * 2. Write to the LBCIF Control Register: bit 7=1, bit 6=1, bit 3=0,
628 * and bits 1:0 both =0. Bit 5 should be set according to the
629 * type of EEPROM being accessed (1=two byte addressing, 0=one
632 if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER,
633 LBCIF_CONTROL_LBCIF_ENABLE | LBCIF_CONTROL_I2C_WRITE))
638 /* Prepare EEPROM address for Step 3 */
640 for (retries = 0; retries < MAX_NUM_WRITE_RETRIES; retries++) {
641 /* Write the address to the LBCIF Address Register */
642 if (pci_write_config_dword(pdev, LBCIF_ADDRESS_REGISTER, addr))
645 * Write the data to the LBCIF Data Register (the I2C write
648 if (pci_write_config_byte(pdev, LBCIF_DATA_REGISTER, data))
651 * Monitor bit 1:0 of the LBCIF Status Register. When bits
652 * 1:0 are both equal to 1, the I2C write has completed and the
653 * internal write cycle of the EEPROM is about to start.
654 * (bits 1:0 = 01 is a legal state while waiting from both
655 * equal to 1, but bits 1:0 = 10 is invalid and implies that
656 * something is broken).
658 err = eeprom_wait_ready(pdev, &status);
663 * Check bit 3 of the LBCIF Status Register. If equal to 1,
664 * an error has occurred.Don't break here if we are revision
665 * 1, this is so we do a blind write for load bug.
667 if ((status & LBCIF_STATUS_GENERAL_ERROR)
668 && adapter->pdev->revision == 0)
672 * Check bit 2 of the LBCIF Status Register. If equal to 1 an
673 * ACK error has occurred on the address phase of the write.
674 * This could be due to an actual hardware failure or the
675 * EEPROM may still be in its internal write cycle from a
676 * previous write. This write operation was ignored and must be
679 if (status & LBCIF_STATUS_ACK_ERROR) {
681 * This could be due to an actual hardware failure
682 * or the EEPROM may still be in its internal write
683 * cycle from a previous write. This write operation
684 * was ignored and must be repeated later.
695 * Set bit 6 of the LBCIF Control Register = 0.
700 if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER,
701 LBCIF_CONTROL_LBCIF_ENABLE))
704 /* Do read until internal ACK_ERROR goes away meaning write
708 pci_write_config_dword(pdev,
709 LBCIF_ADDRESS_REGISTER,
712 pci_read_config_dword(pdev,
713 LBCIF_DATA_REGISTER, &val);
714 } while ((val & 0x00010000) == 0);
715 } while (val & 0x00040000);
717 if ((val & 0xFF00) != 0xC000 || index == 10000)
721 return writeok ? 0 : -EIO;
725 * eeprom_read - Read a byte from the ET1310's EEPROM
726 * @adapter: pointer to our private adapter structure
727 * @addr: the address from which to read
728 * @pdata: a pointer to a byte in which to store the value of the read
729 * @eeprom_id: the ID of the EEPROM
730 * @addrmode: how the EEPROM is to be accessed
732 * Returns 1 for a successful read
734 static int eeprom_read(struct et131x_adapter *adapter, u32 addr, u8 *pdata)
736 struct pci_dev *pdev = adapter->pdev;
741 * A single byte read is similar to the single byte write, with the
742 * exception of the data flow:
745 err = eeprom_wait_ready(pdev, NULL);
749 * Write to the LBCIF Control Register: bit 7=1, bit 6=0, bit 3=0,
750 * and bits 1:0 both =0. Bit 5 should be set according to the type
751 * of EEPROM being accessed (1=two byte addressing, 0=one byte
754 if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER,
755 LBCIF_CONTROL_LBCIF_ENABLE))
758 * Write the address to the LBCIF Address Register (I2C read will
761 if (pci_write_config_dword(pdev, LBCIF_ADDRESS_REGISTER, addr))
764 * Monitor bit 0 of the LBCIF Status Register. When = 1, I2C read
765 * is complete. (if bit 1 =1 and bit 0 stays = 0, a hardware failure
768 err = eeprom_wait_ready(pdev, &status);
772 * Regardless of error status, read data byte from LBCIF Data
777 * Check bit 2 of the LBCIF Status Register. If = 1,
778 * then an error has occurred.
780 return (status & LBCIF_STATUS_ACK_ERROR) ? -EIO : 0;
783 static int et131x_init_eeprom(struct et131x_adapter *adapter)
785 struct pci_dev *pdev = adapter->pdev;
788 /* We first need to check the EEPROM Status code located at offset
789 * 0xB2 of config space
791 pci_read_config_byte(pdev, ET1310_PCI_EEPROM_STATUS,
794 /* THIS IS A WORKAROUND:
795 * I need to call this function twice to get my card in a
796 * LG M1 Express Dual running. I tried also a msleep before this
797 * function, because I thought there could be some time condidions
798 * but it didn't work. Call the whole function twice also work.
800 if (pci_read_config_byte(pdev, ET1310_PCI_EEPROM_STATUS, &eestatus)) {
802 "Could not read PCI config space for EEPROM Status\n");
806 /* Determine if the error(s) we care about are present. If they are
807 * present we need to fail.
809 if (eestatus & 0x4C) {
810 int write_failed = 0;
811 if (pdev->revision == 0x01) {
813 static const u8 eedata[4] = { 0xFE, 0x13, 0x10, 0xFF };
815 /* Re-write the first 4 bytes if we have an eeprom
816 * present and the revision id is 1, this fixes the
817 * corruption seen with 1310 B Silicon
819 for (i = 0; i < 3; i++)
820 if (eeprom_write(adapter, i, eedata[i]) < 0)
823 if (pdev->revision != 0x01 || write_failed) {
825 "Fatal EEPROM Status Error - 0x%04x\n", eestatus);
827 /* This error could mean that there was an error
828 * reading the eeprom or that the eeprom doesn't exist.
829 * We will treat each case the same and not try to
830 * gather additional information that normally would
831 * come from the eeprom, like MAC Address
833 adapter->has_eeprom = 0;
837 adapter->has_eeprom = 1;
839 /* Read the EEPROM for information regarding LED behavior. Refer to
840 * ET1310_phy.c, et131x_xcvr_init(), for its use.
842 eeprom_read(adapter, 0x70, &adapter->eeprom_data[0]);
843 eeprom_read(adapter, 0x71, &adapter->eeprom_data[1]);
845 if (adapter->eeprom_data[0] != 0xcd)
846 /* Disable all optional features */
847 adapter->eeprom_data[1] = 0x00;
853 * et131x_rx_dma_enable - re-start of Rx_DMA on the ET1310.
854 * @adapter: pointer to our adapter structure
856 static void et131x_rx_dma_enable(struct et131x_adapter *adapter)
858 /* Setup the receive dma configuration register for normal operation */
859 u32 csr = 0x2000; /* FBR1 enable */
861 if (adapter->rx_ring.fbr[0]->buffsize == 4096)
863 else if (adapter->rx_ring.fbr[0]->buffsize == 8192)
865 else if (adapter->rx_ring.fbr[0]->buffsize == 16384)
868 csr |= 0x0400; /* FBR0 enable */
869 if (adapter->rx_ring.fbr[1]->buffsize == 256)
871 else if (adapter->rx_ring.fbr[1]->buffsize == 512)
873 else if (adapter->rx_ring.fbr[1]->buffsize == 1024)
875 writel(csr, &adapter->regs->rxdma.csr);
877 csr = readl(&adapter->regs->rxdma.csr);
878 if ((csr & 0x00020000) != 0) {
880 csr = readl(&adapter->regs->rxdma.csr);
881 if ((csr & 0x00020000) != 0) {
882 dev_err(&adapter->pdev->dev,
883 "RX Dma failed to exit halt state. CSR 0x%08x\n",
890 * et131x_rx_dma_disable - Stop of Rx_DMA on the ET1310
891 * @adapter: pointer to our adapter structure
893 static void et131x_rx_dma_disable(struct et131x_adapter *adapter)
896 /* Setup the receive dma configuration register */
897 writel(0x00002001, &adapter->regs->rxdma.csr);
898 csr = readl(&adapter->regs->rxdma.csr);
899 if ((csr & 0x00020000) == 0) { /* Check halt status (bit 17) */
901 csr = readl(&adapter->regs->rxdma.csr);
902 if ((csr & 0x00020000) == 0)
903 dev_err(&adapter->pdev->dev,
904 "RX Dma failed to enter halt state. CSR 0x%08x\n",
910 * et131x_tx_dma_enable - re-start of Tx_DMA on the ET1310.
911 * @adapter: pointer to our adapter structure
913 * Mainly used after a return to the D0 (full-power) state from a lower state.
915 static void et131x_tx_dma_enable(struct et131x_adapter *adapter)
917 /* Setup the transmit dma configuration register for normal
920 writel(ET_TXDMA_SNGL_EPKT|(PARM_DMA_CACHE_DEF << ET_TXDMA_CACHE_SHIFT),
921 &adapter->regs->txdma.csr);
924 static inline void add_10bit(u32 *v, int n)
926 *v = INDEX10(*v + n) | (*v & ET_DMA10_WRAP);
929 static inline void add_12bit(u32 *v, int n)
931 *v = INDEX12(*v + n) | (*v & ET_DMA12_WRAP);
935 * et1310_config_mac_regs1 - Initialize the first part of MAC regs
936 * @adapter: pointer to our adapter structure
938 static void et1310_config_mac_regs1(struct et131x_adapter *adapter)
940 struct mac_regs __iomem *macregs = &adapter->regs->mac;
945 /* First we need to reset everything. Write to MAC configuration
946 * register 1 to perform reset.
948 writel(0xC00F0000, ¯egs->cfg1);
950 /* Next lets configure the MAC Inter-packet gap register */
951 ipg = 0x38005860; /* IPG1 0x38 IPG2 0x58 B2B 0x60 */
952 ipg |= 0x50 << 8; /* ifg enforce 0x50 */
953 writel(ipg, ¯egs->ipg);
955 /* Next lets configure the MAC Half Duplex register */
956 /* BEB trunc 0xA, Ex Defer, Rexmit 0xF Coll 0x37 */
957 writel(0x00A1F037, ¯egs->hfdp);
959 /* Next lets configure the MAC Interface Control register */
960 writel(0, ¯egs->if_ctrl);
962 /* Let's move on to setting up the mii management configuration */
963 writel(0x07, ¯egs->mii_mgmt_cfg); /* Clock reset 0x7 */
965 /* Next lets configure the MAC Station Address register. These
966 * values are read from the EEPROM during initialization and stored
967 * in the adapter structure. We write what is stored in the adapter
968 * structure to the MAC Station Address registers high and low. This
969 * station address is used for generating and checking pause control
972 station2 = (adapter->addr[1] << ET_MAC_STATION_ADDR2_OC2_SHIFT) |
973 (adapter->addr[0] << ET_MAC_STATION_ADDR2_OC1_SHIFT);
974 station1 = (adapter->addr[5] << ET_MAC_STATION_ADDR1_OC6_SHIFT) |
975 (adapter->addr[4] << ET_MAC_STATION_ADDR1_OC5_SHIFT) |
976 (adapter->addr[3] << ET_MAC_STATION_ADDR1_OC4_SHIFT) |
978 writel(station1, ¯egs->station_addr_1);
979 writel(station2, ¯egs->station_addr_2);
981 /* Max ethernet packet in bytes that will be passed by the mac without
982 * being truncated. Allow the MAC to pass 4 more than our max packet
983 * size. This is 4 for the Ethernet CRC.
985 * Packets larger than (registry_jumbo_packet) that do not contain a
986 * VLAN ID will be dropped by the Rx function.
988 writel(adapter->registry_jumbo_packet + 4, ¯egs->max_fm_len);
990 /* clear out MAC config reset */
991 writel(0, ¯egs->cfg1);
995 * et1310_config_mac_regs2 - Initialize the second part of MAC regs
996 * @adapter: pointer to our adapter structure
998 static void et1310_config_mac_regs2(struct et131x_adapter *adapter)
1001 struct mac_regs __iomem *mac = &adapter->regs->mac;
1002 struct phy_device *phydev = adapter->phydev;
1008 ctl = readl(&adapter->regs->txmac.ctl);
1009 cfg1 = readl(&mac->cfg1);
1010 cfg2 = readl(&mac->cfg2);
1011 ifctrl = readl(&mac->if_ctrl);
1013 /* Set up the if mode bits */
1015 if (phydev && phydev->speed == SPEED_1000) {
1018 ifctrl &= ~(1 << 24);
1021 ifctrl |= (1 << 24);
1024 /* We need to enable Rx/Tx */
1025 cfg1 |= CFG1_RX_ENABLE | CFG1_TX_ENABLE | CFG1_TX_FLOW;
1026 /* Initialize loop back to off */
1027 cfg1 &= ~(CFG1_LOOPBACK | CFG1_RX_FLOW);
1028 if (adapter->flowcontrol == FLOW_RXONLY ||
1029 adapter->flowcontrol == FLOW_BOTH)
1030 cfg1 |= CFG1_RX_FLOW;
1031 writel(cfg1, &mac->cfg1);
1033 /* Now we need to initialize the MAC Configuration 2 register */
1034 /* preamble 7, check length, huge frame off, pad crc, crc enable
1039 /* Turn on duplex if needed */
1040 if (phydev && phydev->duplex == DUPLEX_FULL)
1043 ifctrl &= ~(1 << 26);
1044 if (phydev && phydev->duplex == DUPLEX_HALF)
1045 ifctrl |= (1<<26); /* Enable ghd */
1047 writel(ifctrl, &mac->if_ctrl);
1048 writel(cfg2, &mac->cfg2);
1053 cfg1 = readl(&mac->cfg1);
1054 } while ((cfg1 & CFG1_WAIT) != CFG1_WAIT && delay < 100);
1057 dev_warn(&adapter->pdev->dev,
1058 "Syncd bits did not respond correctly cfg1 word 0x%08x\n",
1063 ctl |= 0x09; /* TX mac enable, FC disable */
1064 writel(ctl, &adapter->regs->txmac.ctl);
1066 /* Ready to start the RXDMA/TXDMA engine */
1067 if (adapter->flags & fMP_ADAPTER_LOWER_POWER) {
1068 et131x_rx_dma_enable(adapter);
1069 et131x_tx_dma_enable(adapter);
1074 * et1310_in_phy_coma - check if the device is in phy coma
1075 * @adapter: pointer to our adapter structure
1077 * Returns 0 if the device is not in phy coma, 1 if it is in phy coma
1079 static int et1310_in_phy_coma(struct et131x_adapter *adapter)
1083 pmcsr = readl(&adapter->regs->global.pm_csr);
1085 return ET_PM_PHY_SW_COMA & pmcsr ? 1 : 0;
1088 static void et1310_setup_device_for_multicast(struct et131x_adapter *adapter)
1090 struct rxmac_regs __iomem *rxmac = &adapter->regs->rxmac;
1097 /* If ET131X_PACKET_TYPE_MULTICAST is specified, then we provision
1098 * the multi-cast LIST. If it is NOT specified, (and "ALL" is not
1099 * specified) then we should pass NO multi-cast addresses to the
1102 if (adapter->packet_filter & ET131X_PACKET_TYPE_MULTICAST) {
1105 /* Loop through our multicast array and set up the device */
1106 for (i = 0; i < adapter->multicast_addr_count; i++) {
1109 result = ether_crc(6, adapter->multicast_list[i]);
1111 result = (result & 0x3F800000) >> 23;
1114 hash1 |= (1 << result);
1115 } else if ((31 < result) && (result < 64)) {
1117 hash2 |= (1 << result);
1118 } else if ((63 < result) && (result < 96)) {
1120 hash3 |= (1 << result);
1123 hash4 |= (1 << result);
1128 /* Write out the new hash to the device */
1129 pm_csr = readl(&adapter->regs->global.pm_csr);
1130 if (!et1310_in_phy_coma(adapter)) {
1131 writel(hash1, &rxmac->multi_hash1);
1132 writel(hash2, &rxmac->multi_hash2);
1133 writel(hash3, &rxmac->multi_hash3);
1134 writel(hash4, &rxmac->multi_hash4);
1138 static void et1310_setup_device_for_unicast(struct et131x_adapter *adapter)
1140 struct rxmac_regs __iomem *rxmac = &adapter->regs->rxmac;
1146 /* Set up unicast packet filter reg 3 to be the first two octets of
1147 * the MAC address for both address
1149 * Set up unicast packet filter reg 2 to be the octets 2 - 5 of the
1150 * MAC address for second address
1152 * Set up unicast packet filter reg 3 to be the octets 2 - 5 of the
1153 * MAC address for first address
1155 uni_pf3 = (adapter->addr[0] << ET_UNI_PF_ADDR2_1_SHIFT) |
1156 (adapter->addr[1] << ET_UNI_PF_ADDR2_2_SHIFT) |
1157 (adapter->addr[0] << ET_UNI_PF_ADDR1_1_SHIFT) |
1160 uni_pf2 = (adapter->addr[2] << ET_UNI_PF_ADDR2_3_SHIFT) |
1161 (adapter->addr[3] << ET_UNI_PF_ADDR2_4_SHIFT) |
1162 (adapter->addr[4] << ET_UNI_PF_ADDR2_5_SHIFT) |
1165 uni_pf1 = (adapter->addr[2] << ET_UNI_PF_ADDR1_3_SHIFT) |
1166 (adapter->addr[3] << ET_UNI_PF_ADDR1_4_SHIFT) |
1167 (adapter->addr[4] << ET_UNI_PF_ADDR1_5_SHIFT) |
1170 pm_csr = readl(&adapter->regs->global.pm_csr);
1171 if (!et1310_in_phy_coma(adapter)) {
1172 writel(uni_pf1, &rxmac->uni_pf_addr1);
1173 writel(uni_pf2, &rxmac->uni_pf_addr2);
1174 writel(uni_pf3, &rxmac->uni_pf_addr3);
1178 static void et1310_config_rxmac_regs(struct et131x_adapter *adapter)
1180 struct rxmac_regs __iomem *rxmac = &adapter->regs->rxmac;
1181 struct phy_device *phydev = adapter->phydev;
1186 /* Disable the MAC while it is being configured (also disable WOL) */
1187 writel(0x8, &rxmac->ctrl);
1189 /* Initialize WOL to disabled. */
1190 writel(0, &rxmac->crc0);
1191 writel(0, &rxmac->crc12);
1192 writel(0, &rxmac->crc34);
1194 /* We need to set the WOL mask0 - mask4 next. We initialize it to
1195 * its default Values of 0x00000000 because there are not WOL masks
1198 writel(0, &rxmac->mask0_word0);
1199 writel(0, &rxmac->mask0_word1);
1200 writel(0, &rxmac->mask0_word2);
1201 writel(0, &rxmac->mask0_word3);
1203 writel(0, &rxmac->mask1_word0);
1204 writel(0, &rxmac->mask1_word1);
1205 writel(0, &rxmac->mask1_word2);
1206 writel(0, &rxmac->mask1_word3);
1208 writel(0, &rxmac->mask2_word0);
1209 writel(0, &rxmac->mask2_word1);
1210 writel(0, &rxmac->mask2_word2);
1211 writel(0, &rxmac->mask2_word3);
1213 writel(0, &rxmac->mask3_word0);
1214 writel(0, &rxmac->mask3_word1);
1215 writel(0, &rxmac->mask3_word2);
1216 writel(0, &rxmac->mask3_word3);
1218 writel(0, &rxmac->mask4_word0);
1219 writel(0, &rxmac->mask4_word1);
1220 writel(0, &rxmac->mask4_word2);
1221 writel(0, &rxmac->mask4_word3);
1223 /* Lets setup the WOL Source Address */
1224 sa_lo = (adapter->addr[2] << ET_WOL_LO_SA3_SHIFT) |
1225 (adapter->addr[3] << ET_WOL_LO_SA4_SHIFT) |
1226 (adapter->addr[4] << ET_WOL_LO_SA5_SHIFT) |
1228 writel(sa_lo, &rxmac->sa_lo);
1230 sa_hi = (u32) (adapter->addr[0] << ET_WOL_HI_SA1_SHIFT) |
1232 writel(sa_hi, &rxmac->sa_hi);
1234 /* Disable all Packet Filtering */
1235 writel(0, &rxmac->pf_ctrl);
1237 /* Let's initialize the Unicast Packet filtering address */
1238 if (adapter->packet_filter & ET131X_PACKET_TYPE_DIRECTED) {
1239 et1310_setup_device_for_unicast(adapter);
1240 pf_ctrl |= 4; /* Unicast filter */
1242 writel(0, &rxmac->uni_pf_addr1);
1243 writel(0, &rxmac->uni_pf_addr2);
1244 writel(0, &rxmac->uni_pf_addr3);
1247 /* Let's initialize the Multicast hash */
1248 if (!(adapter->packet_filter & ET131X_PACKET_TYPE_ALL_MULTICAST)) {
1249 pf_ctrl |= 2; /* Multicast filter */
1250 et1310_setup_device_for_multicast(adapter);
1253 /* Runt packet filtering. Didn't work in version A silicon. */
1254 pf_ctrl |= (NIC_MIN_PACKET_SIZE + 4) << 16;
1255 pf_ctrl |= 8; /* Fragment filter */
1257 if (adapter->registry_jumbo_packet > 8192)
1258 /* In order to transmit jumbo packets greater than 8k, the
1259 * FIFO between RxMAC and RxDMA needs to be reduced in size
1260 * to (16k - Jumbo packet size). In order to implement this,
1261 * we must use "cut through" mode in the RxMAC, which chops
1262 * packets down into segments which are (max_size * 16). In
1263 * this case we selected 256 bytes, since this is the size of
1264 * the PCI-Express TLP's that the 1310 uses.
1266 * seg_en on, fc_en off, size 0x10
1268 writel(0x41, &rxmac->mcif_ctrl_max_seg);
1270 writel(0, &rxmac->mcif_ctrl_max_seg);
1272 /* Initialize the MCIF water marks */
1273 writel(0, &rxmac->mcif_water_mark);
1275 /* Initialize the MIF control */
1276 writel(0, &rxmac->mif_ctrl);
1278 /* Initialize the Space Available Register */
1279 writel(0, &rxmac->space_avail);
1281 /* Initialize the the mif_ctrl register
1282 * bit 3: Receive code error. One or more nibbles were signaled as
1283 * errors during the reception of the packet. Clear this
1284 * bit in Gigabit, set it in 100Mbit. This was derived
1285 * experimentally at UNH.
1286 * bit 4: Receive CRC error. The packet's CRC did not match the
1287 * internally generated CRC.
1288 * bit 5: Receive length check error. Indicates that frame length
1289 * field value in the packet does not match the actual data
1290 * byte length and is not a type field.
1291 * bit 16: Receive frame truncated.
1292 * bit 17: Drop packet enable
1294 if (phydev && phydev->speed == SPEED_100)
1295 writel(0x30038, &rxmac->mif_ctrl);
1297 writel(0x30030, &rxmac->mif_ctrl);
1299 /* Finally we initialize RxMac to be enabled & WOL disabled. Packet
1300 * filter is always enabled since it is where the runt packets are
1301 * supposed to be dropped. For version A silicon, runt packet
1302 * dropping doesn't work, so it is disabled in the pf_ctrl register,
1303 * but we still leave the packet filter on.
1305 writel(pf_ctrl, &rxmac->pf_ctrl);
1306 writel(0x9, &rxmac->ctrl);
1309 static void et1310_config_txmac_regs(struct et131x_adapter *adapter)
1311 struct txmac_regs __iomem *txmac = &adapter->regs->txmac;
1313 /* We need to update the Control Frame Parameters
1314 * cfpt - control frame pause timer set to 64 (0x40)
1315 * cfep - control frame extended pause timer set to 0x0
1317 if (adapter->flowcontrol == FLOW_NONE)
1318 writel(0, &txmac->cf_param);
1320 writel(0x40, &txmac->cf_param);
1323 static void et1310_config_macstat_regs(struct et131x_adapter *adapter)
1325 struct macstat_regs __iomem *macstat =
1326 &adapter->regs->macstat;
1328 /* Next we need to initialize all the macstat registers to zero on
1331 writel(0, &macstat->txrx_0_64_byte_frames);
1332 writel(0, &macstat->txrx_65_127_byte_frames);
1333 writel(0, &macstat->txrx_128_255_byte_frames);
1334 writel(0, &macstat->txrx_256_511_byte_frames);
1335 writel(0, &macstat->txrx_512_1023_byte_frames);
1336 writel(0, &macstat->txrx_1024_1518_byte_frames);
1337 writel(0, &macstat->txrx_1519_1522_gvln_frames);
1339 writel(0, &macstat->rx_bytes);
1340 writel(0, &macstat->rx_packets);
1341 writel(0, &macstat->rx_fcs_errs);
1342 writel(0, &macstat->rx_multicast_packets);
1343 writel(0, &macstat->rx_broadcast_packets);
1344 writel(0, &macstat->rx_control_frames);
1345 writel(0, &macstat->rx_pause_frames);
1346 writel(0, &macstat->rx_unknown_opcodes);
1347 writel(0, &macstat->rx_align_errs);
1348 writel(0, &macstat->rx_frame_len_errs);
1349 writel(0, &macstat->rx_code_errs);
1350 writel(0, &macstat->rx_carrier_sense_errs);
1351 writel(0, &macstat->rx_undersize_packets);
1352 writel(0, &macstat->rx_oversize_packets);
1353 writel(0, &macstat->rx_fragment_packets);
1354 writel(0, &macstat->rx_jabbers);
1355 writel(0, &macstat->rx_drops);
1357 writel(0, &macstat->tx_bytes);
1358 writel(0, &macstat->tx_packets);
1359 writel(0, &macstat->tx_multicast_packets);
1360 writel(0, &macstat->tx_broadcast_packets);
1361 writel(0, &macstat->tx_pause_frames);
1362 writel(0, &macstat->tx_deferred);
1363 writel(0, &macstat->tx_excessive_deferred);
1364 writel(0, &macstat->tx_single_collisions);
1365 writel(0, &macstat->tx_multiple_collisions);
1366 writel(0, &macstat->tx_late_collisions);
1367 writel(0, &macstat->tx_excessive_collisions);
1368 writel(0, &macstat->tx_total_collisions);
1369 writel(0, &macstat->tx_pause_honored_frames);
1370 writel(0, &macstat->tx_drops);
1371 writel(0, &macstat->tx_jabbers);
1372 writel(0, &macstat->tx_fcs_errs);
1373 writel(0, &macstat->tx_control_frames);
1374 writel(0, &macstat->tx_oversize_frames);
1375 writel(0, &macstat->tx_undersize_frames);
1376 writel(0, &macstat->tx_fragments);
1377 writel(0, &macstat->carry_reg1);
1378 writel(0, &macstat->carry_reg2);
1380 /* Unmask any counters that we want to track the overflow of.
1381 * Initially this will be all counters. It may become clear later
1382 * that we do not need to track all counters.
1384 writel(0xFFFFBE32, &macstat->carry_reg1_mask);
1385 writel(0xFFFE7E8B, &macstat->carry_reg2_mask);
1389 * et131x_phy_mii_read - Read from the PHY through the MII Interface on the MAC
1390 * @adapter: pointer to our private adapter structure
1391 * @addr: the address of the transceiver
1392 * @reg: the register to read
1393 * @value: pointer to a 16-bit value in which the value will be stored
1395 * Returns 0 on success, errno on failure (as defined in errno.h)
1397 static int et131x_phy_mii_read(struct et131x_adapter *adapter, u8 addr,
1400 struct mac_regs __iomem *mac = &adapter->regs->mac;
1407 /* Save a local copy of the registers we are dealing with so we can
1410 mii_addr = readl(&mac->mii_mgmt_addr);
1411 mii_cmd = readl(&mac->mii_mgmt_cmd);
1413 /* Stop the current operation */
1414 writel(0, &mac->mii_mgmt_cmd);
1416 /* Set up the register we need to read from on the correct PHY */
1417 writel(MII_ADDR(addr, reg), &mac->mii_mgmt_addr);
1419 writel(0x1, &mac->mii_mgmt_cmd);
1424 mii_indicator = readl(&mac->mii_mgmt_indicator);
1425 } while ((mii_indicator & MGMT_WAIT) && delay < 50);
1427 /* If we hit the max delay, we could not read the register */
1429 dev_warn(&adapter->pdev->dev,
1430 "reg 0x%08x could not be read\n", reg);
1431 dev_warn(&adapter->pdev->dev, "status is 0x%08x\n",
1437 /* If we hit here we were able to read the register and we need to
1438 * return the value to the caller */
1439 *value = readl(&mac->mii_mgmt_stat) & 0xFFFF;
1441 /* Stop the read operation */
1442 writel(0, &mac->mii_mgmt_cmd);
1444 /* set the registers we touched back to the state at which we entered
1447 writel(mii_addr, &mac->mii_mgmt_addr);
1448 writel(mii_cmd, &mac->mii_mgmt_cmd);
1453 static int et131x_mii_read(struct et131x_adapter *adapter, u8 reg, u16 *value)
1455 struct phy_device *phydev = adapter->phydev;
1460 return et131x_phy_mii_read(adapter, phydev->addr, reg, value);
1464 * et131x_mii_write - Write to a PHY register through the MII interface of the MAC
1465 * @adapter: pointer to our private adapter structure
1466 * @reg: the register to read
1467 * @value: 16-bit value to write
1469 * FIXME: one caller in netdev still
1471 * Return 0 on success, errno on failure (as defined in errno.h)
1473 static int et131x_mii_write(struct et131x_adapter *adapter, u8 reg, u16 value)
1475 struct mac_regs __iomem *mac = &adapter->regs->mac;
1476 struct phy_device *phydev = adapter->phydev;
1487 addr = phydev->addr;
1489 /* Save a local copy of the registers we are dealing with so we can
1492 mii_addr = readl(&mac->mii_mgmt_addr);
1493 mii_cmd = readl(&mac->mii_mgmt_cmd);
1495 /* Stop the current operation */
1496 writel(0, &mac->mii_mgmt_cmd);
1498 /* Set up the register we need to write to on the correct PHY */
1499 writel(MII_ADDR(addr, reg), &mac->mii_mgmt_addr);
1501 /* Add the value to write to the registers to the mac */
1502 writel(value, &mac->mii_mgmt_ctrl);
1507 mii_indicator = readl(&mac->mii_mgmt_indicator);
1508 } while ((mii_indicator & MGMT_BUSY) && delay < 100);
1510 /* If we hit the max delay, we could not write the register */
1514 dev_warn(&adapter->pdev->dev,
1515 "reg 0x%08x could not be written", reg);
1516 dev_warn(&adapter->pdev->dev, "status is 0x%08x\n",
1518 dev_warn(&adapter->pdev->dev, "command is 0x%08x\n",
1519 readl(&mac->mii_mgmt_cmd));
1521 et131x_mii_read(adapter, reg, &tmp);
1525 /* Stop the write operation */
1526 writel(0, &mac->mii_mgmt_cmd);
1529 * set the registers we touched back to the state at which we entered
1532 writel(mii_addr, &mac->mii_mgmt_addr);
1533 writel(mii_cmd, &mac->mii_mgmt_cmd);
1538 /* Still used from _mac for BIT_READ */
1539 static void et1310_phy_access_mii_bit(struct et131x_adapter *adapter,
1540 u16 action, u16 regnum, u16 bitnum,
1544 u16 mask = 0x0001 << bitnum;
1546 /* Read the requested register */
1547 et131x_mii_read(adapter, regnum, ®);
1550 case TRUEPHY_BIT_READ:
1551 *value = (reg & mask) >> bitnum;
1554 case TRUEPHY_BIT_SET:
1555 et131x_mii_write(adapter, regnum, reg | mask);
1558 case TRUEPHY_BIT_CLEAR:
1559 et131x_mii_write(adapter, regnum, reg & ~mask);
1567 static void et1310_config_flow_control(struct et131x_adapter *adapter)
1569 struct phy_device *phydev = adapter->phydev;
1571 if (phydev->duplex == DUPLEX_HALF) {
1572 adapter->flowcontrol = FLOW_NONE;
1574 char remote_pause, remote_async_pause;
1576 et1310_phy_access_mii_bit(adapter,
1577 TRUEPHY_BIT_READ, 5, 10, &remote_pause);
1578 et1310_phy_access_mii_bit(adapter,
1579 TRUEPHY_BIT_READ, 5, 11,
1580 &remote_async_pause);
1582 if ((remote_pause == TRUEPHY_BIT_SET) &&
1583 (remote_async_pause == TRUEPHY_BIT_SET)) {
1584 adapter->flowcontrol = adapter->wanted_flow;
1585 } else if ((remote_pause == TRUEPHY_BIT_SET) &&
1586 (remote_async_pause == TRUEPHY_BIT_CLEAR)) {
1587 if (adapter->wanted_flow == FLOW_BOTH)
1588 adapter->flowcontrol = FLOW_BOTH;
1590 adapter->flowcontrol = FLOW_NONE;
1591 } else if ((remote_pause == TRUEPHY_BIT_CLEAR) &&
1592 (remote_async_pause == TRUEPHY_BIT_CLEAR)) {
1593 adapter->flowcontrol = FLOW_NONE;
1594 } else {/* if (remote_pause == TRUEPHY_CLEAR_BIT &&
1595 remote_async_pause == TRUEPHY_SET_BIT) */
1596 if (adapter->wanted_flow == FLOW_BOTH)
1597 adapter->flowcontrol = FLOW_RXONLY;
1599 adapter->flowcontrol = FLOW_NONE;
1605 * et1310_update_macstat_host_counters - Update the local copy of the statistics
1606 * @adapter: pointer to the adapter structure
1608 static void et1310_update_macstat_host_counters(struct et131x_adapter *adapter)
1610 struct ce_stats *stats = &adapter->stats;
1611 struct macstat_regs __iomem *macstat =
1612 &adapter->regs->macstat;
1614 stats->tx_collisions += readl(&macstat->tx_total_collisions);
1615 stats->tx_first_collisions += readl(&macstat->tx_single_collisions);
1616 stats->tx_deferred += readl(&macstat->tx_deferred);
1617 stats->tx_excessive_collisions +=
1618 readl(&macstat->tx_multiple_collisions);
1619 stats->tx_late_collisions += readl(&macstat->tx_late_collisions);
1620 stats->tx_underflows += readl(&macstat->tx_undersize_frames);
1621 stats->tx_max_pkt_errs += readl(&macstat->tx_oversize_frames);
1623 stats->rx_align_errs += readl(&macstat->rx_align_errs);
1624 stats->rx_crc_errs += readl(&macstat->rx_code_errs);
1625 stats->rcvd_pkts_dropped += readl(&macstat->rx_drops);
1626 stats->rx_overflows += readl(&macstat->rx_oversize_packets);
1627 stats->rx_code_violations += readl(&macstat->rx_fcs_errs);
1628 stats->rx_length_errs += readl(&macstat->rx_frame_len_errs);
1629 stats->rx_other_errs += readl(&macstat->rx_fragment_packets);
1633 * et1310_handle_macstat_interrupt
1634 * @adapter: pointer to the adapter structure
1636 * One of the MACSTAT counters has wrapped. Update the local copy of
1637 * the statistics held in the adapter structure, checking the "wrap"
1638 * bit for each counter.
1640 static void et1310_handle_macstat_interrupt(struct et131x_adapter *adapter)
1645 /* Read the interrupt bits from the register(s). These are Clear On
1648 carry_reg1 = readl(&adapter->regs->macstat.carry_reg1);
1649 carry_reg2 = readl(&adapter->regs->macstat.carry_reg2);
1651 writel(carry_reg1, &adapter->regs->macstat.carry_reg1);
1652 writel(carry_reg2, &adapter->regs->macstat.carry_reg2);
1654 /* We need to do update the host copy of all the MAC_STAT counters.
1655 * For each counter, check it's overflow bit. If the overflow bit is
1656 * set, then increment the host version of the count by one complete
1657 * revolution of the counter. This routine is called when the counter
1658 * block indicates that one of the counters has wrapped.
1660 if (carry_reg1 & (1 << 14))
1661 adapter->stats.rx_code_violations += COUNTER_WRAP_16_BIT;
1662 if (carry_reg1 & (1 << 8))
1663 adapter->stats.rx_align_errs += COUNTER_WRAP_12_BIT;
1664 if (carry_reg1 & (1 << 7))
1665 adapter->stats.rx_length_errs += COUNTER_WRAP_16_BIT;
1666 if (carry_reg1 & (1 << 2))
1667 adapter->stats.rx_other_errs += COUNTER_WRAP_16_BIT;
1668 if (carry_reg1 & (1 << 6))
1669 adapter->stats.rx_crc_errs += COUNTER_WRAP_16_BIT;
1670 if (carry_reg1 & (1 << 3))
1671 adapter->stats.rx_overflows += COUNTER_WRAP_16_BIT;
1672 if (carry_reg1 & (1 << 0))
1673 adapter->stats.rcvd_pkts_dropped += COUNTER_WRAP_16_BIT;
1674 if (carry_reg2 & (1 << 16))
1675 adapter->stats.tx_max_pkt_errs += COUNTER_WRAP_12_BIT;
1676 if (carry_reg2 & (1 << 15))
1677 adapter->stats.tx_underflows += COUNTER_WRAP_12_BIT;
1678 if (carry_reg2 & (1 << 6))
1679 adapter->stats.tx_first_collisions += COUNTER_WRAP_12_BIT;
1680 if (carry_reg2 & (1 << 8))
1681 adapter->stats.tx_deferred += COUNTER_WRAP_12_BIT;
1682 if (carry_reg2 & (1 << 5))
1683 adapter->stats.tx_excessive_collisions += COUNTER_WRAP_12_BIT;
1684 if (carry_reg2 & (1 << 4))
1685 adapter->stats.tx_late_collisions += COUNTER_WRAP_12_BIT;
1686 if (carry_reg2 & (1 << 2))
1687 adapter->stats.tx_collisions += COUNTER_WRAP_12_BIT;
1690 static int et131x_mdio_read(struct mii_bus *bus, int phy_addr, int reg)
1692 struct net_device *netdev = bus->priv;
1693 struct et131x_adapter *adapter = netdev_priv(netdev);
1697 ret = et131x_phy_mii_read(adapter, phy_addr, reg, &value);
1705 static int et131x_mdio_write(struct mii_bus *bus, int phy_addr,
1708 struct net_device *netdev = bus->priv;
1709 struct et131x_adapter *adapter = netdev_priv(netdev);
1711 return et131x_mii_write(adapter, reg, value);
1714 static int et131x_mdio_reset(struct mii_bus *bus)
1716 struct net_device *netdev = bus->priv;
1717 struct et131x_adapter *adapter = netdev_priv(netdev);
1719 et131x_mii_write(adapter, MII_BMCR, BMCR_RESET);
1725 * et1310_phy_power_down - PHY power control
1726 * @adapter: device to control
1727 * @down: true for off/false for back on
1729 * one hundred, ten, one thousand megs
1730 * How would you like to have your LAN accessed
1731 * Can't you see that this code processed
1732 * Phy power, phy power..
1734 static void et1310_phy_power_down(struct et131x_adapter *adapter, bool down)
1738 et131x_mii_read(adapter, MII_BMCR, &data);
1739 data &= ~BMCR_PDOWN;
1742 et131x_mii_write(adapter, MII_BMCR, data);
1746 * et131x_xcvr_init - Init the phy if we are setting it into force mode
1747 * @adapter: pointer to our private adapter structure
1750 static void et131x_xcvr_init(struct et131x_adapter *adapter)
1756 et131x_mii_read(adapter, PHY_INTERRUPT_STATUS, &isr);
1757 et131x_mii_read(adapter, PHY_INTERRUPT_MASK, &imr);
1759 /* Set the link status interrupt only. Bad behavior when link status
1760 * and auto neg are set, we run into a nested interrupt problem
1762 imr |= (ET_PHY_INT_MASK_AUTONEGSTAT |
1763 ET_PHY_INT_MASK_LINKSTAT |
1764 ET_PHY_INT_MASK_ENABLE);
1766 et131x_mii_write(adapter, PHY_INTERRUPT_MASK, imr);
1768 /* Set the LED behavior such that LED 1 indicates speed (off =
1769 * 10Mbits, blink = 100Mbits, on = 1000Mbits) and LED 2 indicates
1770 * link and activity (on for link, blink off for activity).
1772 * NOTE: Some customizations have been added here for specific
1773 * vendors; The LED behavior is now determined by vendor data in the
1774 * EEPROM. However, the above description is the default.
1776 if ((adapter->eeprom_data[1] & 0x4) == 0) {
1777 et131x_mii_read(adapter, PHY_LED_2, &lcr2);
1779 lcr2 &= (ET_LED2_LED_100TX | ET_LED2_LED_1000T);
1780 lcr2 |= (LED_VAL_LINKON_ACTIVE << LED_LINK_SHIFT);
1782 if ((adapter->eeprom_data[1] & 0x8) == 0)
1783 lcr2 |= (LED_VAL_1000BT_100BTX << LED_TXRX_SHIFT);
1785 lcr2 |= (LED_VAL_LINKON << LED_TXRX_SHIFT);
1787 et131x_mii_write(adapter, PHY_LED_2, lcr2);
1792 * et131x_configure_global_regs - configure JAGCore global regs
1793 * @adapter: pointer to our adapter structure
1795 * Used to configure the global registers on the JAGCore
1797 static void et131x_configure_global_regs(struct et131x_adapter *adapter)
1799 struct global_regs __iomem *regs = &adapter->regs->global;
1801 writel(0, ®s->rxq_start_addr);
1802 writel(INTERNAL_MEM_SIZE - 1, ®s->txq_end_addr);
1804 if (adapter->registry_jumbo_packet < 2048) {
1805 /* Tx / RxDMA and Tx/Rx MAC interfaces have a 1k word
1806 * block of RAM that the driver can split between Tx
1807 * and Rx as it desires. Our default is to split it
1810 writel(PARM_RX_MEM_END_DEF, ®s->rxq_end_addr);
1811 writel(PARM_RX_MEM_END_DEF + 1, ®s->txq_start_addr);
1812 } else if (adapter->registry_jumbo_packet < 8192) {
1813 /* For jumbo packets > 2k but < 8k, split 50-50. */
1814 writel(INTERNAL_MEM_RX_OFFSET, ®s->rxq_end_addr);
1815 writel(INTERNAL_MEM_RX_OFFSET + 1, ®s->txq_start_addr);
1817 /* 9216 is the only packet size greater than 8k that
1818 * is available. The Tx buffer has to be big enough
1819 * for one whole packet on the Tx side. We'll make
1820 * the Tx 9408, and give the rest to Rx
1822 writel(0x01b3, ®s->rxq_end_addr);
1823 writel(0x01b4, ®s->txq_start_addr);
1826 /* Initialize the loopback register. Disable all loopbacks. */
1827 writel(0, ®s->loopback);
1830 writel(0, ®s->msi_config);
1832 /* By default, disable the watchdog timer. It will be enabled when
1833 * a packet is queued.
1835 writel(0, ®s->watchdog_timer);
1839 * et131x_config_rx_dma_regs - Start of Rx_DMA init sequence
1840 * @adapter: pointer to our adapter structure
1842 static void et131x_config_rx_dma_regs(struct et131x_adapter *adapter)
1844 struct rxdma_regs __iomem *rx_dma = &adapter->regs->rxdma;
1845 struct rx_ring *rx_local = &adapter->rx_ring;
1846 struct fbr_desc *fbr_entry;
1849 unsigned long flags;
1851 /* Halt RXDMA to perform the reconfigure. */
1852 et131x_rx_dma_disable(adapter);
1854 /* Load the completion writeback physical address */
1855 writel(upper_32_bits(rx_local->rx_status_bus), &rx_dma->dma_wb_base_hi);
1856 writel(lower_32_bits(rx_local->rx_status_bus), &rx_dma->dma_wb_base_lo);
1858 memset(rx_local->rx_status_block, 0, sizeof(struct rx_status_block));
1860 /* Set the address and parameters of the packet status ring into the
1863 writel(upper_32_bits(rx_local->ps_ring_physaddr), &rx_dma->psr_base_hi);
1864 writel(lower_32_bits(rx_local->ps_ring_physaddr), &rx_dma->psr_base_lo);
1865 writel(rx_local->psr_num_entries - 1, &rx_dma->psr_num_des);
1866 writel(0, &rx_dma->psr_full_offset);
1868 psr_num_des = readl(&rx_dma->psr_num_des) & 0xFFF;
1869 writel((psr_num_des * LO_MARK_PERCENT_FOR_PSR) / 100,
1870 &rx_dma->psr_min_des);
1872 spin_lock_irqsave(&adapter->rcv_lock, flags);
1874 /* These local variables track the PSR in the adapter structure */
1875 rx_local->local_psr_full = 0;
1877 /* Now's the best time to initialize FBR1 contents */
1878 fbr_entry = (struct fbr_desc *) rx_local->fbr[0]->ring_virtaddr;
1879 for (entry = 0; entry < rx_local->fbr[0]->num_entries; entry++) {
1880 fbr_entry->addr_hi = rx_local->fbr[0]->bus_high[entry];
1881 fbr_entry->addr_lo = rx_local->fbr[0]->bus_low[entry];
1882 fbr_entry->word2 = entry;
1886 /* Set the address and parameters of Free buffer ring 1 (and 0 if
1887 * required) into the 1310's registers
1889 writel(upper_32_bits(rx_local->fbr[0]->ring_physaddr),
1890 &rx_dma->fbr1_base_hi);
1891 writel(lower_32_bits(rx_local->fbr[0]->ring_physaddr),
1892 &rx_dma->fbr1_base_lo);
1893 writel(rx_local->fbr[0]->num_entries - 1, &rx_dma->fbr1_num_des);
1894 writel(ET_DMA10_WRAP, &rx_dma->fbr1_full_offset);
1896 /* This variable tracks the free buffer ring 1 full position, so it
1897 * has to match the above.
1899 rx_local->fbr[0]->local_full = ET_DMA10_WRAP;
1901 ((rx_local->fbr[0]->num_entries * LO_MARK_PERCENT_FOR_RX) / 100) - 1,
1902 &rx_dma->fbr1_min_des);
1904 /* Now's the best time to initialize FBR0 contents */
1905 fbr_entry = (struct fbr_desc *) rx_local->fbr[1]->ring_virtaddr;
1906 for (entry = 0; entry < rx_local->fbr[1]->num_entries; entry++) {
1907 fbr_entry->addr_hi = rx_local->fbr[1]->bus_high[entry];
1908 fbr_entry->addr_lo = rx_local->fbr[1]->bus_low[entry];
1909 fbr_entry->word2 = entry;
1913 writel(upper_32_bits(rx_local->fbr[1]->ring_physaddr),
1914 &rx_dma->fbr0_base_hi);
1915 writel(lower_32_bits(rx_local->fbr[1]->ring_physaddr),
1916 &rx_dma->fbr0_base_lo);
1917 writel(rx_local->fbr[1]->num_entries - 1, &rx_dma->fbr0_num_des);
1918 writel(ET_DMA10_WRAP, &rx_dma->fbr0_full_offset);
1920 /* This variable tracks the free buffer ring 0 full position, so it
1921 * has to match the above.
1923 rx_local->fbr[1]->local_full = ET_DMA10_WRAP;
1925 ((rx_local->fbr[1]->num_entries * LO_MARK_PERCENT_FOR_RX) / 100) - 1,
1926 &rx_dma->fbr0_min_des);
1928 /* Program the number of packets we will receive before generating an
1930 * For version B silicon, this value gets updated once autoneg is
1933 writel(PARM_RX_NUM_BUFS_DEF, &rx_dma->num_pkt_done);
1935 /* The "time_done" is not working correctly to coalesce interrupts
1936 * after a given time period, but rather is giving us an interrupt
1937 * regardless of whether we have received packets.
1938 * This value gets updated once autoneg is complete.
1940 writel(PARM_RX_TIME_INT_DEF, &rx_dma->max_pkt_time);
1942 spin_unlock_irqrestore(&adapter->rcv_lock, flags);
1946 * et131x_config_tx_dma_regs - Set up the tx dma section of the JAGCore.
1947 * @adapter: pointer to our private adapter structure
1949 * Configure the transmit engine with the ring buffers we have created
1950 * and prepare it for use.
1952 static void et131x_config_tx_dma_regs(struct et131x_adapter *adapter)
1954 struct txdma_regs __iomem *txdma = &adapter->regs->txdma;
1956 /* Load the hardware with the start of the transmit descriptor ring. */
1957 writel(upper_32_bits(adapter->tx_ring.tx_desc_ring_pa),
1958 &txdma->pr_base_hi);
1959 writel(lower_32_bits(adapter->tx_ring.tx_desc_ring_pa),
1960 &txdma->pr_base_lo);
1962 /* Initialise the transmit DMA engine */
1963 writel(NUM_DESC_PER_RING_TX - 1, &txdma->pr_num_des);
1965 /* Load the completion writeback physical address */
1966 writel(upper_32_bits(adapter->tx_ring.tx_status_pa),
1967 &txdma->dma_wb_base_hi);
1968 writel(lower_32_bits(adapter->tx_ring.tx_status_pa),
1969 &txdma->dma_wb_base_lo);
1971 *adapter->tx_ring.tx_status = 0;
1973 writel(0, &txdma->service_request);
1974 adapter->tx_ring.send_idx = 0;
1978 * et131x_adapter_setup - Set the adapter up as per cassini+ documentation
1979 * @adapter: pointer to our private adapter structure
1981 * Returns 0 on success, errno on failure (as defined in errno.h)
1983 static void et131x_adapter_setup(struct et131x_adapter *adapter)
1985 /* Configure the JAGCore */
1986 et131x_configure_global_regs(adapter);
1988 et1310_config_mac_regs1(adapter);
1990 /* Configure the MMC registers */
1991 /* All we need to do is initialize the Memory Control Register */
1992 writel(ET_MMC_ENABLE, &adapter->regs->mmc.mmc_ctrl);
1994 et1310_config_rxmac_regs(adapter);
1995 et1310_config_txmac_regs(adapter);
1997 et131x_config_rx_dma_regs(adapter);
1998 et131x_config_tx_dma_regs(adapter);
2000 et1310_config_macstat_regs(adapter);
2002 et1310_phy_power_down(adapter, 0);
2003 et131x_xcvr_init(adapter);
2007 * et131x_soft_reset - Issue a soft reset to the hardware, complete for ET1310
2008 * @adapter: pointer to our private adapter structure
2010 static void et131x_soft_reset(struct et131x_adapter *adapter)
2012 /* Disable MAC Core */
2013 writel(0xc00f0000, &adapter->regs->mac.cfg1);
2015 /* Set everything to a reset value */
2016 writel(0x7F, &adapter->regs->global.sw_reset);
2017 writel(0x000f0000, &adapter->regs->mac.cfg1);
2018 writel(0x00000000, &adapter->regs->mac.cfg1);
2022 * et131x_enable_interrupts - enable interrupt
2023 * @adapter: et131x device
2025 * Enable the appropriate interrupts on the ET131x according to our
2028 static void et131x_enable_interrupts(struct et131x_adapter *adapter)
2032 /* Enable all global interrupts */
2033 if (adapter->flowcontrol == FLOW_TXONLY ||
2034 adapter->flowcontrol == FLOW_BOTH)
2035 mask = INT_MASK_ENABLE;
2037 mask = INT_MASK_ENABLE_NO_FLOW;
2039 writel(mask, &adapter->regs->global.int_mask);
2043 * et131x_disable_interrupts - interrupt disable
2044 * @adapter: et131x device
2046 * Block all interrupts from the et131x device at the device itself
2048 static void et131x_disable_interrupts(struct et131x_adapter *adapter)
2050 /* Disable all global interrupts */
2051 writel(INT_MASK_DISABLE, &adapter->regs->global.int_mask);
2055 * et131x_tx_dma_disable - Stop of Tx_DMA on the ET1310
2056 * @adapter: pointer to our adapter structure
2058 static void et131x_tx_dma_disable(struct et131x_adapter *adapter)
2060 /* Setup the tramsmit dma configuration register */
2061 writel(ET_TXDMA_CSR_HALT|ET_TXDMA_SNGL_EPKT,
2062 &adapter->regs->txdma.csr);
2066 * et131x_enable_txrx - Enable tx/rx queues
2067 * @netdev: device to be enabled
2069 static void et131x_enable_txrx(struct net_device *netdev)
2071 struct et131x_adapter *adapter = netdev_priv(netdev);
2073 /* Enable the Tx and Rx DMA engines (if not already enabled) */
2074 et131x_rx_dma_enable(adapter);
2075 et131x_tx_dma_enable(adapter);
2077 /* Enable device interrupts */
2078 if (adapter->flags & fMP_ADAPTER_INTERRUPT_IN_USE)
2079 et131x_enable_interrupts(adapter);
2081 /* We're ready to move some data, so start the queue */
2082 netif_start_queue(netdev);
2086 * et131x_disable_txrx - Disable tx/rx queues
2087 * @netdev: device to be disabled
2089 static void et131x_disable_txrx(struct net_device *netdev)
2091 struct et131x_adapter *adapter = netdev_priv(netdev);
2093 /* First thing is to stop the queue */
2094 netif_stop_queue(netdev);
2096 /* Stop the Tx and Rx DMA engines */
2097 et131x_rx_dma_disable(adapter);
2098 et131x_tx_dma_disable(adapter);
2100 /* Disable device interrupts */
2101 et131x_disable_interrupts(adapter);
2105 * et131x_init_send - Initialize send data structures
2106 * @adapter: pointer to our private adapter structure
2108 static void et131x_init_send(struct et131x_adapter *adapter)
2112 struct tx_ring *tx_ring;
2114 /* Setup some convenience pointers */
2115 tx_ring = &adapter->tx_ring;
2116 tcb = adapter->tx_ring.tcb_ring;
2118 tx_ring->tcb_qhead = tcb;
2120 memset(tcb, 0, sizeof(struct tcb) * NUM_TCB);
2122 /* Go through and set up each TCB */
2123 for (ct = 0; ct++ < NUM_TCB; tcb++)
2124 /* Set the link pointer in HW TCB to the next TCB in the
2127 tcb->next = tcb + 1;
2129 /* Set the tail pointer */
2131 tx_ring->tcb_qtail = tcb;
2133 /* Curr send queue should now be empty */
2134 tx_ring->send_head = NULL;
2135 tx_ring->send_tail = NULL;
2139 * et1310_enable_phy_coma - called when network cable is unplugged
2140 * @adapter: pointer to our adapter structure
2142 * driver receive an phy status change interrupt while in D0 and check that
2143 * phy_status is down.
2145 * -- gate off JAGCore;
2146 * -- set gigE PHY in Coma mode
2147 * -- wake on phy_interrupt; Perform software reset JAGCore,
2148 * re-initialize jagcore and gigE PHY
2150 * Add D0-ASPM-PhyLinkDown Support:
2151 * -- while in D0, when there is a phy_interrupt indicating phy link
2152 * down status, call the MPSetPhyComa routine to enter this active
2153 * state power saving mode
2154 * -- while in D0-ASPM-PhyLinkDown mode, when there is a phy_interrupt
2155 * indicating linkup status, call the MPDisablePhyComa routine to
2156 * restore JAGCore and gigE PHY
2158 static void et1310_enable_phy_coma(struct et131x_adapter *adapter)
2160 unsigned long flags;
2163 pmcsr = readl(&adapter->regs->global.pm_csr);
2165 /* Save the GbE PHY speed and duplex modes. Need to restore this
2166 * when cable is plugged back in
2169 * TODO - when PM is re-enabled, check if we need to
2170 * perform a similar task as this -
2171 * adapter->pdown_speed = adapter->ai_force_speed;
2172 * adapter->pdown_duplex = adapter->ai_force_duplex;
2175 /* Stop sending packets. */
2176 spin_lock_irqsave(&adapter->send_hw_lock, flags);
2177 adapter->flags |= fMP_ADAPTER_LOWER_POWER;
2178 spin_unlock_irqrestore(&adapter->send_hw_lock, flags);
2180 /* Wait for outstanding Receive packets */
2182 et131x_disable_txrx(adapter->netdev);
2184 /* Gate off JAGCore 3 clock domains */
2185 pmcsr &= ~ET_PMCSR_INIT;
2186 writel(pmcsr, &adapter->regs->global.pm_csr);
2188 /* Program gigE PHY in to Coma mode */
2189 pmcsr |= ET_PM_PHY_SW_COMA;
2190 writel(pmcsr, &adapter->regs->global.pm_csr);
2194 * et1310_disable_phy_coma - Disable the Phy Coma Mode
2195 * @adapter: pointer to our adapter structure
2197 static void et1310_disable_phy_coma(struct et131x_adapter *adapter)
2201 pmcsr = readl(&adapter->regs->global.pm_csr);
2203 /* Disable phy_sw_coma register and re-enable JAGCore clocks */
2204 pmcsr |= ET_PMCSR_INIT;
2205 pmcsr &= ~ET_PM_PHY_SW_COMA;
2206 writel(pmcsr, &adapter->regs->global.pm_csr);
2208 /* Restore the GbE PHY speed and duplex modes;
2209 * Reset JAGCore; re-configure and initialize JAGCore and gigE PHY
2211 /* TODO - when PM is re-enabled, check if we need to
2212 * perform a similar task as this -
2213 * adapter->ai_force_speed = adapter->pdown_speed;
2214 * adapter->ai_force_duplex = adapter->pdown_duplex;
2217 /* Re-initialize the send structures */
2218 et131x_init_send(adapter);
2220 /* Bring the device back to the state it was during init prior to
2221 * autonegotiation being complete. This way, when we get the auto-neg
2222 * complete interrupt, we can complete init by calling ConfigMacREGS2.
2224 et131x_soft_reset(adapter);
2226 /* setup et1310 as per the documentation ?? */
2227 et131x_adapter_setup(adapter);
2229 /* Allow Tx to restart */
2230 adapter->flags &= ~fMP_ADAPTER_LOWER_POWER;
2232 et131x_enable_txrx(adapter->netdev);
2235 static inline u32 bump_free_buff_ring(u32 *free_buff_ring, u32 limit)
2237 u32 tmp_free_buff_ring = *free_buff_ring;
2238 tmp_free_buff_ring++;
2239 /* This works for all cases where limit < 1024. The 1023 case
2240 works because 1023++ is 1024 which means the if condition is not
2241 taken but the carry of the bit into the wrap bit toggles the wrap
2243 if ((tmp_free_buff_ring & ET_DMA10_MASK) > limit) {
2244 tmp_free_buff_ring &= ~ET_DMA10_MASK;
2245 tmp_free_buff_ring ^= ET_DMA10_WRAP;
2247 /* For the 1023 case */
2248 tmp_free_buff_ring &= (ET_DMA10_MASK|ET_DMA10_WRAP);
2249 *free_buff_ring = tmp_free_buff_ring;
2250 return tmp_free_buff_ring;
2254 * et131x_align_allocated_memory - Align allocated memory on a given boundary
2255 * @adapter: pointer to our adapter structure
2256 * @phys_addr: pointer to Physical address
2257 * @offset: pointer to the offset variable
2258 * @mask: correct mask
2260 static void et131x_align_allocated_memory(struct et131x_adapter *adapter,
2261 dma_addr_t *phys_addr, dma_addr_t *offset,
2264 u64 new_addr = *phys_addr & ~mask;
2268 if (new_addr != *phys_addr) {
2269 /* Move to next aligned block */
2270 new_addr += mask + 1;
2271 /* Return offset for adjusting virt addr */
2272 *offset = new_addr - *phys_addr;
2273 /* Return new physical address */
2274 *phys_addr = new_addr;
2279 * et131x_rx_dma_memory_alloc
2280 * @adapter: pointer to our private adapter structure
2282 * Returns 0 on success and errno on failure (as defined in errno.h)
2284 * Allocates Free buffer ring 1 for sure, free buffer ring 0 if required,
2285 * and the Packet Status Ring.
2287 static int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter)
2291 u32 pktstat_ringsize, fbr_chunksize;
2292 struct rx_ring *rx_ring;
2294 /* Setup some convenience pointers */
2295 rx_ring = &adapter->rx_ring;
2297 /* Alloc memory for the lookup table */
2298 rx_ring->fbr[1] = kmalloc(sizeof(struct fbr_lookup), GFP_KERNEL);
2299 rx_ring->fbr[0] = kmalloc(sizeof(struct fbr_lookup), GFP_KERNEL);
2301 /* The first thing we will do is configure the sizes of the buffer
2302 * rings. These will change based on jumbo packet support. Larger
2303 * jumbo packets increases the size of each entry in FBR0, and the
2304 * number of entries in FBR0, while at the same time decreasing the
2305 * number of entries in FBR1.
2307 * FBR1 holds "large" frames, FBR0 holds "small" frames. If FBR1
2308 * entries are huge in order to accommodate a "jumbo" frame, then it
2309 * will have less entries. Conversely, FBR1 will now be relied upon
2310 * to carry more "normal" frames, thus it's entry size also increases
2311 * and the number of entries goes up too (since it now carries
2312 * "small" + "regular" packets.
2314 * In this scheme, we try to maintain 512 entries between the two
2315 * rings. Also, FBR1 remains a constant size - when it's size doubles
2316 * the number of entries halves. FBR0 increases in size, however.
2319 if (adapter->registry_jumbo_packet < 2048) {
2320 rx_ring->fbr[1]->buffsize = 256;
2321 rx_ring->fbr[1]->num_entries = 512;
2322 rx_ring->fbr[0]->buffsize = 2048;
2323 rx_ring->fbr[0]->num_entries = 512;
2324 } else if (adapter->registry_jumbo_packet < 4096) {
2325 rx_ring->fbr[1]->buffsize = 512;
2326 rx_ring->fbr[1]->num_entries = 1024;
2327 rx_ring->fbr[0]->buffsize = 4096;
2328 rx_ring->fbr[0]->num_entries = 512;
2330 rx_ring->fbr[1]->buffsize = 1024;
2331 rx_ring->fbr[1]->num_entries = 768;
2332 rx_ring->fbr[0]->buffsize = 16384;
2333 rx_ring->fbr[0]->num_entries = 128;
2336 adapter->rx_ring.psr_num_entries =
2337 adapter->rx_ring.fbr[1]->num_entries +
2338 adapter->rx_ring.fbr[0]->num_entries;
2340 /* Allocate an area of memory for Free Buffer Ring 1 */
2341 bufsize = (sizeof(struct fbr_desc) * rx_ring->fbr[0]->num_entries) +
2343 rx_ring->fbr[0]->ring_virtaddr = dma_alloc_coherent(&adapter->pdev->dev,
2345 &rx_ring->fbr[0]->ring_physaddr,
2347 if (!rx_ring->fbr[0]->ring_virtaddr) {
2348 dev_err(&adapter->pdev->dev,
2349 "Cannot alloc memory for Free Buffer Ring 1\n");
2353 /* Align Free Buffer Ring 1 on a 4K boundary */
2354 et131x_align_allocated_memory(adapter,
2355 &rx_ring->fbr[0]->ring_physaddr,
2356 &rx_ring->fbr[0]->offset, 0x0FFF);
2358 rx_ring->fbr[0]->ring_virtaddr =
2359 (void *)((u8 *) rx_ring->fbr[0]->ring_virtaddr +
2360 rx_ring->fbr[0]->offset);
2362 /* Allocate an area of memory for Free Buffer Ring 0 */
2363 bufsize = (sizeof(struct fbr_desc) * rx_ring->fbr[1]->num_entries) +
2365 rx_ring->fbr[1]->ring_virtaddr = dma_alloc_coherent(&adapter->pdev->dev,
2367 &rx_ring->fbr[1]->ring_physaddr,
2369 if (!rx_ring->fbr[1]->ring_virtaddr) {
2370 dev_err(&adapter->pdev->dev,
2371 "Cannot alloc memory for Free Buffer Ring 0\n");
2375 /* Align Free Buffer Ring 0 on a 4K boundary */
2376 et131x_align_allocated_memory(adapter,
2377 &rx_ring->fbr[1]->ring_physaddr,
2378 &rx_ring->fbr[1]->offset, 0x0FFF);
2380 rx_ring->fbr[1]->ring_virtaddr =
2381 (void *)((u8 *) rx_ring->fbr[1]->ring_virtaddr +
2382 rx_ring->fbr[1]->offset);
2384 for (i = 0; i < (rx_ring->fbr[0]->num_entries / FBR_CHUNKS); i++) {
2385 dma_addr_t fbr1_tmp_physaddr;
2386 dma_addr_t fbr1_offset;
2389 /* This code allocates an area of memory big enough for N
2390 * free buffers + (buffer_size - 1) so that the buffers can
2391 * be aligned on 4k boundaries. If each buffer were aligned
2392 * to a buffer_size boundary, the effect would be to double
2393 * the size of FBR0. By allocating N buffers at once, we
2394 * reduce this overhead.
2396 if (rx_ring->fbr[0]->buffsize > 4096)
2399 fbr1_align = rx_ring->fbr[0]->buffsize;
2402 (FBR_CHUNKS * rx_ring->fbr[0]->buffsize) + fbr1_align - 1;
2403 rx_ring->fbr[0]->mem_virtaddrs[i] =
2404 dma_alloc_coherent(&adapter->pdev->dev, fbr_chunksize,
2405 &rx_ring->fbr[0]->mem_physaddrs[i],
2408 if (!rx_ring->fbr[0]->mem_virtaddrs[i]) {
2409 dev_err(&adapter->pdev->dev,
2410 "Could not alloc memory\n");
2414 /* See NOTE in "Save Physical Address" comment above */
2415 fbr1_tmp_physaddr = rx_ring->fbr[0]->mem_physaddrs[i];
2417 et131x_align_allocated_memory(adapter,
2419 &fbr1_offset, (fbr1_align - 1));
2421 for (j = 0; j < FBR_CHUNKS; j++) {
2422 u32 index = (i * FBR_CHUNKS) + j;
2424 /* Save the Virtual address of this index for quick
2427 rx_ring->fbr[0]->virt[index] =
2428 (u8 *) rx_ring->fbr[0]->mem_virtaddrs[i] +
2429 (j * rx_ring->fbr[0]->buffsize) + fbr1_offset;
2431 /* now store the physical address in the descriptor
2432 * so the device can access it
2434 rx_ring->fbr[0]->bus_high[index] =
2435 upper_32_bits(fbr1_tmp_physaddr);
2436 rx_ring->fbr[0]->bus_low[index] =
2437 lower_32_bits(fbr1_tmp_physaddr);
2439 fbr1_tmp_physaddr += rx_ring->fbr[0]->buffsize;
2441 rx_ring->fbr[0]->buffer1[index] =
2442 rx_ring->fbr[0]->virt[index];
2443 rx_ring->fbr[0]->buffer2[index] =
2444 rx_ring->fbr[0]->virt[index] - 4;
2448 /* Same for FBR0 (if in use) */
2449 for (i = 0; i < (rx_ring->fbr[1]->num_entries / FBR_CHUNKS); i++) {
2450 dma_addr_t fbr0_tmp_physaddr;
2451 dma_addr_t fbr0_offset;
2454 ((FBR_CHUNKS + 1) * rx_ring->fbr[1]->buffsize) - 1;
2455 rx_ring->fbr[1]->mem_virtaddrs[i] =
2456 dma_alloc_coherent(&adapter->pdev->dev, fbr_chunksize,
2457 &rx_ring->fbr[1]->mem_physaddrs[i],
2460 if (!rx_ring->fbr[1]->mem_virtaddrs[i]) {
2461 dev_err(&adapter->pdev->dev,
2462 "Could not alloc memory\n");
2466 /* See NOTE in "Save Physical Address" comment above */
2467 fbr0_tmp_physaddr = rx_ring->fbr[1]->mem_physaddrs[i];
2469 et131x_align_allocated_memory(adapter,
2472 rx_ring->fbr[1]->buffsize - 1);
2474 for (j = 0; j < FBR_CHUNKS; j++) {
2475 u32 index = (i * FBR_CHUNKS) + j;
2477 rx_ring->fbr[1]->virt[index] =
2478 (u8 *) rx_ring->fbr[1]->mem_virtaddrs[i] +
2479 (j * rx_ring->fbr[1]->buffsize) + fbr0_offset;
2481 rx_ring->fbr[1]->bus_high[index] =
2482 upper_32_bits(fbr0_tmp_physaddr);
2483 rx_ring->fbr[1]->bus_low[index] =
2484 lower_32_bits(fbr0_tmp_physaddr);
2486 fbr0_tmp_physaddr += rx_ring->fbr[1]->buffsize;
2488 rx_ring->fbr[1]->buffer1[index] =
2489 rx_ring->fbr[1]->virt[index];
2490 rx_ring->fbr[1]->buffer2[index] =
2491 rx_ring->fbr[1]->virt[index] - 4;
2495 /* Allocate an area of memory for FIFO of Packet Status ring entries */
2497 sizeof(struct pkt_stat_desc) * adapter->rx_ring.psr_num_entries;
2499 rx_ring->ps_ring_virtaddr = dma_alloc_coherent(&adapter->pdev->dev,
2501 &rx_ring->ps_ring_physaddr,
2504 if (!rx_ring->ps_ring_virtaddr) {
2505 dev_err(&adapter->pdev->dev,
2506 "Cannot alloc memory for Packet Status Ring\n");
2509 pr_info("Packet Status Ring %llx\n",
2510 (unsigned long long) rx_ring->ps_ring_physaddr);
2513 * NOTE : dma_alloc_coherent(), used above to alloc DMA regions,
2514 * ALWAYS returns SAC (32-bit) addresses. If DAC (64-bit) addresses
2515 * are ever returned, make sure the high part is retrieved here before
2516 * storing the adjusted address.
2519 /* Allocate an area of memory for writeback of status information */
2520 rx_ring->rx_status_block = dma_alloc_coherent(&adapter->pdev->dev,
2521 sizeof(struct rx_status_block),
2522 &rx_ring->rx_status_bus,
2524 if (!rx_ring->rx_status_block) {
2525 dev_err(&adapter->pdev->dev,
2526 "Cannot alloc memory for Status Block\n");
2529 rx_ring->num_rfd = NIC_DEFAULT_NUM_RFD;
2530 pr_info("PRS %llx\n", (unsigned long long)rx_ring->rx_status_bus);
2533 * kmem_cache_create initializes a lookaside list. After successful
2534 * creation, nonpaged fixed-size blocks can be allocated from and
2535 * freed to the lookaside list.
2536 * RFDs will be allocated from this pool.
2538 rx_ring->recv_lookaside = kmem_cache_create(adapter->netdev->name,
2545 adapter->flags |= fMP_ADAPTER_RECV_LOOKASIDE;
2547 /* The RFDs are going to be put on lists later on, so initialize the
2550 INIT_LIST_HEAD(&rx_ring->recv_list);
2555 * et131x_rx_dma_memory_free - Free all memory allocated within this module.
2556 * @adapter: pointer to our private adapter structure
2558 static void et131x_rx_dma_memory_free(struct et131x_adapter *adapter)
2562 u32 pktstat_ringsize;
2564 struct rx_ring *rx_ring;
2566 /* Setup some convenience pointers */
2567 rx_ring = &adapter->rx_ring;
2569 /* Free RFDs and associated packet descriptors */
2570 WARN_ON(rx_ring->num_ready_recv != rx_ring->num_rfd);
2572 while (!list_empty(&rx_ring->recv_list)) {
2573 rfd = (struct rfd *) list_entry(rx_ring->recv_list.next,
2574 struct rfd, list_node);
2576 list_del(&rfd->list_node);
2578 kmem_cache_free(adapter->rx_ring.recv_lookaside, rfd);
2581 /* Free Free Buffer Ring 1 */
2582 if (rx_ring->fbr[0]->ring_virtaddr) {
2583 /* First the packet memory */
2584 for (index = 0; index <
2585 (rx_ring->fbr[0]->num_entries / FBR_CHUNKS); index++) {
2586 if (rx_ring->fbr[0]->mem_virtaddrs[index]) {
2589 if (rx_ring->fbr[0]->buffsize > 4096)
2592 fbr1_align = rx_ring->fbr[0]->buffsize;
2595 (rx_ring->fbr[0]->buffsize * FBR_CHUNKS) +
2598 dma_free_coherent(&adapter->pdev->dev,
2600 rx_ring->fbr[0]->mem_virtaddrs[index],
2601 rx_ring->fbr[0]->mem_physaddrs[index]);
2603 rx_ring->fbr[0]->mem_virtaddrs[index] = NULL;
2607 /* Now the FIFO itself */
2608 rx_ring->fbr[0]->ring_virtaddr = (void *)((u8 *)
2609 rx_ring->fbr[0]->ring_virtaddr - rx_ring->fbr[0]->offset);
2612 (sizeof(struct fbr_desc) * rx_ring->fbr[0]->num_entries) +
2615 dma_free_coherent(&adapter->pdev->dev, bufsize,
2616 rx_ring->fbr[0]->ring_virtaddr,
2617 rx_ring->fbr[0]->ring_physaddr);
2619 rx_ring->fbr[0]->ring_virtaddr = NULL;
2622 /* Now the same for Free Buffer Ring 0 */
2623 if (rx_ring->fbr[1]->ring_virtaddr) {
2624 /* First the packet memory */
2625 for (index = 0; index <
2626 (rx_ring->fbr[1]->num_entries / FBR_CHUNKS); index++) {
2627 if (rx_ring->fbr[1]->mem_virtaddrs[index]) {
2629 (rx_ring->fbr[1]->buffsize *
2630 (FBR_CHUNKS + 1)) - 1;
2632 dma_free_coherent(&adapter->pdev->dev,
2634 rx_ring->fbr[1]->mem_virtaddrs[index],
2635 rx_ring->fbr[1]->mem_physaddrs[index]);
2637 rx_ring->fbr[1]->mem_virtaddrs[index] = NULL;
2641 /* Now the FIFO itself */
2642 rx_ring->fbr[1]->ring_virtaddr = (void *)((u8 *)
2643 rx_ring->fbr[1]->ring_virtaddr - rx_ring->fbr[1]->offset);
2646 (sizeof(struct fbr_desc) * rx_ring->fbr[1]->num_entries) +
2649 dma_free_coherent(&adapter->pdev->dev,
2651 rx_ring->fbr[1]->ring_virtaddr,
2652 rx_ring->fbr[1]->ring_physaddr);
2654 rx_ring->fbr[1]->ring_virtaddr = NULL;
2657 /* Free Packet Status Ring */
2658 if (rx_ring->ps_ring_virtaddr) {
2660 sizeof(struct pkt_stat_desc) *
2661 adapter->rx_ring.psr_num_entries;
2663 dma_free_coherent(&adapter->pdev->dev, pktstat_ringsize,
2664 rx_ring->ps_ring_virtaddr,
2665 rx_ring->ps_ring_physaddr);
2667 rx_ring->ps_ring_virtaddr = NULL;
2670 /* Free area of memory for the writeback of status information */
2671 if (rx_ring->rx_status_block) {
2672 dma_free_coherent(&adapter->pdev->dev,
2673 sizeof(struct rx_status_block),
2674 rx_ring->rx_status_block, rx_ring->rx_status_bus);
2675 rx_ring->rx_status_block = NULL;
2678 /* Destroy the lookaside (RFD) pool */
2679 if (adapter->flags & fMP_ADAPTER_RECV_LOOKASIDE) {
2680 kmem_cache_destroy(rx_ring->recv_lookaside);
2681 adapter->flags &= ~fMP_ADAPTER_RECV_LOOKASIDE;
2684 /* Free the FBR Lookup Table */
2685 kfree(rx_ring->fbr[1]);
2686 kfree(rx_ring->fbr[0]);
2688 /* Reset Counters */
2689 rx_ring->num_ready_recv = 0;
2693 * et131x_init_recv - Initialize receive data structures.
2694 * @adapter: pointer to our private adapter structure
2696 * Returns 0 on success and errno on failure (as defined in errno.h)
2698 static int et131x_init_recv(struct et131x_adapter *adapter)
2700 int status = -ENOMEM;
2701 struct rfd *rfd = NULL;
2704 struct rx_ring *rx_ring;
2706 /* Setup some convenience pointers */
2707 rx_ring = &adapter->rx_ring;
2709 /* Setup each RFD */
2710 for (rfdct = 0; rfdct < rx_ring->num_rfd; rfdct++) {
2711 rfd = kmem_cache_alloc(rx_ring->recv_lookaside,
2712 GFP_ATOMIC | GFP_DMA);
2715 dev_err(&adapter->pdev->dev,
2716 "Couldn't alloc RFD out of kmem_cache\n");
2723 /* Add this RFD to the recv_list */
2724 list_add_tail(&rfd->list_node, &rx_ring->recv_list);
2726 /* Increment both the available RFD's, and the total RFD's. */
2727 rx_ring->num_ready_recv++;
2731 if (numrfd > NIC_MIN_NUM_RFD)
2734 rx_ring->num_rfd = numrfd;
2737 kmem_cache_free(rx_ring->recv_lookaside, rfd);
2738 dev_err(&adapter->pdev->dev,
2739 "Allocation problems in et131x_init_recv\n");
2745 * et131x_set_rx_dma_timer - Set the heartbeat timer according to line rate.
2746 * @adapter: pointer to our adapter structure
2748 static void et131x_set_rx_dma_timer(struct et131x_adapter *adapter)
2750 struct phy_device *phydev = adapter->phydev;
2755 /* For version B silicon, we do not use the RxDMA timer for 10 and 100
2756 * Mbits/s line rates. We do not enable and RxDMA interrupt coalescing.
2758 if ((phydev->speed == SPEED_100) || (phydev->speed == SPEED_10)) {
2759 writel(0, &adapter->regs->rxdma.max_pkt_time);
2760 writel(1, &adapter->regs->rxdma.num_pkt_done);
2765 * NICReturnRFD - Recycle a RFD and put it back onto the receive list
2766 * @adapter: pointer to our adapter
2767 * @rfd: pointer to the RFD
2769 static void nic_return_rfd(struct et131x_adapter *adapter, struct rfd *rfd)
2771 struct rx_ring *rx_local = &adapter->rx_ring;
2772 struct rxdma_regs __iomem *rx_dma = &adapter->regs->rxdma;
2773 u16 buff_index = rfd->bufferindex;
2774 u8 ring_index = rfd->ringindex;
2775 unsigned long flags;
2777 /* We don't use any of the OOB data besides status. Otherwise, we
2778 * need to clean up OOB data
2781 (ring_index == 0 && buff_index < rx_local->fbr[1]->num_entries) ||
2782 (ring_index == 1 && buff_index < rx_local->fbr[0]->num_entries)) {
2783 spin_lock_irqsave(&adapter->fbr_lock, flags);
2785 if (ring_index == 1) {
2786 struct fbr_desc *next = (struct fbr_desc *)
2787 (rx_local->fbr[0]->ring_virtaddr) +
2788 INDEX10(rx_local->fbr[0]->local_full);
2790 /* Handle the Free Buffer Ring advancement here. Write
2791 * the PA / Buffer Index for the returned buffer into
2792 * the oldest (next to be freed)FBR entry
2794 next->addr_hi = rx_local->fbr[0]->bus_high[buff_index];
2795 next->addr_lo = rx_local->fbr[0]->bus_low[buff_index];
2796 next->word2 = buff_index;
2798 writel(bump_free_buff_ring(
2799 &rx_local->fbr[0]->local_full,
2800 rx_local->fbr[0]->num_entries - 1),
2801 &rx_dma->fbr1_full_offset);
2803 struct fbr_desc *next = (struct fbr_desc *)
2804 rx_local->fbr[1]->ring_virtaddr +
2805 INDEX10(rx_local->fbr[1]->local_full);
2807 /* Handle the Free Buffer Ring advancement here. Write
2808 * the PA / Buffer Index for the returned buffer into
2809 * the oldest (next to be freed) FBR entry
2811 next->addr_hi = rx_local->fbr[1]->bus_high[buff_index];
2812 next->addr_lo = rx_local->fbr[1]->bus_low[buff_index];
2813 next->word2 = buff_index;
2815 writel(bump_free_buff_ring(
2816 &rx_local->fbr[1]->local_full,
2817 rx_local->fbr[1]->num_entries - 1),
2818 &rx_dma->fbr0_full_offset);
2820 spin_unlock_irqrestore(&adapter->fbr_lock, flags);
2822 dev_err(&adapter->pdev->dev,
2823 "%s illegal Buffer Index returned\n", __func__);
2826 /* The processing on this RFD is done, so put it back on the tail of
2829 spin_lock_irqsave(&adapter->rcv_lock, flags);
2830 list_add_tail(&rfd->list_node, &rx_local->recv_list);
2831 rx_local->num_ready_recv++;
2832 spin_unlock_irqrestore(&adapter->rcv_lock, flags);
2834 WARN_ON(rx_local->num_ready_recv > rx_local->num_rfd);
2838 * nic_rx_pkts - Checks the hardware for available packets
2839 * @adapter: pointer to our adapter
2841 * Returns rfd, a pointer to our MPRFD.
2843 * Checks the hardware for available packets, using completion ring
2844 * If packets are available, it gets an RFD from the recv_list, attaches
2845 * the packet to it, puts the RFD in the RecvPendList, and also returns
2846 * the pointer to the RFD.
2848 static struct rfd *nic_rx_pkts(struct et131x_adapter *adapter)
2850 struct rx_ring *rx_local = &adapter->rx_ring;
2851 struct rx_status_block *status;
2852 struct pkt_stat_desc *psr;
2856 unsigned long flags;
2857 struct list_head *element;
2864 /* RX Status block is written by the DMA engine prior to every
2865 * interrupt. It contains the next to be used entry in the Packet
2866 * Status Ring, and also the two Free Buffer rings.
2868 status = rx_local->rx_status_block;
2869 word1 = status->word1 >> 16; /* Get the useful bits */
2871 /* Check the PSR and wrap bits do not match */
2872 if ((word1 & 0x1FFF) == (rx_local->local_psr_full & 0x1FFF))
2873 /* Looks like this ring is not updated yet */
2876 /* The packet status ring indicates that data is available. */
2877 psr = (struct pkt_stat_desc *) (rx_local->ps_ring_virtaddr) +
2878 (rx_local->local_psr_full & 0xFFF);
2880 /* Grab any information that is required once the PSR is
2881 * advanced, since we can no longer rely on the memory being
2884 len = psr->word1 & 0xFFFF;
2885 ring_index = (psr->word1 >> 26) & 0x03;
2886 buff_index = (psr->word1 >> 16) & 0x3FF;
2889 /* Indicate that we have used this PSR entry. */
2891 add_12bit(&rx_local->local_psr_full, 1);
2893 (rx_local->local_psr_full & 0xFFF) > rx_local->psr_num_entries - 1) {
2894 /* Clear psr full and toggle the wrap bit */
2895 rx_local->local_psr_full &= ~0xFFF;
2896 rx_local->local_psr_full ^= 0x1000;
2899 writel(rx_local->local_psr_full,
2900 &adapter->regs->rxdma.psr_full_offset);
2902 if (ring_index > 1 ||
2904 buff_index > rx_local->fbr[1]->num_entries - 1) ||
2906 buff_index > rx_local->fbr[0]->num_entries - 1)) {
2907 /* Illegal buffer or ring index cannot be used by S/W*/
2908 dev_err(&adapter->pdev->dev,
2909 "NICRxPkts PSR Entry %d indicates "
2910 "length of %d and/or bad bi(%d)\n",
2911 rx_local->local_psr_full & 0xFFF,
2916 /* Get and fill the RFD. */
2917 spin_lock_irqsave(&adapter->rcv_lock, flags);
2920 element = rx_local->recv_list.next;
2921 rfd = (struct rfd *) list_entry(element, struct rfd, list_node);
2924 spin_unlock_irqrestore(&adapter->rcv_lock, flags);
2928 list_del(&rfd->list_node);
2929 rx_local->num_ready_recv--;
2931 spin_unlock_irqrestore(&adapter->rcv_lock, flags);
2933 rfd->bufferindex = buff_index;
2934 rfd->ringindex = ring_index;
2936 /* In V1 silicon, there is a bug which screws up filtering of
2937 * runt packets. Therefore runt packet filtering is disabled
2938 * in the MAC and the packets are dropped here. They are
2939 * also counted here.
2941 if (len < (NIC_MIN_PACKET_SIZE + 4)) {
2942 adapter->stats.rx_other_errs++;
2947 /* Determine if this is a multicast packet coming in */
2948 if ((word0 & ALCATEL_MULTICAST_PKT) &&
2949 !(word0 & ALCATEL_BROADCAST_PKT)) {
2950 /* Promiscuous mode and Multicast mode are
2951 * not mutually exclusive as was first
2952 * thought. I guess Promiscuous is just
2953 * considered a super-set of the other
2954 * filters. Generally filter is 0x2b when in
2957 if ((adapter->packet_filter &
2958 ET131X_PACKET_TYPE_MULTICAST)
2959 && !(adapter->packet_filter &
2960 ET131X_PACKET_TYPE_PROMISCUOUS)
2961 && !(adapter->packet_filter &
2962 ET131X_PACKET_TYPE_ALL_MULTICAST)) {
2964 * Note - ring_index for fbr[] array is reversed
2967 buf = rx_local->fbr[(ring_index == 0 ? 1 : 0)]->
2970 /* Loop through our list to see if the
2971 * destination address of this packet
2972 * matches one in our list.
2974 for (i = 0; i < adapter->multicast_addr_count;
2977 adapter->multicast_list[i][0]
2979 adapter->multicast_list[i][1]
2981 adapter->multicast_list[i][2]
2983 adapter->multicast_list[i][3]
2985 adapter->multicast_list[i][4]
2987 adapter->multicast_list[i][5]) {
2992 /* If our index is equal to the number
2993 * of Multicast address we have, then
2994 * this means we did not find this
2995 * packet's matching address in our
2996 * list. Set the len to zero,
2997 * so we free our RFD when we return
2998 * from this function.
3000 if (i == adapter->multicast_addr_count)
3005 adapter->stats.multicast_pkts_rcvd++;
3006 } else if (word0 & ALCATEL_BROADCAST_PKT)
3007 adapter->stats.broadcast_pkts_rcvd++;
3009 /* Not sure what this counter measures in
3010 * promiscuous mode. Perhaps we should check
3011 * the MAC address to see if it is directed
3012 * to us in promiscuous mode.
3014 adapter->stats.unicast_pkts_rcvd++;
3018 struct sk_buff *skb = NULL;
3020 /*rfd->len = len - 4; */
3023 skb = dev_alloc_skb(rfd->len + 2);
3025 dev_err(&adapter->pdev->dev,
3026 "Couldn't alloc an SKB for Rx\n");
3030 adapter->net_stats.rx_bytes += rfd->len;
3033 * Note - ring_index for fbr[] array is reversed,
3036 memcpy(skb_put(skb, rfd->len),
3037 rx_local->fbr[(ring_index == 0 ? 1 : 0)]->virt[buff_index],
3040 skb->dev = adapter->netdev;
3041 skb->protocol = eth_type_trans(skb, adapter->netdev);
3042 skb->ip_summed = CHECKSUM_NONE;
3049 nic_return_rfd(adapter, rfd);
3054 * et131x_handle_recv_interrupt - Interrupt handler for receive processing
3055 * @adapter: pointer to our adapter
3057 * Assumption, Rcv spinlock has been acquired.
3059 static void et131x_handle_recv_interrupt(struct et131x_adapter *adapter)
3061 struct rfd *rfd = NULL;
3065 /* Process up to available RFD's */
3066 while (count < NUM_PACKETS_HANDLED) {
3067 if (list_empty(&adapter->rx_ring.recv_list)) {
3068 WARN_ON(adapter->rx_ring.num_ready_recv != 0);
3073 rfd = nic_rx_pkts(adapter);
3078 /* Do not receive any packets until a filter has been set.
3079 * Do not receive any packets until we have link.
3080 * If length is zero, return the RFD in order to advance the
3083 if (!adapter->packet_filter ||
3084 !netif_carrier_ok(adapter->netdev) ||
3088 /* Increment the number of packets we received */
3089 adapter->net_stats.rx_packets++;
3091 /* Set the status on the packet, either resources or success */
3092 if (adapter->rx_ring.num_ready_recv < RFD_LOW_WATER_MARK) {
3093 dev_warn(&adapter->pdev->dev,
3094 "RFD's are running out\n");
3099 if (count == NUM_PACKETS_HANDLED || !done) {
3100 adapter->rx_ring.unfinished_receives = true;
3101 writel(PARM_TX_TIME_INT_DEF * NANO_IN_A_MICRO,
3102 &adapter->regs->global.watchdog_timer);
3104 /* Watchdog timer will disable itself if appropriate. */
3105 adapter->rx_ring.unfinished_receives = false;
3109 * et131x_tx_dma_memory_alloc
3110 * @adapter: pointer to our private adapter structure
3112 * Returns 0 on success and errno on failure (as defined in errno.h).
3114 * Allocates memory that will be visible both to the device and to the CPU.
3115 * The OS will pass us packets, pointers to which we will insert in the Tx
3116 * Descriptor queue. The device will read this queue to find the packets in
3117 * memory. The device will update the "status" in memory each time it xmits a
3120 static int et131x_tx_dma_memory_alloc(struct et131x_adapter *adapter)
3123 struct tx_ring *tx_ring = &adapter->tx_ring;
3125 /* Allocate memory for the TCB's (Transmit Control Block) */
3126 adapter->tx_ring.tcb_ring =
3127 kcalloc(NUM_TCB, sizeof(struct tcb), GFP_ATOMIC | GFP_DMA);
3128 if (!adapter->tx_ring.tcb_ring) {
3129 dev_err(&adapter->pdev->dev, "Cannot alloc memory for TCBs\n");
3133 /* Allocate enough memory for the Tx descriptor ring, and allocate
3134 * some extra so that the ring can be aligned on a 4k boundary.
3136 desc_size = (sizeof(struct tx_desc) * NUM_DESC_PER_RING_TX) + 4096 - 1;
3137 tx_ring->tx_desc_ring =
3138 (struct tx_desc *) dma_alloc_coherent(&adapter->pdev->dev,
3140 &tx_ring->tx_desc_ring_pa,
3142 if (!adapter->tx_ring.tx_desc_ring) {
3143 dev_err(&adapter->pdev->dev,
3144 "Cannot alloc memory for Tx Ring\n");
3148 /* Save physical address
3150 * NOTE: dma_alloc_coherent(), used above to alloc DMA regions,
3151 * ALWAYS returns SAC (32-bit) addresses. If DAC (64-bit) addresses
3152 * are ever returned, make sure the high part is retrieved here before
3153 * storing the adjusted address.
3155 /* Allocate memory for the Tx status block */
3156 tx_ring->tx_status = dma_alloc_coherent(&adapter->pdev->dev,
3158 &tx_ring->tx_status_pa,
3160 if (!adapter->tx_ring.tx_status_pa) {
3161 dev_err(&adapter->pdev->dev,
3162 "Cannot alloc memory for Tx status block\n");
3169 * et131x_tx_dma_memory_free - Free all memory allocated within this module
3170 * @adapter: pointer to our private adapter structure
3172 * Returns 0 on success and errno on failure (as defined in errno.h).
3174 static void et131x_tx_dma_memory_free(struct et131x_adapter *adapter)
3178 if (adapter->tx_ring.tx_desc_ring) {
3179 /* Free memory relating to Tx rings here */
3180 desc_size = (sizeof(struct tx_desc) * NUM_DESC_PER_RING_TX)
3182 dma_free_coherent(&adapter->pdev->dev,
3184 adapter->tx_ring.tx_desc_ring,
3185 adapter->tx_ring.tx_desc_ring_pa);
3186 adapter->tx_ring.tx_desc_ring = NULL;
3189 /* Free memory for the Tx status block */
3190 if (adapter->tx_ring.tx_status) {
3191 dma_free_coherent(&adapter->pdev->dev,
3193 adapter->tx_ring.tx_status,
3194 adapter->tx_ring.tx_status_pa);
3196 adapter->tx_ring.tx_status = NULL;
3198 /* Free the memory for the tcb structures */
3199 kfree(adapter->tx_ring.tcb_ring);
3203 * nic_send_packet - NIC specific send handler for version B silicon.
3204 * @adapter: pointer to our adapter
3205 * @tcb: pointer to struct tcb
3207 * Returns 0 or errno.
3209 static int nic_send_packet(struct et131x_adapter *adapter, struct tcb *tcb)
3212 struct tx_desc desc[24]; /* 24 x 16 byte */
3214 u32 thiscopy, remainder;
3215 struct sk_buff *skb = tcb->skb;
3216 u32 nr_frags = skb_shinfo(skb)->nr_frags + 1;
3217 struct skb_frag_struct *frags = &skb_shinfo(skb)->frags[0];
3218 unsigned long flags;
3219 struct phy_device *phydev = adapter->phydev;
3220 dma_addr_t dma_addr;
3222 /* Part of the optimizations of this send routine restrict us to
3223 * sending 24 fragments at a pass. In practice we should never see
3224 * more than 5 fragments.
3226 * NOTE: The older version of this function (below) can handle any
3227 * number of fragments. If needed, we can call this function,
3228 * although it is less efficient.
3233 memset(desc, 0, sizeof(struct tx_desc) * (nr_frags + 1));
3235 for (i = 0; i < nr_frags; i++) {
3236 /* If there is something in this element, lets get a
3237 * descriptor from the ring and get the necessary data
3240 /* If the fragments are smaller than a standard MTU,
3241 * then map them to a single descriptor in the Tx
3242 * Desc ring. However, if they're larger, as is
3243 * possible with support for jumbo packets, then
3244 * split them each across 2 descriptors.
3246 * This will work until we determine why the hardware
3247 * doesn't seem to like large fragments.
3249 if (skb_headlen(skb) <= 1514) {
3250 /* Low 16bits are length, high is vlan and
3251 unused currently so zero */
3252 desc[frag].len_vlan = skb_headlen(skb);
3253 dma_addr = dma_map_single(&adapter->pdev->dev,
3257 desc[frag].addr_lo = lower_32_bits(dma_addr);
3258 desc[frag].addr_hi = upper_32_bits(dma_addr);
3261 desc[frag].len_vlan = skb_headlen(skb) / 2;
3262 dma_addr = dma_map_single(&adapter->pdev->dev,
3264 (skb_headlen(skb) / 2),
3266 desc[frag].addr_lo = lower_32_bits(dma_addr);
3267 desc[frag].addr_hi = upper_32_bits(dma_addr);
3270 desc[frag].len_vlan = skb_headlen(skb) / 2;
3271 dma_addr = dma_map_single(&adapter->pdev->dev,
3273 (skb_headlen(skb) / 2),
3274 (skb_headlen(skb) / 2),
3276 desc[frag].addr_lo = lower_32_bits(dma_addr);
3277 desc[frag].addr_hi = upper_32_bits(dma_addr);
3281 desc[frag].len_vlan = frags[i - 1].size;
3282 dma_addr = skb_frag_dma_map(&adapter->pdev->dev,
3287 desc[frag].addr_lo = lower_32_bits(dma_addr);
3288 desc[frag].addr_hi = upper_32_bits(dma_addr);
3293 if (phydev && phydev->speed == SPEED_1000) {
3294 if (++adapter->tx_ring.since_irq == PARM_TX_NUM_BUFS_DEF) {
3295 /* Last element & Interrupt flag */
3296 desc[frag - 1].flags = 0x5;
3297 adapter->tx_ring.since_irq = 0;
3298 } else { /* Last element */
3299 desc[frag - 1].flags = 0x1;
3302 desc[frag - 1].flags = 0x5;
3304 desc[0].flags |= 2; /* First element flag */
3306 tcb->index_start = adapter->tx_ring.send_idx;
3309 spin_lock_irqsave(&adapter->send_hw_lock, flags);
3311 thiscopy = NUM_DESC_PER_RING_TX -
3312 INDEX10(adapter->tx_ring.send_idx);
3314 if (thiscopy >= frag) {
3318 remainder = frag - thiscopy;
3321 memcpy(adapter->tx_ring.tx_desc_ring +
3322 INDEX10(adapter->tx_ring.send_idx), desc,
3323 sizeof(struct tx_desc) * thiscopy);
3325 add_10bit(&adapter->tx_ring.send_idx, thiscopy);
3327 if (INDEX10(adapter->tx_ring.send_idx) == 0 ||
3328 INDEX10(adapter->tx_ring.send_idx) == NUM_DESC_PER_RING_TX) {
3329 adapter->tx_ring.send_idx &= ~ET_DMA10_MASK;
3330 adapter->tx_ring.send_idx ^= ET_DMA10_WRAP;
3334 memcpy(adapter->tx_ring.tx_desc_ring,
3336 sizeof(struct tx_desc) * remainder);
3338 add_10bit(&adapter->tx_ring.send_idx, remainder);
3341 if (INDEX10(adapter->tx_ring.send_idx) == 0) {
3342 if (adapter->tx_ring.send_idx)
3343 tcb->index = NUM_DESC_PER_RING_TX - 1;
3345 tcb->index = ET_DMA10_WRAP|(NUM_DESC_PER_RING_TX - 1);
3347 tcb->index = adapter->tx_ring.send_idx - 1;
3349 spin_lock(&adapter->tcb_send_qlock);
3351 if (adapter->tx_ring.send_tail)
3352 adapter->tx_ring.send_tail->next = tcb;
3354 adapter->tx_ring.send_head = tcb;
3356 adapter->tx_ring.send_tail = tcb;
3358 WARN_ON(tcb->next != NULL);
3360 adapter->tx_ring.used++;
3362 spin_unlock(&adapter->tcb_send_qlock);
3364 /* Write the new write pointer back to the device. */
3365 writel(adapter->tx_ring.send_idx,
3366 &adapter->regs->txdma.service_request);
3368 /* For Gig only, we use Tx Interrupt coalescing. Enable the software
3369 * timer to wake us up if this packet isn't followed by N more.
3371 if (phydev && phydev->speed == SPEED_1000) {
3372 writel(PARM_TX_TIME_INT_DEF * NANO_IN_A_MICRO,
3373 &adapter->regs->global.watchdog_timer);
3375 spin_unlock_irqrestore(&adapter->send_hw_lock, flags);
3381 * send_packet - Do the work to send a packet
3382 * @skb: the packet(s) to send
3383 * @adapter: a pointer to the device's private adapter structure
3385 * Return 0 in almost all cases; non-zero value in extreme hard failure only.
3387 * Assumption: Send spinlock has been acquired
3389 static int send_packet(struct sk_buff *skb, struct et131x_adapter *adapter)
3392 struct tcb *tcb = NULL;
3394 unsigned long flags;
3396 /* All packets must have at least a MAC address and a protocol type */
3397 if (skb->len < ETH_HLEN)
3400 /* Get a TCB for this packet */
3401 spin_lock_irqsave(&adapter->tcb_ready_qlock, flags);
3403 tcb = adapter->tx_ring.tcb_qhead;
3406 spin_unlock_irqrestore(&adapter->tcb_ready_qlock, flags);
3410 adapter->tx_ring.tcb_qhead = tcb->next;
3412 if (adapter->tx_ring.tcb_qhead == NULL)
3413 adapter->tx_ring.tcb_qtail = NULL;
3415 spin_unlock_irqrestore(&adapter->tcb_ready_qlock, flags);
3419 if (skb->data != NULL && skb_headlen(skb) >= 6) {
3420 shbufva = (u16 *) skb->data;
3422 if ((shbufva[0] == 0xffff) &&
3423 (shbufva[1] == 0xffff) && (shbufva[2] == 0xffff)) {
3424 tcb->flags |= fMP_DEST_BROAD;
3425 } else if ((shbufva[0] & 0x3) == 0x0001) {
3426 tcb->flags |= fMP_DEST_MULTI;
3432 /* Call the NIC specific send handler. */
3433 status = nic_send_packet(adapter, tcb);
3436 spin_lock_irqsave(&adapter->tcb_ready_qlock, flags);
3438 if (adapter->tx_ring.tcb_qtail)
3439 adapter->tx_ring.tcb_qtail->next = tcb;
3441 /* Apparently ready Q is empty. */
3442 adapter->tx_ring.tcb_qhead = tcb;
3444 adapter->tx_ring.tcb_qtail = tcb;
3445 spin_unlock_irqrestore(&adapter->tcb_ready_qlock, flags);
3448 WARN_ON(adapter->tx_ring.used > NUM_TCB);
3453 * et131x_send_packets - This function is called by the OS to send packets
3454 * @skb: the packet(s) to send
3455 * @netdev:device on which to TX the above packet(s)
3457 * Return 0 in almost all cases; non-zero value in extreme hard failure only
3459 static int et131x_send_packets(struct sk_buff *skb, struct net_device *netdev)
3462 struct et131x_adapter *adapter = netdev_priv(netdev);
3464 /* Send these packets
3466 * NOTE: The Linux Tx entry point is only given one packet at a time
3467 * to Tx, so the PacketCount and it's array used makes no sense here
3470 /* TCB is not available */
3471 if (adapter->tx_ring.used >= NUM_TCB) {
3472 /* NOTE: If there's an error on send, no need to queue the
3473 * packet under Linux; if we just send an error up to the
3474 * netif layer, it will resend the skb to us.
3478 /* We need to see if the link is up; if it's not, make the
3479 * netif layer think we're good and drop the packet
3481 if ((adapter->flags & fMP_ADAPTER_FAIL_SEND_MASK) ||
3482 !netif_carrier_ok(netdev)) {
3483 dev_kfree_skb_any(skb);
3486 adapter->net_stats.tx_dropped++;
3488 status = send_packet(skb, adapter);
3489 if (status != 0 && status != -ENOMEM) {
3490 /* On any other error, make netif think we're
3491 * OK and drop the packet
3493 dev_kfree_skb_any(skb);
3495 adapter->net_stats.tx_dropped++;
3503 * free_send_packet - Recycle a struct tcb
3504 * @adapter: pointer to our adapter
3505 * @tcb: pointer to struct tcb
3507 * Complete the packet if necessary
3508 * Assumption - Send spinlock has been acquired
3510 static inline void free_send_packet(struct et131x_adapter *adapter,
3513 unsigned long flags;
3514 struct tx_desc *desc = NULL;
3515 struct net_device_stats *stats = &adapter->net_stats;
3518 if (tcb->flags & fMP_DEST_BROAD)
3519 atomic_inc(&adapter->stats.broadcast_pkts_xmtd);
3520 else if (tcb->flags & fMP_DEST_MULTI)
3521 atomic_inc(&adapter->stats.multicast_pkts_xmtd);
3523 atomic_inc(&adapter->stats.unicast_pkts_xmtd);
3526 stats->tx_bytes += tcb->skb->len;
3528 /* Iterate through the TX descriptors on the ring
3529 * corresponding to this packet and umap the fragments
3533 desc = (struct tx_desc *)
3534 (adapter->tx_ring.tx_desc_ring +
3535 INDEX10(tcb->index_start));
3537 dma_addr = desc->addr_lo;
3538 dma_addr |= (u64)desc->addr_hi << 32;
3540 dma_unmap_single(&adapter->pdev->dev,
3542 desc->len_vlan, DMA_TO_DEVICE);
3544 add_10bit(&tcb->index_start, 1);
3545 if (INDEX10(tcb->index_start) >=
3546 NUM_DESC_PER_RING_TX) {
3547 tcb->index_start &= ~ET_DMA10_MASK;
3548 tcb->index_start ^= ET_DMA10_WRAP;
3550 } while (desc != (adapter->tx_ring.tx_desc_ring +
3551 INDEX10(tcb->index)));
3553 dev_kfree_skb_any(tcb->skb);
3556 memset(tcb, 0, sizeof(struct tcb));
3558 /* Add the TCB to the Ready Q */
3559 spin_lock_irqsave(&adapter->tcb_ready_qlock, flags);
3561 adapter->net_stats.tx_packets++;
3563 if (adapter->tx_ring.tcb_qtail)
3564 adapter->tx_ring.tcb_qtail->next = tcb;
3566 /* Apparently ready Q is empty. */
3567 adapter->tx_ring.tcb_qhead = tcb;
3569 adapter->tx_ring.tcb_qtail = tcb;
3571 spin_unlock_irqrestore(&adapter->tcb_ready_qlock, flags);
3572 WARN_ON(adapter->tx_ring.used < 0);
3576 * et131x_free_busy_send_packets - Free and complete the stopped active sends
3577 * @adapter: pointer to our adapter
3579 * Assumption - Send spinlock has been acquired
3581 static void et131x_free_busy_send_packets(struct et131x_adapter *adapter)
3584 unsigned long flags;
3587 /* Any packets being sent? Check the first TCB on the send list */
3588 spin_lock_irqsave(&adapter->tcb_send_qlock, flags);
3590 tcb = adapter->tx_ring.send_head;
3592 while (tcb != NULL && freed < NUM_TCB) {
3593 struct tcb *next = tcb->next;
3595 adapter->tx_ring.send_head = next;
3598 adapter->tx_ring.send_tail = NULL;
3600 adapter->tx_ring.used--;
3602 spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags);
3605 free_send_packet(adapter, tcb);
3607 spin_lock_irqsave(&adapter->tcb_send_qlock, flags);
3609 tcb = adapter->tx_ring.send_head;
3612 WARN_ON(freed == NUM_TCB);
3614 spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags);
3616 adapter->tx_ring.used = 0;
3620 * et131x_handle_send_interrupt - Interrupt handler for sending processing
3621 * @adapter: pointer to our adapter
3623 * Re-claim the send resources, complete sends and get more to send from
3624 * the send wait queue.
3626 * Assumption - Send spinlock has been acquired
3628 static void et131x_handle_send_interrupt(struct et131x_adapter *adapter)
3630 unsigned long flags;
3635 serviced = readl(&adapter->regs->txdma.new_service_complete);
3636 index = INDEX10(serviced);
3638 /* Has the ring wrapped? Process any descriptors that do not have
3639 * the same "wrap" indicator as the current completion indicator
3641 spin_lock_irqsave(&adapter->tcb_send_qlock, flags);
3643 tcb = adapter->tx_ring.send_head;
3646 ((serviced ^ tcb->index) & ET_DMA10_WRAP) &&
3647 index < INDEX10(tcb->index)) {
3648 adapter->tx_ring.used--;
3649 adapter->tx_ring.send_head = tcb->next;
3650 if (tcb->next == NULL)
3651 adapter->tx_ring.send_tail = NULL;
3653 spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags);
3654 free_send_packet(adapter, tcb);
3655 spin_lock_irqsave(&adapter->tcb_send_qlock, flags);
3657 /* Goto the next packet */
3658 tcb = adapter->tx_ring.send_head;
3661 !((serviced ^ tcb->index) & ET_DMA10_WRAP)
3662 && index > (tcb->index & ET_DMA10_MASK)) {
3663 adapter->tx_ring.used--;
3664 adapter->tx_ring.send_head = tcb->next;
3665 if (tcb->next == NULL)
3666 adapter->tx_ring.send_tail = NULL;
3668 spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags);
3669 free_send_packet(adapter, tcb);
3670 spin_lock_irqsave(&adapter->tcb_send_qlock, flags);
3672 /* Goto the next packet */
3673 tcb = adapter->tx_ring.send_head;
3676 /* Wake up the queue when we hit a low-water mark */
3677 if (adapter->tx_ring.used <= NUM_TCB / 3)
3678 netif_wake_queue(adapter->netdev);
3680 spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags);
3683 static int et131x_get_settings(struct net_device *netdev,
3684 struct ethtool_cmd *cmd)
3686 struct et131x_adapter *adapter = netdev_priv(netdev);
3688 return phy_ethtool_gset(adapter->phydev, cmd);
3691 static int et131x_set_settings(struct net_device *netdev,
3692 struct ethtool_cmd *cmd)
3694 struct et131x_adapter *adapter = netdev_priv(netdev);
3696 return phy_ethtool_sset(adapter->phydev, cmd);
3699 static int et131x_get_regs_len(struct net_device *netdev)
3701 #define ET131X_REGS_LEN 256
3702 return ET131X_REGS_LEN * sizeof(u32);
3705 static void et131x_get_regs(struct net_device *netdev,
3706 struct ethtool_regs *regs, void *regs_data)
3708 struct et131x_adapter *adapter = netdev_priv(netdev);
3709 struct address_map __iomem *aregs = adapter->regs;
3710 u32 *regs_buff = regs_data;
3713 memset(regs_data, 0, et131x_get_regs_len(netdev));
3715 regs->version = (1 << 24) | (adapter->pdev->revision << 16) |
3716 adapter->pdev->device;
3719 et131x_mii_read(adapter, MII_BMCR, (u16 *)®s_buff[num++]);
3720 et131x_mii_read(adapter, MII_BMSR, (u16 *)®s_buff[num++]);
3721 et131x_mii_read(adapter, MII_PHYSID1, (u16 *)®s_buff[num++]);
3722 et131x_mii_read(adapter, MII_PHYSID2, (u16 *)®s_buff[num++]);
3723 et131x_mii_read(adapter, MII_ADVERTISE, (u16 *)®s_buff[num++]);
3724 et131x_mii_read(adapter, MII_LPA, (u16 *)®s_buff[num++]);
3725 et131x_mii_read(adapter, MII_EXPANSION, (u16 *)®s_buff[num++]);
3726 /* Autoneg next page transmit reg */
3727 et131x_mii_read(adapter, 0x07, (u16 *)®s_buff[num++]);
3728 /* Link partner next page reg */
3729 et131x_mii_read(adapter, 0x08, (u16 *)®s_buff[num++]);
3730 et131x_mii_read(adapter, MII_CTRL1000, (u16 *)®s_buff[num++]);
3731 et131x_mii_read(adapter, MII_STAT1000, (u16 *)®s_buff[num++]);
3732 et131x_mii_read(adapter, MII_ESTATUS, (u16 *)®s_buff[num++]);
3733 et131x_mii_read(adapter, PHY_INDEX_REG, (u16 *)®s_buff[num++]);
3734 et131x_mii_read(adapter, PHY_DATA_REG, (u16 *)®s_buff[num++]);
3735 et131x_mii_read(adapter, PHY_MPHY_CONTROL_REG,
3736 (u16 *)®s_buff[num++]);
3737 et131x_mii_read(adapter, PHY_LOOPBACK_CONTROL,
3738 (u16 *)®s_buff[num++]);
3739 et131x_mii_read(adapter, PHY_LOOPBACK_CONTROL+1,
3740 (u16 *)®s_buff[num++]);
3741 et131x_mii_read(adapter, PHY_REGISTER_MGMT_CONTROL,
3742 (u16 *)®s_buff[num++]);
3743 et131x_mii_read(adapter, PHY_CONFIG, (u16 *)®s_buff[num++]);
3744 et131x_mii_read(adapter, PHY_PHY_CONTROL, (u16 *)®s_buff[num++]);
3745 et131x_mii_read(adapter, PHY_INTERRUPT_MASK, (u16 *)®s_buff[num++]);
3746 et131x_mii_read(adapter, PHY_INTERRUPT_STATUS,
3747 (u16 *)®s_buff[num++]);
3748 et131x_mii_read(adapter, PHY_PHY_STATUS, (u16 *)®s_buff[num++]);
3749 et131x_mii_read(adapter, PHY_LED_1, (u16 *)®s_buff[num++]);
3750 et131x_mii_read(adapter, PHY_LED_2, (u16 *)®s_buff[num++]);
3753 regs_buff[num++] = readl(&aregs->global.txq_start_addr);
3754 regs_buff[num++] = readl(&aregs->global.txq_end_addr);
3755 regs_buff[num++] = readl(&aregs->global.rxq_start_addr);
3756 regs_buff[num++] = readl(&aregs->global.rxq_end_addr);
3757 regs_buff[num++] = readl(&aregs->global.pm_csr);
3758 regs_buff[num++] = adapter->stats.interrupt_status;
3759 regs_buff[num++] = readl(&aregs->global.int_mask);
3760 regs_buff[num++] = readl(&aregs->global.int_alias_clr_en);
3761 regs_buff[num++] = readl(&aregs->global.int_status_alias);
3762 regs_buff[num++] = readl(&aregs->global.sw_reset);
3763 regs_buff[num++] = readl(&aregs->global.slv_timer);
3764 regs_buff[num++] = readl(&aregs->global.msi_config);
3765 regs_buff[num++] = readl(&aregs->global.loopback);
3766 regs_buff[num++] = readl(&aregs->global.watchdog_timer);
3769 regs_buff[num++] = readl(&aregs->txdma.csr);
3770 regs_buff[num++] = readl(&aregs->txdma.pr_base_hi);
3771 regs_buff[num++] = readl(&aregs->txdma.pr_base_lo);
3772 regs_buff[num++] = readl(&aregs->txdma.pr_num_des);
3773 regs_buff[num++] = readl(&aregs->txdma.txq_wr_addr);
3774 regs_buff[num++] = readl(&aregs->txdma.txq_wr_addr_ext);
3775 regs_buff[num++] = readl(&aregs->txdma.txq_rd_addr);
3776 regs_buff[num++] = readl(&aregs->txdma.dma_wb_base_hi);
3777 regs_buff[num++] = readl(&aregs->txdma.dma_wb_base_lo);
3778 regs_buff[num++] = readl(&aregs->txdma.service_request);
3779 regs_buff[num++] = readl(&aregs->txdma.service_complete);
3780 regs_buff[num++] = readl(&aregs->txdma.cache_rd_index);
3781 regs_buff[num++] = readl(&aregs->txdma.cache_wr_index);
3782 regs_buff[num++] = readl(&aregs->txdma.tx_dma_error);
3783 regs_buff[num++] = readl(&aregs->txdma.desc_abort_cnt);
3784 regs_buff[num++] = readl(&aregs->txdma.payload_abort_cnt);
3785 regs_buff[num++] = readl(&aregs->txdma.writeback_abort_cnt);
3786 regs_buff[num++] = readl(&aregs->txdma.desc_timeout_cnt);
3787 regs_buff[num++] = readl(&aregs->txdma.payload_timeout_cnt);
3788 regs_buff[num++] = readl(&aregs->txdma.writeback_timeout_cnt);
3789 regs_buff[num++] = readl(&aregs->txdma.desc_error_cnt);
3790 regs_buff[num++] = readl(&aregs->txdma.payload_error_cnt);
3791 regs_buff[num++] = readl(&aregs->txdma.writeback_error_cnt);
3792 regs_buff[num++] = readl(&aregs->txdma.dropped_tlp_cnt);
3793 regs_buff[num++] = readl(&aregs->txdma.new_service_complete);
3794 regs_buff[num++] = readl(&aregs->txdma.ethernet_packet_cnt);
3797 regs_buff[num++] = readl(&aregs->rxdma.csr);
3798 regs_buff[num++] = readl(&aregs->rxdma.dma_wb_base_hi);
3799 regs_buff[num++] = readl(&aregs->rxdma.dma_wb_base_lo);
3800 regs_buff[num++] = readl(&aregs->rxdma.num_pkt_done);
3801 regs_buff[num++] = readl(&aregs->rxdma.max_pkt_time);
3802 regs_buff[num++] = readl(&aregs->rxdma.rxq_rd_addr);
3803 regs_buff[num++] = readl(&aregs->rxdma.rxq_rd_addr_ext);
3804 regs_buff[num++] = readl(&aregs->rxdma.rxq_wr_addr);
3805 regs_buff[num++] = readl(&aregs->rxdma.psr_base_hi);
3806 regs_buff[num++] = readl(&aregs->rxdma.psr_base_lo);
3807 regs_buff[num++] = readl(&aregs->rxdma.psr_num_des);
3808 regs_buff[num++] = readl(&aregs->rxdma.psr_avail_offset);
3809 regs_buff[num++] = readl(&aregs->rxdma.psr_full_offset);
3810 regs_buff[num++] = readl(&aregs->rxdma.psr_access_index);
3811 regs_buff[num++] = readl(&aregs->rxdma.psr_min_des);
3812 regs_buff[num++] = readl(&aregs->rxdma.fbr0_base_lo);
3813 regs_buff[num++] = readl(&aregs->rxdma.fbr0_base_hi);
3814 regs_buff[num++] = readl(&aregs->rxdma.fbr0_num_des);
3815 regs_buff[num++] = readl(&aregs->rxdma.fbr0_avail_offset);
3816 regs_buff[num++] = readl(&aregs->rxdma.fbr0_full_offset);
3817 regs_buff[num++] = readl(&aregs->rxdma.fbr0_rd_index);
3818 regs_buff[num++] = readl(&aregs->rxdma.fbr0_min_des);
3819 regs_buff[num++] = readl(&aregs->rxdma.fbr1_base_lo);
3820 regs_buff[num++] = readl(&aregs->rxdma.fbr1_base_hi);
3821 regs_buff[num++] = readl(&aregs->rxdma.fbr1_num_des);
3822 regs_buff[num++] = readl(&aregs->rxdma.fbr1_avail_offset);
3823 regs_buff[num++] = readl(&aregs->rxdma.fbr1_full_offset);
3824 regs_buff[num++] = readl(&aregs->rxdma.fbr1_rd_index);
3825 regs_buff[num++] = readl(&aregs->rxdma.fbr1_min_des);
3828 #define ET131X_DRVINFO_LEN 32 /* value from ethtool.h */
3829 static void et131x_get_drvinfo(struct net_device *netdev,
3830 struct ethtool_drvinfo *info)
3832 struct et131x_adapter *adapter = netdev_priv(netdev);
3834 strncpy(info->driver, DRIVER_NAME, ET131X_DRVINFO_LEN);
3835 strncpy(info->version, DRIVER_VERSION, ET131X_DRVINFO_LEN);
3836 strncpy(info->bus_info, pci_name(adapter->pdev), ET131X_DRVINFO_LEN);
3839 static struct ethtool_ops et131x_ethtool_ops = {
3840 .get_settings = et131x_get_settings,
3841 .set_settings = et131x_set_settings,
3842 .get_drvinfo = et131x_get_drvinfo,
3843 .get_regs_len = et131x_get_regs_len,
3844 .get_regs = et131x_get_regs,
3845 .get_link = ethtool_op_get_link,
3848 * et131x_hwaddr_init - set up the MAC Address on the ET1310
3849 * @adapter: pointer to our private adapter structure
3851 static void et131x_hwaddr_init(struct et131x_adapter *adapter)
3853 /* If have our default mac from init and no mac address from
3854 * EEPROM then we need to generate the last octet and set it on the
3857 if (is_zero_ether_addr(adapter->rom_addr)) {
3859 * We need to randomly generate the last octet so we
3860 * decrease our chances of setting the mac address to
3861 * same as another one of our cards in the system
3863 get_random_bytes(&adapter->addr[5], 1);
3865 * We have the default value in the register we are
3866 * working with so we need to copy the current
3867 * address into the permanent address
3869 memcpy(adapter->rom_addr,
3870 adapter->addr, ETH_ALEN);
3872 /* We do not have an override address, so set the
3873 * current address to the permanent address and add
3876 memcpy(adapter->addr,
3877 adapter->rom_addr, ETH_ALEN);
3882 * et131x_pci_init - initial PCI setup
3883 * @adapter: pointer to our private adapter structure
3884 * @pdev: our PCI device
3886 * Perform the initial setup of PCI registers and if possible initialise
3887 * the MAC address. At this point the I/O registers have yet to be mapped
3889 static int et131x_pci_init(struct et131x_adapter *adapter,
3890 struct pci_dev *pdev)
3895 rc = et131x_init_eeprom(adapter);
3899 if (!pci_is_pcie(pdev)) {
3900 dev_err(&pdev->dev, "Missing PCIe capabilities\n");
3904 /* Let's set up the PORT LOGIC Register. First we need to know what
3905 * the max_payload_size is
3907 if (pcie_capability_read_word(pdev, PCI_EXP_DEVCAP, &max_payload)) {
3909 "Could not read PCI config space for Max Payload Size\n");
3913 /* Program the Ack/Nak latency and replay timers */
3914 max_payload &= 0x07;
3916 if (max_payload < 2) {
3917 static const u16 acknak[2] = { 0x76, 0xD0 };
3918 static const u16 replay[2] = { 0x1E0, 0x2ED };
3920 if (pci_write_config_word(pdev, ET1310_PCI_ACK_NACK,
3921 acknak[max_payload])) {
3923 "Could not write PCI config space for ACK/NAK\n");
3926 if (pci_write_config_word(pdev, ET1310_PCI_REPLAY,
3927 replay[max_payload])) {
3929 "Could not write PCI config space for Replay Timer\n");
3934 /* l0s and l1 latency timers. We are using default values.
3935 * Representing 001 for L0s and 010 for L1
3937 if (pci_write_config_byte(pdev, ET1310_PCI_L0L1LATENCY, 0x11)) {
3939 "Could not write PCI config space for Latency Timers\n");
3943 /* Change the max read size to 2k */
3944 if (pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
3945 PCI_EXP_DEVCTL_READRQ, 0x4 << 12)) {
3947 "Couldn't change PCI config space for Max read size\n");
3951 /* Get MAC address from config space if an eeprom exists, otherwise
3952 * the MAC address there will not be valid
3954 if (!adapter->has_eeprom) {
3955 et131x_hwaddr_init(adapter);
3959 for (i = 0; i < ETH_ALEN; i++) {
3960 if (pci_read_config_byte(pdev, ET1310_PCI_MAC_ADDRESS + i,
3961 adapter->rom_addr + i)) {
3962 dev_err(&pdev->dev, "Could not read PCI config space for MAC address\n");
3966 memcpy(adapter->addr, adapter->rom_addr, ETH_ALEN);
3975 * et131x_error_timer_handler
3976 * @data: timer-specific variable; here a pointer to our adapter structure
3978 * The routine called when the error timer expires, to track the number of
3981 static void et131x_error_timer_handler(unsigned long data)
3983 struct et131x_adapter *adapter = (struct et131x_adapter *) data;
3984 struct phy_device *phydev = adapter->phydev;
3986 if (et1310_in_phy_coma(adapter)) {
3987 /* Bring the device immediately out of coma, to
3988 * prevent it from sleeping indefinitely, this
3989 * mechanism could be improved! */
3990 et1310_disable_phy_coma(adapter);
3991 adapter->boot_coma = 20;
3993 et1310_update_macstat_host_counters(adapter);
3996 if (!phydev->link && adapter->boot_coma < 11)
3997 adapter->boot_coma++;
3999 if (adapter->boot_coma == 10) {
4000 if (!phydev->link) {
4001 if (!et1310_in_phy_coma(adapter)) {
4002 /* NOTE - This was originally a 'sync with
4003 * interrupt'. How to do that under Linux?
4005 et131x_enable_interrupts(adapter);
4006 et1310_enable_phy_coma(adapter);
4011 /* This is a periodic timer, so reschedule */
4012 mod_timer(&adapter->error_timer, jiffies +
4013 TX_ERROR_PERIOD * HZ / 1000);
4017 * et131x_adapter_memory_alloc
4018 * @adapter: pointer to our private adapter structure
4020 * Returns 0 on success, errno on failure (as defined in errno.h).
4022 * Allocate all the memory blocks for send, receive and others.
4024 static int et131x_adapter_memory_alloc(struct et131x_adapter *adapter)
4028 /* Allocate memory for the Tx Ring */
4029 status = et131x_tx_dma_memory_alloc(adapter);
4031 dev_err(&adapter->pdev->dev,
4032 "et131x_tx_dma_memory_alloc FAILED\n");
4035 /* Receive buffer memory allocation */
4036 status = et131x_rx_dma_memory_alloc(adapter);
4038 dev_err(&adapter->pdev->dev,
4039 "et131x_rx_dma_memory_alloc FAILED\n");
4040 et131x_tx_dma_memory_free(adapter);
4044 /* Init receive data structures */
4045 status = et131x_init_recv(adapter);
4047 dev_err(&adapter->pdev->dev,
4048 "et131x_init_recv FAILED\n");
4049 et131x_tx_dma_memory_free(adapter);
4050 et131x_rx_dma_memory_free(adapter);
4056 * et131x_adapter_memory_free - Free all memory allocated for use by Tx & Rx
4057 * @adapter: pointer to our private adapter structure
4059 static void et131x_adapter_memory_free(struct et131x_adapter *adapter)
4061 /* Free DMA memory */
4062 et131x_tx_dma_memory_free(adapter);
4063 et131x_rx_dma_memory_free(adapter);
4066 static void et131x_adjust_link(struct net_device *netdev)
4068 struct et131x_adapter *adapter = netdev_priv(netdev);
4069 struct phy_device *phydev = adapter->phydev;
4071 if (netif_carrier_ok(netdev)) {
4072 adapter->boot_coma = 20;
4074 if (phydev && phydev->speed == SPEED_10) {
4076 * NOTE - Is there a way to query this without
4078 * && TRU_QueryCoreType(adapter->hTruePhy, 0)==
4079 * EMI_TRUEPHY_A13O) {
4083 et131x_mii_read(adapter, PHY_MPHY_CONTROL_REG,
4085 et131x_mii_write(adapter, PHY_MPHY_CONTROL_REG,
4087 et131x_mii_write(adapter, PHY_INDEX_REG,
4088 register18 | 0x8402);
4089 et131x_mii_write(adapter, PHY_DATA_REG,
4091 et131x_mii_write(adapter, PHY_MPHY_CONTROL_REG,
4095 et1310_config_flow_control(adapter);
4097 if (phydev && phydev->speed == SPEED_1000 &&
4098 adapter->registry_jumbo_packet > 2048) {
4101 et131x_mii_read(adapter, PHY_CONFIG, ®);
4102 reg &= ~ET_PHY_CONFIG_TX_FIFO_DEPTH;
4103 reg |= ET_PHY_CONFIG_FIFO_DEPTH_32;
4104 et131x_mii_write(adapter, PHY_CONFIG, reg);
4107 et131x_set_rx_dma_timer(adapter);
4108 et1310_config_mac_regs2(adapter);
4111 if (phydev && phydev->link != adapter->link) {
4113 * Check to see if we are in coma mode and if
4114 * so, disable it because we will not be able
4115 * to read PHY values until we are out.
4117 if (et1310_in_phy_coma(adapter))
4118 et1310_disable_phy_coma(adapter);
4121 adapter->boot_coma = 20;
4123 dev_warn(&adapter->pdev->dev,
4124 "Link down - cable problem ?\n");
4125 adapter->boot_coma = 0;
4127 if (phydev->speed == SPEED_10) {
4128 /* NOTE - Is there a way to query this without
4130 * && TRU_QueryCoreType(adapter->hTruePhy, 0) ==
4135 et131x_mii_read(adapter, PHY_MPHY_CONTROL_REG,
4137 et131x_mii_write(adapter, PHY_MPHY_CONTROL_REG,
4139 et131x_mii_write(adapter, PHY_INDEX_REG,
4140 register18 | 0x8402);
4141 et131x_mii_write(adapter, PHY_DATA_REG,
4143 et131x_mii_write(adapter, PHY_MPHY_CONTROL_REG,
4147 /* Free the packets being actively sent & stopped */
4148 et131x_free_busy_send_packets(adapter);
4150 /* Re-initialize the send structures */
4151 et131x_init_send(adapter);
4154 * Bring the device back to the state it was during
4155 * init prior to autonegotiation being complete. This
4156 * way, when we get the auto-neg complete interrupt,
4157 * we can complete init by calling config_mac_regs2.
4159 et131x_soft_reset(adapter);
4161 /* Setup ET1310 as per the documentation */
4162 et131x_adapter_setup(adapter);
4164 /* perform reset of tx/rx */
4165 et131x_disable_txrx(netdev);
4166 et131x_enable_txrx(netdev);
4169 adapter->link = phydev->link;
4171 phy_print_status(phydev);
4175 static int et131x_mii_probe(struct net_device *netdev)
4177 struct et131x_adapter *adapter = netdev_priv(netdev);
4178 struct phy_device *phydev = NULL;
4180 phydev = phy_find_first(adapter->mii_bus);
4182 dev_err(&adapter->pdev->dev, "no PHY found\n");
4186 phydev = phy_connect(netdev, dev_name(&phydev->dev),
4187 &et131x_adjust_link, 0, PHY_INTERFACE_MODE_MII);
4189 if (IS_ERR(phydev)) {
4190 dev_err(&adapter->pdev->dev, "Could not attach to PHY\n");
4191 return PTR_ERR(phydev);
4194 phydev->supported &= (SUPPORTED_10baseT_Half
4195 | SUPPORTED_10baseT_Full
4196 | SUPPORTED_100baseT_Half
4197 | SUPPORTED_100baseT_Full
4202 if (adapter->pdev->device != ET131X_PCI_DEVICE_ID_FAST)
4203 phydev->supported |= SUPPORTED_1000baseT_Full;
4205 phydev->advertising = phydev->supported;
4206 adapter->phydev = phydev;
4208 dev_info(&adapter->pdev->dev, "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
4209 phydev->drv->name, dev_name(&phydev->dev));
4215 * et131x_adapter_init
4216 * @adapter: pointer to the private adapter struct
4217 * @pdev: pointer to the PCI device
4219 * Initialize the data structures for the et131x_adapter object and link
4220 * them together with the platform provided device structures.
4222 static struct et131x_adapter *et131x_adapter_init(struct net_device *netdev,
4223 struct pci_dev *pdev)
4225 static const u8 default_mac[] = { 0x00, 0x05, 0x3d, 0x00, 0x02, 0x00 };
4227 struct et131x_adapter *adapter;
4229 /* Allocate private adapter struct and copy in relevant information */
4230 adapter = netdev_priv(netdev);
4231 adapter->pdev = pci_dev_get(pdev);
4232 adapter->netdev = netdev;
4234 /* Initialize spinlocks here */
4235 spin_lock_init(&adapter->lock);
4236 spin_lock_init(&adapter->tcb_send_qlock);
4237 spin_lock_init(&adapter->tcb_ready_qlock);
4238 spin_lock_init(&adapter->send_hw_lock);
4239 spin_lock_init(&adapter->rcv_lock);
4240 spin_lock_init(&adapter->rcv_pend_lock);
4241 spin_lock_init(&adapter->fbr_lock);
4242 spin_lock_init(&adapter->phy_lock);
4244 adapter->registry_jumbo_packet = 1514; /* 1514-9216 */
4246 /* Set the MAC address to a default */
4247 memcpy(adapter->addr, default_mac, ETH_ALEN);
4254 * @pdev: a pointer to the device's pci_dev structure
4256 * Registered in the pci_driver structure, this function is called when the
4257 * PCI subsystem detects that a PCI device which matches the information
4258 * contained in the pci_device_id table has been removed.
4260 static void __devexit et131x_pci_remove(struct pci_dev *pdev)
4262 struct net_device *netdev = pci_get_drvdata(pdev);
4263 struct et131x_adapter *adapter = netdev_priv(netdev);
4265 unregister_netdev(netdev);
4266 phy_disconnect(adapter->phydev);
4267 mdiobus_unregister(adapter->mii_bus);
4268 kfree(adapter->mii_bus->irq);
4269 mdiobus_free(adapter->mii_bus);
4271 et131x_adapter_memory_free(adapter);
4272 iounmap(adapter->regs);
4275 free_netdev(netdev);
4276 pci_release_regions(pdev);
4277 pci_disable_device(pdev);
4281 * et131x_up - Bring up a device for use.
4282 * @netdev: device to be opened
4284 static void et131x_up(struct net_device *netdev)
4286 struct et131x_adapter *adapter = netdev_priv(netdev);
4288 et131x_enable_txrx(netdev);
4289 phy_start(adapter->phydev);
4293 * et131x_down - Bring down the device
4294 * @netdev: device to be brought down
4296 static void et131x_down(struct net_device *netdev)
4298 struct et131x_adapter *adapter = netdev_priv(netdev);
4300 /* Save the timestamp for the TX watchdog, prevent a timeout */
4301 netdev->trans_start = jiffies;
4303 phy_stop(adapter->phydev);
4304 et131x_disable_txrx(netdev);
4307 #ifdef CONFIG_PM_SLEEP
4308 static int et131x_suspend(struct device *dev)
4310 struct pci_dev *pdev = to_pci_dev(dev);
4311 struct net_device *netdev = pci_get_drvdata(pdev);
4313 if (netif_running(netdev)) {
4314 netif_device_detach(netdev);
4315 et131x_down(netdev);
4316 pci_save_state(pdev);
4322 static int et131x_resume(struct device *dev)
4324 struct pci_dev *pdev = to_pci_dev(dev);
4325 struct net_device *netdev = pci_get_drvdata(pdev);
4327 if (netif_running(netdev)) {
4328 pci_restore_state(pdev);
4330 netif_device_attach(netdev);
4336 static SIMPLE_DEV_PM_OPS(et131x_pm_ops, et131x_suspend, et131x_resume);
4337 #define ET131X_PM_OPS (&et131x_pm_ops)
4339 #define ET131X_PM_OPS NULL
4343 * et131x_isr - The Interrupt Service Routine for the driver.
4344 * @irq: the IRQ on which the interrupt was received.
4345 * @dev_id: device-specific info (here a pointer to a net_device struct)
4347 * Returns a value indicating if the interrupt was handled.
4349 irqreturn_t et131x_isr(int irq, void *dev_id)
4351 bool handled = true;
4352 struct net_device *netdev = (struct net_device *)dev_id;
4353 struct et131x_adapter *adapter = NULL;
4356 if (!netif_device_present(netdev)) {
4361 adapter = netdev_priv(netdev);
4363 /* If the adapter is in low power state, then it should not
4364 * recognize any interrupt
4367 /* Disable Device Interrupts */
4368 et131x_disable_interrupts(adapter);
4370 /* Get a copy of the value in the interrupt status register
4371 * so we can process the interrupting section
4373 status = readl(&adapter->regs->global.int_status);
4375 if (adapter->flowcontrol == FLOW_TXONLY ||
4376 adapter->flowcontrol == FLOW_BOTH) {
4377 status &= ~INT_MASK_ENABLE;
4379 status &= ~INT_MASK_ENABLE_NO_FLOW;
4382 /* Make sure this is our interrupt */
4385 et131x_enable_interrupts(adapter);
4389 /* This is our interrupt, so process accordingly */
4391 if (status & ET_INTR_WATCHDOG) {
4392 struct tcb *tcb = adapter->tx_ring.send_head;
4395 if (++tcb->stale > 1)
4396 status |= ET_INTR_TXDMA_ISR;
4398 if (adapter->rx_ring.unfinished_receives)
4399 status |= ET_INTR_RXDMA_XFR_DONE;
4400 else if (tcb == NULL)
4401 writel(0, &adapter->regs->global.watchdog_timer);
4403 status &= ~ET_INTR_WATCHDOG;
4407 /* This interrupt has in some way been "handled" by
4408 * the ISR. Either it was a spurious Rx interrupt, or
4409 * it was a Tx interrupt that has been filtered by
4412 et131x_enable_interrupts(adapter);
4416 /* We need to save the interrupt status value for use in our
4417 * DPC. We will clear the software copy of that in that
4420 adapter->stats.interrupt_status = status;
4422 /* Schedule the ISR handler as a bottom-half task in the
4423 * kernel's tq_immediate queue, and mark the queue for
4426 schedule_work(&adapter->task);
4428 return IRQ_RETVAL(handled);
4432 * et131x_isr_handler - The ISR handler
4433 * @p_adapter, a pointer to the device's private adapter structure
4435 * scheduled to run in a deferred context by the ISR. This is where the ISR's
4436 * work actually gets done.
4438 static void et131x_isr_handler(struct work_struct *work)
4440 struct et131x_adapter *adapter =
4441 container_of(work, struct et131x_adapter, task);
4442 u32 status = adapter->stats.interrupt_status;
4443 struct address_map __iomem *iomem = adapter->regs;
4446 * These first two are by far the most common. Once handled, we clear
4447 * their two bits in the status word. If the word is now zero, we
4450 /* Handle all the completed Transmit interrupts */
4451 if (status & ET_INTR_TXDMA_ISR)
4452 et131x_handle_send_interrupt(adapter);
4454 /* Handle all the completed Receives interrupts */
4455 if (status & ET_INTR_RXDMA_XFR_DONE)
4456 et131x_handle_recv_interrupt(adapter);
4458 status &= 0xffffffd7;
4461 /* Handle the TXDMA Error interrupt */
4462 if (status & ET_INTR_TXDMA_ERR) {
4465 /* Following read also clears the register (COR) */
4466 txdma_err = readl(&iomem->txdma.tx_dma_error);
4468 dev_warn(&adapter->pdev->dev,
4469 "TXDMA_ERR interrupt, error = %d\n",
4473 /* Handle Free Buffer Ring 0 and 1 Low interrupt */
4475 (ET_INTR_RXDMA_FB_R0_LOW | ET_INTR_RXDMA_FB_R1_LOW)) {
4477 * This indicates the number of unused buffers in
4478 * RXDMA free buffer ring 0 is <= the limit you
4479 * programmed. Free buffer resources need to be
4480 * returned. Free buffers are consumed as packets
4481 * are passed from the network to the host. The host
4482 * becomes aware of the packets from the contents of
4483 * the packet status ring. This ring is queried when
4484 * the packet done interrupt occurs. Packets are then
4485 * passed to the OS. When the OS is done with the
4486 * packets the resources can be returned to the
4487 * ET1310 for re-use. This interrupt is one method of
4488 * returning resources.
4491 /* If the user has flow control on, then we will
4492 * send a pause packet, otherwise just exit
4494 if (adapter->flowcontrol == FLOW_TXONLY ||
4495 adapter->flowcontrol == FLOW_BOTH) {
4498 /* Tell the device to send a pause packet via
4499 * the back pressure register (bp req and
4502 pm_csr = readl(&iomem->global.pm_csr);
4503 if (!et1310_in_phy_coma(adapter))
4504 writel(3, &iomem->txmac.bp_ctrl);
4508 /* Handle Packet Status Ring Low Interrupt */
4509 if (status & ET_INTR_RXDMA_STAT_LOW) {
4512 * Same idea as with the two Free Buffer Rings.
4513 * Packets going from the network to the host each
4514 * consume a free buffer resource and a packet status
4515 * resource. These resoures are passed to the OS.
4516 * When the OS is done with the resources, they need
4517 * to be returned to the ET1310. This is one method
4518 * of returning the resources.
4522 /* Handle RXDMA Error Interrupt */
4523 if (status & ET_INTR_RXDMA_ERR) {
4525 * The rxdma_error interrupt is sent when a time-out
4526 * on a request issued by the JAGCore has occurred or
4527 * a completion is returned with an un-successful
4528 * status. In both cases the request is considered
4529 * complete. The JAGCore will automatically re-try the
4530 * request in question. Normally information on events
4531 * like these are sent to the host using the "Advanced
4532 * Error Reporting" capability. This interrupt is
4533 * another way of getting similar information. The
4534 * only thing required is to clear the interrupt by
4535 * reading the ISR in the global resources. The
4536 * JAGCore will do a re-try on the request. Normally
4537 * you should never see this interrupt. If you start
4538 * to see this interrupt occurring frequently then
4539 * something bad has occurred. A reset might be the
4544 dev_warn(&adapter->pdev->dev,
4545 "RxDMA_ERR interrupt, error %x\n",
4546 readl(&iomem->txmac.tx_test));
4549 /* Handle the Wake on LAN Event */
4550 if (status & ET_INTR_WOL) {
4552 * This is a secondary interrupt for wake on LAN.
4553 * The driver should never see this, if it does,
4554 * something serious is wrong. We will TRAP the
4555 * message when we are in DBG mode, otherwise we
4558 dev_err(&adapter->pdev->dev, "WAKE_ON_LAN interrupt\n");
4561 /* Let's move on to the TxMac */
4562 if (status & ET_INTR_TXMAC) {
4563 u32 err = readl(&iomem->txmac.err);
4566 * When any of the errors occur and TXMAC generates
4567 * an interrupt to report these errors, it usually
4568 * means that TXMAC has detected an error in the data
4569 * stream retrieved from the on-chip Tx Q. All of
4570 * these errors are catastrophic and TXMAC won't be
4571 * able to recover data when these errors occur. In
4572 * a nutshell, the whole Tx path will have to be reset
4573 * and re-configured afterwards.
4575 dev_warn(&adapter->pdev->dev,
4576 "TXMAC interrupt, error 0x%08x\n",
4579 /* If we are debugging, we want to see this error,
4580 * otherwise we just want the device to be reset and
4585 /* Handle RXMAC Interrupt */
4586 if (status & ET_INTR_RXMAC) {
4588 * These interrupts are catastrophic to the device,
4589 * what we need to do is disable the interrupts and
4590 * set the flag to cause us to reset so we can solve
4593 /* MP_SET_FLAG( adapter,
4594 fMP_ADAPTER_HARDWARE_ERROR); */
4596 dev_warn(&adapter->pdev->dev,
4597 "RXMAC interrupt, error 0x%08x. Requesting reset\n",
4598 readl(&iomem->rxmac.err_reg));
4600 dev_warn(&adapter->pdev->dev,
4601 "Enable 0x%08x, Diag 0x%08x\n",
4602 readl(&iomem->rxmac.ctrl),
4603 readl(&iomem->rxmac.rxq_diag));
4606 * If we are debugging, we want to see this error,
4607 * otherwise we just want the device to be reset and
4612 /* Handle MAC_STAT Interrupt */
4613 if (status & ET_INTR_MAC_STAT) {
4615 * This means at least one of the un-masked counters
4616 * in the MAC_STAT block has rolled over. Use this
4617 * to maintain the top, software managed bits of the
4620 et1310_handle_macstat_interrupt(adapter);
4623 /* Handle SLV Timeout Interrupt */
4624 if (status & ET_INTR_SLV_TIMEOUT) {
4626 * This means a timeout has occurred on a read or
4627 * write request to one of the JAGCore registers. The
4628 * Global Resources block has terminated the request
4629 * and on a read request, returned a "fake" value.
4630 * The most likely reasons are: Bad Address or the
4631 * addressed module is in a power-down state and
4636 et131x_enable_interrupts(adapter);
4640 * et131x_stats - Return the current device statistics.
4641 * @netdev: device whose stats are being queried
4643 * Returns 0 on success, errno on failure (as defined in errno.h)
4645 static struct net_device_stats *et131x_stats(struct net_device *netdev)
4647 struct et131x_adapter *adapter = netdev_priv(netdev);
4648 struct net_device_stats *stats = &adapter->net_stats;
4649 struct ce_stats *devstat = &adapter->stats;
4651 stats->rx_errors = devstat->rx_length_errs +
4652 devstat->rx_align_errs +
4653 devstat->rx_crc_errs +
4654 devstat->rx_code_violations +
4655 devstat->rx_other_errs;
4656 stats->tx_errors = devstat->tx_max_pkt_errs;
4657 stats->multicast = devstat->multicast_pkts_rcvd;
4658 stats->collisions = devstat->tx_collisions;
4660 stats->rx_length_errors = devstat->rx_length_errs;
4661 stats->rx_over_errors = devstat->rx_overflows;
4662 stats->rx_crc_errors = devstat->rx_crc_errs;
4664 /* NOTE: These stats don't have corresponding values in CE_STATS,
4665 * so we're going to have to update these directly from within the
4668 /* stats->rx_bytes = 20; devstat->; */
4669 /* stats->tx_bytes = 20; devstat->; */
4670 /* stats->rx_dropped = devstat->; */
4671 /* stats->tx_dropped = devstat->; */
4673 /* NOTE: Not used, can't find analogous statistics */
4674 /* stats->rx_frame_errors = devstat->; */
4675 /* stats->rx_fifo_errors = devstat->; */
4676 /* stats->rx_missed_errors = devstat->; */
4678 /* stats->tx_aborted_errors = devstat->; */
4679 /* stats->tx_carrier_errors = devstat->; */
4680 /* stats->tx_fifo_errors = devstat->; */
4681 /* stats->tx_heartbeat_errors = devstat->; */
4682 /* stats->tx_window_errors = devstat->; */
4687 * et131x_open - Open the device for use.
4688 * @netdev: device to be opened
4690 * Returns 0 on success, errno on failure (as defined in errno.h)
4692 static int et131x_open(struct net_device *netdev)
4694 struct et131x_adapter *adapter = netdev_priv(netdev);
4695 struct pci_dev *pdev = adapter->pdev;
4696 unsigned int irq = pdev->irq;
4699 /* Start the timer to track NIC errors */
4700 init_timer(&adapter->error_timer);
4701 adapter->error_timer.expires = jiffies + TX_ERROR_PERIOD * HZ / 1000;
4702 adapter->error_timer.function = et131x_error_timer_handler;
4703 adapter->error_timer.data = (unsigned long)adapter;
4704 add_timer(&adapter->error_timer);
4706 result = request_irq(irq, et131x_isr,
4707 IRQF_SHARED, netdev->name, netdev);
4709 dev_err(&pdev->dev, "could not register IRQ %d\n", irq);
4713 adapter->flags |= fMP_ADAPTER_INTERRUPT_IN_USE;
4721 * et131x_close - Close the device
4722 * @netdev: device to be closed
4724 * Returns 0 on success, errno on failure (as defined in errno.h)
4726 static int et131x_close(struct net_device *netdev)
4728 struct et131x_adapter *adapter = netdev_priv(netdev);
4730 et131x_down(netdev);
4732 adapter->flags &= ~fMP_ADAPTER_INTERRUPT_IN_USE;
4733 free_irq(adapter->pdev->irq, netdev);
4735 /* Stop the error timer */
4736 return del_timer_sync(&adapter->error_timer);
4740 * et131x_ioctl - The I/O Control handler for the driver
4741 * @netdev: device on which the control request is being made
4742 * @reqbuf: a pointer to the IOCTL request buffer
4743 * @cmd: the IOCTL command code
4745 * Returns 0 on success, errno on failure (as defined in errno.h)
4747 static int et131x_ioctl(struct net_device *netdev, struct ifreq *reqbuf,
4750 struct et131x_adapter *adapter = netdev_priv(netdev);
4752 if (!adapter->phydev)
4755 return phy_mii_ioctl(adapter->phydev, reqbuf, cmd);
4759 * et131x_set_packet_filter - Configures the Rx Packet filtering on the device
4760 * @adapter: pointer to our private adapter structure
4762 * FIXME: lot of dups with MAC code
4764 * Returns 0 on success, errno on failure
4766 static int et131x_set_packet_filter(struct et131x_adapter *adapter)
4768 int filter = adapter->packet_filter;
4773 ctrl = readl(&adapter->regs->rxmac.ctrl);
4774 pf_ctrl = readl(&adapter->regs->rxmac.pf_ctrl);
4776 /* Default to disabled packet filtering. Enable it in the individual
4777 * case statements that require the device to filter something
4781 /* Set us to be in promiscuous mode so we receive everything, this
4782 * is also true when we get a packet filter of 0
4784 if ((filter & ET131X_PACKET_TYPE_PROMISCUOUS) || filter == 0)
4785 pf_ctrl &= ~7; /* Clear filter bits */
4788 * Set us up with Multicast packet filtering. Three cases are
4789 * possible - (1) we have a multi-cast list, (2) we receive ALL
4790 * multicast entries or (3) we receive none.
4792 if (filter & ET131X_PACKET_TYPE_ALL_MULTICAST)
4793 pf_ctrl &= ~2; /* Multicast filter bit */
4795 et1310_setup_device_for_multicast(adapter);
4800 /* Set us up with Unicast packet filtering */
4801 if (filter & ET131X_PACKET_TYPE_DIRECTED) {
4802 et1310_setup_device_for_unicast(adapter);
4807 /* Set us up with Broadcast packet filtering */
4808 if (filter & ET131X_PACKET_TYPE_BROADCAST) {
4809 pf_ctrl |= 1; /* Broadcast filter bit */
4814 /* Setup the receive mac configuration registers - Packet
4815 * Filter control + the enable / disable for packet filter
4816 * in the control reg.
4818 writel(pf_ctrl, &adapter->regs->rxmac.pf_ctrl);
4819 writel(ctrl, &adapter->regs->rxmac.ctrl);
4825 * et131x_multicast - The handler to configure multicasting on the interface
4826 * @netdev: a pointer to a net_device struct representing the device
4828 static void et131x_multicast(struct net_device *netdev)
4830 struct et131x_adapter *adapter = netdev_priv(netdev);
4832 unsigned long flags;
4833 struct netdev_hw_addr *ha;
4836 spin_lock_irqsave(&adapter->lock, flags);
4838 /* Before we modify the platform-independent filter flags, store them
4839 * locally. This allows us to determine if anything's changed and if
4840 * we even need to bother the hardware
4842 packet_filter = adapter->packet_filter;
4844 /* Clear the 'multicast' flag locally; because we only have a single
4845 * flag to check multicast, and multiple multicast addresses can be
4846 * set, this is the easiest way to determine if more than one
4847 * multicast address is being set.
4849 packet_filter &= ~ET131X_PACKET_TYPE_MULTICAST;
4851 /* Check the net_device flags and set the device independent flags
4855 if (netdev->flags & IFF_PROMISC)
4856 adapter->packet_filter |= ET131X_PACKET_TYPE_PROMISCUOUS;
4858 adapter->packet_filter &= ~ET131X_PACKET_TYPE_PROMISCUOUS;
4860 if (netdev->flags & IFF_ALLMULTI)
4861 adapter->packet_filter |= ET131X_PACKET_TYPE_ALL_MULTICAST;
4863 if (netdev_mc_count(netdev) > NIC_MAX_MCAST_LIST)
4864 adapter->packet_filter |= ET131X_PACKET_TYPE_ALL_MULTICAST;
4866 if (netdev_mc_count(netdev) < 1) {
4867 adapter->packet_filter &= ~ET131X_PACKET_TYPE_ALL_MULTICAST;
4868 adapter->packet_filter &= ~ET131X_PACKET_TYPE_MULTICAST;
4870 adapter->packet_filter |= ET131X_PACKET_TYPE_MULTICAST;
4872 /* Set values in the private adapter struct */
4874 netdev_for_each_mc_addr(ha, netdev) {
4875 if (i == NIC_MAX_MCAST_LIST)
4877 memcpy(adapter->multicast_list[i++], ha->addr, ETH_ALEN);
4879 adapter->multicast_addr_count = i;
4881 /* Are the new flags different from the previous ones? If not, then no
4882 * action is required
4884 * NOTE - This block will always update the multicast_list with the
4885 * hardware, even if the addresses aren't the same.
4887 if (packet_filter != adapter->packet_filter) {
4888 /* Call the device's filter function */
4889 et131x_set_packet_filter(adapter);
4891 spin_unlock_irqrestore(&adapter->lock, flags);
4895 * et131x_tx - The handler to tx a packet on the device
4896 * @skb: data to be Tx'd
4897 * @netdev: device on which data is to be Tx'd
4899 * Returns 0 on success, errno on failure (as defined in errno.h)
4901 static int et131x_tx(struct sk_buff *skb, struct net_device *netdev)
4904 struct et131x_adapter *adapter = netdev_priv(netdev);
4906 /* stop the queue if it's getting full */
4907 if (adapter->tx_ring.used >= NUM_TCB - 1 &&
4908 !netif_queue_stopped(netdev))
4909 netif_stop_queue(netdev);
4911 /* Save the timestamp for the TX timeout watchdog */
4912 netdev->trans_start = jiffies;
4914 /* Call the device-specific data Tx routine */
4915 status = et131x_send_packets(skb, netdev);
4917 /* Check status and manage the netif queue if necessary */
4919 if (status == -ENOMEM)
4920 status = NETDEV_TX_BUSY;
4922 status = NETDEV_TX_OK;
4928 * et131x_tx_timeout - Timeout handler
4929 * @netdev: a pointer to a net_device struct representing the device
4931 * The handler called when a Tx request times out. The timeout period is
4932 * specified by the 'tx_timeo" element in the net_device structure (see
4933 * et131x_alloc_device() to see how this value is set).
4935 static void et131x_tx_timeout(struct net_device *netdev)
4937 struct et131x_adapter *adapter = netdev_priv(netdev);
4939 unsigned long flags;
4941 /* If the device is closed, ignore the timeout */
4942 if (~(adapter->flags & fMP_ADAPTER_INTERRUPT_IN_USE))
4945 /* Any nonrecoverable hardware error?
4946 * Checks adapter->flags for any failure in phy reading
4948 if (adapter->flags & fMP_ADAPTER_NON_RECOVER_ERROR)
4951 /* Hardware failure? */
4952 if (adapter->flags & fMP_ADAPTER_HARDWARE_ERROR) {
4953 dev_err(&adapter->pdev->dev, "hardware error - reset\n");
4957 /* Is send stuck? */
4958 spin_lock_irqsave(&adapter->tcb_send_qlock, flags);
4960 tcb = adapter->tx_ring.send_head;
4965 if (tcb->count > NIC_SEND_HANG_THRESHOLD) {
4966 spin_unlock_irqrestore(&adapter->tcb_send_qlock,
4969 dev_warn(&adapter->pdev->dev,
4970 "Send stuck - reset. tcb->WrIndex %x, flags 0x%08x\n",
4974 adapter->net_stats.tx_errors++;
4976 /* perform reset of tx/rx */
4977 et131x_disable_txrx(netdev);
4978 et131x_enable_txrx(netdev);
4983 spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags);
4987 * et131x_change_mtu - The handler called to change the MTU for the device
4988 * @netdev: device whose MTU is to be changed
4989 * @new_mtu: the desired MTU
4991 * Returns 0 on success, errno on failure (as defined in errno.h)
4993 static int et131x_change_mtu(struct net_device *netdev, int new_mtu)
4996 struct et131x_adapter *adapter = netdev_priv(netdev);
4998 /* Make sure the requested MTU is valid */
4999 if (new_mtu < 64 || new_mtu > 9216)
5002 et131x_disable_txrx(netdev);
5003 et131x_handle_send_interrupt(adapter);
5004 et131x_handle_recv_interrupt(adapter);
5006 /* Set the new MTU */
5007 netdev->mtu = new_mtu;
5009 /* Free Rx DMA memory */
5010 et131x_adapter_memory_free(adapter);
5012 /* Set the config parameter for Jumbo Packet support */
5013 adapter->registry_jumbo_packet = new_mtu + 14;
5014 et131x_soft_reset(adapter);
5016 /* Alloc and init Rx DMA memory */
5017 result = et131x_adapter_memory_alloc(adapter);
5019 dev_warn(&adapter->pdev->dev,
5020 "Change MTU failed; couldn't re-alloc DMA memory\n");
5024 et131x_init_send(adapter);
5026 et131x_hwaddr_init(adapter);
5027 memcpy(netdev->dev_addr, adapter->addr, ETH_ALEN);
5029 /* Init the device with the new settings */
5030 et131x_adapter_setup(adapter);
5032 et131x_enable_txrx(netdev);
5038 * et131x_set_mac_addr - handler to change the MAC address for the device
5039 * @netdev: device whose MAC is to be changed
5040 * @new_mac: the desired MAC address
5042 * Returns 0 on success, errno on failure (as defined in errno.h)
5044 * IMPLEMENTED BY : blux http://berndlux.de 22.01.2007 21:14
5046 static int et131x_set_mac_addr(struct net_device *netdev, void *new_mac)
5049 struct et131x_adapter *adapter = netdev_priv(netdev);
5050 struct sockaddr *address = new_mac;
5054 if (adapter == NULL)
5057 /* Make sure the requested MAC is valid */
5058 if (!is_valid_ether_addr(address->sa_data))
5059 return -EADDRNOTAVAIL;
5061 et131x_disable_txrx(netdev);
5062 et131x_handle_send_interrupt(adapter);
5063 et131x_handle_recv_interrupt(adapter);
5065 /* Set the new MAC */
5066 /* netdev->set_mac_address = &new_mac; */
5068 memcpy(netdev->dev_addr, address->sa_data, netdev->addr_len);
5070 netdev_info(netdev, "Setting MAC address to %pM\n",
5073 /* Free Rx DMA memory */
5074 et131x_adapter_memory_free(adapter);
5076 et131x_soft_reset(adapter);
5078 /* Alloc and init Rx DMA memory */
5079 result = et131x_adapter_memory_alloc(adapter);
5081 dev_err(&adapter->pdev->dev,
5082 "Change MAC failed; couldn't re-alloc DMA memory\n");
5086 et131x_init_send(adapter);
5088 et131x_hwaddr_init(adapter);
5090 /* Init the device with the new settings */
5091 et131x_adapter_setup(adapter);
5093 et131x_enable_txrx(netdev);
5098 static const struct net_device_ops et131x_netdev_ops = {
5099 .ndo_open = et131x_open,
5100 .ndo_stop = et131x_close,
5101 .ndo_start_xmit = et131x_tx,
5102 .ndo_set_rx_mode = et131x_multicast,
5103 .ndo_tx_timeout = et131x_tx_timeout,
5104 .ndo_change_mtu = et131x_change_mtu,
5105 .ndo_set_mac_address = et131x_set_mac_addr,
5106 .ndo_validate_addr = eth_validate_addr,
5107 .ndo_get_stats = et131x_stats,
5108 .ndo_do_ioctl = et131x_ioctl,
5112 * et131x_pci_setup - Perform device initialization
5113 * @pdev: a pointer to the device's pci_dev structure
5114 * @ent: this device's entry in the pci_device_id table
5116 * Returns 0 on success, errno on failure (as defined in errno.h)
5118 * Registered in the pci_driver structure, this function is called when the
5119 * PCI subsystem finds a new PCI device which matches the information
5120 * contained in the pci_device_id table. This routine is the equivalent to
5121 * a device insertion routine.
5123 static int __devinit et131x_pci_setup(struct pci_dev *pdev,
5124 const struct pci_device_id *ent)
5126 struct net_device *netdev;
5127 struct et131x_adapter *adapter;
5131 rc = pci_enable_device(pdev);
5133 dev_err(&pdev->dev, "pci_enable_device() failed\n");
5137 /* Perform some basic PCI checks */
5138 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
5139 dev_err(&pdev->dev, "Can't find PCI device's base address\n");
5144 rc = pci_request_regions(pdev, DRIVER_NAME);
5146 dev_err(&pdev->dev, "Can't get PCI resources\n");
5150 pci_set_master(pdev);
5152 /* Check the DMA addressing support of this device */
5153 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) {
5154 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
5157 "Unable to obtain 64 bit DMA for consistent allocations\n");
5158 goto err_release_res;
5160 } else if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(32))) {
5161 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
5164 "Unable to obtain 32 bit DMA for consistent allocations\n");
5165 goto err_release_res;
5168 dev_err(&pdev->dev, "No usable DMA addressing method\n");
5170 goto err_release_res;
5173 /* Allocate netdev and private adapter structs */
5174 netdev = alloc_etherdev(sizeof(struct et131x_adapter));
5176 dev_err(&pdev->dev, "Couldn't alloc netdev struct\n");
5178 goto err_release_res;
5181 netdev->watchdog_timeo = ET131X_TX_TIMEOUT;
5182 netdev->netdev_ops = &et131x_netdev_ops;
5184 SET_NETDEV_DEV(netdev, &pdev->dev);
5185 SET_ETHTOOL_OPS(netdev, &et131x_ethtool_ops);
5187 adapter = et131x_adapter_init(netdev, pdev);
5189 rc = et131x_pci_init(adapter, pdev);
5193 /* Map the bus-relative registers to system virtual memory */
5194 adapter->regs = pci_ioremap_bar(pdev, 0);
5195 if (!adapter->regs) {
5196 dev_err(&pdev->dev, "Cannot map device registers\n");
5201 /* If Phy COMA mode was enabled when we went down, disable it here. */
5202 writel(ET_PMCSR_INIT, &adapter->regs->global.pm_csr);
5204 /* Issue a global reset to the et1310 */
5205 et131x_soft_reset(adapter);
5207 /* Disable all interrupts (paranoid) */
5208 et131x_disable_interrupts(adapter);
5210 /* Allocate DMA memory */
5211 rc = et131x_adapter_memory_alloc(adapter);
5213 dev_err(&pdev->dev, "Could not alloc adapater memory (DMA)\n");
5217 /* Init send data structures */
5218 et131x_init_send(adapter);
5220 /* Set up the task structure for the ISR's deferred handler */
5221 INIT_WORK(&adapter->task, et131x_isr_handler);
5223 /* Copy address into the net_device struct */
5224 memcpy(netdev->dev_addr, adapter->addr, ETH_ALEN);
5226 /* Init variable for counting how long we do not have link status */
5227 adapter->boot_coma = 0;
5228 et1310_disable_phy_coma(adapter);
5232 /* Setup the mii_bus struct */
5233 adapter->mii_bus = mdiobus_alloc();
5234 if (!adapter->mii_bus) {
5235 dev_err(&pdev->dev, "Alloc of mii_bus struct failed\n");
5239 adapter->mii_bus->name = "et131x_eth_mii";
5240 snprintf(adapter->mii_bus->id, MII_BUS_ID_SIZE, "%x",
5241 (adapter->pdev->bus->number << 8) | adapter->pdev->devfn);
5242 adapter->mii_bus->priv = netdev;
5243 adapter->mii_bus->read = et131x_mdio_read;
5244 adapter->mii_bus->write = et131x_mdio_write;
5245 adapter->mii_bus->reset = et131x_mdio_reset;
5246 adapter->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
5247 if (!adapter->mii_bus->irq) {
5248 dev_err(&pdev->dev, "mii_bus irq allocation failed\n");
5252 for (ii = 0; ii < PHY_MAX_ADDR; ii++)
5253 adapter->mii_bus->irq[ii] = PHY_POLL;
5255 rc = mdiobus_register(adapter->mii_bus);
5257 dev_err(&pdev->dev, "failed to register MII bus\n");
5258 goto err_mdio_free_irq;
5261 rc = et131x_mii_probe(netdev);
5263 dev_err(&pdev->dev, "failed to probe MII bus\n");
5264 goto err_mdio_unregister;
5267 /* Setup et1310 as per the documentation */
5268 et131x_adapter_setup(adapter);
5270 /* We can enable interrupts now
5272 * NOTE - Because registration of interrupt handler is done in the
5273 * device's open(), defer enabling device interrupts to that
5277 /* Register the net_device struct with the Linux network layer */
5278 rc = register_netdev(netdev);
5280 dev_err(&pdev->dev, "register_netdev() failed\n");
5281 goto err_phy_disconnect;
5284 /* Register the net_device struct with the PCI subsystem. Save a copy
5285 * of the PCI config space for this device now that the device has
5286 * been initialized, just in case it needs to be quickly restored.
5288 pci_set_drvdata(pdev, netdev);
5293 phy_disconnect(adapter->phydev);
5294 err_mdio_unregister:
5295 mdiobus_unregister(adapter->mii_bus);
5297 kfree(adapter->mii_bus->irq);
5299 mdiobus_free(adapter->mii_bus);
5301 et131x_adapter_memory_free(adapter);
5303 iounmap(adapter->regs);
5306 free_netdev(netdev);
5308 pci_release_regions(pdev);
5310 pci_disable_device(pdev);
5314 static DEFINE_PCI_DEVICE_TABLE(et131x_pci_table) = {
5315 { PCI_VDEVICE(ATT, ET131X_PCI_DEVICE_ID_GIG), 0UL},
5316 { PCI_VDEVICE(ATT, ET131X_PCI_DEVICE_ID_FAST), 0UL},
5319 MODULE_DEVICE_TABLE(pci, et131x_pci_table);
5321 static struct pci_driver et131x_driver = {
5322 .name = DRIVER_NAME,
5323 .id_table = et131x_pci_table,
5324 .probe = et131x_pci_setup,
5325 .remove = __devexit_p(et131x_pci_remove),
5326 .driver.pm = ET131X_PM_OPS,
5329 module_pci_driver(et131x_driver);