Pileus Git - ~andy/linux/blob - drivers/staging/dwc2/hcd_intr.c

   1 /*
   2  * hcd_intr.c - DesignWare HS OTG Controller host-mode interrupt handling
   3  *
   4  * Copyright (C) 2004-2013 Synopsys, Inc.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions, and the following disclaimer,
  11  *    without modification.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. The names of the above-listed copyright holders may not be used
  16  *    to endorse or promote products derived from this software without
  17  *    specific prior written permission.
  18  *
  19  * ALTERNATIVELY, this software may be distributed under the terms of the
  20  * GNU General Public License ("GPL") as published by the Free Software
  21  * Foundation; either version 2 of the License, or (at your option) any
  22  * later version.
  23  *
  24  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  25  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  26  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  27  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  28  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  29  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  30  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  31  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  32  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  33  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  34  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  35  */
  36
  37 /*
  38  * This file contains the interrupt handlers for Host mode
  39  */
  40 #include <linux/kernel.h>
  41 #include <linux/module.h>
  42 #include <linux/spinlock.h>
  43 #include <linux/interrupt.h>
  44 #include <linux/dma-mapping.h>
  45 #include <linux/io.h>
  46 #include <linux/slab.h>
  47 #include <linux/usb.h>
  48
  49 #include <linux/usb/hcd.h>
  50 #include <linux/usb/ch11.h>
  51
  52 #include "core.h"
  53 #include "hcd.h"
  54
  55 /* This function is for debug only */
  56 static void dwc2_track_missed_sofs(struct dwc2_hsotg *hsotg)
  57 {
  58 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
  59         u16 curr_frame_number = hsotg->frame_number;
  60
  61         if (hsotg->frame_num_idx < FRAME_NUM_ARRAY_SIZE) {
  62                 if (((hsotg->last_frame_num + 1) & HFNUM_MAX_FRNUM) !=
  63                     curr_frame_number) {
  64                         hsotg->frame_num_array[hsotg->frame_num_idx] =
  65                                         curr_frame_number;
  66                         hsotg->last_frame_num_array[hsotg->frame_num_idx] =
  67                                         hsotg->last_frame_num;
  68                         hsotg->frame_num_idx++;
  69                 }
  70         } else if (!hsotg->dumped_frame_num_array) {
  71                 int i;
  72
  73                 dev_info(hsotg->dev, "Frame     Last Frame\n");
  74                 dev_info(hsotg->dev, "-----     ----------\n");
  75                 for (i = 0; i < FRAME_NUM_ARRAY_SIZE; i++) {
  76                         dev_info(hsotg->dev, "0x%04x    0x%04x\n",
  77                                  hsotg->frame_num_array[i],
  78                                  hsotg->last_frame_num_array[i]);
  79                 }
  80                 hsotg->dumped_frame_num_array = 1;
  81         }
  82         hsotg->last_frame_num = curr_frame_number;
  83 #endif
  84 }
  85
  86 static void dwc2_hc_handle_tt_clear(struct dwc2_hsotg *hsotg,
  87                                     struct dwc2_host_chan *chan,
  88                                     struct dwc2_qtd *qtd)
  89 {
  90         struct urb *usb_urb;
  91
  92         if (!chan->qh)
  93                 return;
  94
  95         if (chan->qh->dev_speed == USB_SPEED_HIGH)
  96                 return;
  97
  98         if (!qtd->urb)
  99                 return;
 100
 101         usb_urb = qtd->urb->priv;
 102         if (!usb_urb || !usb_urb->dev || !usb_urb->dev->tt)
 103                 return;
 104
 105         if (qtd->urb->status != -EPIPE && qtd->urb->status != -EREMOTEIO) {
 106                 chan->qh->tt_buffer_dirty = 1;
 107                 if (usb_hub_clear_tt_buffer(usb_urb))
 108                         /* Clear failed; let's hope things work anyway */
 109                         chan->qh->tt_buffer_dirty = 0;
 110         }
 111 }
 112
 113 /*
 114  * Handles the start-of-frame interrupt in host mode. Non-periodic
 115  * transactions may be queued to the DWC_otg controller for the current
 116  * (micro)frame. Periodic transactions may be queued to the controller
 117  * for the next (micro)frame.
 118  */
 119 static void dwc2_sof_intr(struct dwc2_hsotg *hsotg)
 120 {
 121         struct list_head *qh_entry;
 122         struct dwc2_qh *qh;
 123         enum dwc2_transaction_type tr_type;
 124
 125 #ifdef DEBUG_SOF
 126         dev_vdbg(hsotg->dev, "--Start of Frame Interrupt--\n");
 127 #endif
 128
 129         hsotg->frame_number = dwc2_hcd_get_frame_number(hsotg);
 130
 131         dwc2_track_missed_sofs(hsotg);
 132
 133         /* Determine whether any periodic QHs should be executed */
 134         qh_entry = hsotg->periodic_sched_inactive.next;
 135         while (qh_entry != &hsotg->periodic_sched_inactive) {
 136                 qh = list_entry(qh_entry, struct dwc2_qh, qh_list_entry);
 137                 qh_entry = qh_entry->next;
 138                 if (dwc2_frame_num_le(qh->sched_frame, hsotg->frame_number))
 139                         /*
 140                          * Move QH to the ready list to be executed next
 141                          * (micro)frame
 142                          */
 143                         list_move(&qh->qh_list_entry,
 144                                   &hsotg->periodic_sched_ready);
 145         }
 146         tr_type = dwc2_hcd_select_transactions(hsotg);
 147         if (tr_type != DWC2_TRANSACTION_NONE)
 148                 dwc2_hcd_queue_transactions(hsotg, tr_type);
 149
 150         /* Clear interrupt */
 151         writel(GINTSTS_SOF, hsotg->regs + GINTSTS);
 152 }
 153
 154 /*
 155  * Handles the Rx FIFO Level Interrupt, which indicates that there is
 156  * at least one packet in the Rx FIFO. The packets are moved from the FIFO to
 157  * memory if the DWC_otg controller is operating in Slave mode.
 158  */
 159 static void dwc2_rx_fifo_level_intr(struct dwc2_hsotg *hsotg)
 160 {
 161         u32 grxsts, chnum, bcnt, dpid, pktsts;
 162         struct dwc2_host_chan *chan;
 163
 164         if (dbg_perio())
 165                 dev_vdbg(hsotg->dev, "--RxFIFO Level Interrupt--\n");
 166
 167         grxsts = readl(hsotg->regs + GRXSTSP);
 168         chnum = (grxsts & GRXSTS_HCHNUM_MASK) >> GRXSTS_HCHNUM_SHIFT;
 169         chan = hsotg->hc_ptr_array[chnum];
 170         if (!chan) {
 171                 dev_err(hsotg->dev, "Unable to get corresponding channel\n");
 172                 return;
 173         }
 174
 175         bcnt = (grxsts & GRXSTS_BYTECNT_MASK) >> GRXSTS_BYTECNT_SHIFT;
 176         dpid = (grxsts & GRXSTS_DPID_MASK) >> GRXSTS_DPID_SHIFT;
 177         pktsts = (grxsts & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT;
 178
 179         /* Packet Status */
 180         if (dbg_perio()) {
 181                 dev_vdbg(hsotg->dev, "    Ch num = %d\n", chnum);
 182                 dev_vdbg(hsotg->dev, "    Count = %d\n", bcnt);
 183                 dev_vdbg(hsotg->dev, "    DPID = %d, chan.dpid = %d\n", dpid,
 184                          chan->data_pid_start);
 185                 dev_vdbg(hsotg->dev, "    PStatus = %d\n", pktsts);
 186         }
 187
 188         switch (pktsts) {
 189         case GRXSTS_PKTSTS_HCHIN:
 190                 /* Read the data into the host buffer */
 191                 if (bcnt > 0) {
 192                         dwc2_read_packet(hsotg, chan->xfer_buf, bcnt);
 193
 194                         /* Update the HC fields for the next packet received */
 195                         chan->xfer_count += bcnt;
 196                         chan->xfer_buf += bcnt;
 197                 }
 198                 break;
 199         case GRXSTS_PKTSTS_HCHIN_XFER_COMP:
 200         case GRXSTS_PKTSTS_DATATOGGLEERR:
 201         case GRXSTS_PKTSTS_HCHHALTED:
 202                 /* Handled in interrupt, just ignore data */
 203                 break;
 204         default:
 205                 dev_err(hsotg->dev,
 206                         "RxFIFO Level Interrupt: Unknown status %d\n", pktsts);
 207                 break;
 208         }
 209 }
 210
 211 /*
 212  * This interrupt occurs when the non-periodic Tx FIFO is half-empty. More
 213  * data packets may be written to the FIFO for OUT transfers. More requests
 214  * may be written to the non-periodic request queue for IN transfers. This
 215  * interrupt is enabled only in Slave mode.
 216  */
 217 static void dwc2_np_tx_fifo_empty_intr(struct dwc2_hsotg *hsotg)
 218 {
 219         dev_vdbg(hsotg->dev, "--Non-Periodic TxFIFO Empty Interrupt--\n");
 220         dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_NON_PERIODIC);
 221 }
 222
 223 /*
 224  * This interrupt occurs when the periodic Tx FIFO is half-empty. More data
 225  * packets may be written to the FIFO for OUT transfers. More requests may be
 226  * written to the periodic request queue for IN transfers. This interrupt is
 227  * enabled only in Slave mode.
 228  */
 229 static void dwc2_perio_tx_fifo_empty_intr(struct dwc2_hsotg *hsotg)
 230 {
 231         if (dbg_perio())
 232                 dev_vdbg(hsotg->dev, "--Periodic TxFIFO Empty Interrupt--\n");
 233         dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_PERIODIC);
 234 }
 235
 236 static void dwc2_hprt0_enable(struct dwc2_hsotg *hsotg, u32 hprt0,
 237                               u32 *hprt0_modify)
 238 {
 239         struct dwc2_core_params *params = hsotg->core_params;
 240         int do_reset = 0;
 241         u32 usbcfg;
 242         u32 prtspd;
 243         u32 hcfg;
 244         u32 fslspclksel;
 245         u32 hfir;
 246
 247         dev_vdbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
 248
 249         /* Every time when port enables calculate HFIR.FrInterval */
 250         hfir = readl(hsotg->regs + HFIR);
 251         hfir &= ~HFIR_FRINT_MASK;
 252         hfir |= dwc2_calc_frame_interval(hsotg) << HFIR_FRINT_SHIFT &
 253                 HFIR_FRINT_MASK;
 254         writel(hfir, hsotg->regs + HFIR);
 255
 256         /* Check if we need to adjust the PHY clock speed for low power */
 257         if (!params->host_support_fs_ls_low_power) {
 258                 /* Port has been enabled, set the reset change flag */
 259                 hsotg->flags.b.port_reset_change = 1;
 260                 return;
 261         }
 262
 263         usbcfg = readl(hsotg->regs + GUSBCFG);
 264         prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
 265
 266         if (prtspd == HPRT0_SPD_LOW_SPEED || prtspd == HPRT0_SPD_FULL_SPEED) {
 267                 /* Low power */
 268                 if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL)) {
 269                         /* Set PHY low power clock select for FS/LS devices */
 270                         usbcfg |= GUSBCFG_PHY_LP_CLK_SEL;
 271                         writel(usbcfg, hsotg->regs + GUSBCFG);
 272                         do_reset = 1;
 273                 }
 274
 275                 hcfg = readl(hsotg->regs + HCFG);
 276                 fslspclksel = (hcfg & HCFG_FSLSPCLKSEL_MASK) >>
 277                               HCFG_FSLSPCLKSEL_SHIFT;
 278
 279                 if (prtspd == HPRT0_SPD_LOW_SPEED &&
 280                     params->host_ls_low_power_phy_clk ==
 281                     DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ) {
 282                         /* 6 MHZ */
 283                         dev_vdbg(hsotg->dev,
 284                                  "FS_PHY programming HCFG to 6 MHz\n");
 285                         if (fslspclksel != HCFG_FSLSPCLKSEL_6_MHZ) {
 286                                 fslspclksel = HCFG_FSLSPCLKSEL_6_MHZ;
 287                                 hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
 288                                 hcfg |= fslspclksel << HCFG_FSLSPCLKSEL_SHIFT;
 289                                 writel(hcfg, hsotg->regs + HCFG);
 290                                 do_reset = 1;
 291                         }
 292                 } else {
 293                         /* 48 MHZ */
 294                         dev_vdbg(hsotg->dev,
 295                                  "FS_PHY programming HCFG to 48 MHz\n");
 296                         if (fslspclksel != HCFG_FSLSPCLKSEL_48_MHZ) {
 297                                 fslspclksel = HCFG_FSLSPCLKSEL_48_MHZ;
 298                                 hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
 299                                 hcfg |= fslspclksel << HCFG_FSLSPCLKSEL_SHIFT;
 300                                 writel(hcfg, hsotg->regs + HCFG);
 301                                 do_reset = 1;
 302                         }
 303                 }
 304         } else {
 305                 /* Not low power */
 306                 if (usbcfg & GUSBCFG_PHY_LP_CLK_SEL) {
 307                         usbcfg &= ~GUSBCFG_PHY_LP_CLK_SEL;
 308                         writel(usbcfg, hsotg->regs + GUSBCFG);
 309                         do_reset = 1;
 310                 }
 311         }
 312
 313         if (do_reset) {
 314                 *hprt0_modify |= HPRT0_RST;
 315                 queue_delayed_work(hsotg->wq_otg, &hsotg->reset_work,
 316                                    msecs_to_jiffies(60));
 317         } else {
 318                 /* Port has been enabled, set the reset change flag */
 319                 hsotg->flags.b.port_reset_change = 1;
 320         }
 321 }
 322
 323 /*
 324  * There are multiple conditions that can cause a port interrupt. This function
 325  * determines which interrupt conditions have occurred and handles them
 326  * appropriately.
 327  */
 328 static void dwc2_port_intr(struct dwc2_hsotg *hsotg)
 329 {
 330         u32 hprt0;
 331         u32 hprt0_modify;
 332
 333         dev_vdbg(hsotg->dev, "--Port Interrupt--\n");
 334
 335         hprt0 = readl(hsotg->regs + HPRT0);
 336         hprt0_modify = hprt0;
 337
 338         /*
 339          * Clear appropriate bits in HPRT0 to clear the interrupt bit in
 340          * GINTSTS
 341          */
 342         hprt0_modify &= ~(HPRT0_ENA | HPRT0_CONNDET | HPRT0_ENACHG |
 343                           HPRT0_OVRCURRCHG);
 344
 345         /*
 346          * Port Connect Detected
 347          * Set flag and clear if detected
 348          */
 349         if (hprt0 & HPRT0_CONNDET) {
 350                 dev_vdbg(hsotg->dev,
 351                          "--Port Interrupt HPRT0=0x%08x Port Connect Detected--\n",
 352                          hprt0);
 353                 hsotg->flags.b.port_connect_status_change = 1;
 354                 hsotg->flags.b.port_connect_status = 1;
 355                 hprt0_modify |= HPRT0_CONNDET;
 356
 357                 /*
 358                  * The Hub driver asserts a reset when it sees port connect
 359                  * status change flag
 360                  */
 361         }
 362
 363         /*
 364          * Port Enable Changed
 365          * Clear if detected - Set internal flag if disabled
 366          */
 367         if (hprt0 & HPRT0_ENACHG) {
 368                 dev_vdbg(hsotg->dev,
 369                          "  --Port Interrupt HPRT0=0x%08x Port Enable Changed (now %d)--\n",
 370                          hprt0, !!(hprt0 & HPRT0_ENA));
 371                 hprt0_modify |= HPRT0_ENACHG;
 372                 if (hprt0 & HPRT0_ENA)
 373                         dwc2_hprt0_enable(hsotg, hprt0, &hprt0_modify);
 374                 else
 375                         hsotg->flags.b.port_enable_change = 1;
 376         }
 377
 378         /* Overcurrent Change Interrupt */
 379         if (hprt0 & HPRT0_OVRCURRCHG) {
 380                 dev_vdbg(hsotg->dev,
 381                          "  --Port Interrupt HPRT0=0x%08x Port Overcurrent Changed--\n",
 382                          hprt0);
 383                 hsotg->flags.b.port_over_current_change = 1;
 384                 hprt0_modify |= HPRT0_OVRCURRCHG;
 385         }
 386
 387         /* Clear Port Interrupts */
 388         writel(hprt0_modify, hsotg->regs + HPRT0);
 389 }
 390
 391 /*
 392  * Gets the actual length of a transfer after the transfer halts. halt_status
 393  * holds the reason for the halt.
 394  *
 395  * For IN transfers where halt_status is DWC2_HC_XFER_COMPLETE, *short_read
 396  * is set to 1 upon return if less than the requested number of bytes were
 397  * transferred. short_read may also be NULL on entry, in which case it remains
 398  * unchanged.
 399  */
 400 static u32 dwc2_get_actual_xfer_length(struct dwc2_hsotg *hsotg,
 401                                        struct dwc2_host_chan *chan, int chnum,
 402                                        struct dwc2_qtd *qtd,
 403                                        enum dwc2_halt_status halt_status,
 404                                        int *short_read)
 405 {
 406         u32 hctsiz, count, length;
 407
 408         hctsiz = readl(hsotg->regs + HCTSIZ(chnum));
 409
 410         if (halt_status == DWC2_HC_XFER_COMPLETE) {
 411                 if (chan->ep_is_in) {
 412                         count = (hctsiz & TSIZ_XFERSIZE_MASK) >>
 413                                 TSIZ_XFERSIZE_SHIFT;
 414                         length = chan->xfer_len - count;
 415                         if (short_read != NULL)
 416                                 *short_read = (count != 0);
 417                 } else if (chan->qh->do_split) {
 418                         length = qtd->ssplit_out_xfer_count;
 419                 } else {
 420                         length = chan->xfer_len;
 421                 }
 422         } else {
 423                 /*
 424                  * Must use the hctsiz.pktcnt field to determine how much data
 425                  * has been transferred. This field reflects the number of
 426                  * packets that have been transferred via the USB. This is
 427                  * always an integral number of packets if the transfer was
 428                  * halted before its normal completion. (Can't use the
 429                  * hctsiz.xfersize field because that reflects the number of
 430                  * bytes transferred via the AHB, not the USB).
 431                  */
 432                 count = (hctsiz & TSIZ_PKTCNT_MASK) >> TSIZ_PKTCNT_SHIFT;
 433                 length = (chan->start_pkt_count - count) * chan->max_packet;
 434         }
 435
 436         return length;
 437 }
 438
 439 /**
 440  * dwc2_update_urb_state() - Updates the state of the URB after a Transfer
 441  * Complete interrupt on the host channel. Updates the actual_length field
 442  * of the URB based on the number of bytes transferred via the host channel.
 443  * Sets the URB status if the data transfer is finished.
 444  *
 445  * Return: 1 if the data transfer specified by the URB is completely finished,
 446  * 0 otherwise
 447  */
 448 static int dwc2_update_urb_state(struct dwc2_hsotg *hsotg,
 449                                  struct dwc2_host_chan *chan, int chnum,
 450                                  struct dwc2_hcd_urb *urb,
 451                                  struct dwc2_qtd *qtd)
 452 {
 453         u32 hctsiz;
 454         int xfer_done = 0;
 455         int short_read = 0;
 456         int xfer_length = dwc2_get_actual_xfer_length(hsotg, chan, chnum, qtd,
 457                                                       DWC2_HC_XFER_COMPLETE,
 458                                                       &short_read);
 459
 460         if (urb->actual_length + xfer_length > urb->length) {
 461                 dev_warn(hsotg->dev, "%s(): trimming xfer length\n", __func__);
 462                 xfer_length = urb->length - urb->actual_length;
 463         }
 464
 465         /* Non DWORD-aligned buffer case handling */
 466         if (chan->align_buf && xfer_length && chan->ep_is_in) {
 467                 dev_vdbg(hsotg->dev, "%s(): non-aligned buffer\n", __func__);
 468                 dma_sync_single_for_cpu(hsotg->dev, urb->dma, urb->length,
 469                                         DMA_FROM_DEVICE);
 470                 memcpy(urb->buf + urb->actual_length, chan->qh->dw_align_buf,
 471                        xfer_length);
 472                 dma_sync_single_for_device(hsotg->dev, urb->dma, urb->length,
 473                                            DMA_FROM_DEVICE);
 474         }
 475
 476         dev_vdbg(hsotg->dev, "urb->actual_length=%d xfer_length=%d\n",
 477                  urb->actual_length, xfer_length);
 478         urb->actual_length += xfer_length;
 479
 480         if (xfer_length && chan->ep_type == USB_ENDPOINT_XFER_BULK &&
 481             (urb->flags & URB_SEND_ZERO_PACKET) &&
 482             urb->actual_length >= urb->length &&
 483             !(urb->length % chan->max_packet)) {
 484                 xfer_done = 0;
 485         } else if (short_read || urb->actual_length >= urb->length) {
 486                 xfer_done = 1;
 487                 urb->status = 0;
 488         }
 489
 490         hctsiz = readl(hsotg->regs + HCTSIZ(chnum));
 491         dev_vdbg(hsotg->dev, "DWC_otg: %s: %s, channel %d\n",
 492                  __func__, (chan->ep_is_in ? "IN" : "OUT"), chnum);
 493         dev_vdbg(hsotg->dev, "  chan->xfer_len %d\n", chan->xfer_len);
 494         dev_vdbg(hsotg->dev, "  hctsiz.xfersize %d\n",
 495                  (hctsiz & TSIZ_XFERSIZE_MASK) >> TSIZ_XFERSIZE_SHIFT);
 496         dev_vdbg(hsotg->dev, "  urb->transfer_buffer_length %d\n", urb->length);
 497         dev_vdbg(hsotg->dev, "  urb->actual_length %d\n", urb->actual_length);
 498         dev_vdbg(hsotg->dev, "  short_read %d, xfer_done %d\n", short_read,
 499                  xfer_done);
 500
 501         return xfer_done;
 502 }
 503
 504 /*
 505  * Save the starting data toggle for the next transfer. The data toggle is
 506  * saved in the QH for non-control transfers and it's saved in the QTD for
 507  * control transfers.
 508  */
 509 void dwc2_hcd_save_data_toggle(struct dwc2_hsotg *hsotg,
 510                                struct dwc2_host_chan *chan, int chnum,
 511                                struct dwc2_qtd *qtd)
 512 {
 513         u32 hctsiz = readl(hsotg->regs + HCTSIZ(chnum));
 514         u32 pid = (hctsiz & TSIZ_SC_MC_PID_MASK) >> TSIZ_SC_MC_PID_SHIFT;
 515
 516         if (chan->ep_type != USB_ENDPOINT_XFER_CONTROL) {
 517                 if (pid == TSIZ_SC_MC_PID_DATA0)
 518                         chan->qh->data_toggle = DWC2_HC_PID_DATA0;
 519                 else
 520                         chan->qh->data_toggle = DWC2_HC_PID_DATA1;
 521         } else {
 522                 if (pid == TSIZ_SC_MC_PID_DATA0)
 523                         qtd->data_toggle = DWC2_HC_PID_DATA0;
 524                 else
 525                         qtd->data_toggle = DWC2_HC_PID_DATA1;
 526         }
 527 }
 528
 529 /**
 530  * dwc2_update_isoc_urb_state() - Updates the state of an Isochronous URB when
 531  * the transfer is stopped for any reason. The fields of the current entry in
 532  * the frame descriptor array are set based on the transfer state and the input
 533  * halt_status. Completes the Isochronous URB if all the URB frames have been
 534  * completed.
 535  *
 536  * Return: DWC2_HC_XFER_COMPLETE if there are more frames remaining to be
 537  * transferred in the URB. Otherwise return DWC2_HC_XFER_URB_COMPLETE.
 538  */
 539 static enum dwc2_halt_status dwc2_update_isoc_urb_state(
 540                 struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan,
 541                 int chnum, struct dwc2_qtd *qtd,
 542                 enum dwc2_halt_status halt_status)
 543 {
 544         struct dwc2_hcd_iso_packet_desc *frame_desc;
 545         struct dwc2_hcd_urb *urb = qtd->urb;
 546
 547         if (!urb)
 548                 return DWC2_HC_XFER_NO_HALT_STATUS;
 549
 550         frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
 551
 552         switch (halt_status) {
 553         case DWC2_HC_XFER_COMPLETE:
 554                 frame_desc->status = 0;
 555                 frame_desc->actual_length = dwc2_get_actual_xfer_length(hsotg,
 556                                         chan, chnum, qtd, halt_status, NULL);
 557
 558                 /* Non DWORD-aligned buffer case handling */
 559                 if (chan->align_buf && frame_desc->actual_length &&
 560                     chan->ep_is_in) {
 561                         dev_vdbg(hsotg->dev, "%s(): non-aligned buffer\n",
 562                                  __func__);
 563                         dma_sync_single_for_cpu(hsotg->dev, urb->dma,
 564                                                 urb->length, DMA_FROM_DEVICE);
 565                         memcpy(urb->buf + frame_desc->offset +
 566                                qtd->isoc_split_offset, chan->qh->dw_align_buf,
 567                                frame_desc->actual_length);
 568                         dma_sync_single_for_device(hsotg->dev, urb->dma,
 569                                                    urb->length,
 570                                                    DMA_FROM_DEVICE);
 571                 }
 572                 break;
 573         case DWC2_HC_XFER_FRAME_OVERRUN:
 574                 urb->error_count++;
 575                 if (chan->ep_is_in)
 576                         frame_desc->status = -ENOSR;
 577                 else
 578                         frame_desc->status = -ECOMM;
 579                 frame_desc->actual_length = 0;
 580                 break;
 581         case DWC2_HC_XFER_BABBLE_ERR:
 582                 urb->error_count++;
 583                 frame_desc->status = -EOVERFLOW;
 584                 /* Don't need to update actual_length in this case */
 585                 break;
 586         case DWC2_HC_XFER_XACT_ERR:
 587                 urb->error_count++;
 588                 frame_desc->status = -EPROTO;
 589                 frame_desc->actual_length = dwc2_get_actual_xfer_length(hsotg,
 590                                         chan, chnum, qtd, halt_status, NULL);
 591
 592                 /* Non DWORD-aligned buffer case handling */
 593                 if (chan->align_buf && frame_desc->actual_length &&
 594                     chan->ep_is_in) {
 595                         dev_vdbg(hsotg->dev, "%s(): non-aligned buffer\n",
 596                                  __func__);
 597                         dma_sync_single_for_cpu(hsotg->dev, urb->dma,
 598                                                 urb->length, DMA_FROM_DEVICE);
 599                         memcpy(urb->buf + frame_desc->offset +
 600                                qtd->isoc_split_offset, chan->qh->dw_align_buf,
 601                                frame_desc->actual_length);
 602                         dma_sync_single_for_device(hsotg->dev, urb->dma,
 603                                                    urb->length,
 604                                                    DMA_FROM_DEVICE);
 605                 }
 606
 607                 /* Skip whole frame */
 608                 if (chan->qh->do_split &&
 609                     chan->ep_type == USB_ENDPOINT_XFER_ISOC && chan->ep_is_in &&
 610                     hsotg->core_params->dma_enable > 0) {
 611                         qtd->complete_split = 0;
 612                         qtd->isoc_split_offset = 0;
 613                 }
 614
 615                 break;
 616         default:
 617                 dev_err(hsotg->dev, "Unhandled halt_status (%d)\n",
 618                         halt_status);
 619                 break;
 620         }
 621
 622         if (++qtd->isoc_frame_index == urb->packet_count) {
 623                 /*
 624                  * urb->status is not used for isoc transfers. The individual
 625                  * frame_desc statuses are used instead.
 626                  */
 627                 dwc2_host_complete(hsotg, qtd, 0);
 628                 halt_status = DWC2_HC_XFER_URB_COMPLETE;
 629         } else {
 630                 halt_status = DWC2_HC_XFER_COMPLETE;
 631         }
 632
 633         return halt_status;
 634 }
 635
 636 /*
 637  * Frees the first QTD in the QH's list if free_qtd is 1. For non-periodic
 638  * QHs, removes the QH from the active non-periodic schedule. If any QTDs are
 639  * still linked to the QH, the QH is added to the end of the inactive
 640  * non-periodic schedule. For periodic QHs, removes the QH from the periodic
 641  * schedule if no more QTDs are linked to the QH.
 642  */
 643 static void dwc2_deactivate_qh(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
 644                                int free_qtd)
 645 {
 646         int continue_split = 0;
 647         struct dwc2_qtd *qtd;
 648
 649         if (dbg_qh(qh))
 650                 dev_vdbg(hsotg->dev, "  %s(%p,%p,%d)\n", __func__,
 651                          hsotg, qh, free_qtd);
 652
 653         if (list_empty(&qh->qtd_list)) {
 654                 dev_dbg(hsotg->dev, "## QTD list empty ##\n");
 655                 goto no_qtd;
 656         }
 657
 658         qtd = list_first_entry(&qh->qtd_list, struct dwc2_qtd, qtd_list_entry);
 659
 660         if (qtd->complete_split)
 661                 continue_split = 1;
 662         else if (qtd->isoc_split_pos == DWC2_HCSPLT_XACTPOS_MID ||
 663                  qtd->isoc_split_pos == DWC2_HCSPLT_XACTPOS_END)
 664                 continue_split = 1;
 665
 666         if (free_qtd) {
 667                 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
 668                 continue_split = 0;
 669         }
 670
 671 no_qtd:
 672         if (qh->channel)
 673                 qh->channel->align_buf = 0;
 674         qh->channel = NULL;
 675         dwc2_hcd_qh_deactivate(hsotg, qh, continue_split);
 676 }
 677
 678 /**
 679  * dwc2_release_channel() - Releases a host channel for use by other transfers
 680  *
 681  * @hsotg:       The HCD state structure
 682  * @chan:        The host channel to release
 683  * @qtd:         The QTD associated with the host channel. This QTD may be
 684  *               freed if the transfer is complete or an error has occurred.
 685  * @halt_status: Reason the channel is being released. This status
 686  *               determines the actions taken by this function.
 687  *
 688  * Also attempts to select and queue more transactions since at least one host
 689  * channel is available.
 690  */
 691 static void dwc2_release_channel(struct dwc2_hsotg *hsotg,
 692                                  struct dwc2_host_chan *chan,
 693                                  struct dwc2_qtd *qtd,
 694                                  enum dwc2_halt_status halt_status)
 695 {
 696         enum dwc2_transaction_type tr_type;
 697         u32 haintmsk;
 698         int free_qtd = 0;
 699
 700         if (dbg_hc(chan))
 701                 dev_vdbg(hsotg->dev, "  %s: channel %d, halt_status %d\n",
 702                          __func__, chan->hc_num, halt_status);
 703
 704         switch (halt_status) {
 705         case DWC2_HC_XFER_URB_COMPLETE:
 706                 free_qtd = 1;
 707                 break;
 708         case DWC2_HC_XFER_AHB_ERR:
 709         case DWC2_HC_XFER_STALL:
 710         case DWC2_HC_XFER_BABBLE_ERR:
 711                 free_qtd = 1;
 712                 break;
 713         case DWC2_HC_XFER_XACT_ERR:
 714                 if (qtd && qtd->error_count >= 3) {
 715                         dev_vdbg(hsotg->dev,
 716                                  "  Complete URB with transaction error\n");
 717                         free_qtd = 1;
 718                         dwc2_host_complete(hsotg, qtd, -EPROTO);
 719                 }
 720                 break;
 721         case DWC2_HC_XFER_URB_DEQUEUE:
 722                 /*
 723                  * The QTD has already been removed and the QH has been
 724                  * deactivated. Don't want to do anything except release the
 725                  * host channel and try to queue more transfers.
 726                  */
 727                 goto cleanup;
 728         case DWC2_HC_XFER_PERIODIC_INCOMPLETE:
 729                 dev_vdbg(hsotg->dev, "  Complete URB with I/O error\n");
 730                 free_qtd = 1;
 731                 dwc2_host_complete(hsotg, qtd, -EIO);
 732                 break;
 733         case DWC2_HC_XFER_NO_HALT_STATUS:
 734         default:
 735                 break;
 736         }
 737
 738         dwc2_deactivate_qh(hsotg, chan->qh, free_qtd);
 739
 740 cleanup:
 741         /*
 742          * Release the host channel for use by other transfers. The cleanup
 743          * function clears the channel interrupt enables and conditions, so
 744          * there's no need to clear the Channel Halted interrupt separately.
 745          */
 746         if (!list_empty(&chan->hc_list_entry))
 747                 list_del(&chan->hc_list_entry);
 748         dwc2_hc_cleanup(hsotg, chan);
 749         list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list);
 750
 751         switch (chan->ep_type) {
 752         case USB_ENDPOINT_XFER_CONTROL:
 753         case USB_ENDPOINT_XFER_BULK:
 754                 hsotg->non_periodic_channels--;
 755                 break;
 756         default:
 757                 /*
 758                  * Don't release reservations for periodic channels here.
 759                  * That's done when a periodic transfer is descheduled (i.e.
 760                  * when the QH is removed from the periodic schedule).
 761                  */
 762                 break;
 763         }
 764
 765         haintmsk = readl(hsotg->regs + HAINTMSK);
 766         haintmsk &= ~(1 << chan->hc_num);
 767         writel(haintmsk, hsotg->regs + HAINTMSK);
 768
 769         /* Try to queue more transfers now that there's a free channel */
 770         tr_type = dwc2_hcd_select_transactions(hsotg);
 771         if (tr_type != DWC2_TRANSACTION_NONE)
 772                 dwc2_hcd_queue_transactions(hsotg, tr_type);
 773 }
 774
 775 /*
 776  * Halts a host channel. If the channel cannot be halted immediately because
 777  * the request queue is full, this function ensures that the FIFO empty
 778  * interrupt for the appropriate queue is enabled so that the halt request can
 779  * be queued when there is space in the request queue.
 780  *
 781  * This function may also be called in DMA mode. In that case, the channel is
 782  * simply released since the core always halts the channel automatically in
 783  * DMA mode.
 784  */
 785 static void dwc2_halt_channel(struct dwc2_hsotg *hsotg,
 786                               struct dwc2_host_chan *chan, struct dwc2_qtd *qtd,
 787                               enum dwc2_halt_status halt_status)
 788 {
 789         if (dbg_hc(chan))
 790                 dev_vdbg(hsotg->dev, "%s()\n", __func__);
 791
 792         if (hsotg->core_params->dma_enable > 0) {
 793                 if (dbg_hc(chan))
 794                         dev_vdbg(hsotg->dev, "DMA enabled\n");
 795                 dwc2_release_channel(hsotg, chan, qtd, halt_status);
 796                 return;
 797         }
 798
 799         /* Slave mode processing */
 800         dwc2_hc_halt(hsotg, chan, halt_status);
 801
 802         if (chan->halt_on_queue) {
 803                 u32 gintmsk;
 804
 805                 dev_vdbg(hsotg->dev, "Halt on queue\n");
 806                 if (chan->ep_type == USB_ENDPOINT_XFER_CONTROL ||
 807                     chan->ep_type == USB_ENDPOINT_XFER_BULK) {
 808                         dev_vdbg(hsotg->dev, "control/bulk\n");
 809                         /*
 810                          * Make sure the Non-periodic Tx FIFO empty interrupt
 811                          * is enabled so that the non-periodic schedule will
 812                          * be processed
 813                          */
 814                         gintmsk = readl(hsotg->regs + GINTMSK);
 815                         gintmsk |= GINTSTS_NPTXFEMP;
 816                         writel(gintmsk, hsotg->regs + GINTMSK);
 817                 } else {
 818                         dev_vdbg(hsotg->dev, "isoc/intr\n");
 819                         /*
 820                          * Move the QH from the periodic queued schedule to
 821                          * the periodic assigned schedule. This allows the
 822                          * halt to be queued when the periodic schedule is
 823                          * processed.
 824                          */
 825                         list_move(&chan->qh->qh_list_entry,
 826                                   &hsotg->periodic_sched_assigned);
 827
 828                         /*
 829                          * Make sure the Periodic Tx FIFO Empty interrupt is
 830                          * enabled so that the periodic schedule will be
 831                          * processed
 832                          */
 833                         gintmsk = readl(hsotg->regs + GINTMSK);
 834                         gintmsk |= GINTSTS_PTXFEMP;
 835                         writel(gintmsk, hsotg->regs + GINTMSK);
 836                 }
 837         }
 838 }
 839
 840 /*
 841  * Performs common cleanup for non-periodic transfers after a Transfer
 842  * Complete interrupt. This function should be called after any endpoint type
 843  * specific handling is finished to release the host channel.
 844  */
 845 static void dwc2_complete_non_periodic_xfer(struct dwc2_hsotg *hsotg,
 846                                             struct dwc2_host_chan *chan,
 847                                             int chnum, struct dwc2_qtd *qtd,
 848                                             enum dwc2_halt_status halt_status)
 849 {
 850         dev_vdbg(hsotg->dev, "%s()\n", __func__);
 851
 852         qtd->error_count = 0;
 853
 854         if (chan->hcint & HCINTMSK_NYET) {
 855                 /*
 856                  * Got a NYET on the last transaction of the transfer. This
 857                  * means that the endpoint should be in the PING state at the
 858                  * beginning of the next transfer.
 859                  */
 860                 dev_vdbg(hsotg->dev, "got NYET\n");
 861                 chan->qh->ping_state = 1;
 862         }
 863
 864         /*
 865          * Always halt and release the host channel to make it available for
 866          * more transfers. There may still be more phases for a control
 867          * transfer or more data packets for a bulk transfer at this point,
 868          * but the host channel is still halted. A channel will be reassigned
 869          * to the transfer when the non-periodic schedule is processed after
 870          * the channel is released. This allows transactions to be queued
 871          * properly via dwc2_hcd_queue_transactions, which also enables the
 872          * Tx FIFO Empty interrupt if necessary.
 873          */
 874         if (chan->ep_is_in) {
 875                 /*
 876                  * IN transfers in Slave mode require an explicit disable to
 877                  * halt the channel. (In DMA mode, this call simply releases
 878                  * the channel.)
 879                  */
 880                 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
 881         } else {
 882                 /*
 883                  * The channel is automatically disabled by the core for OUT
 884                  * transfers in Slave mode
 885                  */
 886                 dwc2_release_channel(hsotg, chan, qtd, halt_status);
 887         }
 888 }
 889
 890 /*
 891  * Performs common cleanup for periodic transfers after a Transfer Complete
 892  * interrupt. This function should be called after any endpoint type specific
 893  * handling is finished to release the host channel.
 894  */
 895 static void dwc2_complete_periodic_xfer(struct dwc2_hsotg *hsotg,
 896                                         struct dwc2_host_chan *chan, int chnum,
 897                                         struct dwc2_qtd *qtd,
 898                                         enum dwc2_halt_status halt_status)
 899 {
 900         u32 hctsiz = readl(hsotg->regs + HCTSIZ(chnum));
 901
 902         qtd->error_count = 0;
 903
 904         if (!chan->ep_is_in || (hctsiz & TSIZ_PKTCNT_MASK) == 0)
 905                 /* Core halts channel in these cases */
 906                 dwc2_release_channel(hsotg, chan, qtd, halt_status);
 907         else
 908                 /* Flush any outstanding requests from the Tx queue */
 909                 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
 910 }
 911
 912 static int dwc2_xfercomp_isoc_split_in(struct dwc2_hsotg *hsotg,
 913                                        struct dwc2_host_chan *chan, int chnum,
 914                                        struct dwc2_qtd *qtd)
 915 {
 916         struct dwc2_hcd_iso_packet_desc *frame_desc;
 917         u32 len;
 918
 919         if (!qtd->urb)
 920                 return 0;
 921
 922         frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];
 923         len = dwc2_get_actual_xfer_length(hsotg, chan, chnum, qtd,
 924                                           DWC2_HC_XFER_COMPLETE, NULL);
 925         if (!len) {
 926                 qtd->complete_split = 0;
 927                 qtd->isoc_split_offset = 0;
 928                 return 0;
 929         }
 930
 931         frame_desc->actual_length += len;
 932
 933         if (chan->align_buf && len) {
 934                 dev_vdbg(hsotg->dev, "%s(): non-aligned buffer\n", __func__);
 935                 dma_sync_single_for_cpu(hsotg->dev, qtd->urb->dma,
 936                                         qtd->urb->length, DMA_FROM_DEVICE);
 937                 memcpy(qtd->urb->buf + frame_desc->offset +
 938                        qtd->isoc_split_offset, chan->qh->dw_align_buf, len);
 939                 dma_sync_single_for_device(hsotg->dev, qtd->urb->dma,
 940                                            qtd->urb->length, DMA_FROM_DEVICE);
 941         }
 942
 943         qtd->isoc_split_offset += len;
 944
 945         if (frame_desc->actual_length >= frame_desc->length) {
 946                 frame_desc->status = 0;
 947                 qtd->isoc_frame_index++;
 948                 qtd->complete_split = 0;
 949                 qtd->isoc_split_offset = 0;
 950         }
 951
 952         if (qtd->isoc_frame_index == qtd->urb->packet_count) {
 953                 dwc2_host_complete(hsotg, qtd, 0);
 954                 dwc2_release_channel(hsotg, chan, qtd,
 955                                      DWC2_HC_XFER_URB_COMPLETE);
 956         } else {
 957                 dwc2_release_channel(hsotg, chan, qtd,
 958                                      DWC2_HC_XFER_NO_HALT_STATUS);
 959         }
 960
 961         return 1;       /* Indicates that channel released */
 962 }
 963
 964 /*
 965  * Handles a host channel Transfer Complete interrupt. This handler may be
 966  * called in either DMA mode or Slave mode.
 967  */
 968 static void dwc2_hc_xfercomp_intr(struct dwc2_hsotg *hsotg,
 969                                   struct dwc2_host_chan *chan, int chnum,
 970                                   struct dwc2_qtd *qtd)
 971 {
 972         struct dwc2_hcd_urb *urb = qtd->urb;
 973         int pipe_type = dwc2_hcd_get_pipe_type(&urb->pipe_info);
 974         enum dwc2_halt_status halt_status = DWC2_HC_XFER_COMPLETE;
 975         int urb_xfer_done;
 976
 977         if (dbg_hc(chan))
 978                 dev_vdbg(hsotg->dev,
 979                          "--Host Channel %d Interrupt: Transfer Complete--\n",
 980                          chnum);
 981
 982         if (hsotg->core_params->dma_desc_enable > 0) {
 983                 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum, halt_status);
 984                 if (pipe_type == USB_ENDPOINT_XFER_ISOC)
 985                         /* Do not disable the interrupt, just clear it */
 986                         return;
 987                 goto handle_xfercomp_done;
 988         }
 989
 990         /* Handle xfer complete on CSPLIT */
 991         if (chan->qh->do_split) {
 992                 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC && chan->ep_is_in &&
 993                     hsotg->core_params->dma_enable > 0) {
 994                         if (qtd->complete_split &&
 995                             dwc2_xfercomp_isoc_split_in(hsotg, chan, chnum,
 996                                                         qtd))
 997                                 goto handle_xfercomp_done;
 998                 } else {
 999                         qtd->complete_split = 0;
1000                 }
1001         }
1002
1003         if (!urb)
1004                 goto handle_xfercomp_done;
1005
1006         /* Update the QTD and URB states */
1007         switch (pipe_type) {
1008         case USB_ENDPOINT_XFER_CONTROL:
1009                 switch (qtd->control_phase) {
1010                 case DWC2_CONTROL_SETUP:
1011                         if (urb->length > 0)
1012                                 qtd->control_phase = DWC2_CONTROL_DATA;
1013                         else
1014                                 qtd->control_phase = DWC2_CONTROL_STATUS;
1015                         dev_vdbg(hsotg->dev,
1016                                  "  Control setup transaction done\n");
1017                         halt_status = DWC2_HC_XFER_COMPLETE;
1018                         break;
1019                 case DWC2_CONTROL_DATA:
1020                         urb_xfer_done = dwc2_update_urb_state(hsotg, chan,
1021                                                               chnum, urb, qtd);
1022                         if (urb_xfer_done) {
1023                                 qtd->control_phase = DWC2_CONTROL_STATUS;
1024                                 dev_vdbg(hsotg->dev,
1025                                          "  Control data transfer done\n");
1026                         } else {
1027                                 dwc2_hcd_save_data_toggle(hsotg, chan, chnum,
1028                                                           qtd);
1029                         }
1030                         halt_status = DWC2_HC_XFER_COMPLETE;
1031                         break;
1032                 case DWC2_CONTROL_STATUS:
1033                         dev_vdbg(hsotg->dev, "  Control transfer complete\n");
1034                         if (urb->status == -EINPROGRESS)
1035                                 urb->status = 0;
1036                         dwc2_host_complete(hsotg, qtd, urb->status);
1037                         halt_status = DWC2_HC_XFER_URB_COMPLETE;
1038                         break;
1039                 }
1040
1041                 dwc2_complete_non_periodic_xfer(hsotg, chan, chnum, qtd,
1042                                                 halt_status);
1043                 break;
1044         case USB_ENDPOINT_XFER_BULK:
1045                 dev_vdbg(hsotg->dev, "  Bulk transfer complete\n");
1046                 urb_xfer_done = dwc2_update_urb_state(hsotg, chan, chnum, urb,
1047                                                       qtd);
1048                 if (urb_xfer_done) {
1049                         dwc2_host_complete(hsotg, qtd, urb->status);
1050                         halt_status = DWC2_HC_XFER_URB_COMPLETE;
1051                 } else {
1052                         halt_status = DWC2_HC_XFER_COMPLETE;
1053                 }
1054
1055                 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1056                 dwc2_complete_non_periodic_xfer(hsotg, chan, chnum, qtd,
1057                                                 halt_status);
1058                 break;
1059         case USB_ENDPOINT_XFER_INT:
1060                 dev_vdbg(hsotg->dev, "  Interrupt transfer complete\n");
1061                 urb_xfer_done = dwc2_update_urb_state(hsotg, chan, chnum, urb,
1062                                                       qtd);
1063
1064                 /*
1065                  * Interrupt URB is done on the first transfer complete
1066                  * interrupt
1067                  */
1068                 if (urb_xfer_done) {
1069                         dwc2_host_complete(hsotg, qtd, urb->status);
1070                         halt_status = DWC2_HC_XFER_URB_COMPLETE;
1071                 } else {
1072                         halt_status = DWC2_HC_XFER_COMPLETE;
1073                 }
1074
1075                 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1076                 dwc2_complete_periodic_xfer(hsotg, chan, chnum, qtd,
1077                                             halt_status);
1078                 break;
1079         case USB_ENDPOINT_XFER_ISOC:
1080                 if (dbg_perio())
1081                         dev_vdbg(hsotg->dev, "  Isochronous transfer complete\n");
1082                 if (qtd->isoc_split_pos == DWC2_HCSPLT_XACTPOS_ALL)
1083                         halt_status = dwc2_update_isoc_urb_state(hsotg, chan,
1084                                         chnum, qtd, DWC2_HC_XFER_COMPLETE);
1085                 dwc2_complete_periodic_xfer(hsotg, chan, chnum, qtd,
1086                                             halt_status);
1087                 break;
1088         }
1089
1090 handle_xfercomp_done:
1091         disable_hc_int(hsotg, chnum, HCINTMSK_XFERCOMPL);
1092 }
1093
1094 /*
1095  * Handles a host channel STALL interrupt. This handler may be called in
1096  * either DMA mode or Slave mode.
1097  */
1098 static void dwc2_hc_stall_intr(struct dwc2_hsotg *hsotg,
1099                                struct dwc2_host_chan *chan, int chnum,
1100                                struct dwc2_qtd *qtd)
1101 {
1102         struct dwc2_hcd_urb *urb = qtd->urb;
1103         int pipe_type = dwc2_hcd_get_pipe_type(&urb->pipe_info);
1104
1105         dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: STALL Received--\n",
1106                 chnum);
1107
1108         if (hsotg->core_params->dma_desc_enable > 0) {
1109                 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1110                                             DWC2_HC_XFER_STALL);
1111                 goto handle_stall_done;
1112         }
1113
1114         if (!urb)
1115                 goto handle_stall_halt;
1116
1117         if (pipe_type == USB_ENDPOINT_XFER_CONTROL)
1118                 dwc2_host_complete(hsotg, qtd, -EPIPE);
1119
1120         if (pipe_type == USB_ENDPOINT_XFER_BULK ||
1121             pipe_type == USB_ENDPOINT_XFER_INT) {
1122                 dwc2_host_complete(hsotg, qtd, -EPIPE);
1123                 /*
1124                  * USB protocol requires resetting the data toggle for bulk
1125                  * and interrupt endpoints when a CLEAR_FEATURE(ENDPOINT_HALT)
1126                  * setup command is issued to the endpoint. Anticipate the
1127                  * CLEAR_FEATURE command since a STALL has occurred and reset
1128                  * the data toggle now.
1129                  */
1130                 chan->qh->data_toggle = 0;
1131         }
1132
1133 handle_stall_halt:
1134         dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_STALL);
1135
1136 handle_stall_done:
1137         disable_hc_int(hsotg, chnum, HCINTMSK_STALL);
1138 }
1139
1140 /*
1141  * Updates the state of the URB when a transfer has been stopped due to an
1142  * abnormal condition before the transfer completes. Modifies the
1143  * actual_length field of the URB to reflect the number of bytes that have
1144  * actually been transferred via the host channel.
1145  */
1146 static void dwc2_update_urb_state_abn(struct dwc2_hsotg *hsotg,
1147                                       struct dwc2_host_chan *chan, int chnum,
1148                                       struct dwc2_hcd_urb *urb,
1149                                       struct dwc2_qtd *qtd,
1150                                       enum dwc2_halt_status halt_status)
1151 {
1152         u32 xfer_length = dwc2_get_actual_xfer_length(hsotg, chan, chnum,
1153                                                       qtd, halt_status, NULL);
1154         u32 hctsiz;
1155
1156         if (urb->actual_length + xfer_length > urb->length) {
1157                 dev_warn(hsotg->dev, "%s(): trimming xfer length\n", __func__);
1158                 xfer_length = urb->length - urb->actual_length;
1159         }
1160
1161         /* Non DWORD-aligned buffer case handling */
1162         if (chan->align_buf && xfer_length && chan->ep_is_in) {
1163                 dev_vdbg(hsotg->dev, "%s(): non-aligned buffer\n", __func__);
1164                 dma_sync_single_for_cpu(hsotg->dev, urb->dma, urb->length,
1165                                         DMA_FROM_DEVICE);
1166                 memcpy(urb->buf + urb->actual_length, chan->qh->dw_align_buf,
1167                        xfer_length);
1168                 dma_sync_single_for_device(hsotg->dev, urb->dma, urb->length,
1169                                            DMA_FROM_DEVICE);
1170         }
1171
1172         urb->actual_length += xfer_length;
1173
1174         hctsiz = readl(hsotg->regs + HCTSIZ(chnum));
1175         dev_vdbg(hsotg->dev, "DWC_otg: %s: %s, channel %d\n",
1176                  __func__, (chan->ep_is_in ? "IN" : "OUT"), chnum);
1177         dev_vdbg(hsotg->dev, "  chan->start_pkt_count %d\n",
1178                  chan->start_pkt_count);
1179         dev_vdbg(hsotg->dev, "  hctsiz.pktcnt %d\n",
1180                  (hctsiz & TSIZ_PKTCNT_MASK) >> TSIZ_PKTCNT_SHIFT);
1181         dev_vdbg(hsotg->dev, "  chan->max_packet %d\n", chan->max_packet);
1182         dev_vdbg(hsotg->dev, "  bytes_transferred %d\n",
1183                  xfer_length);
1184         dev_vdbg(hsotg->dev, "  urb->actual_length %d\n",
1185                  urb->actual_length);
1186         dev_vdbg(hsotg->dev, "  urb->transfer_buffer_length %d\n",
1187                  urb->length);
1188 }
1189
1190 /*
1191  * Handles a host channel NAK interrupt. This handler may be called in either
1192  * DMA mode or Slave mode.
1193  */
1194 static void dwc2_hc_nak_intr(struct dwc2_hsotg *hsotg,
1195                              struct dwc2_host_chan *chan, int chnum,
1196                              struct dwc2_qtd *qtd)
1197 {
1198         if (dbg_hc(chan))
1199                 dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: NAK Received--\n",
1200                          chnum);
1201
1202         /*
1203          * Handle NAK for IN/OUT SSPLIT/CSPLIT transfers, bulk, control, and
1204          * interrupt. Re-start the SSPLIT transfer.
1205          */
1206         if (chan->do_split) {
1207                 if (chan->complete_split)
1208                         qtd->error_count = 0;
1209                 qtd->complete_split = 0;
1210                 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NAK);
1211                 goto handle_nak_done;
1212         }
1213
1214         switch (dwc2_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
1215         case USB_ENDPOINT_XFER_CONTROL:
1216         case USB_ENDPOINT_XFER_BULK:
1217                 if (hsotg->core_params->dma_enable > 0 && chan->ep_is_in) {
1218                         /*
1219                          * NAK interrupts are enabled on bulk/control IN
1220                          * transfers in DMA mode for the sole purpose of
1221                          * resetting the error count after a transaction error
1222                          * occurs. The core will continue transferring data.
1223                          */
1224                         qtd->error_count = 0;
1225                         break;
1226                 }
1227
1228                 /*
1229                  * NAK interrupts normally occur during OUT transfers in DMA
1230                  * or Slave mode. For IN transfers, more requests will be
1231                  * queued as request queue space is available.
1232                  */
1233                 qtd->error_count = 0;
1234
1235                 if (!chan->qh->ping_state) {
1236                         dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb,
1237                                                   qtd, DWC2_HC_XFER_NAK);
1238                         dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1239
1240                         if (chan->speed == USB_SPEED_HIGH)
1241                                 chan->qh->ping_state = 1;
1242                 }
1243
1244                 /*
1245                  * Halt the channel so the transfer can be re-started from
1246                  * the appropriate point or the PING protocol will
1247                  * start/continue
1248                  */
1249                 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NAK);
1250                 break;
1251         case USB_ENDPOINT_XFER_INT:
1252                 qtd->error_count = 0;
1253                 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NAK);
1254                 break;
1255         case USB_ENDPOINT_XFER_ISOC:
1256                 /* Should never get called for isochronous transfers */
1257                 dev_err(hsotg->dev, "NACK interrupt for ISOC transfer\n");
1258                 break;
1259         }
1260
1261 handle_nak_done:
1262         disable_hc_int(hsotg, chnum, HCINTMSK_NAK);
1263 }
1264
1265 /*
1266  * Handles a host channel ACK interrupt. This interrupt is enabled when
1267  * performing the PING protocol in Slave mode, when errors occur during
1268  * either Slave mode or DMA mode, and during Start Split transactions.
1269  */
1270 static void dwc2_hc_ack_intr(struct dwc2_hsotg *hsotg,
1271                              struct dwc2_host_chan *chan, int chnum,
1272                              struct dwc2_qtd *qtd)
1273 {
1274         struct dwc2_hcd_iso_packet_desc *frame_desc;
1275
1276         if (dbg_hc(chan))
1277                 dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: ACK Received--\n",
1278                          chnum);
1279
1280         if (chan->do_split) {
1281                 /* Handle ACK on SSPLIT. ACK should not occur in CSPLIT. */
1282                 if (!chan->ep_is_in &&
1283                     chan->data_pid_start != DWC2_HC_PID_SETUP)
1284                         qtd->ssplit_out_xfer_count = chan->xfer_len;
1285
1286                 if (chan->ep_type != USB_ENDPOINT_XFER_ISOC || chan->ep_is_in) {
1287                         qtd->complete_split = 1;
1288                         dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_ACK);
1289                 } else {
1290                         /* ISOC OUT */
1291                         switch (chan->xact_pos) {
1292                         case DWC2_HCSPLT_XACTPOS_ALL:
1293                                 break;
1294                         case DWC2_HCSPLT_XACTPOS_END:
1295                                 qtd->isoc_split_pos = DWC2_HCSPLT_XACTPOS_ALL;
1296                                 qtd->isoc_split_offset = 0;
1297                                 break;
1298                         case DWC2_HCSPLT_XACTPOS_BEGIN:
1299                         case DWC2_HCSPLT_XACTPOS_MID:
1300                                 /*
1301                                  * For BEGIN or MID, calculate the length for
1302                                  * the next microframe to determine the correct
1303                                  * SSPLIT token, either MID or END
1304                                  */
1305                                 frame_desc = &qtd->urb->iso_descs[
1306                                                 qtd->isoc_frame_index];
1307                                 qtd->isoc_split_offset += 188;
1308
1309                                 if (frame_desc->length - qtd->isoc_split_offset
1310                                                         <= 188)
1311                                         qtd->isoc_split_pos =
1312                                                         DWC2_HCSPLT_XACTPOS_END;
1313                                 else
1314                                         qtd->isoc_split_pos =
1315                                                         DWC2_HCSPLT_XACTPOS_MID;
1316                                 break;
1317                         }
1318                 }
1319         } else {
1320                 qtd->error_count = 0;
1321
1322                 if (chan->qh->ping_state) {
1323                         chan->qh->ping_state = 0;
1324                         /*
1325                          * Halt the channel so the transfer can be re-started
1326                          * from the appropriate point. This only happens in
1327                          * Slave mode. In DMA mode, the ping_state is cleared
1328                          * when the transfer is started because the core
1329                          * automatically executes the PING, then the transfer.
1330                          */
1331                         dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_ACK);
1332                 }
1333         }
1334
1335         /*
1336          * If the ACK occurred when _not_ in the PING state, let the channel
1337          * continue transferring data after clearing the error count
1338          */
1339         disable_hc_int(hsotg, chnum, HCINTMSK_ACK);
1340 }
1341
1342 /*
1343  * Handles a host channel NYET interrupt. This interrupt should only occur on
1344  * Bulk and Control OUT endpoints and for complete split transactions. If a
1345  * NYET occurs at the same time as a Transfer Complete interrupt, it is
1346  * handled in the xfercomp interrupt handler, not here. This handler may be
1347  * called in either DMA mode or Slave mode.
1348  */
1349 static void dwc2_hc_nyet_intr(struct dwc2_hsotg *hsotg,
1350                               struct dwc2_host_chan *chan, int chnum,
1351                               struct dwc2_qtd *qtd)
1352 {
1353         if (dbg_hc(chan))
1354                 dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: NYET Received--\n",
1355                          chnum);
1356
1357         /*
1358          * NYET on CSPLIT
1359          * re-do the CSPLIT immediately on non-periodic
1360          */
1361         if (chan->do_split && chan->complete_split) {
1362                 if (chan->ep_is_in && chan->ep_type == USB_ENDPOINT_XFER_ISOC &&
1363                     hsotg->core_params->dma_enable > 0) {
1364                         qtd->complete_split = 0;
1365                         qtd->isoc_split_offset = 0;
1366                         qtd->isoc_frame_index++;
1367                         if (qtd->urb &&
1368                             qtd->isoc_frame_index == qtd->urb->packet_count) {
1369                                 dwc2_host_complete(hsotg, qtd, 0);
1370                                 dwc2_release_channel(hsotg, chan, qtd,
1371                                                      DWC2_HC_XFER_URB_COMPLETE);
1372                         } else {
1373                                 dwc2_release_channel(hsotg, chan, qtd,
1374                                                 DWC2_HC_XFER_NO_HALT_STATUS);
1375                         }
1376                         goto handle_nyet_done;
1377                 }
1378
1379                 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1380                     chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1381                         int frnum = dwc2_hcd_get_frame_number(hsotg);
1382
1383                         if (dwc2_full_frame_num(frnum) !=
1384                             dwc2_full_frame_num(chan->qh->sched_frame)) {
1385                                 /*
1386                                  * No longer in the same full speed frame.
1387                                  * Treat this as a transaction error.
1388                                  */
1389 #if 0
1390                                 /*
1391                                  * Todo: Fix system performance so this can
1392                                  * be treated as an error. Right now complete
1393                                  * splits cannot be scheduled precisely enough
1394                                  * due to other system activity, so this error
1395                                  * occurs regularly in Slave mode.
1396                                  */
1397                                 qtd->error_count++;
1398 #endif
1399                                 qtd->complete_split = 0;
1400                                 dwc2_halt_channel(hsotg, chan, qtd,
1401                                                   DWC2_HC_XFER_XACT_ERR);
1402                                 /* Todo: add support for isoc release */
1403                                 goto handle_nyet_done;
1404                         }
1405                 }
1406
1407                 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NYET);
1408                 goto handle_nyet_done;
1409         }
1410
1411         chan->qh->ping_state = 1;
1412         qtd->error_count = 0;
1413
1414         dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb, qtd,
1415                                   DWC2_HC_XFER_NYET);
1416         dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1417
1418         /*
1419          * Halt the channel and re-start the transfer so the PING protocol
1420          * will start
1421          */
1422         dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NYET);
1423
1424 handle_nyet_done:
1425         disable_hc_int(hsotg, chnum, HCINTMSK_NYET);
1426 }
1427
1428 /*
1429  * Handles a host channel babble interrupt. This handler may be called in
1430  * either DMA mode or Slave mode.
1431  */
1432 static void dwc2_hc_babble_intr(struct dwc2_hsotg *hsotg,
1433                                 struct dwc2_host_chan *chan, int chnum,
1434                                 struct dwc2_qtd *qtd)
1435 {
1436         dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: Babble Error--\n",
1437                 chnum);
1438
1439         dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1440
1441         if (hsotg->core_params->dma_desc_enable > 0) {
1442                 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1443                                             DWC2_HC_XFER_BABBLE_ERR);
1444                 goto disable_int;
1445         }
1446
1447         if (chan->ep_type != USB_ENDPOINT_XFER_ISOC) {
1448                 dwc2_host_complete(hsotg, qtd, -EOVERFLOW);
1449                 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_BABBLE_ERR);
1450         } else {
1451                 enum dwc2_halt_status halt_status;
1452
1453                 halt_status = dwc2_update_isoc_urb_state(hsotg, chan, chnum,
1454                                                 qtd, DWC2_HC_XFER_BABBLE_ERR);
1455                 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
1456         }
1457
1458 disable_int:
1459         disable_hc_int(hsotg, chnum, HCINTMSK_BBLERR);
1460 }
1461
1462 /*
1463  * Handles a host channel AHB error interrupt. This handler is only called in
1464  * DMA mode.
1465  */
1466 static void dwc2_hc_ahberr_intr(struct dwc2_hsotg *hsotg,
1467                                 struct dwc2_host_chan *chan, int chnum,
1468                                 struct dwc2_qtd *qtd)
1469 {
1470         struct dwc2_hcd_urb *urb = qtd->urb;
1471         char *pipetype, *speed;
1472         u32 hcchar;
1473         u32 hcsplt;
1474         u32 hctsiz;
1475         u32 hc_dma;
1476
1477         dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: AHB Error--\n",
1478                 chnum);
1479
1480         if (!urb)
1481                 goto handle_ahberr_halt;
1482
1483         dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1484
1485         hcchar = readl(hsotg->regs + HCCHAR(chnum));
1486         hcsplt = readl(hsotg->regs + HCSPLT(chnum));
1487         hctsiz = readl(hsotg->regs + HCTSIZ(chnum));
1488         hc_dma = readl(hsotg->regs + HCDMA(chnum));
1489
1490         dev_err(hsotg->dev, "AHB ERROR, Channel %d\n", chnum);
1491         dev_err(hsotg->dev, "  hcchar 0x%08x, hcsplt 0x%08x\n", hcchar, hcsplt);
1492         dev_err(hsotg->dev, "  hctsiz 0x%08x, hc_dma 0x%08x\n", hctsiz, hc_dma);
1493         dev_err(hsotg->dev, "  Device address: %d\n",
1494                 dwc2_hcd_get_dev_addr(&urb->pipe_info));
1495         dev_err(hsotg->dev, "  Endpoint: %d, %s\n",
1496                 dwc2_hcd_get_ep_num(&urb->pipe_info),
1497                 dwc2_hcd_is_pipe_in(&urb->pipe_info) ? "IN" : "OUT");
1498
1499         switch (dwc2_hcd_get_pipe_type(&urb->pipe_info)) {
1500         case USB_ENDPOINT_XFER_CONTROL:
1501                 pipetype = "CONTROL";
1502                 break;
1503         case USB_ENDPOINT_XFER_BULK:
1504                 pipetype = "BULK";
1505                 break;
1506         case USB_ENDPOINT_XFER_INT:
1507                 pipetype = "INTERRUPT";
1508                 break;
1509         case USB_ENDPOINT_XFER_ISOC:
1510                 pipetype = "ISOCHRONOUS";
1511                 break;
1512         default:
1513                 pipetype = "UNKNOWN";
1514                 break;
1515         }
1516
1517         dev_err(hsotg->dev, "  Endpoint type: %s\n", pipetype);
1518
1519         switch (chan->speed) {
1520         case USB_SPEED_HIGH:
1521                 speed = "HIGH";
1522                 break;
1523         case USB_SPEED_FULL:
1524                 speed = "FULL";
1525                 break;
1526         case USB_SPEED_LOW:
1527                 speed = "LOW";
1528                 break;
1529         default:
1530                 speed = "UNKNOWN";
1531                 break;
1532         }
1533
1534         dev_err(hsotg->dev, "  Speed: %s\n", speed);
1535
1536         dev_err(hsotg->dev, "  Max packet size: %d\n",
1537                 dwc2_hcd_get_mps(&urb->pipe_info));
1538         dev_err(hsotg->dev, "  Data buffer length: %d\n", urb->length);
1539         dev_err(hsotg->dev, "  Transfer buffer: %p, Transfer DMA: %08lx\n",
1540                 urb->buf, (unsigned long)urb->dma);
1541         dev_err(hsotg->dev, "  Setup buffer: %p, Setup DMA: %08lx\n",
1542                 urb->setup_packet, (unsigned long)urb->setup_dma);
1543         dev_err(hsotg->dev, "  Interval: %d\n", urb->interval);
1544
1545         /* Core halts the channel for Descriptor DMA mode */
1546         if (hsotg->core_params->dma_desc_enable > 0) {
1547                 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1548                                             DWC2_HC_XFER_AHB_ERR);
1549                 goto handle_ahberr_done;
1550         }
1551
1552         dwc2_host_complete(hsotg, qtd, -EIO);
1553
1554 handle_ahberr_halt:
1555         /*
1556          * Force a channel halt. Don't call dwc2_halt_channel because that won't
1557          * write to the HCCHARn register in DMA mode to force the halt.
1558          */
1559         dwc2_hc_halt(hsotg, chan, DWC2_HC_XFER_AHB_ERR);
1560
1561 handle_ahberr_done:
1562         disable_hc_int(hsotg, chnum, HCINTMSK_AHBERR);
1563 }
1564
1565 /*
1566  * Handles a host channel transaction error interrupt. This handler may be
1567  * called in either DMA mode or Slave mode.
1568  */
1569 static void dwc2_hc_xacterr_intr(struct dwc2_hsotg *hsotg,
1570                                  struct dwc2_host_chan *chan, int chnum,
1571                                  struct dwc2_qtd *qtd)
1572 {
1573         dev_dbg(hsotg->dev,
1574                 "--Host Channel %d Interrupt: Transaction Error--\n", chnum);
1575
1576         dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1577
1578         if (hsotg->core_params->dma_desc_enable > 0) {
1579                 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1580                                             DWC2_HC_XFER_XACT_ERR);
1581                 goto handle_xacterr_done;
1582         }
1583
1584         switch (dwc2_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
1585         case USB_ENDPOINT_XFER_CONTROL:
1586         case USB_ENDPOINT_XFER_BULK:
1587                 qtd->error_count++;
1588                 if (!chan->qh->ping_state) {
1589
1590                         dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb,
1591                                                   qtd, DWC2_HC_XFER_XACT_ERR);
1592                         dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1593                         if (!chan->ep_is_in && chan->speed == USB_SPEED_HIGH)
1594                                 chan->qh->ping_state = 1;
1595                 }
1596
1597                 /*
1598                  * Halt the channel so the transfer can be re-started from
1599                  * the appropriate point or the PING protocol will start
1600                  */
1601                 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_XACT_ERR);
1602                 break;
1603         case USB_ENDPOINT_XFER_INT:
1604                 qtd->error_count++;
1605                 if (chan->do_split && chan->complete_split)
1606                         qtd->complete_split = 0;
1607                 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_XACT_ERR);
1608                 break;
1609         case USB_ENDPOINT_XFER_ISOC:
1610                 {
1611                         enum dwc2_halt_status halt_status;
1612
1613                         halt_status = dwc2_update_isoc_urb_state(hsotg, chan,
1614                                         chnum, qtd, DWC2_HC_XFER_XACT_ERR);
1615                         dwc2_halt_channel(hsotg, chan, qtd, halt_status);
1616                 }
1617                 break;
1618         }
1619
1620 handle_xacterr_done:
1621         disable_hc_int(hsotg, chnum, HCINTMSK_XACTERR);
1622 }
1623
1624 /*
1625  * Handles a host channel frame overrun interrupt. This handler may be called
1626  * in either DMA mode or Slave mode.
1627  */
1628 static void dwc2_hc_frmovrun_intr(struct dwc2_hsotg *hsotg,
1629                                   struct dwc2_host_chan *chan, int chnum,
1630                                   struct dwc2_qtd *qtd)
1631 {
1632         enum dwc2_halt_status halt_status;
1633
1634         if (dbg_hc(chan))
1635                 dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: Frame Overrun--\n",
1636                         chnum);
1637
1638         dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1639
1640         switch (dwc2_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
1641         case USB_ENDPOINT_XFER_CONTROL:
1642         case USB_ENDPOINT_XFER_BULK:
1643                 break;
1644         case USB_ENDPOINT_XFER_INT:
1645                 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_FRAME_OVERRUN);
1646                 break;
1647         case USB_ENDPOINT_XFER_ISOC:
1648                 halt_status = dwc2_update_isoc_urb_state(hsotg, chan, chnum,
1649                                         qtd, DWC2_HC_XFER_FRAME_OVERRUN);
1650                 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
1651                 break;
1652         }
1653
1654         disable_hc_int(hsotg, chnum, HCINTMSK_FRMOVRUN);
1655 }
1656
1657 /*
1658  * Handles a host channel data toggle error interrupt. This handler may be
1659  * called in either DMA mode or Slave mode.
1660  */
1661 static void dwc2_hc_datatglerr_intr(struct dwc2_hsotg *hsotg,
1662                                     struct dwc2_host_chan *chan, int chnum,
1663                                     struct dwc2_qtd *qtd)
1664 {
1665         dev_dbg(hsotg->dev,
1666                 "--Host Channel %d Interrupt: Data Toggle Error--\n", chnum);
1667
1668         if (chan->ep_is_in)
1669                 qtd->error_count = 0;
1670         else
1671                 dev_err(hsotg->dev,
1672                         "Data Toggle Error on OUT transfer, channel %d\n",
1673                         chnum);
1674
1675         dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1676         disable_hc_int(hsotg, chnum, HCINTMSK_DATATGLERR);
1677 }
1678
1679 /*
1680  * For debug only. It checks that a valid halt status is set and that
1681  * HCCHARn.chdis is clear. If there's a problem, corrective action is
1682  * taken and a warning is issued.
1683  *
1684  * Return: true if halt status is ok, false otherwise
1685  */
1686 static bool dwc2_halt_status_ok(struct dwc2_hsotg *hsotg,
1687                                 struct dwc2_host_chan *chan, int chnum,
1688                                 struct dwc2_qtd *qtd)
1689 {
1690 #ifdef DEBUG
1691         u32 hcchar;
1692         u32 hctsiz;
1693         u32 hcintmsk;
1694         u32 hcsplt;
1695
1696         if (chan->halt_status == DWC2_HC_XFER_NO_HALT_STATUS) {
1697                 /*
1698                  * This code is here only as a check. This condition should
1699                  * never happen. Ignore the halt if it does occur.
1700                  */
1701                 hcchar = readl(hsotg->regs + HCCHAR(chnum));
1702                 hctsiz = readl(hsotg->regs + HCTSIZ(chnum));
1703                 hcintmsk = readl(hsotg->regs + HCINTMSK(chnum));
1704                 hcsplt = readl(hsotg->regs + HCSPLT(chnum));
1705                 dev_dbg(hsotg->dev,
1706                         "%s: chan->halt_status DWC2_HC_XFER_NO_HALT_STATUS,\n",
1707                          __func__);
1708                 dev_dbg(hsotg->dev,
1709                         "channel %d, hcchar 0x%08x, hctsiz 0x%08x,\n",
1710                         chnum, hcchar, hctsiz);
1711                 dev_dbg(hsotg->dev,
1712                         "hcint 0x%08x, hcintmsk 0x%08x, hcsplt 0x%08x,\n",
1713                         chan->hcint, hcintmsk, hcsplt);
1714                 if (qtd)
1715                         dev_dbg(hsotg->dev, "qtd->complete_split %d\n",
1716                                 qtd->complete_split);
1717                 dev_warn(hsotg->dev,
1718                          "%s: no halt status, channel %d, ignoring interrupt\n",
1719                          __func__, chnum);
1720                 return false;
1721         }
1722
1723         /*
1724          * This code is here only as a check. hcchar.chdis should never be set
1725          * when the halt interrupt occurs. Halt the channel again if it does
1726          * occur.
1727          */
1728         hcchar = readl(hsotg->regs + HCCHAR(chnum));
1729         if (hcchar & HCCHAR_CHDIS) {
1730                 dev_warn(hsotg->dev,
1731                          "%s: hcchar.chdis set unexpectedly, hcchar 0x%08x, trying to halt again\n",
1732                          __func__, hcchar);
1733                 chan->halt_pending = 0;
1734                 dwc2_halt_channel(hsotg, chan, qtd, chan->halt_status);
1735                 return false;
1736         }
1737 #endif
1738
1739         return true;
1740 }
1741
1742 /*
1743  * Handles a host Channel Halted interrupt in DMA mode. This handler
1744  * determines the reason the channel halted and proceeds accordingly.
1745  */
1746 static void dwc2_hc_chhltd_intr_dma(struct dwc2_hsotg *hsotg,
1747                                     struct dwc2_host_chan *chan, int chnum,
1748                                     struct dwc2_qtd *qtd)
1749 {
1750         u32 hcintmsk;
1751         int out_nak_enh = 0;
1752
1753         if (dbg_hc(chan))
1754                 dev_vdbg(hsotg->dev,
1755                          "--Host Channel %d Interrupt: DMA Channel Halted--\n",
1756                          chnum);
1757
1758         /*
1759          * For core with OUT NAK enhancement, the flow for high-speed
1760          * CONTROL/BULK OUT is handled a little differently
1761          */
1762         if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_71a) {
1763                 if (chan->speed == USB_SPEED_HIGH && !chan->ep_is_in &&
1764                     (chan->ep_type == USB_ENDPOINT_XFER_CONTROL ||
1765                      chan->ep_type == USB_ENDPOINT_XFER_BULK)) {
1766                         out_nak_enh = 1;
1767                 }
1768         }
1769
1770         if (chan->halt_status == DWC2_HC_XFER_URB_DEQUEUE ||
1771             (chan->halt_status == DWC2_HC_XFER_AHB_ERR &&
1772              hsotg->core_params->dma_desc_enable <= 0)) {
1773                 if (hsotg->core_params->dma_desc_enable > 0)
1774                         dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1775                                                     chan->halt_status);
1776                 else
1777                         /*
1778                          * Just release the channel. A dequeue can happen on a
1779                          * transfer timeout. In the case of an AHB Error, the
1780                          * channel was forced to halt because there's no way to
1781                          * gracefully recover.
1782                          */
1783                         dwc2_release_channel(hsotg, chan, qtd,
1784                                              chan->halt_status);
1785                 return;
1786         }
1787
1788         hcintmsk = readl(hsotg->regs + HCINTMSK(chnum));
1789
1790         if (chan->hcint & HCINTMSK_XFERCOMPL) {
1791                 /*
1792                  * Todo: This is here because of a possible hardware bug. Spec
1793                  * says that on SPLIT-ISOC OUT transfers in DMA mode that a HALT
1794                  * interrupt w/ACK bit set should occur, but I only see the
1795                  * XFERCOMP bit, even with it masked out. This is a workaround
1796                  * for that behavior. Should fix this when hardware is fixed.
1797                  */
1798                 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC && !chan->ep_is_in)
1799                         dwc2_hc_ack_intr(hsotg, chan, chnum, qtd);
1800                 dwc2_hc_xfercomp_intr(hsotg, chan, chnum, qtd);
1801         } else if (chan->hcint & HCINTMSK_STALL) {
1802                 dwc2_hc_stall_intr(hsotg, chan, chnum, qtd);
1803         } else if ((chan->hcint & HCINTMSK_XACTERR) &&
1804                    hsotg->core_params->dma_desc_enable <= 0) {
1805                 if (out_nak_enh) {
1806                         if (chan->hcint &
1807                             (HCINTMSK_NYET | HCINTMSK_NAK | HCINTMSK_ACK)) {
1808                                 dev_vdbg(hsotg->dev,
1809                                          "XactErr with NYET/NAK/ACK\n");
1810                                 qtd->error_count = 0;
1811                         } else {
1812                                 dev_vdbg(hsotg->dev,
1813                                          "XactErr without NYET/NAK/ACK\n");
1814                         }
1815                 }
1816
1817                 /*
1818                  * Must handle xacterr before nak or ack. Could get a xacterr
1819                  * at the same time as either of these on a BULK/CONTROL OUT
1820                  * that started with a PING. The xacterr takes precedence.
1821                  */
1822                 dwc2_hc_xacterr_intr(hsotg, chan, chnum, qtd);
1823         } else if ((chan->hcint & HCINTMSK_XCS_XACT) &&
1824                    hsotg->core_params->dma_desc_enable > 0) {
1825                 dwc2_hc_xacterr_intr(hsotg, chan, chnum, qtd);
1826         } else if ((chan->hcint & HCINTMSK_AHBERR) &&
1827                    hsotg->core_params->dma_desc_enable > 0) {
1828                 dwc2_hc_ahberr_intr(hsotg, chan, chnum, qtd);
1829         } else if (chan->hcint & HCINTMSK_BBLERR) {
1830                 dwc2_hc_babble_intr(hsotg, chan, chnum, qtd);
1831         } else if (chan->hcint & HCINTMSK_FRMOVRUN) {
1832                 dwc2_hc_frmovrun_intr(hsotg, chan, chnum, qtd);
1833         } else if (!out_nak_enh) {
1834                 if (chan->hcint & HCINTMSK_NYET) {
1835                         /*
1836                          * Must handle nyet before nak or ack. Could get a nyet
1837                          * at the same time as either of those on a BULK/CONTROL
1838                          * OUT that started with a PING. The nyet takes
1839                          * precedence.
1840                          */
1841                         dwc2_hc_nyet_intr(hsotg, chan, chnum, qtd);
1842                 } else if ((chan->hcint & HCINTMSK_NAK) &&
1843                            !(hcintmsk & HCINTMSK_NAK)) {
1844                         /*
1845                          * If nak is not masked, it's because a non-split IN
1846                          * transfer is in an error state. In that case, the nak
1847                          * is handled by the nak interrupt handler, not here.
1848                          * Handle nak here for BULK/CONTROL OUT transfers, which
1849                          * halt on a NAK to allow rewinding the buffer pointer.
1850                          */
1851                         dwc2_hc_nak_intr(hsotg, chan, chnum, qtd);
1852                 } else if ((chan->hcint & HCINTMSK_ACK) &&
1853                            !(hcintmsk & HCINTMSK_ACK)) {
1854                         /*
1855                          * If ack is not masked, it's because a non-split IN
1856                          * transfer is in an error state. In that case, the ack
1857                          * is handled by the ack interrupt handler, not here.
1858                          * Handle ack here for split transfers. Start splits
1859                          * halt on ACK.
1860                          */
1861                         dwc2_hc_ack_intr(hsotg, chan, chnum, qtd);
1862                 } else {
1863                         if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1864                             chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1865                                 /*
1866                                  * A periodic transfer halted with no other
1867                                  * channel interrupts set. Assume it was halted
1868                                  * by the core because it could not be completed
1869                                  * in its scheduled (micro)frame.
1870                                  */
1871                                 dev_dbg(hsotg->dev,
1872                                         "%s: Halt channel %d (assume incomplete periodic transfer)\n",
1873                                         __func__, chnum);
1874                                 dwc2_halt_channel(hsotg, chan, qtd,
1875                                         DWC2_HC_XFER_PERIODIC_INCOMPLETE);
1876                         } else {
1877                                 dev_err(hsotg->dev,
1878                                         "%s: Channel %d - ChHltd set, but reason is unknown\n",
1879                                         __func__, chnum);
1880                                 dev_err(hsotg->dev,
1881                                         "hcint 0x%08x, intsts 0x%08x\n",
1882                                         chan->hcint,
1883                                         readl(hsotg->regs + GINTSTS));
1884                         }
1885                 }
1886         } else {
1887                 dev_info(hsotg->dev,
1888                          "NYET/NAK/ACK/other in non-error case, 0x%08x\n",
1889                          chan->hcint);
1890         }
1891 }
1892
1893 /*
1894  * Handles a host channel Channel Halted interrupt
1895  *
1896  * In slave mode, this handler is called only when the driver specifically
1897  * requests a halt. This occurs during handling other host channel interrupts
1898  * (e.g. nak, xacterr, stall, nyet, etc.).
1899  *
1900  * In DMA mode, this is the interrupt that occurs when the core has finished
1901  * processing a transfer on a channel. Other host channel interrupts (except
1902  * ahberr) are disabled in DMA mode.
1903  */
1904 static void dwc2_hc_chhltd_intr(struct dwc2_hsotg *hsotg,
1905                                 struct dwc2_host_chan *chan, int chnum,
1906                                 struct dwc2_qtd *qtd)
1907 {
1908         if (dbg_hc(chan))
1909                 dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: Channel Halted--\n",
1910                          chnum);
1911
1912         if (hsotg->core_params->dma_enable > 0) {
1913                 dwc2_hc_chhltd_intr_dma(hsotg, chan, chnum, qtd);
1914         } else {
1915                 if (!dwc2_halt_status_ok(hsotg, chan, chnum, qtd))
1916                         return;
1917                 dwc2_release_channel(hsotg, chan, qtd, chan->halt_status);
1918         }
1919 }
1920
1921 /* Handles interrupt for a specific Host Channel */
1922 static void dwc2_hc_n_intr(struct dwc2_hsotg *hsotg, int chnum)
1923 {
1924         struct dwc2_qtd *qtd;
1925         struct dwc2_host_chan *chan;
1926         u32 hcint, hcintmsk;
1927
1928         chan = hsotg->hc_ptr_array[chnum];
1929
1930         if (dbg_hc(chan))
1931                 dev_vdbg(hsotg->dev, "--Host Channel Interrupt--, Channel %d\n",
1932                          chnum);
1933
1934         hcint = readl(hsotg->regs + HCINT(chnum));
1935         hcintmsk = readl(hsotg->regs + HCINTMSK(chnum));
1936         if (dbg_hc(chan))
1937                 dev_vdbg(hsotg->dev,
1938                          "  hcint 0x%08x, hcintmsk 0x%08x, hcint&hcintmsk 0x%08x\n",
1939                          hcint, hcintmsk, hcint & hcintmsk);
1940
1941         if (!chan) {
1942                 dev_err(hsotg->dev, "## hc_ptr_array for channel is NULL ##\n");
1943                 writel(hcint, hsotg->regs + HCINT(chnum));
1944                 return;
1945         }
1946
1947         writel(hcint, hsotg->regs + HCINT(chnum));
1948         chan->hcint = hcint;
1949         hcint &= hcintmsk;
1950
1951         /*
1952          * If the channel was halted due to a dequeue, the qtd list might
1953          * be empty or at least the first entry will not be the active qtd.
1954          * In this case, take a shortcut and just release the channel.
1955          */
1956         if (chan->halt_status == DWC2_HC_XFER_URB_DEQUEUE) {
1957                 /*
1958                  * If the channel was halted, this should be the only
1959                  * interrupt unmasked
1960                  */
1961                 WARN_ON(hcint != HCINTMSK_CHHLTD);
1962                 if (hsotg->core_params->dma_desc_enable > 0)
1963                         dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1964                                                     chan->halt_status);
1965                 else
1966                         dwc2_release_channel(hsotg, chan, NULL,
1967                                              chan->halt_status);
1968                 return;
1969         }
1970
1971         if (list_empty(&chan->qh->qtd_list)) {
1972                 /*
1973                  * TODO: Will this ever happen with the
1974                  * DWC2_HC_XFER_URB_DEQUEUE handling above?
1975                  */
1976                 dev_dbg(hsotg->dev, "## no QTD queued for channel %d ##\n",
1977                         chnum);
1978                 dev_dbg(hsotg->dev,
1979                         "  hcint 0x%08x, hcintmsk 0x%08x, hcint&hcintmsk 0x%08x\n",
1980                         chan->hcint, hcintmsk, hcint);
1981                 chan->halt_status = DWC2_HC_XFER_NO_HALT_STATUS;
1982                 disable_hc_int(hsotg, chnum, HCINTMSK_CHHLTD);
1983                 chan->hcint = 0;
1984                 return;
1985         }
1986
1987         qtd = list_first_entry(&chan->qh->qtd_list, struct dwc2_qtd,
1988                                qtd_list_entry);
1989
1990         if (hsotg->core_params->dma_enable <= 0) {
1991                 if ((hcint & HCINTMSK_CHHLTD) && hcint != HCINTMSK_CHHLTD)
1992                         hcint &= ~HCINTMSK_CHHLTD;
1993         }
1994
1995         if (hcint & HCINTMSK_XFERCOMPL) {
1996                 dwc2_hc_xfercomp_intr(hsotg, chan, chnum, qtd);
1997                 /*
1998                  * If NYET occurred at same time as Xfer Complete, the NYET is
1999                  * handled by the Xfer Complete interrupt handler. Don't want
2000                  * to call the NYET interrupt handler in this case.
2001                  */
2002                 hcint &= ~HCINTMSK_NYET;
2003         }
2004         if (hcint & HCINTMSK_CHHLTD)
2005                 dwc2_hc_chhltd_intr(hsotg, chan, chnum, qtd);
2006         if (hcint & HCINTMSK_AHBERR)
2007                 dwc2_hc_ahberr_intr(hsotg, chan, chnum, qtd);
2008         if (hcint & HCINTMSK_STALL)
2009                 dwc2_hc_stall_intr(hsotg, chan, chnum, qtd);
2010         if (hcint & HCINTMSK_NAK)
2011                 dwc2_hc_nak_intr(hsotg, chan, chnum, qtd);
2012         if (hcint & HCINTMSK_ACK)
2013                 dwc2_hc_ack_intr(hsotg, chan, chnum, qtd);
2014         if (hcint & HCINTMSK_NYET)
2015                 dwc2_hc_nyet_intr(hsotg, chan, chnum, qtd);
2016         if (hcint & HCINTMSK_XACTERR)
2017                 dwc2_hc_xacterr_intr(hsotg, chan, chnum, qtd);
2018         if (hcint & HCINTMSK_BBLERR)
2019                 dwc2_hc_babble_intr(hsotg, chan, chnum, qtd);
2020         if (hcint & HCINTMSK_FRMOVRUN)
2021                 dwc2_hc_frmovrun_intr(hsotg, chan, chnum, qtd);
2022         if (hcint & HCINTMSK_DATATGLERR)
2023                 dwc2_hc_datatglerr_intr(hsotg, chan, chnum, qtd);
2024
2025         chan->hcint = 0;
2026 }
2027
2028 /*
2029  * This interrupt indicates that one or more host channels has a pending
2030  * interrupt. There are multiple conditions that can cause each host channel
2031  * interrupt. This function determines which conditions have occurred for each
2032  * host channel interrupt and handles them appropriately.
2033  */
2034 static void dwc2_hc_intr(struct dwc2_hsotg *hsotg)
2035 {
2036         u32 haint;
2037         int i;
2038
2039         haint = readl(hsotg->regs + HAINT);
2040         if (dbg_perio()) {
2041                 dev_vdbg(hsotg->dev, "%s()\n", __func__);
2042
2043                 dev_vdbg(hsotg->dev, "HAINT=%08x\n", haint);
2044         }
2045
2046         for (i = 0; i < hsotg->core_params->host_channels; i++) {
2047                 if (haint & (1 << i))
2048                         dwc2_hc_n_intr(hsotg, i);
2049         }
2050 }
2051
2052 /* This function handles interrupts for the HCD */
2053 irqreturn_t dwc2_handle_hcd_intr(struct dwc2_hsotg *hsotg)
2054 {
2055         u32 gintsts, dbg_gintsts;
2056         irqreturn_t retval = IRQ_NONE;
2057
2058         if (dwc2_check_core_status(hsotg) < 0) {
2059                 dev_warn(hsotg->dev, "Controller is disconnected\n");
2060                 return retval;
2061         }
2062
2063         spin_lock(&hsotg->lock);
2064
2065         /* Check if HOST Mode */
2066         if (dwc2_is_host_mode(hsotg)) {
2067                 gintsts = dwc2_read_core_intr(hsotg);
2068                 if (!gintsts) {
2069                         spin_unlock(&hsotg->lock);
2070                         return retval;
2071                 }
2072
2073                 retval = IRQ_HANDLED;
2074
2075                 dbg_gintsts = gintsts;
2076 #ifndef DEBUG_SOF
2077                 dbg_gintsts &= ~GINTSTS_SOF;
2078 #endif
2079                 if (!dbg_perio())
2080                         dbg_gintsts &= ~(GINTSTS_HCHINT | GINTSTS_RXFLVL |
2081                                          GINTSTS_PTXFEMP);
2082
2083                 /* Only print if there are any non-suppressed interrupts left */
2084                 if (dbg_gintsts)
2085                         dev_vdbg(hsotg->dev,
2086                                  "DWC OTG HCD Interrupt Detected gintsts&gintmsk=0x%08x\n",
2087                                  gintsts);
2088
2089                 if (gintsts & GINTSTS_SOF)
2090                         dwc2_sof_intr(hsotg);
2091                 if (gintsts & GINTSTS_RXFLVL)
2092                         dwc2_rx_fifo_level_intr(hsotg);
2093                 if (gintsts & GINTSTS_NPTXFEMP)
2094                         dwc2_np_tx_fifo_empty_intr(hsotg);
2095                 if (gintsts & GINTSTS_PRTINT)
2096                         dwc2_port_intr(hsotg);
2097                 if (gintsts & GINTSTS_HCHINT)
2098                         dwc2_hc_intr(hsotg);
2099                 if (gintsts & GINTSTS_PTXFEMP)
2100                         dwc2_perio_tx_fifo_empty_intr(hsotg);
2101
2102                 if (dbg_gintsts) {
2103                         dev_vdbg(hsotg->dev,
2104                                  "DWC OTG HCD Finished Servicing Interrupts\n");
2105                         dev_vdbg(hsotg->dev,
2106                                  "DWC OTG HCD gintsts=0x%08x gintmsk=0x%08x\n",
2107                                  readl(hsotg->regs + GINTSTS),
2108                                  readl(hsotg->regs + GINTMSK));
2109                 }
2110         }
2111
2112         spin_unlock(&hsotg->lock);
2113
2114         return retval;
2115 }